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Alexander Duyckb3890e32014-09-20 19:46:05 -04001/* Intel Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19 */
20
21#ifndef _FM10K_H_
22#define _FM10K_H_
23
24#include <linux/types.h>
25#include <linux/etherdevice.h>
26#include <linux/rtnetlink.h>
27#include <linux/if_vlan.h>
28#include <linux/pci.h>
29
Alexander Duyck0e7b3642014-09-20 19:48:10 -040030#include "fm10k_pf.h"
31
32#define FM10K_MAX_JUMBO_FRAME_SIZE 15358 /* Maximum supported size 15K */
33
Alexander Duycke27ef592014-09-20 19:49:03 -040034#define MAX_QUEUES FM10K_MAX_QUEUES_PF
35
36#define FM10K_MIN_RXD 128
37#define FM10K_MAX_RXD 4096
38#define FM10K_DEFAULT_RXD 256
39
40#define FM10K_MIN_TXD 128
41#define FM10K_MAX_TXD 4096
42#define FM10K_DEFAULT_TXD 256
43#define FM10K_DEFAULT_TX_WORK 256
44
45#define FM10K_RXBUFFER_256 256
46#define FM10K_RXBUFFER_16384 16384
47#define FM10K_RX_HDR_LEN FM10K_RXBUFFER_256
48#if PAGE_SIZE <= FM10K_RXBUFFER_16384
49#define FM10K_RX_BUFSZ (PAGE_SIZE / 2)
50#else
51#define FM10K_RX_BUFSZ FM10K_RXBUFFER_16384
52#endif
53
54/* How many Rx Buffers do we bundle into one write to the hardware ? */
55#define FM10K_RX_BUFFER_WRITE 16 /* Must be power of 2 */
56
57enum fm10k_ring_state_t {
58 __FM10K_TX_DETECT_HANG,
59 __FM10K_HANG_CHECK_ARMED,
60};
61
62#define check_for_tx_hang(ring) \
63 test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
64#define set_check_for_tx_hang(ring) \
65 set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
66#define clear_check_for_tx_hang(ring) \
67 clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
68
69struct fm10k_tx_buffer {
70 struct fm10k_tx_desc *next_to_watch;
71 struct sk_buff *skb;
72 unsigned int bytecount;
73 u16 gso_segs;
74 u16 tx_flags;
75 DEFINE_DMA_UNMAP_ADDR(dma);
76 DEFINE_DMA_UNMAP_LEN(len);
77};
78
79struct fm10k_rx_buffer {
80 dma_addr_t dma;
81 struct page *page;
82 u32 page_offset;
83};
84
85struct fm10k_queue_stats {
86 u64 packets;
87 u64 bytes;
88};
89
90struct fm10k_tx_queue_stats {
91 u64 restart_queue;
92 u64 csum_err;
93 u64 tx_busy;
94 u64 tx_done_old;
95};
96
97struct fm10k_rx_queue_stats {
98 u64 alloc_failed;
99 u64 csum_err;
100 u64 errors;
101};
102
103struct fm10k_ring {
104 struct fm10k_q_vector *q_vector;/* backpointer to host q_vector */
105 struct net_device *netdev; /* netdev ring belongs to */
106 struct device *dev; /* device for DMA mapping */
107 void *desc; /* descriptor ring memory */
108 union {
109 struct fm10k_tx_buffer *tx_buffer;
110 struct fm10k_rx_buffer *rx_buffer;
111 };
112 u32 __iomem *tail;
113 unsigned long state;
114 dma_addr_t dma; /* phys. address of descriptor ring */
115 unsigned int size; /* length in bytes */
116
117 u8 queue_index; /* needed for queue management */
118 u8 reg_idx; /* holds the special value that gets
119 * the hardware register offset
120 * associated with this ring, which is
121 * different for DCB and RSS modes
122 */
123 u8 qos_pc; /* priority class of queue */
124 u16 vid; /* default vlan ID of queue */
125 u16 count; /* amount of descriptors */
126
127 u16 next_to_alloc;
128 u16 next_to_use;
129 u16 next_to_clean;
130
131 struct fm10k_queue_stats stats;
132 struct u64_stats_sync syncp;
133 union {
134 /* Tx */
135 struct fm10k_tx_queue_stats tx_stats;
136 /* Rx */
137 struct {
138 struct fm10k_rx_queue_stats rx_stats;
139 struct sk_buff *skb;
140 };
141 };
142} ____cacheline_internodealigned_in_smp;
143
Alexander Duyck18283ca2014-09-20 19:48:51 -0400144struct fm10k_ring_container {
Alexander Duycke27ef592014-09-20 19:49:03 -0400145 struct fm10k_ring *ring; /* pointer to linked list of rings */
Alexander Duyck18283ca2014-09-20 19:48:51 -0400146 unsigned int total_bytes; /* total bytes processed this int */
147 unsigned int total_packets; /* total packets processed this int */
148 u16 work_limit; /* total work allowed per interrupt */
149 u16 itr; /* interrupt throttle rate value */
150 u8 count; /* total number of rings in vector */
151};
152
153#define FM10K_ITR_MAX 0x0FFF /* maximum value for ITR */
154#define FM10K_ITR_10K 100 /* 100us */
155#define FM10K_ITR_20K 50 /* 50us */
156#define FM10K_ITR_ADAPTIVE 0x8000 /* adaptive interrupt moderation flag */
157
158#define FM10K_ITR_ENABLE (FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR)
159
Alexander Duycke27ef592014-09-20 19:49:03 -0400160static inline struct netdev_queue *txring_txq(const struct fm10k_ring *ring)
161{
162 return &ring->netdev->_tx[ring->queue_index];
163}
164
165/* iterator for handling rings in ring container */
166#define fm10k_for_each_ring(pos, head) \
167 for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)
168
Alexander Duyck18283ca2014-09-20 19:48:51 -0400169#define MAX_Q_VECTORS 256
170#define MIN_Q_VECTORS 1
171enum fm10k_non_q_vectors {
172 FM10K_MBX_VECTOR,
173 NON_Q_VECTORS_PF
174};
175
176#define NON_Q_VECTORS(hw) (((hw)->mac.type == fm10k_mac_pf) ? \
177 NON_Q_VECTORS_PF : \
178 0)
179#define MIN_MSIX_COUNT(hw) (MIN_Q_VECTORS + NON_Q_VECTORS(hw))
180
181struct fm10k_q_vector {
182 struct fm10k_intfc *interface;
183 u32 __iomem *itr; /* pointer to ITR register for this vector */
184 u16 v_idx; /* index of q_vector within interface array */
185 struct fm10k_ring_container rx, tx;
186
187 struct napi_struct napi;
188 char name[IFNAMSIZ + 9];
189
190 struct rcu_head rcu; /* to avoid race with update stats on free */
Alexander Duycke27ef592014-09-20 19:49:03 -0400191
192 /* for dynamic allocation of rings associated with this q_vector */
193 struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
Alexander Duyck18283ca2014-09-20 19:48:51 -0400194};
195
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400196enum fm10k_ring_f_enum {
197 RING_F_RSS,
198 RING_F_QOS,
199 RING_F_ARRAY_SIZE /* must be last in enum set */
200};
201
202struct fm10k_ring_feature {
203 u16 limit; /* upper limit on feature indices */
204 u16 indices; /* current value of indices */
205 u16 mask; /* Mask used for feature to ring mapping */
206 u16 offset; /* offset to start of feature */
207};
208
209#define fm10k_vxlan_port_for_each(vp, intfc) \
210 list_for_each_entry(vp, &(intfc)->vxlan_port, list)
211struct fm10k_vxlan_port {
212 struct list_head list;
213 sa_family_t sa_family;
214 __be16 port;
215};
Alexander Duyck04a5aef2014-09-20 19:46:45 -0400216
217struct fm10k_intfc {
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400218 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
219 struct net_device *netdev;
Alexander Duyck04a5aef2014-09-20 19:46:45 -0400220 struct pci_dev *pdev;
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400221 unsigned long state;
Alexander Duyck04a5aef2014-09-20 19:46:45 -0400222
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400223 u32 flags;
224#define FM10K_FLAG_RESET_REQUESTED (u32)(1 << 0)
225#define FM10K_FLAG_RSS_FIELD_IPV4_UDP (u32)(1 << 1)
226#define FM10K_FLAG_RSS_FIELD_IPV6_UDP (u32)(1 << 2)
227#define FM10K_FLAG_RX_TS_ENABLED (u32)(1 << 3)
228#define FM10K_FLAG_SWPRI_CONFIG (u32)(1 << 4)
229 int xcast_mode;
230
Alexander Duyck18283ca2014-09-20 19:48:51 -0400231 /* Tx fast path data */
232 int num_tx_queues;
233 u16 tx_itr;
234
235 /* Rx fast path data */
236 int num_rx_queues;
237 u16 rx_itr;
238
Alexander Duycke27ef592014-09-20 19:49:03 -0400239 /* TX */
240 struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;
241
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400242 u64 rx_overrun_pf;
243 u64 rx_overrun_vf;
244
Alexander Duycke27ef592014-09-20 19:49:03 -0400245 /* RX */
246 struct fm10k_ring *rx_ring[MAX_QUEUES];
247
Alexander Duyck18283ca2014-09-20 19:48:51 -0400248 /* Queueing vectors */
249 struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
250 struct msix_entry *msix_entries;
251 int num_q_vectors; /* current number of q_vectors for device */
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400252 struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE];
253
254 struct fm10k_hw_stats stats;
Alexander Duyck04a5aef2014-09-20 19:46:45 -0400255 struct fm10k_hw hw;
256 u32 __iomem *uc_addr;
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400257 u16 msg_enable;
Alexander Duyck18283ca2014-09-20 19:48:51 -0400258 u16 tx_ring_count;
259 u16 rx_ring_count;
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400260
261 u32 reta[FM10K_RETA_SIZE];
262 u32 rssrk[FM10K_RSSRK_SIZE];
263
264 /* VXLAN port tracking information */
265 struct list_head vxlan_port;
266
267#if defined(HAVE_DCBNL_IEEE) && defined(CONFIG_DCB)
268 u8 pfc_en;
269#endif
270 u8 rx_pause;
271
272 /* GLORT resources in use by PF */
273 u16 glort;
274 u16 glort_count;
275
276 /* VLAN ID for updating multicast/unicast lists */
277 u16 vid;
Alexander Duyck04a5aef2014-09-20 19:46:45 -0400278};
Alexander Duyckb3890e32014-09-20 19:46:05 -0400279
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400280enum fm10k_state_t {
281 __FM10K_RESETTING,
282 __FM10K_DOWN,
283 __FM10K_MBX_LOCK,
284 __FM10K_LINK_DOWN,
285};
286
287static inline void fm10k_mbx_lock(struct fm10k_intfc *interface)
288{
289 /* busy loop if we cannot obtain the lock as some calls
290 * such as ndo_set_rx_mode may be made in atomic context
291 */
292 while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state))
293 udelay(20);
294}
295
296static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface)
297{
298 /* flush memory to make sure state is correct */
299 smp_mb__before_atomic();
300 clear_bit(__FM10K_MBX_LOCK, &interface->state);
301}
302
303static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
304{
305 return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
306}
307
Alexander Duycke27ef592014-09-20 19:49:03 -0400308/* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
309static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
310 const u32 stat_err_bits)
311{
312 return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
313}
314
315/* fm10k_desc_unused - calculate if we have unused descriptors */
316static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
317{
318 s16 unused = ring->next_to_clean - ring->next_to_use - 1;
319
320 return likely(unused < 0) ? unused + ring->count : unused;
321}
322
323#define FM10K_TX_DESC(R, i) \
324 (&(((struct fm10k_tx_desc *)((R)->desc))[i]))
325#define FM10K_RX_DESC(R, i) \
326 (&(((union fm10k_rx_desc *)((R)->desc))[i]))
327
328#define FM10K_MAX_TXD_PWR 14
329#define FM10K_MAX_DATA_PER_TXD (1 << FM10K_MAX_TXD_PWR)
330
331/* Tx Descriptors needed, worst case */
332#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
333#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
334
335enum fm10k_tx_flags {
336 /* Tx offload flags */
337 FM10K_TX_FLAGS_CSUM = 0x01,
338};
339
340/* This structure is stored as little endian values as that is the native
341 * format of the Rx descriptor. The ordering of these fields is reversed
342 * from the actual ftag header to allow for a single bswap to take care
343 * of placing all of the values in network order
344 */
345union fm10k_ftag_info {
346 __le64 ftag;
347 struct {
348 /* dglort and sglort combined into a single 32bit desc read */
349 __le32 glort;
350 /* upper 16 bits of vlan are reserved 0 for swpri_type_user */
351 __le32 vlan;
352 } d;
353 struct {
354 __le16 dglort;
355 __le16 sglort;
356 __le16 vlan;
357 __le16 swpri_type_user;
358 } w;
359};
360
361struct fm10k_cb {
362 union fm10k_ftag_info fi;
363};
364
365#define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)
366
Alexander Duyckb3890e32014-09-20 19:46:05 -0400367/* main */
368extern char fm10k_driver_name[];
369extern const char fm10k_driver_version[];
Alexander Duyck18283ca2014-09-20 19:48:51 -0400370int fm10k_init_queueing_scheme(struct fm10k_intfc *interface);
371void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface);
Alexander Duyckb3890e32014-09-20 19:46:05 -0400372
373/* PCI */
Alexander Duyck18283ca2014-09-20 19:48:51 -0400374void fm10k_mbx_free_irq(struct fm10k_intfc *);
375int fm10k_mbx_request_irq(struct fm10k_intfc *);
376void fm10k_qv_free_irq(struct fm10k_intfc *interface);
377int fm10k_qv_request_irq(struct fm10k_intfc *interface);
Alexander Duyckb3890e32014-09-20 19:46:05 -0400378int fm10k_register_pci_driver(void);
379void fm10k_unregister_pci_driver(void);
Alexander Duyck504c5ea2014-09-20 19:48:29 -0400380void fm10k_up(struct fm10k_intfc *interface);
381void fm10k_down(struct fm10k_intfc *interface);
Alexander Duyck0e7b3642014-09-20 19:48:10 -0400382
383/* Netdev */
384struct net_device *fm10k_alloc_netdev(void);
Alexander Duyck8f5e20d2014-09-20 19:48:20 -0400385void fm10k_restore_rx_state(struct fm10k_intfc *);
386void fm10k_reset_rx_state(struct fm10k_intfc *);
Alexander Duyck504c5ea2014-09-20 19:48:29 -0400387int fm10k_open(struct net_device *netdev);
388int fm10k_close(struct net_device *netdev);
Alexander Duyckb3890e32014-09-20 19:46:05 -0400389#endif /* _FM10K_H_ */