Peter Chen | c10b4f0 | 2013-08-14 12:44:06 +0300 | [diff] [blame] | 1 | /* |
| 2 | * otg.c - ChipIdea USB IP core OTG driver |
| 3 | * |
| 4 | * Copyright (C) 2013 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * Author: Peter Chen |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * This file mainly handles otgsc register, it may include OTG operation |
| 15 | * in the future. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/usb/otg.h> |
| 19 | #include <linux/usb/gadget.h> |
| 20 | #include <linux/usb/chipidea.h> |
| 21 | |
| 22 | #include "ci.h" |
| 23 | #include "bits.h" |
| 24 | #include "otg.h" |
Li Jun | 57677be | 2014-04-23 15:56:44 +0800 | [diff] [blame] | 25 | #include "otg_fsm.h" |
Peter Chen | c10b4f0 | 2013-08-14 12:44:06 +0300 | [diff] [blame] | 26 | |
| 27 | /** |
Li Jun | 0c33bf7 | 2014-04-23 15:56:38 +0800 | [diff] [blame] | 28 | * hw_read_otgsc returns otgsc register bits value. |
| 29 | * @mask: bitfield mask |
| 30 | */ |
| 31 | u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask) |
| 32 | { |
| 33 | return hw_read(ci, OP_OTGSC, mask); |
| 34 | } |
| 35 | |
| 36 | /** |
| 37 | * hw_write_otgsc updates target bits of OTGSC register. |
| 38 | * @mask: bitfield mask |
| 39 | * @data: to be written |
| 40 | */ |
| 41 | void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data) |
| 42 | { |
| 43 | hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data); |
| 44 | } |
| 45 | |
| 46 | /** |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 47 | * ci_otg_role - pick role based on ID pin state |
| 48 | * @ci: the controller |
| 49 | */ |
| 50 | enum ci_role ci_otg_role(struct ci_hdrc *ci) |
| 51 | { |
Li Jun | 0c33bf7 | 2014-04-23 15:56:38 +0800 | [diff] [blame] | 52 | enum ci_role role = hw_read_otgsc(ci, OTGSC_ID) |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 53 | ? CI_ROLE_GADGET |
| 54 | : CI_ROLE_HOST; |
| 55 | |
| 56 | return role; |
| 57 | } |
| 58 | |
Peter Chen | a107f8c | 2013-08-14 12:44:11 +0300 | [diff] [blame] | 59 | void ci_handle_vbus_change(struct ci_hdrc *ci) |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 60 | { |
Peter Chen | a107f8c | 2013-08-14 12:44:11 +0300 | [diff] [blame] | 61 | if (!ci->is_otg) |
| 62 | return; |
| 63 | |
Li Jun | 0c33bf7 | 2014-04-23 15:56:38 +0800 | [diff] [blame] | 64 | if (hw_read_otgsc(ci, OTGSC_BSV)) |
Peter Chen | a107f8c | 2013-08-14 12:44:11 +0300 | [diff] [blame] | 65 | usb_gadget_vbus_connect(&ci->gadget); |
| 66 | else |
| 67 | usb_gadget_vbus_disconnect(&ci->gadget); |
| 68 | } |
| 69 | |
Peter Chen | 22fa844 | 2013-08-14 12:44:12 +0300 | [diff] [blame] | 70 | #define CI_VBUS_STABLE_TIMEOUT_MS 5000 |
Peter Chen | a107f8c | 2013-08-14 12:44:11 +0300 | [diff] [blame] | 71 | static void ci_handle_id_switch(struct ci_hdrc *ci) |
| 72 | { |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 73 | enum ci_role role = ci_otg_role(ci); |
| 74 | |
| 75 | if (role != ci->role) { |
| 76 | dev_dbg(ci->dev, "switching from %s to %s\n", |
| 77 | ci_role(ci)->name, ci->roles[role]->name); |
| 78 | |
| 79 | ci_role_stop(ci); |
Peter Chen | 22fa844 | 2013-08-14 12:44:12 +0300 | [diff] [blame] | 80 | /* wait vbus lower than OTGSC_BSV */ |
| 81 | hw_wait_reg(ci, OP_OTGSC, OTGSC_BSV, 0, |
| 82 | CI_VBUS_STABLE_TIMEOUT_MS); |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 83 | ci_role_start(ci, role); |
| 84 | } |
Peter Chen | a107f8c | 2013-08-14 12:44:11 +0300 | [diff] [blame] | 85 | } |
| 86 | /** |
| 87 | * ci_otg_work - perform otg (vbus/id) event handle |
| 88 | * @work: work struct |
| 89 | */ |
| 90 | static void ci_otg_work(struct work_struct *work) |
| 91 | { |
| 92 | struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work); |
| 93 | |
| 94 | if (ci->id_event) { |
| 95 | ci->id_event = false; |
| 96 | ci_handle_id_switch(ci); |
| 97 | } else if (ci->b_sess_valid_event) { |
| 98 | ci->b_sess_valid_event = false; |
| 99 | ci_handle_vbus_change(ci); |
| 100 | } else |
| 101 | dev_err(ci->dev, "unexpected event occurs at %s\n", __func__); |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 102 | |
| 103 | enable_irq(ci->irq); |
| 104 | } |
| 105 | |
Peter Chen | a107f8c | 2013-08-14 12:44:11 +0300 | [diff] [blame] | 106 | |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 107 | /** |
| 108 | * ci_hdrc_otg_init - initialize otg struct |
Peter Chen | c10b4f0 | 2013-08-14 12:44:06 +0300 | [diff] [blame] | 109 | * ci: the controller |
| 110 | */ |
| 111 | int ci_hdrc_otg_init(struct ci_hdrc *ci) |
| 112 | { |
Peter Chen | a107f8c | 2013-08-14 12:44:11 +0300 | [diff] [blame] | 113 | INIT_WORK(&ci->work, ci_otg_work); |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 114 | ci->wq = create_singlethread_workqueue("ci_otg"); |
| 115 | if (!ci->wq) { |
| 116 | dev_err(ci->dev, "can't create workqueue\n"); |
| 117 | return -ENODEV; |
| 118 | } |
Peter Chen | c10b4f0 | 2013-08-14 12:44:06 +0300 | [diff] [blame] | 119 | |
Li Jun | 57677be | 2014-04-23 15:56:44 +0800 | [diff] [blame] | 120 | if (ci_otg_is_fsm_mode(ci)) |
| 121 | return ci_hdrc_otg_fsm_init(ci); |
| 122 | |
Peter Chen | c10b4f0 | 2013-08-14 12:44:06 +0300 | [diff] [blame] | 123 | return 0; |
| 124 | } |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 125 | |
| 126 | /** |
| 127 | * ci_hdrc_otg_destroy - destroy otg struct |
| 128 | * ci: the controller |
| 129 | */ |
| 130 | void ci_hdrc_otg_destroy(struct ci_hdrc *ci) |
| 131 | { |
| 132 | if (ci->wq) { |
| 133 | flush_workqueue(ci->wq); |
| 134 | destroy_workqueue(ci->wq); |
| 135 | } |
Li Jun | 0c33bf7 | 2014-04-23 15:56:38 +0800 | [diff] [blame] | 136 | /* Disable all OTG irq and clear status */ |
| 137 | hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, |
| 138 | OTGSC_INT_STATUS_BITS); |
Peter Chen | cbec6bd | 2013-08-14 12:44:10 +0300 | [diff] [blame] | 139 | } |