blob: d76db51ecda7996fd482325cc7303e44247a056c [file] [log] [blame]
Peter Chenc10b4f02013-08-14 12:44:06 +03001/*
2 * otg.c - ChipIdea USB IP core OTG driver
3 *
4 * Copyright (C) 2013 Freescale Semiconductor, Inc.
5 *
6 * Author: Peter Chen
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * This file mainly handles otgsc register, it may include OTG operation
15 * in the future.
16 */
17
18#include <linux/usb/otg.h>
19#include <linux/usb/gadget.h>
20#include <linux/usb/chipidea.h>
21
22#include "ci.h"
23#include "bits.h"
24#include "otg.h"
Li Jun57677be2014-04-23 15:56:44 +080025#include "otg_fsm.h"
Peter Chenc10b4f02013-08-14 12:44:06 +030026
27/**
Li Jun0c33bf72014-04-23 15:56:38 +080028 * hw_read_otgsc returns otgsc register bits value.
29 * @mask: bitfield mask
30 */
31u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask)
32{
33 return hw_read(ci, OP_OTGSC, mask);
34}
35
36/**
37 * hw_write_otgsc updates target bits of OTGSC register.
38 * @mask: bitfield mask
39 * @data: to be written
40 */
41void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data)
42{
43 hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data);
44}
45
46/**
Peter Chencbec6bd2013-08-14 12:44:10 +030047 * ci_otg_role - pick role based on ID pin state
48 * @ci: the controller
49 */
50enum ci_role ci_otg_role(struct ci_hdrc *ci)
51{
Li Jun0c33bf72014-04-23 15:56:38 +080052 enum ci_role role = hw_read_otgsc(ci, OTGSC_ID)
Peter Chencbec6bd2013-08-14 12:44:10 +030053 ? CI_ROLE_GADGET
54 : CI_ROLE_HOST;
55
56 return role;
57}
58
Peter Chena107f8c2013-08-14 12:44:11 +030059void ci_handle_vbus_change(struct ci_hdrc *ci)
Peter Chencbec6bd2013-08-14 12:44:10 +030060{
Peter Chena107f8c2013-08-14 12:44:11 +030061 if (!ci->is_otg)
62 return;
63
Li Jun0c33bf72014-04-23 15:56:38 +080064 if (hw_read_otgsc(ci, OTGSC_BSV))
Peter Chena107f8c2013-08-14 12:44:11 +030065 usb_gadget_vbus_connect(&ci->gadget);
66 else
67 usb_gadget_vbus_disconnect(&ci->gadget);
68}
69
Peter Chen22fa8442013-08-14 12:44:12 +030070#define CI_VBUS_STABLE_TIMEOUT_MS 5000
Peter Chena107f8c2013-08-14 12:44:11 +030071static void ci_handle_id_switch(struct ci_hdrc *ci)
72{
Peter Chencbec6bd2013-08-14 12:44:10 +030073 enum ci_role role = ci_otg_role(ci);
74
75 if (role != ci->role) {
76 dev_dbg(ci->dev, "switching from %s to %s\n",
77 ci_role(ci)->name, ci->roles[role]->name);
78
79 ci_role_stop(ci);
Peter Chen22fa8442013-08-14 12:44:12 +030080 /* wait vbus lower than OTGSC_BSV */
81 hw_wait_reg(ci, OP_OTGSC, OTGSC_BSV, 0,
82 CI_VBUS_STABLE_TIMEOUT_MS);
Peter Chencbec6bd2013-08-14 12:44:10 +030083 ci_role_start(ci, role);
84 }
Peter Chena107f8c2013-08-14 12:44:11 +030085}
86/**
87 * ci_otg_work - perform otg (vbus/id) event handle
88 * @work: work struct
89 */
90static void ci_otg_work(struct work_struct *work)
91{
92 struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
93
94 if (ci->id_event) {
95 ci->id_event = false;
96 ci_handle_id_switch(ci);
97 } else if (ci->b_sess_valid_event) {
98 ci->b_sess_valid_event = false;
99 ci_handle_vbus_change(ci);
100 } else
101 dev_err(ci->dev, "unexpected event occurs at %s\n", __func__);
Peter Chencbec6bd2013-08-14 12:44:10 +0300102
103 enable_irq(ci->irq);
104}
105
Peter Chena107f8c2013-08-14 12:44:11 +0300106
Peter Chencbec6bd2013-08-14 12:44:10 +0300107/**
108 * ci_hdrc_otg_init - initialize otg struct
Peter Chenc10b4f02013-08-14 12:44:06 +0300109 * ci: the controller
110 */
111int ci_hdrc_otg_init(struct ci_hdrc *ci)
112{
Peter Chena107f8c2013-08-14 12:44:11 +0300113 INIT_WORK(&ci->work, ci_otg_work);
Peter Chencbec6bd2013-08-14 12:44:10 +0300114 ci->wq = create_singlethread_workqueue("ci_otg");
115 if (!ci->wq) {
116 dev_err(ci->dev, "can't create workqueue\n");
117 return -ENODEV;
118 }
Peter Chenc10b4f02013-08-14 12:44:06 +0300119
Li Jun57677be2014-04-23 15:56:44 +0800120 if (ci_otg_is_fsm_mode(ci))
121 return ci_hdrc_otg_fsm_init(ci);
122
Peter Chenc10b4f02013-08-14 12:44:06 +0300123 return 0;
124}
Peter Chencbec6bd2013-08-14 12:44:10 +0300125
126/**
127 * ci_hdrc_otg_destroy - destroy otg struct
128 * ci: the controller
129 */
130void ci_hdrc_otg_destroy(struct ci_hdrc *ci)
131{
132 if (ci->wq) {
133 flush_workqueue(ci->wq);
134 destroy_workqueue(ci->wq);
135 }
Li Jun0c33bf72014-04-23 15:56:38 +0800136 /* Disable all OTG irq and clear status */
137 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
138 OTGSC_INT_STATUS_BITS);
Peter Chencbec6bd2013-08-14 12:44:10 +0300139}