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gerrit-public.fairphone.software / kernel / msm-5.4 / e2fee5723bbda4a05c86f16a9d0f889a2c4ecede / . / arch / mips / include / asm / mach-loongson / loongson.h
blob: e6869aa52bc836abe8300661f4229f0dbf7f6e45 [file] [log] [blame]
Wu Zhangjin5e983ff2009-07-02 23:23:03 +0800[diff] [blame]1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 */
11
12#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
13#define __ASM_MACH_LOONGSON_LOONGSON_H
14
15#include <linux/io.h>
16#include <linux/init.h>
17
Wu Zhangjin5e983ff2009-07-02 23:23:03 +0800[diff] [blame]18/* loongson internal northbridge initialization */
19extern void bonito_irq_init(void);
20
Wu Zhangjin85749d22009-07-02 23:26:45 +0800[diff] [blame]21/* machine-specific reboot/halt operation */
22extern void mach_prepare_reboot(void);
23extern void mach_prepare_shutdown(void);
24
Wu Zhangjin5e983ff2009-07-02 23:23:03 +0800[diff] [blame]25/* environment arguments from bootloader */
26extern unsigned long bus_clock, cpu_clock_freq;
27extern unsigned long memsize, highmemsize;
28
29/* loongson-specific command line, env and memory initialization */
30extern void __init prom_init_memory(void);
31extern void __init prom_init_cmdline(void);
32extern void __init prom_init_env(void);
33
Wu Zhangjin85749d22009-07-02 23:26:45 +0800[diff] [blame]34/* irq operation functions */
35extern void bonito_irqdispatch(void);
36extern void __init bonito_irq_init(void);
37extern void __init set_irq_trigger_mode(void);
38extern void __init mach_init_irq(void);
39extern void mach_irq_dispatch(unsigned int pending);
40
Wu Zhangjine2fee572009-10-16 14:17:19 +0800[diff] [blame^]41#define LOONGSON_REG(x) \
42 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
43
44#define LOONGSON_IRQ_BASE 32
45#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
46
47#define LOONGSON_FLASH_BASE 0x1c000000
48#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
49#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
50
51#define LOONGSON_LIO0_BASE 0x1e000000
52#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
53#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
54
55#define LOONGSON_BOOT_BASE 0x1fc00000
56#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
57#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
58#define LOONGSON_REG_BASE 0x1fe00000
59#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
60#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
61
62#define LOONGSON_LIO1_BASE 0x1ff00000
63#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
64#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
65
66#define LOONGSON_PCILO0_BASE 0x10000000
67#define LOONGSON_PCILO1_BASE 0x14000000
68#define LOONGSON_PCILO2_BASE 0x18000000
69#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
70#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
71#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
72
73#define LOONGSON_PCICFG_BASE 0x1fe80000
74#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
75#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
76#define LOONGSON_PCIIO_BASE 0x1fd00000
77#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
78#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
79
80/* Loongson Register Bases */
81
82#define LOONGSON_PCICONFIGBASE 0x00
83#define LOONGSON_REGBASE 0x100
84
Wu Zhangjinf7face02009-07-02 23:23:30 +0800[diff] [blame]85/* PCI Configuration Registers */
Wu Zhangjine2fee572009-10-16 14:17:19 +0800[diff] [blame^]86
87#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
88#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
89#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
90#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
91#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
92#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
93#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
94#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
95#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
96#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
97#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
98#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
99
100#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
101
102#define LOONGSON_PCICMD_PERR_CLR 0x80000000
103#define LOONGSON_PCICMD_SERR_CLR 0x40000000
104#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
105#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
106#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
107#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
108#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
109#define LOONGSON_PCICMD_ASTEPEN 0x00000080
110#define LOONGSON_PCICMD_SERREN 0x00000100
111#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
112#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
113
114/* Loongson h/w Configuration */
115
116#define LOONGSON_GENCFG_OFFSET 0x4
117#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
118
119#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
120#define LOONGSON_GENCFG_SNOOPEN 0x00000002
121#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
122
123#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
124#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
125#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
126#define LOONGSON_GENCFG_BYTESWAP 0x00000040
127
128#define LOONGSON_GENCFG_UNCACHED 0x00000080
129#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
130#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
131#define LOONGSON_GENCFG_CACHEALG 0x00000c00
132#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
133#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
134#define LOONGSON_GENCFG_CACHESTOP 0x00002000
135#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
136#define LOONGSON_GENCFG_BUSERREN 0x00008000
137#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
138#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
139
140/* PCI address map control */
141
142#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
143#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
144#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
145
146/* GPIO Regs - r/w */
147
148#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
149#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
150
151/* ICU Configuration Regs - r/w */
152
153#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
154#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
155#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
156
157/* ICU Enable Regs - IntEn & IntISR are r/o. */
158
159#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
160#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
161#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
162#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
163
164/* ICU */
165#define LOONGSON_ICU_MBOXES 0x0000000f
166#define LOONGSON_ICU_MBOXES_SHIFT 0
167#define LOONGSON_ICU_DMARDY 0x00000010
168#define LOONGSON_ICU_DMAEMPTY 0x00000020
169#define LOONGSON_ICU_COPYRDY 0x00000040
170#define LOONGSON_ICU_COPYEMPTY 0x00000080
171#define LOONGSON_ICU_COPYERR 0x00000100
172#define LOONGSON_ICU_PCIIRQ 0x00000200
173#define LOONGSON_ICU_MASTERERR 0x00000400
174#define LOONGSON_ICU_SYSTEMERR 0x00000800
175#define LOONGSON_ICU_DRAMPERR 0x00001000
176#define LOONGSON_ICU_RETRYERR 0x00002000
177#define LOONGSON_ICU_GPIOS 0x01ff0000
178#define LOONGSON_ICU_GPIOS_SHIFT 16
179#define LOONGSON_ICU_GPINS 0x7e000000
180#define LOONGSON_ICU_GPINS_SHIFT 25
181#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
182#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
183#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
184
185/* PCI prefetch window base & mask */
186
187#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
188#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
189#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
190#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
Wu Zhangjinf7face02009-07-02 23:23:30 +0800[diff] [blame]191
192/* PCI_Hit*_Sel_* */
193
Wu Zhangjine2fee572009-10-16 14:17:19 +0800[diff] [blame^]194#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
195#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
196#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
197#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
198#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
199#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
Wu Zhangjinf7face02009-07-02 23:23:30 +0800[diff] [blame]200
201/* PXArb Config & Status */
202
Wu Zhangjine2fee572009-10-16 14:17:19 +0800[diff] [blame^]203#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
204#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
Wu Zhangjinf7face02009-07-02 23:23:30 +0800[diff] [blame]205
Wu Zhangjine2fee572009-10-16 14:17:19 +0800[diff] [blame^]206/* pcimap */
207
208#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
209#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
210#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
211#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
212#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
213#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
214#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
215#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
216 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
Wu Zhangjin67b35e52009-07-02 23:25:46 +0800[diff] [blame]217
Wu Zhangjin5e983ff2009-07-02 23:23:03 +0800[diff] [blame]218#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */