| David Howells | a0616cd | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright IBM Corp. 1999, 2009 |
| 3 | * |
| 4 | * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __ASM_BARRIER_H |
| 8 | #define __ASM_BARRIER_H |
| 9 | |
| 10 | /* |
| 11 | * Force strict CPU ordering. |
| 12 | * And yes, this is required on UP too when we're talking |
| 13 | * to devices. |
| David Howells | a0616cd | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 14 | */ |
| 15 | |
| Heiko Carstens | c6f48b0 | 2012-05-14 12:40:43 +0200 | [diff] [blame] | 16 | static inline void mb(void) |
| 17 | { |
| Heiko Carstens | e5b8d75 | 2012-05-14 12:41:54 +0200 | [diff] [blame^] | 18 | #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES |
| 19 | /* Fast-BCR without checkpoint synchronization */ |
| 20 | asm volatile("bcr 14,0" : : : "memory"); |
| 21 | #else |
| Heiko Carstens | c6f48b0 | 2012-05-14 12:40:43 +0200 | [diff] [blame] | 22 | asm volatile("bcr 15,0" : : : "memory"); |
| Heiko Carstens | e5b8d75 | 2012-05-14 12:41:54 +0200 | [diff] [blame^] | 23 | #endif |
| Heiko Carstens | c6f48b0 | 2012-05-14 12:40:43 +0200 | [diff] [blame] | 24 | } |
| David Howells | a0616cd | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 25 | |
| Heiko Carstens | c6f48b0 | 2012-05-14 12:40:43 +0200 | [diff] [blame] | 26 | #define rmb() mb() |
| 27 | #define wmb() mb() |
| 28 | #define read_barrier_depends() do { } while(0) |
| 29 | #define smp_mb() mb() |
| 30 | #define smp_rmb() rmb() |
| 31 | #define smp_wmb() wmb() |
| 32 | #define smp_read_barrier_depends() read_barrier_depends() |
| 33 | #define smp_mb__before_clear_bit() smp_mb() |
| 34 | #define smp_mb__after_clear_bit() smp_mb() |
| 35 | |
| 36 | #define set_mb(var, value) do { var = value; mb(); } while (0) |
| David Howells | a0616cd | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 37 | |
| 38 | #endif /* __ASM_BARRIER_H */ |