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gerrit-public.fairphone.software / kernel / msm-5.4 / e71c9fac316221a4594f3bd58c2d30ada0cabaf6 / . / drivers / net / wireless / ath5k / phy.c
blob: 405195ffb24d49f042f4cc30d1d06f2e56b91dc5 [file] [log] [blame]
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1/*
2 * PHY functions
3 *
4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006, 2007 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22#include <linux/delay.h>
23
24#include "ath5k.h"
25#include "reg.h"
26#include "base.h"
27
28/* Struct to hold initial RF register values (RF Banks) */
29struct ath5k_ini_rf {
30 u8 rf_bank; /* check out ath5k_reg.h */
31 u16 rf_register; /* register address */
32 u32 rf_value[5]; /* register value for different modes (above) */
33};
34
35/*
36 * Mode-specific RF Gain table (64bytes) for RF5111/5112
37 * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
38 * RF Gain values are included in AR5K_AR5210_INI)
39 */
40struct ath5k_ini_rfgain {
41 u16 rfg_register; /* RF Gain register address */
42 u32 rfg_value[2]; /* [freq (see below)] */
43};
44
45struct ath5k_gain_opt {
46 u32 go_default;
47 u32 go_steps_count;
48 const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
49};
50
51/* RF5111 mode-specific init registers */
52static const struct ath5k_ini_rf rfregs_5111[] = {
53 { 0, 0x989c,
54 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
55 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
56 { 0, 0x989c,
57 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
58 { 0, 0x989c,
59 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
60 { 0, 0x989c,
61 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
62 { 0, 0x989c,
63 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
64 { 0, 0x989c,
65 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
66 { 0, 0x989c,
67 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
68 { 0, 0x989c,
69 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
70 { 0, 0x989c,
71 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
72 { 0, 0x989c,
73 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
74 { 0, 0x989c,
75 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
76 { 0, 0x989c,
77 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
78 { 0, 0x989c,
79 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
80 { 0, 0x989c,
81 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
82 { 0, 0x989c,
83 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
84 { 0, 0x989c,
85 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
86 { 0, 0x98d4,
87 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
88 { 1, 0x98d4,
89 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
90 { 2, 0x98d4,
91 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
92 { 3, 0x98d8,
93 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
94 { 6, 0x989c,
95 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
96 { 6, 0x989c,
97 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
98 { 6, 0x989c,
99 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
100 { 6, 0x989c,
101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
102 { 6, 0x989c,
103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
104 { 6, 0x989c,
105 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
106 { 6, 0x989c,
107 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
108 { 6, 0x989c,
109 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
110 { 6, 0x989c,
111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
112 { 6, 0x989c,
113 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
114 { 6, 0x989c,
115 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
116 { 6, 0x989c,
117 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
118 { 6, 0x989c,
119 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
120 { 6, 0x989c,
121 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
122 { 6, 0x989c,
123 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
124 { 6, 0x989c,
125 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
126 { 6, 0x98d4,
127 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
128 { 7, 0x989c,
129 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
130 { 7, 0x989c,
131 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
132 { 7, 0x989c,
133 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
134 { 7, 0x989c,
135 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
136 { 7, 0x989c,
137 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
138 { 7, 0x989c,
139 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
140 { 7, 0x989c,
141 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
142 { 7, 0x98cc,
143 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
144};
145
146/* Initial RF Gain settings for RF5111 */
147static const struct ath5k_ini_rfgain rfgain_5111[] = {
148 /* 5Ghz 2Ghz */
149 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
150 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
151 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
152 { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
153 { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
154 { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
155 { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
156 { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
157 { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
158 { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
159 { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } },
160 { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } },
161 { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } },
162 { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } },
163 { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } },
164 { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } },
165 { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } },
166 { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } },
167 { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } },
168 { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } },
169 { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } },
170 { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } },
171 { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } },
172 { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } },
173 { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } },
174 { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } },
175 { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } },
176 { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } },
177 { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } },
178 { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } },
179 { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } },
180 { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } },
181 { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } },
182 { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } },
183 { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } },
184 { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } },
185 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } },
186 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } },
187 { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } },
188 { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } },
189 { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } },
190 { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } },
191 { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } },
192 { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } },
193 { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } },
194 { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } },
195 { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } },
196 { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } },
197 { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } },
198 { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } },
199 { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } },
200 { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } },
201 { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } },
202 { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } },
203 { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } },
204 { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } },
205 { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } },
206 { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } },
207 { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } },
208 { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } },
209 { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } },
210 { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } },
211 { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } },
212 { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } },
213};
214
215static const struct ath5k_gain_opt rfgain_opt_5111 = {
216 4,
217 9,
218 {
219 { { 4, 1, 1, 1 }, 6 },
220 { { 4, 0, 1, 1 }, 4 },
221 { { 3, 1, 1, 1 }, 3 },
222 { { 4, 0, 0, 1 }, 1 },
223 { { 4, 1, 1, 0 }, 0 },
224 { { 4, 0, 1, 0 }, -2 },
225 { { 3, 1, 1, 0 }, -3 },
226 { { 4, 0, 0, 0 }, -4 },
227 { { 2, 1, 1, 0 }, -6 }
228 }
229};
230
231/* RF5112 mode-specific init registers */
232static const struct ath5k_ini_rf rfregs_5112[] = {
233 { 1, 0x98d4,
234 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
235 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
236 { 2, 0x98d0,
237 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
238 { 3, 0x98dc,
239 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
240 { 6, 0x989c,
241 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
242 { 6, 0x989c,
243 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
244 { 6, 0x989c,
245 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
246 { 6, 0x989c,
247 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
248 { 6, 0x989c,
249 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
250 { 6, 0x989c,
251 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
252 { 6, 0x989c,
253 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
254 { 6, 0x989c,
255 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
256 { 6, 0x989c,
257 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
258 { 6, 0x989c,
259 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
260 { 6, 0x989c,
261 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
262 { 6, 0x989c,
263 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
264 { 6, 0x989c,
265 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
266 { 6, 0x989c,
267 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
268 { 6, 0x989c,
269 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
270 { 6, 0x989c,
271 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
272 { 6, 0x989c,
273 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
274 { 6, 0x989c,
275 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
276 { 6, 0x989c,
277 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
278 { 6, 0x989c,
279 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
280 { 6, 0x989c,
281 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
282 { 6, 0x989c,
283 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
284 { 6, 0x989c,
285 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
286 { 6, 0x989c,
287 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
288 { 6, 0x989c,
289 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
290 { 6, 0x989c,
291 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
292 { 6, 0x989c,
293 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
294 { 6, 0x989c,
295 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
296 { 6, 0x989c,
297 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
298 { 6, 0x989c,
299 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
300 { 6, 0x989c,
301 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
302 { 6, 0x989c,
303 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
304 { 6, 0x989c,
305 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
306 { 6, 0x989c,
307 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
308 { 6, 0x989c,
309 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
310 { 6, 0x989c,
311 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
312 { 6, 0x989c,
313 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
314 { 6, 0x98d0,
315 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
316 { 7, 0x989c,
317 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
318 { 7, 0x989c,
319 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
320 { 7, 0x989c,
321 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
322 { 7, 0x989c,
323 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
324 { 7, 0x989c,
325 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
326 { 7, 0x989c,
327 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
328 { 7, 0x989c,
329 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
330 { 7, 0x989c,
331 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
332 { 7, 0x989c,
333 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
334 { 7, 0x989c,
335 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
336 { 7, 0x989c,
337 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
338 { 7, 0x989c,
339 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
340 { 7, 0x98c4,
341 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
342};
343
344/* RF5112A mode-specific init registers */
345static const struct ath5k_ini_rf rfregs_5112a[] = {
346 { 1, 0x98d4,
347 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
348 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
349 { 2, 0x98d0,
350 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
351 { 3, 0x98dc,
352 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
353 { 6, 0x989c,
354 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
355 { 6, 0x989c,
356 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
357 { 6, 0x989c,
358 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
359 { 6, 0x989c,
360 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
361 { 6, 0x989c,
362 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
363 { 6, 0x989c,
364 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
365 { 6, 0x989c,
366 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
367 { 6, 0x989c,
368 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
369 { 6, 0x989c,
370 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
371 { 6, 0x989c,
372 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
373 { 6, 0x989c,
374 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
375 { 6, 0x989c,
376 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
377 { 6, 0x989c,
378 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
379 { 6, 0x989c,
380 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
381 { 6, 0x989c,
382 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
383 { 6, 0x989c,
384 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
385 { 6, 0x989c,
386 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
387 { 6, 0x989c,
388 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
389 { 6, 0x989c,
390 { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
391 { 6, 0x989c,
392 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
393 { 6, 0x989c,
394 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
395 { 6, 0x989c,
396 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
397 { 6, 0x989c,
398 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
399 { 6, 0x989c,
400 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
401 { 6, 0x989c,
402 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
403 { 6, 0x989c,
404 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
405 { 6, 0x989c,
406 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
407 { 6, 0x989c,
408 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
409 { 6, 0x989c,
410 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
411 { 6, 0x989c,
412 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
413 { 6, 0x989c,
414 { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
415 { 6, 0x989c,
416 { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
417 { 6, 0x989c,
418 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
419 { 6, 0x989c,
420 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
421 { 6, 0x989c,
422 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
423 { 6, 0x989c,
424 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
425 { 6, 0x989c,
426 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
427 { 6, 0x989c,
428 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
429 { 6, 0x989c,
430 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
431 { 6, 0x98d8,
432 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
433 { 7, 0x989c,
434 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
435 { 7, 0x989c,
436 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
437 { 7, 0x989c,
438 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
439 { 7, 0x989c,
440 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
441 { 7, 0x989c,
442 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
443 { 7, 0x989c,
444 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
445 { 7, 0x989c,
446 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
447 { 7, 0x989c,
448 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
449 { 7, 0x989c,
450 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
451 { 7, 0x989c,
452 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
453 { 7, 0x989c,
454 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
455 { 7, 0x989c,
456 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
457 { 7, 0x98c4,
458 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
459};
460
461
462static const struct ath5k_ini_rf rfregs_2112a[] = {
463 { 1, AR5K_RF_BUFFER_CONTROL_4,
464 /* mode b mode g mode gTurbo */
465 { 0x00000020, 0x00000020, 0x00000020 } },
466 { 2, AR5K_RF_BUFFER_CONTROL_3,
467 { 0x03060408, 0x03060408, 0x03070408 } },
468 { 3, AR5K_RF_BUFFER_CONTROL_6,
469 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
470 { 6, AR5K_RF_BUFFER,
471 { 0x0a000000, 0x0a000000, 0x0a000000 } },
472 { 6, AR5K_RF_BUFFER,
473 { 0x00000000, 0x00000000, 0x00000000 } },
474 { 6, AR5K_RF_BUFFER,
475 { 0x00800000, 0x00800000, 0x00800000 } },
476 { 6, AR5K_RF_BUFFER,
477 { 0x002a0000, 0x002a0000, 0x002a0000 } },
478 { 6, AR5K_RF_BUFFER,
479 { 0x00010000, 0x00010000, 0x00010000 } },
480 { 6, AR5K_RF_BUFFER,
481 { 0x00000000, 0x00000000, 0x00000000 } },
482 { 6, AR5K_RF_BUFFER,
483 { 0x00180000, 0x00180000, 0x00180000 } },
484 { 6, AR5K_RF_BUFFER,
485 { 0x006e0000, 0x006e0000, 0x006e0000 } },
486 { 6, AR5K_RF_BUFFER,
487 { 0x00c70000, 0x00c70000, 0x00c70000 } },
488 { 6, AR5K_RF_BUFFER,
489 { 0x004b0000, 0x004b0000, 0x004b0000 } },
490 { 6, AR5K_RF_BUFFER,
491 { 0x04480000, 0x04480000, 0x04480000 } },
492 { 6, AR5K_RF_BUFFER,
493 { 0x002a0000, 0x002a0000, 0x002a0000 } },
494 { 6, AR5K_RF_BUFFER,
495 { 0x00e40000, 0x00e40000, 0x00e40000 } },
496 { 6, AR5K_RF_BUFFER,
497 { 0x00000000, 0x00000000, 0x00000000 } },
498 { 6, AR5K_RF_BUFFER,
499 { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
500 { 6, AR5K_RF_BUFFER,
501 { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
502 { 6, AR5K_RF_BUFFER,
503 { 0x043f0000, 0x043f0000, 0x043f0000 } },
504 { 6, AR5K_RF_BUFFER,
505 { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
506 { 6, AR5K_RF_BUFFER,
507 { 0x02190000, 0x02190000, 0x02190000 } },
508 { 6, AR5K_RF_BUFFER,
509 { 0x00240000, 0x00240000, 0x00240000 } },
510 { 6, AR5K_RF_BUFFER,
511 { 0x00b40000, 0x00b40000, 0x00b40000 } },
512 { 6, AR5K_RF_BUFFER,
513 { 0x00990000, 0x00990000, 0x00990000 } },
514 { 6, AR5K_RF_BUFFER,
515 { 0x00500000, 0x00500000, 0x00500000 } },
516 { 6, AR5K_RF_BUFFER,
517 { 0x002a0000, 0x002a0000, 0x002a0000 } },
518 { 6, AR5K_RF_BUFFER,
519 { 0x00120000, 0x00120000, 0x00120000 } },
520 { 6, AR5K_RF_BUFFER,
521 { 0xc0320000, 0xc0320000, 0xc0320000 } },
522 { 6, AR5K_RF_BUFFER,
523 { 0x01740000, 0x01740000, 0x01740000 } },
524 { 6, AR5K_RF_BUFFER,
525 { 0x00110000, 0x00110000, 0x00110000 } },
526 { 6, AR5K_RF_BUFFER,
527 { 0x86280000, 0x86280000, 0x86280000 } },
528 { 6, AR5K_RF_BUFFER,
529 { 0x31840000, 0x31840000, 0x31840000 } },
530 { 6, AR5K_RF_BUFFER,
531 { 0x00f20080, 0x00f20080, 0x00f20080 } },
532 { 6, AR5K_RF_BUFFER,
533 { 0x00070019, 0x00070019, 0x00070019 } },
534 { 6, AR5K_RF_BUFFER,
535 { 0x00000000, 0x00000000, 0x00000000 } },
536 { 6, AR5K_RF_BUFFER,
537 { 0x00000000, 0x00000000, 0x00000000 } },
538 { 6, AR5K_RF_BUFFER,
539 { 0x000000b2, 0x000000b2, 0x000000b2 } },
540 { 6, AR5K_RF_BUFFER,
541 { 0x00b02184, 0x00b02184, 0x00b02184 } },
542 { 6, AR5K_RF_BUFFER,
543 { 0x004125a4, 0x004125a4, 0x004125a4 } },
544 { 6, AR5K_RF_BUFFER,
545 { 0x00119220, 0x00119220, 0x00119220 } },
546 { 6, AR5K_RF_BUFFER,
547 { 0x001a4800, 0x001a4800, 0x001a4800 } },
548 { 6, AR5K_RF_BUFFER_CONTROL_5,
549 { 0x000b0230, 0x000b0230, 0x000b0230 } },
550 { 7, AR5K_RF_BUFFER,
551 { 0x00000094, 0x00000094, 0x00000094 } },
552 { 7, AR5K_RF_BUFFER,
553 { 0x00000091, 0x00000091, 0x00000091 } },
554 { 7, AR5K_RF_BUFFER,
555 { 0x00000012, 0x00000012, 0x00000012 } },
556 { 7, AR5K_RF_BUFFER,
557 { 0x00000080, 0x00000080, 0x00000080 } },
558 { 7, AR5K_RF_BUFFER,
559 { 0x000000d9, 0x000000d9, 0x000000d9 } },
560 { 7, AR5K_RF_BUFFER,
561 { 0x00000060, 0x00000060, 0x00000060 } },
562 { 7, AR5K_RF_BUFFER,
563 { 0x000000f0, 0x000000f0, 0x000000f0 } },
564 { 7, AR5K_RF_BUFFER,
565 { 0x000000a2, 0x000000a2, 0x000000a2 } },
566 { 7, AR5K_RF_BUFFER,
567 { 0x00000052, 0x00000052, 0x00000052 } },
568 { 7, AR5K_RF_BUFFER,
569 { 0x000000d4, 0x000000d4, 0x000000d4 } },
570 { 7, AR5K_RF_BUFFER,
571 { 0x000014cc, 0x000014cc, 0x000014cc } },
572 { 7, AR5K_RF_BUFFER,
573 { 0x0000048c, 0x0000048c, 0x0000048c } },
574 { 7, AR5K_RF_BUFFER_CONTROL_1,
575 { 0x00000003, 0x00000003, 0x00000003 } },
576};
577
578/* RF5413/5414 mode-specific init registers */
579static const struct ath5k_ini_rf rfregs_5413[] = {
580 { 1, 0x98d4,
581 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
582 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
583 { 2, 0x98d0,
584 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
585 { 3, 0x98dc,
586 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
587 { 6, 0x989c,
588 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
589 { 6, 0x989c,
590 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
591 { 6, 0x989c,
592 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
593 { 6, 0x989c,
594 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
595 { 6, 0x989c,
596 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
597 { 6, 0x989c,
598 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
599 { 6, 0x989c,
600 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
601 { 6, 0x989c,
602 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
603 { 6, 0x989c,
604 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
605 { 6, 0x989c,
606 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
607 { 6, 0x989c,
608 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
609 { 6, 0x989c,
610 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
611 { 6, 0x989c,
612 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
613 { 6, 0x989c,
614 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
615 { 6, 0x989c,
616 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
617 { 6, 0x989c,
618 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
619 { 6, 0x989c,
620 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
621 { 6, 0x989c,
622 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
623 { 6, 0x989c,
624 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
625 { 6, 0x989c,
626 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
627 { 6, 0x989c,
628 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
629 { 6, 0x989c,
630 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
631 { 6, 0x989c,
632 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
633 { 6, 0x989c,
634 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
635 { 6, 0x989c,
636 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
637 { 6, 0x989c,
638 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
639 { 6, 0x989c,
640 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
641 { 6, 0x989c,
642 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
643 { 6, 0x989c,
644 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
645 { 6, 0x989c,
646 { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
647 { 6, 0x989c,
648 { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
649 { 6, 0x989c,
650 { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
651 { 6, 0x989c,
652 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
653 { 6, 0x989c,
654 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
655 { 6, 0x989c,
656 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
657 { 6, 0x989c,
658 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
659 { 6, 0x98c8,
660 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
661 { 7, 0x989c,
662 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
663 { 7, 0x989c,
664 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
665 { 7, 0x98cc,
666 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
667};
668
669
670/* Initial RF Gain settings for RF5112 */
671static const struct ath5k_ini_rfgain rfgain_5112[] = {
672 /* 5Ghz 2Ghz */
673 { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
674 { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
675 { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
676 { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } },
677 { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } },
678 { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } },
679 { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } },
680 { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } },
681 { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } },
682 { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } },
683 { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } },
684 { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } },
685 { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } },
686 { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } },
687 { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } },
688 { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } },
689 { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } },
690 { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } },
691 { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } },
692 { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } },
693 { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } },
694 { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } },
695 { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } },
696 { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } },
697 { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } },
698 { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } },
699 { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } },
700 { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } },
701 { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } },
702 { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } },
703 { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } },
704 { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } },
705 { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } },
706 { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } },
707 { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } },
708 { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } },
709 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } },
710 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } },
711 { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } },
712 { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } },
713 { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } },
714 { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } },
715 { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } },
716 { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } },
717 { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } },
718 { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } },
719 { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } },
720 { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } },
721 { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } },
722 { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } },
723 { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } },
724 { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } },
725 { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } },
726 { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } },
727 { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } },
728 { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } },
729 { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } },
730 { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } },
731 { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } },
732 { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } },
733 { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } },
734 { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } },
735 { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } },
736 { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } },
737};
738
739/* Initial RF Gain settings for RF5413 */
740static const struct ath5k_ini_rfgain rfgain_5413[] = {
741 /* 5Ghz 2Ghz */
742 { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
743 { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
744 { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
745 { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } },
746 { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } },
747 { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } },
748 { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } },
749 { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } },
750 { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } },
751 { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } },
752 { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } },
753 { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } },
754 { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } },
755 { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } },
756 { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } },
757 { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } },
758 { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } },
759 { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } },
760 { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } },
761 { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } },
762 { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } },
763 { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } },
764 { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } },
765 { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } },
766 { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } },
767 { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } },
768 { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } },
769 { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } },
770 { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } },
771 { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } },
772 { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } },
773 { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } },
774 { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } },
775 { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } },
776 { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } },
777 { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } },
778 { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } },
779 { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } },
780 { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } },
781 { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } },
782 { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } },
783 { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } },
784 { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } },
785 { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } },
786 { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } },
787 { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } },
788 { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } },
789 { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } },
790 { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } },
791 { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } },
792 { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } },
793 { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } },
794 { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } },
795 { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } },
796 { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } },
797 { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } },
798 { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } },
799 { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } },
800 { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } },
801 { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } },
802 { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } },
803 { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } },
804 { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } },
805 { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
806};
807
808static const struct ath5k_gain_opt rfgain_opt_5112 = {
809 1,
810 8,
811 {
812 { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
813 { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
814 { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
815 { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
816 { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
817 { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
818 { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
819 { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
820 }
821};
822
823/*
824 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
825 */
826static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
827 u32 first, u32 col, bool set)
828{
829 u32 mask, entry, last, data, shift, position;
830 s32 left;
831 int i;
832
833 data = 0;
834
835 if (rf == NULL)
836 /* should not happen */
837 return 0;
838
839 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
840 ATH5K_PRINTF("invalid values at offset %u\n", offset);
841 return 0;
842 }
843
844 entry = ((first - 1) / 8) + offset;
845 position = (first - 1) % 8;
846
847 if (set == true)
848 data = ath5k_hw_bitswap(reg, bits);
849
850 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
851 last = (position + left > 8) ? 8 : position + left;
852 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
853
854 if (set == true) {
855 rf[entry] &= ~mask;
856 rf[entry] |= ((data << position) << (col * 8)) & mask;
857 data >>= (8 - position);
858 } else {
859 data = (((rf[entry] & mask) >> (col * 8)) >> position)
860 << shift;
861 shift += last - position;
862 }
863
864 left -= 8 - position;
865 }
866
867 data = set == true ? 1 : ath5k_hw_bitswap(data, bits);
868
869 return data;
870}
871
872static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
873{
874 u32 mix, step;
875 u32 *rf;
876
877 if (ah->ah_rf_banks == NULL)
878 return 0;
879
880 rf = ah->ah_rf_banks;
881 ah->ah_gain.g_f_corr = 0;
882
883 if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
884 return 0;
885
886 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
887 mix = ah->ah_gain.g_step->gos_param[0];
888
889 switch (mix) {
890 case 3:
891 ah->ah_gain.g_f_corr = step * 2;
892 break;
893 case 2:
894 ah->ah_gain.g_f_corr = (step - 5) * 2;
895 break;
896 case 1:
897 ah->ah_gain.g_f_corr = step;
898 break;
899 default:
900 ah->ah_gain.g_f_corr = 0;
901 break;
902 }
903
904 return ah->ah_gain.g_f_corr;
905}
906
907static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
908{
909 u32 step, mix, level[4];
910 u32 *rf;
911
912 if (ah->ah_rf_banks == NULL)
913 return false;
914
915 rf = ah->ah_rf_banks;
916
917 if (ah->ah_radio == AR5K_RF5111) {
918 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
919 false);
920 level[0] = 0;
921 level[1] = (step == 0x3f) ? 0x32 : step + 4;
922 level[2] = (step != 0x3f) ? 0x40 : level[0];
923 level[3] = level[2] + 0x32;
924
925 ah->ah_gain.g_high = level[3] -
926 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
927 ah->ah_gain.g_low = level[0] +
928 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
929 } else {
930 mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
931 false);
932 level[0] = level[2] = 0;
933
934 if (mix == 1) {
935 level[1] = level[3] = 83;
936 } else {
937 level[1] = level[3] = 107;
938 ah->ah_gain.g_high = 55;
939 }
940 }
941
942 return (ah->ah_gain.g_current >= level[0] &&
943 ah->ah_gain.g_current <= level[1]) ||
944 (ah->ah_gain.g_current >= level[2] &&
945 ah->ah_gain.g_current <= level[3]);
946}
947
948static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
949{
950 const struct ath5k_gain_opt *go;
951 int ret = 0;
952
953 switch (ah->ah_radio) {
954 case AR5K_RF5111:
955 go = &rfgain_opt_5111;
956 break;
957 case AR5K_RF5112:
958 case AR5K_RF5413: /* ??? */
959 go = &rfgain_opt_5112;
960 break;
961 default:
962 return 0;
963 }
964
965 ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
966
967 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
968 if (ah->ah_gain.g_step_idx == 0)
969 return -1;
970 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
971 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
972 ah->ah_gain.g_step_idx > 0;
973 ah->ah_gain.g_step =
974 &go->go_step[ah->ah_gain.g_step_idx])
975 ah->ah_gain.g_target -= 2 *
976 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
977 ah->ah_gain.g_step->gos_gain);
978
979 ret = 1;
980 goto done;
981 }
982
983 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
984 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
985 return -2;
986 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
987 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
988 ah->ah_gain.g_step_idx < go->go_steps_count-1;
989 ah->ah_gain.g_step =
990 &go->go_step[ah->ah_gain.g_step_idx])
991 ah->ah_gain.g_target -= 2 *
992 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
993 ah->ah_gain.g_step->gos_gain);
994
995 ret = 2;
996 goto done;
997 }
998
999done:
1000 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1001 "ret %d, gain step %u, current gain %u, target gain %u\n",
1002 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
1003 ah->ah_gain.g_target);
1004
1005 return ret;
1006}
1007
1008/*
1009 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
1010 */
1011static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1012 struct ieee80211_channel *channel, unsigned int mode)
1013{
1014 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1015 u32 *rf;
1016 const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
1017 unsigned int i;
1018 int obdb = -1, bank = -1;
1019 u32 ee_mode;
1020
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1021 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1022
1023 rf = ah->ah_rf_banks;
1024
1025 /* Copy values to modify them */
1026 for (i = 0; i < rf_size; i++) {
1027 if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
1028 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1029 return -EINVAL;
1030 }
1031
1032 if (bank != rfregs_5111[i].rf_bank) {
1033 bank = rfregs_5111[i].rf_bank;
1034 ah->ah_offset[bank] = i;
1035 }
1036
1037 rf[i] = rfregs_5111[i].rf_value[mode];
1038 }
1039
1040 /* Modify bank 0 */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1041 if (channel->hw_value & CHANNEL_2GHZ) {
1042 if (channel->hw_value & CHANNEL_CCK)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1043 ee_mode = AR5K_EEPROM_MODE_11B;
1044 else
1045 ee_mode = AR5K_EEPROM_MODE_11G;
1046 obdb = 0;
1047
1048 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1049 ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
1050 return -EINVAL;
1051
1052 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1053 ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
1054 return -EINVAL;
1055
1056 obdb = 1;
1057 /* Modify bank 6 */
1058 } else {
1059 /* For 11a, Turbo and XR */
1060 ee_mode = AR5K_EEPROM_MODE_11A;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1061 obdb = channel->center_freq >= 5725 ? 3 :
1062 (channel->center_freq >= 5500 ? 2 :
1063 (channel->center_freq >= 5260 ? 1 :
1064 (channel->center_freq > 4000 ? 0 : -1)));
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1065
1066 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1067 ee->ee_pwd_84, 1, 51, 3, true))
1068 return -EINVAL;
1069
1070 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1071 ee->ee_pwd_90, 1, 45, 3, true))
1072 return -EINVAL;
1073 }
1074
1075 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1076 !ee->ee_xpd[ee_mode], 1, 95, 0, true))
1077 return -EINVAL;
1078
1079 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1080 ee->ee_x_gain[ee_mode], 4, 96, 0, true))
1081 return -EINVAL;
1082
1083 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1084 ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
1085 return -EINVAL;
1086
1087 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1088 ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
1089 return -EINVAL;
1090
1091 /* Modify bank 7 */
1092 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1093 ee->ee_i_gain[ee_mode], 6, 29, 0, true))
1094 return -EINVAL;
1095
1096 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1097 ee->ee_xpd[ee_mode], 1, 4, 0, true))
1098 return -EINVAL;
1099
1100 /* Write RF values */
1101 for (i = 0; i < rf_size; i++) {
1102 AR5K_REG_WAIT(i);
1103 ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
1104 }
1105
1106 return 0;
1107}
1108
1109/*
1110 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
1111 */
1112static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1113 struct ieee80211_channel *channel, unsigned int mode)
1114{
1115 const struct ath5k_ini_rf *rf_ini;
1116 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1117 u32 *rf;
1118 unsigned int rf_size, i;
1119 int obdb = -1, bank = -1;
1120 u32 ee_mode;
1121
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1122 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1123
1124 rf = ah->ah_rf_banks;
1125
1126 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1127 && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1128 rf_ini = rfregs_2112a;
1129 rf_size = ARRAY_SIZE(rfregs_5112a);
1130 if (mode < 2) {
1131 ATH5K_ERR(ah->ah_sc,"invalid channel mode: %i\n",mode);
1132 return -EINVAL;
1133 }
1134 mode = mode - 2; /*no a/turboa modes for 2112*/
1135 } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1136 rf_ini = rfregs_5112a;
1137 rf_size = ARRAY_SIZE(rfregs_5112a);
1138 } else {
1139 rf_ini = rfregs_5112;
1140 rf_size = ARRAY_SIZE(rfregs_5112);
1141 }
1142
1143 /* Copy values to modify them */
1144 for (i = 0; i < rf_size; i++) {
1145 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1146 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1147 return -EINVAL;
1148 }
1149
1150 if (bank != rf_ini[i].rf_bank) {
1151 bank = rf_ini[i].rf_bank;
1152 ah->ah_offset[bank] = i;
1153 }
1154
1155 rf[i] = rf_ini[i].rf_value[mode];
1156 }
1157
1158 /* Modify bank 6 */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1159 if (channel->hw_value & CHANNEL_2GHZ) {
1160 if (channel->hw_value & CHANNEL_OFDM)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1161 ee_mode = AR5K_EEPROM_MODE_11G;
1162 else
1163 ee_mode = AR5K_EEPROM_MODE_11B;
1164 obdb = 0;
1165
1166 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1167 ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
1168 return -EINVAL;
1169
1170 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1171 ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
1172 return -EINVAL;
1173 } else {
1174 /* For 11a, Turbo and XR */
1175 ee_mode = AR5K_EEPROM_MODE_11A;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1176 obdb = channel->center_freq >= 5725 ? 3 :
1177 (channel->center_freq >= 5500 ? 2 :
1178 (channel->center_freq >= 5260 ? 1 :
1179 (channel->center_freq > 4000 ? 0 : -1)));
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1180
Luis R. Rodrigueze71c9fa2008-02-03 21:53:51 -0500[diff] [blame^]1181 if (obdb == -1)
1182 return -EINVAL;
1183
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1184 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1185 ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
1186 return -EINVAL;
1187
1188 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1189 ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
1190 return -EINVAL;
1191 }
1192
1193 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1194 ee->ee_x_gain[ee_mode], 2, 270, 0, true);
1195 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1196 ee->ee_x_gain[ee_mode], 2, 257, 0, true);
1197
1198 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1199 ee->ee_xpd[ee_mode], 1, 302, 0, true))
1200 return -EINVAL;
1201
1202 /* Modify bank 7 */
1203 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1204 ee->ee_i_gain[ee_mode], 6, 14, 0, true))
1205 return -EINVAL;
1206
1207 /* Write RF values */
1208 for (i = 0; i < rf_size; i++)
1209 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1210
1211 return 0;
1212}
1213
1214/*
1215 * Initialize RF5413/5414
1216 */
1217static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1218 struct ieee80211_channel *channel, unsigned int mode)
1219{
1220 const struct ath5k_ini_rf *rf_ini;
1221 u32 *rf;
1222 unsigned int rf_size, i;
1223 int bank = -1;
1224
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1225 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1226
1227 rf = ah->ah_rf_banks;
1228
1229 rf_ini = rfregs_5413;
1230 rf_size = ARRAY_SIZE(rfregs_5413);
1231
1232 /* Copy values to modify them */
1233 for (i = 0; i < rf_size; i++) {
1234 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1235 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1236 return -EINVAL;
1237 }
1238
1239 if (bank != rf_ini[i].rf_bank) {
1240 bank = rf_ini[i].rf_bank;
1241 ah->ah_offset[bank] = i;
1242 }
1243
1244 rf[i] = rf_ini[i].rf_value[mode];
1245 }
1246
1247 /*
1248 * After compairing dumps from different cards
1249 * we get the same RF_BUFFER settings (diff returns
1250 * 0 lines). It seems that RF_BUFFER settings are static
1251 * and are written unmodified (no EEPROM stuff
1252 * is used because calibration data would be
1253 * different between different cards and would result
1254 * different RF_BUFFER settings)
1255 */
1256
1257 /* Write RF values */
1258 for (i = 0; i < rf_size; i++)
1259 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1260
1261 return 0;
1262}
1263
1264/*
1265 * Initialize RF
1266 */
1267int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1268 unsigned int mode)
1269{
1270 int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
1271 int ret;
1272
1273 switch (ah->ah_radio) {
1274 case AR5K_RF5111:
1275 ah->ah_rf_banks_size = sizeof(rfregs_5111);
1276 func = ath5k_hw_rf5111_rfregs;
1277 break;
1278 case AR5K_RF5112:
1279 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
1280 ah->ah_rf_banks_size = sizeof(rfregs_5112a);
1281 else
1282 ah->ah_rf_banks_size = sizeof(rfregs_5112);
1283 func = ath5k_hw_rf5112_rfregs;
1284 break;
1285 case AR5K_RF5413:
1286 ah->ah_rf_banks_size = sizeof(rfregs_5413);
1287 func = ath5k_hw_rf5413_rfregs;
1288 break;
1289 default:
1290 return -EINVAL;
1291 }
1292
1293 if (ah->ah_rf_banks == NULL) {
1294 /* XXX do extra checks? */
1295 ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
1296 if (ah->ah_rf_banks == NULL) {
1297 ATH5K_ERR(ah->ah_sc, "out of memory\n");
1298 return -ENOMEM;
1299 }
1300 }
1301
1302 ret = func(ah, channel, mode);
1303 if (!ret)
1304 ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
1305
1306 return ret;
1307}
1308
1309int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
1310{
1311 const struct ath5k_ini_rfgain *ath5k_rfg;
1312 unsigned int i, size;
1313
1314 switch (ah->ah_radio) {
1315 case AR5K_RF5111:
1316 ath5k_rfg = rfgain_5111;
1317 size = ARRAY_SIZE(rfgain_5111);
1318 break;
1319 case AR5K_RF5112:
1320 ath5k_rfg = rfgain_5112;
1321 size = ARRAY_SIZE(rfgain_5112);
1322 break;
1323 case AR5K_RF5413:
1324 ath5k_rfg = rfgain_5413;
1325 size = ARRAY_SIZE(rfgain_5413);
1326 break;
1327 default:
1328 return -EINVAL;
1329 }
1330
1331 switch (freq) {
1332 case AR5K_INI_RFGAIN_2GHZ:
1333 case AR5K_INI_RFGAIN_5GHZ:
1334 break;
1335 default:
1336 return -EINVAL;
1337 }
1338
1339 for (i = 0; i < size; i++) {
1340 AR5K_REG_WAIT(i);
1341 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
1342 (u32)ath5k_rfg[i].rfg_register);
1343 }
1344
1345 return 0;
1346}
1347
1348enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
1349{
1350 u32 data, type;
1351
1352 ATH5K_TRACE(ah->ah_sc);
1353
1354 if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
1355 ah->ah_version <= AR5K_AR5211)
1356 return AR5K_RFGAIN_INACTIVE;
1357
1358 if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
1359 goto done;
1360
1361 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
1362
1363 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
1364 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
1365 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
1366
1367 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
1368 ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
1369
1370 if (ah->ah_radio >= AR5K_RF5112) {
1371 ath5k_hw_rfregs_gainf_corr(ah);
1372 ah->ah_gain.g_current =
1373 ah->ah_gain.g_current>=ah->ah_gain.g_f_corr ?
1374 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
1375 0;
1376 }
1377
1378 if (ath5k_hw_rfregs_gain_readback(ah) &&
1379 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
1380 ath5k_hw_rfregs_gain_adjust(ah))
1381 ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
1382 }
1383
1384done:
1385 return ah->ah_rf_gain;
1386}
1387
1388int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
1389{
1390 /* Initialize the gain optimization values */
1391 switch (ah->ah_radio) {
1392 case AR5K_RF5111:
1393 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
1394 ah->ah_gain.g_step =
1395 &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
1396 ah->ah_gain.g_low = 20;
1397 ah->ah_gain.g_high = 35;
1398 ah->ah_gain.g_active = 1;
1399 break;
1400 case AR5K_RF5112:
1401 case AR5K_RF5413: /* ??? */
1402 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
1403 ah->ah_gain.g_step =
1404 &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
1405 ah->ah_gain.g_low = 20;
1406 ah->ah_gain.g_high = 85;
1407 ah->ah_gain.g_active = 1;
1408 break;
1409 default:
1410 return -EINVAL;
1411 }
1412
1413 return 0;
1414}
1415
1416/**************************\
1417 PHY/RF channel functions
1418\**************************/
1419
1420/*
1421 * Check if a channel is supported
1422 */
1423bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
1424{
1425 /* Check if the channel is in our supported range */
1426 if (flags & CHANNEL_2GHZ) {
1427 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
1428 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
1429 return true;
1430 } else if (flags & CHANNEL_5GHZ)
1431 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
1432 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
1433 return true;
1434
1435 return false;
1436}
1437
1438/*
1439 * Convertion needed for RF5110
1440 */
1441static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1442{
1443 u32 athchan;
1444
1445 /*
1446 * Convert IEEE channel/MHz to an internal channel value used
1447 * by the AR5210 chipset. This has not been verified with
1448 * newer chipsets like the AR5212A who have a completely
1449 * different RF/PHY part.
1450 */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1451 athchan = (ath5k_hw_bitswap(
1452 (ieee80211_frequency_to_channel(
1453 channel->center_freq) - 24) / 2, 5)
1454 << 1) | (1 << 6) | 0x1;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1455 return athchan;
1456}
1457
1458/*
1459 * Set channel on RF5110
1460 */
1461static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1462 struct ieee80211_channel *channel)
1463{
1464 u32 data;
1465
1466 /*
1467 * Set the channel and wait
1468 */
1469 data = ath5k_hw_rf5110_chan2athchan(channel);
1470 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1471 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1472 mdelay(1);
1473
1474 return 0;
1475}
1476
1477/*
1478 * Convertion needed for 5111
1479 */
1480static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1481 struct ath5k_athchan_2ghz *athchan)
1482{
1483 int channel;
1484
1485 /* Cast this value to catch negative channel numbers (>= -19) */
1486 channel = (int)ieee;
1487
1488 /*
1489 * Map 2GHz IEEE channel to 5GHz Atheros channel
1490 */
1491 if (channel <= 13) {
1492 athchan->a2_athchan = 115 + channel;
1493 athchan->a2_flags = 0x46;
1494 } else if (channel == 14) {
1495 athchan->a2_athchan = 124;
1496 athchan->a2_flags = 0x44;
1497 } else if (channel >= 15 && channel <= 26) {
1498 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1499 athchan->a2_flags = 0x46;
1500 } else
1501 return -EINVAL;
1502
1503 return 0;
1504}
1505
1506/*
1507 * Set channel on 5111
1508 */
1509static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1510 struct ieee80211_channel *channel)
1511{
1512 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1513 unsigned int ath5k_channel =
1514 ieee80211_frequency_to_channel(channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1515 u32 data0, data1, clock;
1516 int ret;
1517
1518 /*
1519 * Set the channel on the RF5111 radio
1520 */
1521 data0 = data1 = 0;
1522
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1523 if (channel->hw_value & CHANNEL_2GHZ) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1524 /* Map 2GHz channel to 5GHz Atheros channel ID */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1525 ret = ath5k_hw_rf5111_chan2athchan(
1526 ieee80211_frequency_to_channel(channel->center_freq),
1527 &ath5k_channel_2ghz);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1528 if (ret)
1529 return ret;
1530
1531 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1532 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1533 << 5) | (1 << 4);
1534 }
1535
1536 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1537 clock = 1;
1538 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1539 (clock << 1) | (1 << 10) | 1;
1540 } else {
1541 clock = 0;
1542 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1543 << 2) | (clock << 1) | (1 << 10) | 1;
1544 }
1545
1546 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1547 AR5K_RF_BUFFER);
1548 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1549 AR5K_RF_BUFFER_CONTROL_3);
1550
1551 return 0;
1552}
1553
1554/*
1555 * Set channel on 5112 and newer
1556 */
1557static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1558 struct ieee80211_channel *channel)
1559{
1560 u32 data, data0, data1, data2;
1561 u16 c;
1562
1563 data = data0 = data1 = data2 = 0;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1564 c = channel->center_freq;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1565
1566 /*
1567 * Set the channel on the RF5112 or newer
1568 */
1569 if (c < 4800) {
1570 if (!((c - 2224) % 5)) {
1571 data0 = ((2 * (c - 704)) - 3040) / 10;
1572 data1 = 1;
1573 } else if (!((c - 2192) % 5)) {
1574 data0 = ((2 * (c - 672)) - 3040) / 10;
1575 data1 = 0;
1576 } else
1577 return -EINVAL;
1578
1579 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1580 } else {
1581 if (!(c % 20) && c >= 5120) {
1582 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1583 data2 = ath5k_hw_bitswap(3, 2);
1584 } else if (!(c % 10)) {
1585 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1586 data2 = ath5k_hw_bitswap(2, 2);
1587 } else if (!(c % 5)) {
1588 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1589 data2 = ath5k_hw_bitswap(1, 2);
1590 } else
1591 return -EINVAL;
1592 }
1593
1594 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1595
1596 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1597 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1598
1599 return 0;
1600}
1601
1602/*
1603 * Set a channel on the radio chip
1604 */
1605int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1606{
1607 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1608 /*
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1609 * Check bounds supported by the PHY (we don't care about regultory
1610 * restrictions at this point). Note: hw_value already has the band
1611 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1612 * of the band by that */
1613 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1614 ATH5K_ERR(ah->ah_sc,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1615 "channel frequency (%u MHz) out of supported "
1616 "band range\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1617 channel->center_freq);
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1618 return -EINVAL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1619 }
1620
1621 /*
1622 * Set the channel and wait
1623 */
1624 switch (ah->ah_radio) {
1625 case AR5K_RF5110:
1626 ret = ath5k_hw_rf5110_channel(ah, channel);
1627 break;
1628 case AR5K_RF5111:
1629 ret = ath5k_hw_rf5111_channel(ah, channel);
1630 break;
1631 default:
1632 ret = ath5k_hw_rf5112_channel(ah, channel);
1633 break;
1634 }
1635
1636 if (ret)
1637 return ret;
1638
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1639 ah->ah_current_channel.center_freq = channel->center_freq;
1640 ah->ah_current_channel.hw_value = channel->hw_value;
1641 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1642
1643 return 0;
1644}
1645
1646/*****************\
1647 PHY calibration
1648\*****************/
1649
1650/**
1651 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
1652 *
1653 * @ah: struct ath5k_hw pointer we are operating on
1654 * @freq: the channel frequency, just used for error logging
1655 *
1656 * This function performs a noise floor calibration of the PHY and waits for
1657 * it to complete. Then the noise floor value is compared to some maximum
1658 * noise floor we consider valid.
1659 *
1660 * Note that this is different from what the madwifi HAL does: it reads the
1661 * noise floor and afterwards initiates the calibration. Since the noise floor
1662 * calibration can take some time to finish, depending on the current channel
1663 * use, that avoids the occasional timeout warnings we are seeing now.
1664 *
1665 * See the following link for an Atheros patent on noise floor calibration:
1666 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
1667 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
1668 *
1669 */
1670int
1671ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
1672{
1673 int ret;
1674 unsigned int i;
1675 s32 noise_floor;
1676
1677 /*
1678 * Enable noise floor calibration and wait until completion
1679 */
1680 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1681 AR5K_PHY_AGCCTL_NF);
1682
1683 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1684 AR5K_PHY_AGCCTL_NF, 0, false);
1685 if (ret) {
1686 ATH5K_ERR(ah->ah_sc,
1687 "noise floor calibration timeout (%uMHz)\n", freq);
1688 return ret;
1689 }
1690
1691 /* Wait until the noise floor is calibrated and read the value */
1692 for (i = 20; i > 0; i--) {
1693 mdelay(1);
1694 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1695 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
1696 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
1697 noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
1698
1699 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
1700 break;
1701 }
1702 }
1703
1704 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1705 "noise floor %d\n", noise_floor);
1706
1707 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
1708 ATH5K_ERR(ah->ah_sc,
1709 "noise floor calibration failed (%uMHz)\n", freq);
1710 return -EIO;
1711 }
1712
1713 ah->ah_noise_floor = noise_floor;
1714
1715 return 0;
1716}
1717
1718/*
1719 * Perform a PHY calibration on RF5110
1720 * -Fix BPSK/QAM Constellation (I/Q correction)
1721 * -Calculate Noise Floor
1722 */
1723static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1724 struct ieee80211_channel *channel)
1725{
1726 u32 phy_sig, phy_agc, phy_sat, beacon;
1727 int ret;
1728
1729 /*
1730 * Disable beacons and RX/TX queues, wait
1731 */
1732 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1733 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1734 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1735 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1736
1737 udelay(2300);
1738
1739 /*
1740 * Set the channel (with AGC turned off)
1741 */
1742 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1743 udelay(10);
1744 ret = ath5k_hw_channel(ah, channel);
1745
1746 /*
1747 * Activate PHY and wait
1748 */
1749 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1750 mdelay(1);
1751
1752 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1753
1754 if (ret)
1755 return ret;
1756
1757 /*
1758 * Calibrate the radio chip
1759 */
1760
1761 /* Remember normal state */
1762 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1763 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1764 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1765
1766 /* Update radio registers */
1767 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1768 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1769
1770 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1771 AR5K_PHY_AGCCOARSE_LO)) |
1772 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1773 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1774
1775 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1776 AR5K_PHY_ADCSAT_THR)) |
1777 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1778 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1779
1780 udelay(20);
1781
1782 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1783 udelay(10);
1784 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1785 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1786
1787 mdelay(1);
1788
1789 /*
1790 * Enable calibration and wait until completion
1791 */
1792 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1793
1794 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1795 AR5K_PHY_AGCCTL_CAL, 0, false);
1796
1797 /* Reset to normal state */
1798 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1799 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1800 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1801
1802 if (ret) {
1803 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1804 channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1805 return ret;
1806 }
1807
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1808 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1809 if (ret)
1810 return ret;
1811
1812 /*
1813 * Re-enable RX/TX and beacons
1814 */
1815 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1816 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1817 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1818
1819 return 0;
1820}
1821
1822/*
1823 * Perform a PHY calibration on RF5111/5112
1824 */
1825static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1826 struct ieee80211_channel *channel)
1827{
1828 u32 i_pwr, q_pwr;
1829 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1830 ATH5K_TRACE(ah->ah_sc);
1831
1832 if (ah->ah_calibration == false ||
1833 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1834 goto done;
1835
1836 ah->ah_calibration = false;
1837
1838 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1839 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1840 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1841 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1842 q_coffd = q_pwr >> 6;
1843
1844 if (i_coffd == 0 || q_coffd == 0)
1845 goto done;
1846
1847 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
1848 q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f;
1849
1850 /* Commit new IQ value */
1851 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
1852 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
1853
1854done:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1855 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1856
1857 /* Request RF gain */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1858 if (channel->hw_value & CHANNEL_5GHZ) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1859 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
1860 AR5K_PHY_PAPD_PROBE_TXPOWER) |
1861 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
1862 ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
1863 }
1864
1865 return 0;
1866}
1867
1868/*
1869 * Perform a PHY calibration
1870 */
1871int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1872 struct ieee80211_channel *channel)
1873{
1874 int ret;
1875
1876 if (ah->ah_radio == AR5K_RF5110)
1877 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1878 else
1879 ret = ath5k_hw_rf511x_calibrate(ah, channel);
1880
1881 return ret;
1882}
1883
1884int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1885{
1886 ATH5K_TRACE(ah->ah_sc);
1887 /*Just a try M.F.*/
1888 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1889
1890 return 0;
1891}
1892
1893/********************\
1894 Misc PHY functions
1895\********************/
1896
1897/*
1898 * Get the PHY Chip revision
1899 */
1900u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1901{
1902 unsigned int i;
1903 u32 srev;
1904 u16 ret;
1905
1906 ATH5K_TRACE(ah->ah_sc);
1907
1908 /*
1909 * Set the radio chip access register
1910 */
1911 switch (chan) {
1912 case CHANNEL_2GHZ:
1913 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1914 break;
1915 case CHANNEL_5GHZ:
1916 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1917 break;
1918 default:
1919 return 0;
1920 }
1921
1922 mdelay(2);
1923
1924 /* ...wait until PHY is ready and read the selected radio revision */
1925 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1926
1927 for (i = 0; i < 8; i++)
1928 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1929
1930 if (ah->ah_version == AR5K_AR5210) {
1931 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1932 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1933 } else {
1934 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1935 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1936 ((srev & 0x0f) << 4), 8);
1937 }
1938
1939 /* Reset to the 5GHz mode */
1940 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1941
1942 return ret;
1943}
1944
1945void /*TODO:Boundary check*/
1946ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
1947{
1948 ATH5K_TRACE(ah->ah_sc);
1949 /*Just a try M.F.*/
1950 if (ah->ah_version != AR5K_AR5210)
1951 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
1952}
1953
1954unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
1955{
1956 ATH5K_TRACE(ah->ah_sc);
1957 /*Just a try M.F.*/
1958 if (ah->ah_version != AR5K_AR5210)
1959 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
1960
1961 return false; /*XXX: What do we return for 5210 ?*/
1962}
1963
1964/*
1965 * TX power setup
1966 */
1967
1968/*
1969 * Initialize the tx power table (not fully implemented)
1970 */
1971static void ath5k_txpower_table(struct ath5k_hw *ah,
1972 struct ieee80211_channel *channel, s16 max_power)
1973{
1974 unsigned int i, min, max, n;
1975 u16 txpower, *rates;
1976
1977 rates = ah->ah_txpower.txp_rates;
1978
1979 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
1980 if (max_power > txpower)
1981 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
1982 AR5K_TUNE_MAX_TXPOWER : max_power;
1983
1984 for (i = 0; i < AR5K_MAX_RATES; i++)
1985 rates[i] = txpower;
1986
1987 /* XXX setup target powers by rate */
1988
1989 ah->ah_txpower.txp_min = rates[7];
1990 ah->ah_txpower.txp_max = rates[0];
1991 ah->ah_txpower.txp_ofdm = rates[0];
1992
1993 /* Calculate the power table */
1994 n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
1995 min = AR5K_EEPROM_PCDAC_START;
1996 max = AR5K_EEPROM_PCDAC_STOP;
1997 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
1998 ah->ah_txpower.txp_pcdac[i] =
1999#ifdef notyet
2000 min + ((i * (max - min)) / n);
2001#else
2002 min;
2003#endif
2004}
2005
2006/*
2007 * Set transmition power
2008 */
2009int /*O.K. - txpower_table is unimplemented so this doesn't work*/
2010ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2011 unsigned int txpower)
2012{
2013 bool tpc = ah->ah_txpower.txp_tpc;
2014 unsigned int i;
2015
2016 ATH5K_TRACE(ah->ah_sc);
2017 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2018 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2019 return -EINVAL;
2020 }
2021
2022 /* Reset TX power values */
2023 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2024 ah->ah_txpower.txp_tpc = tpc;
2025
2026 /* Initialize TX power table */
2027 ath5k_txpower_table(ah, channel, txpower);
2028
2029 /*
2030 * Write TX power values
2031 */
2032 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2033 ath5k_hw_reg_write(ah,
2034 ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
2035 (((ah->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff),
2036 AR5K_PHY_PCDAC_TXPOWER(i));
2037 }
2038
2039 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2040 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2041 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2042
2043 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2044 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2045 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2046
2047 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2048 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2049 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2050
2051 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2052 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2053 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2054
2055 if (ah->ah_txpower.txp_tpc == true)
2056 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2057 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2058 else
2059 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
2060 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2061
2062 return 0;
2063}
2064
2065int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
2066{
2067 /*Just a try M.F.*/
2068 struct ieee80211_channel *channel = &ah->ah_current_channel;
2069
2070 ATH5K_TRACE(ah->ah_sc);
2071 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
2072 "changing txpower to %d\n", power);
2073
2074 return ath5k_hw_txpower(ah, channel, power);
2075}