Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2007 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Eric Anholt <eric@anholt.net> |
| 27 | */ |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/delay.h> |
| 31 | #include "drmP.h" |
| 32 | #include "drm.h" |
| 33 | #include "drm_crtc.h" |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 34 | #include "drm_edid.h" |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 35 | #include "intel_drv.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "i915_drm.h" |
| 37 | #include "i915_drv.h" |
| 38 | #include "intel_sdvo_regs.h" |
| 39 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 40 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
| 41 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
| 42 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
| 43 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) |
| 44 | |
| 45 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
| 46 | SDVO_TV_MASK) |
| 47 | |
| 48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
| 49 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
| 50 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 51 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 52 | static char *tv_format_names[] = { |
| 53 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
| 54 | "PAL_B" , "PAL_D" , "PAL_G" , |
| 55 | "PAL_H" , "PAL_I" , "PAL_M" , |
| 56 | "PAL_N" , "PAL_NC" , "PAL_60" , |
| 57 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
| 58 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
| 59 | "SECAM_60" |
| 60 | }; |
| 61 | |
| 62 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
| 63 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 64 | struct intel_sdvo { |
| 65 | struct intel_encoder base; |
| 66 | |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 67 | u8 slave_addr; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 68 | |
| 69 | /* Register for the SDVO device: SDVOB or SDVOC */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 70 | int sdvo_reg; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 71 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 72 | /* Active outputs controlled by this SDVO output */ |
| 73 | uint16_t controlled_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 74 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 75 | /* |
| 76 | * Capabilities of the SDVO device returned by |
| 77 | * i830_sdvo_get_capabilities() |
| 78 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 79 | struct intel_sdvo_caps caps; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 80 | |
| 81 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 82 | int pixel_clock_min, pixel_clock_max; |
| 83 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 84 | /* |
| 85 | * For multiple function SDVO device, |
| 86 | * this is for current attached outputs. |
| 87 | */ |
| 88 | uint16_t attached_output; |
| 89 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 90 | /** |
| 91 | * This is set if we're going to treat the device as TV-out. |
| 92 | * |
| 93 | * While we have these nice friendly flags for output types that ought |
| 94 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
| 95 | * shows up as RGB1 (VGA). |
| 96 | */ |
| 97 | bool is_tv; |
| 98 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 99 | /* This is for current tv format name */ |
| 100 | char *tv_format_name; |
| 101 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 102 | /** |
| 103 | * This is set if we treat the device as HDMI, instead of DVI. |
| 104 | */ |
| 105 | bool is_hdmi; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 106 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 107 | /** |
| 108 | * This is set if we detect output of sdvo device as LVDS. |
| 109 | */ |
| 110 | bool is_lvds; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 111 | |
| 112 | /** |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 113 | * This is sdvo flags for input timing. |
| 114 | */ |
| 115 | uint8_t sdvo_flags; |
| 116 | |
| 117 | /** |
| 118 | * This is sdvo fixed pannel mode pointer |
| 119 | */ |
| 120 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
| 121 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 122 | /* |
| 123 | * supported encoding mode, used to determine whether HDMI is |
| 124 | * supported |
| 125 | */ |
| 126 | struct intel_sdvo_encode encode; |
| 127 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 128 | /* DDC bus used by this SDVO encoder */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 129 | uint8_t ddc_bus; |
| 130 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 131 | /* Mac mini hack -- use the same DDC as the analog connector */ |
| 132 | struct i2c_adapter *analog_ddc_bus; |
| 133 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | struct intel_sdvo_connector { |
| 137 | /* Mark the type of connector */ |
| 138 | uint16_t output_flag; |
| 139 | |
| 140 | /* This contains all current supported TV format */ |
| 141 | char *tv_format_supported[TV_FORMAT_NUM]; |
| 142 | int format_supported_num; |
| 143 | struct drm_property *tv_format_property; |
| 144 | struct drm_property *tv_format_name_property[TV_FORMAT_NUM]; |
| 145 | |
| 146 | /** |
| 147 | * Returned SDTV resolutions allowed for the current format, if the |
| 148 | * device reported it. |
| 149 | */ |
| 150 | struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions; |
| 151 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 152 | /* add the property for the SDVO-TV */ |
| 153 | struct drm_property *left_property; |
| 154 | struct drm_property *right_property; |
| 155 | struct drm_property *top_property; |
| 156 | struct drm_property *bottom_property; |
| 157 | struct drm_property *hpos_property; |
| 158 | struct drm_property *vpos_property; |
| 159 | |
| 160 | /* add the property for the SDVO-TV/LVDS */ |
| 161 | struct drm_property *brightness_property; |
| 162 | struct drm_property *contrast_property; |
| 163 | struct drm_property *saturation_property; |
| 164 | struct drm_property *hue_property; |
| 165 | |
| 166 | /* Add variable to record current setting for the above property */ |
| 167 | u32 left_margin, right_margin, top_margin, bottom_margin; |
| 168 | /* this is to get the range of margin.*/ |
| 169 | u32 max_hscan, max_vscan; |
| 170 | u32 max_hpos, cur_hpos; |
| 171 | u32 max_vpos, cur_vpos; |
| 172 | u32 cur_brightness, max_brightness; |
| 173 | u32 cur_contrast, max_contrast; |
| 174 | u32 cur_saturation, max_saturation; |
| 175 | u32 cur_hue, max_hue; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 176 | }; |
| 177 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 178 | static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder) |
| 179 | { |
| 180 | return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base); |
| 181 | } |
| 182 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 183 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 184 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 185 | static void |
| 186 | intel_sdvo_tv_create_property(struct drm_connector *connector, int type); |
| 187 | static void |
| 188 | intel_sdvo_create_enhance_property(struct drm_connector *connector); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 189 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 190 | /** |
| 191 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
| 192 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
| 193 | * comments in the BIOS). |
| 194 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 195 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 196 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 197 | struct drm_device *dev = intel_sdvo->base.enc.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 198 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 199 | u32 bval = val, cval = val; |
| 200 | int i; |
| 201 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 202 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
| 203 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
| 204 | I915_READ(intel_sdvo->sdvo_reg); |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 205 | return; |
| 206 | } |
| 207 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 208 | if (intel_sdvo->sdvo_reg == SDVOB) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 209 | cval = I915_READ(SDVOC); |
| 210 | } else { |
| 211 | bval = I915_READ(SDVOB); |
| 212 | } |
| 213 | /* |
| 214 | * Write the registers twice for luck. Sometimes, |
| 215 | * writing them only once doesn't appear to 'stick'. |
| 216 | * The BIOS does this too. Yay, magic |
| 217 | */ |
| 218 | for (i = 0; i < 2; i++) |
| 219 | { |
| 220 | I915_WRITE(SDVOB, bval); |
| 221 | I915_READ(SDVOB); |
| 222 | I915_WRITE(SDVOC, cval); |
| 223 | I915_READ(SDVOC); |
| 224 | } |
| 225 | } |
| 226 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 227 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 228 | u8 *ch) |
| 229 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 230 | u8 out_buf[2]; |
| 231 | u8 buf[2]; |
| 232 | int ret; |
| 233 | |
| 234 | struct i2c_msg msgs[] = { |
| 235 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 236 | .addr = intel_sdvo->slave_addr >> 1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 237 | .flags = 0, |
| 238 | .len = 1, |
| 239 | .buf = out_buf, |
| 240 | }, |
| 241 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 242 | .addr = intel_sdvo->slave_addr >> 1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 243 | .flags = I2C_M_RD, |
| 244 | .len = 1, |
| 245 | .buf = buf, |
| 246 | } |
| 247 | }; |
| 248 | |
| 249 | out_buf[0] = addr; |
| 250 | out_buf[1] = 0; |
| 251 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 252 | if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 253 | { |
| 254 | *ch = buf[0]; |
| 255 | return true; |
| 256 | } |
| 257 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 258 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 259 | return false; |
| 260 | } |
| 261 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 262 | static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 263 | u8 ch) |
| 264 | { |
| 265 | u8 out_buf[2]; |
| 266 | struct i2c_msg msgs[] = { |
| 267 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 268 | .addr = intel_sdvo->slave_addr >> 1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 269 | .flags = 0, |
| 270 | .len = 2, |
| 271 | .buf = out_buf, |
| 272 | } |
| 273 | }; |
| 274 | |
| 275 | out_buf[0] = addr; |
| 276 | out_buf[1] = ch; |
| 277 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 278 | if (i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 279 | { |
| 280 | return true; |
| 281 | } |
| 282 | return false; |
| 283 | } |
| 284 | |
| 285 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
| 286 | /** Mapping of command numbers to names, for debug output */ |
Tobias Klauser | 005568b | 2009-02-09 22:02:42 +0100 | [diff] [blame] | 287 | static const struct _sdvo_cmd_name { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 288 | u8 cmd; |
| 289 | char *name; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 290 | } sdvo_cmd_names[] = { |
| 291 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
| 292 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
| 293 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
| 294 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
| 295 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
| 296 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
| 297 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
| 298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
| 299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
| 300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
| 301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
| 302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
| 303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
| 304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
| 305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
| 306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
| 307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
| 308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
| 310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
| 312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
| 313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
| 314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
| 315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
| 316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
| 317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
| 318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
| 319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
| 320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
| 321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
| 322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
| 323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
| 324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
| 325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
| 327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
| 328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
| 329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
| 332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
| 333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 334 | /* Add the op code for SDVO enhancements */ |
| 335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H), |
| 336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H), |
| 337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H), |
| 338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V), |
| 339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V), |
| 340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V), |
| 341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
| 342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
| 343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
| 344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
| 345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
| 346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
| 347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
| 348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
| 349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
| 350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
| 351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
| 352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
| 353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
| 354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
| 355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
| 356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
| 357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
| 358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 359 | /* HDMI op code */ |
| 360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
| 361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
| 362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
| 363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
| 364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
| 365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
| 366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
| 367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
| 368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
| 369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
| 370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
| 371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
| 372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
| 373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
| 374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
| 375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
| 376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
| 377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
| 378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
| 379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 380 | }; |
| 381 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 382 | #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 383 | #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 384 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 385 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 386 | void *args, int args_len) |
| 387 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 388 | int i; |
| 389 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 390 | DRM_DEBUG_KMS("%s: W: %02X ", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 391 | SDVO_NAME(intel_sdvo), cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 392 | for (i = 0; i < args_len; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 393 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 394 | for (; i < 8; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 395 | DRM_LOG_KMS(" "); |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 396 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 397 | if (cmd == sdvo_cmd_names[i].cmd) { |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 398 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 399 | break; |
| 400 | } |
| 401 | } |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 402 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 403 | DRM_LOG_KMS("(%02X)", cmd); |
| 404 | DRM_LOG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 405 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 406 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 407 | static void intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 408 | void *args, int args_len) |
| 409 | { |
| 410 | int i; |
| 411 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 412 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 413 | |
| 414 | for (i = 0; i < args_len; i++) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 415 | intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 416 | ((u8*)args)[i]); |
| 417 | } |
| 418 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 419 | intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 420 | } |
| 421 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 422 | static const char *cmd_status_names[] = { |
| 423 | "Power on", |
| 424 | "Success", |
| 425 | "Not supported", |
| 426 | "Invalid arg", |
| 427 | "Pending", |
| 428 | "Target not specified", |
| 429 | "Scaling not supported" |
| 430 | }; |
| 431 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 432 | static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 433 | void *response, int response_len, |
| 434 | u8 status) |
| 435 | { |
Zhenyu Wang | 33b5296 | 2009-03-24 14:02:40 +0800 | [diff] [blame] | 436 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 437 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 438 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 439 | for (i = 0; i < response_len; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 440 | DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 441 | for (; i < 8; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 442 | DRM_LOG_KMS(" "); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 443 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 444 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 445 | else |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 446 | DRM_LOG_KMS("(??? %d)", status); |
| 447 | DRM_LOG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 448 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 449 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 450 | static u8 intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 451 | void *response, int response_len) |
| 452 | { |
| 453 | int i; |
| 454 | u8 status; |
| 455 | u8 retry = 50; |
| 456 | |
| 457 | while (retry--) { |
| 458 | /* Read the command response */ |
| 459 | for (i = 0; i < response_len; i++) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 460 | intel_sdvo_read_byte(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 461 | SDVO_I2C_RETURN_0 + i, |
| 462 | &((u8 *)response)[i]); |
| 463 | } |
| 464 | |
| 465 | /* read the return status */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 466 | intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 467 | &status); |
| 468 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 469 | intel_sdvo_debug_response(intel_sdvo, response, response_len, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 470 | status); |
| 471 | if (status != SDVO_CMD_STATUS_PENDING) |
| 472 | return status; |
| 473 | |
| 474 | mdelay(50); |
| 475 | } |
| 476 | |
| 477 | return status; |
| 478 | } |
| 479 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 480 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 481 | { |
| 482 | if (mode->clock >= 100000) |
| 483 | return 1; |
| 484 | else if (mode->clock >= 50000) |
| 485 | return 2; |
| 486 | else |
| 487 | return 4; |
| 488 | } |
| 489 | |
| 490 | /** |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 491 | * Try to read the response after issuie the DDC switch command. But it |
| 492 | * is noted that we must do the action of reading response and issuing DDC |
| 493 | * switch command in one I2C transaction. Otherwise when we try to start |
| 494 | * another I2C transaction after issuing the DDC bus switch, it will be |
| 495 | * switched to the internal SDVO register. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 496 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 497 | static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 498 | u8 target) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 499 | { |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 500 | u8 out_buf[2], cmd_buf[2], ret_value[2], ret; |
| 501 | struct i2c_msg msgs[] = { |
| 502 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 503 | .addr = intel_sdvo->slave_addr >> 1, |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 504 | .flags = 0, |
| 505 | .len = 2, |
| 506 | .buf = out_buf, |
| 507 | }, |
| 508 | /* the following two are to read the response */ |
| 509 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 510 | .addr = intel_sdvo->slave_addr >> 1, |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 511 | .flags = 0, |
| 512 | .len = 1, |
| 513 | .buf = cmd_buf, |
| 514 | }, |
| 515 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 516 | .addr = intel_sdvo->slave_addr >> 1, |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 517 | .flags = I2C_M_RD, |
| 518 | .len = 1, |
| 519 | .buf = ret_value, |
| 520 | }, |
| 521 | }; |
| 522 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 523 | intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 524 | &target, 1); |
| 525 | /* write the DDC switch command argument */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 526 | intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target); |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 527 | |
| 528 | out_buf[0] = SDVO_I2C_OPCODE; |
| 529 | out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH; |
| 530 | cmd_buf[0] = SDVO_I2C_CMD_STATUS; |
| 531 | cmd_buf[1] = 0; |
| 532 | ret_value[0] = 0; |
| 533 | ret_value[1] = 0; |
| 534 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 535 | ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3); |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 536 | if (ret != 3) { |
| 537 | /* failure in I2C transfer */ |
| 538 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); |
| 539 | return; |
| 540 | } |
| 541 | if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) { |
| 542 | DRM_DEBUG_KMS("DDC switch command returns response %d\n", |
| 543 | ret_value[0]); |
| 544 | return; |
| 545 | } |
| 546 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 547 | } |
| 548 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 549 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo, bool target_0, bool target_1) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 550 | { |
| 551 | struct intel_sdvo_set_target_input_args targets = {0}; |
| 552 | u8 status; |
| 553 | |
| 554 | if (target_0 && target_1) |
| 555 | return SDVO_CMD_STATUS_NOTSUPP; |
| 556 | |
| 557 | if (target_1) |
| 558 | targets.target_1 = 1; |
| 559 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 560 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_TARGET_INPUT, &targets, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 561 | sizeof(targets)); |
| 562 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 563 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 564 | |
| 565 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 566 | } |
| 567 | |
| 568 | /** |
| 569 | * Return whether each input is trained. |
| 570 | * |
| 571 | * This function is making an assumption about the layout of the response, |
| 572 | * which should be checked against the docs. |
| 573 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 574 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 575 | { |
| 576 | struct intel_sdvo_get_trained_inputs_response response; |
| 577 | u8 status; |
| 578 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 579 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0); |
| 580 | status = intel_sdvo_read_response(intel_sdvo, &response, sizeof(response)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 581 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 582 | return false; |
| 583 | |
| 584 | *input_1 = response.input0_trained; |
| 585 | *input_2 = response.input1_trained; |
| 586 | return true; |
| 587 | } |
| 588 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 589 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 590 | u16 outputs) |
| 591 | { |
| 592 | u8 status; |
| 593 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 594 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 595 | sizeof(outputs)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 596 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 597 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 598 | } |
| 599 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 600 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 601 | int mode) |
| 602 | { |
| 603 | u8 status, state = SDVO_ENCODER_STATE_ON; |
| 604 | |
| 605 | switch (mode) { |
| 606 | case DRM_MODE_DPMS_ON: |
| 607 | state = SDVO_ENCODER_STATE_ON; |
| 608 | break; |
| 609 | case DRM_MODE_DPMS_STANDBY: |
| 610 | state = SDVO_ENCODER_STATE_STANDBY; |
| 611 | break; |
| 612 | case DRM_MODE_DPMS_SUSPEND: |
| 613 | state = SDVO_ENCODER_STATE_SUSPEND; |
| 614 | break; |
| 615 | case DRM_MODE_DPMS_OFF: |
| 616 | state = SDVO_ENCODER_STATE_OFF; |
| 617 | break; |
| 618 | } |
| 619 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 620 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ENCODER_POWER_STATE, &state, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 621 | sizeof(state)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 622 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 623 | |
| 624 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 625 | } |
| 626 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 627 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 628 | int *clock_min, |
| 629 | int *clock_max) |
| 630 | { |
| 631 | struct intel_sdvo_pixel_clock_range clocks; |
| 632 | u8 status; |
| 633 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 634 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 635 | NULL, 0); |
| 636 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 637 | status = intel_sdvo_read_response(intel_sdvo, &clocks, sizeof(clocks)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 638 | |
| 639 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 640 | return false; |
| 641 | |
| 642 | /* Convert the values from units of 10 kHz to kHz. */ |
| 643 | *clock_min = clocks.min * 10; |
| 644 | *clock_max = clocks.max * 10; |
| 645 | |
| 646 | return true; |
| 647 | } |
| 648 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 649 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 650 | u16 outputs) |
| 651 | { |
| 652 | u8 status; |
| 653 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 654 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_TARGET_OUTPUT, &outputs, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 655 | sizeof(outputs)); |
| 656 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 657 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 658 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 659 | } |
| 660 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 661 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 662 | struct intel_sdvo_dtd *dtd) |
| 663 | { |
| 664 | u8 status; |
| 665 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 666 | intel_sdvo_write_cmd(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)); |
| 667 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 668 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 669 | return false; |
| 670 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 671 | intel_sdvo_write_cmd(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
| 672 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 673 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 674 | return false; |
| 675 | |
| 676 | return true; |
| 677 | } |
| 678 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 679 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 680 | struct intel_sdvo_dtd *dtd) |
| 681 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 682 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 683 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
| 684 | } |
| 685 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 686 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 687 | struct intel_sdvo_dtd *dtd) |
| 688 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 689 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 690 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
| 691 | } |
| 692 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 693 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 694 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 695 | uint16_t clock, |
| 696 | uint16_t width, |
| 697 | uint16_t height) |
| 698 | { |
| 699 | struct intel_sdvo_preferred_input_timing_args args; |
| 700 | uint8_t status; |
| 701 | |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 702 | memset(&args, 0, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 703 | args.clock = clock; |
| 704 | args.width = width; |
| 705 | args.height = height; |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 706 | args.interlace = 0; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 707 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 708 | if (intel_sdvo->is_lvds && |
| 709 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || |
| 710 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 711 | args.scaled = 1; |
| 712 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 713 | intel_sdvo_write_cmd(intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 714 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 715 | &args, sizeof(args)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 716 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 717 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 718 | return false; |
| 719 | |
| 720 | return true; |
| 721 | } |
| 722 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 723 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 724 | struct intel_sdvo_dtd *dtd) |
| 725 | { |
| 726 | bool status; |
| 727 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 728 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 729 | NULL, 0); |
| 730 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 731 | status = intel_sdvo_read_response(intel_sdvo, &dtd->part1, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 732 | sizeof(dtd->part1)); |
| 733 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 734 | return false; |
| 735 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 736 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 737 | NULL, 0); |
| 738 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 739 | status = intel_sdvo_read_response(intel_sdvo, &dtd->part2, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 740 | sizeof(dtd->part2)); |
| 741 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 742 | return false; |
| 743 | |
| 744 | return false; |
| 745 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 746 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 747 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 748 | { |
| 749 | u8 status; |
| 750 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 751 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
| 752 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 753 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 754 | return false; |
| 755 | |
| 756 | return true; |
| 757 | } |
| 758 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 759 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
| 760 | struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 761 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 762 | uint16_t width, height; |
| 763 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
| 764 | uint16_t h_sync_offset, v_sync_offset; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 765 | |
| 766 | width = mode->crtc_hdisplay; |
| 767 | height = mode->crtc_vdisplay; |
| 768 | |
| 769 | /* do some mode translations */ |
| 770 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; |
| 771 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; |
| 772 | |
| 773 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; |
| 774 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; |
| 775 | |
| 776 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; |
| 777 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; |
| 778 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 779 | dtd->part1.clock = mode->clock / 10; |
| 780 | dtd->part1.h_active = width & 0xff; |
| 781 | dtd->part1.h_blank = h_blank_len & 0xff; |
| 782 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 783 | ((h_blank_len >> 8) & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 784 | dtd->part1.v_active = height & 0xff; |
| 785 | dtd->part1.v_blank = v_blank_len & 0xff; |
| 786 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 787 | ((v_blank_len >> 8) & 0xf); |
| 788 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 789 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 790 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
| 791 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 792 | (v_sync_len & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 793 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 794 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
| 795 | ((v_sync_len & 0x30) >> 4); |
| 796 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 797 | dtd->part2.dtd_flags = 0x18; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 798 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 799 | dtd->part2.dtd_flags |= 0x2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 800 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 801 | dtd->part2.dtd_flags |= 0x4; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 802 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 803 | dtd->part2.sdvo_flags = 0; |
| 804 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
| 805 | dtd->part2.reserved = 0; |
| 806 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 807 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 808 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, |
| 809 | struct intel_sdvo_dtd *dtd) |
| 810 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 811 | mode->hdisplay = dtd->part1.h_active; |
| 812 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
| 813 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 814 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 815 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
| 816 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
| 817 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; |
| 818 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; |
| 819 | |
| 820 | mode->vdisplay = dtd->part1.v_active; |
| 821 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
| 822 | mode->vsync_start = mode->vdisplay; |
| 823 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 824 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 825 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
| 826 | mode->vsync_end = mode->vsync_start + |
| 827 | (dtd->part2.v_sync_off_width & 0xf); |
| 828 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
| 829 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; |
| 830 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; |
| 831 | |
| 832 | mode->clock = dtd->part1.clock * 10; |
| 833 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 834 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 835 | if (dtd->part2.dtd_flags & 0x2) |
| 836 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
| 837 | if (dtd->part2.dtd_flags & 0x4) |
| 838 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
| 839 | } |
| 840 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 841 | static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 842 | struct intel_sdvo_encode *encode) |
| 843 | { |
| 844 | uint8_t status; |
| 845 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 846 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0); |
| 847 | status = intel_sdvo_read_response(intel_sdvo, encode, sizeof(*encode)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 848 | if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */ |
| 849 | memset(encode, 0, sizeof(*encode)); |
| 850 | return false; |
| 851 | } |
| 852 | |
| 853 | return true; |
| 854 | } |
| 855 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 856 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 857 | uint8_t mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 858 | { |
| 859 | uint8_t status; |
| 860 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 861 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
| 862 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 863 | |
| 864 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 865 | } |
| 866 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 867 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 868 | uint8_t mode) |
| 869 | { |
| 870 | uint8_t status; |
| 871 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 872 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
| 873 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 874 | |
| 875 | return (status == SDVO_CMD_STATUS_SUCCESS); |
| 876 | } |
| 877 | |
| 878 | #if 0 |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 879 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 880 | { |
| 881 | int i, j; |
| 882 | uint8_t set_buf_index[2]; |
| 883 | uint8_t av_split; |
| 884 | uint8_t buf_size; |
| 885 | uint8_t buf[48]; |
| 886 | uint8_t *pos; |
| 887 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 888 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0); |
| 889 | intel_sdvo_read_response(encoder, &av_split, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 890 | |
| 891 | for (i = 0; i <= av_split; i++) { |
| 892 | set_buf_index[0] = i; set_buf_index[1] = 0; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 893 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 894 | set_buf_index, 2); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 895 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
| 896 | intel_sdvo_read_response(encoder, &buf_size, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 897 | |
| 898 | pos = buf; |
| 899 | for (j = 0; j <= buf_size; j += 8) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 900 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 901 | NULL, 0); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 902 | intel_sdvo_read_response(encoder, pos, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 903 | pos += 8; |
| 904 | } |
| 905 | } |
| 906 | } |
| 907 | #endif |
| 908 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 909 | static void intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 910 | int index, |
| 911 | uint8_t *data, int8_t size, uint8_t tx_rate) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 912 | { |
| 913 | uint8_t set_buf_index[2]; |
| 914 | |
| 915 | set_buf_index[0] = index; |
| 916 | set_buf_index[1] = 0; |
| 917 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 918 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 919 | set_buf_index, 2); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 920 | |
| 921 | for (; size > 0; size -= 8) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 922 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 923 | data += 8; |
| 924 | } |
| 925 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 926 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 927 | } |
| 928 | |
| 929 | static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) |
| 930 | { |
| 931 | uint8_t csum = 0; |
| 932 | int i; |
| 933 | |
| 934 | for (i = 0; i < size; i++) |
| 935 | csum += data[i]; |
| 936 | |
| 937 | return 0x100 - csum; |
| 938 | } |
| 939 | |
| 940 | #define DIP_TYPE_AVI 0x82 |
| 941 | #define DIP_VERSION_AVI 0x2 |
| 942 | #define DIP_LEN_AVI 13 |
| 943 | |
| 944 | struct dip_infoframe { |
| 945 | uint8_t type; |
| 946 | uint8_t version; |
| 947 | uint8_t len; |
| 948 | uint8_t checksum; |
| 949 | union { |
| 950 | struct { |
| 951 | /* Packet Byte #1 */ |
| 952 | uint8_t S:2; |
| 953 | uint8_t B:2; |
| 954 | uint8_t A:1; |
| 955 | uint8_t Y:2; |
| 956 | uint8_t rsvd1:1; |
| 957 | /* Packet Byte #2 */ |
| 958 | uint8_t R:4; |
| 959 | uint8_t M:2; |
| 960 | uint8_t C:2; |
| 961 | /* Packet Byte #3 */ |
| 962 | uint8_t SC:2; |
| 963 | uint8_t Q:2; |
| 964 | uint8_t EC:3; |
| 965 | uint8_t ITC:1; |
| 966 | /* Packet Byte #4 */ |
| 967 | uint8_t VIC:7; |
| 968 | uint8_t rsvd2:1; |
| 969 | /* Packet Byte #5 */ |
| 970 | uint8_t PR:4; |
| 971 | uint8_t rsvd3:4; |
| 972 | /* Packet Byte #6~13 */ |
| 973 | uint16_t top_bar_end; |
| 974 | uint16_t bottom_bar_start; |
| 975 | uint16_t left_bar_end; |
| 976 | uint16_t right_bar_start; |
| 977 | } avi; |
| 978 | struct { |
| 979 | /* Packet Byte #1 */ |
| 980 | uint8_t channel_count:3; |
| 981 | uint8_t rsvd1:1; |
| 982 | uint8_t coding_type:4; |
| 983 | /* Packet Byte #2 */ |
| 984 | uint8_t sample_size:2; /* SS0, SS1 */ |
| 985 | uint8_t sample_frequency:3; |
| 986 | uint8_t rsvd2:3; |
| 987 | /* Packet Byte #3 */ |
| 988 | uint8_t coding_type_private:5; |
| 989 | uint8_t rsvd3:3; |
| 990 | /* Packet Byte #4 */ |
| 991 | uint8_t channel_allocation; |
| 992 | /* Packet Byte #5 */ |
| 993 | uint8_t rsvd4:3; |
| 994 | uint8_t level_shift:4; |
| 995 | uint8_t downmix_inhibit:1; |
| 996 | } audio; |
| 997 | uint8_t payload[28]; |
| 998 | } __attribute__ ((packed)) u; |
| 999 | } __attribute__((packed)); |
| 1000 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1001 | static void intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1002 | struct drm_display_mode * mode) |
| 1003 | { |
| 1004 | struct dip_infoframe avi_if = { |
| 1005 | .type = DIP_TYPE_AVI, |
| 1006 | .version = DIP_VERSION_AVI, |
| 1007 | .len = DIP_LEN_AVI, |
| 1008 | }; |
| 1009 | |
| 1010 | avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, |
| 1011 | 4 + avi_if.len); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1012 | intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1013 | 4 + avi_if.len, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1014 | SDVO_HBUF_TX_VSYNC); |
| 1015 | } |
| 1016 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1017 | static void intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1018 | { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1019 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1020 | struct intel_sdvo_tv_format format; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1021 | uint32_t format_map, i; |
| 1022 | uint8_t status; |
| 1023 | |
| 1024 | for (i = 0; i < TV_FORMAT_NUM; i++) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1025 | if (tv_format_names[i] == intel_sdvo->tv_format_name) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1026 | break; |
| 1027 | |
| 1028 | format_map = 1 << i; |
| 1029 | memset(&format, 0, sizeof(format)); |
| 1030 | memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? |
| 1031 | sizeof(format) : sizeof(format_map)); |
| 1032 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1033 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_TV_FORMAT, &format, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1034 | sizeof(format)); |
| 1035 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1036 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1037 | if (status != SDVO_CMD_STATUS_SUCCESS) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1038 | DRM_DEBUG_KMS("%s: Failed to set TV format\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1039 | SDVO_NAME(intel_sdvo)); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1040 | } |
| 1041 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1042 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
| 1043 | struct drm_display_mode *mode, |
| 1044 | struct drm_display_mode *adjusted_mode) |
| 1045 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1046 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1047 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1048 | if (intel_sdvo->is_tv) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1049 | struct intel_sdvo_dtd output_dtd; |
| 1050 | bool success; |
| 1051 | |
| 1052 | /* We need to construct preferred input timings based on our |
| 1053 | * output timings. To do that, we have to set the output |
| 1054 | * timings, even though this isn't really the right place in |
| 1055 | * the sequence to do it. Oh well. |
| 1056 | */ |
| 1057 | |
| 1058 | |
| 1059 | /* Set output timings */ |
| 1060 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1061 | intel_sdvo_set_target_output(intel_sdvo, |
| 1062 | intel_sdvo->attached_output); |
| 1063 | intel_sdvo_set_output_timing(intel_sdvo, &output_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1064 | |
| 1065 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1066 | intel_sdvo_set_target_input(intel_sdvo, true, false); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1067 | |
| 1068 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1069 | success = intel_sdvo_create_preferred_input_timing(intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1070 | mode->clock / 10, |
| 1071 | mode->hdisplay, |
| 1072 | mode->vdisplay); |
| 1073 | if (success) { |
| 1074 | struct intel_sdvo_dtd input_dtd; |
| 1075 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1076 | intel_sdvo_get_preferred_input_timing(intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1077 | &input_dtd); |
| 1078 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1079 | intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1080 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1081 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 1082 | |
| 1083 | mode->clock = adjusted_mode->clock; |
| 1084 | |
| 1085 | adjusted_mode->clock *= |
| 1086 | intel_sdvo_get_pixel_multiplier(mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1087 | } else { |
| 1088 | return false; |
| 1089 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1090 | } else if (intel_sdvo->is_lvds) { |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1091 | struct intel_sdvo_dtd output_dtd; |
| 1092 | bool success; |
| 1093 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1094 | drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0); |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1095 | /* Set output timings */ |
| 1096 | intel_sdvo_get_dtd_from_mode(&output_dtd, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1097 | intel_sdvo->sdvo_lvds_fixed_mode); |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1098 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1099 | intel_sdvo_set_target_output(intel_sdvo, |
| 1100 | intel_sdvo->attached_output); |
| 1101 | intel_sdvo_set_output_timing(intel_sdvo, &output_dtd); |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1102 | |
| 1103 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1104 | intel_sdvo_set_target_input(intel_sdvo, true, false); |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1105 | |
| 1106 | |
| 1107 | success = intel_sdvo_create_preferred_input_timing( |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1108 | intel_sdvo, |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1109 | mode->clock / 10, |
| 1110 | mode->hdisplay, |
| 1111 | mode->vdisplay); |
| 1112 | |
| 1113 | if (success) { |
| 1114 | struct intel_sdvo_dtd input_dtd; |
| 1115 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1116 | intel_sdvo_get_preferred_input_timing(intel_sdvo, |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1117 | &input_dtd); |
| 1118 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1119 | intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1120 | |
| 1121 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 1122 | |
| 1123 | mode->clock = adjusted_mode->clock; |
| 1124 | |
| 1125 | adjusted_mode->clock *= |
| 1126 | intel_sdvo_get_pixel_multiplier(mode); |
| 1127 | } else { |
| 1128 | return false; |
| 1129 | } |
| 1130 | |
| 1131 | } else { |
| 1132 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
| 1133 | * SDVO device will be told of the multiplier during mode_set. |
| 1134 | */ |
| 1135 | adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1136 | } |
| 1137 | return true; |
| 1138 | } |
| 1139 | |
| 1140 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, |
| 1141 | struct drm_display_mode *mode, |
| 1142 | struct drm_display_mode *adjusted_mode) |
| 1143 | { |
| 1144 | struct drm_device *dev = encoder->dev; |
| 1145 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1146 | struct drm_crtc *crtc = encoder->crtc; |
| 1147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1148 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1149 | u32 sdvox = 0; |
| 1150 | int sdvo_pixel_multiply; |
| 1151 | struct intel_sdvo_in_out_map in_out; |
| 1152 | struct intel_sdvo_dtd input_dtd; |
| 1153 | u8 status; |
| 1154 | |
| 1155 | if (!mode) |
| 1156 | return; |
| 1157 | |
| 1158 | /* First, set the input mapping for the first input to our controlled |
| 1159 | * output. This is only correct if we're a single-input device, in |
| 1160 | * which case the first input is the output from the appropriate SDVO |
| 1161 | * channel on the motherboard. In a two-input device, the first input |
| 1162 | * will be SDVOB and the second SDVOC. |
| 1163 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1164 | in_out.in0 = intel_sdvo->attached_output; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1165 | in_out.in1 = 0; |
| 1166 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1167 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_IN_OUT_MAP, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1168 | &in_out, sizeof(in_out)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1169 | status = intel_sdvo_read_response(intel_sdvo, NULL, 0); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1170 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1171 | if (intel_sdvo->is_hdmi) { |
| 1172 | intel_sdvo_set_avi_infoframe(intel_sdvo, mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1173 | sdvox |= SDVO_AUDIO_ENABLE; |
| 1174 | } |
| 1175 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1176 | /* We have tried to get input timing in mode_fixup, and filled into |
| 1177 | adjusted_mode */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1178 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1179 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1180 | input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1181 | } else |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1182 | intel_sdvo_get_dtd_from_mode(&input_dtd, mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1183 | |
| 1184 | /* If it's a TV, we already set the output timing in mode_fixup. |
| 1185 | * Otherwise, the output timing is equal to the input timing. |
| 1186 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1187 | if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1188 | /* Set the output timing to the screen */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1189 | intel_sdvo_set_target_output(intel_sdvo, |
| 1190 | intel_sdvo->attached_output); |
| 1191 | intel_sdvo_set_output_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1192 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1193 | |
| 1194 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1195 | intel_sdvo_set_target_input(intel_sdvo, true, false); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1196 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1197 | if (intel_sdvo->is_tv) |
| 1198 | intel_sdvo_set_tv_format(intel_sdvo); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1199 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1200 | /* We would like to use intel_sdvo_create_preferred_input_timing() to |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1201 | * provide the device with a timing it can support, if it supports that |
| 1202 | * feature. However, presumably we would need to adjust the CRTC to |
| 1203 | * output the preferred timing, and we don't support that currently. |
| 1204 | */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1205 | #if 0 |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1206 | success = intel_sdvo_create_preferred_input_timing(encoder, clock, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1207 | width, height); |
| 1208 | if (success) { |
| 1209 | struct intel_sdvo_dtd *input_dtd; |
| 1210 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1211 | intel_sdvo_get_preferred_input_timing(encoder, &input_dtd); |
| 1212 | intel_sdvo_set_input_timing(encoder, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1213 | } |
| 1214 | #else |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1215 | intel_sdvo_set_input_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1216 | #endif |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1217 | |
| 1218 | switch (intel_sdvo_get_pixel_multiplier(mode)) { |
| 1219 | case 1: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1220 | intel_sdvo_set_clock_rate_mult(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1221 | SDVO_CLOCK_RATE_MULT_1X); |
| 1222 | break; |
| 1223 | case 2: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1224 | intel_sdvo_set_clock_rate_mult(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1225 | SDVO_CLOCK_RATE_MULT_2X); |
| 1226 | break; |
| 1227 | case 4: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1228 | intel_sdvo_set_clock_rate_mult(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1229 | SDVO_CLOCK_RATE_MULT_4X); |
| 1230 | break; |
| 1231 | } |
| 1232 | |
| 1233 | /* Set the SDVO control regs. */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1234 | if (IS_I965G(dev)) { |
Adam Jackson | 81a14b4 | 2010-07-16 14:46:32 -0400 | [diff] [blame] | 1235 | sdvox |= SDVO_BORDER_ENABLE; |
| 1236 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1237 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
| 1238 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1239 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1240 | } else { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1241 | sdvox |= I915_READ(intel_sdvo->sdvo_reg); |
| 1242 | switch (intel_sdvo->sdvo_reg) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1243 | case SDVOB: |
| 1244 | sdvox &= SDVOB_PRESERVE_MASK; |
| 1245 | break; |
| 1246 | case SDVOC: |
| 1247 | sdvox &= SDVOC_PRESERVE_MASK; |
| 1248 | break; |
| 1249 | } |
| 1250 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
| 1251 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1252 | if (intel_crtc->pipe == 1) |
| 1253 | sdvox |= SDVO_PIPE_B_SELECT; |
| 1254 | |
| 1255 | sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode); |
| 1256 | if (IS_I965G(dev)) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1257 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
| 1258 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 1259 | /* done in crtc_mode_set as it lives inside the dpll register */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1260 | } else { |
| 1261 | sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
| 1262 | } |
| 1263 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1264 | if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1265 | sdvox |= SDVO_STALL_SELECT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1266 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1267 | } |
| 1268 | |
| 1269 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) |
| 1270 | { |
| 1271 | struct drm_device *dev = encoder->dev; |
| 1272 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1273 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1274 | u32 temp; |
| 1275 | |
| 1276 | if (mode != DRM_MODE_DPMS_ON) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1277 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1278 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1279 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1280 | |
| 1281 | if (mode == DRM_MODE_DPMS_OFF) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1282 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1283 | if ((temp & SDVO_ENABLE) != 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1284 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1285 | } |
| 1286 | } |
| 1287 | } else { |
| 1288 | bool input1, input2; |
| 1289 | int i; |
| 1290 | u8 status; |
| 1291 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1292 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1293 | if ((temp & SDVO_ENABLE) == 0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1294 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1295 | for (i = 0; i < 2; i++) |
| 1296 | intel_wait_for_vblank(dev); |
| 1297 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1298 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1299 | &input2); |
| 1300 | |
| 1301 | |
| 1302 | /* Warn if the device reported failure to sync. |
| 1303 | * A lot of SDVO devices fail to notify of sync, but it's |
| 1304 | * a given it the status is a success, we succeeded. |
| 1305 | */ |
| 1306 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1307 | DRM_DEBUG_KMS("First %s output reported failure to " |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1308 | "sync\n", SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1309 | } |
| 1310 | |
| 1311 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1312 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
| 1313 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1314 | } |
| 1315 | return; |
| 1316 | } |
| 1317 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1318 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
| 1319 | struct drm_display_mode *mode) |
| 1320 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1321 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1322 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1323 | |
| 1324 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1325 | return MODE_NO_DBLESCAN; |
| 1326 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1327 | if (intel_sdvo->pixel_clock_min > mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1328 | return MODE_CLOCK_LOW; |
| 1329 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1330 | if (intel_sdvo->pixel_clock_max < mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1331 | return MODE_CLOCK_HIGH; |
| 1332 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1333 | if (intel_sdvo->is_lvds == true) { |
| 1334 | if (intel_sdvo->sdvo_lvds_fixed_mode == NULL) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1335 | return MODE_PANEL; |
| 1336 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1337 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1338 | return MODE_PANEL; |
| 1339 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1340 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1341 | return MODE_PANEL; |
| 1342 | } |
| 1343 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1344 | return MODE_OK; |
| 1345 | } |
| 1346 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1347 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1348 | { |
| 1349 | u8 status; |
| 1350 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1351 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0); |
| 1352 | status = intel_sdvo_read_response(intel_sdvo, caps, sizeof(*caps)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1353 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 1354 | return false; |
| 1355 | |
| 1356 | return true; |
| 1357 | } |
| 1358 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1359 | /* No use! */ |
| 1360 | #if 0 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1361 | struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) |
| 1362 | { |
| 1363 | struct drm_connector *connector = NULL; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1364 | struct intel_sdvo *iout = NULL; |
| 1365 | struct intel_sdvo *sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1366 | |
| 1367 | /* find the sdvo connector */ |
| 1368 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1369 | iout = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1370 | |
| 1371 | if (iout->type != INTEL_OUTPUT_SDVO) |
| 1372 | continue; |
| 1373 | |
| 1374 | sdvo = iout->dev_priv; |
| 1375 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1376 | if (sdvo->sdvo_reg == SDVOB && sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1377 | return connector; |
| 1378 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1379 | if (sdvo->sdvo_reg == SDVOC && !sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1380 | return connector; |
| 1381 | |
| 1382 | } |
| 1383 | |
| 1384 | return NULL; |
| 1385 | } |
| 1386 | |
| 1387 | int intel_sdvo_supports_hotplug(struct drm_connector *connector) |
| 1388 | { |
| 1389 | u8 response[2]; |
| 1390 | u8 status; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1391 | struct intel_sdvo *intel_sdvo; |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1392 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1393 | |
| 1394 | if (!connector) |
| 1395 | return 0; |
| 1396 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1397 | intel_sdvo = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1398 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1399 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); |
| 1400 | status = intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1401 | |
| 1402 | if (response[0] !=0) |
| 1403 | return 1; |
| 1404 | |
| 1405 | return 0; |
| 1406 | } |
| 1407 | |
| 1408 | void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) |
| 1409 | { |
| 1410 | u8 response[2]; |
| 1411 | u8 status; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1412 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1413 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1414 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1415 | intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1416 | |
| 1417 | if (on) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1418 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); |
| 1419 | status = intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1420 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1421 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1422 | } else { |
| 1423 | response[0] = 0; |
| 1424 | response[1] = 0; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1425 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1426 | } |
| 1427 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1428 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1429 | intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1430 | } |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1431 | #endif |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1432 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1433 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1434 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1435 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1436 | int caps = 0; |
| 1437 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1438 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1439 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) |
| 1440 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1441 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1442 | (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) |
| 1443 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1444 | if (intel_sdvo->caps.output_flags & |
Roel Kluin | 19e1f88 | 2009-08-09 13:50:53 +0200 | [diff] [blame] | 1445 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1446 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1447 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1448 | (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) |
| 1449 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1450 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1451 | (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) |
| 1452 | caps++; |
| 1453 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1454 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1455 | (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) |
| 1456 | caps++; |
| 1457 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1458 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1459 | (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) |
| 1460 | caps++; |
| 1461 | |
| 1462 | return (caps > 1); |
| 1463 | } |
| 1464 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1465 | static struct drm_connector * |
| 1466 | intel_find_analog_connector(struct drm_device *dev) |
| 1467 | { |
| 1468 | struct drm_connector *connector; |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1469 | struct drm_encoder *encoder; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1470 | struct intel_sdvo *intel_sdvo; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1471 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1472 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1473 | intel_sdvo = enc_to_intel_sdvo(encoder); |
| 1474 | if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1475 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Dan Carpenter | 90a78e8 | 2010-05-07 10:40:09 +0200 | [diff] [blame] | 1476 | if (encoder == intel_attached_encoder(connector)) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1477 | return connector; |
| 1478 | } |
| 1479 | } |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1480 | } |
| 1481 | return NULL; |
| 1482 | } |
| 1483 | |
| 1484 | static int |
| 1485 | intel_analog_is_connected(struct drm_device *dev) |
| 1486 | { |
| 1487 | struct drm_connector *analog_connector; |
| 1488 | analog_connector = intel_find_analog_connector(dev); |
| 1489 | |
| 1490 | if (!analog_connector) |
| 1491 | return false; |
| 1492 | |
| 1493 | if (analog_connector->funcs->detect(analog_connector) == |
| 1494 | connector_status_disconnected) |
| 1495 | return false; |
| 1496 | |
| 1497 | return true; |
| 1498 | } |
| 1499 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1500 | enum drm_connector_status |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1501 | intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1502 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1503 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1504 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1505 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1506 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1507 | enum drm_connector_status status = connector_status_connected; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1508 | struct edid *edid = NULL; |
| 1509 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1510 | edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1511 | |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1512 | /* This is only applied to SDVO cards with multiple outputs */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1513 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1514 | uint8_t saved_ddc, temp_ddc; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1515 | saved_ddc = intel_sdvo->ddc_bus; |
| 1516 | temp_ddc = intel_sdvo->ddc_bus >> 1; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1517 | /* |
| 1518 | * Don't use the 1 as the argument of DDC bus switch to get |
| 1519 | * the EDID. It is used for SDVO SPD ROM. |
| 1520 | */ |
| 1521 | while(temp_ddc > 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1522 | intel_sdvo->ddc_bus = temp_ddc; |
| 1523 | edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus); |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1524 | if (edid) { |
| 1525 | /* |
| 1526 | * When we can get the EDID, maybe it is the |
| 1527 | * correct DDC bus. Update it. |
| 1528 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1529 | intel_sdvo->ddc_bus = temp_ddc; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1530 | break; |
| 1531 | } |
| 1532 | temp_ddc >>= 1; |
| 1533 | } |
| 1534 | if (edid == NULL) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1535 | intel_sdvo->ddc_bus = saved_ddc; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1536 | } |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1537 | /* when there is no edid and no monitor is connected with VGA |
| 1538 | * port, try to use the CRT ddc to read the EDID for DVI-connector |
| 1539 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1540 | if (edid == NULL && intel_sdvo->analog_ddc_bus && |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1541 | !intel_analog_is_connected(connector->dev)) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1542 | edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus); |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1543 | |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1544 | if (edid != NULL) { |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1545 | bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); |
| 1546 | bool need_digital = !!(sdvo_connector->output_flag & SDVO_TMDS_MASK); |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1547 | |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1548 | /* DDC bus is shared, match EDID to connector type */ |
| 1549 | if (is_digital && need_digital) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1550 | intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid); |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1551 | else if (is_digital != need_digital) |
| 1552 | status = connector_status_disconnected; |
| 1553 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1554 | connector->display_info.raw_edid = NULL; |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1555 | } else |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1556 | status = connector_status_disconnected; |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1557 | |
| 1558 | kfree(edid); |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1559 | |
| 1560 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1561 | } |
| 1562 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1563 | static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector) |
| 1564 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1565 | uint16_t response; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1566 | u8 status; |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1567 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1568 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1569 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1570 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
| 1571 | enum drm_connector_status ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1572 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1573 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1574 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1575 | if (intel_sdvo->is_tv) { |
Zhao Yakui | d09c23d | 2009-11-06 15:39:56 +0800 | [diff] [blame] | 1576 | /* add 30ms delay when the output type is SDVO-TV */ |
| 1577 | mdelay(30); |
| 1578 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1579 | status = intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1580 | |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 1581 | DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1582 | |
| 1583 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 1584 | return connector_status_unknown; |
| 1585 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1586 | if (response == 0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1587 | return connector_status_disconnected; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1588 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1589 | intel_sdvo->attached_output = response; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1590 | |
| 1591 | if ((sdvo_connector->output_flag & response) == 0) |
| 1592 | ret = connector_status_disconnected; |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1593 | else if (response & SDVO_TMDS_MASK) |
| 1594 | ret = intel_sdvo_hdmi_sink_detect(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1595 | else |
| 1596 | ret = connector_status_connected; |
| 1597 | |
| 1598 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
| 1599 | if (ret == connector_status_connected) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1600 | intel_sdvo->is_tv = false; |
| 1601 | intel_sdvo->is_lvds = false; |
| 1602 | intel_sdvo->base.needs_tv_clock = false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1603 | |
| 1604 | if (response & SDVO_TV_MASK) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1605 | intel_sdvo->is_tv = true; |
| 1606 | intel_sdvo->base.needs_tv_clock = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1607 | } |
| 1608 | if (response & SDVO_LVDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1609 | intel_sdvo->is_lvds = true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1610 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1611 | |
| 1612 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1613 | } |
| 1614 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1615 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1616 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1617 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1618 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1619 | int num_modes; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1620 | |
| 1621 | /* set the bus switch and get the modes */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1622 | num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1623 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1624 | /* |
| 1625 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
| 1626 | * link between analog and digital outputs. So, if the regular SDVO |
| 1627 | * DDC fails, check to see if the analog output is disconnected, in |
| 1628 | * which case we'll look there for the digital DDC data. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1629 | */ |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1630 | if (num_modes == 0 && |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1631 | intel_sdvo->analog_ddc_bus && |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1632 | !intel_analog_is_connected(connector->dev)) { |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1633 | /* Switch to the analog ddc bus and try that |
| 1634 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1635 | (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1636 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1637 | } |
| 1638 | |
| 1639 | /* |
| 1640 | * Set of SDVO TV modes. |
| 1641 | * Note! This is in reply order (see loop in get_tv_modes). |
| 1642 | * XXX: all 60Hz refresh? |
| 1643 | */ |
| 1644 | struct drm_display_mode sdvo_tv_modes[] = { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1645 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
| 1646 | 416, 0, 200, 201, 232, 233, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1647 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1648 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
| 1649 | 416, 0, 240, 241, 272, 273, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1650 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1651 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
| 1652 | 496, 0, 300, 301, 332, 333, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1653 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1654 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
| 1655 | 736, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1656 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1657 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
| 1658 | 736, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1659 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1660 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
| 1661 | 736, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1662 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1663 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
| 1664 | 800, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1665 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1666 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
| 1667 | 800, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1668 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1669 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
| 1670 | 816, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1671 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1672 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
| 1673 | 816, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1674 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1675 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
| 1676 | 816, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1677 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1678 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
| 1679 | 816, 0, 540, 541, 572, 573, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1680 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1681 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
| 1682 | 816, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1683 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1684 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
| 1685 | 864, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1686 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1687 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
| 1688 | 896, 0, 600, 601, 632, 633, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1689 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1690 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
| 1691 | 928, 0, 624, 625, 656, 657, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1692 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1693 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
| 1694 | 1016, 0, 766, 767, 798, 799, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1695 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1696 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
| 1697 | 1120, 0, 768, 769, 800, 801, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1698 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1699 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
| 1700 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1701 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
| 1702 | }; |
| 1703 | |
| 1704 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
| 1705 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1706 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1707 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1708 | struct intel_sdvo_sdtv_resolution_request tv_res; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1709 | uint32_t reply = 0, format_map = 0; |
| 1710 | int i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1711 | uint8_t status; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1712 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1713 | |
| 1714 | /* Read the list of supported input resolutions for the selected TV |
| 1715 | * format. |
| 1716 | */ |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1717 | for (i = 0; i < TV_FORMAT_NUM; i++) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1718 | if (tv_format_names[i] == intel_sdvo->tv_format_name) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1719 | break; |
| 1720 | |
| 1721 | format_map = (1 << i); |
| 1722 | memcpy(&tv_res, &format_map, |
| 1723 | sizeof(struct intel_sdvo_sdtv_resolution_request) > |
| 1724 | sizeof(format_map) ? sizeof(format_map) : |
| 1725 | sizeof(struct intel_sdvo_sdtv_resolution_request)); |
| 1726 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1727 | intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1728 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1729 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1730 | &tv_res, sizeof(tv_res)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1731 | status = intel_sdvo_read_response(intel_sdvo, &reply, 3); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1732 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 1733 | return; |
| 1734 | |
| 1735 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1736 | if (reply & (1 << i)) { |
| 1737 | struct drm_display_mode *nmode; |
| 1738 | nmode = drm_mode_duplicate(connector->dev, |
| 1739 | &sdvo_tv_modes[i]); |
| 1740 | if (nmode) |
| 1741 | drm_mode_probed_add(connector, nmode); |
| 1742 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1743 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1744 | } |
| 1745 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1746 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
| 1747 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1748 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1749 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1750 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1751 | struct drm_display_mode *newmode; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1752 | |
| 1753 | /* |
| 1754 | * Attempt to get the mode list from DDC. |
| 1755 | * Assume that the preferred modes are |
| 1756 | * arranged in priority order. |
| 1757 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1758 | intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1759 | if (list_empty(&connector->probed_modes) == false) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1760 | goto end; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1761 | |
| 1762 | /* Fetch modes from VBT */ |
| 1763 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1764 | newmode = drm_mode_duplicate(connector->dev, |
| 1765 | dev_priv->sdvo_lvds_vbt_mode); |
| 1766 | if (newmode != NULL) { |
| 1767 | /* Guarantee the mode is preferred */ |
| 1768 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
| 1769 | DRM_MODE_TYPE_DRIVER); |
| 1770 | drm_mode_probed_add(connector, newmode); |
| 1771 | } |
| 1772 | } |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1773 | |
| 1774 | end: |
| 1775 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
| 1776 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1777 | intel_sdvo->sdvo_lvds_fixed_mode = |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1778 | drm_mode_duplicate(connector->dev, newmode); |
| 1779 | break; |
| 1780 | } |
| 1781 | } |
| 1782 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1783 | } |
| 1784 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1785 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
| 1786 | { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1787 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1788 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1789 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1790 | if (IS_TV(sdvo_connector)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1791 | intel_sdvo_get_tv_modes(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1792 | else if (IS_LVDS(sdvo_connector)) |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1793 | intel_sdvo_get_lvds_modes(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1794 | else |
| 1795 | intel_sdvo_get_ddc_modes(connector); |
| 1796 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1797 | if (list_empty(&connector->probed_modes)) |
| 1798 | return 0; |
| 1799 | return 1; |
| 1800 | } |
| 1801 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1802 | static |
| 1803 | void intel_sdvo_destroy_enhance_property(struct drm_connector *connector) |
| 1804 | { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1805 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1806 | struct intel_sdvo_connector *intel_sdvo = intel_connector->dev_priv; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1807 | struct drm_device *dev = connector->dev; |
| 1808 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1809 | if (IS_TV(intel_sdvo)) { |
| 1810 | if (intel_sdvo->left_property) |
| 1811 | drm_property_destroy(dev, intel_sdvo->left_property); |
| 1812 | if (intel_sdvo->right_property) |
| 1813 | drm_property_destroy(dev, intel_sdvo->right_property); |
| 1814 | if (intel_sdvo->top_property) |
| 1815 | drm_property_destroy(dev, intel_sdvo->top_property); |
| 1816 | if (intel_sdvo->bottom_property) |
| 1817 | drm_property_destroy(dev, intel_sdvo->bottom_property); |
| 1818 | if (intel_sdvo->hpos_property) |
| 1819 | drm_property_destroy(dev, intel_sdvo->hpos_property); |
| 1820 | if (intel_sdvo->vpos_property) |
| 1821 | drm_property_destroy(dev, intel_sdvo->vpos_property); |
| 1822 | if (intel_sdvo->saturation_property) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1823 | drm_property_destroy(dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1824 | intel_sdvo->saturation_property); |
| 1825 | if (intel_sdvo->contrast_property) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1826 | drm_property_destroy(dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1827 | intel_sdvo->contrast_property); |
| 1828 | if (intel_sdvo->hue_property) |
| 1829 | drm_property_destroy(dev, intel_sdvo->hue_property); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1830 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1831 | if (IS_TV(intel_sdvo) || IS_LVDS(intel_sdvo)) { |
| 1832 | if (intel_sdvo->brightness_property) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1833 | drm_property_destroy(dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1834 | intel_sdvo->brightness_property); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1835 | } |
| 1836 | return; |
| 1837 | } |
| 1838 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1839 | static void intel_sdvo_destroy(struct drm_connector *connector) |
| 1840 | { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1841 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1842 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1843 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1844 | if (sdvo_connector->tv_format_property) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1845 | drm_property_destroy(connector->dev, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1846 | sdvo_connector->tv_format_property); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1847 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1848 | intel_sdvo_destroy_enhance_property(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1849 | drm_sysfs_connector_remove(connector); |
| 1850 | drm_connector_cleanup(connector); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1851 | kfree(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1852 | } |
| 1853 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1854 | static int |
| 1855 | intel_sdvo_set_property(struct drm_connector *connector, |
| 1856 | struct drm_property *property, |
| 1857 | uint64_t val) |
| 1858 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1859 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1860 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1861 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 1862 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1863 | struct drm_crtc *crtc = encoder->crtc; |
| 1864 | int ret = 0; |
| 1865 | bool changed = false; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1866 | uint8_t cmd, status; |
| 1867 | uint16_t temp_value; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1868 | |
| 1869 | ret = drm_connector_property_set_value(connector, property, val); |
| 1870 | if (ret < 0) |
| 1871 | goto out; |
| 1872 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1873 | if (property == sdvo_connector->tv_format_property) { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1874 | if (val >= TV_FORMAT_NUM) { |
| 1875 | ret = -EINVAL; |
| 1876 | goto out; |
| 1877 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1878 | if (intel_sdvo->tv_format_name == |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1879 | sdvo_connector->tv_format_supported[val]) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1880 | goto out; |
| 1881 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1882 | intel_sdvo->tv_format_name = sdvo_connector->tv_format_supported[val]; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1883 | changed = true; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1884 | } |
| 1885 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1886 | if (IS_TV(sdvo_connector) || IS_LVDS(sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1887 | cmd = 0; |
| 1888 | temp_value = val; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1889 | if (sdvo_connector->left_property == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1890 | drm_connector_property_set_value(connector, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1891 | sdvo_connector->right_property, val); |
| 1892 | if (sdvo_connector->left_margin == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1893 | goto out; |
| 1894 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1895 | sdvo_connector->left_margin = temp_value; |
| 1896 | sdvo_connector->right_margin = temp_value; |
| 1897 | temp_value = sdvo_connector->max_hscan - |
| 1898 | sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1899 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1900 | } else if (sdvo_connector->right_property == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1901 | drm_connector_property_set_value(connector, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1902 | sdvo_connector->left_property, val); |
| 1903 | if (sdvo_connector->right_margin == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1904 | goto out; |
| 1905 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1906 | sdvo_connector->left_margin = temp_value; |
| 1907 | sdvo_connector->right_margin = temp_value; |
| 1908 | temp_value = sdvo_connector->max_hscan - |
| 1909 | sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1910 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1911 | } else if (sdvo_connector->top_property == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1912 | drm_connector_property_set_value(connector, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1913 | sdvo_connector->bottom_property, val); |
| 1914 | if (sdvo_connector->top_margin == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1915 | goto out; |
| 1916 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1917 | sdvo_connector->top_margin = temp_value; |
| 1918 | sdvo_connector->bottom_margin = temp_value; |
| 1919 | temp_value = sdvo_connector->max_vscan - |
| 1920 | sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1921 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1922 | } else if (sdvo_connector->bottom_property == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1923 | drm_connector_property_set_value(connector, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1924 | sdvo_connector->top_property, val); |
| 1925 | if (sdvo_connector->bottom_margin == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1926 | goto out; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1927 | sdvo_connector->top_margin = temp_value; |
| 1928 | sdvo_connector->bottom_margin = temp_value; |
| 1929 | temp_value = sdvo_connector->max_vscan - |
| 1930 | sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1931 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1932 | } else if (sdvo_connector->hpos_property == property) { |
| 1933 | if (sdvo_connector->cur_hpos == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1934 | goto out; |
| 1935 | |
| 1936 | cmd = SDVO_CMD_SET_POSITION_H; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1937 | sdvo_connector->cur_hpos = temp_value; |
| 1938 | } else if (sdvo_connector->vpos_property == property) { |
| 1939 | if (sdvo_connector->cur_vpos == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1940 | goto out; |
| 1941 | |
| 1942 | cmd = SDVO_CMD_SET_POSITION_V; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1943 | sdvo_connector->cur_vpos = temp_value; |
| 1944 | } else if (sdvo_connector->saturation_property == property) { |
| 1945 | if (sdvo_connector->cur_saturation == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1946 | goto out; |
| 1947 | |
| 1948 | cmd = SDVO_CMD_SET_SATURATION; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1949 | sdvo_connector->cur_saturation = temp_value; |
| 1950 | } else if (sdvo_connector->contrast_property == property) { |
| 1951 | if (sdvo_connector->cur_contrast == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1952 | goto out; |
| 1953 | |
| 1954 | cmd = SDVO_CMD_SET_CONTRAST; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1955 | sdvo_connector->cur_contrast = temp_value; |
| 1956 | } else if (sdvo_connector->hue_property == property) { |
| 1957 | if (sdvo_connector->cur_hue == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1958 | goto out; |
| 1959 | |
| 1960 | cmd = SDVO_CMD_SET_HUE; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1961 | sdvo_connector->cur_hue = temp_value; |
| 1962 | } else if (sdvo_connector->brightness_property == property) { |
| 1963 | if (sdvo_connector->cur_brightness == temp_value) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1964 | goto out; |
| 1965 | |
| 1966 | cmd = SDVO_CMD_SET_BRIGHTNESS; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1967 | sdvo_connector->cur_brightness = temp_value; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1968 | } |
| 1969 | if (cmd) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 1970 | intel_sdvo_write_cmd(intel_sdvo, cmd, &temp_value, 2); |
| 1971 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1972 | NULL, 0); |
| 1973 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 1974 | DRM_DEBUG_KMS("Incorrect SDVO command \n"); |
| 1975 | return -EINVAL; |
| 1976 | } |
| 1977 | changed = true; |
| 1978 | } |
| 1979 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1980 | if (changed && crtc) |
| 1981 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, |
| 1982 | crtc->y, crtc->fb); |
| 1983 | out: |
| 1984 | return ret; |
| 1985 | } |
| 1986 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1987 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
| 1988 | .dpms = intel_sdvo_dpms, |
| 1989 | .mode_fixup = intel_sdvo_mode_fixup, |
| 1990 | .prepare = intel_encoder_prepare, |
| 1991 | .mode_set = intel_sdvo_mode_set, |
| 1992 | .commit = intel_encoder_commit, |
| 1993 | }; |
| 1994 | |
| 1995 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
Keith Packard | c9fb15f | 2009-05-30 20:42:28 -0700 | [diff] [blame] | 1996 | .dpms = drm_helper_connector_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1997 | .detect = intel_sdvo_detect, |
| 1998 | .fill_modes = drm_helper_probe_single_connector_modes, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1999 | .set_property = intel_sdvo_set_property, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2000 | .destroy = intel_sdvo_destroy, |
| 2001 | }; |
| 2002 | |
| 2003 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
| 2004 | .get_modes = intel_sdvo_get_modes, |
| 2005 | .mode_valid = intel_sdvo_mode_valid, |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2006 | .best_encoder = intel_attached_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2007 | }; |
| 2008 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 2009 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2010 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2011 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2012 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2013 | if (intel_sdvo->analog_ddc_bus) |
| 2014 | intel_i2c_destroy(intel_sdvo->analog_ddc_bus); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2015 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2016 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2017 | drm_mode_destroy(encoder->dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2018 | intel_sdvo->sdvo_lvds_fixed_mode); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2019 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2020 | intel_encoder_destroy(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2021 | } |
| 2022 | |
| 2023 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
| 2024 | .destroy = intel_sdvo_enc_destroy, |
| 2025 | }; |
| 2026 | |
| 2027 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2028 | /** |
| 2029 | * Choose the appropriate DDC bus for control bus switch command for this |
| 2030 | * SDVO output based on the controlled output. |
| 2031 | * |
| 2032 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
| 2033 | * outputs, then LVDS outputs. |
| 2034 | */ |
| 2035 | static void |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2036 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2037 | struct intel_sdvo *sdvo, u32 reg) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2038 | { |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2039 | struct sdvo_device_mapping *mapping; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2040 | |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2041 | if (IS_SDVOB(reg)) |
| 2042 | mapping = &(dev_priv->sdvo_mappings[0]); |
| 2043 | else |
| 2044 | mapping = &(dev_priv->sdvo_mappings[1]); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2045 | |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 2046 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2047 | } |
| 2048 | |
| 2049 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2050 | intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2051 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2052 | uint8_t status; |
| 2053 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2054 | if (device == 0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2055 | intel_sdvo_set_target_output(intel_sdvo, SDVO_OUTPUT_TMDS0); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2056 | else |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2057 | intel_sdvo_set_target_output(intel_sdvo, SDVO_OUTPUT_TMDS1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2058 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2059 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ENCODE, NULL, 0); |
| 2060 | status = intel_sdvo_read_response(intel_sdvo, &intel_sdvo->is_hdmi, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2061 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 2062 | return false; |
| 2063 | return true; |
| 2064 | } |
| 2065 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2066 | static struct intel_sdvo * |
| 2067 | intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan) |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2068 | { |
| 2069 | struct drm_device *dev = chan->drm_dev; |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2070 | struct drm_encoder *encoder; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2071 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2072 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2073 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
| 2074 | if (intel_sdvo->base.ddc_bus == &chan->adapter) |
| 2075 | return intel_sdvo; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2076 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2077 | |
| 2078 | return NULL;; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2079 | } |
| 2080 | |
| 2081 | static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap, |
| 2082 | struct i2c_msg msgs[], int num) |
| 2083 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2084 | struct intel_sdvo *intel_sdvo; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2085 | struct i2c_algo_bit_data *algo_data; |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 2086 | const struct i2c_algorithm *algo; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2087 | |
| 2088 | algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2089 | intel_sdvo = |
| 2090 | intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *) |
| 2091 | (algo_data->data)); |
| 2092 | if (intel_sdvo == NULL) |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2093 | return -EINVAL; |
| 2094 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2095 | algo = intel_sdvo->base.i2c_bus->algo; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2096 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2097 | intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus); |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2098 | return algo->master_xfer(i2c_adap, msgs, num); |
| 2099 | } |
| 2100 | |
| 2101 | static struct i2c_algorithm intel_sdvo_i2c_bit_algo = { |
| 2102 | .master_xfer = intel_sdvo_master_xfer, |
| 2103 | }; |
| 2104 | |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2105 | static u8 |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2106 | intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2107 | { |
| 2108 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2109 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
| 2110 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2111 | if (IS_SDVOB(sdvo_reg)) { |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2112 | my_mapping = &dev_priv->sdvo_mappings[0]; |
| 2113 | other_mapping = &dev_priv->sdvo_mappings[1]; |
| 2114 | } else { |
| 2115 | my_mapping = &dev_priv->sdvo_mappings[1]; |
| 2116 | other_mapping = &dev_priv->sdvo_mappings[0]; |
| 2117 | } |
| 2118 | |
| 2119 | /* If the BIOS described our SDVO device, take advantage of it. */ |
| 2120 | if (my_mapping->slave_addr) |
| 2121 | return my_mapping->slave_addr; |
| 2122 | |
| 2123 | /* If the BIOS only described a different SDVO device, use the |
| 2124 | * address that it isn't using. |
| 2125 | */ |
| 2126 | if (other_mapping->slave_addr) { |
| 2127 | if (other_mapping->slave_addr == 0x70) |
| 2128 | return 0x72; |
| 2129 | else |
| 2130 | return 0x70; |
| 2131 | } |
| 2132 | |
| 2133 | /* No SDVO device info is found for another DVO port, |
| 2134 | * so use mapping assumption we had before BIOS parsing. |
| 2135 | */ |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2136 | if (IS_SDVOB(sdvo_reg)) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2137 | return 0x70; |
| 2138 | else |
| 2139 | return 0x72; |
| 2140 | } |
| 2141 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2142 | static bool |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2143 | intel_sdvo_connector_alloc (struct intel_connector **ret) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2144 | { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2145 | struct intel_connector *intel_connector; |
| 2146 | struct intel_sdvo_connector *sdvo_connector; |
| 2147 | |
| 2148 | *ret = kzalloc(sizeof(*intel_connector) + |
| 2149 | sizeof(*sdvo_connector), GFP_KERNEL); |
| 2150 | if (!*ret) |
| 2151 | return false; |
| 2152 | |
| 2153 | intel_connector = *ret; |
| 2154 | sdvo_connector = (struct intel_sdvo_connector *)(intel_connector + 1); |
| 2155 | intel_connector->dev_priv = sdvo_connector; |
| 2156 | |
| 2157 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2158 | } |
| 2159 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2160 | static void |
| 2161 | intel_sdvo_connector_create (struct drm_encoder *encoder, |
| 2162 | struct drm_connector *connector) |
| 2163 | { |
| 2164 | drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs, |
| 2165 | connector->connector_type); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2166 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2167 | drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs); |
| 2168 | |
| 2169 | connector->interlace_allowed = 0; |
| 2170 | connector->doublescan_allowed = 0; |
| 2171 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; |
| 2172 | |
| 2173 | drm_mode_connector_attach_encoder(connector, encoder); |
| 2174 | drm_sysfs_connector_add(connector); |
| 2175 | } |
| 2176 | |
| 2177 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2178 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2179 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2180 | struct drm_encoder *encoder = &intel_sdvo->base.enc; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2181 | struct drm_connector *connector; |
| 2182 | struct intel_connector *intel_connector; |
| 2183 | struct intel_sdvo_connector *sdvo_connector; |
| 2184 | |
| 2185 | if (!intel_sdvo_connector_alloc(&intel_connector)) |
| 2186 | return false; |
| 2187 | |
| 2188 | sdvo_connector = intel_connector->dev_priv; |
| 2189 | |
| 2190 | if (device == 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2191 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2192 | sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
| 2193 | } else if (device == 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2194 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2195 | sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
| 2196 | } |
| 2197 | |
| 2198 | connector = &intel_connector->base; |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 2199 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2200 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
| 2201 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
| 2202 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2203 | if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode) |
| 2204 | && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device) |
| 2205 | && intel_sdvo->is_hdmi) { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2206 | /* enable hdmi encoding mode if supported */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2207 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
| 2208 | intel_sdvo_set_colorimetry(intel_sdvo, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2209 | SDVO_COLORIMETRY_RGB256); |
| 2210 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
| 2211 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2212 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2213 | (1 << INTEL_ANALOG_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2214 | |
| 2215 | intel_sdvo_connector_create(encoder, connector); |
| 2216 | |
| 2217 | return true; |
| 2218 | } |
| 2219 | |
| 2220 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2221 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2222 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2223 | struct drm_encoder *encoder = &intel_sdvo->base.enc; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2224 | struct drm_connector *connector; |
| 2225 | struct intel_connector *intel_connector; |
| 2226 | struct intel_sdvo_connector *sdvo_connector; |
| 2227 | |
| 2228 | if (!intel_sdvo_connector_alloc(&intel_connector)) |
| 2229 | return false; |
| 2230 | |
| 2231 | connector = &intel_connector->base; |
| 2232 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
| 2233 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
| 2234 | sdvo_connector = intel_connector->dev_priv; |
| 2235 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2236 | intel_sdvo->controlled_output |= type; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2237 | sdvo_connector->output_flag = type; |
| 2238 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2239 | intel_sdvo->is_tv = true; |
| 2240 | intel_sdvo->base.needs_tv_clock = true; |
| 2241 | intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2242 | |
| 2243 | intel_sdvo_connector_create(encoder, connector); |
| 2244 | |
| 2245 | intel_sdvo_tv_create_property(connector, type); |
| 2246 | |
| 2247 | intel_sdvo_create_enhance_property(connector); |
| 2248 | |
| 2249 | return true; |
| 2250 | } |
| 2251 | |
| 2252 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2253 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2254 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2255 | struct drm_encoder *encoder = &intel_sdvo->base.enc; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2256 | struct drm_connector *connector; |
| 2257 | struct intel_connector *intel_connector; |
| 2258 | struct intel_sdvo_connector *sdvo_connector; |
| 2259 | |
| 2260 | if (!intel_sdvo_connector_alloc(&intel_connector)) |
| 2261 | return false; |
| 2262 | |
| 2263 | connector = &intel_connector->base; |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 2264 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2265 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
| 2266 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
| 2267 | sdvo_connector = intel_connector->dev_priv; |
| 2268 | |
| 2269 | if (device == 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2270 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2271 | sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
| 2272 | } else if (device == 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2273 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2274 | sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
| 2275 | } |
| 2276 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2277 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2278 | (1 << INTEL_ANALOG_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2279 | |
| 2280 | intel_sdvo_connector_create(encoder, connector); |
| 2281 | return true; |
| 2282 | } |
| 2283 | |
| 2284 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2285 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2286 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2287 | struct drm_encoder *encoder = &intel_sdvo->base.enc; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2288 | struct drm_connector *connector; |
| 2289 | struct intel_connector *intel_connector; |
| 2290 | struct intel_sdvo_connector *sdvo_connector; |
| 2291 | |
| 2292 | if (!intel_sdvo_connector_alloc(&intel_connector)) |
| 2293 | return false; |
| 2294 | |
| 2295 | connector = &intel_connector->base; |
| 2296 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
| 2297 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
| 2298 | sdvo_connector = intel_connector->dev_priv; |
| 2299 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2300 | intel_sdvo->is_lvds = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2301 | |
| 2302 | if (device == 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2303 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2304 | sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
| 2305 | } else if (device == 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2306 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2307 | sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
| 2308 | } |
| 2309 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2310 | intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | |
| 2311 | (1 << INTEL_SDVO_LVDS_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2312 | |
| 2313 | intel_sdvo_connector_create(encoder, connector); |
| 2314 | intel_sdvo_create_enhance_property(connector); |
| 2315 | return true; |
| 2316 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2317 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2318 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2319 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2320 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2321 | intel_sdvo->is_tv = false; |
| 2322 | intel_sdvo->base.needs_tv_clock = false; |
| 2323 | intel_sdvo->is_lvds = false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2324 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2325 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2326 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2327 | if (flags & SDVO_OUTPUT_TMDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2328 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2329 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2330 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2331 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2332 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2333 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2334 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2335 | /* TV has no XXX1 function block */ |
Zhenyu Wang | a1f4b7ff | 2010-03-29 23:16:13 +0800 | [diff] [blame] | 2336 | if (flags & SDVO_OUTPUT_SVID0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2337 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2338 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2339 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2340 | if (flags & SDVO_OUTPUT_CVBS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2341 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2342 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2343 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2344 | if (flags & SDVO_OUTPUT_RGB0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2345 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2346 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2347 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2348 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2349 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2350 | return false; |
Zhao Yakui | 2dd8738 | 2010-01-27 16:32:46 +0800 | [diff] [blame] | 2351 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2352 | if (flags & SDVO_OUTPUT_LVDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2353 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2354 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2355 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2356 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2357 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2358 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2359 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2360 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2361 | unsigned char bytes[2]; |
| 2362 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2363 | intel_sdvo->controlled_output = 0; |
| 2364 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2365 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2366 | SDVO_NAME(intel_sdvo), |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2367 | bytes[0], bytes[1]); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2368 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2369 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2370 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2371 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2372 | return true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2373 | } |
| 2374 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2375 | static void intel_sdvo_tv_create_property(struct drm_connector *connector, int type) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2376 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2377 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2378 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2379 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 2380 | struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2381 | struct intel_sdvo_tv_format format; |
| 2382 | uint32_t format_map, i; |
| 2383 | uint8_t status; |
| 2384 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2385 | intel_sdvo_set_target_output(intel_sdvo, type); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2386 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2387 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2388 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2389 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2390 | &format, sizeof(format)); |
| 2391 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 2392 | return; |
| 2393 | |
| 2394 | memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ? |
| 2395 | sizeof(format_map) : sizeof(format)); |
| 2396 | |
| 2397 | if (format_map == 0) |
| 2398 | return; |
| 2399 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2400 | sdvo_connector->format_supported_num = 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2401 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
| 2402 | if (format_map & (1 << i)) { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2403 | sdvo_connector->tv_format_supported |
| 2404 | [sdvo_connector->format_supported_num++] = |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2405 | tv_format_names[i]; |
| 2406 | } |
| 2407 | |
| 2408 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2409 | sdvo_connector->tv_format_property = |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2410 | drm_property_create( |
| 2411 | connector->dev, DRM_MODE_PROP_ENUM, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2412 | "mode", sdvo_connector->format_supported_num); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2413 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2414 | for (i = 0; i < sdvo_connector->format_supported_num; i++) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2415 | drm_property_add_enum( |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2416 | sdvo_connector->tv_format_property, i, |
| 2417 | i, sdvo_connector->tv_format_supported[i]); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2418 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2419 | intel_sdvo->tv_format_name = sdvo_connector->tv_format_supported[0]; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2420 | drm_connector_attach_property( |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2421 | connector, sdvo_connector->tv_format_property, 0); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2422 | |
| 2423 | } |
| 2424 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2425 | static void intel_sdvo_create_enhance_property(struct drm_connector *connector) |
| 2426 | { |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 2427 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2428 | struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2429 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2430 | struct intel_sdvo_connector *intel_sdvo_connector = intel_connector->dev_priv; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2431 | struct intel_sdvo_enhancements_reply sdvo_data; |
| 2432 | struct drm_device *dev = connector->dev; |
| 2433 | uint8_t status; |
| 2434 | uint16_t response, data_value[2]; |
| 2435 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2436 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2437 | NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2438 | status = intel_sdvo_read_response(intel_sdvo, &sdvo_data, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2439 | sizeof(sdvo_data)); |
| 2440 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2441 | DRM_DEBUG_KMS(" incorrect response is returned\n"); |
| 2442 | return; |
| 2443 | } |
| 2444 | response = *((uint16_t *)&sdvo_data); |
| 2445 | if (!response) { |
| 2446 | DRM_DEBUG_KMS("No enhancement is supported\n"); |
| 2447 | return; |
| 2448 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2449 | if (IS_TV(intel_sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2450 | /* when horizontal overscan is supported, Add the left/right |
| 2451 | * property |
| 2452 | */ |
| 2453 | if (sdvo_data.overscan_h) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2454 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2455 | SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2456 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2457 | &data_value, 4); |
| 2458 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2459 | DRM_DEBUG_KMS("Incorrect SDVO max " |
| 2460 | "h_overscan\n"); |
| 2461 | return; |
| 2462 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2463 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2464 | SDVO_CMD_GET_OVERSCAN_H, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2465 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2466 | &response, 2); |
| 2467 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2468 | DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n"); |
| 2469 | return; |
| 2470 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2471 | intel_sdvo_connector->max_hscan = data_value[0]; |
| 2472 | intel_sdvo_connector->left_margin = data_value[0] - response; |
| 2473 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; |
| 2474 | intel_sdvo_connector->left_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2475 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2476 | "left_margin", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2477 | intel_sdvo_connector->left_property->values[0] = 0; |
| 2478 | intel_sdvo_connector->left_property->values[1] = data_value[0]; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2479 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2480 | intel_sdvo_connector->left_property, |
| 2481 | intel_sdvo_connector->left_margin); |
| 2482 | intel_sdvo_connector->right_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2483 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2484 | "right_margin", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2485 | intel_sdvo_connector->right_property->values[0] = 0; |
| 2486 | intel_sdvo_connector->right_property->values[1] = data_value[0]; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2487 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2488 | intel_sdvo_connector->right_property, |
| 2489 | intel_sdvo_connector->right_margin); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2490 | DRM_DEBUG_KMS("h_overscan: max %d, " |
| 2491 | "default %d, current %d\n", |
| 2492 | data_value[0], data_value[1], response); |
| 2493 | } |
| 2494 | if (sdvo_data.overscan_v) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2495 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2496 | SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2497 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2498 | &data_value, 4); |
| 2499 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2500 | DRM_DEBUG_KMS("Incorrect SDVO max " |
| 2501 | "v_overscan\n"); |
| 2502 | return; |
| 2503 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2504 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2505 | SDVO_CMD_GET_OVERSCAN_V, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2506 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2507 | &response, 2); |
| 2508 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2509 | DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n"); |
| 2510 | return; |
| 2511 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2512 | intel_sdvo_connector->max_vscan = data_value[0]; |
| 2513 | intel_sdvo_connector->top_margin = data_value[0] - response; |
| 2514 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; |
| 2515 | intel_sdvo_connector->top_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2516 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2517 | "top_margin", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2518 | intel_sdvo_connector->top_property->values[0] = 0; |
| 2519 | intel_sdvo_connector->top_property->values[1] = data_value[0]; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2520 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2521 | intel_sdvo_connector->top_property, |
| 2522 | intel_sdvo_connector->top_margin); |
| 2523 | intel_sdvo_connector->bottom_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2524 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2525 | "bottom_margin", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2526 | intel_sdvo_connector->bottom_property->values[0] = 0; |
| 2527 | intel_sdvo_connector->bottom_property->values[1] = data_value[0]; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2528 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2529 | intel_sdvo_connector->bottom_property, |
| 2530 | intel_sdvo_connector->bottom_margin); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2531 | DRM_DEBUG_KMS("v_overscan: max %d, " |
| 2532 | "default %d, current %d\n", |
| 2533 | data_value[0], data_value[1], response); |
| 2534 | } |
| 2535 | if (sdvo_data.position_h) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2536 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2537 | SDVO_CMD_GET_MAX_POSITION_H, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2538 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2539 | &data_value, 4); |
| 2540 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2541 | DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n"); |
| 2542 | return; |
| 2543 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2544 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2545 | SDVO_CMD_GET_POSITION_H, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2546 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2547 | &response, 2); |
| 2548 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2549 | DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n"); |
| 2550 | return; |
| 2551 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2552 | intel_sdvo_connector->max_hpos = data_value[0]; |
| 2553 | intel_sdvo_connector->cur_hpos = response; |
| 2554 | intel_sdvo_connector->hpos_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2555 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2556 | "hpos", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2557 | intel_sdvo_connector->hpos_property->values[0] = 0; |
| 2558 | intel_sdvo_connector->hpos_property->values[1] = data_value[0]; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2559 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2560 | intel_sdvo_connector->hpos_property, |
| 2561 | intel_sdvo_connector->cur_hpos); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2562 | DRM_DEBUG_KMS("h_position: max %d, " |
| 2563 | "default %d, current %d\n", |
| 2564 | data_value[0], data_value[1], response); |
| 2565 | } |
| 2566 | if (sdvo_data.position_v) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2567 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2568 | SDVO_CMD_GET_MAX_POSITION_V, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2569 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2570 | &data_value, 4); |
| 2571 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2572 | DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n"); |
| 2573 | return; |
| 2574 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2575 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2576 | SDVO_CMD_GET_POSITION_V, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2577 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2578 | &response, 2); |
| 2579 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2580 | DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n"); |
| 2581 | return; |
| 2582 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2583 | intel_sdvo_connector->max_vpos = data_value[0]; |
| 2584 | intel_sdvo_connector->cur_vpos = response; |
| 2585 | intel_sdvo_connector->vpos_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2586 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2587 | "vpos", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2588 | intel_sdvo_connector->vpos_property->values[0] = 0; |
| 2589 | intel_sdvo_connector->vpos_property->values[1] = data_value[0]; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2590 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2591 | intel_sdvo_connector->vpos_property, |
| 2592 | intel_sdvo_connector->cur_vpos); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2593 | DRM_DEBUG_KMS("v_position: max %d, " |
| 2594 | "default %d, current %d\n", |
| 2595 | data_value[0], data_value[1], response); |
| 2596 | } |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2597 | if (sdvo_data.saturation) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2598 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2599 | SDVO_CMD_GET_MAX_SATURATION, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2600 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2601 | &data_value, 4); |
| 2602 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2603 | DRM_DEBUG_KMS("Incorrect SDVO Max sat\n"); |
| 2604 | return; |
| 2605 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2606 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2607 | SDVO_CMD_GET_SATURATION, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2608 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2609 | &response, 2); |
| 2610 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2611 | DRM_DEBUG_KMS("Incorrect SDVO get sat\n"); |
| 2612 | return; |
| 2613 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2614 | intel_sdvo_connector->max_saturation = data_value[0]; |
| 2615 | intel_sdvo_connector->cur_saturation = response; |
| 2616 | intel_sdvo_connector->saturation_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2617 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2618 | "saturation", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2619 | intel_sdvo_connector->saturation_property->values[0] = 0; |
| 2620 | intel_sdvo_connector->saturation_property->values[1] = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2621 | data_value[0]; |
| 2622 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2623 | intel_sdvo_connector->saturation_property, |
| 2624 | intel_sdvo_connector->cur_saturation); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2625 | DRM_DEBUG_KMS("saturation: max %d, " |
| 2626 | "default %d, current %d\n", |
| 2627 | data_value[0], data_value[1], response); |
| 2628 | } |
| 2629 | if (sdvo_data.contrast) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2630 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2631 | SDVO_CMD_GET_MAX_CONTRAST, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2632 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2633 | &data_value, 4); |
| 2634 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2635 | DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n"); |
| 2636 | return; |
| 2637 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2638 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2639 | SDVO_CMD_GET_CONTRAST, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2640 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2641 | &response, 2); |
| 2642 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2643 | DRM_DEBUG_KMS("Incorrect SDVO get contrast\n"); |
| 2644 | return; |
| 2645 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2646 | intel_sdvo_connector->max_contrast = data_value[0]; |
| 2647 | intel_sdvo_connector->cur_contrast = response; |
| 2648 | intel_sdvo_connector->contrast_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2649 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2650 | "contrast", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2651 | intel_sdvo_connector->contrast_property->values[0] = 0; |
| 2652 | intel_sdvo_connector->contrast_property->values[1] = data_value[0]; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2653 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2654 | intel_sdvo_connector->contrast_property, |
| 2655 | intel_sdvo_connector->cur_contrast); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2656 | DRM_DEBUG_KMS("contrast: max %d, " |
| 2657 | "default %d, current %d\n", |
| 2658 | data_value[0], data_value[1], response); |
| 2659 | } |
| 2660 | if (sdvo_data.hue) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2661 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2662 | SDVO_CMD_GET_MAX_HUE, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2663 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2664 | &data_value, 4); |
| 2665 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2666 | DRM_DEBUG_KMS("Incorrect SDVO Max hue\n"); |
| 2667 | return; |
| 2668 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2669 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2670 | SDVO_CMD_GET_HUE, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2671 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2672 | &response, 2); |
| 2673 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2674 | DRM_DEBUG_KMS("Incorrect SDVO get hue\n"); |
| 2675 | return; |
| 2676 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2677 | intel_sdvo_connector->max_hue = data_value[0]; |
| 2678 | intel_sdvo_connector->cur_hue = response; |
| 2679 | intel_sdvo_connector->hue_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2680 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2681 | "hue", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2682 | intel_sdvo_connector->hue_property->values[0] = 0; |
| 2683 | intel_sdvo_connector->hue_property->values[1] = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2684 | data_value[0]; |
| 2685 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2686 | intel_sdvo_connector->hue_property, |
| 2687 | intel_sdvo_connector->cur_hue); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2688 | DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n", |
| 2689 | data_value[0], data_value[1], response); |
| 2690 | } |
| 2691 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2692 | if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2693 | if (sdvo_data.brightness) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2694 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2695 | SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2696 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2697 | &data_value, 4); |
| 2698 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2699 | DRM_DEBUG_KMS("Incorrect SDVO Max bright\n"); |
| 2700 | return; |
| 2701 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2702 | intel_sdvo_write_cmd(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2703 | SDVO_CMD_GET_BRIGHTNESS, NULL, 0); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2704 | status = intel_sdvo_read_response(intel_sdvo, |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2705 | &response, 2); |
| 2706 | if (status != SDVO_CMD_STATUS_SUCCESS) { |
| 2707 | DRM_DEBUG_KMS("Incorrect SDVO get brigh\n"); |
| 2708 | return; |
| 2709 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2710 | intel_sdvo_connector->max_brightness = data_value[0]; |
| 2711 | intel_sdvo_connector->cur_brightness = response; |
| 2712 | intel_sdvo_connector->brightness_property = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2713 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2714 | "brightness", 2); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2715 | intel_sdvo_connector->brightness_property->values[0] = 0; |
| 2716 | intel_sdvo_connector->brightness_property->values[1] = |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2717 | data_value[0]; |
| 2718 | drm_connector_attach_property(connector, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2719 | intel_sdvo_connector->brightness_property, |
| 2720 | intel_sdvo_connector->cur_brightness); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2721 | DRM_DEBUG_KMS("brightness: max %d, " |
| 2722 | "default %d, current %d\n", |
| 2723 | data_value[0], data_value[1], response); |
| 2724 | } |
| 2725 | } |
| 2726 | return; |
| 2727 | } |
| 2728 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2729 | bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2730 | { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2731 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2732 | struct intel_encoder *intel_encoder; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2733 | struct intel_sdvo *intel_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2734 | u8 ch[0x40]; |
| 2735 | int i; |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2736 | u32 i2c_reg, ddc_reg, analog_ddc_reg; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2737 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2738 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
| 2739 | if (!intel_sdvo) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2740 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2741 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2742 | intel_sdvo->sdvo_reg = sdvo_reg; |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2743 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2744 | intel_encoder = &intel_sdvo->base; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2745 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2746 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2747 | if (HAS_PCH_SPLIT(dev)) { |
| 2748 | i2c_reg = PCH_GPIOE; |
| 2749 | ddc_reg = PCH_GPIOE; |
| 2750 | analog_ddc_reg = PCH_GPIOA; |
| 2751 | } else { |
| 2752 | i2c_reg = GPIOE; |
| 2753 | ddc_reg = GPIOE; |
| 2754 | analog_ddc_reg = GPIOA; |
| 2755 | } |
| 2756 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2757 | /* setup the DDC bus. */ |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2758 | if (IS_SDVOB(sdvo_reg)) |
| 2759 | intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB"); |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2760 | else |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2761 | intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC"); |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2762 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2763 | if (!intel_encoder->i2c_bus) |
Jonas Bonn | ad5b2a6 | 2009-05-15 09:10:41 +0200 | [diff] [blame] | 2764 | goto err_inteloutput; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2765 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2766 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2767 | |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2768 | /* Save the bit-banging i2c functionality for use by the DDC wrapper */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2769 | intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2770 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2771 | /* Read the regs to test if we can talk to the device */ |
| 2772 | for (i = 0; i < 0x40; i++) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2773 | if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2774 | DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2775 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2776 | goto err_i2c; |
| 2777 | } |
| 2778 | } |
| 2779 | |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2780 | /* setup the DDC bus. */ |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2781 | if (IS_SDVOB(sdvo_reg)) { |
| 2782 | intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS"); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2783 | intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 2784 | "SDVOB/VGA DDC BUS"); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2785 | dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 2786 | } else { |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2787 | intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS"); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2788 | intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 2789 | "SDVOC/VGA DDC BUS"); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2790 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 2791 | } |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2792 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2793 | if (intel_encoder->ddc_bus == NULL) |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2794 | goto err_i2c; |
| 2795 | |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2796 | /* Wrap with our custom algo which switches to DDC mode */ |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2797 | intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2798 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2799 | /* encoder type will be decided later */ |
| 2800 | drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0); |
| 2801 | drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs); |
| 2802 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 2803 | /* In default case sdvo lvds is false */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2804 | intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2805 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2806 | if (intel_sdvo_output_setup(intel_sdvo, |
| 2807 | intel_sdvo->caps.output_flags) != true) { |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2808 | DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2809 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2810 | goto err_i2c; |
| 2811 | } |
| 2812 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2813 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2814 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2815 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2816 | intel_sdvo_set_target_input(intel_sdvo, true, false); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2817 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2818 | intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
| 2819 | &intel_sdvo->pixel_clock_min, |
| 2820 | &intel_sdvo->pixel_clock_max); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2821 | |
| 2822 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2823 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2824 | "clock range %dMHz - %dMHz, " |
| 2825 | "input 1: %c, input 2: %c, " |
| 2826 | "output 1: %c, output 2: %c\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2827 | SDVO_NAME(intel_sdvo), |
| 2828 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, |
| 2829 | intel_sdvo->caps.device_rev_id, |
| 2830 | intel_sdvo->pixel_clock_min / 1000, |
| 2831 | intel_sdvo->pixel_clock_max / 1000, |
| 2832 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
| 2833 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2834 | /* check currently supported outputs */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2835 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2836 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2837 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2838 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
| 2839 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2840 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2841 | |
| 2842 | err_i2c: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2843 | if (intel_sdvo->analog_ddc_bus != NULL) |
| 2844 | intel_i2c_destroy(intel_sdvo->analog_ddc_bus); |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2845 | if (intel_encoder->ddc_bus != NULL) |
| 2846 | intel_i2c_destroy(intel_encoder->ddc_bus); |
| 2847 | if (intel_encoder->i2c_bus != NULL) |
| 2848 | intel_i2c_destroy(intel_encoder->i2c_bus); |
Jonas Bonn | ad5b2a6 | 2009-05-15 09:10:41 +0200 | [diff] [blame] | 2849 | err_inteloutput: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame^] | 2850 | kfree(intel_sdvo); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2851 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2852 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2853 | } |