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Dmitry Baryshkovf024ff12008-06-27 10:37:57 +01001#ifndef MFD_TMIO_H
2#define MFD_TMIO_H
3
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +01004#include <linux/device.h>
Dmitry Baryshkovb53cde32008-10-15 22:03:55 -07005#include <linux/fb.h>
Ian Molton64e88672010-01-06 13:51:48 +01006#include <linux/io.h>
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +01007#include <linux/jiffies.h>
Kuninori Morimotobbf02082014-09-08 23:45:25 -07008#include <linux/mmc/card.h>
Ian Molton64e88672010-01-06 13:51:48 +01009#include <linux/platform_device.h>
Guennadi Liakhovetski7311bef2011-05-11 16:51:11 +000010#include <linux/pm_runtime.h>
Dmitry Baryshkovb53cde32008-10-15 22:03:55 -070011
Ian Moltond3a2f712008-07-31 20:44:28 +020012#define tmio_ioread8(addr) readb(addr)
13#define tmio_ioread16(addr) readw(addr)
14#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
15#define tmio_ioread32(addr) \
16 (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
17
18#define tmio_iowrite8(val, addr) writeb((val), (addr))
19#define tmio_iowrite16(val, addr) writew((val), (addr))
20#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
21#define tmio_iowrite32(val, addr) \
22 do { \
23 writew((val), (addr)); \
24 writew((val) >> 16, (addr) + 2); \
25 } while (0)
26
Ian Molton64e88672010-01-06 13:51:48 +010027#define CNF_CMD 0x04
28#define CNF_CTL_BASE 0x10
29#define CNF_INT_PIN 0x3d
30#define CNF_STOP_CLK_CTL 0x40
31#define CNF_GCLK_CTL 0x41
32#define CNF_SD_CLK_MODE 0x42
33#define CNF_PIN_STATUS 0x44
34#define CNF_PWR_CTL_1 0x48
35#define CNF_PWR_CTL_2 0x49
36#define CNF_PWR_CTL_3 0x4a
37#define CNF_CARD_DETECT_MODE 0x4c
38#define CNF_SD_SLOT 0x50
39#define CNF_EXT_GCLK_CTL_1 0xf0
40#define CNF_EXT_GCLK_CTL_2 0xf1
41#define CNF_EXT_GCLK_CTL_3 0xf9
42#define CNF_SD_LED_EN_1 0xfa
43#define CNF_SD_LED_EN_2 0xfe
44
45#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
46
47#define sd_config_write8(base, shift, reg, val) \
48 tmio_iowrite8((val), (base) + ((reg) << (shift)))
49#define sd_config_write16(base, shift, reg, val) \
50 tmio_iowrite16((val), (base) + ((reg) << (shift)))
51#define sd_config_write32(base, shift, reg, val) \
52 do { \
53 tmio_iowrite16((val), (base) + ((reg) << (shift))); \
54 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
55 } while (0)
56
Guennadi Liakhovetskiac8fb3e2010-05-19 18:36:02 +000057/* tmio MMC platform flags */
58#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
Yusuke Godaf1334fb2010-08-30 11:50:19 +010059/*
60 * Some controllers can support a 2-byte block size when the bus width
61 * is configured in 4-bit mode.
62 */
63#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
Arnd Hannemann845ecd22010-12-28 23:22:31 +010064/*
65 * Some controllers can support SDIO IRQ signalling.
66 */
67#define TMIO_MMC_SDIO_IRQ (1 << 2)
Wolfram Sang04e24b82016-01-19 12:28:31 +010068
69/* Some controllers don't need to wait 10ms for clock changes */
70#define TMIO_MMC_FAST_CLK_CHG (1 << 3)
71
Guennadi Liakhovetski7311bef2011-05-11 16:51:11 +000072/*
Simon Horman973ed3a2011-06-21 08:00:10 +090073 * Some controllers require waiting for the SD bus to become
74 * idle before writing to some registers.
75 */
76#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +010077/*
78 * A GPIO is used for card hotplug detection. We need an extra flag for this,
79 * because 0 is a valid GPIO number too, and requiring users to specify
80 * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
81 */
82#define TMIO_MMC_USE_GPIO_CD (1 << 5)
Guennadi Liakhovetskiac8fb3e2010-05-19 18:36:02 +000083
Kuninori Morimoto5d60e502013-11-20 00:31:06 -080084/*
85 * Some controllers doesn't have over 0x100 register.
86 * it is used to checking accessibility of
87 * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
88 */
89#define TMIO_MMC_HAVE_HIGH_REG (1 << 6)
90
Shinobu Ueharab8d11962014-08-24 20:00:25 -070091/*
92 * Some controllers have CMD12 automatically
93 * issue/non-issue register
94 */
95#define TMIO_MMC_HAVE_CMD12_CTRL (1 << 7)
96
Shinobu Uehara6b987572014-08-24 20:00:52 -070097/*
98 * Some controllers needs to set 1 on SDIO status reserved bits
99 */
100#define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8)
101
Kuninori Morimotoe85dd042014-08-24 20:01:54 -0700102/*
Shinobu Ueharada29fe22014-08-24 20:03:00 -0700103 * Some controllers allows to set SDx actual clock
104 */
105#define TMIO_MMC_CLK_ACTUAL (1 << 10)
106
Ian Molton64e88672010-01-06 13:51:48 +0100107int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
108int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
109void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
110void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
111
Guennadi Liakhovetski03a06752013-04-26 17:47:17 +0200112struct dma_chan;
113
Dmitry Baryshkovf024ff12008-06-27 10:37:57 +0100114/*
Philipp Zabelf0e46cc2009-06-04 20:12:31 +0200115 * data for the MMC controller
116 */
117struct tmio_mmc_data {
Kuninori Morimotof33c9d62015-02-24 02:06:43 +0000118 void *chan_priv_tx;
119 void *chan_priv_rx;
Magnus Damm707f0b22010-02-17 16:38:14 +0900120 unsigned int hclk;
Yusuke Godab741d442010-02-17 16:37:55 +0900121 unsigned long capabilities;
Guennadi Liakhovetski02cb3222012-05-23 10:44:37 +0200122 unsigned long capabilities2;
Guennadi Liakhovetskiac8fb3e2010-05-19 18:36:02 +0000123 unsigned long flags;
Guennadi Liakhovetskia2b14dc2010-05-19 18:37:25 +0000124 u32 ocr_mask; /* available voltages */
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +0100125 unsigned int cd_gpio;
Kuninori Morimotoe471df02015-01-13 04:58:46 +0000126 int alignment_shift;
Kuninori Morimoto8b4c8f32015-01-13 04:58:56 +0000127 dma_addr_t dma_rx_offset;
Chris Ball9d731e72013-09-06 07:29:05 -0400128 void (*set_pwr)(struct platform_device *host, int state);
Ian Molton64e88672010-01-06 13:51:48 +0100129 void (*set_clk_div)(struct platform_device *host, int state);
Philipp Zabelf0e46cc2009-06-04 20:12:31 +0200130};
131
Guennadi Liakhovetskic8be24c2012-02-09 22:57:09 +0100132/*
Dmitry Baryshkovf024ff12008-06-27 10:37:57 +0100133 * data for the NAND controller
134 */
135struct tmio_nand_data {
136 struct nand_bbt_descr *badblock_pattern;
137 struct mtd_partition *partition;
138 unsigned int num_partitions;
139};
140
Dmitry Baryshkovb53cde32008-10-15 22:03:55 -0700141#define FBIO_TMIO_ACC_WRITE 0x7C639300
142#define FBIO_TMIO_ACC_SYNC 0x7C639301
143
144struct tmio_fb_data {
145 int (*lcd_set_power)(struct platform_device *fb_dev,
146 bool on);
147 int (*lcd_mode)(struct platform_device *fb_dev,
148 const struct fb_videomode *mode);
149 int num_modes;
150 struct fb_videomode *modes;
151
152 /* in mm: size of screen */
153 int height;
154 int width;
155};
156
157
Dmitry Baryshkovf024ff12008-06-27 10:37:57 +0100158#endif