Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Advanced Micro Devices, Inc. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Christian König <deathsimple@vodafone.de> |
| 29 | */ |
| 30 | |
| 31 | #include <linux/firmware.h> |
| 32 | #include <linux/module.h> |
| 33 | #include <drm/drmP.h> |
| 34 | #include <drm/drm.h> |
| 35 | |
| 36 | #include "amdgpu.h" |
| 37 | #include "amdgpu_pm.h" |
| 38 | #include "amdgpu_uvd.h" |
| 39 | #include "cikd.h" |
| 40 | #include "uvd/uvd_4_2_d.h" |
| 41 | |
| 42 | /* 1 second timeout */ |
Christian König | 0808663 | 2016-07-01 17:45:49 +0200 | [diff] [blame] | 43 | #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) |
Christian König | 4cb5877c | 2016-07-26 12:05:40 +0200 | [diff] [blame] | 44 | |
| 45 | /* Firmware versions for VI */ |
| 46 | #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) |
| 47 | #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) |
| 48 | #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) |
| 49 | #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) |
| 50 | |
Sonny Jiang | 8e008dd | 2016-05-11 13:29:48 -0400 | [diff] [blame] | 51 | /* Polaris10/11 firmware version */ |
Christian König | 4cb5877c | 2016-07-26 12:05:40 +0200 | [diff] [blame] | 52 | #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 53 | |
| 54 | /* Firmware Names */ |
| 55 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 56 | #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin" |
Christian König | edf600d | 2016-05-03 15:54:54 +0200 | [diff] [blame] | 57 | #define FIRMWARE_KABINI "radeon/kabini_uvd.bin" |
| 58 | #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin" |
| 59 | #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin" |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 60 | #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin" |
| 61 | #endif |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 62 | #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" |
| 63 | #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" |
David Zhang | 974ee3d | 2015-07-08 17:32:15 +0800 | [diff] [blame] | 64 | #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" |
Samuel Li | a39c8ce | 2015-10-08 16:27:21 -0400 | [diff] [blame] | 65 | #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" |
Flora Cui | 2cc0c0b | 2016-03-14 18:33:29 -0400 | [diff] [blame] | 66 | #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" |
Rex Zhu | 925a51c | 2016-03-23 14:48:03 +0800 | [diff] [blame] | 67 | #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" |
Junwei Zhang | c4642a4 | 2016-12-14 15:32:28 -0500 | [diff] [blame] | 68 | #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 69 | |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 70 | #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" |
| 71 | |
| 72 | #define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00) |
| 73 | #define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00) |
| 74 | #define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00) |
| 75 | #define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00) |
| 76 | #define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00) |
| 77 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 78 | /** |
| 79 | * amdgpu_uvd_cs_ctx - Command submission parser context |
| 80 | * |
| 81 | * Used for emulating virtual memory support on UVD 4.2. |
| 82 | */ |
| 83 | struct amdgpu_uvd_cs_ctx { |
| 84 | struct amdgpu_cs_parser *parser; |
| 85 | unsigned reg, count; |
| 86 | unsigned data0, data1; |
| 87 | unsigned idx; |
| 88 | unsigned ib_idx; |
| 89 | |
| 90 | /* does the IB has a msg command */ |
| 91 | bool has_msg_cmd; |
| 92 | |
| 93 | /* minimum buffer sizes */ |
| 94 | unsigned *buf_sizes; |
| 95 | }; |
| 96 | |
| 97 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 98 | MODULE_FIRMWARE(FIRMWARE_BONAIRE); |
| 99 | MODULE_FIRMWARE(FIRMWARE_KABINI); |
| 100 | MODULE_FIRMWARE(FIRMWARE_KAVERI); |
| 101 | MODULE_FIRMWARE(FIRMWARE_HAWAII); |
| 102 | MODULE_FIRMWARE(FIRMWARE_MULLINS); |
| 103 | #endif |
| 104 | MODULE_FIRMWARE(FIRMWARE_TONGA); |
| 105 | MODULE_FIRMWARE(FIRMWARE_CARRIZO); |
David Zhang | 974ee3d | 2015-07-08 17:32:15 +0800 | [diff] [blame] | 106 | MODULE_FIRMWARE(FIRMWARE_FIJI); |
Samuel Li | a39c8ce | 2015-10-08 16:27:21 -0400 | [diff] [blame] | 107 | MODULE_FIRMWARE(FIRMWARE_STONEY); |
Flora Cui | 2cc0c0b | 2016-03-14 18:33:29 -0400 | [diff] [blame] | 108 | MODULE_FIRMWARE(FIRMWARE_POLARIS10); |
| 109 | MODULE_FIRMWARE(FIRMWARE_POLARIS11); |
Junwei Zhang | c4642a4 | 2016-12-14 15:32:28 -0500 | [diff] [blame] | 110 | MODULE_FIRMWARE(FIRMWARE_POLARIS12); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 111 | |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 112 | MODULE_FIRMWARE(FIRMWARE_VEGA10); |
| 113 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 114 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work); |
| 115 | |
| 116 | int amdgpu_uvd_sw_init(struct amdgpu_device *adev) |
| 117 | { |
Christian König | ead833e | 2016-02-10 14:35:19 +0100 | [diff] [blame] | 118 | struct amdgpu_ring *ring; |
Lucas Stach | 1b1f42d | 2017-12-06 17:49:39 +0100 | [diff] [blame] | 119 | struct drm_sched_rq *rq; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 120 | unsigned long bo_size; |
| 121 | const char *fw_name; |
| 122 | const struct common_firmware_header *hdr; |
| 123 | unsigned version_major, version_minor, family_id; |
| 124 | int i, r; |
| 125 | |
| 126 | INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); |
| 127 | |
| 128 | switch (adev->asic_type) { |
| 129 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 130 | case CHIP_BONAIRE: |
| 131 | fw_name = FIRMWARE_BONAIRE; |
| 132 | break; |
| 133 | case CHIP_KABINI: |
| 134 | fw_name = FIRMWARE_KABINI; |
| 135 | break; |
| 136 | case CHIP_KAVERI: |
| 137 | fw_name = FIRMWARE_KAVERI; |
| 138 | break; |
| 139 | case CHIP_HAWAII: |
| 140 | fw_name = FIRMWARE_HAWAII; |
| 141 | break; |
| 142 | case CHIP_MULLINS: |
| 143 | fw_name = FIRMWARE_MULLINS; |
| 144 | break; |
| 145 | #endif |
| 146 | case CHIP_TONGA: |
| 147 | fw_name = FIRMWARE_TONGA; |
| 148 | break; |
David Zhang | 974ee3d | 2015-07-08 17:32:15 +0800 | [diff] [blame] | 149 | case CHIP_FIJI: |
| 150 | fw_name = FIRMWARE_FIJI; |
| 151 | break; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 152 | case CHIP_CARRIZO: |
| 153 | fw_name = FIRMWARE_CARRIZO; |
| 154 | break; |
Samuel Li | a39c8ce | 2015-10-08 16:27:21 -0400 | [diff] [blame] | 155 | case CHIP_STONEY: |
| 156 | fw_name = FIRMWARE_STONEY; |
| 157 | break; |
Flora Cui | 2cc0c0b | 2016-03-14 18:33:29 -0400 | [diff] [blame] | 158 | case CHIP_POLARIS10: |
| 159 | fw_name = FIRMWARE_POLARIS10; |
Sonny Jiang | 38d7581 | 2015-11-05 15:17:18 -0500 | [diff] [blame] | 160 | break; |
Flora Cui | 2cc0c0b | 2016-03-14 18:33:29 -0400 | [diff] [blame] | 161 | case CHIP_POLARIS11: |
| 162 | fw_name = FIRMWARE_POLARIS11; |
Sonny Jiang | 38d7581 | 2015-11-05 15:17:18 -0500 | [diff] [blame] | 163 | break; |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 164 | case CHIP_VEGA10: |
| 165 | fw_name = FIRMWARE_VEGA10; |
| 166 | break; |
Junwei Zhang | c4642a4 | 2016-12-14 15:32:28 -0500 | [diff] [blame] | 167 | case CHIP_POLARIS12: |
| 168 | fw_name = FIRMWARE_POLARIS12; |
| 169 | break; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 170 | default: |
| 171 | return -EINVAL; |
| 172 | } |
| 173 | |
| 174 | r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); |
| 175 | if (r) { |
| 176 | dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", |
| 177 | fw_name); |
| 178 | return r; |
| 179 | } |
| 180 | |
| 181 | r = amdgpu_ucode_validate(adev->uvd.fw); |
| 182 | if (r) { |
| 183 | dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", |
| 184 | fw_name); |
| 185 | release_firmware(adev->uvd.fw); |
| 186 | adev->uvd.fw = NULL; |
| 187 | return r; |
| 188 | } |
| 189 | |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 190 | /* Set the default UVD handles that the firmware can handle */ |
| 191 | adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; |
| 192 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 193 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; |
| 194 | family_id = le32_to_cpu(hdr->ucode_version) & 0xff; |
| 195 | version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; |
| 196 | version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; |
| 197 | DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", |
| 198 | version_major, version_minor, family_id); |
| 199 | |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 200 | /* |
| 201 | * Limit the number of UVD handles depending on microcode major |
| 202 | * and minor versions. The firmware version which has 40 UVD |
| 203 | * instances support is 1.80. So all subsequent versions should |
| 204 | * also have the same support. |
| 205 | */ |
| 206 | if ((version_major > 0x01) || |
| 207 | ((version_major == 0x01) && (version_minor >= 0x50))) |
| 208 | adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; |
| 209 | |
Sonny Jiang | 562e268 | 2016-04-18 16:05:04 -0400 | [diff] [blame] | 210 | adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | |
| 211 | (family_id << 8)); |
| 212 | |
Sonny Jiang | 8e008dd | 2016-05-11 13:29:48 -0400 | [diff] [blame] | 213 | if ((adev->asic_type == CHIP_POLARIS10 || |
| 214 | adev->asic_type == CHIP_POLARIS11) && |
| 215 | (adev->uvd.fw_version < FW_1_66_16)) |
| 216 | DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", |
| 217 | version_major, version_minor); |
| 218 | |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 219 | bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 220 | + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 221 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) |
| 222 | bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); |
| 223 | |
Christian König | 4b62e69 | 2016-07-25 17:37:38 +0200 | [diff] [blame] | 224 | r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, |
| 225 | AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo, |
| 226 | &adev->uvd.gpu_addr, &adev->uvd.cpu_addr); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 227 | if (r) { |
| 228 | dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); |
| 229 | return r; |
| 230 | } |
| 231 | |
Christian König | ead833e | 2016-02-10 14:35:19 +0100 | [diff] [blame] | 232 | ring = &adev->uvd.ring; |
Lucas Stach | 1b1f42d | 2017-12-06 17:49:39 +0100 | [diff] [blame] | 233 | rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; |
| 234 | r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity, |
Monk Liu | b3eebe3 | 2017-10-23 12:23:29 +0800 | [diff] [blame] | 235 | rq, amdgpu_sched_jobs, NULL); |
Christian König | ead833e | 2016-02-10 14:35:19 +0100 | [diff] [blame] | 236 | if (r != 0) { |
| 237 | DRM_ERROR("Failed setting up UVD run queue.\n"); |
| 238 | return r; |
| 239 | } |
| 240 | |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 241 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 242 | atomic_set(&adev->uvd.handles[i], 0); |
| 243 | adev->uvd.filp[i] = NULL; |
| 244 | } |
| 245 | |
| 246 | /* from uvd v5.0 HW addressing capacity increased to 64 bits */ |
Alex Deucher | 2990a1f | 2017-12-15 16:18:00 -0500 | [diff] [blame] | 247 | if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 248 | adev->uvd.address_64_bit = true; |
| 249 | |
Christian König | 4cb5877c | 2016-07-26 12:05:40 +0200 | [diff] [blame] | 250 | switch (adev->asic_type) { |
| 251 | case CHIP_TONGA: |
| 252 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; |
| 253 | break; |
| 254 | case CHIP_CARRIZO: |
| 255 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; |
| 256 | break; |
| 257 | case CHIP_FIJI: |
| 258 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; |
| 259 | break; |
| 260 | case CHIP_STONEY: |
| 261 | adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; |
| 262 | break; |
| 263 | default: |
| 264 | adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; |
| 265 | } |
| 266 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 267 | return 0; |
| 268 | } |
| 269 | |
| 270 | int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) |
| 271 | { |
Monk Liu | 4ff184d | 2017-09-15 16:43:01 +0800 | [diff] [blame] | 272 | int i; |
Monk Liu | 05f19eb | 2016-05-30 15:13:59 +0800 | [diff] [blame] | 273 | kfree(adev->uvd.saved_bo); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 274 | |
Lucas Stach | 1b1f42d | 2017-12-06 17:49:39 +0100 | [diff] [blame] | 275 | drm_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity); |
Christian König | ead833e | 2016-02-10 14:35:19 +0100 | [diff] [blame] | 276 | |
Junwei Zhang | 8640fae | 2016-09-07 17:14:46 +0800 | [diff] [blame] | 277 | amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo, |
| 278 | &adev->uvd.gpu_addr, |
| 279 | (void **)&adev->uvd.cpu_addr); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 280 | |
| 281 | amdgpu_ring_fini(&adev->uvd.ring); |
| 282 | |
Monk Liu | 4ff184d | 2017-09-15 16:43:01 +0800 | [diff] [blame] | 283 | for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) |
| 284 | amdgpu_ring_fini(&adev->uvd.ring_enc[i]); |
| 285 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 286 | release_firmware(adev->uvd.fw); |
| 287 | |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | int amdgpu_uvd_suspend(struct amdgpu_device *adev) |
| 292 | { |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 293 | unsigned size; |
| 294 | void *ptr; |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 295 | int i; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 296 | |
| 297 | if (adev->uvd.vcpu_bo == NULL) |
| 298 | return 0; |
| 299 | |
Jim Qu | 8daf94e | 2017-12-15 15:27:57 +0800 | [diff] [blame] | 300 | cancel_delayed_work_sync(&adev->uvd.idle_work); |
| 301 | |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 302 | for (i = 0; i < adev->uvd.max_handles; ++i) |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 303 | if (atomic_read(&adev->uvd.handles[i])) |
| 304 | break; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 305 | |
James Zhu | ec7549df | 2018-03-06 14:43:50 -0500 | [diff] [blame^] | 306 | if (i == adev->uvd.max_handles) |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 307 | return 0; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 308 | |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 309 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 310 | ptr = adev->uvd.cpu_addr; |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 311 | |
| 312 | adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL); |
| 313 | if (!adev->uvd.saved_bo) |
| 314 | return -ENOMEM; |
| 315 | |
Christian König | ba0b227 | 2016-08-23 11:00:17 +0200 | [diff] [blame] | 316 | memcpy_fromio(adev->uvd.saved_bo, ptr, size); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 317 | |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | int amdgpu_uvd_resume(struct amdgpu_device *adev) |
| 322 | { |
| 323 | unsigned size; |
| 324 | void *ptr; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 325 | |
| 326 | if (adev->uvd.vcpu_bo == NULL) |
| 327 | return -EINVAL; |
| 328 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 329 | size = amdgpu_bo_size(adev->uvd.vcpu_bo); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 330 | ptr = adev->uvd.cpu_addr; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 331 | |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 332 | if (adev->uvd.saved_bo != NULL) { |
Christian König | ba0b227 | 2016-08-23 11:00:17 +0200 | [diff] [blame] | 333 | memcpy_toio(ptr, adev->uvd.saved_bo, size); |
Leo Liu | 3f99dd8 | 2016-04-01 10:36:06 -0400 | [diff] [blame] | 334 | kfree(adev->uvd.saved_bo); |
| 335 | adev->uvd.saved_bo = NULL; |
Leo Liu | d23be4e | 2016-04-04 10:55:43 -0400 | [diff] [blame] | 336 | } else { |
| 337 | const struct common_firmware_header *hdr; |
| 338 | unsigned offset; |
| 339 | |
| 340 | hdr = (const struct common_firmware_header *)adev->uvd.fw->data; |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 341 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
| 342 | offset = le32_to_cpu(hdr->ucode_array_offset_bytes); |
| 343 | memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset, |
| 344 | le32_to_cpu(hdr->ucode_size_bytes)); |
| 345 | size -= le32_to_cpu(hdr->ucode_size_bytes); |
| 346 | ptr += le32_to_cpu(hdr->ucode_size_bytes); |
| 347 | } |
Christian König | ba0b227 | 2016-08-23 11:00:17 +0200 | [diff] [blame] | 348 | memset_io(ptr, 0, size); |
Jim Qu | 3b1186f | 2017-12-18 10:08:38 +0800 | [diff] [blame] | 349 | /* to restore uvd fence seq */ |
| 350 | amdgpu_fence_driver_force_completion(&adev->uvd.ring); |
Leo Liu | d23be4e | 2016-04-04 10:55:43 -0400 | [diff] [blame] | 351 | } |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 352 | |
| 353 | return 0; |
| 354 | } |
| 355 | |
| 356 | void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) |
| 357 | { |
| 358 | struct amdgpu_ring *ring = &adev->uvd.ring; |
| 359 | int i, r; |
| 360 | |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 361 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 362 | uint32_t handle = atomic_read(&adev->uvd.handles[i]); |
| 363 | if (handle != 0 && adev->uvd.filp[i] == filp) { |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 364 | struct dma_fence *fence; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 365 | |
Christian König | d7af97d | 2016-02-03 16:01:06 +0100 | [diff] [blame] | 366 | r = amdgpu_uvd_get_destroy_msg(ring, handle, |
| 367 | false, &fence); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 368 | if (r) { |
| 369 | DRM_ERROR("Error destroying UVD (%d)!\n", r); |
| 370 | continue; |
| 371 | } |
| 372 | |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 373 | dma_fence_wait(fence, false); |
| 374 | dma_fence_put(fence); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 375 | |
| 376 | adev->uvd.filp[i] = NULL; |
| 377 | atomic_set(&adev->uvd.handles[i], 0); |
| 378 | } |
| 379 | } |
| 380 | } |
| 381 | |
Christian König | 765e7fb | 2016-09-15 15:06:50 +0200 | [diff] [blame] | 382 | static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 383 | { |
| 384 | int i; |
Christian König | 765e7fb | 2016-09-15 15:06:50 +0200 | [diff] [blame] | 385 | for (i = 0; i < abo->placement.num_placement; ++i) { |
| 386 | abo->placements[i].fpfn = 0 >> PAGE_SHIFT; |
| 387 | abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 388 | } |
| 389 | } |
| 390 | |
Alex Deucher | 80983e4 | 2016-11-21 16:24:37 -0500 | [diff] [blame] | 391 | static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) |
| 392 | { |
| 393 | uint32_t lo, hi; |
| 394 | uint64_t addr; |
| 395 | |
| 396 | lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); |
| 397 | hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); |
| 398 | addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); |
| 399 | |
| 400 | return addr; |
| 401 | } |
| 402 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 403 | /** |
| 404 | * amdgpu_uvd_cs_pass1 - first parsing round |
| 405 | * |
| 406 | * @ctx: UVD parser context |
| 407 | * |
| 408 | * Make sure UVD message and feedback buffers are in VRAM and |
| 409 | * nobody is violating an 256MB boundary. |
| 410 | */ |
| 411 | static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) |
| 412 | { |
Christian König | 19be557 | 2017-04-12 14:24:39 +0200 | [diff] [blame] | 413 | struct ttm_operation_ctx tctx = { false, false }; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 414 | struct amdgpu_bo_va_mapping *mapping; |
| 415 | struct amdgpu_bo *bo; |
Alex Deucher | 80983e4 | 2016-11-21 16:24:37 -0500 | [diff] [blame] | 416 | uint32_t cmd; |
| 417 | uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 418 | int r = 0; |
| 419 | |
Christian König | 9cca0b8 | 2017-09-06 16:15:28 +0200 | [diff] [blame] | 420 | r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); |
| 421 | if (r) { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 422 | DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); |
Christian König | 9cca0b8 | 2017-09-06 16:15:28 +0200 | [diff] [blame] | 423 | return r; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 424 | } |
| 425 | |
| 426 | if (!ctx->parser->adev->uvd.address_64_bit) { |
| 427 | /* check if it's a message or feedback command */ |
| 428 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; |
| 429 | if (cmd == 0x0 || cmd == 0x3) { |
| 430 | /* yes, force it into VRAM */ |
| 431 | uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; |
| 432 | amdgpu_ttm_placement_from_domain(bo, domain); |
| 433 | } |
| 434 | amdgpu_uvd_force_into_uvd_segment(bo); |
| 435 | |
Christian König | 19be557 | 2017-04-12 14:24:39 +0200 | [diff] [blame] | 436 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | return r; |
| 440 | } |
| 441 | |
| 442 | /** |
| 443 | * amdgpu_uvd_cs_msg_decode - handle UVD decode message |
| 444 | * |
| 445 | * @msg: pointer to message structure |
| 446 | * @buf_sizes: returned buffer sizes |
| 447 | * |
| 448 | * Peek into the decode message and calculate the necessary buffer sizes. |
| 449 | */ |
Sonny Jiang | 8e008dd | 2016-05-11 13:29:48 -0400 | [diff] [blame] | 450 | static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, |
| 451 | unsigned buf_sizes[]) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 452 | { |
| 453 | unsigned stream_type = msg[4]; |
| 454 | unsigned width = msg[6]; |
| 455 | unsigned height = msg[7]; |
| 456 | unsigned dpb_size = msg[9]; |
| 457 | unsigned pitch = msg[28]; |
| 458 | unsigned level = msg[57]; |
| 459 | |
| 460 | unsigned width_in_mb = width / 16; |
| 461 | unsigned height_in_mb = ALIGN(height / 16, 2); |
| 462 | unsigned fs_in_mb = width_in_mb * height_in_mb; |
| 463 | |
Jammy Zhou | 21df89a | 2015-08-07 15:30:44 +0800 | [diff] [blame] | 464 | unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; |
Christian König | e5a6858 | 2016-07-26 10:51:29 +0200 | [diff] [blame] | 465 | unsigned min_ctx_size = ~0; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 466 | |
| 467 | image_size = width * height; |
| 468 | image_size += image_size / 2; |
| 469 | image_size = ALIGN(image_size, 1024); |
| 470 | |
| 471 | switch (stream_type) { |
| 472 | case 0: /* H264 */ |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 473 | switch(level) { |
| 474 | case 30: |
| 475 | num_dpb_buffer = 8100 / fs_in_mb; |
| 476 | break; |
| 477 | case 31: |
| 478 | num_dpb_buffer = 18000 / fs_in_mb; |
| 479 | break; |
| 480 | case 32: |
| 481 | num_dpb_buffer = 20480 / fs_in_mb; |
| 482 | break; |
| 483 | case 41: |
| 484 | num_dpb_buffer = 32768 / fs_in_mb; |
| 485 | break; |
| 486 | case 42: |
| 487 | num_dpb_buffer = 34816 / fs_in_mb; |
| 488 | break; |
| 489 | case 50: |
| 490 | num_dpb_buffer = 110400 / fs_in_mb; |
| 491 | break; |
| 492 | case 51: |
| 493 | num_dpb_buffer = 184320 / fs_in_mb; |
| 494 | break; |
| 495 | default: |
| 496 | num_dpb_buffer = 184320 / fs_in_mb; |
| 497 | break; |
| 498 | } |
| 499 | num_dpb_buffer++; |
| 500 | if (num_dpb_buffer > 17) |
| 501 | num_dpb_buffer = 17; |
| 502 | |
| 503 | /* reference picture buffer */ |
| 504 | min_dpb_size = image_size * num_dpb_buffer; |
| 505 | |
| 506 | /* macroblock context buffer */ |
| 507 | min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; |
| 508 | |
| 509 | /* IT surface buffer */ |
| 510 | min_dpb_size += width_in_mb * height_in_mb * 32; |
| 511 | break; |
| 512 | |
| 513 | case 1: /* VC1 */ |
| 514 | |
| 515 | /* reference picture buffer */ |
| 516 | min_dpb_size = image_size * 3; |
| 517 | |
| 518 | /* CONTEXT_BUFFER */ |
| 519 | min_dpb_size += width_in_mb * height_in_mb * 128; |
| 520 | |
| 521 | /* IT surface buffer */ |
| 522 | min_dpb_size += width_in_mb * 64; |
| 523 | |
| 524 | /* DB surface buffer */ |
| 525 | min_dpb_size += width_in_mb * 128; |
| 526 | |
| 527 | /* BP */ |
| 528 | tmp = max(width_in_mb, height_in_mb); |
| 529 | min_dpb_size += ALIGN(tmp * 7 * 16, 64); |
| 530 | break; |
| 531 | |
| 532 | case 3: /* MPEG2 */ |
| 533 | |
| 534 | /* reference picture buffer */ |
| 535 | min_dpb_size = image_size * 3; |
| 536 | break; |
| 537 | |
| 538 | case 4: /* MPEG4 */ |
| 539 | |
| 540 | /* reference picture buffer */ |
| 541 | min_dpb_size = image_size * 3; |
| 542 | |
| 543 | /* CM */ |
| 544 | min_dpb_size += width_in_mb * height_in_mb * 64; |
| 545 | |
| 546 | /* IT surface buffer */ |
| 547 | min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); |
| 548 | break; |
| 549 | |
Sonny Jiang | 8e008dd | 2016-05-11 13:29:48 -0400 | [diff] [blame] | 550 | case 7: /* H264 Perf */ |
| 551 | switch(level) { |
| 552 | case 30: |
| 553 | num_dpb_buffer = 8100 / fs_in_mb; |
| 554 | break; |
| 555 | case 31: |
| 556 | num_dpb_buffer = 18000 / fs_in_mb; |
| 557 | break; |
| 558 | case 32: |
| 559 | num_dpb_buffer = 20480 / fs_in_mb; |
| 560 | break; |
| 561 | case 41: |
| 562 | num_dpb_buffer = 32768 / fs_in_mb; |
| 563 | break; |
| 564 | case 42: |
| 565 | num_dpb_buffer = 34816 / fs_in_mb; |
| 566 | break; |
| 567 | case 50: |
| 568 | num_dpb_buffer = 110400 / fs_in_mb; |
| 569 | break; |
| 570 | case 51: |
| 571 | num_dpb_buffer = 184320 / fs_in_mb; |
| 572 | break; |
| 573 | default: |
| 574 | num_dpb_buffer = 184320 / fs_in_mb; |
| 575 | break; |
| 576 | } |
| 577 | num_dpb_buffer++; |
| 578 | if (num_dpb_buffer > 17) |
| 579 | num_dpb_buffer = 17; |
| 580 | |
| 581 | /* reference picture buffer */ |
| 582 | min_dpb_size = image_size * num_dpb_buffer; |
| 583 | |
Christian König | 4cb5877c | 2016-07-26 12:05:40 +0200 | [diff] [blame] | 584 | if (!adev->uvd.use_ctx_buf){ |
Sonny Jiang | 8e008dd | 2016-05-11 13:29:48 -0400 | [diff] [blame] | 585 | /* macroblock context buffer */ |
| 586 | min_dpb_size += |
| 587 | width_in_mb * height_in_mb * num_dpb_buffer * 192; |
| 588 | |
| 589 | /* IT surface buffer */ |
| 590 | min_dpb_size += width_in_mb * height_in_mb * 32; |
| 591 | } else { |
| 592 | /* macroblock context buffer */ |
| 593 | min_ctx_size = |
| 594 | width_in_mb * height_in_mb * num_dpb_buffer * 192; |
| 595 | } |
| 596 | break; |
| 597 | |
Leo Liu | d0b83d4 | 2017-08-15 10:57:34 -0400 | [diff] [blame] | 598 | case 8: /* MJPEG */ |
| 599 | min_dpb_size = 0; |
| 600 | break; |
| 601 | |
Christian König | 86fa0bd | 2015-05-05 16:36:01 +0200 | [diff] [blame] | 602 | case 16: /* H265 */ |
| 603 | image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; |
| 604 | image_size = ALIGN(image_size, 256); |
| 605 | |
| 606 | num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; |
| 607 | min_dpb_size = image_size * num_dpb_buffer; |
Boyuan Zhang | 8c8bac5 | 2015-08-05 14:03:48 -0400 | [diff] [blame] | 608 | min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) |
| 609 | * 16 * num_dpb_buffer + 52 * 1024; |
Christian König | 86fa0bd | 2015-05-05 16:36:01 +0200 | [diff] [blame] | 610 | break; |
| 611 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 612 | default: |
| 613 | DRM_ERROR("UVD codec not handled %d!\n", stream_type); |
| 614 | return -EINVAL; |
| 615 | } |
| 616 | |
| 617 | if (width > pitch) { |
| 618 | DRM_ERROR("Invalid UVD decoding target pitch!\n"); |
| 619 | return -EINVAL; |
| 620 | } |
| 621 | |
| 622 | if (dpb_size < min_dpb_size) { |
| 623 | DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", |
| 624 | dpb_size, min_dpb_size); |
| 625 | return -EINVAL; |
| 626 | } |
| 627 | |
| 628 | buf_sizes[0x1] = dpb_size; |
| 629 | buf_sizes[0x2] = image_size; |
Boyuan Zhang | 8c8bac5 | 2015-08-05 14:03:48 -0400 | [diff] [blame] | 630 | buf_sizes[0x4] = min_ctx_size; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 631 | return 0; |
| 632 | } |
| 633 | |
| 634 | /** |
| 635 | * amdgpu_uvd_cs_msg - handle UVD message |
| 636 | * |
| 637 | * @ctx: UVD parser context |
| 638 | * @bo: buffer object containing the message |
| 639 | * @offset: offset into the buffer object |
| 640 | * |
| 641 | * Peek into the UVD message and extract the session id. |
| 642 | * Make sure that we don't open up to many sessions. |
| 643 | */ |
| 644 | static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, |
| 645 | struct amdgpu_bo *bo, unsigned offset) |
| 646 | { |
| 647 | struct amdgpu_device *adev = ctx->parser->adev; |
| 648 | int32_t *msg, msg_type, handle; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 649 | void *ptr; |
Christian König | 4127a59 | 2015-08-11 16:35:54 +0200 | [diff] [blame] | 650 | long r; |
| 651 | int i; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 652 | |
| 653 | if (offset & 0x3F) { |
| 654 | DRM_ERROR("UVD messages must be 64 byte aligned!\n"); |
| 655 | return -EINVAL; |
| 656 | } |
| 657 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 658 | r = amdgpu_bo_kmap(bo, &ptr); |
| 659 | if (r) { |
Christian König | 4127a59 | 2015-08-11 16:35:54 +0200 | [diff] [blame] | 660 | DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 661 | return r; |
| 662 | } |
| 663 | |
| 664 | msg = ptr + offset; |
| 665 | |
| 666 | msg_type = msg[1]; |
| 667 | handle = msg[2]; |
| 668 | |
| 669 | if (handle == 0) { |
| 670 | DRM_ERROR("Invalid UVD handle!\n"); |
| 671 | return -EINVAL; |
| 672 | } |
| 673 | |
Leo Liu | 5146419 | 2015-09-15 10:38:38 -0400 | [diff] [blame] | 674 | switch (msg_type) { |
| 675 | case 0: |
| 676 | /* it's a create msg, calc image size (width * height) */ |
| 677 | amdgpu_bo_kunmap(bo); |
| 678 | |
| 679 | /* try to alloc a new handle */ |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 680 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
Leo Liu | 5146419 | 2015-09-15 10:38:38 -0400 | [diff] [blame] | 681 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
| 682 | DRM_ERROR("Handle 0x%x already in use!\n", handle); |
| 683 | return -EINVAL; |
| 684 | } |
| 685 | |
| 686 | if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { |
| 687 | adev->uvd.filp[i] = ctx->parser->filp; |
| 688 | return 0; |
| 689 | } |
| 690 | } |
| 691 | |
| 692 | DRM_ERROR("No more free UVD handles!\n"); |
Christian König | 7129d3a | 2016-07-13 21:24:59 +0200 | [diff] [blame] | 693 | return -ENOSPC; |
Leo Liu | 5146419 | 2015-09-15 10:38:38 -0400 | [diff] [blame] | 694 | |
| 695 | case 1: |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 696 | /* it's a decode msg, calc buffer sizes */ |
Sonny Jiang | 8e008dd | 2016-05-11 13:29:48 -0400 | [diff] [blame] | 697 | r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 698 | amdgpu_bo_kunmap(bo); |
| 699 | if (r) |
| 700 | return r; |
| 701 | |
Leo Liu | 5146419 | 2015-09-15 10:38:38 -0400 | [diff] [blame] | 702 | /* validate the handle */ |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 703 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
Leo Liu | 5146419 | 2015-09-15 10:38:38 -0400 | [diff] [blame] | 704 | if (atomic_read(&adev->uvd.handles[i]) == handle) { |
| 705 | if (adev->uvd.filp[i] != ctx->parser->filp) { |
| 706 | DRM_ERROR("UVD handle collision detected!\n"); |
| 707 | return -EINVAL; |
| 708 | } |
| 709 | return 0; |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); |
| 714 | return -ENOENT; |
| 715 | |
| 716 | case 2: |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 717 | /* it's a destroy msg, free the handle */ |
Arindam Nath | c036554 | 2016-04-12 13:46:15 +0200 | [diff] [blame] | 718 | for (i = 0; i < adev->uvd.max_handles; ++i) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 719 | atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); |
| 720 | amdgpu_bo_kunmap(bo); |
| 721 | return 0; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 722 | |
Leo Liu | 5146419 | 2015-09-15 10:38:38 -0400 | [diff] [blame] | 723 | default: |
| 724 | DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); |
| 725 | return -EINVAL; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 726 | } |
Leo Liu | 5146419 | 2015-09-15 10:38:38 -0400 | [diff] [blame] | 727 | BUG(); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 728 | return -EINVAL; |
| 729 | } |
| 730 | |
| 731 | /** |
| 732 | * amdgpu_uvd_cs_pass2 - second parsing round |
| 733 | * |
| 734 | * @ctx: UVD parser context |
| 735 | * |
| 736 | * Patch buffer addresses, make sure buffer sizes are correct. |
| 737 | */ |
| 738 | static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) |
| 739 | { |
| 740 | struct amdgpu_bo_va_mapping *mapping; |
| 741 | struct amdgpu_bo *bo; |
Alex Deucher | 80983e4 | 2016-11-21 16:24:37 -0500 | [diff] [blame] | 742 | uint32_t cmd; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 743 | uint64_t start, end; |
Alex Deucher | 80983e4 | 2016-11-21 16:24:37 -0500 | [diff] [blame] | 744 | uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 745 | int r; |
| 746 | |
Christian König | 9cca0b8 | 2017-09-06 16:15:28 +0200 | [diff] [blame] | 747 | r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); |
| 748 | if (r) { |
Alex Deucher | 042eb91 | 2016-11-21 16:34:29 -0500 | [diff] [blame] | 749 | DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); |
Christian König | 9cca0b8 | 2017-09-06 16:15:28 +0200 | [diff] [blame] | 750 | return r; |
Alex Deucher | 042eb91 | 2016-11-21 16:34:29 -0500 | [diff] [blame] | 751 | } |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 752 | |
| 753 | start = amdgpu_bo_gpu_offset(bo); |
| 754 | |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 755 | end = (mapping->last + 1 - mapping->start); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 756 | end = end * AMDGPU_GPU_PAGE_SIZE + start; |
| 757 | |
Christian König | a9f87f6 | 2017-03-30 14:03:59 +0200 | [diff] [blame] | 758 | addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 759 | start += addr; |
| 760 | |
Christian König | 7270f83 | 2016-01-31 11:00:41 +0100 | [diff] [blame] | 761 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, |
| 762 | lower_32_bits(start)); |
| 763 | amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, |
| 764 | upper_32_bits(start)); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 765 | |
| 766 | cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; |
| 767 | if (cmd < 0x4) { |
| 768 | if ((end - start) < ctx->buf_sizes[cmd]) { |
| 769 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, |
| 770 | (unsigned)(end - start), |
| 771 | ctx->buf_sizes[cmd]); |
| 772 | return -EINVAL; |
| 773 | } |
| 774 | |
Boyuan Zhang | 8c8bac5 | 2015-08-05 14:03:48 -0400 | [diff] [blame] | 775 | } else if (cmd == 0x206) { |
| 776 | if ((end - start) < ctx->buf_sizes[4]) { |
| 777 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, |
| 778 | (unsigned)(end - start), |
| 779 | ctx->buf_sizes[4]); |
| 780 | return -EINVAL; |
| 781 | } |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 782 | } else if ((cmd != 0x100) && (cmd != 0x204)) { |
| 783 | DRM_ERROR("invalid UVD command %X!\n", cmd); |
| 784 | return -EINVAL; |
| 785 | } |
| 786 | |
| 787 | if (!ctx->parser->adev->uvd.address_64_bit) { |
| 788 | if ((start >> 28) != ((end - 1) >> 28)) { |
| 789 | DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", |
| 790 | start, end); |
| 791 | return -EINVAL; |
| 792 | } |
| 793 | |
| 794 | if ((cmd == 0 || cmd == 0x3) && |
| 795 | (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) { |
| 796 | DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", |
| 797 | start, end); |
| 798 | return -EINVAL; |
| 799 | } |
| 800 | } |
| 801 | |
| 802 | if (cmd == 0) { |
| 803 | ctx->has_msg_cmd = true; |
| 804 | r = amdgpu_uvd_cs_msg(ctx, bo, addr); |
| 805 | if (r) |
| 806 | return r; |
| 807 | } else if (!ctx->has_msg_cmd) { |
| 808 | DRM_ERROR("Message needed before other commands are send!\n"); |
| 809 | return -EINVAL; |
| 810 | } |
| 811 | |
| 812 | return 0; |
| 813 | } |
| 814 | |
| 815 | /** |
| 816 | * amdgpu_uvd_cs_reg - parse register writes |
| 817 | * |
| 818 | * @ctx: UVD parser context |
| 819 | * @cb: callback function |
| 820 | * |
| 821 | * Parse the register writes, call cb on each complete command. |
| 822 | */ |
| 823 | static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, |
| 824 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) |
| 825 | { |
Christian König | 50838c8 | 2016-02-03 13:44:52 +0100 | [diff] [blame] | 826 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 827 | int i, r; |
| 828 | |
| 829 | ctx->idx++; |
| 830 | for (i = 0; i <= ctx->count; ++i) { |
| 831 | unsigned reg = ctx->reg + i; |
| 832 | |
| 833 | if (ctx->idx >= ib->length_dw) { |
| 834 | DRM_ERROR("Register command after end of CS!\n"); |
| 835 | return -EINVAL; |
| 836 | } |
| 837 | |
| 838 | switch (reg) { |
| 839 | case mmUVD_GPCOM_VCPU_DATA0: |
| 840 | ctx->data0 = ctx->idx; |
| 841 | break; |
| 842 | case mmUVD_GPCOM_VCPU_DATA1: |
| 843 | ctx->data1 = ctx->idx; |
| 844 | break; |
| 845 | case mmUVD_GPCOM_VCPU_CMD: |
| 846 | r = cb(ctx); |
| 847 | if (r) |
| 848 | return r; |
| 849 | break; |
| 850 | case mmUVD_ENGINE_CNTL: |
Alex Deucher | 8dd31d7 | 2016-08-22 17:58:14 -0400 | [diff] [blame] | 851 | case mmUVD_NO_OP: |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 852 | break; |
| 853 | default: |
| 854 | DRM_ERROR("Invalid reg 0x%X!\n", reg); |
| 855 | return -EINVAL; |
| 856 | } |
| 857 | ctx->idx++; |
| 858 | } |
| 859 | return 0; |
| 860 | } |
| 861 | |
| 862 | /** |
| 863 | * amdgpu_uvd_cs_packets - parse UVD packets |
| 864 | * |
| 865 | * @ctx: UVD parser context |
| 866 | * @cb: callback function |
| 867 | * |
| 868 | * Parse the command stream packets. |
| 869 | */ |
| 870 | static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, |
| 871 | int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) |
| 872 | { |
Christian König | 50838c8 | 2016-02-03 13:44:52 +0100 | [diff] [blame] | 873 | struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 874 | int r; |
| 875 | |
| 876 | for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { |
| 877 | uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); |
| 878 | unsigned type = CP_PACKET_GET_TYPE(cmd); |
| 879 | switch (type) { |
| 880 | case PACKET_TYPE0: |
| 881 | ctx->reg = CP_PACKET0_GET_REG(cmd); |
| 882 | ctx->count = CP_PACKET_GET_COUNT(cmd); |
| 883 | r = amdgpu_uvd_cs_reg(ctx, cb); |
| 884 | if (r) |
| 885 | return r; |
| 886 | break; |
| 887 | case PACKET_TYPE2: |
| 888 | ++ctx->idx; |
| 889 | break; |
| 890 | default: |
| 891 | DRM_ERROR("Unknown packet type %d !\n", type); |
| 892 | return -EINVAL; |
| 893 | } |
| 894 | } |
| 895 | return 0; |
| 896 | } |
| 897 | |
| 898 | /** |
| 899 | * amdgpu_uvd_ring_parse_cs - UVD command submission parser |
| 900 | * |
| 901 | * @parser: Command submission parser context |
| 902 | * |
| 903 | * Parse the command stream, patch in addresses as necessary. |
| 904 | */ |
| 905 | int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) |
| 906 | { |
| 907 | struct amdgpu_uvd_cs_ctx ctx = {}; |
| 908 | unsigned buf_sizes[] = { |
| 909 | [0x00000000] = 2048, |
Boyuan Zhang | 8c8bac5 | 2015-08-05 14:03:48 -0400 | [diff] [blame] | 910 | [0x00000001] = 0xFFFFFFFF, |
| 911 | [0x00000002] = 0xFFFFFFFF, |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 912 | [0x00000003] = 2048, |
Boyuan Zhang | 8c8bac5 | 2015-08-05 14:03:48 -0400 | [diff] [blame] | 913 | [0x00000004] = 0xFFFFFFFF, |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 914 | }; |
Christian König | 50838c8 | 2016-02-03 13:44:52 +0100 | [diff] [blame] | 915 | struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 916 | int r; |
| 917 | |
Christian König | 45088ef | 2016-10-05 16:49:19 +0200 | [diff] [blame] | 918 | parser->job->vm = NULL; |
| 919 | ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); |
| 920 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 921 | if (ib->length_dw % 16) { |
| 922 | DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", |
| 923 | ib->length_dw); |
| 924 | return -EINVAL; |
| 925 | } |
| 926 | |
| 927 | ctx.parser = parser; |
| 928 | ctx.buf_sizes = buf_sizes; |
| 929 | ctx.ib_idx = ib_idx; |
| 930 | |
Alex Deucher | 042eb91 | 2016-11-21 16:34:29 -0500 | [diff] [blame] | 931 | /* first round only required on chips without UVD 64 bit address support */ |
| 932 | if (!parser->adev->uvd.address_64_bit) { |
| 933 | /* first round, make sure the buffers are actually in the UVD segment */ |
| 934 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); |
| 935 | if (r) |
| 936 | return r; |
| 937 | } |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 938 | |
| 939 | /* second round, patch buffer addresses into the command stream */ |
| 940 | r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); |
| 941 | if (r) |
| 942 | return r; |
| 943 | |
| 944 | if (!ctx.has_msg_cmd) { |
| 945 | DRM_ERROR("UVD-IBs need a msg command!\n"); |
| 946 | return -EINVAL; |
| 947 | } |
| 948 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 949 | return 0; |
| 950 | } |
| 951 | |
Christian König | d7af97d | 2016-02-03 16:01:06 +0100 | [diff] [blame] | 952 | static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 953 | bool direct, struct dma_fence **fence) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 954 | { |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 955 | struct amdgpu_device *adev = ring->adev; |
| 956 | struct dma_fence *f = NULL; |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 957 | struct amdgpu_job *job; |
| 958 | struct amdgpu_ib *ib; |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 959 | uint32_t data[4]; |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 960 | uint64_t addr; |
| 961 | long r; |
| 962 | int i; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 963 | |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 964 | amdgpu_bo_kunmap(bo); |
| 965 | amdgpu_bo_unpin(bo); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 966 | |
Christian König | a7d64de | 2016-09-15 14:58:48 +0200 | [diff] [blame] | 967 | if (!ring->adev->uvd.address_64_bit) { |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 968 | struct ttm_operation_ctx ctx = { true, false }; |
| 969 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 970 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); |
| 971 | amdgpu_uvd_force_into_uvd_segment(bo); |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 972 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
| 973 | if (r) |
| 974 | goto err; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 975 | } |
| 976 | |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 977 | r = amdgpu_job_alloc_with_ib(adev, 64, &job); |
| 978 | if (r) |
| 979 | goto err; |
| 980 | |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 981 | if (adev->asic_type >= CHIP_VEGA10) { |
| 982 | data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0); |
| 983 | data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0); |
| 984 | data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0); |
| 985 | data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0); |
| 986 | } else { |
| 987 | data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); |
| 988 | data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); |
| 989 | data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); |
| 990 | data[3] = PACKET0(mmUVD_NO_OP, 0); |
| 991 | } |
| 992 | |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 993 | ib = &job->ibs[0]; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 994 | addr = amdgpu_bo_gpu_offset(bo); |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 995 | ib->ptr[0] = data[0]; |
Chunming Zhou | 7b5ec43 | 2015-07-03 14:08:18 +0800 | [diff] [blame] | 996 | ib->ptr[1] = addr; |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 997 | ib->ptr[2] = data[1]; |
Chunming Zhou | 7b5ec43 | 2015-07-03 14:08:18 +0800 | [diff] [blame] | 998 | ib->ptr[3] = addr >> 32; |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 999 | ib->ptr[4] = data[2]; |
Chunming Zhou | 7b5ec43 | 2015-07-03 14:08:18 +0800 | [diff] [blame] | 1000 | ib->ptr[5] = 0; |
Alex Deucher | c8b4f28 | 2016-08-23 09:12:21 -0400 | [diff] [blame] | 1001 | for (i = 6; i < 16; i += 2) { |
Leo Liu | 09bfb89 | 2017-03-03 18:13:26 -0500 | [diff] [blame] | 1002 | ib->ptr[i] = data[3]; |
Alex Deucher | c8b4f28 | 2016-08-23 09:12:21 -0400 | [diff] [blame] | 1003 | ib->ptr[i+1] = 0; |
| 1004 | } |
Chunming Zhou | 7b5ec43 | 2015-07-03 14:08:18 +0800 | [diff] [blame] | 1005 | ib->length_dw = 16; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1006 | |
Christian König | d7af97d | 2016-02-03 16:01:06 +0100 | [diff] [blame] | 1007 | if (direct) { |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 1008 | r = reservation_object_wait_timeout_rcu(bo->tbo.resv, |
| 1009 | true, false, |
| 1010 | msecs_to_jiffies(10)); |
| 1011 | if (r == 0) |
| 1012 | r = -ETIMEDOUT; |
| 1013 | if (r < 0) |
| 1014 | goto err_free; |
| 1015 | |
Junwei Zhang | 50ddc75 | 2017-01-23 16:30:38 +0800 | [diff] [blame] | 1016 | r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f); |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1017 | job->fence = dma_fence_get(f); |
Christian König | d7af97d | 2016-02-03 16:01:06 +0100 | [diff] [blame] | 1018 | if (r) |
| 1019 | goto err_free; |
| 1020 | |
| 1021 | amdgpu_job_free(job); |
| 1022 | } else { |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 1023 | r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, |
| 1024 | AMDGPU_FENCE_OWNER_UNDEFINED, false); |
| 1025 | if (r) |
| 1026 | goto err_free; |
| 1027 | |
Christian König | ead833e | 2016-02-10 14:35:19 +0100 | [diff] [blame] | 1028 | r = amdgpu_job_submit(job, ring, &adev->uvd.entity, |
Christian König | d7af97d | 2016-02-03 16:01:06 +0100 | [diff] [blame] | 1029 | AMDGPU_FENCE_OWNER_UNDEFINED, &f); |
| 1030 | if (r) |
| 1031 | goto err_free; |
| 1032 | } |
Chunming Zhou | 7b5ec43 | 2015-07-03 14:08:18 +0800 | [diff] [blame] | 1033 | |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 1034 | amdgpu_bo_fence(bo, f, false); |
| 1035 | amdgpu_bo_unreserve(bo); |
| 1036 | amdgpu_bo_unref(&bo); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1037 | |
| 1038 | if (fence) |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1039 | *fence = dma_fence_get(f); |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1040 | dma_fence_put(f); |
Chunming Zhou | 7b5ec43 | 2015-07-03 14:08:18 +0800 | [diff] [blame] | 1041 | |
Chunming Zhou | 7b5ec43 | 2015-07-03 14:08:18 +0800 | [diff] [blame] | 1042 | return 0; |
Christian König | d71518b | 2016-02-01 12:20:25 +0100 | [diff] [blame] | 1043 | |
| 1044 | err_free: |
| 1045 | amdgpu_job_free(job); |
| 1046 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1047 | err: |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 1048 | amdgpu_bo_unreserve(bo); |
| 1049 | amdgpu_bo_unref(&bo); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1050 | return r; |
| 1051 | } |
| 1052 | |
| 1053 | /* multiple fence commands without any stream commands in between can |
| 1054 | crash the vcpu so just try to emmit a dummy create/destroy msg to |
| 1055 | avoid this */ |
| 1056 | int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1057 | struct dma_fence **fence) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1058 | { |
| 1059 | struct amdgpu_device *adev = ring->adev; |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 1060 | struct amdgpu_bo *bo = NULL; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1061 | uint32_t *msg; |
| 1062 | int r, i; |
| 1063 | |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 1064 | r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, |
| 1065 | AMDGPU_GEM_DOMAIN_VRAM, |
| 1066 | &bo, NULL, (void **)&msg); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1067 | if (r) |
| 1068 | return r; |
| 1069 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1070 | /* stitch together an UVD create msg */ |
| 1071 | msg[0] = cpu_to_le32(0x00000de4); |
| 1072 | msg[1] = cpu_to_le32(0x00000000); |
| 1073 | msg[2] = cpu_to_le32(handle); |
| 1074 | msg[3] = cpu_to_le32(0x00000000); |
| 1075 | msg[4] = cpu_to_le32(0x00000000); |
| 1076 | msg[5] = cpu_to_le32(0x00000000); |
| 1077 | msg[6] = cpu_to_le32(0x00000000); |
| 1078 | msg[7] = cpu_to_le32(0x00000780); |
| 1079 | msg[8] = cpu_to_le32(0x00000440); |
| 1080 | msg[9] = cpu_to_le32(0x00000000); |
| 1081 | msg[10] = cpu_to_le32(0x01b37000); |
| 1082 | for (i = 11; i < 1024; ++i) |
| 1083 | msg[i] = cpu_to_le32(0x0); |
| 1084 | |
Christian König | d7af97d | 2016-02-03 16:01:06 +0100 | [diff] [blame] | 1085 | return amdgpu_uvd_send_msg(ring, bo, true, fence); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1086 | } |
| 1087 | |
| 1088 | int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1089 | bool direct, struct dma_fence **fence) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1090 | { |
| 1091 | struct amdgpu_device *adev = ring->adev; |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 1092 | struct amdgpu_bo *bo = NULL; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1093 | uint32_t *msg; |
| 1094 | int r, i; |
| 1095 | |
Christian König | 4ab91cf | 2018-02-07 20:48:21 +0100 | [diff] [blame] | 1096 | r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, |
| 1097 | AMDGPU_GEM_DOMAIN_VRAM, |
| 1098 | &bo, NULL, (void **)&msg); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1099 | if (r) |
| 1100 | return r; |
| 1101 | |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1102 | /* stitch together an UVD destroy msg */ |
| 1103 | msg[0] = cpu_to_le32(0x00000de4); |
| 1104 | msg[1] = cpu_to_le32(0x00000002); |
| 1105 | msg[2] = cpu_to_le32(handle); |
| 1106 | msg[3] = cpu_to_le32(0x00000000); |
| 1107 | for (i = 4; i < 1024; ++i) |
| 1108 | msg[i] = cpu_to_le32(0x0); |
| 1109 | |
Christian König | d7af97d | 2016-02-03 16:01:06 +0100 | [diff] [blame] | 1110 | return amdgpu_uvd_send_msg(ring, bo, direct, fence); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1111 | } |
| 1112 | |
| 1113 | static void amdgpu_uvd_idle_work_handler(struct work_struct *work) |
| 1114 | { |
| 1115 | struct amdgpu_device *adev = |
| 1116 | container_of(work, struct amdgpu_device, uvd.idle_work.work); |
Leo Liu | 713c002 | 2016-08-03 09:25:59 -0400 | [diff] [blame] | 1117 | unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1118 | |
Leo Liu | 713c002 | 2016-08-03 09:25:59 -0400 | [diff] [blame] | 1119 | if (fences == 0) { |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1120 | if (adev->pm.dpm_enabled) { |
| 1121 | amdgpu_dpm_enable_uvd(adev, false); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1122 | } else { |
| 1123 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); |
Rex Zhu | e38ca2b | 2017-01-20 12:06:05 +0800 | [diff] [blame] | 1124 | /* shutdown the UVD block */ |
Alex Deucher | 2990a1f | 2017-12-15 16:18:00 -0500 | [diff] [blame] | 1125 | amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, |
| 1126 | AMD_PG_STATE_GATE); |
| 1127 | amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, |
| 1128 | AMD_CG_STATE_GATE); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1129 | } |
| 1130 | } else { |
Christian König | 0808663 | 2016-07-01 17:45:49 +0200 | [diff] [blame] | 1131 | schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1132 | } |
| 1133 | } |
| 1134 | |
Christian König | c4120d5 | 2016-07-20 14:11:26 +0200 | [diff] [blame] | 1135 | void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1136 | { |
Christian König | c4120d5 | 2016-07-20 14:11:26 +0200 | [diff] [blame] | 1137 | struct amdgpu_device *adev = ring->adev; |
Monk Liu | 14a8032 | 2018-01-19 20:29:17 +0800 | [diff] [blame] | 1138 | bool set_clocks; |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1139 | |
Xiangliang Yu | d9af225 | 2017-03-07 14:45:25 +0800 | [diff] [blame] | 1140 | if (amdgpu_sriov_vf(adev)) |
| 1141 | return; |
| 1142 | |
Monk Liu | 14a8032 | 2018-01-19 20:29:17 +0800 | [diff] [blame] | 1143 | set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1144 | if (set_clocks) { |
| 1145 | if (adev->pm.dpm_enabled) { |
| 1146 | amdgpu_dpm_enable_uvd(adev, true); |
| 1147 | } else { |
| 1148 | amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); |
Alex Deucher | 2990a1f | 2017-12-15 16:18:00 -0500 | [diff] [blame] | 1149 | amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, |
| 1150 | AMD_CG_STATE_UNGATE); |
| 1151 | amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, |
| 1152 | AMD_PG_STATE_UNGATE); |
Alex Deucher | d38ceaf | 2015-04-20 16:55:21 -0400 | [diff] [blame] | 1153 | } |
| 1154 | } |
| 1155 | } |
Christian König | c4120d5 | 2016-07-20 14:11:26 +0200 | [diff] [blame] | 1156 | |
| 1157 | void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) |
| 1158 | { |
Monk Liu | 14a8032 | 2018-01-19 20:29:17 +0800 | [diff] [blame] | 1159 | if (!amdgpu_sriov_vf(ring->adev)) |
| 1160 | schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); |
Christian König | c4120d5 | 2016-07-20 14:11:26 +0200 | [diff] [blame] | 1161 | } |
Christian König | 8de190c | 2016-07-05 16:47:54 +0200 | [diff] [blame] | 1162 | |
| 1163 | /** |
| 1164 | * amdgpu_uvd_ring_test_ib - test ib execution |
| 1165 | * |
| 1166 | * @ring: amdgpu_ring pointer |
| 1167 | * |
| 1168 | * Test if we can successfully execute an IB |
| 1169 | */ |
Christian König | bbec97a | 2016-07-05 21:07:17 +0200 | [diff] [blame] | 1170 | int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
Christian König | 8de190c | 2016-07-05 16:47:54 +0200 | [diff] [blame] | 1171 | { |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1172 | struct dma_fence *fence; |
Christian König | bbec97a | 2016-07-05 21:07:17 +0200 | [diff] [blame] | 1173 | long r; |
Christian König | 8de190c | 2016-07-05 16:47:54 +0200 | [diff] [blame] | 1174 | |
| 1175 | r = amdgpu_uvd_get_create_msg(ring, 1, NULL); |
| 1176 | if (r) { |
Christian König | bbec97a | 2016-07-05 21:07:17 +0200 | [diff] [blame] | 1177 | DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r); |
Christian König | 8de190c | 2016-07-05 16:47:54 +0200 | [diff] [blame] | 1178 | goto error; |
| 1179 | } |
| 1180 | |
| 1181 | r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); |
| 1182 | if (r) { |
Christian König | bbec97a | 2016-07-05 21:07:17 +0200 | [diff] [blame] | 1183 | DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r); |
Christian König | 8de190c | 2016-07-05 16:47:54 +0200 | [diff] [blame] | 1184 | goto error; |
| 1185 | } |
| 1186 | |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1187 | r = dma_fence_wait_timeout(fence, false, timeout); |
Christian König | bbec97a | 2016-07-05 21:07:17 +0200 | [diff] [blame] | 1188 | if (r == 0) { |
| 1189 | DRM_ERROR("amdgpu: IB test timed out.\n"); |
| 1190 | r = -ETIMEDOUT; |
| 1191 | } else if (r < 0) { |
| 1192 | DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); |
| 1193 | } else { |
pding | 9953b72 | 2017-10-26 09:30:38 +0800 | [diff] [blame] | 1194 | DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); |
Christian König | bbec97a | 2016-07-05 21:07:17 +0200 | [diff] [blame] | 1195 | r = 0; |
Christian König | 8de190c | 2016-07-05 16:47:54 +0200 | [diff] [blame] | 1196 | } |
Christian König | bbec97a | 2016-07-05 21:07:17 +0200 | [diff] [blame] | 1197 | |
Chris Wilson | f54d186 | 2016-10-25 13:00:45 +0100 | [diff] [blame] | 1198 | dma_fence_put(fence); |
Jay Cornwall | c2a4c5b | 2016-08-03 13:39:42 -0500 | [diff] [blame] | 1199 | |
| 1200 | error: |
Christian König | 8de190c | 2016-07-05 16:47:54 +0200 | [diff] [blame] | 1201 | return r; |
| 1202 | } |
Arindam Nath | 44879b6 | 2016-12-12 15:29:33 +0530 | [diff] [blame] | 1203 | |
| 1204 | /** |
| 1205 | * amdgpu_uvd_used_handles - returns used UVD handles |
| 1206 | * |
| 1207 | * @adev: amdgpu_device pointer |
| 1208 | * |
| 1209 | * Returns the number of UVD handles in use |
| 1210 | */ |
| 1211 | uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) |
| 1212 | { |
| 1213 | unsigned i; |
| 1214 | uint32_t used_handles = 0; |
| 1215 | |
| 1216 | for (i = 0; i < adev->uvd.max_handles; ++i) { |
| 1217 | /* |
| 1218 | * Handles can be freed in any order, and not |
| 1219 | * necessarily linear. So we need to count |
| 1220 | * all non-zero handles. |
| 1221 | */ |
| 1222 | if (atomic_read(&adev->uvd.handles[i])) |
| 1223 | used_handles++; |
| 1224 | } |
| 1225 | |
| 1226 | return used_handles; |
| 1227 | } |