Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s3c6410/mach-smdk6410.c |
| 2 | * |
| 3 | * Copyright 2008 Openmoko, Inc. |
| 4 | * Copyright 2008 Simtec Electronics |
| 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/types.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/list.h> |
| 18 | #include <linux/timer.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/serial_core.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/io.h> |
Ben Dooks | 096941e | 2008-10-31 16:14:59 +0000 | [diff] [blame] | 23 | #include <linux/i2c.h> |
Ben Dooks | 438a5d4 | 2008-11-19 15:41:34 +0000 | [diff] [blame] | 24 | #include <linux/fb.h> |
| 25 | #include <linux/gpio.h> |
| 26 | #include <linux/delay.h> |
Mark Brown | 3056ea0 | 2009-01-27 16:18:01 +0000 | [diff] [blame] | 27 | #include <linux/smsc911x.h> |
Ben Dooks | 438a5d4 | 2008-11-19 15:41:34 +0000 | [diff] [blame] | 28 | |
Mark Brown | ecc558a | 2009-02-17 15:59:38 +0000 | [diff] [blame^] | 29 | #ifdef CONFIG_SMDK6410_WM1190_EV1 |
| 30 | #include <linux/mfd/wm8350/core.h> |
| 31 | #include <linux/mfd/wm8350/pmic.h> |
| 32 | #endif |
| 33 | |
Ben Dooks | 438a5d4 | 2008-11-19 15:41:34 +0000 | [diff] [blame] | 34 | #include <video/platform_lcd.h> |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 35 | |
| 36 | #include <asm/mach/arch.h> |
| 37 | #include <asm/mach/map.h> |
| 38 | #include <asm/mach/irq.h> |
| 39 | |
| 40 | #include <mach/hardware.h> |
Ben Dooks | 438a5d4 | 2008-11-19 15:41:34 +0000 | [diff] [blame] | 41 | #include <mach/regs-fb.h> |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 42 | #include <mach/map.h> |
| 43 | |
| 44 | #include <asm/irq.h> |
| 45 | #include <asm/mach-types.h> |
| 46 | |
| 47 | #include <plat/regs-serial.h> |
Ben Dooks | d6662c3 | 2008-12-12 00:24:40 +0000 | [diff] [blame] | 48 | #include <plat/regs-modem.h> |
| 49 | #include <plat/regs-gpio.h> |
| 50 | #include <plat/regs-sys.h> |
Ben Dooks | d85fa24 | 2008-10-31 16:14:52 +0000 | [diff] [blame] | 51 | #include <plat/iic.h> |
Ben Dooks | 438a5d4 | 2008-11-19 15:41:34 +0000 | [diff] [blame] | 52 | #include <plat/fb.h> |
Mark Brown | 3056ea0 | 2009-01-27 16:18:01 +0000 | [diff] [blame] | 53 | #include <plat/gpio-cfg.h> |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 54 | |
| 55 | #include <plat/s3c6410.h> |
| 56 | #include <plat/clock.h> |
| 57 | #include <plat/devs.h> |
| 58 | #include <plat/cpu.h> |
| 59 | |
| 60 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK |
| 61 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB |
| 62 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE |
| 63 | |
| 64 | static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = { |
| 65 | [0] = { |
| 66 | .hwport = 0, |
| 67 | .flags = 0, |
| 68 | .ucon = 0x3c5, |
| 69 | .ulcon = 0x03, |
| 70 | .ufcon = 0x51, |
| 71 | }, |
| 72 | [1] = { |
| 73 | .hwport = 1, |
| 74 | .flags = 0, |
| 75 | .ucon = 0x3c5, |
| 76 | .ulcon = 0x03, |
| 77 | .ufcon = 0x51, |
| 78 | }, |
| 79 | }; |
| 80 | |
Ben Dooks | 438a5d4 | 2008-11-19 15:41:34 +0000 | [diff] [blame] | 81 | /* framebuffer and LCD setup. */ |
| 82 | |
| 83 | /* GPF15 = LCD backlight control |
| 84 | * GPF13 => Panel power |
| 85 | * GPN5 = LCD nRESET signal |
| 86 | * PWM_TOUT1 => backlight brightness |
| 87 | */ |
| 88 | |
| 89 | static void smdk6410_lcd_power_set(struct plat_lcd_data *pd, |
| 90 | unsigned int power) |
| 91 | { |
| 92 | if (power) { |
| 93 | gpio_direction_output(S3C64XX_GPF(13), 1); |
| 94 | gpio_direction_output(S3C64XX_GPF(15), 1); |
| 95 | |
| 96 | /* fire nRESET on power up */ |
| 97 | gpio_direction_output(S3C64XX_GPN(5), 0); |
| 98 | msleep(10); |
| 99 | gpio_direction_output(S3C64XX_GPN(5), 1); |
| 100 | msleep(1); |
| 101 | } else { |
| 102 | gpio_direction_output(S3C64XX_GPF(15), 0); |
| 103 | gpio_direction_output(S3C64XX_GPF(13), 0); |
| 104 | } |
| 105 | } |
| 106 | |
| 107 | static struct plat_lcd_data smdk6410_lcd_power_data = { |
| 108 | .set_power = smdk6410_lcd_power_set, |
| 109 | }; |
| 110 | |
| 111 | static struct platform_device smdk6410_lcd_powerdev = { |
| 112 | .name = "platform-lcd", |
| 113 | .dev.parent = &s3c_device_fb.dev, |
| 114 | .dev.platform_data = &smdk6410_lcd_power_data, |
| 115 | }; |
| 116 | |
| 117 | static struct s3c_fb_pd_win smdk6410_fb_win0 = { |
| 118 | /* this is to ensure we use win0 */ |
| 119 | .win_mode = { |
| 120 | .pixclock = 41094, |
| 121 | .left_margin = 8, |
| 122 | .right_margin = 13, |
| 123 | .upper_margin = 7, |
| 124 | .lower_margin = 5, |
| 125 | .hsync_len = 3, |
| 126 | .vsync_len = 1, |
| 127 | .xres = 800, |
| 128 | .yres = 480, |
| 129 | }, |
| 130 | .max_bpp = 32, |
| 131 | .default_bpp = 16, |
| 132 | }; |
| 133 | |
| 134 | /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ |
| 135 | static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { |
| 136 | .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, |
| 137 | .win[0] = &smdk6410_fb_win0, |
| 138 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, |
| 139 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, |
| 140 | }; |
| 141 | |
Mark Brown | 3056ea0 | 2009-01-27 16:18:01 +0000 | [diff] [blame] | 142 | static struct resource smdk6410_smsc911x_resources[] = { |
| 143 | [0] = { |
| 144 | .start = 0x18000000, |
| 145 | .end = 0x18000000 + SZ_64K - 1, |
| 146 | .flags = IORESOURCE_MEM, |
| 147 | }, |
| 148 | [1] = { |
| 149 | .start = S3C_EINT(10), |
| 150 | .end = S3C_EINT(10), |
| 151 | .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW, |
| 152 | }, |
| 153 | }; |
| 154 | |
| 155 | static struct smsc911x_platform_config smdk6410_smsc911x_pdata = { |
| 156 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, |
| 157 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, |
| 158 | .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, |
| 159 | .phy_interface = PHY_INTERFACE_MODE_MII, |
| 160 | }; |
| 161 | |
| 162 | |
| 163 | static struct platform_device smdk6410_smsc911x = { |
| 164 | .name = "smsc911x", |
| 165 | .id = -1, |
| 166 | .num_resources = ARRAY_SIZE(smdk6410_smsc911x_resources), |
| 167 | .resource = &smdk6410_smsc911x_resources[0], |
| 168 | .dev = { |
| 169 | .platform_data = &smdk6410_smsc911x_pdata, |
| 170 | }, |
| 171 | }; |
| 172 | |
Mark Brown | 027191a | 2009-01-23 16:29:43 +0000 | [diff] [blame] | 173 | static struct map_desc smdk6410_iodesc[] = {}; |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 174 | |
| 175 | static struct platform_device *smdk6410_devices[] __initdata = { |
Ben Dooks | b24636c | 2008-11-03 20:14:53 +0000 | [diff] [blame] | 176 | #ifdef CONFIG_SMDK6410_SD_CH0 |
Ben Dooks | 39057f2 | 2008-10-31 16:14:29 +0000 | [diff] [blame] | 177 | &s3c_device_hsmmc0, |
Ben Dooks | b24636c | 2008-11-03 20:14:53 +0000 | [diff] [blame] | 178 | #endif |
| 179 | #ifdef CONFIG_SMDK6410_SD_CH1 |
| 180 | &s3c_device_hsmmc1, |
| 181 | #endif |
Ben Dooks | d85fa24 | 2008-10-31 16:14:52 +0000 | [diff] [blame] | 182 | &s3c_device_i2c0, |
Ben Dooks | d7ea374 | 2008-10-31 16:14:57 +0000 | [diff] [blame] | 183 | &s3c_device_i2c1, |
Ben Dooks | 438a5d4 | 2008-11-19 15:41:34 +0000 | [diff] [blame] | 184 | &s3c_device_fb, |
| 185 | &smdk6410_lcd_powerdev, |
Mark Brown | 3056ea0 | 2009-01-27 16:18:01 +0000 | [diff] [blame] | 186 | |
| 187 | &smdk6410_smsc911x, |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 188 | }; |
| 189 | |
Mark Brown | ecc558a | 2009-02-17 15:59:38 +0000 | [diff] [blame^] | 190 | #ifdef CONFIG_SMDK6410_WM1190_EV1 |
| 191 | /* S3C64xx internal logic & PLL */ |
| 192 | static struct regulator_init_data wm8350_dcdc1_data = { |
| 193 | .constraints = { |
| 194 | .name = "PVDD_INT/PVDD_PLL", |
| 195 | .min_uV = 1200000, |
| 196 | .max_uV = 1200000, |
| 197 | .always_on = 1, |
| 198 | .apply_uV = 1, |
| 199 | }, |
| 200 | }; |
| 201 | |
| 202 | /* Memory */ |
| 203 | static struct regulator_init_data wm8350_dcdc3_data = { |
| 204 | .constraints = { |
| 205 | .name = "PVDD_MEM", |
| 206 | .min_uV = 1800000, |
| 207 | .max_uV = 1800000, |
| 208 | .always_on = 1, |
| 209 | .state_mem = { |
| 210 | .uV = 1800000, |
| 211 | .mode = REGULATOR_MODE_NORMAL, |
| 212 | .enabled = 1, |
| 213 | }, |
| 214 | .initial_state = PM_SUSPEND_MEM, |
| 215 | }, |
| 216 | }; |
| 217 | |
| 218 | /* USB, EXT, PCM, ADC/DAC, USB, MMC */ |
| 219 | static struct regulator_init_data wm8350_dcdc4_data = { |
| 220 | .constraints = { |
| 221 | .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV", |
| 222 | .min_uV = 3000000, |
| 223 | .max_uV = 3000000, |
| 224 | .always_on = 1, |
| 225 | }, |
| 226 | }; |
| 227 | |
| 228 | /* ARM core */ |
| 229 | static struct regulator_init_data wm8350_dcdc6_data = { |
| 230 | .constraints = { |
| 231 | .name = "PVDD_ARM", |
| 232 | .min_uV = 1000000, |
| 233 | .max_uV = 1300000, |
| 234 | .always_on = 1, |
| 235 | }, |
| 236 | }; |
| 237 | |
| 238 | /* Alive */ |
| 239 | static struct regulator_init_data wm8350_ldo1_data = { |
| 240 | .constraints = { |
| 241 | .name = "PVDD_ALIVE", |
| 242 | .min_uV = 1200000, |
| 243 | .max_uV = 1200000, |
| 244 | .always_on = 1, |
| 245 | .apply_uV = 1, |
| 246 | }, |
| 247 | }; |
| 248 | |
| 249 | /* OTG */ |
| 250 | static struct regulator_init_data wm8350_ldo2_data = { |
| 251 | .constraints = { |
| 252 | .name = "PVDD_OTG", |
| 253 | .min_uV = 3300000, |
| 254 | .max_uV = 3300000, |
| 255 | }, |
| 256 | }; |
| 257 | |
| 258 | /* LCD */ |
| 259 | static struct regulator_init_data wm8350_ldo3_data = { |
| 260 | .constraints = { |
| 261 | .name = "PVDD_LCD", |
| 262 | .min_uV = 3000000, |
| 263 | .max_uV = 3000000, |
| 264 | }, |
| 265 | }; |
| 266 | |
| 267 | /* OTGi/1190-EV1 HPVDD & AVDD */ |
| 268 | static struct regulator_init_data wm8350_ldo4_data = { |
| 269 | .constraints = { |
| 270 | .name = "PVDD_OTGI/HPVDD/AVDD", |
| 271 | .min_uV = 1200000, |
| 272 | .max_uV = 1200000, |
| 273 | .apply_uV = 1, |
| 274 | }, |
| 275 | }; |
| 276 | |
| 277 | static struct { |
| 278 | int regulator; |
| 279 | struct regulator_init_data *initdata; |
| 280 | } wm1190_regulators[] = { |
| 281 | { WM8350_DCDC_1, &wm8350_dcdc1_data }, |
| 282 | { WM8350_DCDC_3, &wm8350_dcdc3_data }, |
| 283 | { WM8350_DCDC_4, &wm8350_dcdc4_data }, |
| 284 | { WM8350_DCDC_6, &wm8350_dcdc6_data }, |
| 285 | { WM8350_LDO_1, &wm8350_ldo1_data }, |
| 286 | { WM8350_LDO_2, &wm8350_ldo2_data }, |
| 287 | { WM8350_LDO_3, &wm8350_ldo3_data }, |
| 288 | { WM8350_LDO_4, &wm8350_ldo4_data }, |
| 289 | }; |
| 290 | |
| 291 | static int __init smdk6410_wm8350_init(struct wm8350 *wm8350) |
| 292 | { |
| 293 | int i; |
| 294 | |
| 295 | /* Instantiate the regulators */ |
| 296 | for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++) |
| 297 | wm8350_register_regulator(wm8350, |
| 298 | wm1190_regulators[i].regulator, |
| 299 | wm1190_regulators[i].initdata); |
| 300 | |
| 301 | return 0; |
| 302 | } |
| 303 | |
| 304 | static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = { |
| 305 | .init = smdk6410_wm8350_init, |
| 306 | }; |
| 307 | #endif |
| 308 | |
Ben Dooks | 096941e | 2008-10-31 16:14:59 +0000 | [diff] [blame] | 309 | static struct i2c_board_info i2c_devs0[] __initdata = { |
| 310 | { I2C_BOARD_INFO("24c08", 0x50), }, |
Mark Brown | 7789747 | 2009-01-23 16:29:41 +0000 | [diff] [blame] | 311 | { I2C_BOARD_INFO("wm8580", 0x1b), }, |
Mark Brown | ecc558a | 2009-02-17 15:59:38 +0000 | [diff] [blame^] | 312 | |
| 313 | #ifdef CONFIG_SMDK6410_WM1190_EV1 |
| 314 | { I2C_BOARD_INFO("wm8350", 0x1a), |
| 315 | .platform_data = &smdk6410_wm8350_pdata, |
| 316 | .irq = S3C_EINT(12), |
| 317 | }, |
| 318 | #endif |
Ben Dooks | 096941e | 2008-10-31 16:14:59 +0000 | [diff] [blame] | 319 | }; |
| 320 | |
| 321 | static struct i2c_board_info i2c_devs1[] __initdata = { |
| 322 | { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 323 | }; |
| 324 | |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 325 | static void __init smdk6410_map_io(void) |
| 326 | { |
Ben Dooks | d6662c3 | 2008-12-12 00:24:40 +0000 | [diff] [blame] | 327 | u32 tmp; |
| 328 | |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 329 | s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); |
| 330 | s3c24xx_init_clocks(12000000); |
| 331 | s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); |
Ben Dooks | d6662c3 | 2008-12-12 00:24:40 +0000 | [diff] [blame] | 332 | |
| 333 | /* set the LCD type */ |
| 334 | |
| 335 | tmp = __raw_readl(S3C64XX_SPCON); |
| 336 | tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; |
| 337 | tmp |= S3C64XX_SPCON_LCD_SEL_RGB; |
| 338 | __raw_writel(tmp, S3C64XX_SPCON); |
| 339 | |
| 340 | /* remove the lcd bypass */ |
| 341 | tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); |
| 342 | tmp &= ~MIFPCON_LCD_BYPASS; |
| 343 | __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | static void __init smdk6410_machine_init(void) |
| 347 | { |
Ben Dooks | d85fa24 | 2008-10-31 16:14:52 +0000 | [diff] [blame] | 348 | s3c_i2c0_set_platdata(NULL); |
Ben Dooks | d7ea374 | 2008-10-31 16:14:57 +0000 | [diff] [blame] | 349 | s3c_i2c1_set_platdata(NULL); |
Ben Dooks | 438a5d4 | 2008-11-19 15:41:34 +0000 | [diff] [blame] | 350 | s3c_fb_set_platdata(&smdk6410_lcd_pdata); |
Ben Dooks | 096941e | 2008-10-31 16:14:59 +0000 | [diff] [blame] | 351 | |
Mark Brown | b7f9a94 | 2009-04-08 16:12:35 +0100 | [diff] [blame] | 352 | gpio_request(S3C64XX_GPN(5), "LCD power"); |
| 353 | gpio_request(S3C64XX_GPF(13), "LCD power"); |
| 354 | gpio_request(S3C64XX_GPF(15), "LCD power"); |
| 355 | |
Ben Dooks | 096941e | 2008-10-31 16:14:59 +0000 | [diff] [blame] | 356 | i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); |
| 357 | i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); |
| 358 | |
Ben Dooks | 5718df9 | 2008-10-21 14:07:09 +0100 | [diff] [blame] | 359 | platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); |
| 360 | } |
| 361 | |
| 362 | MACHINE_START(SMDK6410, "SMDK6410") |
| 363 | /* Maintainer: Ben Dooks <ben@fluff.org> */ |
| 364 | .phys_io = S3C_PA_UART & 0xfff00000, |
| 365 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, |
| 366 | .boot_params = S3C64XX_PA_SDRAM + 0x100, |
| 367 | |
| 368 | .init_irq = s3c6410_init_irq, |
| 369 | .map_io = smdk6410_map_io, |
| 370 | .init_machine = smdk6410_machine_init, |
| 371 | .timer = &s3c24xx_timer, |
| 372 | MACHINE_END |