blob: 58d9ca8ac0f2e0d7340d248bf27ef2c4b10a44ca [file] [log] [blame]
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001/*
2 * Cryptographic API.
3 *
4 * Support for ATMEL SHA1/SHA256 HW acceleration.
5 *
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Some ideas are from omap-sham.c drivers.
14 */
15
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/hw_random.h>
24#include <linux/platform_device.h>
25
26#include <linux/device.h>
Nicolas Royerebc82ef2012-07-01 19:19:46 +020027#include <linux/init.h>
28#include <linux/errno.h>
29#include <linux/interrupt.h>
Nicolas Royerebc82ef2012-07-01 19:19:46 +020030#include <linux/irq.h>
Nicolas Royerebc82ef2012-07-01 19:19:46 +020031#include <linux/scatterlist.h>
32#include <linux/dma-mapping.h>
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +020033#include <linux/of_device.h>
Nicolas Royerebc82ef2012-07-01 19:19:46 +020034#include <linux/delay.h>
35#include <linux/crypto.h>
36#include <linux/cryptohash.h>
37#include <crypto/scatterwalk.h>
38#include <crypto/algapi.h>
39#include <crypto/sha.h>
40#include <crypto/hash.h>
41#include <crypto/internal/hash.h>
Nicolas Royerd4905b32013-02-20 17:10:26 +010042#include <linux/platform_data/crypto-atmel.h>
Nicolas Royerebc82ef2012-07-01 19:19:46 +020043#include "atmel-sha-regs.h"
44
45/* SHA flags */
46#define SHA_FLAGS_BUSY BIT(0)
47#define SHA_FLAGS_FINAL BIT(1)
48#define SHA_FLAGS_DMA_ACTIVE BIT(2)
49#define SHA_FLAGS_OUTPUT_READY BIT(3)
50#define SHA_FLAGS_INIT BIT(4)
51#define SHA_FLAGS_CPU BIT(5)
52#define SHA_FLAGS_DMA_READY BIT(6)
53
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +010054/* bits[10:8] are reserved. */
55#define SHA_FLAGS_ALGO_MASK SHA_MR_ALGO_MASK
56#define SHA_FLAGS_SHA1 SHA_MR_ALGO_SHA1
57#define SHA_FLAGS_SHA256 SHA_MR_ALGO_SHA256
58#define SHA_FLAGS_SHA384 SHA_MR_ALGO_SHA384
59#define SHA_FLAGS_SHA512 SHA_MR_ALGO_SHA512
60#define SHA_FLAGS_SHA224 SHA_MR_ALGO_SHA224
61
Nicolas Royerebc82ef2012-07-01 19:19:46 +020062#define SHA_FLAGS_FINUP BIT(16)
63#define SHA_FLAGS_SG BIT(17)
Nicolas Royerd4905b32013-02-20 17:10:26 +010064#define SHA_FLAGS_ERROR BIT(23)
65#define SHA_FLAGS_PAD BIT(24)
Cyrille Pitchen7cee3502016-01-15 15:49:34 +010066#define SHA_FLAGS_RESTORE BIT(25)
Cyrille Pitcheneec12f62017-01-26 17:07:52 +010067#define SHA_FLAGS_IDATAR0 BIT(26)
68#define SHA_FLAGS_WAIT_DATARDY BIT(27)
Nicolas Royerebc82ef2012-07-01 19:19:46 +020069
70#define SHA_OP_UPDATE 1
71#define SHA_OP_FINAL 2
72
Cyrille Pitchencc831d32016-01-29 17:04:02 +010073#define SHA_BUFFER_LEN (PAGE_SIZE / 16)
Nicolas Royerebc82ef2012-07-01 19:19:46 +020074
75#define ATMEL_SHA_DMA_THRESHOLD 56
76
Nicolas Royerd4905b32013-02-20 17:10:26 +010077struct atmel_sha_caps {
78 bool has_dma;
79 bool has_dualbuff;
80 bool has_sha224;
81 bool has_sha_384_512;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +010082 bool has_uihv;
Nicolas Royerd4905b32013-02-20 17:10:26 +010083};
Nicolas Royerebc82ef2012-07-01 19:19:46 +020084
85struct atmel_sha_dev;
86
Cyrille Pitchencc831d32016-01-29 17:04:02 +010087/*
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +010088 * .statesize = sizeof(struct atmel_sha_reqctx) must be <= PAGE_SIZE / 8 as
Cyrille Pitchencc831d32016-01-29 17:04:02 +010089 * tested by the ahash_prepare_alg() function.
90 */
Nicolas Royerebc82ef2012-07-01 19:19:46 +020091struct atmel_sha_reqctx {
92 struct atmel_sha_dev *dd;
93 unsigned long flags;
94 unsigned long op;
95
Nicolas Royerd4905b32013-02-20 17:10:26 +010096 u8 digest[SHA512_DIGEST_SIZE] __aligned(sizeof(u32));
97 u64 digcnt[2];
Nicolas Royerebc82ef2012-07-01 19:19:46 +020098 size_t bufcnt;
99 size_t buflen;
100 dma_addr_t dma_addr;
101
102 /* walk state */
103 struct scatterlist *sg;
104 unsigned int offset; /* offset in current sg */
105 unsigned int total; /* total request */
106
Nicolas Royerd4905b32013-02-20 17:10:26 +0100107 size_t block_size;
108
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +0100109 u8 buffer[SHA_BUFFER_LEN + SHA512_BLOCK_SIZE] __aligned(sizeof(u32));
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200110};
111
Cyrille Pitchena29af932017-01-26 17:07:47 +0100112typedef int (*atmel_sha_fn_t)(struct atmel_sha_dev *);
113
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200114struct atmel_sha_ctx {
115 struct atmel_sha_dev *dd;
Cyrille Pitchena29af932017-01-26 17:07:47 +0100116 atmel_sha_fn_t start;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200117
118 unsigned long flags;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200119};
120
Nicolas Royerd4905b32013-02-20 17:10:26 +0100121#define ATMEL_SHA_QUEUE_LENGTH 50
122
123struct atmel_sha_dma {
124 struct dma_chan *chan;
125 struct dma_slave_config dma_conf;
126};
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200127
128struct atmel_sha_dev {
129 struct list_head list;
130 unsigned long phys_base;
131 struct device *dev;
132 struct clk *iclk;
133 int irq;
134 void __iomem *io_base;
135
136 spinlock_t lock;
137 int err;
138 struct tasklet_struct done_task;
Cyrille Pitchenf56809c2016-01-15 15:49:32 +0100139 struct tasklet_struct queue_task;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200140
141 unsigned long flags;
142 struct crypto_queue queue;
143 struct ahash_request *req;
Cyrille Pitchena29af932017-01-26 17:07:47 +0100144 bool is_async;
Cyrille Pitchenb5ce82a2017-01-26 17:07:48 +0100145 atmel_sha_fn_t resume;
Cyrille Pitcheneec12f62017-01-26 17:07:52 +0100146 atmel_sha_fn_t cpu_transfer_complete;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100147
148 struct atmel_sha_dma dma_lch_in;
149
150 struct atmel_sha_caps caps;
151
152 u32 hw_version;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200153};
154
155struct atmel_sha_drv {
156 struct list_head dev_list;
157 spinlock_t lock;
158};
159
160static struct atmel_sha_drv atmel_sha = {
161 .dev_list = LIST_HEAD_INIT(atmel_sha.dev_list),
162 .lock = __SPIN_LOCK_UNLOCKED(atmel_sha.lock),
163};
164
165static inline u32 atmel_sha_read(struct atmel_sha_dev *dd, u32 offset)
166{
167 return readl_relaxed(dd->io_base + offset);
168}
169
170static inline void atmel_sha_write(struct atmel_sha_dev *dd,
171 u32 offset, u32 value)
172{
173 writel_relaxed(value, dd->io_base + offset);
174}
175
Cyrille Pitchena29af932017-01-26 17:07:47 +0100176static inline int atmel_sha_complete(struct atmel_sha_dev *dd, int err)
177{
178 struct ahash_request *req = dd->req;
179
180 dd->flags &= ~(SHA_FLAGS_BUSY | SHA_FLAGS_FINAL | SHA_FLAGS_CPU |
181 SHA_FLAGS_DMA_READY | SHA_FLAGS_OUTPUT_READY);
182
183 clk_disable(dd->iclk);
184
185 if (dd->is_async && req->base.complete)
186 req->base.complete(&req->base, err);
187
188 /* handle new request */
189 tasklet_schedule(&dd->queue_task);
190
191 return err;
192}
193
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200194static size_t atmel_sha_append_sg(struct atmel_sha_reqctx *ctx)
195{
196 size_t count;
197
198 while ((ctx->bufcnt < ctx->buflen) && ctx->total) {
199 count = min(ctx->sg->length - ctx->offset, ctx->total);
200 count = min(count, ctx->buflen - ctx->bufcnt);
201
Leilei Zhao803eeae2015-04-07 17:45:05 +0800202 if (count <= 0) {
203 /*
204 * Check if count <= 0 because the buffer is full or
205 * because the sg length is 0. In the latest case,
206 * check if there is another sg in the list, a 0 length
207 * sg doesn't necessarily mean the end of the sg list.
208 */
209 if ((ctx->sg->length == 0) && !sg_is_last(ctx->sg)) {
210 ctx->sg = sg_next(ctx->sg);
211 continue;
212 } else {
213 break;
214 }
215 }
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200216
217 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, ctx->sg,
218 ctx->offset, count, 0);
219
220 ctx->bufcnt += count;
221 ctx->offset += count;
222 ctx->total -= count;
223
224 if (ctx->offset == ctx->sg->length) {
225 ctx->sg = sg_next(ctx->sg);
226 if (ctx->sg)
227 ctx->offset = 0;
228 else
229 ctx->total = 0;
230 }
231 }
232
233 return 0;
234}
235
236/*
Nicolas Royerd4905b32013-02-20 17:10:26 +0100237 * The purpose of this padding is to ensure that the padded message is a
238 * multiple of 512 bits (SHA1/SHA224/SHA256) or 1024 bits (SHA384/SHA512).
239 * The bit "1" is appended at the end of the message followed by
240 * "padlen-1" zero bits. Then a 64 bits block (SHA1/SHA224/SHA256) or
241 * 128 bits block (SHA384/SHA512) equals to the message length in bits
242 * is appended.
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200243 *
Nicolas Royerd4905b32013-02-20 17:10:26 +0100244 * For SHA1/SHA224/SHA256, padlen is calculated as followed:
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200245 * - if message length < 56 bytes then padlen = 56 - message length
246 * - else padlen = 64 + 56 - message length
Nicolas Royerd4905b32013-02-20 17:10:26 +0100247 *
248 * For SHA384/SHA512, padlen is calculated as followed:
249 * - if message length < 112 bytes then padlen = 112 - message length
250 * - else padlen = 128 + 112 - message length
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200251 */
252static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length)
253{
254 unsigned int index, padlen;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100255 u64 bits[2];
256 u64 size[2];
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200257
Nicolas Royerd4905b32013-02-20 17:10:26 +0100258 size[0] = ctx->digcnt[0];
259 size[1] = ctx->digcnt[1];
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200260
Nicolas Royerd4905b32013-02-20 17:10:26 +0100261 size[0] += ctx->bufcnt;
262 if (size[0] < ctx->bufcnt)
263 size[1]++;
264
265 size[0] += length;
266 if (size[0] < length)
267 size[1]++;
268
269 bits[1] = cpu_to_be64(size[0] << 3);
270 bits[0] = cpu_to_be64(size[1] << 3 | size[0] >> 61);
271
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +0100272 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
273 case SHA_FLAGS_SHA384:
274 case SHA_FLAGS_SHA512:
Nicolas Royerd4905b32013-02-20 17:10:26 +0100275 index = ctx->bufcnt & 0x7f;
276 padlen = (index < 112) ? (112 - index) : ((128+112) - index);
277 *(ctx->buffer + ctx->bufcnt) = 0x80;
278 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
279 memcpy(ctx->buffer + ctx->bufcnt + padlen, bits, 16);
280 ctx->bufcnt += padlen + 16;
281 ctx->flags |= SHA_FLAGS_PAD;
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +0100282 break;
283
284 default:
Nicolas Royerd4905b32013-02-20 17:10:26 +0100285 index = ctx->bufcnt & 0x3f;
286 padlen = (index < 56) ? (56 - index) : ((64+56) - index);
287 *(ctx->buffer + ctx->bufcnt) = 0x80;
288 memset(ctx->buffer + ctx->bufcnt + 1, 0, padlen-1);
289 memcpy(ctx->buffer + ctx->bufcnt + padlen, &bits[1], 8);
290 ctx->bufcnt += padlen + 8;
291 ctx->flags |= SHA_FLAGS_PAD;
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +0100292 break;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100293 }
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200294}
295
Cyrille Pitchen8340c7f2017-01-26 17:07:46 +0100296static struct atmel_sha_dev *atmel_sha_find_dev(struct atmel_sha_ctx *tctx)
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200297{
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200298 struct atmel_sha_dev *dd = NULL;
299 struct atmel_sha_dev *tmp;
300
301 spin_lock_bh(&atmel_sha.lock);
302 if (!tctx->dd) {
303 list_for_each_entry(tmp, &atmel_sha.dev_list, list) {
304 dd = tmp;
305 break;
306 }
307 tctx->dd = dd;
308 } else {
309 dd = tctx->dd;
310 }
311
312 spin_unlock_bh(&atmel_sha.lock);
313
Cyrille Pitchen8340c7f2017-01-26 17:07:46 +0100314 return dd;
315}
316
317static int atmel_sha_init(struct ahash_request *req)
318{
319 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
320 struct atmel_sha_ctx *tctx = crypto_ahash_ctx(tfm);
321 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
322 struct atmel_sha_dev *dd = atmel_sha_find_dev(tctx);
323
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200324 ctx->dd = dd;
325
326 ctx->flags = 0;
327
328 dev_dbg(dd->dev, "init: digest size: %d\n",
329 crypto_ahash_digestsize(tfm));
330
Nicolas Royerd4905b32013-02-20 17:10:26 +0100331 switch (crypto_ahash_digestsize(tfm)) {
332 case SHA1_DIGEST_SIZE:
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200333 ctx->flags |= SHA_FLAGS_SHA1;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100334 ctx->block_size = SHA1_BLOCK_SIZE;
335 break;
336 case SHA224_DIGEST_SIZE:
337 ctx->flags |= SHA_FLAGS_SHA224;
338 ctx->block_size = SHA224_BLOCK_SIZE;
339 break;
340 case SHA256_DIGEST_SIZE:
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200341 ctx->flags |= SHA_FLAGS_SHA256;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100342 ctx->block_size = SHA256_BLOCK_SIZE;
343 break;
344 case SHA384_DIGEST_SIZE:
345 ctx->flags |= SHA_FLAGS_SHA384;
346 ctx->block_size = SHA384_BLOCK_SIZE;
347 break;
348 case SHA512_DIGEST_SIZE:
349 ctx->flags |= SHA_FLAGS_SHA512;
350 ctx->block_size = SHA512_BLOCK_SIZE;
351 break;
352 default:
353 return -EINVAL;
354 break;
355 }
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200356
357 ctx->bufcnt = 0;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100358 ctx->digcnt[0] = 0;
359 ctx->digcnt[1] = 0;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200360 ctx->buflen = SHA_BUFFER_LEN;
361
362 return 0;
363}
364
365static void atmel_sha_write_ctrl(struct atmel_sha_dev *dd, int dma)
366{
367 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100368 u32 valmr = SHA_MR_MODE_AUTO;
369 unsigned int i, hashsize = 0;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200370
371 if (likely(dma)) {
Nicolas Royerd4905b32013-02-20 17:10:26 +0100372 if (!dd->caps.has_dma)
373 atmel_sha_write(dd, SHA_IER, SHA_INT_TXBUFE);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200374 valmr = SHA_MR_MODE_PDC;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100375 if (dd->caps.has_dualbuff)
376 valmr |= SHA_MR_DUALBUFF;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200377 } else {
378 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
379 }
380
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100381 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
382 case SHA_FLAGS_SHA1:
Nicolas Royerd4905b32013-02-20 17:10:26 +0100383 valmr |= SHA_MR_ALGO_SHA1;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100384 hashsize = SHA1_DIGEST_SIZE;
385 break;
386
387 case SHA_FLAGS_SHA224:
Nicolas Royerd4905b32013-02-20 17:10:26 +0100388 valmr |= SHA_MR_ALGO_SHA224;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100389 hashsize = SHA256_DIGEST_SIZE;
390 break;
391
392 case SHA_FLAGS_SHA256:
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200393 valmr |= SHA_MR_ALGO_SHA256;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100394 hashsize = SHA256_DIGEST_SIZE;
395 break;
396
397 case SHA_FLAGS_SHA384:
Nicolas Royerd4905b32013-02-20 17:10:26 +0100398 valmr |= SHA_MR_ALGO_SHA384;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100399 hashsize = SHA512_DIGEST_SIZE;
400 break;
401
402 case SHA_FLAGS_SHA512:
Nicolas Royerd4905b32013-02-20 17:10:26 +0100403 valmr |= SHA_MR_ALGO_SHA512;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100404 hashsize = SHA512_DIGEST_SIZE;
405 break;
406
407 default:
408 break;
409 }
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200410
411 /* Setting CR_FIRST only for the first iteration */
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100412 if (!(ctx->digcnt[0] || ctx->digcnt[1])) {
413 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
414 } else if (dd->caps.has_uihv && (ctx->flags & SHA_FLAGS_RESTORE)) {
415 const u32 *hash = (const u32 *)ctx->digest;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200416
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100417 /*
418 * Restore the hardware context: update the User Initialize
419 * Hash Value (UIHV) with the value saved when the latest
420 * 'update' operation completed on this very same crypto
421 * request.
422 */
423 ctx->flags &= ~SHA_FLAGS_RESTORE;
424 atmel_sha_write(dd, SHA_CR, SHA_CR_WUIHV);
425 for (i = 0; i < hashsize / sizeof(u32); ++i)
426 atmel_sha_write(dd, SHA_REG_DIN(i), hash[i]);
427 atmel_sha_write(dd, SHA_CR, SHA_CR_FIRST);
428 valmr |= SHA_MR_UIHV;
429 }
430 /*
431 * WARNING: If the UIHV feature is not available, the hardware CANNOT
432 * process concurrent requests: the internal registers used to store
433 * the hash/digest are still set to the partial digest output values
434 * computed during the latest round.
435 */
436
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200437 atmel_sha_write(dd, SHA_MR, valmr);
438}
439
Cyrille Pitchen9064ed92017-01-26 17:07:50 +0100440static inline int atmel_sha_wait_for_data_ready(struct atmel_sha_dev *dd,
441 atmel_sha_fn_t resume)
442{
443 u32 isr = atmel_sha_read(dd, SHA_ISR);
444
445 if (unlikely(isr & SHA_INT_DATARDY))
446 return resume(dd);
447
448 dd->resume = resume;
449 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
450 return -EINPROGRESS;
451}
452
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200453static int atmel_sha_xmit_cpu(struct atmel_sha_dev *dd, const u8 *buf,
454 size_t length, int final)
455{
456 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
457 int count, len32;
458 const u32 *buffer = (const u32 *)buf;
459
Nicolas Royerd4905b32013-02-20 17:10:26 +0100460 dev_dbg(dd->dev, "xmit_cpu: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
461 ctx->digcnt[1], ctx->digcnt[0], length, final);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200462
463 atmel_sha_write_ctrl(dd, 0);
464
465 /* should be non-zero before next lines to disable clocks later */
Nicolas Royerd4905b32013-02-20 17:10:26 +0100466 ctx->digcnt[0] += length;
467 if (ctx->digcnt[0] < length)
468 ctx->digcnt[1]++;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200469
470 if (final)
471 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
472
473 len32 = DIV_ROUND_UP(length, sizeof(u32));
474
475 dd->flags |= SHA_FLAGS_CPU;
476
477 for (count = 0; count < len32; count++)
478 atmel_sha_write(dd, SHA_REG_DIN(count), buffer[count]);
479
480 return -EINPROGRESS;
481}
482
483static int atmel_sha_xmit_pdc(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
484 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
485{
486 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
487 int len32;
488
Nicolas Royerd4905b32013-02-20 17:10:26 +0100489 dev_dbg(dd->dev, "xmit_pdc: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
490 ctx->digcnt[1], ctx->digcnt[0], length1, final);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200491
492 len32 = DIV_ROUND_UP(length1, sizeof(u32));
493 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTDIS);
494 atmel_sha_write(dd, SHA_TPR, dma_addr1);
495 atmel_sha_write(dd, SHA_TCR, len32);
496
497 len32 = DIV_ROUND_UP(length2, sizeof(u32));
498 atmel_sha_write(dd, SHA_TNPR, dma_addr2);
499 atmel_sha_write(dd, SHA_TNCR, len32);
500
501 atmel_sha_write_ctrl(dd, 1);
502
503 /* should be non-zero before next lines to disable clocks later */
Nicolas Royerd4905b32013-02-20 17:10:26 +0100504 ctx->digcnt[0] += length1;
505 if (ctx->digcnt[0] < length1)
506 ctx->digcnt[1]++;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200507
508 if (final)
509 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
510
511 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
512
513 /* Start DMA transfer */
514 atmel_sha_write(dd, SHA_PTCR, SHA_PTCR_TXTEN);
515
516 return -EINPROGRESS;
517}
518
Nicolas Royerd4905b32013-02-20 17:10:26 +0100519static void atmel_sha_dma_callback(void *data)
520{
521 struct atmel_sha_dev *dd = data;
522
Cyrille Pitchena29af932017-01-26 17:07:47 +0100523 dd->is_async = true;
524
Nicolas Royerd4905b32013-02-20 17:10:26 +0100525 /* dma_lch_in - completed - wait DATRDY */
526 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
527}
528
529static int atmel_sha_xmit_dma(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
530 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
531{
532 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
533 struct dma_async_tx_descriptor *in_desc;
534 struct scatterlist sg[2];
535
536 dev_dbg(dd->dev, "xmit_dma: digcnt: 0x%llx 0x%llx, length: %d, final: %d\n",
537 ctx->digcnt[1], ctx->digcnt[0], length1, final);
538
Leilei Zhao3f1992c2015-04-07 17:45:07 +0800539 dd->dma_lch_in.dma_conf.src_maxburst = 16;
540 dd->dma_lch_in.dma_conf.dst_maxburst = 16;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100541
542 dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
543
544 if (length2) {
545 sg_init_table(sg, 2);
546 sg_dma_address(&sg[0]) = dma_addr1;
547 sg_dma_len(&sg[0]) = length1;
548 sg_dma_address(&sg[1]) = dma_addr2;
549 sg_dma_len(&sg[1]) = length2;
550 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 2,
551 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
552 } else {
553 sg_init_table(sg, 1);
554 sg_dma_address(&sg[0]) = dma_addr1;
555 sg_dma_len(&sg[0]) = length1;
556 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, sg, 1,
557 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
558 }
559 if (!in_desc)
Cyrille Pitchena29af932017-01-26 17:07:47 +0100560 atmel_sha_complete(dd, -EINVAL);
Nicolas Royerd4905b32013-02-20 17:10:26 +0100561
562 in_desc->callback = atmel_sha_dma_callback;
563 in_desc->callback_param = dd;
564
565 atmel_sha_write_ctrl(dd, 1);
566
567 /* should be non-zero before next lines to disable clocks later */
568 ctx->digcnt[0] += length1;
569 if (ctx->digcnt[0] < length1)
570 ctx->digcnt[1]++;
571
572 if (final)
573 dd->flags |= SHA_FLAGS_FINAL; /* catch last interrupt */
574
575 dd->flags |= SHA_FLAGS_DMA_ACTIVE;
576
577 /* Start DMA transfer */
578 dmaengine_submit(in_desc);
579 dma_async_issue_pending(dd->dma_lch_in.chan);
580
581 return -EINPROGRESS;
582}
583
584static int atmel_sha_xmit_start(struct atmel_sha_dev *dd, dma_addr_t dma_addr1,
585 size_t length1, dma_addr_t dma_addr2, size_t length2, int final)
586{
587 if (dd->caps.has_dma)
588 return atmel_sha_xmit_dma(dd, dma_addr1, length1,
589 dma_addr2, length2, final);
590 else
591 return atmel_sha_xmit_pdc(dd, dma_addr1, length1,
592 dma_addr2, length2, final);
593}
594
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200595static int atmel_sha_update_cpu(struct atmel_sha_dev *dd)
596{
597 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
598 int bufcnt;
599
600 atmel_sha_append_sg(ctx);
601 atmel_sha_fill_padding(ctx, 0);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200602 bufcnt = ctx->bufcnt;
603 ctx->bufcnt = 0;
604
605 return atmel_sha_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
606}
607
608static int atmel_sha_xmit_dma_map(struct atmel_sha_dev *dd,
609 struct atmel_sha_reqctx *ctx,
610 size_t length, int final)
611{
612 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
Nicolas Royerd4905b32013-02-20 17:10:26 +0100613 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200614 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
615 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen +
Nicolas Royerd4905b32013-02-20 17:10:26 +0100616 ctx->block_size);
Cyrille Pitchena29af932017-01-26 17:07:47 +0100617 atmel_sha_complete(dd, -EINVAL);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200618 }
619
620 ctx->flags &= ~SHA_FLAGS_SG;
621
622 /* next call does not fail... so no unmap in the case of error */
Nicolas Royerd4905b32013-02-20 17:10:26 +0100623 return atmel_sha_xmit_start(dd, ctx->dma_addr, length, 0, 0, final);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200624}
625
626static int atmel_sha_update_dma_slow(struct atmel_sha_dev *dd)
627{
628 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
629 unsigned int final;
630 size_t count;
631
632 atmel_sha_append_sg(ctx);
633
634 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
635
Nicolas Royerd4905b32013-02-20 17:10:26 +0100636 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: 0x%llx 0x%llx, final: %d\n",
637 ctx->bufcnt, ctx->digcnt[1], ctx->digcnt[0], final);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200638
639 if (final)
640 atmel_sha_fill_padding(ctx, 0);
641
Ludovic Desroches00992862015-04-07 17:45:04 +0800642 if (final || (ctx->bufcnt == ctx->buflen)) {
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200643 count = ctx->bufcnt;
644 ctx->bufcnt = 0;
645 return atmel_sha_xmit_dma_map(dd, ctx, count, final);
646 }
647
648 return 0;
649}
650
651static int atmel_sha_update_dma_start(struct atmel_sha_dev *dd)
652{
653 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
654 unsigned int length, final, tail;
655 struct scatterlist *sg;
656 unsigned int count;
657
658 if (!ctx->total)
659 return 0;
660
661 if (ctx->bufcnt || ctx->offset)
662 return atmel_sha_update_dma_slow(dd);
663
Nicolas Royerd4905b32013-02-20 17:10:26 +0100664 dev_dbg(dd->dev, "fast: digcnt: 0x%llx 0x%llx, bufcnt: %u, total: %u\n",
665 ctx->digcnt[1], ctx->digcnt[0], ctx->bufcnt, ctx->total);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200666
667 sg = ctx->sg;
668
669 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
670 return atmel_sha_update_dma_slow(dd);
671
Nicolas Royerd4905b32013-02-20 17:10:26 +0100672 if (!sg_is_last(sg) && !IS_ALIGNED(sg->length, ctx->block_size))
673 /* size is not ctx->block_size aligned */
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200674 return atmel_sha_update_dma_slow(dd);
675
676 length = min(ctx->total, sg->length);
677
678 if (sg_is_last(sg)) {
679 if (!(ctx->flags & SHA_FLAGS_FINUP)) {
Nicolas Royerd4905b32013-02-20 17:10:26 +0100680 /* not last sg must be ctx->block_size aligned */
681 tail = length & (ctx->block_size - 1);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200682 length -= tail;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200683 }
684 }
685
686 ctx->total -= length;
687 ctx->offset = length; /* offset where to start slow */
688
689 final = (ctx->flags & SHA_FLAGS_FINUP) && !ctx->total;
690
691 /* Add padding */
692 if (final) {
Nicolas Royerd4905b32013-02-20 17:10:26 +0100693 tail = length & (ctx->block_size - 1);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200694 length -= tail;
695 ctx->total += tail;
696 ctx->offset = length; /* offset where to start slow */
697
698 sg = ctx->sg;
699 atmel_sha_append_sg(ctx);
700
701 atmel_sha_fill_padding(ctx, length);
702
703 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer,
Nicolas Royerd4905b32013-02-20 17:10:26 +0100704 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200705 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
706 dev_err(dd->dev, "dma %u bytes error\n",
Nicolas Royerd4905b32013-02-20 17:10:26 +0100707 ctx->buflen + ctx->block_size);
Cyrille Pitchena29af932017-01-26 17:07:47 +0100708 atmel_sha_complete(dd, -EINVAL);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200709 }
710
711 if (length == 0) {
712 ctx->flags &= ~SHA_FLAGS_SG;
713 count = ctx->bufcnt;
714 ctx->bufcnt = 0;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100715 return atmel_sha_xmit_start(dd, ctx->dma_addr, count, 0,
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200716 0, final);
717 } else {
718 ctx->sg = sg;
719 if (!dma_map_sg(dd->dev, ctx->sg, 1,
720 DMA_TO_DEVICE)) {
721 dev_err(dd->dev, "dma_map_sg error\n");
Cyrille Pitchena29af932017-01-26 17:07:47 +0100722 atmel_sha_complete(dd, -EINVAL);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200723 }
724
725 ctx->flags |= SHA_FLAGS_SG;
726
727 count = ctx->bufcnt;
728 ctx->bufcnt = 0;
Nicolas Royerd4905b32013-02-20 17:10:26 +0100729 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg),
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200730 length, ctx->dma_addr, count, final);
731 }
732 }
733
734 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
735 dev_err(dd->dev, "dma_map_sg error\n");
Cyrille Pitchena29af932017-01-26 17:07:47 +0100736 atmel_sha_complete(dd, -EINVAL);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200737 }
738
739 ctx->flags |= SHA_FLAGS_SG;
740
741 /* next call does not fail... so no unmap in the case of error */
Nicolas Royerd4905b32013-02-20 17:10:26 +0100742 return atmel_sha_xmit_start(dd, sg_dma_address(ctx->sg), length, 0,
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200743 0, final);
744}
745
746static int atmel_sha_update_dma_stop(struct atmel_sha_dev *dd)
747{
748 struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
749
750 if (ctx->flags & SHA_FLAGS_SG) {
751 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
752 if (ctx->sg->length == ctx->offset) {
753 ctx->sg = sg_next(ctx->sg);
754 if (ctx->sg)
755 ctx->offset = 0;
756 }
Nicolas Royerd4905b32013-02-20 17:10:26 +0100757 if (ctx->flags & SHA_FLAGS_PAD) {
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200758 dma_unmap_single(dd->dev, ctx->dma_addr,
Nicolas Royerd4905b32013-02-20 17:10:26 +0100759 ctx->buflen + ctx->block_size, DMA_TO_DEVICE);
760 }
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200761 } else {
762 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen +
Nicolas Royerd4905b32013-02-20 17:10:26 +0100763 ctx->block_size, DMA_TO_DEVICE);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200764 }
765
766 return 0;
767}
768
769static int atmel_sha_update_req(struct atmel_sha_dev *dd)
770{
771 struct ahash_request *req = dd->req;
772 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
773 int err;
774
Nicolas Royerd4905b32013-02-20 17:10:26 +0100775 dev_dbg(dd->dev, "update_req: total: %u, digcnt: 0x%llx 0x%llx\n",
776 ctx->total, ctx->digcnt[1], ctx->digcnt[0]);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200777
778 if (ctx->flags & SHA_FLAGS_CPU)
779 err = atmel_sha_update_cpu(dd);
780 else
781 err = atmel_sha_update_dma_start(dd);
782
783 /* wait for dma completion before can take more data */
Nicolas Royerd4905b32013-02-20 17:10:26 +0100784 dev_dbg(dd->dev, "update: err: %d, digcnt: 0x%llx 0%llx\n",
785 err, ctx->digcnt[1], ctx->digcnt[0]);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200786
787 return err;
788}
789
790static int atmel_sha_final_req(struct atmel_sha_dev *dd)
791{
792 struct ahash_request *req = dd->req;
793 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
794 int err = 0;
795 int count;
796
797 if (ctx->bufcnt >= ATMEL_SHA_DMA_THRESHOLD) {
798 atmel_sha_fill_padding(ctx, 0);
799 count = ctx->bufcnt;
800 ctx->bufcnt = 0;
801 err = atmel_sha_xmit_dma_map(dd, ctx, count, 1);
802 }
803 /* faster to handle last block with cpu */
804 else {
805 atmel_sha_fill_padding(ctx, 0);
806 count = ctx->bufcnt;
807 ctx->bufcnt = 0;
808 err = atmel_sha_xmit_cpu(dd, ctx->buffer, count, 1);
809 }
810
811 dev_dbg(dd->dev, "final_req: err: %d\n", err);
812
813 return err;
814}
815
816static void atmel_sha_copy_hash(struct ahash_request *req)
817{
818 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
819 u32 *hash = (u32 *)ctx->digest;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100820 unsigned int i, hashsize;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200821
Cyrille Pitchen7cee3502016-01-15 15:49:34 +0100822 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
823 case SHA_FLAGS_SHA1:
824 hashsize = SHA1_DIGEST_SIZE;
825 break;
826
827 case SHA_FLAGS_SHA224:
828 case SHA_FLAGS_SHA256:
829 hashsize = SHA256_DIGEST_SIZE;
830 break;
831
832 case SHA_FLAGS_SHA384:
833 case SHA_FLAGS_SHA512:
834 hashsize = SHA512_DIGEST_SIZE;
835 break;
836
837 default:
838 /* Should not happen... */
839 return;
840 }
841
842 for (i = 0; i < hashsize / sizeof(u32); ++i)
843 hash[i] = atmel_sha_read(ctx->dd, SHA_REG_DIGEST(i));
844 ctx->flags |= SHA_FLAGS_RESTORE;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200845}
846
847static void atmel_sha_copy_ready_hash(struct ahash_request *req)
848{
849 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
850
851 if (!req->result)
852 return;
853
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +0100854 switch (ctx->flags & SHA_FLAGS_ALGO_MASK) {
855 default:
856 case SHA_FLAGS_SHA1:
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200857 memcpy(req->result, ctx->digest, SHA1_DIGEST_SIZE);
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +0100858 break;
859
860 case SHA_FLAGS_SHA224:
Nicolas Royerd4905b32013-02-20 17:10:26 +0100861 memcpy(req->result, ctx->digest, SHA224_DIGEST_SIZE);
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +0100862 break;
863
864 case SHA_FLAGS_SHA256:
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200865 memcpy(req->result, ctx->digest, SHA256_DIGEST_SIZE);
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +0100866 break;
867
868 case SHA_FLAGS_SHA384:
Nicolas Royerd4905b32013-02-20 17:10:26 +0100869 memcpy(req->result, ctx->digest, SHA384_DIGEST_SIZE);
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +0100870 break;
871
872 case SHA_FLAGS_SHA512:
Nicolas Royerd4905b32013-02-20 17:10:26 +0100873 memcpy(req->result, ctx->digest, SHA512_DIGEST_SIZE);
Cyrille Pitchenf07ceba2017-01-26 17:07:49 +0100874 break;
875 }
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200876}
877
878static int atmel_sha_finish(struct ahash_request *req)
879{
880 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
881 struct atmel_sha_dev *dd = ctx->dd;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200882
Nicolas Royerd4905b32013-02-20 17:10:26 +0100883 if (ctx->digcnt[0] || ctx->digcnt[1])
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200884 atmel_sha_copy_ready_hash(req);
885
Nicolas Royerd4905b32013-02-20 17:10:26 +0100886 dev_dbg(dd->dev, "digcnt: 0x%llx 0x%llx, bufcnt: %d\n", ctx->digcnt[1],
887 ctx->digcnt[0], ctx->bufcnt);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200888
Rahul Pathak871b88a2015-12-14 08:44:19 +0000889 return 0;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200890}
891
892static void atmel_sha_finish_req(struct ahash_request *req, int err)
893{
894 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
895 struct atmel_sha_dev *dd = ctx->dd;
896
897 if (!err) {
898 atmel_sha_copy_hash(req);
899 if (SHA_FLAGS_FINAL & dd->flags)
900 err = atmel_sha_finish(req);
901 } else {
902 ctx->flags |= SHA_FLAGS_ERROR;
903 }
904
905 /* atomic operation is not needed here */
Cyrille Pitchena29af932017-01-26 17:07:47 +0100906 (void)atmel_sha_complete(dd, err);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200907}
908
909static int atmel_sha_hw_init(struct atmel_sha_dev *dd)
910{
LABBE Corentin9d83d292015-10-02 14:12:58 +0200911 int err;
912
Cyrille Pitchenc0330422016-02-05 13:45:13 +0100913 err = clk_enable(dd->iclk);
LABBE Corentin9d83d292015-10-02 14:12:58 +0200914 if (err)
915 return err;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200916
Nicolas Royerd4905b32013-02-20 17:10:26 +0100917 if (!(SHA_FLAGS_INIT & dd->flags)) {
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200918 atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST);
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200919 dd->flags |= SHA_FLAGS_INIT;
920 dd->err = 0;
921 }
922
923 return 0;
924}
925
Nicolas Royerd4905b32013-02-20 17:10:26 +0100926static inline unsigned int atmel_sha_get_version(struct atmel_sha_dev *dd)
927{
928 return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff;
929}
930
931static void atmel_sha_hw_version_init(struct atmel_sha_dev *dd)
932{
933 atmel_sha_hw_init(dd);
934
935 dd->hw_version = atmel_sha_get_version(dd);
936
937 dev_info(dd->dev,
938 "version: 0x%x\n", dd->hw_version);
939
Cyrille Pitchenc0330422016-02-05 13:45:13 +0100940 clk_disable(dd->iclk);
Nicolas Royerd4905b32013-02-20 17:10:26 +0100941}
942
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200943static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
944 struct ahash_request *req)
945{
946 struct crypto_async_request *async_req, *backlog;
Cyrille Pitchena29af932017-01-26 17:07:47 +0100947 struct atmel_sha_ctx *ctx;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200948 unsigned long flags;
Cyrille Pitchena29af932017-01-26 17:07:47 +0100949 bool start_async;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200950 int err = 0, ret = 0;
951
952 spin_lock_irqsave(&dd->lock, flags);
953 if (req)
954 ret = ahash_enqueue_request(&dd->queue, req);
955
956 if (SHA_FLAGS_BUSY & dd->flags) {
957 spin_unlock_irqrestore(&dd->lock, flags);
958 return ret;
959 }
960
961 backlog = crypto_get_backlog(&dd->queue);
962 async_req = crypto_dequeue_request(&dd->queue);
963 if (async_req)
964 dd->flags |= SHA_FLAGS_BUSY;
965
966 spin_unlock_irqrestore(&dd->lock, flags);
967
968 if (!async_req)
969 return ret;
970
971 if (backlog)
972 backlog->complete(backlog, -EINPROGRESS);
973
Cyrille Pitchena29af932017-01-26 17:07:47 +0100974 ctx = crypto_tfm_ctx(async_req->tfm);
975
976 dd->req = ahash_request_cast(async_req);
977 start_async = (dd->req != req);
978 dd->is_async = start_async;
979
980 /* WARNING: ctx->start() MAY change dd->is_async. */
981 err = ctx->start(dd);
982 return (start_async) ? ret : err;
983}
984
Cyrille Pitchenb5ce82a2017-01-26 17:07:48 +0100985static int atmel_sha_done(struct atmel_sha_dev *dd);
986
Cyrille Pitchena29af932017-01-26 17:07:47 +0100987static int atmel_sha_start(struct atmel_sha_dev *dd)
988{
989 struct ahash_request *req = dd->req;
990 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
991 int err;
Nicolas Royerebc82ef2012-07-01 19:19:46 +0200992
993 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
994 ctx->op, req->nbytes);
995
996 err = atmel_sha_hw_init(dd);
997
998 if (err)
999 goto err1;
1000
Cyrille Pitchenb5ce82a2017-01-26 17:07:48 +01001001 dd->resume = atmel_sha_done;
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001002 if (ctx->op == SHA_OP_UPDATE) {
1003 err = atmel_sha_update_req(dd);
Nicolas Royerd4905b32013-02-20 17:10:26 +01001004 if (err != -EINPROGRESS && (ctx->flags & SHA_FLAGS_FINUP))
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001005 /* no final() after finup() */
1006 err = atmel_sha_final_req(dd);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001007 } else if (ctx->op == SHA_OP_FINAL) {
1008 err = atmel_sha_final_req(dd);
1009 }
1010
1011err1:
1012 if (err != -EINPROGRESS)
1013 /* done_task will not finish it, so do it here */
1014 atmel_sha_finish_req(req, err);
1015
1016 dev_dbg(dd->dev, "exit, err: %d\n", err);
1017
Cyrille Pitchena29af932017-01-26 17:07:47 +01001018 return err;
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001019}
1020
1021static int atmel_sha_enqueue(struct ahash_request *req, unsigned int op)
1022{
1023 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1024 struct atmel_sha_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1025 struct atmel_sha_dev *dd = tctx->dd;
1026
1027 ctx->op = op;
1028
1029 return atmel_sha_handle_queue(dd, req);
1030}
1031
1032static int atmel_sha_update(struct ahash_request *req)
1033{
1034 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1035
1036 if (!req->nbytes)
1037 return 0;
1038
1039 ctx->total = req->nbytes;
1040 ctx->sg = req->src;
1041 ctx->offset = 0;
1042
1043 if (ctx->flags & SHA_FLAGS_FINUP) {
1044 if (ctx->bufcnt + ctx->total < ATMEL_SHA_DMA_THRESHOLD)
1045 /* faster to use CPU for short transfers */
1046 ctx->flags |= SHA_FLAGS_CPU;
1047 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1048 atmel_sha_append_sg(ctx);
1049 return 0;
1050 }
1051 return atmel_sha_enqueue(req, SHA_OP_UPDATE);
1052}
1053
1054static int atmel_sha_final(struct ahash_request *req)
1055{
1056 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001057
1058 ctx->flags |= SHA_FLAGS_FINUP;
1059
1060 if (ctx->flags & SHA_FLAGS_ERROR)
1061 return 0; /* uncompleted hash is not needed */
1062
Cyrille Pitchenad841122016-02-08 16:26:49 +01001063 if (ctx->flags & SHA_FLAGS_PAD)
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001064 /* copy ready hash (+ finalize hmac) */
1065 return atmel_sha_finish(req);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001066
Cyrille Pitchenad841122016-02-08 16:26:49 +01001067 return atmel_sha_enqueue(req, SHA_OP_FINAL);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001068}
1069
1070static int atmel_sha_finup(struct ahash_request *req)
1071{
1072 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1073 int err1, err2;
1074
1075 ctx->flags |= SHA_FLAGS_FINUP;
1076
1077 err1 = atmel_sha_update(req);
1078 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1079 return err1;
1080
1081 /*
1082 * final() has to be always called to cleanup resources
1083 * even if udpate() failed, except EINPROGRESS
1084 */
1085 err2 = atmel_sha_final(req);
1086
1087 return err1 ?: err2;
1088}
1089
1090static int atmel_sha_digest(struct ahash_request *req)
1091{
1092 return atmel_sha_init(req) ?: atmel_sha_finup(req);
1093}
1094
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001095
1096static int atmel_sha_export(struct ahash_request *req, void *out)
1097{
1098 const struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001099
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +01001100 memcpy(out, ctx, sizeof(*ctx));
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001101 return 0;
1102}
1103
1104static int atmel_sha_import(struct ahash_request *req, const void *in)
1105{
1106 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001107
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +01001108 memcpy(ctx, in, sizeof(*ctx));
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001109 return 0;
1110}
1111
Svenning Sørensenbe95f0f2014-12-05 01:18:57 +01001112static int atmel_sha_cra_init(struct crypto_tfm *tfm)
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001113{
Cyrille Pitchena29af932017-01-26 17:07:47 +01001114 struct atmel_sha_ctx *ctx = crypto_tfm_ctx(tfm);
1115
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001116 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +01001117 sizeof(struct atmel_sha_reqctx));
Cyrille Pitchena29af932017-01-26 17:07:47 +01001118 ctx->start = atmel_sha_start;
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001119
1120 return 0;
1121}
1122
Nicolas Royerd4905b32013-02-20 17:10:26 +01001123static struct ahash_alg sha_1_256_algs[] = {
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001124{
1125 .init = atmel_sha_init,
1126 .update = atmel_sha_update,
1127 .final = atmel_sha_final,
1128 .finup = atmel_sha_finup,
1129 .digest = atmel_sha_digest,
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001130 .export = atmel_sha_export,
1131 .import = atmel_sha_import,
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001132 .halg = {
1133 .digestsize = SHA1_DIGEST_SIZE,
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +01001134 .statesize = sizeof(struct atmel_sha_reqctx),
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001135 .base = {
1136 .cra_name = "sha1",
1137 .cra_driver_name = "atmel-sha1",
1138 .cra_priority = 100,
Svenning Sørensenbe95f0f2014-12-05 01:18:57 +01001139 .cra_flags = CRYPTO_ALG_ASYNC,
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001140 .cra_blocksize = SHA1_BLOCK_SIZE,
1141 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1142 .cra_alignmask = 0,
1143 .cra_module = THIS_MODULE,
1144 .cra_init = atmel_sha_cra_init,
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001145 }
1146 }
1147},
1148{
1149 .init = atmel_sha_init,
1150 .update = atmel_sha_update,
1151 .final = atmel_sha_final,
1152 .finup = atmel_sha_finup,
1153 .digest = atmel_sha_digest,
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001154 .export = atmel_sha_export,
1155 .import = atmel_sha_import,
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001156 .halg = {
1157 .digestsize = SHA256_DIGEST_SIZE,
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +01001158 .statesize = sizeof(struct atmel_sha_reqctx),
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001159 .base = {
1160 .cra_name = "sha256",
1161 .cra_driver_name = "atmel-sha256",
1162 .cra_priority = 100,
Svenning Sørensenbe95f0f2014-12-05 01:18:57 +01001163 .cra_flags = CRYPTO_ALG_ASYNC,
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001164 .cra_blocksize = SHA256_BLOCK_SIZE,
1165 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1166 .cra_alignmask = 0,
1167 .cra_module = THIS_MODULE,
1168 .cra_init = atmel_sha_cra_init,
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001169 }
1170 }
1171},
1172};
1173
Nicolas Royerd4905b32013-02-20 17:10:26 +01001174static struct ahash_alg sha_224_alg = {
1175 .init = atmel_sha_init,
1176 .update = atmel_sha_update,
1177 .final = atmel_sha_final,
1178 .finup = atmel_sha_finup,
1179 .digest = atmel_sha_digest,
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001180 .export = atmel_sha_export,
1181 .import = atmel_sha_import,
Nicolas Royerd4905b32013-02-20 17:10:26 +01001182 .halg = {
1183 .digestsize = SHA224_DIGEST_SIZE,
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +01001184 .statesize = sizeof(struct atmel_sha_reqctx),
Nicolas Royerd4905b32013-02-20 17:10:26 +01001185 .base = {
1186 .cra_name = "sha224",
1187 .cra_driver_name = "atmel-sha224",
1188 .cra_priority = 100,
Svenning Sørensenbe95f0f2014-12-05 01:18:57 +01001189 .cra_flags = CRYPTO_ALG_ASYNC,
Nicolas Royerd4905b32013-02-20 17:10:26 +01001190 .cra_blocksize = SHA224_BLOCK_SIZE,
1191 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1192 .cra_alignmask = 0,
1193 .cra_module = THIS_MODULE,
1194 .cra_init = atmel_sha_cra_init,
Nicolas Royerd4905b32013-02-20 17:10:26 +01001195 }
1196 }
1197};
1198
1199static struct ahash_alg sha_384_512_algs[] = {
1200{
1201 .init = atmel_sha_init,
1202 .update = atmel_sha_update,
1203 .final = atmel_sha_final,
1204 .finup = atmel_sha_finup,
1205 .digest = atmel_sha_digest,
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001206 .export = atmel_sha_export,
1207 .import = atmel_sha_import,
Nicolas Royerd4905b32013-02-20 17:10:26 +01001208 .halg = {
1209 .digestsize = SHA384_DIGEST_SIZE,
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +01001210 .statesize = sizeof(struct atmel_sha_reqctx),
Nicolas Royerd4905b32013-02-20 17:10:26 +01001211 .base = {
1212 .cra_name = "sha384",
1213 .cra_driver_name = "atmel-sha384",
1214 .cra_priority = 100,
Svenning Sørensenbe95f0f2014-12-05 01:18:57 +01001215 .cra_flags = CRYPTO_ALG_ASYNC,
Nicolas Royerd4905b32013-02-20 17:10:26 +01001216 .cra_blocksize = SHA384_BLOCK_SIZE,
1217 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1218 .cra_alignmask = 0x3,
1219 .cra_module = THIS_MODULE,
1220 .cra_init = atmel_sha_cra_init,
Nicolas Royerd4905b32013-02-20 17:10:26 +01001221 }
1222 }
1223},
1224{
1225 .init = atmel_sha_init,
1226 .update = atmel_sha_update,
1227 .final = atmel_sha_final,
1228 .finup = atmel_sha_finup,
1229 .digest = atmel_sha_digest,
Cyrille Pitchencc831d32016-01-29 17:04:02 +01001230 .export = atmel_sha_export,
1231 .import = atmel_sha_import,
Nicolas Royerd4905b32013-02-20 17:10:26 +01001232 .halg = {
1233 .digestsize = SHA512_DIGEST_SIZE,
Cyrille Pitchen9c4274d2016-02-08 16:26:48 +01001234 .statesize = sizeof(struct atmel_sha_reqctx),
Nicolas Royerd4905b32013-02-20 17:10:26 +01001235 .base = {
1236 .cra_name = "sha512",
1237 .cra_driver_name = "atmel-sha512",
1238 .cra_priority = 100,
Svenning Sørensenbe95f0f2014-12-05 01:18:57 +01001239 .cra_flags = CRYPTO_ALG_ASYNC,
Nicolas Royerd4905b32013-02-20 17:10:26 +01001240 .cra_blocksize = SHA512_BLOCK_SIZE,
1241 .cra_ctxsize = sizeof(struct atmel_sha_ctx),
1242 .cra_alignmask = 0x3,
1243 .cra_module = THIS_MODULE,
1244 .cra_init = atmel_sha_cra_init,
Nicolas Royerd4905b32013-02-20 17:10:26 +01001245 }
1246 }
1247},
1248};
1249
Cyrille Pitchenf56809c2016-01-15 15:49:32 +01001250static void atmel_sha_queue_task(unsigned long data)
1251{
1252 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
1253
1254 atmel_sha_handle_queue(dd, NULL);
1255}
1256
Cyrille Pitchenb5ce82a2017-01-26 17:07:48 +01001257static int atmel_sha_done(struct atmel_sha_dev *dd)
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001258{
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001259 int err = 0;
1260
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001261 if (SHA_FLAGS_CPU & dd->flags) {
1262 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1263 dd->flags &= ~SHA_FLAGS_OUTPUT_READY;
1264 goto finish;
1265 }
1266 } else if (SHA_FLAGS_DMA_READY & dd->flags) {
1267 if (SHA_FLAGS_DMA_ACTIVE & dd->flags) {
1268 dd->flags &= ~SHA_FLAGS_DMA_ACTIVE;
1269 atmel_sha_update_dma_stop(dd);
1270 if (dd->err) {
1271 err = dd->err;
1272 goto finish;
1273 }
1274 }
1275 if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
1276 /* hash or semi-hash ready */
1277 dd->flags &= ~(SHA_FLAGS_DMA_READY |
1278 SHA_FLAGS_OUTPUT_READY);
1279 err = atmel_sha_update_dma_start(dd);
1280 if (err != -EINPROGRESS)
1281 goto finish;
1282 }
1283 }
Cyrille Pitchenb5ce82a2017-01-26 17:07:48 +01001284 return err;
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001285
1286finish:
1287 /* finish curent request */
1288 atmel_sha_finish_req(dd->req, err);
Cyrille Pitchenb5ce82a2017-01-26 17:07:48 +01001289
1290 return err;
1291}
1292
1293static void atmel_sha_done_task(unsigned long data)
1294{
1295 struct atmel_sha_dev *dd = (struct atmel_sha_dev *)data;
1296
1297 dd->is_async = true;
1298 (void)dd->resume(dd);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001299}
1300
1301static irqreturn_t atmel_sha_irq(int irq, void *dev_id)
1302{
1303 struct atmel_sha_dev *sha_dd = dev_id;
1304 u32 reg;
1305
1306 reg = atmel_sha_read(sha_dd, SHA_ISR);
1307 if (reg & atmel_sha_read(sha_dd, SHA_IMR)) {
1308 atmel_sha_write(sha_dd, SHA_IDR, reg);
1309 if (SHA_FLAGS_BUSY & sha_dd->flags) {
1310 sha_dd->flags |= SHA_FLAGS_OUTPUT_READY;
1311 if (!(SHA_FLAGS_CPU & sha_dd->flags))
1312 sha_dd->flags |= SHA_FLAGS_DMA_READY;
1313 tasklet_schedule(&sha_dd->done_task);
1314 } else {
1315 dev_warn(sha_dd->dev, "SHA interrupt when no active requests.\n");
1316 }
1317 return IRQ_HANDLED;
1318 }
1319
1320 return IRQ_NONE;
1321}
1322
Cyrille Pitcheneec12f62017-01-26 17:07:52 +01001323
1324/* CPU transfer functions */
1325
1326static int atmel_sha_cpu_transfer(struct atmel_sha_dev *dd)
1327{
1328 struct ahash_request *req = dd->req;
1329 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1330 const u32 *words = (const u32 *)ctx->buffer;
1331 size_t i, num_words;
1332 u32 isr, din, din_inc;
1333
1334 din_inc = (ctx->flags & SHA_FLAGS_IDATAR0) ? 0 : 1;
1335 for (;;) {
1336 /* Write data into the Input Data Registers. */
1337 num_words = DIV_ROUND_UP(ctx->bufcnt, sizeof(u32));
1338 for (i = 0, din = 0; i < num_words; ++i, din += din_inc)
1339 atmel_sha_write(dd, SHA_REG_DIN(din), words[i]);
1340
1341 ctx->offset += ctx->bufcnt;
1342 ctx->total -= ctx->bufcnt;
1343
1344 if (!ctx->total)
1345 break;
1346
1347 /*
1348 * Prepare next block:
1349 * Fill ctx->buffer now with the next data to be written into
1350 * IDATARx: it gives time for the SHA hardware to process
1351 * the current data so the SHA_INT_DATARDY flag might be set
1352 * in SHA_ISR when polling this register at the beginning of
1353 * the next loop.
1354 */
1355 ctx->bufcnt = min_t(size_t, ctx->block_size, ctx->total);
1356 scatterwalk_map_and_copy(ctx->buffer, ctx->sg,
1357 ctx->offset, ctx->bufcnt, 0);
1358
1359 /* Wait for hardware to be ready again. */
1360 isr = atmel_sha_read(dd, SHA_ISR);
1361 if (!(isr & SHA_INT_DATARDY)) {
1362 /* Not ready yet. */
1363 dd->resume = atmel_sha_cpu_transfer;
1364 atmel_sha_write(dd, SHA_IER, SHA_INT_DATARDY);
1365 return -EINPROGRESS;
1366 }
1367 }
1368
1369 if (unlikely(!(ctx->flags & SHA_FLAGS_WAIT_DATARDY)))
1370 return dd->cpu_transfer_complete(dd);
1371
1372 return atmel_sha_wait_for_data_ready(dd, dd->cpu_transfer_complete);
1373}
1374
1375static int atmel_sha_cpu_start(struct atmel_sha_dev *dd,
1376 struct scatterlist *sg,
1377 unsigned int len,
1378 bool idatar0_only,
1379 bool wait_data_ready,
1380 atmel_sha_fn_t resume)
1381{
1382 struct ahash_request *req = dd->req;
1383 struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
1384
1385 if (!len)
1386 return resume(dd);
1387
1388 ctx->flags &= ~(SHA_FLAGS_IDATAR0 | SHA_FLAGS_WAIT_DATARDY);
1389
1390 if (idatar0_only)
1391 ctx->flags |= SHA_FLAGS_IDATAR0;
1392
1393 if (wait_data_ready)
1394 ctx->flags |= SHA_FLAGS_WAIT_DATARDY;
1395
1396 ctx->sg = sg;
1397 ctx->total = len;
1398 ctx->offset = 0;
1399
1400 /* Prepare the first block to be written. */
1401 ctx->bufcnt = min_t(size_t, ctx->block_size, ctx->total);
1402 scatterwalk_map_and_copy(ctx->buffer, ctx->sg,
1403 ctx->offset, ctx->bufcnt, 0);
1404
1405 dd->cpu_transfer_complete = resume;
1406 return atmel_sha_cpu_transfer(dd);
1407}
1408
1409
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001410static void atmel_sha_unregister_algs(struct atmel_sha_dev *dd)
1411{
1412 int i;
1413
Nicolas Royerd4905b32013-02-20 17:10:26 +01001414 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++)
1415 crypto_unregister_ahash(&sha_1_256_algs[i]);
1416
1417 if (dd->caps.has_sha224)
1418 crypto_unregister_ahash(&sha_224_alg);
1419
1420 if (dd->caps.has_sha_384_512) {
1421 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++)
1422 crypto_unregister_ahash(&sha_384_512_algs[i]);
1423 }
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001424}
1425
1426static int atmel_sha_register_algs(struct atmel_sha_dev *dd)
1427{
1428 int err, i, j;
1429
Nicolas Royerd4905b32013-02-20 17:10:26 +01001430 for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) {
1431 err = crypto_register_ahash(&sha_1_256_algs[i]);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001432 if (err)
Nicolas Royerd4905b32013-02-20 17:10:26 +01001433 goto err_sha_1_256_algs;
1434 }
1435
1436 if (dd->caps.has_sha224) {
1437 err = crypto_register_ahash(&sha_224_alg);
1438 if (err)
1439 goto err_sha_224_algs;
1440 }
1441
1442 if (dd->caps.has_sha_384_512) {
1443 for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) {
1444 err = crypto_register_ahash(&sha_384_512_algs[i]);
1445 if (err)
1446 goto err_sha_384_512_algs;
1447 }
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001448 }
1449
1450 return 0;
1451
Nicolas Royerd4905b32013-02-20 17:10:26 +01001452err_sha_384_512_algs:
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001453 for (j = 0; j < i; j++)
Nicolas Royerd4905b32013-02-20 17:10:26 +01001454 crypto_unregister_ahash(&sha_384_512_algs[j]);
1455 crypto_unregister_ahash(&sha_224_alg);
1456err_sha_224_algs:
1457 i = ARRAY_SIZE(sha_1_256_algs);
1458err_sha_1_256_algs:
1459 for (j = 0; j < i; j++)
1460 crypto_unregister_ahash(&sha_1_256_algs[j]);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001461
1462 return err;
1463}
1464
Nicolas Royerd4905b32013-02-20 17:10:26 +01001465static bool atmel_sha_filter(struct dma_chan *chan, void *slave)
1466{
1467 struct at_dma_slave *sl = slave;
1468
1469 if (sl && sl->dma_dev == chan->device->dev) {
1470 chan->private = sl;
1471 return true;
1472 } else {
1473 return false;
1474 }
1475}
1476
1477static int atmel_sha_dma_init(struct atmel_sha_dev *dd,
1478 struct crypto_platform_data *pdata)
1479{
1480 int err = -ENOMEM;
1481 dma_cap_mask_t mask_in;
1482
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +02001483 /* Try to grab DMA channel */
1484 dma_cap_zero(mask_in);
1485 dma_cap_set(DMA_SLAVE, mask_in);
Nicolas Royerd4905b32013-02-20 17:10:26 +01001486
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +02001487 dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in,
1488 atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx");
1489 if (!dd->dma_lch_in.chan) {
1490 dev_warn(dd->dev, "no DMA channel available\n");
1491 return err;
Nicolas Royerd4905b32013-02-20 17:10:26 +01001492 }
1493
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +02001494 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
1495 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
1496 SHA_REG_DIN(0);
1497 dd->dma_lch_in.dma_conf.src_maxburst = 1;
1498 dd->dma_lch_in.dma_conf.src_addr_width =
1499 DMA_SLAVE_BUSWIDTH_4_BYTES;
1500 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
1501 dd->dma_lch_in.dma_conf.dst_addr_width =
1502 DMA_SLAVE_BUSWIDTH_4_BYTES;
1503 dd->dma_lch_in.dma_conf.device_fc = false;
1504
1505 return 0;
Nicolas Royerd4905b32013-02-20 17:10:26 +01001506}
1507
1508static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd)
1509{
1510 dma_release_channel(dd->dma_lch_in.chan);
1511}
1512
1513static void atmel_sha_get_cap(struct atmel_sha_dev *dd)
1514{
1515
1516 dd->caps.has_dma = 0;
1517 dd->caps.has_dualbuff = 0;
1518 dd->caps.has_sha224 = 0;
1519 dd->caps.has_sha_384_512 = 0;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +01001520 dd->caps.has_uihv = 0;
Nicolas Royerd4905b32013-02-20 17:10:26 +01001521
1522 /* keep only major version number */
1523 switch (dd->hw_version & 0xff0) {
Cyrille Pitchen507c5cc2016-01-15 15:49:33 +01001524 case 0x510:
1525 dd->caps.has_dma = 1;
1526 dd->caps.has_dualbuff = 1;
1527 dd->caps.has_sha224 = 1;
1528 dd->caps.has_sha_384_512 = 1;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +01001529 dd->caps.has_uihv = 1;
Cyrille Pitchen507c5cc2016-01-15 15:49:33 +01001530 break;
Leilei Zhao141824d2015-04-07 17:45:03 +08001531 case 0x420:
1532 dd->caps.has_dma = 1;
1533 dd->caps.has_dualbuff = 1;
1534 dd->caps.has_sha224 = 1;
1535 dd->caps.has_sha_384_512 = 1;
Cyrille Pitchen7cee3502016-01-15 15:49:34 +01001536 dd->caps.has_uihv = 1;
Leilei Zhao141824d2015-04-07 17:45:03 +08001537 break;
Nicolas Royerd4905b32013-02-20 17:10:26 +01001538 case 0x410:
1539 dd->caps.has_dma = 1;
1540 dd->caps.has_dualbuff = 1;
1541 dd->caps.has_sha224 = 1;
1542 dd->caps.has_sha_384_512 = 1;
1543 break;
1544 case 0x400:
1545 dd->caps.has_dma = 1;
1546 dd->caps.has_dualbuff = 1;
1547 dd->caps.has_sha224 = 1;
1548 break;
1549 case 0x320:
1550 break;
1551 default:
1552 dev_warn(dd->dev,
1553 "Unmanaged sha version, set minimum capabilities\n");
1554 break;
1555 }
1556}
1557
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +02001558#if defined(CONFIG_OF)
1559static const struct of_device_id atmel_sha_dt_ids[] = {
1560 { .compatible = "atmel,at91sam9g46-sha" },
1561 { /* sentinel */ }
1562};
1563
1564MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids);
1565
1566static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev)
1567{
1568 struct device_node *np = pdev->dev.of_node;
1569 struct crypto_platform_data *pdata;
1570
1571 if (!np) {
1572 dev_err(&pdev->dev, "device node not found\n");
1573 return ERR_PTR(-EINVAL);
1574 }
1575
1576 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1577 if (!pdata) {
1578 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1579 return ERR_PTR(-ENOMEM);
1580 }
1581
1582 pdata->dma_slave = devm_kzalloc(&pdev->dev,
1583 sizeof(*(pdata->dma_slave)),
1584 GFP_KERNEL);
1585 if (!pdata->dma_slave) {
1586 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +02001587 return ERR_PTR(-ENOMEM);
1588 }
1589
1590 return pdata;
1591}
1592#else /* CONFIG_OF */
1593static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev)
1594{
1595 return ERR_PTR(-EINVAL);
1596}
1597#endif
1598
Greg Kroah-Hartman49cfe4d2012-12-21 13:14:09 -08001599static int atmel_sha_probe(struct platform_device *pdev)
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001600{
1601 struct atmel_sha_dev *sha_dd;
Nicolas Royerd4905b32013-02-20 17:10:26 +01001602 struct crypto_platform_data *pdata;
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001603 struct device *dev = &pdev->dev;
1604 struct resource *sha_res;
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001605 int err;
1606
LABBE Corentinb0e8b342015-10-12 19:47:03 +02001607 sha_dd = devm_kzalloc(&pdev->dev, sizeof(*sha_dd), GFP_KERNEL);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001608 if (sha_dd == NULL) {
1609 dev_err(dev, "unable to alloc data struct.\n");
1610 err = -ENOMEM;
1611 goto sha_dd_err;
1612 }
1613
1614 sha_dd->dev = dev;
1615
1616 platform_set_drvdata(pdev, sha_dd);
1617
1618 INIT_LIST_HEAD(&sha_dd->list);
Leilei Zhao62728e82015-04-07 17:45:06 +08001619 spin_lock_init(&sha_dd->lock);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001620
1621 tasklet_init(&sha_dd->done_task, atmel_sha_done_task,
1622 (unsigned long)sha_dd);
Cyrille Pitchenf56809c2016-01-15 15:49:32 +01001623 tasklet_init(&sha_dd->queue_task, atmel_sha_queue_task,
1624 (unsigned long)sha_dd);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001625
1626 crypto_init_queue(&sha_dd->queue, ATMEL_SHA_QUEUE_LENGTH);
1627
1628 sha_dd->irq = -1;
1629
1630 /* Get the base address */
1631 sha_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1632 if (!sha_res) {
1633 dev_err(dev, "no MEM resource info\n");
1634 err = -ENODEV;
1635 goto res_err;
1636 }
1637 sha_dd->phys_base = sha_res->start;
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001638
1639 /* Get the IRQ */
1640 sha_dd->irq = platform_get_irq(pdev, 0);
1641 if (sha_dd->irq < 0) {
1642 dev_err(dev, "no IRQ resource info\n");
1643 err = sha_dd->irq;
1644 goto res_err;
1645 }
1646
LABBE Corentinb0e8b342015-10-12 19:47:03 +02001647 err = devm_request_irq(&pdev->dev, sha_dd->irq, atmel_sha_irq,
1648 IRQF_SHARED, "atmel-sha", sha_dd);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001649 if (err) {
1650 dev_err(dev, "unable to request sha irq.\n");
1651 goto res_err;
1652 }
1653
1654 /* Initializing the clock */
LABBE Corentinb0e8b342015-10-12 19:47:03 +02001655 sha_dd->iclk = devm_clk_get(&pdev->dev, "sha_clk");
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001656 if (IS_ERR(sha_dd->iclk)) {
Colin Ian Kingbe208352015-02-28 20:40:10 +00001657 dev_err(dev, "clock initialization failed.\n");
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001658 err = PTR_ERR(sha_dd->iclk);
LABBE Corentinb0e8b342015-10-12 19:47:03 +02001659 goto res_err;
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001660 }
1661
LABBE Corentinb0e8b342015-10-12 19:47:03 +02001662 sha_dd->io_base = devm_ioremap_resource(&pdev->dev, sha_res);
Vladimir Zapolskiy9b52d552016-03-06 03:21:52 +02001663 if (IS_ERR(sha_dd->io_base)) {
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001664 dev_err(dev, "can't ioremap\n");
Vladimir Zapolskiy9b52d552016-03-06 03:21:52 +02001665 err = PTR_ERR(sha_dd->io_base);
LABBE Corentinb0e8b342015-10-12 19:47:03 +02001666 goto res_err;
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001667 }
1668
Cyrille Pitchenc0330422016-02-05 13:45:13 +01001669 err = clk_prepare(sha_dd->iclk);
1670 if (err)
1671 goto res_err;
1672
Nicolas Royerd4905b32013-02-20 17:10:26 +01001673 atmel_sha_hw_version_init(sha_dd);
1674
1675 atmel_sha_get_cap(sha_dd);
1676
1677 if (sha_dd->caps.has_dma) {
1678 pdata = pdev->dev.platform_data;
1679 if (!pdata) {
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +02001680 pdata = atmel_sha_of_init(pdev);
1681 if (IS_ERR(pdata)) {
1682 dev_err(&pdev->dev, "platform data not available\n");
1683 err = PTR_ERR(pdata);
Cyrille Pitchenc0330422016-02-05 13:45:13 +01001684 goto iclk_unprepare;
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +02001685 }
1686 }
1687 if (!pdata->dma_slave) {
Nicolas Royerd4905b32013-02-20 17:10:26 +01001688 err = -ENXIO;
Cyrille Pitchenc0330422016-02-05 13:45:13 +01001689 goto iclk_unprepare;
Nicolas Royerd4905b32013-02-20 17:10:26 +01001690 }
1691 err = atmel_sha_dma_init(sha_dd, pdata);
1692 if (err)
1693 goto err_sha_dma;
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +02001694
1695 dev_info(dev, "using %s for DMA transfers\n",
1696 dma_chan_name(sha_dd->dma_lch_in.chan));
Nicolas Royerd4905b32013-02-20 17:10:26 +01001697 }
1698
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001699 spin_lock(&atmel_sha.lock);
1700 list_add_tail(&sha_dd->list, &atmel_sha.dev_list);
1701 spin_unlock(&atmel_sha.lock);
1702
1703 err = atmel_sha_register_algs(sha_dd);
1704 if (err)
1705 goto err_algs;
1706
Nicolas Ferre1ca5b7d2013-10-15 16:37:44 +02001707 dev_info(dev, "Atmel SHA1/SHA256%s%s\n",
1708 sha_dd->caps.has_sha224 ? "/SHA224" : "",
1709 sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : "");
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001710
1711 return 0;
1712
1713err_algs:
1714 spin_lock(&atmel_sha.lock);
1715 list_del(&sha_dd->list);
1716 spin_unlock(&atmel_sha.lock);
Nicolas Royerd4905b32013-02-20 17:10:26 +01001717 if (sha_dd->caps.has_dma)
1718 atmel_sha_dma_cleanup(sha_dd);
1719err_sha_dma:
Cyrille Pitchenc0330422016-02-05 13:45:13 +01001720iclk_unprepare:
1721 clk_unprepare(sha_dd->iclk);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001722res_err:
Cyrille Pitchenf56809c2016-01-15 15:49:32 +01001723 tasklet_kill(&sha_dd->queue_task);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001724 tasklet_kill(&sha_dd->done_task);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001725sha_dd_err:
1726 dev_err(dev, "initialization failed.\n");
1727
1728 return err;
1729}
1730
Greg Kroah-Hartman49cfe4d2012-12-21 13:14:09 -08001731static int atmel_sha_remove(struct platform_device *pdev)
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001732{
1733 static struct atmel_sha_dev *sha_dd;
1734
1735 sha_dd = platform_get_drvdata(pdev);
1736 if (!sha_dd)
1737 return -ENODEV;
1738 spin_lock(&atmel_sha.lock);
1739 list_del(&sha_dd->list);
1740 spin_unlock(&atmel_sha.lock);
1741
1742 atmel_sha_unregister_algs(sha_dd);
1743
Cyrille Pitchenf56809c2016-01-15 15:49:32 +01001744 tasklet_kill(&sha_dd->queue_task);
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001745 tasklet_kill(&sha_dd->done_task);
1746
Nicolas Royerd4905b32013-02-20 17:10:26 +01001747 if (sha_dd->caps.has_dma)
1748 atmel_sha_dma_cleanup(sha_dd);
1749
Cyrille Pitchenc0330422016-02-05 13:45:13 +01001750 clk_unprepare(sha_dd->iclk);
1751
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001752 return 0;
1753}
1754
1755static struct platform_driver atmel_sha_driver = {
1756 .probe = atmel_sha_probe,
Greg Kroah-Hartman49cfe4d2012-12-21 13:14:09 -08001757 .remove = atmel_sha_remove,
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001758 .driver = {
1759 .name = "atmel_sha",
Nicolas Ferreabfe7ae2013-10-15 15:36:34 +02001760 .of_match_table = of_match_ptr(atmel_sha_dt_ids),
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001761 },
1762};
1763
1764module_platform_driver(atmel_sha_driver);
1765
Nicolas Royerd4905b32013-02-20 17:10:26 +01001766MODULE_DESCRIPTION("Atmel SHA (1/256/224/384/512) hw acceleration support.");
Nicolas Royerebc82ef2012-07-01 19:19:46 +02001767MODULE_LICENSE("GPL v2");
1768MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");