blob: b44f1eddb570b9f4a8e0ba6205b1bfb59e36ba20 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Reding1503ca42014-11-24 17:41:23 +010036static void tegra_atomic_schedule(struct tegra_drm *tegra,
37 struct drm_atomic_state *state)
38{
39 tegra->commit.state = state;
40 schedule_work(&tegra->commit.work);
41}
42
43static void tegra_atomic_complete(struct tegra_drm *tegra,
44 struct drm_atomic_state *state)
45{
46 struct drm_device *drm = tegra->drm;
47
48 /*
49 * Everything below can be run asynchronously without the need to grab
50 * any modeset locks at all under one condition: It must be guaranteed
51 * that the asynchronous work has either been cancelled (if the driver
52 * supports it, which at least requires that the framebuffers get
53 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
54 * before the new state gets committed on the software side with
55 * drm_atomic_helper_swap_state().
56 *
57 * This scheme allows new atomic state updates to be prepared and
58 * checked in parallel to the asynchronous completion of the previous
59 * update. Which is important since compositors need to figure out the
60 * composition of the next frame right after having submitted the
61 * current layout.
62 */
63
Daniel Vetter1af434a2015-02-22 12:24:19 +010064 drm_atomic_helper_commit_modeset_disables(drm, state);
Daniel Vetter1af434a2015-02-22 12:24:19 +010065 drm_atomic_helper_commit_modeset_enables(drm, state);
Liu Ying2b58e982016-08-29 17:12:03 +080066 drm_atomic_helper_commit_planes(drm, state,
67 DRM_PLANE_COMMIT_ACTIVE_ONLY);
Thierry Reding1503ca42014-11-24 17:41:23 +010068
69 drm_atomic_helper_wait_for_vblanks(drm, state);
70
71 drm_atomic_helper_cleanup_planes(drm, state);
Chris Wilson08536952016-10-14 13:18:18 +010072 drm_atomic_state_put(state);
Thierry Reding1503ca42014-11-24 17:41:23 +010073}
74
75static void tegra_atomic_work(struct work_struct *work)
76{
77 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
78 commit.work);
79
80 tegra_atomic_complete(tegra, tegra->commit.state);
81}
82
83static int tegra_atomic_commit(struct drm_device *drm,
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020084 struct drm_atomic_state *state, bool nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +010085{
86 struct tegra_drm *tegra = drm->dev_private;
87 int err;
88
89 err = drm_atomic_helper_prepare_planes(drm, state);
90 if (err)
91 return err;
92
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020093 /* serialize outstanding nonblocking commits */
Thierry Reding1503ca42014-11-24 17:41:23 +010094 mutex_lock(&tegra->commit.lock);
95 flush_work(&tegra->commit.work);
96
97 /*
98 * This is the point of no return - everything below never fails except
99 * when the hw goes bonghits. Which means we can commit the new state on
100 * the software side now.
101 */
102
Daniel Vetter5e84c262016-06-10 00:06:32 +0200103 drm_atomic_helper_swap_state(state, true);
Thierry Reding1503ca42014-11-24 17:41:23 +0100104
Chris Wilson08536952016-10-14 13:18:18 +0100105 drm_atomic_state_get(state);
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +0200106 if (nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +0100107 tegra_atomic_schedule(tegra, state);
108 else
109 tegra_atomic_complete(tegra, state);
110
111 mutex_unlock(&tegra->commit.lock);
112 return 0;
113}
114
Thierry Redingf9914212014-11-26 13:03:57 +0100115static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
116 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +0530117#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +0100118 .output_poll_changed = tegra_fb_output_poll_changed,
119#endif
Thierry Reding07866962014-11-24 17:08:06 +0100120 .atomic_check = drm_atomic_helper_check,
Thierry Reding1503ca42014-11-24 17:41:23 +0100121 .atomic_commit = tegra_atomic_commit,
Thierry Redingf9914212014-11-26 13:03:57 +0100122};
123
Thierry Reding776dc382013-10-14 14:43:22 +0200124static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000125{
Thierry Reding776dc382013-10-14 14:43:22 +0200126 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200127 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000128 int err;
129
Thierry Reding776dc382013-10-14 14:43:22 +0200130 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200131 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200132 return -ENOMEM;
133
Thierry Redingdf06b752014-06-26 21:41:53 +0200134 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200135 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100136 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200137 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100138
Thierry Redingdf06b752014-06-26 21:41:53 +0200139 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300140 if (!tegra->domain) {
141 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200142 goto free;
143 }
144
Thierry Reding4553f732015-01-19 16:15:04 +0100145 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200146 gem_start = geometry->aperture_start;
147 gem_end = geometry->aperture_end - CARVEOUT_SZ;
148 carveout_start = gem_end + 1;
149 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100150
Mikko Perttunenad926012016-12-14 13:16:11 +0200151 order = __ffs(tegra->domain->pgsize_bitmap);
152 init_iova_domain(&tegra->carveout.domain, 1UL << order,
153 carveout_start >> order,
154 carveout_end >> order);
155
156 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
157 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
158
159 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100160 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200161
162 DRM_DEBUG("IOMMU apertures:\n");
163 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
164 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
165 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200166 }
167
Thierry Reding386a2a72013-09-24 13:22:17 +0200168 mutex_init(&tegra->clients_lock);
169 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100170
171 mutex_init(&tegra->commit.lock);
172 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
173
Thierry Reding386a2a72013-09-24 13:22:17 +0200174 drm->dev_private = tegra;
175 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000176
177 drm_mode_config_init(drm);
178
Thierry Redingf9914212014-11-26 13:03:57 +0100179 drm->mode_config.min_width = 0;
180 drm->mode_config.min_height = 0;
181
182 drm->mode_config.max_width = 4096;
183 drm->mode_config.max_height = 4096;
184
Alexandre Courbot5e911442016-11-08 16:50:42 +0900185 drm->mode_config.allow_fb_modifiers = true;
186
Thierry Redingf9914212014-11-26 13:03:57 +0100187 drm->mode_config.funcs = &tegra_drm_mode_funcs;
188
Thierry Redinge2215322014-06-27 17:19:25 +0200189 err = tegra_drm_fb_prepare(drm);
190 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100191 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200192
193 drm_kms_helper_poll_init(drm);
194
Thierry Reding776dc382013-10-14 14:43:22 +0200195 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000196 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100197 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000198
Thierry Reding603f0cc2013-04-22 21:22:14 +0200199 /*
200 * We don't use the drm_irq_install() helpers provided by the DRM
201 * core, so we need to set this manually in order to allow the
202 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
203 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300204 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200205
Thierry Reding42e9ce02015-01-28 14:43:05 +0100206 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100207 drm->max_vblank_count = 0xffffffff;
208
Thierry Reding6e5ff992012-11-28 11:45:47 +0100209 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
210 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100211 goto device;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100212
Thierry Reding31930d42015-07-02 17:04:06 +0200213 drm_mode_config_reset(drm);
214
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000215 err = tegra_drm_fb_init(drm);
216 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100217 goto vblank;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000218
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000219 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100220
221vblank:
222 drm_vblank_cleanup(drm);
223device:
224 host1x_device_exit(device);
225fbdev:
226 drm_kms_helper_poll_fini(drm);
227 tegra_drm_fb_free(drm);
228config:
229 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200230
231 if (tegra->domain) {
232 iommu_domain_free(tegra->domain);
233 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100234 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200235 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200236 }
237free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100238 kfree(tegra);
239 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000240}
241
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200242static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000243{
Thierry Reding776dc382013-10-14 14:43:22 +0200244 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200245 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200246 int err;
247
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000248 drm_kms_helper_poll_fini(drm);
249 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200250 drm_mode_config_cleanup(drm);
Thierry Reding4aa3df72014-11-24 16:27:13 +0100251 drm_vblank_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000252
Thierry Reding776dc382013-10-14 14:43:22 +0200253 err = host1x_device_exit(device);
254 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200255 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200256
Thierry Redingdf06b752014-06-26 21:41:53 +0200257 if (tegra->domain) {
258 iommu_domain_free(tegra->domain);
259 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100260 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200261 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200262 }
263
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100264 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000265}
266
267static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
268{
Thierry Reding08943e62013-09-26 16:08:18 +0200269 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200270
271 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
272 if (!fpriv)
273 return -ENOMEM;
274
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100275 idr_init(&fpriv->contexts);
276 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200277 filp->driver_priv = fpriv;
278
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000279 return 0;
280}
281
Thierry Redingc88c3632013-09-26 16:08:22 +0200282static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200283{
284 context->client->ops->close_channel(context);
285 kfree(context);
286}
287
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000288static void tegra_drm_lastclose(struct drm_device *drm)
289{
Archit Tanejab110ef32015-10-27 13:40:59 +0530290#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200291 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000292
Thierry Reding386a2a72013-09-24 13:22:17 +0200293 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100294#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000295}
296
Thierry Redingc40f0f12013-10-10 11:00:33 +0200297static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100298host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200299{
300 struct drm_gem_object *gem;
301 struct tegra_bo *bo;
302
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100303 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200304 if (!gem)
305 return NULL;
306
Daniel Vettera07cdfe2015-11-23 10:32:48 +0100307 drm_gem_object_unreference_unlocked(gem);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200308
309 bo = to_tegra_bo(gem);
310 return &bo->base;
311}
312
Thierry Reding961e3be2014-06-10 10:25:00 +0200313static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
314 struct drm_tegra_reloc __user *src,
315 struct drm_device *drm,
316 struct drm_file *file)
317{
318 u32 cmdbuf, target;
319 int err;
320
321 err = get_user(cmdbuf, &src->cmdbuf.handle);
322 if (err < 0)
323 return err;
324
325 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
326 if (err < 0)
327 return err;
328
329 err = get_user(target, &src->target.handle);
330 if (err < 0)
331 return err;
332
David Ung31f40f82015-01-20 18:37:35 -0800333 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200334 if (err < 0)
335 return err;
336
337 err = get_user(dest->shift, &src->shift);
338 if (err < 0)
339 return err;
340
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100341 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200342 if (!dest->cmdbuf.bo)
343 return -ENOENT;
344
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100345 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200346 if (!dest->target.bo)
347 return -ENOENT;
348
349 return 0;
350}
351
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300352static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
353 struct drm_tegra_waitchk __user *src,
354 struct drm_file *file)
355{
356 u32 cmdbuf;
357 int err;
358
359 err = get_user(cmdbuf, &src->handle);
360 if (err < 0)
361 return err;
362
363 err = get_user(dest->offset, &src->offset);
364 if (err < 0)
365 return err;
366
367 err = get_user(dest->syncpt_id, &src->syncpt);
368 if (err < 0)
369 return err;
370
371 err = get_user(dest->thresh, &src->thresh);
372 if (err < 0)
373 return err;
374
375 dest->bo = host1x_bo_lookup(file, cmdbuf);
376 if (!dest->bo)
377 return -ENOENT;
378
379 return 0;
380}
381
Thierry Redingc40f0f12013-10-10 11:00:33 +0200382int tegra_drm_submit(struct tegra_drm_context *context,
383 struct drm_tegra_submit *args, struct drm_device *drm,
384 struct drm_file *file)
385{
386 unsigned int num_cmdbufs = args->num_cmdbufs;
387 unsigned int num_relocs = args->num_relocs;
388 unsigned int num_waitchks = args->num_waitchks;
389 struct drm_tegra_cmdbuf __user *cmdbufs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100390 (void __user *)(uintptr_t)args->cmdbufs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200391 struct drm_tegra_reloc __user *relocs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100392 (void __user *)(uintptr_t)args->relocs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200393 struct drm_tegra_waitchk __user *waitchks =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100394 (void __user *)(uintptr_t)args->waitchks;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200395 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300396 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
397 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200398 struct host1x_job *job;
399 int err;
400
401 /* We don't yet support other than one syncpt_incr struct per submit */
402 if (args->num_syncpts != 1)
403 return -EINVAL;
404
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300405 /* We don't yet support waitchks */
406 if (args->num_waitchks != 0)
407 return -EINVAL;
408
Thierry Redingc40f0f12013-10-10 11:00:33 +0200409 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
410 args->num_relocs, args->num_waitchks);
411 if (!job)
412 return -ENOMEM;
413
414 job->num_relocs = args->num_relocs;
415 job->num_waitchk = args->num_waitchks;
416 job->client = (u32)args->context;
417 job->class = context->client->base.class;
418 job->serialize = true;
419
420 while (num_cmdbufs) {
421 struct drm_tegra_cmdbuf cmdbuf;
422 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300423 struct tegra_bo *obj;
424 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200425
Dan Carpenter9a991602013-11-08 13:07:37 +0300426 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
427 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200428 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300429 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200430
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300431 /*
432 * The maximum number of CDMA gather fetches is 16383, a higher
433 * value means the words count is malformed.
434 */
435 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
436 err = -EINVAL;
437 goto fail;
438 }
439
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100440 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200441 if (!bo) {
442 err = -ENOENT;
443 goto fail;
444 }
445
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300446 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
447 obj = host1x_to_tegra_bo(bo);
448
449 /*
450 * Gather buffer base address must be 4-bytes aligned,
451 * unaligned offset is malformed and cause commands stream
452 * corruption on the buffer address relocation.
453 */
454 if (offset & 3 || offset >= obj->gem.size) {
455 err = -EINVAL;
456 goto fail;
457 }
458
Thierry Redingc40f0f12013-10-10 11:00:33 +0200459 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
460 num_cmdbufs--;
461 cmdbufs++;
462 }
463
Thierry Reding961e3be2014-06-10 10:25:00 +0200464 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200465 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300466 struct host1x_reloc *reloc;
467 struct tegra_bo *obj;
468
Thierry Reding961e3be2014-06-10 10:25:00 +0200469 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
470 &relocs[num_relocs], drm,
471 file);
472 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200473 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300474
475 reloc = &job->relocarray[num_relocs];
476 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
477
478 /*
479 * The unaligned cmdbuf offset will cause an unaligned write
480 * during of the relocations patching, corrupting the commands
481 * stream.
482 */
483 if (reloc->cmdbuf.offset & 3 ||
484 reloc->cmdbuf.offset >= obj->gem.size) {
485 err = -EINVAL;
486 goto fail;
487 }
488
489 obj = host1x_to_tegra_bo(reloc->target.bo);
490
491 if (reloc->target.offset >= obj->gem.size) {
492 err = -EINVAL;
493 goto fail;
494 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200495 }
496
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300497 /* copy and resolve waitchks from submit */
498 while (num_waitchks--) {
499 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
500 struct tegra_bo *obj;
501
502 err = host1x_waitchk_copy_from_user(wait,
503 &waitchks[num_waitchks],
504 file);
505 if (err < 0)
506 goto fail;
507
508 obj = host1x_to_tegra_bo(wait->bo);
509
510 /*
511 * The unaligned offset will cause an unaligned write during
512 * of the waitchks patching, corrupting the commands stream.
513 */
514 if (wait->offset & 3 ||
515 wait->offset >= obj->gem.size) {
516 err = -EINVAL;
517 goto fail;
518 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300519 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200520
Dan Carpenter9a991602013-11-08 13:07:37 +0300521 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
522 sizeof(syncpt))) {
523 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200524 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300525 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200526
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300527 /* check whether syncpoint ID is valid */
528 sp = host1x_syncpt_get(host1x, syncpt.id);
529 if (!sp) {
530 err = -ENOENT;
531 goto fail;
532 }
533
Thierry Redingc40f0f12013-10-10 11:00:33 +0200534 job->is_addr_reg = context->client->ops->is_addr_reg;
535 job->syncpt_incrs = syncpt.incrs;
536 job->syncpt_id = syncpt.id;
537 job->timeout = 10000;
538
539 if (args->timeout && args->timeout < 10000)
540 job->timeout = args->timeout;
541
542 err = host1x_job_pin(job, context->client->base.dev);
543 if (err)
544 goto fail;
545
546 err = host1x_job_submit(job);
547 if (err)
548 goto fail_submit;
549
550 args->fence = job->syncpt_end;
551
552 host1x_job_put(job);
553 return 0;
554
555fail_submit:
556 host1x_job_unpin(job);
557fail:
558 host1x_job_put(job);
559 return err;
560}
561
562
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200563#ifdef CONFIG_DRM_TEGRA_STAGING
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100564static struct tegra_drm_context *
565tegra_drm_file_get_context(struct tegra_drm_file *file, u32 id)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200566{
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100567 struct tegra_drm_context *context;
Thierry Redingc88c3632013-09-26 16:08:22 +0200568
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100569 mutex_lock(&file->lock);
570 context = idr_find(&file->contexts, id);
571 mutex_unlock(&file->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200572
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100573 return context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200574}
575
576static int tegra_gem_create(struct drm_device *drm, void *data,
577 struct drm_file *file)
578{
579 struct drm_tegra_gem_create *args = data;
580 struct tegra_bo *bo;
581
Thierry Reding773af772013-10-04 22:34:01 +0200582 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200583 &args->handle);
584 if (IS_ERR(bo))
585 return PTR_ERR(bo);
586
587 return 0;
588}
589
590static int tegra_gem_mmap(struct drm_device *drm, void *data,
591 struct drm_file *file)
592{
593 struct drm_tegra_gem_mmap *args = data;
594 struct drm_gem_object *gem;
595 struct tegra_bo *bo;
596
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100597 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200598 if (!gem)
599 return -EINVAL;
600
601 bo = to_tegra_bo(gem);
602
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200603 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200604
Daniel Vetter11533302015-11-23 10:32:40 +0100605 drm_gem_object_unreference_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200606
607 return 0;
608}
609
610static int tegra_syncpt_read(struct drm_device *drm, void *data,
611 struct drm_file *file)
612{
Thierry Reding776dc382013-10-14 14:43:22 +0200613 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200614 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200615 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200616
Thierry Reding776dc382013-10-14 14:43:22 +0200617 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200618 if (!sp)
619 return -EINVAL;
620
621 args->value = host1x_syncpt_read_min(sp);
622 return 0;
623}
624
625static int tegra_syncpt_incr(struct drm_device *drm, void *data,
626 struct drm_file *file)
627{
Thierry Reding776dc382013-10-14 14:43:22 +0200628 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200629 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200630 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200631
Thierry Reding776dc382013-10-14 14:43:22 +0200632 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200633 if (!sp)
634 return -EINVAL;
635
Arto Merilainenebae30b2013-05-29 13:26:08 +0300636 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200637}
638
639static int tegra_syncpt_wait(struct drm_device *drm, void *data,
640 struct drm_file *file)
641{
Thierry Reding776dc382013-10-14 14:43:22 +0200642 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200643 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200644 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200645
Thierry Reding776dc382013-10-14 14:43:22 +0200646 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200647 if (!sp)
648 return -EINVAL;
649
650 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
651 &args->value);
652}
653
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100654static int tegra_client_open(struct tegra_drm_file *fpriv,
655 struct tegra_drm_client *client,
656 struct tegra_drm_context *context)
657{
658 int err;
659
660 err = client->ops->open_channel(client, context);
661 if (err < 0)
662 return err;
663
664 err = idr_alloc(&fpriv->contexts, context, 0, 0, GFP_KERNEL);
665 if (err < 0) {
666 client->ops->close_channel(context);
667 return err;
668 }
669
670 context->client = client;
671 context->id = err;
672
673 return 0;
674}
675
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200676static int tegra_open_channel(struct drm_device *drm, void *data,
677 struct drm_file *file)
678{
Thierry Reding08943e62013-09-26 16:08:18 +0200679 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200680 struct tegra_drm *tegra = drm->dev_private;
681 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200682 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200683 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200684 int err = -ENODEV;
685
686 context = kzalloc(sizeof(*context), GFP_KERNEL);
687 if (!context)
688 return -ENOMEM;
689
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100690 mutex_lock(&fpriv->lock);
691
Thierry Reding776dc382013-10-14 14:43:22 +0200692 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200693 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100694 err = tegra_client_open(fpriv, client, context);
695 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200696 break;
697
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100698 args->context = context->id;
699 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200700 }
701
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100702 if (err < 0)
703 kfree(context);
704
705 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200706 return err;
707}
708
709static int tegra_close_channel(struct drm_device *drm, void *data,
710 struct drm_file *file)
711{
Thierry Reding08943e62013-09-26 16:08:18 +0200712 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200713 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200714 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100715 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200716
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100717 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200718
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100719 context = tegra_drm_file_get_context(fpriv, args->context);
720 if (!context) {
721 err = -EINVAL;
722 goto unlock;
723 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200724
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100725 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200726 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200727
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100728unlock:
729 mutex_unlock(&fpriv->lock);
730 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200731}
732
733static int tegra_get_syncpt(struct drm_device *drm, void *data,
734 struct drm_file *file)
735{
Thierry Reding08943e62013-09-26 16:08:18 +0200736 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200737 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200738 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200739 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100740 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200741
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100742 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200743
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100744 context = tegra_drm_file_get_context(fpriv, args->context);
745 if (!context) {
746 err = -ENODEV;
747 goto unlock;
748 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200749
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100750 if (args->index >= context->client->base.num_syncpts) {
751 err = -EINVAL;
752 goto unlock;
753 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200754
Thierry Reding53fa7f72013-09-24 15:35:40 +0200755 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200756 args->id = host1x_syncpt_id(syncpt);
757
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100758unlock:
759 mutex_unlock(&fpriv->lock);
760 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200761}
762
763static int tegra_submit(struct drm_device *drm, void *data,
764 struct drm_file *file)
765{
Thierry Reding08943e62013-09-26 16:08:18 +0200766 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200767 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200768 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100769 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200770
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100771 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200772
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100773 context = tegra_drm_file_get_context(fpriv, args->context);
774 if (!context) {
775 err = -ENODEV;
776 goto unlock;
777 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200778
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100779 err = context->client->ops->submit(context, args, drm, file);
780
781unlock:
782 mutex_unlock(&fpriv->lock);
783 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200784}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300785
786static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
787 struct drm_file *file)
788{
789 struct tegra_drm_file *fpriv = file->driver_priv;
790 struct drm_tegra_get_syncpt_base *args = data;
791 struct tegra_drm_context *context;
792 struct host1x_syncpt_base *base;
793 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100794 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300795
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100796 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300797
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100798 context = tegra_drm_file_get_context(fpriv, args->context);
799 if (!context) {
800 err = -ENODEV;
801 goto unlock;
802 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300803
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100804 if (args->syncpt >= context->client->base.num_syncpts) {
805 err = -EINVAL;
806 goto unlock;
807 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300808
809 syncpt = context->client->base.syncpts[args->syncpt];
810
811 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100812 if (!base) {
813 err = -ENXIO;
814 goto unlock;
815 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300816
817 args->id = host1x_syncpt_base_id(base);
818
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100819unlock:
820 mutex_unlock(&fpriv->lock);
821 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300822}
Thierry Reding7678d712014-06-03 14:56:57 +0200823
824static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
825 struct drm_file *file)
826{
827 struct drm_tegra_gem_set_tiling *args = data;
828 enum tegra_bo_tiling_mode mode;
829 struct drm_gem_object *gem;
830 unsigned long value = 0;
831 struct tegra_bo *bo;
832
833 switch (args->mode) {
834 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
835 mode = TEGRA_BO_TILING_MODE_PITCH;
836
837 if (args->value != 0)
838 return -EINVAL;
839
840 break;
841
842 case DRM_TEGRA_GEM_TILING_MODE_TILED:
843 mode = TEGRA_BO_TILING_MODE_TILED;
844
845 if (args->value != 0)
846 return -EINVAL;
847
848 break;
849
850 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
851 mode = TEGRA_BO_TILING_MODE_BLOCK;
852
853 if (args->value > 5)
854 return -EINVAL;
855
856 value = args->value;
857 break;
858
859 default:
860 return -EINVAL;
861 }
862
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100863 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200864 if (!gem)
865 return -ENOENT;
866
867 bo = to_tegra_bo(gem);
868
869 bo->tiling.mode = mode;
870 bo->tiling.value = value;
871
Daniel Vetter11533302015-11-23 10:32:40 +0100872 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200873
874 return 0;
875}
876
877static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
878 struct drm_file *file)
879{
880 struct drm_tegra_gem_get_tiling *args = data;
881 struct drm_gem_object *gem;
882 struct tegra_bo *bo;
883 int err = 0;
884
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100885 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200886 if (!gem)
887 return -ENOENT;
888
889 bo = to_tegra_bo(gem);
890
891 switch (bo->tiling.mode) {
892 case TEGRA_BO_TILING_MODE_PITCH:
893 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
894 args->value = 0;
895 break;
896
897 case TEGRA_BO_TILING_MODE_TILED:
898 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
899 args->value = 0;
900 break;
901
902 case TEGRA_BO_TILING_MODE_BLOCK:
903 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
904 args->value = bo->tiling.value;
905 break;
906
907 default:
908 err = -EINVAL;
909 break;
910 }
911
Daniel Vetter11533302015-11-23 10:32:40 +0100912 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200913
914 return err;
915}
Thierry Reding7b129082014-06-10 12:04:03 +0200916
917static int tegra_gem_set_flags(struct drm_device *drm, void *data,
918 struct drm_file *file)
919{
920 struct drm_tegra_gem_set_flags *args = data;
921 struct drm_gem_object *gem;
922 struct tegra_bo *bo;
923
924 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
925 return -EINVAL;
926
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100927 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200928 if (!gem)
929 return -ENOENT;
930
931 bo = to_tegra_bo(gem);
932 bo->flags = 0;
933
934 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
935 bo->flags |= TEGRA_BO_BOTTOM_UP;
936
Daniel Vetter11533302015-11-23 10:32:40 +0100937 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200938
939 return 0;
940}
941
942static int tegra_gem_get_flags(struct drm_device *drm, void *data,
943 struct drm_file *file)
944{
945 struct drm_tegra_gem_get_flags *args = data;
946 struct drm_gem_object *gem;
947 struct tegra_bo *bo;
948
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100949 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200950 if (!gem)
951 return -ENOENT;
952
953 bo = to_tegra_bo(gem);
954 args->flags = 0;
955
956 if (bo->flags & TEGRA_BO_BOTTOM_UP)
957 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
958
Daniel Vetter11533302015-11-23 10:32:40 +0100959 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200960
961 return 0;
962}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200963#endif
964
Rob Clarkbaa70942013-08-02 13:27:49 -0400965static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200966#ifdef CONFIG_DRM_TEGRA_STAGING
Daniel Vetterf8c47142015-09-08 13:56:30 +0200967 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
968 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
969 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
970 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
971 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
972 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
973 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
974 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
975 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
976 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
977 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
978 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
979 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
980 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200981#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000982};
983
984static const struct file_operations tegra_drm_fops = {
985 .owner = THIS_MODULE,
986 .open = drm_open,
987 .release = drm_release,
988 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200989 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000990 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000991 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000992 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000993 .llseek = noop_llseek,
994};
995
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100996static int tegra_drm_context_cleanup(int id, void *p, void *data)
997{
998 struct tegra_drm_context *context = p;
999
1000 tegra_drm_context_free(context);
1001
1002 return 0;
1003}
1004
Thierry Reding3c03c462012-11-28 12:00:18 +01001005static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file)
1006{
Thierry Reding08943e62013-09-26 16:08:18 +02001007 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +01001008
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001009 mutex_lock(&fpriv->lock);
1010 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
1011 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001012
Thierry Redingbdd2f9c2017-03-09 20:04:55 +01001013 idr_destroy(&fpriv->contexts);
1014 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001015 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001016}
1017
Thierry Redinge450fcc2013-02-13 16:13:16 +01001018#ifdef CONFIG_DEBUG_FS
1019static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1020{
1021 struct drm_info_node *node = (struct drm_info_node *)s->private;
1022 struct drm_device *drm = node->minor->dev;
1023 struct drm_framebuffer *fb;
1024
1025 mutex_lock(&drm->mode_config.fb_lock);
1026
1027 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1028 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001029 fb->base.id, fb->width, fb->height,
1030 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001031 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001032 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001033 }
1034
1035 mutex_unlock(&drm->mode_config.fb_lock);
1036
1037 return 0;
1038}
1039
Thierry Reding28c23372015-01-23 09:16:03 +01001040static int tegra_debugfs_iova(struct seq_file *s, void *data)
1041{
1042 struct drm_info_node *node = (struct drm_info_node *)s->private;
1043 struct drm_device *drm = node->minor->dev;
1044 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001045 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001046
Thierry Reding347ad49d2017-03-09 20:04:56 +01001047 mutex_lock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +01001048 drm_mm_print(&tegra->mm, &p);
Thierry Reding347ad49d2017-03-09 20:04:56 +01001049 mutex_unlock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +01001050
1051 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001052}
1053
Thierry Redinge450fcc2013-02-13 16:13:16 +01001054static struct drm_info_list tegra_debugfs_list[] = {
1055 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001056 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001057};
1058
1059static int tegra_debugfs_init(struct drm_minor *minor)
1060{
1061 return drm_debugfs_create_files(tegra_debugfs_list,
1062 ARRAY_SIZE(tegra_debugfs_list),
1063 minor->debugfs_root, minor);
1064}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001065#endif
1066
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001067static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001068 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
1069 DRIVER_ATOMIC,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001070 .load = tegra_drm_load,
1071 .unload = tegra_drm_unload,
1072 .open = tegra_drm_open,
Thierry Reding3c03c462012-11-28 12:00:18 +01001073 .preclose = tegra_drm_preclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001074 .lastclose = tegra_drm_lastclose,
1075
Thierry Redinge450fcc2013-02-13 16:13:16 +01001076#if defined(CONFIG_DEBUG_FS)
1077 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001078#endif
1079
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001080 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001081 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001082
1083 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1084 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1085 .gem_prime_export = tegra_gem_prime_export,
1086 .gem_prime_import = tegra_gem_prime_import,
1087
Arto Merilainende2ba662013-03-22 16:34:08 +02001088 .dumb_create = tegra_bo_dumb_create,
1089 .dumb_map_offset = tegra_bo_dumb_map_offset,
Daniel Vetter43387b32013-07-16 09:12:04 +02001090 .dumb_destroy = drm_gem_dumb_destroy,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001091
1092 .ioctls = tegra_drm_ioctls,
1093 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1094 .fops = &tegra_drm_fops,
1095
1096 .name = DRIVER_NAME,
1097 .desc = DRIVER_DESC,
1098 .date = DRIVER_DATE,
1099 .major = DRIVER_MAJOR,
1100 .minor = DRIVER_MINOR,
1101 .patchlevel = DRIVER_PATCHLEVEL,
1102};
Thierry Reding776dc382013-10-14 14:43:22 +02001103
1104int tegra_drm_register_client(struct tegra_drm *tegra,
1105 struct tegra_drm_client *client)
1106{
1107 mutex_lock(&tegra->clients_lock);
1108 list_add_tail(&client->list, &tegra->clients);
1109 mutex_unlock(&tegra->clients_lock);
1110
1111 return 0;
1112}
1113
1114int tegra_drm_unregister_client(struct tegra_drm *tegra,
1115 struct tegra_drm_client *client)
1116{
1117 mutex_lock(&tegra->clients_lock);
1118 list_del_init(&client->list);
1119 mutex_unlock(&tegra->clients_lock);
1120
1121 return 0;
1122}
1123
Mikko Perttunenad926012016-12-14 13:16:11 +02001124void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
1125 dma_addr_t *dma)
1126{
1127 struct iova *alloc;
1128 void *virt;
1129 gfp_t gfp;
1130 int err;
1131
1132 if (tegra->domain)
1133 size = iova_align(&tegra->carveout.domain, size);
1134 else
1135 size = PAGE_ALIGN(size);
1136
1137 gfp = GFP_KERNEL | __GFP_ZERO;
1138 if (!tegra->domain) {
1139 /*
1140 * Many units only support 32-bit addresses, even on 64-bit
1141 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1142 * virtual address space, force allocations to be in the
1143 * lower 32-bit range.
1144 */
1145 gfp |= GFP_DMA;
1146 }
1147
1148 virt = (void *)__get_free_pages(gfp, get_order(size));
1149 if (!virt)
1150 return ERR_PTR(-ENOMEM);
1151
1152 if (!tegra->domain) {
1153 /*
1154 * If IOMMU is disabled, devices address physical memory
1155 * directly.
1156 */
1157 *dma = virt_to_phys(virt);
1158 return virt;
1159 }
1160
1161 alloc = alloc_iova(&tegra->carveout.domain,
1162 size >> tegra->carveout.shift,
1163 tegra->carveout.limit, true);
1164 if (!alloc) {
1165 err = -EBUSY;
1166 goto free_pages;
1167 }
1168
1169 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1170 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1171 size, IOMMU_READ | IOMMU_WRITE);
1172 if (err < 0)
1173 goto free_iova;
1174
1175 return virt;
1176
1177free_iova:
1178 __free_iova(&tegra->carveout.domain, alloc);
1179free_pages:
1180 free_pages((unsigned long)virt, get_order(size));
1181
1182 return ERR_PTR(err);
1183}
1184
1185void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1186 dma_addr_t dma)
1187{
1188 if (tegra->domain)
1189 size = iova_align(&tegra->carveout.domain, size);
1190 else
1191 size = PAGE_ALIGN(size);
1192
1193 if (tegra->domain) {
1194 iommu_unmap(tegra->domain, dma, size);
1195 free_iova(&tegra->carveout.domain,
1196 iova_pfn(&tegra->carveout.domain, dma));
1197 }
1198
1199 free_pages((unsigned long)virt, get_order(size));
1200}
1201
Thierry Reding9910f5c2014-05-22 09:57:15 +02001202static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001203{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001204 struct drm_driver *driver = &tegra_drm_driver;
1205 struct drm_device *drm;
1206 int err;
1207
1208 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001209 if (IS_ERR(drm))
1210 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001211
Thierry Reding9910f5c2014-05-22 09:57:15 +02001212 dev_set_drvdata(&dev->dev, drm);
1213
1214 err = drm_dev_register(drm, 0);
1215 if (err < 0)
1216 goto unref;
1217
Thierry Reding9910f5c2014-05-22 09:57:15 +02001218 return 0;
1219
1220unref:
1221 drm_dev_unref(drm);
1222 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001223}
1224
Thierry Reding9910f5c2014-05-22 09:57:15 +02001225static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001226{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001227 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1228
1229 drm_dev_unregister(drm);
1230 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001231
1232 return 0;
1233}
1234
Thierry Reding359ae682014-12-18 17:15:25 +01001235#ifdef CONFIG_PM_SLEEP
1236static int host1x_drm_suspend(struct device *dev)
1237{
1238 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001239 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001240
1241 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001242 tegra_drm_fb_suspend(drm);
1243
1244 tegra->state = drm_atomic_helper_suspend(drm);
1245 if (IS_ERR(tegra->state)) {
1246 tegra_drm_fb_resume(drm);
1247 drm_kms_helper_poll_enable(drm);
1248 return PTR_ERR(tegra->state);
1249 }
Thierry Reding359ae682014-12-18 17:15:25 +01001250
1251 return 0;
1252}
1253
1254static int host1x_drm_resume(struct device *dev)
1255{
1256 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001257 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001258
Thierry Reding986c58d2015-08-11 13:11:49 +02001259 drm_atomic_helper_resume(drm, tegra->state);
1260 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001261 drm_kms_helper_poll_enable(drm);
1262
1263 return 0;
1264}
1265#endif
1266
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001267static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1268 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001269
Thierry Reding776dc382013-10-14 14:43:22 +02001270static const struct of_device_id host1x_drm_subdevs[] = {
1271 { .compatible = "nvidia,tegra20-dc", },
1272 { .compatible = "nvidia,tegra20-hdmi", },
1273 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001274 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001275 { .compatible = "nvidia,tegra30-dc", },
1276 { .compatible = "nvidia,tegra30-hdmi", },
1277 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001278 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001279 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001280 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001281 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001282 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001283 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001284 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001285 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001286 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001287 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001288 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001289 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001290 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001291 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001292 { .compatible = "nvidia,tegra210-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001293 { /* sentinel */ }
1294};
1295
1296static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001297 .driver = {
1298 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001299 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001300 },
Thierry Reding776dc382013-10-14 14:43:22 +02001301 .probe = host1x_drm_probe,
1302 .remove = host1x_drm_remove,
1303 .subdevs = host1x_drm_subdevs,
1304};
1305
Thierry Reding473112e2015-09-10 16:07:14 +02001306static struct platform_driver * const drivers[] = {
1307 &tegra_dc_driver,
1308 &tegra_hdmi_driver,
1309 &tegra_dsi_driver,
1310 &tegra_dpaux_driver,
1311 &tegra_sor_driver,
1312 &tegra_gr2d_driver,
1313 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001314 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001315};
1316
Thierry Reding776dc382013-10-14 14:43:22 +02001317static int __init host1x_drm_init(void)
1318{
1319 int err;
1320
1321 err = host1x_driver_register(&host1x_drm_driver);
1322 if (err < 0)
1323 return err;
1324
Thierry Reding473112e2015-09-10 16:07:14 +02001325 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001326 if (err < 0)
1327 goto unregister_host1x;
1328
Thierry Reding776dc382013-10-14 14:43:22 +02001329 return 0;
1330
Thierry Reding776dc382013-10-14 14:43:22 +02001331unregister_host1x:
1332 host1x_driver_unregister(&host1x_drm_driver);
1333 return err;
1334}
1335module_init(host1x_drm_init);
1336
1337static void __exit host1x_drm_exit(void)
1338{
Thierry Reding473112e2015-09-10 16:07:14 +02001339 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001340 host1x_driver_unregister(&host1x_drm_driver);
1341}
1342module_exit(host1x_drm_exit);
1343
1344MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1345MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1346MODULE_LICENSE("GPL v2");