blob: c1b79190ce4dee120634fda2d046e88b2a099b22 [file] [log] [blame]
Yuval Mintz32a47e72016-05-11 16:36:12 +03001/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
Yuval Mintzdacd88d2016-05-11 16:36:16 +03009#include <linux/etherdevice.h>
Yuval Mintz36558c32016-05-11 16:36:17 +030010#include <linux/crc32.h>
Yuval Mintz0b55e272016-05-11 16:36:15 +030011#include <linux/qed/qed_iov_if.h>
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030012#include "qed_cxt.h"
13#include "qed_hsi.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030014#include "qed_hw.h"
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030015#include "qed_init_ops.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030016#include "qed_int.h"
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030017#include "qed_mcp.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030018#include "qed_reg_addr.h"
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030019#include "qed_sp.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030020#include "qed_sriov.h"
21#include "qed_vf.h"
22
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030023/* IOV ramrods */
24static int qed_sp_vf_start(struct qed_hwfn *p_hwfn,
25 u32 concrete_vfid, u16 opaque_vfid)
26{
27 struct vf_start_ramrod_data *p_ramrod = NULL;
28 struct qed_spq_entry *p_ent = NULL;
29 struct qed_sp_init_data init_data;
30 int rc = -EINVAL;
31
32 /* Get SPQ entry */
33 memset(&init_data, 0, sizeof(init_data));
34 init_data.cid = qed_spq_get_cid(p_hwfn);
35 init_data.opaque_fid = opaque_vfid;
36 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
37
38 rc = qed_sp_init_request(p_hwfn, &p_ent,
39 COMMON_RAMROD_VF_START,
40 PROTOCOLID_COMMON, &init_data);
41 if (rc)
42 return rc;
43
44 p_ramrod = &p_ent->ramrod.vf_start;
45
46 p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
47 p_ramrod->opaque_fid = cpu_to_le16(opaque_vfid);
48
49 p_ramrod->personality = PERSONALITY_ETH;
50
51 return qed_spq_post(p_hwfn, p_ent, NULL);
52}
53
Yuval Mintz0b55e272016-05-11 16:36:15 +030054static int qed_sp_vf_stop(struct qed_hwfn *p_hwfn,
55 u32 concrete_vfid, u16 opaque_vfid)
56{
57 struct vf_stop_ramrod_data *p_ramrod = NULL;
58 struct qed_spq_entry *p_ent = NULL;
59 struct qed_sp_init_data init_data;
60 int rc = -EINVAL;
61
62 /* Get SPQ entry */
63 memset(&init_data, 0, sizeof(init_data));
64 init_data.cid = qed_spq_get_cid(p_hwfn);
65 init_data.opaque_fid = opaque_vfid;
66 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
67
68 rc = qed_sp_init_request(p_hwfn, &p_ent,
69 COMMON_RAMROD_VF_STOP,
70 PROTOCOLID_COMMON, &init_data);
71 if (rc)
72 return rc;
73
74 p_ramrod = &p_ent->ramrod.vf_stop;
75
76 p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
77
78 return qed_spq_post(p_hwfn, p_ent, NULL);
79}
80
Yuval Mintz32a47e72016-05-11 16:36:12 +030081bool qed_iov_is_valid_vfid(struct qed_hwfn *p_hwfn,
82 int rel_vf_id, bool b_enabled_only)
83{
84 if (!p_hwfn->pf_iov_info) {
85 DP_NOTICE(p_hwfn->cdev, "No iov info\n");
86 return false;
87 }
88
89 if ((rel_vf_id >= p_hwfn->cdev->p_iov_info->total_vfs) ||
90 (rel_vf_id < 0))
91 return false;
92
93 if ((!p_hwfn->pf_iov_info->vfs_array[rel_vf_id].b_init) &&
94 b_enabled_only)
95 return false;
96
97 return true;
98}
99
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300100static struct qed_vf_info *qed_iov_get_vf_info(struct qed_hwfn *p_hwfn,
101 u16 relative_vf_id,
102 bool b_enabled_only)
103{
104 struct qed_vf_info *vf = NULL;
105
106 if (!p_hwfn->pf_iov_info) {
107 DP_NOTICE(p_hwfn->cdev, "No iov info\n");
108 return NULL;
109 }
110
111 if (qed_iov_is_valid_vfid(p_hwfn, relative_vf_id, b_enabled_only))
112 vf = &p_hwfn->pf_iov_info->vfs_array[relative_vf_id];
113 else
114 DP_ERR(p_hwfn, "qed_iov_get_vf_info: VF[%d] is not enabled\n",
115 relative_vf_id);
116
117 return vf;
118}
119
Yuval Mintz36558c32016-05-11 16:36:17 +0300120int qed_iov_post_vf_bulletin(struct qed_hwfn *p_hwfn,
121 int vfid, struct qed_ptt *p_ptt)
122{
123 struct qed_bulletin_content *p_bulletin;
124 int crc_size = sizeof(p_bulletin->crc);
125 struct qed_dmae_params params;
126 struct qed_vf_info *p_vf;
127
128 p_vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
129 if (!p_vf)
130 return -EINVAL;
131
132 if (!p_vf->vf_bulletin)
133 return -EINVAL;
134
135 p_bulletin = p_vf->bulletin.p_virt;
136
137 /* Increment bulletin board version and compute crc */
138 p_bulletin->version++;
139 p_bulletin->crc = crc32(0, (u8 *)p_bulletin + crc_size,
140 p_vf->bulletin.size - crc_size);
141
142 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
143 "Posting Bulletin 0x%08x to VF[%d] (CRC 0x%08x)\n",
144 p_bulletin->version, p_vf->relative_vf_id, p_bulletin->crc);
145
146 /* propagate bulletin board via dmae to vm memory */
147 memset(&params, 0, sizeof(params));
148 params.flags = QED_DMAE_FLAG_VF_DST;
149 params.dst_vfid = p_vf->abs_vf_id;
150 return qed_dmae_host2host(p_hwfn, p_ptt, p_vf->bulletin.phys,
151 p_vf->vf_bulletin, p_vf->bulletin.size / 4,
152 &params);
153}
154
Yuval Mintz32a47e72016-05-11 16:36:12 +0300155static int qed_iov_pci_cfg_info(struct qed_dev *cdev)
156{
157 struct qed_hw_sriov_info *iov = cdev->p_iov_info;
158 int pos = iov->pos;
159
160 DP_VERBOSE(cdev, QED_MSG_IOV, "sriov ext pos %d\n", pos);
161 pci_read_config_word(cdev->pdev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
162
163 pci_read_config_word(cdev->pdev,
164 pos + PCI_SRIOV_TOTAL_VF, &iov->total_vfs);
165 pci_read_config_word(cdev->pdev,
166 pos + PCI_SRIOV_INITIAL_VF, &iov->initial_vfs);
167
168 pci_read_config_word(cdev->pdev, pos + PCI_SRIOV_NUM_VF, &iov->num_vfs);
169 if (iov->num_vfs) {
170 DP_VERBOSE(cdev,
171 QED_MSG_IOV,
172 "Number of VFs are already set to non-zero value. Ignoring PCI configuration value\n");
173 iov->num_vfs = 0;
174 }
175
176 pci_read_config_word(cdev->pdev,
177 pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
178
179 pci_read_config_word(cdev->pdev,
180 pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
181
182 pci_read_config_word(cdev->pdev,
183 pos + PCI_SRIOV_VF_DID, &iov->vf_device_id);
184
185 pci_read_config_dword(cdev->pdev,
186 pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
187
188 pci_read_config_dword(cdev->pdev, pos + PCI_SRIOV_CAP, &iov->cap);
189
190 pci_read_config_byte(cdev->pdev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
191
192 DP_VERBOSE(cdev,
193 QED_MSG_IOV,
194 "IOV info: nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n",
195 iov->nres,
196 iov->cap,
197 iov->ctrl,
198 iov->total_vfs,
199 iov->initial_vfs,
200 iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz);
201
202 /* Some sanity checks */
203 if (iov->num_vfs > NUM_OF_VFS(cdev) ||
204 iov->total_vfs > NUM_OF_VFS(cdev)) {
205 /* This can happen only due to a bug. In this case we set
206 * num_vfs to zero to avoid memory corruption in the code that
207 * assumes max number of vfs
208 */
209 DP_NOTICE(cdev,
210 "IOV: Unexpected number of vfs set: %d setting num_vf to zero\n",
211 iov->num_vfs);
212
213 iov->num_vfs = 0;
214 iov->total_vfs = 0;
215 }
216
217 return 0;
218}
219
220static void qed_iov_clear_vf_igu_blocks(struct qed_hwfn *p_hwfn,
221 struct qed_ptt *p_ptt)
222{
223 struct qed_igu_block *p_sb;
224 u16 sb_id;
225 u32 val;
226
227 if (!p_hwfn->hw_info.p_igu_info) {
228 DP_ERR(p_hwfn,
229 "qed_iov_clear_vf_igu_blocks IGU Info not initialized\n");
230 return;
231 }
232
233 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
234 sb_id++) {
235 p_sb = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
236 if ((p_sb->status & QED_IGU_STATUS_FREE) &&
237 !(p_sb->status & QED_IGU_STATUS_PF)) {
238 val = qed_rd(p_hwfn, p_ptt,
239 IGU_REG_MAPPING_MEMORY + sb_id * 4);
240 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 0);
241 qed_wr(p_hwfn, p_ptt,
242 IGU_REG_MAPPING_MEMORY + 4 * sb_id, val);
243 }
244 }
245}
246
247static void qed_iov_setup_vfdb(struct qed_hwfn *p_hwfn)
248{
249 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
250 struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
251 struct qed_bulletin_content *p_bulletin_virt;
252 dma_addr_t req_p, rply_p, bulletin_p;
253 union pfvf_tlvs *p_reply_virt_addr;
254 union vfpf_tlvs *p_req_virt_addr;
255 u8 idx = 0;
256
257 memset(p_iov_info->vfs_array, 0, sizeof(p_iov_info->vfs_array));
258
259 p_req_virt_addr = p_iov_info->mbx_msg_virt_addr;
260 req_p = p_iov_info->mbx_msg_phys_addr;
261 p_reply_virt_addr = p_iov_info->mbx_reply_virt_addr;
262 rply_p = p_iov_info->mbx_reply_phys_addr;
263 p_bulletin_virt = p_iov_info->p_bulletins;
264 bulletin_p = p_iov_info->bulletins_phys;
265 if (!p_req_virt_addr || !p_reply_virt_addr || !p_bulletin_virt) {
266 DP_ERR(p_hwfn,
267 "qed_iov_setup_vfdb called without allocating mem first\n");
268 return;
269 }
270
271 for (idx = 0; idx < p_iov->total_vfs; idx++) {
272 struct qed_vf_info *vf = &p_iov_info->vfs_array[idx];
273 u32 concrete;
274
275 vf->vf_mbx.req_virt = p_req_virt_addr + idx;
276 vf->vf_mbx.req_phys = req_p + idx * sizeof(union vfpf_tlvs);
277 vf->vf_mbx.reply_virt = p_reply_virt_addr + idx;
278 vf->vf_mbx.reply_phys = rply_p + idx * sizeof(union pfvf_tlvs);
279
280 vf->state = VF_STOPPED;
281 vf->b_init = false;
282
283 vf->bulletin.phys = idx *
284 sizeof(struct qed_bulletin_content) +
285 bulletin_p;
286 vf->bulletin.p_virt = p_bulletin_virt + idx;
287 vf->bulletin.size = sizeof(struct qed_bulletin_content);
288
289 vf->relative_vf_id = idx;
290 vf->abs_vf_id = idx + p_iov->first_vf_in_pf;
291 concrete = qed_vfid_to_concrete(p_hwfn, vf->abs_vf_id);
292 vf->concrete_fid = concrete;
293 vf->opaque_fid = (p_hwfn->hw_info.opaque_fid & 0xff) |
294 (vf->abs_vf_id << 8);
295 vf->vport_id = idx + 1;
296 }
297}
298
299static int qed_iov_allocate_vfdb(struct qed_hwfn *p_hwfn)
300{
301 struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
302 void **p_v_addr;
303 u16 num_vfs = 0;
304
305 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
306
307 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
308 "qed_iov_allocate_vfdb for %d VFs\n", num_vfs);
309
310 /* Allocate PF Mailbox buffer (per-VF) */
311 p_iov_info->mbx_msg_size = sizeof(union vfpf_tlvs) * num_vfs;
312 p_v_addr = &p_iov_info->mbx_msg_virt_addr;
313 *p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
314 p_iov_info->mbx_msg_size,
315 &p_iov_info->mbx_msg_phys_addr,
316 GFP_KERNEL);
317 if (!*p_v_addr)
318 return -ENOMEM;
319
320 /* Allocate PF Mailbox Reply buffer (per-VF) */
321 p_iov_info->mbx_reply_size = sizeof(union pfvf_tlvs) * num_vfs;
322 p_v_addr = &p_iov_info->mbx_reply_virt_addr;
323 *p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
324 p_iov_info->mbx_reply_size,
325 &p_iov_info->mbx_reply_phys_addr,
326 GFP_KERNEL);
327 if (!*p_v_addr)
328 return -ENOMEM;
329
330 p_iov_info->bulletins_size = sizeof(struct qed_bulletin_content) *
331 num_vfs;
332 p_v_addr = &p_iov_info->p_bulletins;
333 *p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
334 p_iov_info->bulletins_size,
335 &p_iov_info->bulletins_phys,
336 GFP_KERNEL);
337 if (!*p_v_addr)
338 return -ENOMEM;
339
340 DP_VERBOSE(p_hwfn,
341 QED_MSG_IOV,
342 "PF's Requests mailbox [%p virt 0x%llx phys], Response mailbox [%p virt 0x%llx phys] Bulletins [%p virt 0x%llx phys]\n",
343 p_iov_info->mbx_msg_virt_addr,
344 (u64) p_iov_info->mbx_msg_phys_addr,
345 p_iov_info->mbx_reply_virt_addr,
346 (u64) p_iov_info->mbx_reply_phys_addr,
347 p_iov_info->p_bulletins, (u64) p_iov_info->bulletins_phys);
348
349 return 0;
350}
351
352static void qed_iov_free_vfdb(struct qed_hwfn *p_hwfn)
353{
354 struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
355
356 if (p_hwfn->pf_iov_info->mbx_msg_virt_addr)
357 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
358 p_iov_info->mbx_msg_size,
359 p_iov_info->mbx_msg_virt_addr,
360 p_iov_info->mbx_msg_phys_addr);
361
362 if (p_hwfn->pf_iov_info->mbx_reply_virt_addr)
363 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
364 p_iov_info->mbx_reply_size,
365 p_iov_info->mbx_reply_virt_addr,
366 p_iov_info->mbx_reply_phys_addr);
367
368 if (p_iov_info->p_bulletins)
369 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
370 p_iov_info->bulletins_size,
371 p_iov_info->p_bulletins,
372 p_iov_info->bulletins_phys);
373}
374
375int qed_iov_alloc(struct qed_hwfn *p_hwfn)
376{
377 struct qed_pf_iov *p_sriov;
378
379 if (!IS_PF_SRIOV(p_hwfn)) {
380 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
381 "No SR-IOV - no need for IOV db\n");
382 return 0;
383 }
384
385 p_sriov = kzalloc(sizeof(*p_sriov), GFP_KERNEL);
386 if (!p_sriov) {
387 DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_sriov'\n");
388 return -ENOMEM;
389 }
390
391 p_hwfn->pf_iov_info = p_sriov;
392
393 return qed_iov_allocate_vfdb(p_hwfn);
394}
395
396void qed_iov_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
397{
398 if (!IS_PF_SRIOV(p_hwfn) || !IS_PF_SRIOV_ALLOC(p_hwfn))
399 return;
400
401 qed_iov_setup_vfdb(p_hwfn);
402 qed_iov_clear_vf_igu_blocks(p_hwfn, p_ptt);
403}
404
405void qed_iov_free(struct qed_hwfn *p_hwfn)
406{
407 if (IS_PF_SRIOV_ALLOC(p_hwfn)) {
408 qed_iov_free_vfdb(p_hwfn);
409 kfree(p_hwfn->pf_iov_info);
410 }
411}
412
413void qed_iov_free_hw_info(struct qed_dev *cdev)
414{
415 kfree(cdev->p_iov_info);
416 cdev->p_iov_info = NULL;
417}
418
419int qed_iov_hw_info(struct qed_hwfn *p_hwfn)
420{
421 struct qed_dev *cdev = p_hwfn->cdev;
422 int pos;
423 int rc;
424
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300425 if (IS_VF(p_hwfn->cdev))
426 return 0;
427
Yuval Mintz32a47e72016-05-11 16:36:12 +0300428 /* Learn the PCI configuration */
429 pos = pci_find_ext_capability(p_hwfn->cdev->pdev,
430 PCI_EXT_CAP_ID_SRIOV);
431 if (!pos) {
432 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "No PCIe IOV support\n");
433 return 0;
434 }
435
436 /* Allocate a new struct for IOV information */
437 cdev->p_iov_info = kzalloc(sizeof(*cdev->p_iov_info), GFP_KERNEL);
438 if (!cdev->p_iov_info) {
439 DP_NOTICE(p_hwfn, "Can't support IOV due to lack of memory\n");
440 return -ENOMEM;
441 }
442 cdev->p_iov_info->pos = pos;
443
444 rc = qed_iov_pci_cfg_info(cdev);
445 if (rc)
446 return rc;
447
448 /* We want PF IOV to be synonemous with the existance of p_iov_info;
449 * In case the capability is published but there are no VFs, simply
450 * de-allocate the struct.
451 */
452 if (!cdev->p_iov_info->total_vfs) {
453 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
454 "IOV capabilities, but no VFs are published\n");
455 kfree(cdev->p_iov_info);
456 cdev->p_iov_info = NULL;
457 return 0;
458 }
459
460 /* Calculate the first VF index - this is a bit tricky; Basically,
461 * VFs start at offset 16 relative to PF0, and 2nd engine VFs begin
462 * after the first engine's VFs.
463 */
464 cdev->p_iov_info->first_vf_in_pf = p_hwfn->cdev->p_iov_info->offset +
465 p_hwfn->abs_pf_id - 16;
466 if (QED_PATH_ID(p_hwfn))
467 cdev->p_iov_info->first_vf_in_pf -= MAX_NUM_VFS_BB;
468
469 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
470 "First VF in hwfn 0x%08x\n",
471 cdev->p_iov_info->first_vf_in_pf);
472
473 return 0;
474}
475
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300476static bool qed_iov_pf_sanity_check(struct qed_hwfn *p_hwfn, int vfid)
477{
478 /* Check PF supports sriov */
479 if (!IS_QED_SRIOV(p_hwfn->cdev) || !IS_PF_SRIOV_ALLOC(p_hwfn))
480 return false;
481
482 /* Check VF validity */
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300483 if (IS_VF(p_hwfn->cdev) || !IS_QED_SRIOV(p_hwfn->cdev) ||
484 !IS_PF_SRIOV_ALLOC(p_hwfn))
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300485 return false;
486
487 return true;
488}
489
Yuval Mintz0b55e272016-05-11 16:36:15 +0300490static void qed_iov_set_vf_to_disable(struct qed_dev *cdev,
491 u16 rel_vf_id, u8 to_disable)
492{
493 struct qed_vf_info *vf;
494 int i;
495
496 for_each_hwfn(cdev, i) {
497 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
498
499 vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, false);
500 if (!vf)
501 continue;
502
503 vf->to_disable = to_disable;
504 }
505}
506
507void qed_iov_set_vfs_to_disable(struct qed_dev *cdev, u8 to_disable)
508{
509 u16 i;
510
511 if (!IS_QED_SRIOV(cdev))
512 return;
513
514 for (i = 0; i < cdev->p_iov_info->total_vfs; i++)
515 qed_iov_set_vf_to_disable(cdev, i, to_disable);
516}
517
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300518static void qed_iov_vf_pglue_clear_err(struct qed_hwfn *p_hwfn,
519 struct qed_ptt *p_ptt, u8 abs_vfid)
520{
521 qed_wr(p_hwfn, p_ptt,
522 PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR + (abs_vfid >> 5) * 4,
523 1 << (abs_vfid & 0x1f));
524}
525
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300526static void qed_iov_vf_igu_reset(struct qed_hwfn *p_hwfn,
527 struct qed_ptt *p_ptt, struct qed_vf_info *vf)
528{
529 u16 igu_sb_id;
530 int i;
531
532 /* Set VF masks and configuration - pretend */
533 qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
534
535 qed_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_VF_MSG_SENT, 0);
536
537 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
538 "value in VF_CONFIGURATION of vf %d after write %x\n",
539 vf->abs_vf_id,
540 qed_rd(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION));
541
542 /* unpretend */
543 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
544
545 /* iterate over all queues, clear sb consumer */
546 for (i = 0; i < vf->num_sbs; i++) {
547 igu_sb_id = vf->igu_sbs[i];
548 /* Set then clear... */
549 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1,
550 vf->opaque_fid);
551 qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0,
552 vf->opaque_fid);
553 }
554}
555
Yuval Mintz0b55e272016-05-11 16:36:15 +0300556static void qed_iov_vf_igu_set_int(struct qed_hwfn *p_hwfn,
557 struct qed_ptt *p_ptt,
558 struct qed_vf_info *vf, bool enable)
559{
560 u32 igu_vf_conf;
561
562 qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
563
564 igu_vf_conf = qed_rd(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION);
565
566 if (enable)
567 igu_vf_conf |= IGU_VF_CONF_MSI_MSIX_EN;
568 else
569 igu_vf_conf &= ~IGU_VF_CONF_MSI_MSIX_EN;
570
571 qed_wr(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION, igu_vf_conf);
572
573 /* unpretend */
574 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
575}
576
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300577static int qed_iov_enable_vf_access(struct qed_hwfn *p_hwfn,
578 struct qed_ptt *p_ptt,
579 struct qed_vf_info *vf)
580{
581 u32 igu_vf_conf = IGU_VF_CONF_FUNC_EN;
582 int rc;
583
Yuval Mintz0b55e272016-05-11 16:36:15 +0300584 if (vf->to_disable)
585 return 0;
586
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300587 DP_VERBOSE(p_hwfn,
588 QED_MSG_IOV,
589 "Enable internal access for vf %x [abs %x]\n",
590 vf->abs_vf_id, QED_VF_ABS_ID(p_hwfn, vf));
591
592 qed_iov_vf_pglue_clear_err(p_hwfn, p_ptt, QED_VF_ABS_ID(p_hwfn, vf));
593
594 rc = qed_mcp_config_vf_msix(p_hwfn, p_ptt, vf->abs_vf_id, vf->num_sbs);
595 if (rc)
596 return rc;
597
598 qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
599
600 SET_FIELD(igu_vf_conf, IGU_VF_CONF_PARENT, p_hwfn->rel_pf_id);
601 STORE_RT_REG(p_hwfn, IGU_REG_VF_CONFIGURATION_RT_OFFSET, igu_vf_conf);
602
603 qed_init_run(p_hwfn, p_ptt, PHASE_VF, vf->abs_vf_id,
604 p_hwfn->hw_info.hw_mode);
605
606 /* unpretend */
607 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
608
609 if (vf->state != VF_STOPPED) {
610 DP_NOTICE(p_hwfn, "VF[%02x] is already started\n",
611 vf->abs_vf_id);
612 return -EINVAL;
613 }
614
615 /* Start VF */
616 rc = qed_sp_vf_start(p_hwfn, vf->concrete_fid, vf->opaque_fid);
617 if (rc)
618 DP_NOTICE(p_hwfn, "Failed to start VF[%02x]\n", vf->abs_vf_id);
619
620 vf->state = VF_FREE;
621
622 return rc;
623}
624
Yuval Mintz0b55e272016-05-11 16:36:15 +0300625/**
626 * @brief qed_iov_config_perm_table - configure the permission
627 * zone table.
628 * In E4, queue zone permission table size is 320x9. There
629 * are 320 VF queues for single engine device (256 for dual
630 * engine device), and each entry has the following format:
631 * {Valid, VF[7:0]}
632 * @param p_hwfn
633 * @param p_ptt
634 * @param vf
635 * @param enable
636 */
637static void qed_iov_config_perm_table(struct qed_hwfn *p_hwfn,
638 struct qed_ptt *p_ptt,
639 struct qed_vf_info *vf, u8 enable)
640{
641 u32 reg_addr, val;
642 u16 qzone_id = 0;
643 int qid;
644
645 for (qid = 0; qid < vf->num_rxqs; qid++) {
646 qed_fw_l2_queue(p_hwfn, vf->vf_queues[qid].fw_rx_qid,
647 &qzone_id);
648
649 reg_addr = PSWHST_REG_ZONE_PERMISSION_TABLE + qzone_id * 4;
650 val = enable ? (vf->abs_vf_id | (1 << 8)) : 0;
651 qed_wr(p_hwfn, p_ptt, reg_addr, val);
652 }
653}
654
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300655static void qed_iov_enable_vf_traffic(struct qed_hwfn *p_hwfn,
656 struct qed_ptt *p_ptt,
657 struct qed_vf_info *vf)
658{
659 /* Reset vf in IGU - interrupts are still disabled */
660 qed_iov_vf_igu_reset(p_hwfn, p_ptt, vf);
661
662 qed_iov_vf_igu_set_int(p_hwfn, p_ptt, vf, 1);
663
664 /* Permission Table */
665 qed_iov_config_perm_table(p_hwfn, p_ptt, vf, true);
666}
667
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300668static u8 qed_iov_alloc_vf_igu_sbs(struct qed_hwfn *p_hwfn,
669 struct qed_ptt *p_ptt,
670 struct qed_vf_info *vf, u16 num_rx_queues)
671{
672 struct qed_igu_block *igu_blocks;
673 int qid = 0, igu_id = 0;
674 u32 val = 0;
675
676 igu_blocks = p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks;
677
678 if (num_rx_queues > p_hwfn->hw_info.p_igu_info->free_blks)
679 num_rx_queues = p_hwfn->hw_info.p_igu_info->free_blks;
680 p_hwfn->hw_info.p_igu_info->free_blks -= num_rx_queues;
681
682 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, vf->abs_vf_id);
683 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 1);
684 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, 0);
685
686 while ((qid < num_rx_queues) &&
687 (igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev))) {
688 if (igu_blocks[igu_id].status & QED_IGU_STATUS_FREE) {
689 struct cau_sb_entry sb_entry;
690
691 vf->igu_sbs[qid] = (u16)igu_id;
692 igu_blocks[igu_id].status &= ~QED_IGU_STATUS_FREE;
693
694 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, qid);
695
696 qed_wr(p_hwfn, p_ptt,
697 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_id,
698 val);
699
700 /* Configure igu sb in CAU which were marked valid */
701 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
702 p_hwfn->rel_pf_id,
703 vf->abs_vf_id, 1);
704 qed_dmae_host2grc(p_hwfn, p_ptt,
705 (u64)(uintptr_t)&sb_entry,
706 CAU_REG_SB_VAR_MEMORY +
707 igu_id * sizeof(u64), 2, 0);
708 qid++;
709 }
710 igu_id++;
711 }
712
713 vf->num_sbs = (u8) num_rx_queues;
714
715 return vf->num_sbs;
716}
717
Yuval Mintz0b55e272016-05-11 16:36:15 +0300718static void qed_iov_free_vf_igu_sbs(struct qed_hwfn *p_hwfn,
719 struct qed_ptt *p_ptt,
720 struct qed_vf_info *vf)
721{
722 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
723 int idx, igu_id;
724 u32 addr, val;
725
726 /* Invalidate igu CAM lines and mark them as free */
727 for (idx = 0; idx < vf->num_sbs; idx++) {
728 igu_id = vf->igu_sbs[idx];
729 addr = IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_id;
730
731 val = qed_rd(p_hwfn, p_ptt, addr);
732 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 0);
733 qed_wr(p_hwfn, p_ptt, addr, val);
734
735 p_info->igu_map.igu_blocks[igu_id].status |=
736 QED_IGU_STATUS_FREE;
737
738 p_hwfn->hw_info.p_igu_info->free_blks++;
739 }
740
741 vf->num_sbs = 0;
742}
743
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300744static int qed_iov_init_hw_for_vf(struct qed_hwfn *p_hwfn,
745 struct qed_ptt *p_ptt,
746 u16 rel_vf_id, u16 num_rx_queues)
747{
748 u8 num_of_vf_avaiable_chains = 0;
749 struct qed_vf_info *vf = NULL;
750 int rc = 0;
751 u32 cids;
752 u8 i;
753
754 vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, false);
755 if (!vf) {
756 DP_ERR(p_hwfn, "qed_iov_init_hw_for_vf : vf is NULL\n");
757 return -EINVAL;
758 }
759
760 if (vf->b_init) {
761 DP_NOTICE(p_hwfn, "VF[%d] is already active.\n", rel_vf_id);
762 return -EINVAL;
763 }
764
765 /* Limit number of queues according to number of CIDs */
766 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, &cids);
767 DP_VERBOSE(p_hwfn,
768 QED_MSG_IOV,
769 "VF[%d] - requesting to initialize for 0x%04x queues [0x%04x CIDs available]\n",
770 vf->relative_vf_id, num_rx_queues, (u16) cids);
771 num_rx_queues = min_t(u16, num_rx_queues, ((u16) cids));
772
773 num_of_vf_avaiable_chains = qed_iov_alloc_vf_igu_sbs(p_hwfn,
774 p_ptt,
775 vf,
776 num_rx_queues);
777 if (!num_of_vf_avaiable_chains) {
778 DP_ERR(p_hwfn, "no available igu sbs\n");
779 return -ENOMEM;
780 }
781
782 /* Choose queue number and index ranges */
783 vf->num_rxqs = num_of_vf_avaiable_chains;
784 vf->num_txqs = num_of_vf_avaiable_chains;
785
786 for (i = 0; i < vf->num_rxqs; i++) {
787 u16 queue_id = qed_int_queue_id_from_sb_id(p_hwfn,
788 vf->igu_sbs[i]);
789
790 if (queue_id > RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
791 DP_NOTICE(p_hwfn,
792 "VF[%d] will require utilizing of out-of-bounds queues - %04x\n",
793 vf->relative_vf_id, queue_id);
794 return -EINVAL;
795 }
796
797 /* CIDs are per-VF, so no problem having them 0-based. */
798 vf->vf_queues[i].fw_rx_qid = queue_id;
799 vf->vf_queues[i].fw_tx_qid = queue_id;
800 vf->vf_queues[i].fw_cid = i;
801
802 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
803 "VF[%d] - [%d] SB %04x, Tx/Rx queue %04x CID %04x\n",
804 vf->relative_vf_id, i, vf->igu_sbs[i], queue_id, i);
805 }
806 rc = qed_iov_enable_vf_access(p_hwfn, p_ptt, vf);
807 if (!rc) {
808 vf->b_init = true;
809
810 if (IS_LEAD_HWFN(p_hwfn))
811 p_hwfn->cdev->p_iov_info->num_vfs++;
812 }
813
814 return rc;
815}
816
Yuval Mintz0b55e272016-05-11 16:36:15 +0300817static int qed_iov_release_hw_for_vf(struct qed_hwfn *p_hwfn,
818 struct qed_ptt *p_ptt, u16 rel_vf_id)
819{
820 struct qed_vf_info *vf = NULL;
821 int rc = 0;
822
823 vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
824 if (!vf) {
825 DP_ERR(p_hwfn, "qed_iov_release_hw_for_vf : vf is NULL\n");
826 return -EINVAL;
827 }
828
Yuval Mintz36558c32016-05-11 16:36:17 +0300829 if (vf->bulletin.p_virt)
830 memset(vf->bulletin.p_virt, 0, sizeof(*vf->bulletin.p_virt));
831
832 memset(&vf->p_vf_info, 0, sizeof(vf->p_vf_info));
833
Yuval Mintz0b55e272016-05-11 16:36:15 +0300834 if (vf->state != VF_STOPPED) {
835 /* Stopping the VF */
836 rc = qed_sp_vf_stop(p_hwfn, vf->concrete_fid, vf->opaque_fid);
837
838 if (rc != 0) {
839 DP_ERR(p_hwfn, "qed_sp_vf_stop returned error %d\n",
840 rc);
841 return rc;
842 }
843
844 vf->state = VF_STOPPED;
845 }
846
847 /* disablng interrupts and resetting permission table was done during
848 * vf-close, however, we could get here without going through vf_close
849 */
850 /* Disable Interrupts for VF */
851 qed_iov_vf_igu_set_int(p_hwfn, p_ptt, vf, 0);
852
853 /* Reset Permission table */
854 qed_iov_config_perm_table(p_hwfn, p_ptt, vf, 0);
855
856 vf->num_rxqs = 0;
857 vf->num_txqs = 0;
858 qed_iov_free_vf_igu_sbs(p_hwfn, p_ptt, vf);
859
860 if (vf->b_init) {
861 vf->b_init = false;
862
863 if (IS_LEAD_HWFN(p_hwfn))
864 p_hwfn->cdev->p_iov_info->num_vfs--;
865 }
866
867 return 0;
868}
869
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300870static bool qed_iov_tlv_supported(u16 tlvtype)
871{
872 return CHANNEL_TLV_NONE < tlvtype && tlvtype < CHANNEL_TLV_MAX;
873}
874
875/* place a given tlv on the tlv buffer, continuing current tlv list */
876void *qed_add_tlv(struct qed_hwfn *p_hwfn, u8 **offset, u16 type, u16 length)
877{
878 struct channel_tlv *tl = (struct channel_tlv *)*offset;
879
880 tl->type = type;
881 tl->length = length;
882
883 /* Offset should keep pointing to next TLV (the end of the last) */
884 *offset += length;
885
886 /* Return a pointer to the start of the added tlv */
887 return *offset - length;
888}
889
890/* list the types and lengths of the tlvs on the buffer */
891void qed_dp_tlv_list(struct qed_hwfn *p_hwfn, void *tlvs_list)
892{
893 u16 i = 1, total_length = 0;
894 struct channel_tlv *tlv;
895
896 do {
897 tlv = (struct channel_tlv *)((u8 *)tlvs_list + total_length);
898
899 /* output tlv */
900 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
901 "TLV number %d: type %d, length %d\n",
902 i, tlv->type, tlv->length);
903
904 if (tlv->type == CHANNEL_TLV_LIST_END)
905 return;
906
907 /* Validate entry - protect against malicious VFs */
908 if (!tlv->length) {
909 DP_NOTICE(p_hwfn, "TLV of length 0 found\n");
910 return;
911 }
912
913 total_length += tlv->length;
914
915 if (total_length >= sizeof(struct tlv_buffer_size)) {
916 DP_NOTICE(p_hwfn, "TLV ==> Buffer overflow\n");
917 return;
918 }
919
920 i++;
921 } while (1);
922}
923
924static void qed_iov_send_response(struct qed_hwfn *p_hwfn,
925 struct qed_ptt *p_ptt,
926 struct qed_vf_info *p_vf,
927 u16 length, u8 status)
928{
929 struct qed_iov_vf_mbx *mbx = &p_vf->vf_mbx;
930 struct qed_dmae_params params;
931 u8 eng_vf_id;
932
933 mbx->reply_virt->default_resp.hdr.status = status;
934
935 qed_dp_tlv_list(p_hwfn, mbx->reply_virt);
936
937 eng_vf_id = p_vf->abs_vf_id;
938
939 memset(&params, 0, sizeof(struct qed_dmae_params));
940 params.flags = QED_DMAE_FLAG_VF_DST;
941 params.dst_vfid = eng_vf_id;
942
943 qed_dmae_host2host(p_hwfn, p_ptt, mbx->reply_phys + sizeof(u64),
944 mbx->req_virt->first_tlv.reply_address +
945 sizeof(u64),
946 (sizeof(union pfvf_tlvs) - sizeof(u64)) / 4,
947 &params);
948
949 qed_dmae_host2host(p_hwfn, p_ptt, mbx->reply_phys,
950 mbx->req_virt->first_tlv.reply_address,
951 sizeof(u64) / 4, &params);
952
953 REG_WR(p_hwfn,
954 GTT_BAR0_MAP_REG_USDM_RAM +
955 USTORM_VF_PF_CHANNEL_READY_OFFSET(eng_vf_id), 1);
956}
957
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300958static u16 qed_iov_vport_to_tlv(struct qed_hwfn *p_hwfn,
959 enum qed_iov_vport_update_flag flag)
960{
961 switch (flag) {
962 case QED_IOV_VP_UPDATE_ACTIVATE:
963 return CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
Yuval Mintz17b235c2016-05-11 16:36:18 +0300964 case QED_IOV_VP_UPDATE_VLAN_STRIP:
965 return CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP;
966 case QED_IOV_VP_UPDATE_TX_SWITCH:
967 return CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300968 case QED_IOV_VP_UPDATE_MCAST:
969 return CHANNEL_TLV_VPORT_UPDATE_MCAST;
970 case QED_IOV_VP_UPDATE_ACCEPT_PARAM:
971 return CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
972 case QED_IOV_VP_UPDATE_RSS:
973 return CHANNEL_TLV_VPORT_UPDATE_RSS;
Yuval Mintz17b235c2016-05-11 16:36:18 +0300974 case QED_IOV_VP_UPDATE_ACCEPT_ANY_VLAN:
975 return CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
976 case QED_IOV_VP_UPDATE_SGE_TPA:
977 return CHANNEL_TLV_VPORT_UPDATE_SGE_TPA;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300978 default:
979 return 0;
980 }
981}
982
983static u16 qed_iov_prep_vp_update_resp_tlvs(struct qed_hwfn *p_hwfn,
984 struct qed_vf_info *p_vf,
985 struct qed_iov_vf_mbx *p_mbx,
986 u8 status,
987 u16 tlvs_mask, u16 tlvs_accepted)
988{
989 struct pfvf_def_resp_tlv *resp;
990 u16 size, total_len, i;
991
992 memset(p_mbx->reply_virt, 0, sizeof(union pfvf_tlvs));
993 p_mbx->offset = (u8 *)p_mbx->reply_virt;
994 size = sizeof(struct pfvf_def_resp_tlv);
995 total_len = size;
996
997 qed_add_tlv(p_hwfn, &p_mbx->offset, CHANNEL_TLV_VPORT_UPDATE, size);
998
999 /* Prepare response for all extended tlvs if they are found by PF */
1000 for (i = 0; i < QED_IOV_VP_UPDATE_MAX; i++) {
1001 if (!(tlvs_mask & (1 << i)))
1002 continue;
1003
1004 resp = qed_add_tlv(p_hwfn, &p_mbx->offset,
1005 qed_iov_vport_to_tlv(p_hwfn, i), size);
1006
1007 if (tlvs_accepted & (1 << i))
1008 resp->hdr.status = status;
1009 else
1010 resp->hdr.status = PFVF_STATUS_NOT_SUPPORTED;
1011
1012 DP_VERBOSE(p_hwfn,
1013 QED_MSG_IOV,
1014 "VF[%d] - vport_update response: TLV %d, status %02x\n",
1015 p_vf->relative_vf_id,
1016 qed_iov_vport_to_tlv(p_hwfn, i), resp->hdr.status);
1017
1018 total_len += size;
1019 }
1020
1021 qed_add_tlv(p_hwfn, &p_mbx->offset, CHANNEL_TLV_LIST_END,
1022 sizeof(struct channel_list_end_tlv));
1023
1024 return total_len;
1025}
1026
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001027static void qed_iov_prepare_resp(struct qed_hwfn *p_hwfn,
1028 struct qed_ptt *p_ptt,
1029 struct qed_vf_info *vf_info,
1030 u16 type, u16 length, u8 status)
1031{
1032 struct qed_iov_vf_mbx *mbx = &vf_info->vf_mbx;
1033
1034 mbx->offset = (u8 *)mbx->reply_virt;
1035
1036 qed_add_tlv(p_hwfn, &mbx->offset, type, length);
1037 qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_LIST_END,
1038 sizeof(struct channel_list_end_tlv));
1039
1040 qed_iov_send_response(p_hwfn, p_ptt, vf_info, length, status);
1041}
1042
Yuval Mintz0b55e272016-05-11 16:36:15 +03001043struct qed_public_vf_info *qed_iov_get_public_vf_info(struct qed_hwfn *p_hwfn,
1044 u16 relative_vf_id,
1045 bool b_enabled_only)
1046{
1047 struct qed_vf_info *vf = NULL;
1048
1049 vf = qed_iov_get_vf_info(p_hwfn, relative_vf_id, b_enabled_only);
1050 if (!vf)
1051 return NULL;
1052
1053 return &vf->p_vf_info;
1054}
1055
1056void qed_iov_clean_vf(struct qed_hwfn *p_hwfn, u8 vfid)
1057{
1058 struct qed_public_vf_info *vf_info;
1059
1060 vf_info = qed_iov_get_public_vf_info(p_hwfn, vfid, false);
1061
1062 if (!vf_info)
1063 return;
1064
1065 /* Clear the VF mac */
1066 memset(vf_info->mac, 0, ETH_ALEN);
1067}
1068
1069static void qed_iov_vf_cleanup(struct qed_hwfn *p_hwfn,
1070 struct qed_vf_info *p_vf)
1071{
1072 u32 i;
1073
1074 p_vf->vf_bulletin = 0;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001075 p_vf->vport_instance = 0;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001076 p_vf->num_mac_filters = 0;
1077 p_vf->num_vlan_filters = 0;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001078 p_vf->configured_features = 0;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001079
1080 /* If VF previously requested less resources, go back to default */
1081 p_vf->num_rxqs = p_vf->num_sbs;
1082 p_vf->num_txqs = p_vf->num_sbs;
1083
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001084 p_vf->num_active_rxqs = 0;
1085
Yuval Mintz0b55e272016-05-11 16:36:15 +03001086 for (i = 0; i < QED_MAX_VF_CHAINS_PER_PF; i++)
1087 p_vf->vf_queues[i].rxq_active = 0;
1088
Yuval Mintz08feecd2016-05-11 16:36:20 +03001089 memset(&p_vf->shadow_config, 0, sizeof(p_vf->shadow_config));
Yuval Mintz0b55e272016-05-11 16:36:15 +03001090 qed_iov_clean_vf(p_hwfn, p_vf->relative_vf_id);
1091}
1092
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001093static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
1094 struct qed_ptt *p_ptt,
1095 struct qed_vf_info *vf)
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001096{
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001097 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1098 struct pfvf_acquire_resp_tlv *resp = &mbx->reply_virt->acquire_resp;
1099 struct pf_vf_pfdev_info *pfdev_info = &resp->pfdev_info;
1100 struct vfpf_acquire_tlv *req = &mbx->req_virt->acquire;
1101 u8 i, vfpf_status = PFVF_STATUS_SUCCESS;
1102 struct pf_vf_resc *resc = &resp->resc;
1103
1104 /* Validate FW compatibility */
1105 if (req->vfdev_info.fw_major != FW_MAJOR_VERSION ||
1106 req->vfdev_info.fw_minor != FW_MINOR_VERSION ||
1107 req->vfdev_info.fw_revision != FW_REVISION_VERSION ||
1108 req->vfdev_info.fw_engineering != FW_ENGINEERING_VERSION) {
1109 DP_INFO(p_hwfn,
1110 "VF[%d] is running an incompatible driver [VF needs FW %02x:%02x:%02x:%02x but Hypervisor is using %02x:%02x:%02x:%02x]\n",
1111 vf->abs_vf_id,
1112 req->vfdev_info.fw_major,
1113 req->vfdev_info.fw_minor,
1114 req->vfdev_info.fw_revision,
1115 req->vfdev_info.fw_engineering,
1116 FW_MAJOR_VERSION,
1117 FW_MINOR_VERSION,
1118 FW_REVISION_VERSION, FW_ENGINEERING_VERSION);
1119 vfpf_status = PFVF_STATUS_NOT_SUPPORTED;
1120 goto out;
1121 }
1122
1123 /* On 100g PFs, prevent old VFs from loading */
1124 if ((p_hwfn->cdev->num_hwfns > 1) &&
1125 !(req->vfdev_info.capabilities & VFPF_ACQUIRE_CAP_100G)) {
1126 DP_INFO(p_hwfn,
1127 "VF[%d] is running an old driver that doesn't support 100g\n",
1128 vf->abs_vf_id);
1129 vfpf_status = PFVF_STATUS_NOT_SUPPORTED;
1130 goto out;
1131 }
1132
1133 memset(resp, 0, sizeof(*resp));
1134
1135 /* Fill in vf info stuff */
1136 vf->opaque_fid = req->vfdev_info.opaque_fid;
1137 vf->num_mac_filters = 1;
1138 vf->num_vlan_filters = QED_ETH_VF_NUM_VLAN_FILTERS;
1139
1140 vf->vf_bulletin = req->bulletin_addr;
1141 vf->bulletin.size = (vf->bulletin.size < req->bulletin_size) ?
1142 vf->bulletin.size : req->bulletin_size;
1143
1144 /* fill in pfdev info */
1145 pfdev_info->chip_num = p_hwfn->cdev->chip_num;
1146 pfdev_info->db_size = 0;
1147 pfdev_info->indices_per_sb = PIS_PER_SB;
1148
1149 pfdev_info->capabilities = PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED |
1150 PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE;
1151 if (p_hwfn->cdev->num_hwfns > 1)
1152 pfdev_info->capabilities |= PFVF_ACQUIRE_CAP_100G;
1153
1154 pfdev_info->stats_info.mstats.address =
1155 PXP_VF_BAR0_START_MSDM_ZONE_B +
1156 offsetof(struct mstorm_vf_zone, non_trigger.eth_queue_stat);
1157 pfdev_info->stats_info.mstats.len =
1158 sizeof(struct eth_mstorm_per_queue_stat);
1159
1160 pfdev_info->stats_info.ustats.address =
1161 PXP_VF_BAR0_START_USDM_ZONE_B +
1162 offsetof(struct ustorm_vf_zone, non_trigger.eth_queue_stat);
1163 pfdev_info->stats_info.ustats.len =
1164 sizeof(struct eth_ustorm_per_queue_stat);
1165
1166 pfdev_info->stats_info.pstats.address =
1167 PXP_VF_BAR0_START_PSDM_ZONE_B +
1168 offsetof(struct pstorm_vf_zone, non_trigger.eth_queue_stat);
1169 pfdev_info->stats_info.pstats.len =
1170 sizeof(struct eth_pstorm_per_queue_stat);
1171
1172 pfdev_info->stats_info.tstats.address = 0;
1173 pfdev_info->stats_info.tstats.len = 0;
1174
1175 memcpy(pfdev_info->port_mac, p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
1176
1177 pfdev_info->fw_major = FW_MAJOR_VERSION;
1178 pfdev_info->fw_minor = FW_MINOR_VERSION;
1179 pfdev_info->fw_rev = FW_REVISION_VERSION;
1180 pfdev_info->fw_eng = FW_ENGINEERING_VERSION;
1181 pfdev_info->os_type = VFPF_ACQUIRE_OS_LINUX;
1182 qed_mcp_get_mfw_ver(p_hwfn, p_ptt, &pfdev_info->mfw_ver, NULL);
1183
1184 pfdev_info->dev_type = p_hwfn->cdev->type;
1185 pfdev_info->chip_rev = p_hwfn->cdev->chip_rev;
1186
1187 resc->num_rxqs = vf->num_rxqs;
1188 resc->num_txqs = vf->num_txqs;
1189 resc->num_sbs = vf->num_sbs;
1190 for (i = 0; i < resc->num_sbs; i++) {
1191 resc->hw_sbs[i].hw_sb_id = vf->igu_sbs[i];
1192 resc->hw_sbs[i].sb_qid = 0;
1193 }
1194
1195 for (i = 0; i < resc->num_rxqs; i++) {
1196 qed_fw_l2_queue(p_hwfn, vf->vf_queues[i].fw_rx_qid,
1197 (u16 *)&resc->hw_qid[i]);
1198 resc->cid[i] = vf->vf_queues[i].fw_cid;
1199 }
1200
1201 resc->num_mac_filters = min_t(u8, vf->num_mac_filters,
1202 req->resc_request.num_mac_filters);
1203 resc->num_vlan_filters = min_t(u8, vf->num_vlan_filters,
1204 req->resc_request.num_vlan_filters);
1205
1206 /* This isn't really required as VF isn't limited, but some VFs might
1207 * actually test this value, so need to provide it.
1208 */
1209 resc->num_mc_filters = req->resc_request.num_mc_filters;
1210
1211 /* Fill agreed size of bulletin board in response */
1212 resp->bulletin_size = vf->bulletin.size;
Yuval Mintz36558c32016-05-11 16:36:17 +03001213 qed_iov_post_vf_bulletin(p_hwfn, vf->relative_vf_id, p_ptt);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001214
1215 DP_VERBOSE(p_hwfn,
1216 QED_MSG_IOV,
1217 "VF[%d] ACQUIRE_RESPONSE: pfdev_info- chip_num=0x%x, db_size=%d, idx_per_sb=%d, pf_cap=0x%llx\n"
1218 "resources- n_rxq-%d, n_txq-%d, n_sbs-%d, n_macs-%d, n_vlans-%d\n",
1219 vf->abs_vf_id,
1220 resp->pfdev_info.chip_num,
1221 resp->pfdev_info.db_size,
1222 resp->pfdev_info.indices_per_sb,
1223 resp->pfdev_info.capabilities,
1224 resc->num_rxqs,
1225 resc->num_txqs,
1226 resc->num_sbs,
1227 resc->num_mac_filters,
1228 resc->num_vlan_filters);
1229 vf->state = VF_ACQUIRED;
1230
1231 /* Prepare Response */
1232out:
1233 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_ACQUIRE,
1234 sizeof(struct pfvf_acquire_resp_tlv), vfpf_status);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001235}
1236
Yuval Mintz08feecd2016-05-11 16:36:20 +03001237static int qed_iov_reconfigure_unicast_vlan(struct qed_hwfn *p_hwfn,
1238 struct qed_vf_info *p_vf)
1239{
1240 struct qed_filter_ucast filter;
1241 int rc = 0;
1242 int i;
1243
1244 memset(&filter, 0, sizeof(filter));
1245 filter.is_rx_filter = 1;
1246 filter.is_tx_filter = 1;
1247 filter.vport_to_add_to = p_vf->vport_id;
1248 filter.opcode = QED_FILTER_ADD;
1249
1250 /* Reconfigure vlans */
1251 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++) {
1252 if (!p_vf->shadow_config.vlans[i].used)
1253 continue;
1254
1255 filter.type = QED_FILTER_VLAN;
1256 filter.vlan = p_vf->shadow_config.vlans[i].vid;
1257 DP_VERBOSE(p_hwfn,
1258 QED_MSG_IOV,
1259 "Reconfiguring VLAN [0x%04x] for VF [%04x]\n",
1260 filter.vlan, p_vf->relative_vf_id);
1261 rc = qed_sp_eth_filter_ucast(p_hwfn,
1262 p_vf->opaque_fid,
1263 &filter,
1264 QED_SPQ_MODE_CB, NULL);
1265 if (rc) {
1266 DP_NOTICE(p_hwfn,
1267 "Failed to configure VLAN [%04x] to VF [%04x]\n",
1268 filter.vlan, p_vf->relative_vf_id);
1269 break;
1270 }
1271 }
1272
1273 return rc;
1274}
1275
1276static int
1277qed_iov_reconfigure_unicast_shadow(struct qed_hwfn *p_hwfn,
1278 struct qed_vf_info *p_vf, u64 events)
1279{
1280 int rc = 0;
1281
1282 if ((events & (1 << VLAN_ADDR_FORCED)) &&
1283 !(p_vf->configured_features & (1 << VLAN_ADDR_FORCED)))
1284 rc = qed_iov_reconfigure_unicast_vlan(p_hwfn, p_vf);
1285
1286 return rc;
1287}
1288
1289static int qed_iov_configure_vport_forced(struct qed_hwfn *p_hwfn,
1290 struct qed_vf_info *p_vf, u64 events)
1291{
1292 int rc = 0;
1293 struct qed_filter_ucast filter;
1294
1295 if (!p_vf->vport_instance)
1296 return -EINVAL;
1297
Yuval Mintzeff16962016-05-11 16:36:21 +03001298 if (events & (1 << MAC_ADDR_FORCED)) {
1299 /* Since there's no way [currently] of removing the MAC,
1300 * we can always assume this means we need to force it.
1301 */
1302 memset(&filter, 0, sizeof(filter));
1303 filter.type = QED_FILTER_MAC;
1304 filter.opcode = QED_FILTER_REPLACE;
1305 filter.is_rx_filter = 1;
1306 filter.is_tx_filter = 1;
1307 filter.vport_to_add_to = p_vf->vport_id;
1308 ether_addr_copy(filter.mac, p_vf->bulletin.p_virt->mac);
1309
1310 rc = qed_sp_eth_filter_ucast(p_hwfn, p_vf->opaque_fid,
1311 &filter, QED_SPQ_MODE_CB, NULL);
1312 if (rc) {
1313 DP_NOTICE(p_hwfn,
1314 "PF failed to configure MAC for VF\n");
1315 return rc;
1316 }
1317
1318 p_vf->configured_features |= 1 << MAC_ADDR_FORCED;
1319 }
1320
Yuval Mintz08feecd2016-05-11 16:36:20 +03001321 if (events & (1 << VLAN_ADDR_FORCED)) {
1322 struct qed_sp_vport_update_params vport_update;
1323 u8 removal;
1324 int i;
1325
1326 memset(&filter, 0, sizeof(filter));
1327 filter.type = QED_FILTER_VLAN;
1328 filter.is_rx_filter = 1;
1329 filter.is_tx_filter = 1;
1330 filter.vport_to_add_to = p_vf->vport_id;
1331 filter.vlan = p_vf->bulletin.p_virt->pvid;
1332 filter.opcode = filter.vlan ? QED_FILTER_REPLACE :
1333 QED_FILTER_FLUSH;
1334
1335 /* Send the ramrod */
1336 rc = qed_sp_eth_filter_ucast(p_hwfn, p_vf->opaque_fid,
1337 &filter, QED_SPQ_MODE_CB, NULL);
1338 if (rc) {
1339 DP_NOTICE(p_hwfn,
1340 "PF failed to configure VLAN for VF\n");
1341 return rc;
1342 }
1343
1344 /* Update the default-vlan & silent vlan stripping */
1345 memset(&vport_update, 0, sizeof(vport_update));
1346 vport_update.opaque_fid = p_vf->opaque_fid;
1347 vport_update.vport_id = p_vf->vport_id;
1348 vport_update.update_default_vlan_enable_flg = 1;
1349 vport_update.default_vlan_enable_flg = filter.vlan ? 1 : 0;
1350 vport_update.update_default_vlan_flg = 1;
1351 vport_update.default_vlan = filter.vlan;
1352
1353 vport_update.update_inner_vlan_removal_flg = 1;
1354 removal = filter.vlan ? 1
1355 : p_vf->shadow_config.inner_vlan_removal;
1356 vport_update.inner_vlan_removal_flg = removal;
1357 vport_update.silent_vlan_removal_flg = filter.vlan ? 1 : 0;
1358 rc = qed_sp_vport_update(p_hwfn,
1359 &vport_update,
1360 QED_SPQ_MODE_EBLOCK, NULL);
1361 if (rc) {
1362 DP_NOTICE(p_hwfn,
1363 "PF failed to configure VF vport for vlan\n");
1364 return rc;
1365 }
1366
1367 /* Update all the Rx queues */
1368 for (i = 0; i < QED_MAX_VF_CHAINS_PER_PF; i++) {
1369 u16 qid;
1370
1371 if (!p_vf->vf_queues[i].rxq_active)
1372 continue;
1373
1374 qid = p_vf->vf_queues[i].fw_rx_qid;
1375
1376 rc = qed_sp_eth_rx_queues_update(p_hwfn, qid,
1377 1, 0, 1,
1378 QED_SPQ_MODE_EBLOCK,
1379 NULL);
1380 if (rc) {
1381 DP_NOTICE(p_hwfn,
1382 "Failed to send Rx update fo queue[0x%04x]\n",
1383 qid);
1384 return rc;
1385 }
1386 }
1387
1388 if (filter.vlan)
1389 p_vf->configured_features |= 1 << VLAN_ADDR_FORCED;
1390 else
1391 p_vf->configured_features &= ~(1 << VLAN_ADDR_FORCED);
1392 }
1393
1394 /* If forced features are terminated, we need to configure the shadow
1395 * configuration back again.
1396 */
1397 if (events)
1398 qed_iov_reconfigure_unicast_shadow(p_hwfn, p_vf, events);
1399
1400 return rc;
1401}
1402
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001403static void qed_iov_vf_mbx_start_vport(struct qed_hwfn *p_hwfn,
1404 struct qed_ptt *p_ptt,
1405 struct qed_vf_info *vf)
1406{
1407 struct qed_sp_vport_start_params params = { 0 };
1408 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1409 struct vfpf_vport_start_tlv *start;
1410 u8 status = PFVF_STATUS_SUCCESS;
1411 struct qed_vf_info *vf_info;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001412 u64 *p_bitmap;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001413 int sb_id;
1414 int rc;
1415
1416 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vf->relative_vf_id, true);
1417 if (!vf_info) {
1418 DP_NOTICE(p_hwfn->cdev,
1419 "Failed to get VF info, invalid vfid [%d]\n",
1420 vf->relative_vf_id);
1421 return;
1422 }
1423
1424 vf->state = VF_ENABLED;
1425 start = &mbx->req_virt->start_vport;
1426
1427 /* Initialize Status block in CAU */
1428 for (sb_id = 0; sb_id < vf->num_sbs; sb_id++) {
1429 if (!start->sb_addr[sb_id]) {
1430 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1431 "VF[%d] did not fill the address of SB %d\n",
1432 vf->relative_vf_id, sb_id);
1433 break;
1434 }
1435
1436 qed_int_cau_conf_sb(p_hwfn, p_ptt,
1437 start->sb_addr[sb_id],
1438 vf->igu_sbs[sb_id],
1439 vf->abs_vf_id, 1);
1440 }
1441 qed_iov_enable_vf_traffic(p_hwfn, p_ptt, vf);
1442
1443 vf->mtu = start->mtu;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001444 vf->shadow_config.inner_vlan_removal = start->inner_vlan_removal;
1445
1446 /* Take into consideration configuration forced by hypervisor;
1447 * If none is configured, use the supplied VF values [for old
1448 * vfs that would still be fine, since they passed '0' as padding].
1449 */
1450 p_bitmap = &vf_info->bulletin.p_virt->valid_bitmap;
1451 if (!(*p_bitmap & (1 << VFPF_BULLETIN_UNTAGGED_DEFAULT_FORCED))) {
1452 u8 vf_req = start->only_untagged;
1453
1454 vf_info->bulletin.p_virt->default_only_untagged = vf_req;
1455 *p_bitmap |= 1 << VFPF_BULLETIN_UNTAGGED_DEFAULT;
1456 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001457
1458 params.tpa_mode = start->tpa_mode;
1459 params.remove_inner_vlan = start->inner_vlan_removal;
1460
Yuval Mintz08feecd2016-05-11 16:36:20 +03001461 params.only_untagged = vf_info->bulletin.p_virt->default_only_untagged;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001462 params.drop_ttl0 = false;
1463 params.concrete_fid = vf->concrete_fid;
1464 params.opaque_fid = vf->opaque_fid;
1465 params.vport_id = vf->vport_id;
1466 params.max_buffers_per_cqe = start->max_buffers_per_cqe;
1467 params.mtu = vf->mtu;
1468
1469 rc = qed_sp_eth_vport_start(p_hwfn, &params);
1470 if (rc != 0) {
1471 DP_ERR(p_hwfn,
1472 "qed_iov_vf_mbx_start_vport returned error %d\n", rc);
1473 status = PFVF_STATUS_FAILURE;
1474 } else {
1475 vf->vport_instance++;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001476
1477 /* Force configuration if needed on the newly opened vport */
1478 qed_iov_configure_vport_forced(p_hwfn, vf, *p_bitmap);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001479 }
1480 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_VPORT_START,
1481 sizeof(struct pfvf_def_resp_tlv), status);
1482}
1483
1484static void qed_iov_vf_mbx_stop_vport(struct qed_hwfn *p_hwfn,
1485 struct qed_ptt *p_ptt,
1486 struct qed_vf_info *vf)
1487{
1488 u8 status = PFVF_STATUS_SUCCESS;
1489 int rc;
1490
1491 vf->vport_instance--;
1492
1493 rc = qed_sp_vport_stop(p_hwfn, vf->opaque_fid, vf->vport_id);
1494 if (rc != 0) {
1495 DP_ERR(p_hwfn, "qed_iov_vf_mbx_stop_vport returned error %d\n",
1496 rc);
1497 status = PFVF_STATUS_FAILURE;
1498 }
1499
Yuval Mintz08feecd2016-05-11 16:36:20 +03001500 /* Forget the configuration on the vport */
1501 vf->configured_features = 0;
1502 memset(&vf->shadow_config, 0, sizeof(vf->shadow_config));
1503
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001504 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_VPORT_TEARDOWN,
1505 sizeof(struct pfvf_def_resp_tlv), status);
1506}
1507
1508#define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
1509#define MSTORM_QZONE_START(dev) (TSTORM_QZONE_START + \
1510 (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
1511
1512static void qed_iov_vf_mbx_start_rxq_resp(struct qed_hwfn *p_hwfn,
1513 struct qed_ptt *p_ptt,
1514 struct qed_vf_info *vf, u8 status)
1515{
1516 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1517 struct pfvf_start_queue_resp_tlv *p_tlv;
1518 struct vfpf_start_rxq_tlv *req;
1519
1520 mbx->offset = (u8 *)mbx->reply_virt;
1521
1522 p_tlv = qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_START_RXQ,
1523 sizeof(*p_tlv));
1524 qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_LIST_END,
1525 sizeof(struct channel_list_end_tlv));
1526
1527 /* Update the TLV with the response */
1528 if (status == PFVF_STATUS_SUCCESS) {
1529 u16 hw_qid = 0;
1530
1531 req = &mbx->req_virt->start_rxq;
1532 qed_fw_l2_queue(p_hwfn, vf->vf_queues[req->rx_qid].fw_rx_qid,
1533 &hw_qid);
1534
1535 p_tlv->offset = MSTORM_QZONE_START(p_hwfn->cdev) +
1536 hw_qid * MSTORM_QZONE_SIZE +
1537 offsetof(struct mstorm_eth_queue_zone,
1538 rx_producers);
1539 }
1540
1541 qed_iov_send_response(p_hwfn, p_ptt, vf, sizeof(*p_tlv), status);
1542}
1543
1544static void qed_iov_vf_mbx_start_rxq(struct qed_hwfn *p_hwfn,
1545 struct qed_ptt *p_ptt,
1546 struct qed_vf_info *vf)
1547{
1548 struct qed_queue_start_common_params params;
1549 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1550 u8 status = PFVF_STATUS_SUCCESS;
1551 struct vfpf_start_rxq_tlv *req;
1552 int rc;
1553
1554 memset(&params, 0, sizeof(params));
1555 req = &mbx->req_virt->start_rxq;
1556 params.queue_id = vf->vf_queues[req->rx_qid].fw_rx_qid;
1557 params.vport_id = vf->vport_id;
1558 params.sb = req->hw_sb;
1559 params.sb_idx = req->sb_index;
1560
1561 rc = qed_sp_eth_rxq_start_ramrod(p_hwfn, vf->opaque_fid,
1562 vf->vf_queues[req->rx_qid].fw_cid,
1563 &params,
1564 vf->abs_vf_id + 0x10,
1565 req->bd_max_bytes,
1566 req->rxq_addr,
1567 req->cqe_pbl_addr, req->cqe_pbl_size);
1568
1569 if (rc) {
1570 status = PFVF_STATUS_FAILURE;
1571 } else {
1572 vf->vf_queues[req->rx_qid].rxq_active = true;
1573 vf->num_active_rxqs++;
1574 }
1575
1576 qed_iov_vf_mbx_start_rxq_resp(p_hwfn, p_ptt, vf, status);
1577}
1578
1579static void qed_iov_vf_mbx_start_txq(struct qed_hwfn *p_hwfn,
1580 struct qed_ptt *p_ptt,
1581 struct qed_vf_info *vf)
1582{
1583 u16 length = sizeof(struct pfvf_def_resp_tlv);
1584 struct qed_queue_start_common_params params;
1585 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1586 union qed_qm_pq_params pq_params;
1587 u8 status = PFVF_STATUS_SUCCESS;
1588 struct vfpf_start_txq_tlv *req;
1589 int rc;
1590
1591 /* Prepare the parameters which would choose the right PQ */
1592 memset(&pq_params, 0, sizeof(pq_params));
1593 pq_params.eth.is_vf = 1;
1594 pq_params.eth.vf_id = vf->relative_vf_id;
1595
1596 memset(&params, 0, sizeof(params));
1597 req = &mbx->req_virt->start_txq;
1598 params.queue_id = vf->vf_queues[req->tx_qid].fw_tx_qid;
1599 params.vport_id = vf->vport_id;
1600 params.sb = req->hw_sb;
1601 params.sb_idx = req->sb_index;
1602
1603 rc = qed_sp_eth_txq_start_ramrod(p_hwfn,
1604 vf->opaque_fid,
1605 vf->vf_queues[req->tx_qid].fw_cid,
1606 &params,
1607 vf->abs_vf_id + 0x10,
1608 req->pbl_addr,
1609 req->pbl_size, &pq_params);
1610
1611 if (rc)
1612 status = PFVF_STATUS_FAILURE;
1613 else
1614 vf->vf_queues[req->tx_qid].txq_active = true;
1615
1616 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_START_TXQ,
1617 length, status);
1618}
1619
1620static int qed_iov_vf_stop_rxqs(struct qed_hwfn *p_hwfn,
1621 struct qed_vf_info *vf,
1622 u16 rxq_id, u8 num_rxqs, bool cqe_completion)
1623{
1624 int rc = 0;
1625 int qid;
1626
1627 if (rxq_id + num_rxqs > ARRAY_SIZE(vf->vf_queues))
1628 return -EINVAL;
1629
1630 for (qid = rxq_id; qid < rxq_id + num_rxqs; qid++) {
1631 if (vf->vf_queues[qid].rxq_active) {
1632 rc = qed_sp_eth_rx_queue_stop(p_hwfn,
1633 vf->vf_queues[qid].
1634 fw_rx_qid, false,
1635 cqe_completion);
1636
1637 if (rc)
1638 return rc;
1639 }
1640 vf->vf_queues[qid].rxq_active = false;
1641 vf->num_active_rxqs--;
1642 }
1643
1644 return rc;
1645}
1646
1647static int qed_iov_vf_stop_txqs(struct qed_hwfn *p_hwfn,
1648 struct qed_vf_info *vf, u16 txq_id, u8 num_txqs)
1649{
1650 int rc = 0;
1651 int qid;
1652
1653 if (txq_id + num_txqs > ARRAY_SIZE(vf->vf_queues))
1654 return -EINVAL;
1655
1656 for (qid = txq_id; qid < txq_id + num_txqs; qid++) {
1657 if (vf->vf_queues[qid].txq_active) {
1658 rc = qed_sp_eth_tx_queue_stop(p_hwfn,
1659 vf->vf_queues[qid].
1660 fw_tx_qid);
1661
1662 if (rc)
1663 return rc;
1664 }
1665 vf->vf_queues[qid].txq_active = false;
1666 }
1667 return rc;
1668}
1669
1670static void qed_iov_vf_mbx_stop_rxqs(struct qed_hwfn *p_hwfn,
1671 struct qed_ptt *p_ptt,
1672 struct qed_vf_info *vf)
1673{
1674 u16 length = sizeof(struct pfvf_def_resp_tlv);
1675 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1676 u8 status = PFVF_STATUS_SUCCESS;
1677 struct vfpf_stop_rxqs_tlv *req;
1678 int rc;
1679
1680 /* We give the option of starting from qid != 0, in this case we
1681 * need to make sure that qid + num_qs doesn't exceed the actual
1682 * amount of queues that exist.
1683 */
1684 req = &mbx->req_virt->stop_rxqs;
1685 rc = qed_iov_vf_stop_rxqs(p_hwfn, vf, req->rx_qid,
1686 req->num_rxqs, req->cqe_completion);
1687 if (rc)
1688 status = PFVF_STATUS_FAILURE;
1689
1690 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_STOP_RXQS,
1691 length, status);
1692}
1693
1694static void qed_iov_vf_mbx_stop_txqs(struct qed_hwfn *p_hwfn,
1695 struct qed_ptt *p_ptt,
1696 struct qed_vf_info *vf)
1697{
1698 u16 length = sizeof(struct pfvf_def_resp_tlv);
1699 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1700 u8 status = PFVF_STATUS_SUCCESS;
1701 struct vfpf_stop_txqs_tlv *req;
1702 int rc;
1703
1704 /* We give the option of starting from qid != 0, in this case we
1705 * need to make sure that qid + num_qs doesn't exceed the actual
1706 * amount of queues that exist.
1707 */
1708 req = &mbx->req_virt->stop_txqs;
1709 rc = qed_iov_vf_stop_txqs(p_hwfn, vf, req->tx_qid, req->num_txqs);
1710 if (rc)
1711 status = PFVF_STATUS_FAILURE;
1712
1713 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_STOP_TXQS,
1714 length, status);
1715}
1716
Yuval Mintz17b235c2016-05-11 16:36:18 +03001717static void qed_iov_vf_mbx_update_rxqs(struct qed_hwfn *p_hwfn,
1718 struct qed_ptt *p_ptt,
1719 struct qed_vf_info *vf)
1720{
1721 u16 length = sizeof(struct pfvf_def_resp_tlv);
1722 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1723 struct vfpf_update_rxq_tlv *req;
1724 u8 status = PFVF_STATUS_SUCCESS;
1725 u8 complete_event_flg;
1726 u8 complete_cqe_flg;
1727 u16 qid;
1728 int rc;
1729 u8 i;
1730
1731 req = &mbx->req_virt->update_rxq;
1732 complete_cqe_flg = !!(req->flags & VFPF_RXQ_UPD_COMPLETE_CQE_FLAG);
1733 complete_event_flg = !!(req->flags & VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG);
1734
1735 for (i = 0; i < req->num_rxqs; i++) {
1736 qid = req->rx_qid + i;
1737
1738 if (!vf->vf_queues[qid].rxq_active) {
1739 DP_NOTICE(p_hwfn, "VF rx_qid = %d isn`t active!\n",
1740 qid);
1741 status = PFVF_STATUS_FAILURE;
1742 break;
1743 }
1744
1745 rc = qed_sp_eth_rx_queues_update(p_hwfn,
1746 vf->vf_queues[qid].fw_rx_qid,
1747 1,
1748 complete_cqe_flg,
1749 complete_event_flg,
1750 QED_SPQ_MODE_EBLOCK, NULL);
1751
1752 if (rc) {
1753 status = PFVF_STATUS_FAILURE;
1754 break;
1755 }
1756 }
1757
1758 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_UPDATE_RXQ,
1759 length, status);
1760}
1761
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001762void *qed_iov_search_list_tlvs(struct qed_hwfn *p_hwfn,
1763 void *p_tlvs_list, u16 req_type)
1764{
1765 struct channel_tlv *p_tlv = (struct channel_tlv *)p_tlvs_list;
1766 int len = 0;
1767
1768 do {
1769 if (!p_tlv->length) {
1770 DP_NOTICE(p_hwfn, "Zero length TLV found\n");
1771 return NULL;
1772 }
1773
1774 if (p_tlv->type == req_type) {
1775 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1776 "Extended tlv type %d, length %d found\n",
1777 p_tlv->type, p_tlv->length);
1778 return p_tlv;
1779 }
1780
1781 len += p_tlv->length;
1782 p_tlv = (struct channel_tlv *)((u8 *)p_tlv + p_tlv->length);
1783
1784 if ((len + p_tlv->length) > TLV_BUFFER_SIZE) {
1785 DP_NOTICE(p_hwfn, "TLVs has overrun the buffer size\n");
1786 return NULL;
1787 }
1788 } while (p_tlv->type != CHANNEL_TLV_LIST_END);
1789
1790 return NULL;
1791}
1792
1793static void
1794qed_iov_vp_update_act_param(struct qed_hwfn *p_hwfn,
1795 struct qed_sp_vport_update_params *p_data,
1796 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
1797{
1798 struct vfpf_vport_update_activate_tlv *p_act_tlv;
1799 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
1800
1801 p_act_tlv = (struct vfpf_vport_update_activate_tlv *)
1802 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
1803 if (!p_act_tlv)
1804 return;
1805
1806 p_data->update_vport_active_rx_flg = p_act_tlv->update_rx;
1807 p_data->vport_active_rx_flg = p_act_tlv->active_rx;
1808 p_data->update_vport_active_tx_flg = p_act_tlv->update_tx;
1809 p_data->vport_active_tx_flg = p_act_tlv->active_tx;
1810 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_ACTIVATE;
1811}
1812
1813static void
Yuval Mintz17b235c2016-05-11 16:36:18 +03001814qed_iov_vp_update_vlan_param(struct qed_hwfn *p_hwfn,
1815 struct qed_sp_vport_update_params *p_data,
1816 struct qed_vf_info *p_vf,
1817 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
1818{
1819 struct vfpf_vport_update_vlan_strip_tlv *p_vlan_tlv;
1820 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP;
1821
1822 p_vlan_tlv = (struct vfpf_vport_update_vlan_strip_tlv *)
1823 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
1824 if (!p_vlan_tlv)
1825 return;
1826
Yuval Mintz08feecd2016-05-11 16:36:20 +03001827 p_vf->shadow_config.inner_vlan_removal = p_vlan_tlv->remove_vlan;
1828
1829 /* Ignore the VF request if we're forcing a vlan */
1830 if (!(p_vf->configured_features & (1 << VLAN_ADDR_FORCED))) {
1831 p_data->update_inner_vlan_removal_flg = 1;
1832 p_data->inner_vlan_removal_flg = p_vlan_tlv->remove_vlan;
1833 }
Yuval Mintz17b235c2016-05-11 16:36:18 +03001834
1835 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_VLAN_STRIP;
1836}
1837
1838static void
1839qed_iov_vp_update_tx_switch(struct qed_hwfn *p_hwfn,
1840 struct qed_sp_vport_update_params *p_data,
1841 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
1842{
1843 struct vfpf_vport_update_tx_switch_tlv *p_tx_switch_tlv;
1844 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
1845
1846 p_tx_switch_tlv = (struct vfpf_vport_update_tx_switch_tlv *)
1847 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt,
1848 tlv);
1849 if (!p_tx_switch_tlv)
1850 return;
1851
1852 p_data->update_tx_switching_flg = 1;
1853 p_data->tx_switching_flg = p_tx_switch_tlv->tx_switching;
1854 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_TX_SWITCH;
1855}
1856
1857static void
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001858qed_iov_vp_update_mcast_bin_param(struct qed_hwfn *p_hwfn,
1859 struct qed_sp_vport_update_params *p_data,
1860 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
1861{
1862 struct vfpf_vport_update_mcast_bin_tlv *p_mcast_tlv;
1863 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_MCAST;
1864
1865 p_mcast_tlv = (struct vfpf_vport_update_mcast_bin_tlv *)
1866 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
1867 if (!p_mcast_tlv)
1868 return;
1869
1870 p_data->update_approx_mcast_flg = 1;
1871 memcpy(p_data->bins, p_mcast_tlv->bins,
1872 sizeof(unsigned long) * ETH_MULTICAST_MAC_BINS_IN_REGS);
1873 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_MCAST;
1874}
1875
1876static void
1877qed_iov_vp_update_accept_flag(struct qed_hwfn *p_hwfn,
1878 struct qed_sp_vport_update_params *p_data,
1879 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
1880{
1881 struct qed_filter_accept_flags *p_flags = &p_data->accept_flags;
1882 struct vfpf_vport_update_accept_param_tlv *p_accept_tlv;
1883 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
1884
1885 p_accept_tlv = (struct vfpf_vport_update_accept_param_tlv *)
1886 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
1887 if (!p_accept_tlv)
1888 return;
1889
1890 p_flags->update_rx_mode_config = p_accept_tlv->update_rx_mode;
1891 p_flags->rx_accept_filter = p_accept_tlv->rx_accept_filter;
1892 p_flags->update_tx_mode_config = p_accept_tlv->update_tx_mode;
1893 p_flags->tx_accept_filter = p_accept_tlv->tx_accept_filter;
1894 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_ACCEPT_PARAM;
1895}
1896
1897static void
Yuval Mintz17b235c2016-05-11 16:36:18 +03001898qed_iov_vp_update_accept_any_vlan(struct qed_hwfn *p_hwfn,
1899 struct qed_sp_vport_update_params *p_data,
1900 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
1901{
1902 struct vfpf_vport_update_accept_any_vlan_tlv *p_accept_any_vlan;
1903 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
1904
1905 p_accept_any_vlan = (struct vfpf_vport_update_accept_any_vlan_tlv *)
1906 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt,
1907 tlv);
1908 if (!p_accept_any_vlan)
1909 return;
1910
1911 p_data->accept_any_vlan = p_accept_any_vlan->accept_any_vlan;
1912 p_data->update_accept_any_vlan_flg =
1913 p_accept_any_vlan->update_accept_any_vlan_flg;
1914 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_ACCEPT_ANY_VLAN;
1915}
1916
1917static void
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001918qed_iov_vp_update_rss_param(struct qed_hwfn *p_hwfn,
1919 struct qed_vf_info *vf,
1920 struct qed_sp_vport_update_params *p_data,
1921 struct qed_rss_params *p_rss,
1922 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
1923{
1924 struct vfpf_vport_update_rss_tlv *p_rss_tlv;
1925 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_RSS;
1926 u16 i, q_idx, max_q_idx;
1927 u16 table_size;
1928
1929 p_rss_tlv = (struct vfpf_vport_update_rss_tlv *)
1930 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
1931 if (!p_rss_tlv) {
1932 p_data->rss_params = NULL;
1933 return;
1934 }
1935
1936 memset(p_rss, 0, sizeof(struct qed_rss_params));
1937
1938 p_rss->update_rss_config = !!(p_rss_tlv->update_rss_flags &
1939 VFPF_UPDATE_RSS_CONFIG_FLAG);
1940 p_rss->update_rss_capabilities = !!(p_rss_tlv->update_rss_flags &
1941 VFPF_UPDATE_RSS_CAPS_FLAG);
1942 p_rss->update_rss_ind_table = !!(p_rss_tlv->update_rss_flags &
1943 VFPF_UPDATE_RSS_IND_TABLE_FLAG);
1944 p_rss->update_rss_key = !!(p_rss_tlv->update_rss_flags &
1945 VFPF_UPDATE_RSS_KEY_FLAG);
1946
1947 p_rss->rss_enable = p_rss_tlv->rss_enable;
1948 p_rss->rss_eng_id = vf->relative_vf_id + 1;
1949 p_rss->rss_caps = p_rss_tlv->rss_caps;
1950 p_rss->rss_table_size_log = p_rss_tlv->rss_table_size_log;
1951 memcpy(p_rss->rss_ind_table, p_rss_tlv->rss_ind_table,
1952 sizeof(p_rss->rss_ind_table));
1953 memcpy(p_rss->rss_key, p_rss_tlv->rss_key, sizeof(p_rss->rss_key));
1954
1955 table_size = min_t(u16, ARRAY_SIZE(p_rss->rss_ind_table),
1956 (1 << p_rss_tlv->rss_table_size_log));
1957
1958 max_q_idx = ARRAY_SIZE(vf->vf_queues);
1959
1960 for (i = 0; i < table_size; i++) {
1961 u16 index = vf->vf_queues[0].fw_rx_qid;
1962
1963 q_idx = p_rss->rss_ind_table[i];
1964 if (q_idx >= max_q_idx)
1965 DP_NOTICE(p_hwfn,
1966 "rss_ind_table[%d] = %d, rxq is out of range\n",
1967 i, q_idx);
1968 else if (!vf->vf_queues[q_idx].rxq_active)
1969 DP_NOTICE(p_hwfn,
1970 "rss_ind_table[%d] = %d, rxq is not active\n",
1971 i, q_idx);
1972 else
1973 index = vf->vf_queues[q_idx].fw_rx_qid;
1974 p_rss->rss_ind_table[i] = index;
1975 }
1976
1977 p_data->rss_params = p_rss;
1978 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_RSS;
1979}
1980
Yuval Mintz17b235c2016-05-11 16:36:18 +03001981static void
1982qed_iov_vp_update_sge_tpa_param(struct qed_hwfn *p_hwfn,
1983 struct qed_vf_info *vf,
1984 struct qed_sp_vport_update_params *p_data,
1985 struct qed_sge_tpa_params *p_sge_tpa,
1986 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
1987{
1988 struct vfpf_vport_update_sge_tpa_tlv *p_sge_tpa_tlv;
1989 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_SGE_TPA;
1990
1991 p_sge_tpa_tlv = (struct vfpf_vport_update_sge_tpa_tlv *)
1992 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
1993
1994 if (!p_sge_tpa_tlv) {
1995 p_data->sge_tpa_params = NULL;
1996 return;
1997 }
1998
1999 memset(p_sge_tpa, 0, sizeof(struct qed_sge_tpa_params));
2000
2001 p_sge_tpa->update_tpa_en_flg =
2002 !!(p_sge_tpa_tlv->update_sge_tpa_flags & VFPF_UPDATE_TPA_EN_FLAG);
2003 p_sge_tpa->update_tpa_param_flg =
2004 !!(p_sge_tpa_tlv->update_sge_tpa_flags &
2005 VFPF_UPDATE_TPA_PARAM_FLAG);
2006
2007 p_sge_tpa->tpa_ipv4_en_flg =
2008 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_IPV4_EN_FLAG);
2009 p_sge_tpa->tpa_ipv6_en_flg =
2010 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_IPV6_EN_FLAG);
2011 p_sge_tpa->tpa_pkt_split_flg =
2012 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_PKT_SPLIT_FLAG);
2013 p_sge_tpa->tpa_hdr_data_split_flg =
2014 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_HDR_DATA_SPLIT_FLAG);
2015 p_sge_tpa->tpa_gro_consistent_flg =
2016 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_GRO_CONSIST_FLAG);
2017
2018 p_sge_tpa->tpa_max_aggs_num = p_sge_tpa_tlv->tpa_max_aggs_num;
2019 p_sge_tpa->tpa_max_size = p_sge_tpa_tlv->tpa_max_size;
2020 p_sge_tpa->tpa_min_size_to_start = p_sge_tpa_tlv->tpa_min_size_to_start;
2021 p_sge_tpa->tpa_min_size_to_cont = p_sge_tpa_tlv->tpa_min_size_to_cont;
2022 p_sge_tpa->max_buffers_per_cqe = p_sge_tpa_tlv->max_buffers_per_cqe;
2023
2024 p_data->sge_tpa_params = p_sge_tpa;
2025
2026 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_SGE_TPA;
2027}
2028
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002029static void qed_iov_vf_mbx_vport_update(struct qed_hwfn *p_hwfn,
2030 struct qed_ptt *p_ptt,
2031 struct qed_vf_info *vf)
2032{
2033 struct qed_sp_vport_update_params params;
2034 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
Yuval Mintz17b235c2016-05-11 16:36:18 +03002035 struct qed_sge_tpa_params sge_tpa_params;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002036 struct qed_rss_params rss_params;
2037 u8 status = PFVF_STATUS_SUCCESS;
2038 u16 tlvs_mask = 0;
2039 u16 length;
2040 int rc;
2041
2042 memset(&params, 0, sizeof(params));
2043 params.opaque_fid = vf->opaque_fid;
2044 params.vport_id = vf->vport_id;
2045 params.rss_params = NULL;
2046
2047 /* Search for extended tlvs list and update values
2048 * from VF in struct qed_sp_vport_update_params.
2049 */
2050 qed_iov_vp_update_act_param(p_hwfn, &params, mbx, &tlvs_mask);
Yuval Mintz17b235c2016-05-11 16:36:18 +03002051 qed_iov_vp_update_vlan_param(p_hwfn, &params, vf, mbx, &tlvs_mask);
2052 qed_iov_vp_update_tx_switch(p_hwfn, &params, mbx, &tlvs_mask);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002053 qed_iov_vp_update_mcast_bin_param(p_hwfn, &params, mbx, &tlvs_mask);
2054 qed_iov_vp_update_accept_flag(p_hwfn, &params, mbx, &tlvs_mask);
2055 qed_iov_vp_update_rss_param(p_hwfn, vf, &params, &rss_params,
2056 mbx, &tlvs_mask);
Yuval Mintz17b235c2016-05-11 16:36:18 +03002057 qed_iov_vp_update_accept_any_vlan(p_hwfn, &params, mbx, &tlvs_mask);
2058 qed_iov_vp_update_sge_tpa_param(p_hwfn, vf, &params,
2059 &sge_tpa_params, mbx, &tlvs_mask);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002060
2061 /* Just log a message if there is no single extended tlv in buffer.
2062 * When all features of vport update ramrod would be requested by VF
2063 * as extended TLVs in buffer then an error can be returned in response
2064 * if there is no extended TLV present in buffer.
2065 */
2066 if (!tlvs_mask) {
2067 DP_NOTICE(p_hwfn,
2068 "No feature tlvs found for vport update\n");
2069 status = PFVF_STATUS_NOT_SUPPORTED;
2070 goto out;
2071 }
2072
2073 rc = qed_sp_vport_update(p_hwfn, &params, QED_SPQ_MODE_EBLOCK, NULL);
2074
2075 if (rc)
2076 status = PFVF_STATUS_FAILURE;
2077
2078out:
2079 length = qed_iov_prep_vp_update_resp_tlvs(p_hwfn, vf, mbx, status,
2080 tlvs_mask, tlvs_mask);
2081 qed_iov_send_response(p_hwfn, p_ptt, vf, length, status);
2082}
2083
Yuval Mintz08feecd2016-05-11 16:36:20 +03002084static int qed_iov_vf_update_unicast_shadow(struct qed_hwfn *p_hwfn,
2085 struct qed_vf_info *p_vf,
2086 struct qed_filter_ucast *p_params)
2087{
2088 int i;
2089
2090 if (p_params->type == QED_FILTER_MAC)
2091 return 0;
2092
2093 /* First remove entries and then add new ones */
2094 if (p_params->opcode == QED_FILTER_REMOVE) {
2095 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++)
2096 if (p_vf->shadow_config.vlans[i].used &&
2097 p_vf->shadow_config.vlans[i].vid ==
2098 p_params->vlan) {
2099 p_vf->shadow_config.vlans[i].used = false;
2100 break;
2101 }
2102 if (i == QED_ETH_VF_NUM_VLAN_FILTERS + 1) {
2103 DP_VERBOSE(p_hwfn,
2104 QED_MSG_IOV,
2105 "VF [%d] - Tries to remove a non-existing vlan\n",
2106 p_vf->relative_vf_id);
2107 return -EINVAL;
2108 }
2109 } else if (p_params->opcode == QED_FILTER_REPLACE ||
2110 p_params->opcode == QED_FILTER_FLUSH) {
2111 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++)
2112 p_vf->shadow_config.vlans[i].used = false;
2113 }
2114
2115 /* In forced mode, we're willing to remove entries - but we don't add
2116 * new ones.
2117 */
2118 if (p_vf->bulletin.p_virt->valid_bitmap & (1 << VLAN_ADDR_FORCED))
2119 return 0;
2120
2121 if (p_params->opcode == QED_FILTER_ADD ||
2122 p_params->opcode == QED_FILTER_REPLACE) {
2123 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++) {
2124 if (p_vf->shadow_config.vlans[i].used)
2125 continue;
2126
2127 p_vf->shadow_config.vlans[i].used = true;
2128 p_vf->shadow_config.vlans[i].vid = p_params->vlan;
2129 break;
2130 }
2131
2132 if (i == QED_ETH_VF_NUM_VLAN_FILTERS + 1) {
2133 DP_VERBOSE(p_hwfn,
2134 QED_MSG_IOV,
2135 "VF [%d] - Tries to configure more than %d vlan filters\n",
2136 p_vf->relative_vf_id,
2137 QED_ETH_VF_NUM_VLAN_FILTERS + 1);
2138 return -EINVAL;
2139 }
2140 }
2141
2142 return 0;
2143}
2144
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002145int qed_iov_chk_ucast(struct qed_hwfn *hwfn,
2146 int vfid, struct qed_filter_ucast *params)
2147{
2148 struct qed_public_vf_info *vf;
2149
2150 vf = qed_iov_get_public_vf_info(hwfn, vfid, true);
2151 if (!vf)
2152 return -EINVAL;
2153
2154 /* No real decision to make; Store the configured MAC */
2155 if (params->type == QED_FILTER_MAC ||
2156 params->type == QED_FILTER_MAC_VLAN)
2157 ether_addr_copy(vf->mac, params->mac);
2158
2159 return 0;
2160}
2161
2162static void qed_iov_vf_mbx_ucast_filter(struct qed_hwfn *p_hwfn,
2163 struct qed_ptt *p_ptt,
2164 struct qed_vf_info *vf)
2165{
Yuval Mintz08feecd2016-05-11 16:36:20 +03002166 struct qed_bulletin_content *p_bulletin = vf->bulletin.p_virt;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002167 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
2168 struct vfpf_ucast_filter_tlv *req;
2169 u8 status = PFVF_STATUS_SUCCESS;
2170 struct qed_filter_ucast params;
2171 int rc;
2172
2173 /* Prepare the unicast filter params */
2174 memset(&params, 0, sizeof(struct qed_filter_ucast));
2175 req = &mbx->req_virt->ucast_filter;
2176 params.opcode = (enum qed_filter_opcode)req->opcode;
2177 params.type = (enum qed_filter_ucast_type)req->type;
2178
2179 params.is_rx_filter = 1;
2180 params.is_tx_filter = 1;
2181 params.vport_to_remove_from = vf->vport_id;
2182 params.vport_to_add_to = vf->vport_id;
2183 memcpy(params.mac, req->mac, ETH_ALEN);
2184 params.vlan = req->vlan;
2185
2186 DP_VERBOSE(p_hwfn,
2187 QED_MSG_IOV,
2188 "VF[%d]: opcode 0x%02x type 0x%02x [%s %s] [vport 0x%02x] MAC %02x:%02x:%02x:%02x:%02x:%02x, vlan 0x%04x\n",
2189 vf->abs_vf_id, params.opcode, params.type,
2190 params.is_rx_filter ? "RX" : "",
2191 params.is_tx_filter ? "TX" : "",
2192 params.vport_to_add_to,
2193 params.mac[0], params.mac[1],
2194 params.mac[2], params.mac[3],
2195 params.mac[4], params.mac[5], params.vlan);
2196
2197 if (!vf->vport_instance) {
2198 DP_VERBOSE(p_hwfn,
2199 QED_MSG_IOV,
2200 "No VPORT instance available for VF[%d], failing ucast MAC configuration\n",
2201 vf->abs_vf_id);
2202 status = PFVF_STATUS_FAILURE;
2203 goto out;
2204 }
2205
Yuval Mintz08feecd2016-05-11 16:36:20 +03002206 /* Update shadow copy of the VF configuration */
2207 if (qed_iov_vf_update_unicast_shadow(p_hwfn, vf, &params)) {
2208 status = PFVF_STATUS_FAILURE;
2209 goto out;
2210 }
2211
2212 /* Determine if the unicast filtering is acceptible by PF */
2213 if ((p_bulletin->valid_bitmap & (1 << VLAN_ADDR_FORCED)) &&
2214 (params.type == QED_FILTER_VLAN ||
2215 params.type == QED_FILTER_MAC_VLAN)) {
2216 /* Once VLAN is forced or PVID is set, do not allow
2217 * to add/replace any further VLANs.
2218 */
2219 if (params.opcode == QED_FILTER_ADD ||
2220 params.opcode == QED_FILTER_REPLACE)
2221 status = PFVF_STATUS_FORCED;
2222 goto out;
2223 }
2224
Yuval Mintzeff16962016-05-11 16:36:21 +03002225 if ((p_bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)) &&
2226 (params.type == QED_FILTER_MAC ||
2227 params.type == QED_FILTER_MAC_VLAN)) {
2228 if (!ether_addr_equal(p_bulletin->mac, params.mac) ||
2229 (params.opcode != QED_FILTER_ADD &&
2230 params.opcode != QED_FILTER_REPLACE))
2231 status = PFVF_STATUS_FORCED;
2232 goto out;
2233 }
2234
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002235 rc = qed_iov_chk_ucast(p_hwfn, vf->relative_vf_id, &params);
2236 if (rc) {
2237 status = PFVF_STATUS_FAILURE;
2238 goto out;
2239 }
2240
2241 rc = qed_sp_eth_filter_ucast(p_hwfn, vf->opaque_fid, &params,
2242 QED_SPQ_MODE_CB, NULL);
2243 if (rc)
2244 status = PFVF_STATUS_FAILURE;
2245
2246out:
2247 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_UCAST_FILTER,
2248 sizeof(struct pfvf_def_resp_tlv), status);
2249}
2250
Yuval Mintz0b55e272016-05-11 16:36:15 +03002251static void qed_iov_vf_mbx_int_cleanup(struct qed_hwfn *p_hwfn,
2252 struct qed_ptt *p_ptt,
2253 struct qed_vf_info *vf)
2254{
2255 int i;
2256
2257 /* Reset the SBs */
2258 for (i = 0; i < vf->num_sbs; i++)
2259 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2260 vf->igu_sbs[i],
2261 vf->opaque_fid, false);
2262
2263 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_INT_CLEANUP,
2264 sizeof(struct pfvf_def_resp_tlv),
2265 PFVF_STATUS_SUCCESS);
2266}
2267
2268static void qed_iov_vf_mbx_close(struct qed_hwfn *p_hwfn,
2269 struct qed_ptt *p_ptt, struct qed_vf_info *vf)
2270{
2271 u16 length = sizeof(struct pfvf_def_resp_tlv);
2272 u8 status = PFVF_STATUS_SUCCESS;
2273
2274 /* Disable Interrupts for VF */
2275 qed_iov_vf_igu_set_int(p_hwfn, p_ptt, vf, 0);
2276
2277 /* Reset Permission table */
2278 qed_iov_config_perm_table(p_hwfn, p_ptt, vf, 0);
2279
2280 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_CLOSE,
2281 length, status);
2282}
2283
2284static void qed_iov_vf_mbx_release(struct qed_hwfn *p_hwfn,
2285 struct qed_ptt *p_ptt,
2286 struct qed_vf_info *p_vf)
2287{
2288 u16 length = sizeof(struct pfvf_def_resp_tlv);
2289
2290 qed_iov_vf_cleanup(p_hwfn, p_vf);
2291
2292 qed_iov_prepare_resp(p_hwfn, p_ptt, p_vf, CHANNEL_TLV_RELEASE,
2293 length, PFVF_STATUS_SUCCESS);
2294}
2295
2296static int
2297qed_iov_vf_flr_poll_dorq(struct qed_hwfn *p_hwfn,
2298 struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
2299{
2300 int cnt;
2301 u32 val;
2302
2303 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_vf->concrete_fid);
2304
2305 for (cnt = 0; cnt < 50; cnt++) {
2306 val = qed_rd(p_hwfn, p_ptt, DORQ_REG_VF_USAGE_CNT);
2307 if (!val)
2308 break;
2309 msleep(20);
2310 }
2311 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
2312
2313 if (cnt == 50) {
2314 DP_ERR(p_hwfn,
2315 "VF[%d] - dorq failed to cleanup [usage 0x%08x]\n",
2316 p_vf->abs_vf_id, val);
2317 return -EBUSY;
2318 }
2319
2320 return 0;
2321}
2322
2323static int
2324qed_iov_vf_flr_poll_pbf(struct qed_hwfn *p_hwfn,
2325 struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
2326{
2327 u32 cons[MAX_NUM_VOQS], distance[MAX_NUM_VOQS];
2328 int i, cnt;
2329
2330 /* Read initial consumers & producers */
2331 for (i = 0; i < MAX_NUM_VOQS; i++) {
2332 u32 prod;
2333
2334 cons[i] = qed_rd(p_hwfn, p_ptt,
2335 PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 +
2336 i * 0x40);
2337 prod = qed_rd(p_hwfn, p_ptt,
2338 PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 +
2339 i * 0x40);
2340 distance[i] = prod - cons[i];
2341 }
2342
2343 /* Wait for consumers to pass the producers */
2344 i = 0;
2345 for (cnt = 0; cnt < 50; cnt++) {
2346 for (; i < MAX_NUM_VOQS; i++) {
2347 u32 tmp;
2348
2349 tmp = qed_rd(p_hwfn, p_ptt,
2350 PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 +
2351 i * 0x40);
2352 if (distance[i] > tmp - cons[i])
2353 break;
2354 }
2355
2356 if (i == MAX_NUM_VOQS)
2357 break;
2358
2359 msleep(20);
2360 }
2361
2362 if (cnt == 50) {
2363 DP_ERR(p_hwfn, "VF[%d] - pbf polling failed on VOQ %d\n",
2364 p_vf->abs_vf_id, i);
2365 return -EBUSY;
2366 }
2367
2368 return 0;
2369}
2370
2371static int qed_iov_vf_flr_poll(struct qed_hwfn *p_hwfn,
2372 struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
2373{
2374 int rc;
2375
2376 rc = qed_iov_vf_flr_poll_dorq(p_hwfn, p_vf, p_ptt);
2377 if (rc)
2378 return rc;
2379
2380 rc = qed_iov_vf_flr_poll_pbf(p_hwfn, p_vf, p_ptt);
2381 if (rc)
2382 return rc;
2383
2384 return 0;
2385}
2386
2387static int
2388qed_iov_execute_vf_flr_cleanup(struct qed_hwfn *p_hwfn,
2389 struct qed_ptt *p_ptt,
2390 u16 rel_vf_id, u32 *ack_vfs)
2391{
2392 struct qed_vf_info *p_vf;
2393 int rc = 0;
2394
2395 p_vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, false);
2396 if (!p_vf)
2397 return 0;
2398
2399 if (p_hwfn->pf_iov_info->pending_flr[rel_vf_id / 64] &
2400 (1ULL << (rel_vf_id % 64))) {
2401 u16 vfid = p_vf->abs_vf_id;
2402
2403 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2404 "VF[%d] - Handling FLR\n", vfid);
2405
2406 qed_iov_vf_cleanup(p_hwfn, p_vf);
2407
2408 /* If VF isn't active, no need for anything but SW */
2409 if (!p_vf->b_init)
2410 goto cleanup;
2411
2412 rc = qed_iov_vf_flr_poll(p_hwfn, p_vf, p_ptt);
2413 if (rc)
2414 goto cleanup;
2415
2416 rc = qed_final_cleanup(p_hwfn, p_ptt, vfid, true);
2417 if (rc) {
2418 DP_ERR(p_hwfn, "Failed handle FLR of VF[%d]\n", vfid);
2419 return rc;
2420 }
2421
2422 /* VF_STOPPED has to be set only after final cleanup
2423 * but prior to re-enabling the VF.
2424 */
2425 p_vf->state = VF_STOPPED;
2426
2427 rc = qed_iov_enable_vf_access(p_hwfn, p_ptt, p_vf);
2428 if (rc) {
2429 DP_ERR(p_hwfn, "Failed to re-enable VF[%d] acces\n",
2430 vfid);
2431 return rc;
2432 }
2433cleanup:
2434 /* Mark VF for ack and clean pending state */
2435 if (p_vf->state == VF_RESET)
2436 p_vf->state = VF_STOPPED;
2437 ack_vfs[vfid / 32] |= (1 << (vfid % 32));
2438 p_hwfn->pf_iov_info->pending_flr[rel_vf_id / 64] &=
2439 ~(1ULL << (rel_vf_id % 64));
2440 p_hwfn->pf_iov_info->pending_events[rel_vf_id / 64] &=
2441 ~(1ULL << (rel_vf_id % 64));
2442 }
2443
2444 return rc;
2445}
2446
2447int qed_iov_vf_flr_cleanup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2448{
2449 u32 ack_vfs[VF_MAX_STATIC / 32];
2450 int rc = 0;
2451 u16 i;
2452
2453 memset(ack_vfs, 0, sizeof(u32) * (VF_MAX_STATIC / 32));
2454
2455 /* Since BRB <-> PRS interface can't be tested as part of the flr
2456 * polling due to HW limitations, simply sleep a bit. And since
2457 * there's no need to wait per-vf, do it before looping.
2458 */
2459 msleep(100);
2460
2461 for (i = 0; i < p_hwfn->cdev->p_iov_info->total_vfs; i++)
2462 qed_iov_execute_vf_flr_cleanup(p_hwfn, p_ptt, i, ack_vfs);
2463
2464 rc = qed_mcp_ack_vf_flr(p_hwfn, p_ptt, ack_vfs);
2465 return rc;
2466}
2467
2468int qed_iov_mark_vf_flr(struct qed_hwfn *p_hwfn, u32 *p_disabled_vfs)
2469{
2470 u16 i, found = 0;
2471
2472 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "Marking FLR-ed VFs\n");
2473 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
2474 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2475 "[%08x,...,%08x]: %08x\n",
2476 i * 32, (i + 1) * 32 - 1, p_disabled_vfs[i]);
2477
2478 if (!p_hwfn->cdev->p_iov_info) {
2479 DP_NOTICE(p_hwfn, "VF flr but no IOV\n");
2480 return 0;
2481 }
2482
2483 /* Mark VFs */
2484 for (i = 0; i < p_hwfn->cdev->p_iov_info->total_vfs; i++) {
2485 struct qed_vf_info *p_vf;
2486 u8 vfid;
2487
2488 p_vf = qed_iov_get_vf_info(p_hwfn, i, false);
2489 if (!p_vf)
2490 continue;
2491
2492 vfid = p_vf->abs_vf_id;
2493 if ((1 << (vfid % 32)) & p_disabled_vfs[vfid / 32]) {
2494 u64 *p_flr = p_hwfn->pf_iov_info->pending_flr;
2495 u16 rel_vf_id = p_vf->relative_vf_id;
2496
2497 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2498 "VF[%d] [rel %d] got FLR-ed\n",
2499 vfid, rel_vf_id);
2500
2501 p_vf->state = VF_RESET;
2502
2503 /* No need to lock here, since pending_flr should
2504 * only change here and before ACKing MFw. Since
2505 * MFW will not trigger an additional attention for
2506 * VF flr until ACKs, we're safe.
2507 */
2508 p_flr[rel_vf_id / 64] |= 1ULL << (rel_vf_id % 64);
2509 found = 1;
2510 }
2511 }
2512
2513 return found;
2514}
2515
Yuval Mintz36558c32016-05-11 16:36:17 +03002516void qed_iov_set_link(struct qed_hwfn *p_hwfn,
2517 u16 vfid,
2518 struct qed_mcp_link_params *params,
2519 struct qed_mcp_link_state *link,
2520 struct qed_mcp_link_capabilities *p_caps)
2521{
2522 struct qed_vf_info *p_vf = qed_iov_get_vf_info(p_hwfn,
2523 vfid,
2524 false);
2525 struct qed_bulletin_content *p_bulletin;
2526
2527 if (!p_vf)
2528 return;
2529
2530 p_bulletin = p_vf->bulletin.p_virt;
2531 p_bulletin->req_autoneg = params->speed.autoneg;
2532 p_bulletin->req_adv_speed = params->speed.advertised_speeds;
2533 p_bulletin->req_forced_speed = params->speed.forced_speed;
2534 p_bulletin->req_autoneg_pause = params->pause.autoneg;
2535 p_bulletin->req_forced_rx = params->pause.forced_rx;
2536 p_bulletin->req_forced_tx = params->pause.forced_tx;
2537 p_bulletin->req_loopback = params->loopback_mode;
2538
2539 p_bulletin->link_up = link->link_up;
2540 p_bulletin->speed = link->speed;
2541 p_bulletin->full_duplex = link->full_duplex;
2542 p_bulletin->autoneg = link->an;
2543 p_bulletin->autoneg_complete = link->an_complete;
2544 p_bulletin->parallel_detection = link->parallel_detection;
2545 p_bulletin->pfc_enabled = link->pfc_enabled;
2546 p_bulletin->partner_adv_speed = link->partner_adv_speed;
2547 p_bulletin->partner_tx_flow_ctrl_en = link->partner_tx_flow_ctrl_en;
2548 p_bulletin->partner_rx_flow_ctrl_en = link->partner_rx_flow_ctrl_en;
2549 p_bulletin->partner_adv_pause = link->partner_adv_pause;
2550 p_bulletin->sfp_tx_fault = link->sfp_tx_fault;
2551
2552 p_bulletin->capability_speed = p_caps->speed_capabilities;
2553}
2554
Yuval Mintz37bff2b2016-05-11 16:36:13 +03002555static void qed_iov_process_mbx_req(struct qed_hwfn *p_hwfn,
2556 struct qed_ptt *p_ptt, int vfid)
2557{
2558 struct qed_iov_vf_mbx *mbx;
2559 struct qed_vf_info *p_vf;
2560 int i;
2561
2562 p_vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
2563 if (!p_vf)
2564 return;
2565
2566 mbx = &p_vf->vf_mbx;
2567
2568 /* qed_iov_process_mbx_request */
2569 DP_VERBOSE(p_hwfn,
2570 QED_MSG_IOV,
2571 "qed_iov_process_mbx_req vfid %d\n", p_vf->abs_vf_id);
2572
2573 mbx->first_tlv = mbx->req_virt->first_tlv;
2574
2575 /* check if tlv type is known */
2576 if (qed_iov_tlv_supported(mbx->first_tlv.tl.type)) {
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002577 switch (mbx->first_tlv.tl.type) {
2578 case CHANNEL_TLV_ACQUIRE:
2579 qed_iov_vf_mbx_acquire(p_hwfn, p_ptt, p_vf);
2580 break;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002581 case CHANNEL_TLV_VPORT_START:
2582 qed_iov_vf_mbx_start_vport(p_hwfn, p_ptt, p_vf);
2583 break;
2584 case CHANNEL_TLV_VPORT_TEARDOWN:
2585 qed_iov_vf_mbx_stop_vport(p_hwfn, p_ptt, p_vf);
2586 break;
2587 case CHANNEL_TLV_START_RXQ:
2588 qed_iov_vf_mbx_start_rxq(p_hwfn, p_ptt, p_vf);
2589 break;
2590 case CHANNEL_TLV_START_TXQ:
2591 qed_iov_vf_mbx_start_txq(p_hwfn, p_ptt, p_vf);
2592 break;
2593 case CHANNEL_TLV_STOP_RXQS:
2594 qed_iov_vf_mbx_stop_rxqs(p_hwfn, p_ptt, p_vf);
2595 break;
2596 case CHANNEL_TLV_STOP_TXQS:
2597 qed_iov_vf_mbx_stop_txqs(p_hwfn, p_ptt, p_vf);
2598 break;
Yuval Mintz17b235c2016-05-11 16:36:18 +03002599 case CHANNEL_TLV_UPDATE_RXQ:
2600 qed_iov_vf_mbx_update_rxqs(p_hwfn, p_ptt, p_vf);
2601 break;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002602 case CHANNEL_TLV_VPORT_UPDATE:
2603 qed_iov_vf_mbx_vport_update(p_hwfn, p_ptt, p_vf);
2604 break;
2605 case CHANNEL_TLV_UCAST_FILTER:
2606 qed_iov_vf_mbx_ucast_filter(p_hwfn, p_ptt, p_vf);
2607 break;
Yuval Mintz0b55e272016-05-11 16:36:15 +03002608 case CHANNEL_TLV_CLOSE:
2609 qed_iov_vf_mbx_close(p_hwfn, p_ptt, p_vf);
2610 break;
2611 case CHANNEL_TLV_INT_CLEANUP:
2612 qed_iov_vf_mbx_int_cleanup(p_hwfn, p_ptt, p_vf);
2613 break;
2614 case CHANNEL_TLV_RELEASE:
2615 qed_iov_vf_mbx_release(p_hwfn, p_ptt, p_vf);
2616 break;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002617 }
Yuval Mintz37bff2b2016-05-11 16:36:13 +03002618 } else {
2619 /* unknown TLV - this may belong to a VF driver from the future
2620 * - a version written after this PF driver was written, which
2621 * supports features unknown as of yet. Too bad since we don't
2622 * support them. Or this may be because someone wrote a crappy
2623 * VF driver and is sending garbage over the channel.
2624 */
2625 DP_ERR(p_hwfn,
2626 "unknown TLV. type %d length %d. first 20 bytes of mailbox buffer:\n",
2627 mbx->first_tlv.tl.type, mbx->first_tlv.tl.length);
2628
2629 for (i = 0; i < 20; i++) {
2630 DP_VERBOSE(p_hwfn,
2631 QED_MSG_IOV,
2632 "%x ",
2633 mbx->req_virt->tlv_buf_size.tlv_buffer[i]);
2634 }
2635 }
2636}
2637
2638void qed_iov_pf_add_pending_events(struct qed_hwfn *p_hwfn, u8 vfid)
2639{
2640 u64 add_bit = 1ULL << (vfid % 64);
2641
2642 p_hwfn->pf_iov_info->pending_events[vfid / 64] |= add_bit;
2643}
2644
2645static void qed_iov_pf_get_and_clear_pending_events(struct qed_hwfn *p_hwfn,
2646 u64 *events)
2647{
2648 u64 *p_pending_events = p_hwfn->pf_iov_info->pending_events;
2649
2650 memcpy(events, p_pending_events, sizeof(u64) * QED_VF_ARRAY_LENGTH);
2651 memset(p_pending_events, 0, sizeof(u64) * QED_VF_ARRAY_LENGTH);
2652}
2653
2654static int qed_sriov_vfpf_msg(struct qed_hwfn *p_hwfn,
2655 u16 abs_vfid, struct regpair *vf_msg)
2656{
2657 u8 min = (u8)p_hwfn->cdev->p_iov_info->first_vf_in_pf;
2658 struct qed_vf_info *p_vf;
2659
2660 if (!qed_iov_pf_sanity_check(p_hwfn, (int)abs_vfid - min)) {
2661 DP_VERBOSE(p_hwfn,
2662 QED_MSG_IOV,
2663 "Got a message from VF [abs 0x%08x] that cannot be handled by PF\n",
2664 abs_vfid);
2665 return 0;
2666 }
2667 p_vf = &p_hwfn->pf_iov_info->vfs_array[(u8)abs_vfid - min];
2668
2669 /* List the physical address of the request so that handler
2670 * could later on copy the message from it.
2671 */
2672 p_vf->vf_mbx.pending_req = (((u64)vf_msg->hi) << 32) | vf_msg->lo;
2673
2674 /* Mark the event and schedule the workqueue */
2675 qed_iov_pf_add_pending_events(p_hwfn, p_vf->relative_vf_id);
2676 qed_schedule_iov(p_hwfn, QED_IOV_WQ_MSG_FLAG);
2677
2678 return 0;
2679}
2680
2681int qed_sriov_eqe_event(struct qed_hwfn *p_hwfn,
2682 u8 opcode, __le16 echo, union event_ring_data *data)
2683{
2684 switch (opcode) {
2685 case COMMON_EVENT_VF_PF_CHANNEL:
2686 return qed_sriov_vfpf_msg(p_hwfn, le16_to_cpu(echo),
2687 &data->vf_pf_channel.msg_addr);
2688 default:
2689 DP_INFO(p_hwfn->cdev, "Unknown sriov eqe event 0x%02x\n",
2690 opcode);
2691 return -EINVAL;
2692 }
2693}
2694
Yuval Mintz32a47e72016-05-11 16:36:12 +03002695u16 qed_iov_get_next_active_vf(struct qed_hwfn *p_hwfn, u16 rel_vf_id)
2696{
2697 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
2698 u16 i;
2699
2700 if (!p_iov)
2701 goto out;
2702
2703 for (i = rel_vf_id; i < p_iov->total_vfs; i++)
2704 if (qed_iov_is_valid_vfid(p_hwfn, rel_vf_id, true))
2705 return i;
2706
2707out:
2708 return MAX_NUM_VFS;
2709}
Yuval Mintz37bff2b2016-05-11 16:36:13 +03002710
2711static int qed_iov_copy_vf_msg(struct qed_hwfn *p_hwfn, struct qed_ptt *ptt,
2712 int vfid)
2713{
2714 struct qed_dmae_params params;
2715 struct qed_vf_info *vf_info;
2716
2717 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
2718 if (!vf_info)
2719 return -EINVAL;
2720
2721 memset(&params, 0, sizeof(struct qed_dmae_params));
2722 params.flags = QED_DMAE_FLAG_VF_SRC | QED_DMAE_FLAG_COMPLETION_DST;
2723 params.src_vfid = vf_info->abs_vf_id;
2724
2725 if (qed_dmae_host2host(p_hwfn, ptt,
2726 vf_info->vf_mbx.pending_req,
2727 vf_info->vf_mbx.req_phys,
2728 sizeof(union vfpf_tlvs) / 4, &params)) {
2729 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2730 "Failed to copy message from VF 0x%02x\n", vfid);
2731
2732 return -EIO;
2733 }
2734
2735 return 0;
2736}
2737
Yuval Mintzeff16962016-05-11 16:36:21 +03002738static void qed_iov_bulletin_set_forced_mac(struct qed_hwfn *p_hwfn,
2739 u8 *mac, int vfid)
2740{
2741 struct qed_vf_info *vf_info;
2742 u64 feature;
2743
2744 vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
2745 if (!vf_info) {
2746 DP_NOTICE(p_hwfn->cdev,
2747 "Can not set forced MAC, invalid vfid [%d]\n", vfid);
2748 return;
2749 }
2750
2751 feature = 1 << MAC_ADDR_FORCED;
2752 memcpy(vf_info->bulletin.p_virt->mac, mac, ETH_ALEN);
2753
2754 vf_info->bulletin.p_virt->valid_bitmap |= feature;
2755 /* Forced MAC will disable MAC_ADDR */
2756 vf_info->bulletin.p_virt->valid_bitmap &=
2757 ~(1 << VFPF_BULLETIN_MAC_ADDR);
2758
2759 qed_iov_configure_vport_forced(p_hwfn, vf_info, feature);
2760}
2761
Yuval Mintz08feecd2016-05-11 16:36:20 +03002762void qed_iov_bulletin_set_forced_vlan(struct qed_hwfn *p_hwfn,
2763 u16 pvid, int vfid)
2764{
2765 struct qed_vf_info *vf_info;
2766 u64 feature;
2767
2768 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
2769 if (!vf_info) {
2770 DP_NOTICE(p_hwfn->cdev,
2771 "Can not set forced MAC, invalid vfid [%d]\n", vfid);
2772 return;
2773 }
2774
2775 feature = 1 << VLAN_ADDR_FORCED;
2776 vf_info->bulletin.p_virt->pvid = pvid;
2777 if (pvid)
2778 vf_info->bulletin.p_virt->valid_bitmap |= feature;
2779 else
2780 vf_info->bulletin.p_virt->valid_bitmap &= ~feature;
2781
2782 qed_iov_configure_vport_forced(p_hwfn, vf_info, feature);
2783}
2784
Yuval Mintz0b55e272016-05-11 16:36:15 +03002785bool qed_iov_is_vf_stopped(struct qed_hwfn *p_hwfn, int vfid)
2786{
2787 struct qed_vf_info *p_vf_info;
2788
2789 p_vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
2790 if (!p_vf_info)
2791 return true;
2792
2793 return p_vf_info->state == VF_STOPPED;
2794}
2795
Yuval Mintzeff16962016-05-11 16:36:21 +03002796static u8 *qed_iov_bulletin_get_forced_mac(struct qed_hwfn *p_hwfn,
2797 u16 rel_vf_id)
2798{
2799 struct qed_vf_info *p_vf;
2800
2801 p_vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
2802 if (!p_vf || !p_vf->bulletin.p_virt)
2803 return NULL;
2804
2805 if (!(p_vf->bulletin.p_virt->valid_bitmap & (1 << MAC_ADDR_FORCED)))
2806 return NULL;
2807
2808 return p_vf->bulletin.p_virt->mac;
2809}
2810
Yuval Mintz08feecd2016-05-11 16:36:20 +03002811u16 qed_iov_bulletin_get_forced_vlan(struct qed_hwfn *p_hwfn, u16 rel_vf_id)
2812{
2813 struct qed_vf_info *p_vf;
2814
2815 p_vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
2816 if (!p_vf || !p_vf->bulletin.p_virt)
2817 return 0;
2818
2819 if (!(p_vf->bulletin.p_virt->valid_bitmap & (1 << VLAN_ADDR_FORCED)))
2820 return 0;
2821
2822 return p_vf->bulletin.p_virt->pvid;
2823}
2824
Yuval Mintz37bff2b2016-05-11 16:36:13 +03002825/**
2826 * qed_schedule_iov - schedules IOV task for VF and PF
2827 * @hwfn: hardware function pointer
2828 * @flag: IOV flag for VF/PF
2829 */
2830void qed_schedule_iov(struct qed_hwfn *hwfn, enum qed_iov_wq_flag flag)
2831{
2832 smp_mb__before_atomic();
2833 set_bit(flag, &hwfn->iov_task_flags);
2834 smp_mb__after_atomic();
2835 DP_VERBOSE(hwfn, QED_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag);
2836 queue_delayed_work(hwfn->iov_wq, &hwfn->iov_task, 0);
2837}
2838
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03002839void qed_vf_start_iov_wq(struct qed_dev *cdev)
2840{
2841 int i;
2842
2843 for_each_hwfn(cdev, i)
2844 queue_delayed_work(cdev->hwfns[i].iov_wq,
2845 &cdev->hwfns[i].iov_task, 0);
2846}
2847
Yuval Mintz0b55e272016-05-11 16:36:15 +03002848int qed_sriov_disable(struct qed_dev *cdev, bool pci_enabled)
2849{
2850 int i, j;
2851
2852 for_each_hwfn(cdev, i)
2853 if (cdev->hwfns[i].iov_wq)
2854 flush_workqueue(cdev->hwfns[i].iov_wq);
2855
2856 /* Mark VFs for disablement */
2857 qed_iov_set_vfs_to_disable(cdev, true);
2858
2859 if (cdev->p_iov_info && cdev->p_iov_info->num_vfs && pci_enabled)
2860 pci_disable_sriov(cdev->pdev);
2861
2862 for_each_hwfn(cdev, i) {
2863 struct qed_hwfn *hwfn = &cdev->hwfns[i];
2864 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
2865
2866 /* Failure to acquire the ptt in 100g creates an odd error
2867 * where the first engine has already relased IOV.
2868 */
2869 if (!ptt) {
2870 DP_ERR(hwfn, "Failed to acquire ptt\n");
2871 return -EBUSY;
2872 }
2873
2874 qed_for_each_vf(hwfn, j) {
2875 int k;
2876
2877 if (!qed_iov_is_valid_vfid(hwfn, j, true))
2878 continue;
2879
2880 /* Wait until VF is disabled before releasing */
2881 for (k = 0; k < 100; k++) {
2882 if (!qed_iov_is_vf_stopped(hwfn, j))
2883 msleep(20);
2884 else
2885 break;
2886 }
2887
2888 if (k < 100)
2889 qed_iov_release_hw_for_vf(&cdev->hwfns[i],
2890 ptt, j);
2891 else
2892 DP_ERR(hwfn,
2893 "Timeout waiting for VF's FLR to end\n");
2894 }
2895
2896 qed_ptt_release(hwfn, ptt);
2897 }
2898
2899 qed_iov_set_vfs_to_disable(cdev, false);
2900
2901 return 0;
2902}
2903
2904static int qed_sriov_enable(struct qed_dev *cdev, int num)
2905{
2906 struct qed_sb_cnt_info sb_cnt_info;
2907 int i, j, rc;
2908
2909 if (num >= RESC_NUM(&cdev->hwfns[0], QED_VPORT)) {
2910 DP_NOTICE(cdev, "Can start at most %d VFs\n",
2911 RESC_NUM(&cdev->hwfns[0], QED_VPORT) - 1);
2912 return -EINVAL;
2913 }
2914
2915 /* Initialize HW for VF access */
2916 for_each_hwfn(cdev, j) {
2917 struct qed_hwfn *hwfn = &cdev->hwfns[j];
2918 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
2919 int num_sbs = 0, limit = 16;
2920
2921 if (!ptt) {
2922 DP_ERR(hwfn, "Failed to acquire ptt\n");
2923 rc = -EBUSY;
2924 goto err;
2925 }
2926
2927 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
2928 qed_int_get_num_sbs(hwfn, &sb_cnt_info);
2929 num_sbs = min_t(int, sb_cnt_info.sb_free_blk, limit);
2930
2931 for (i = 0; i < num; i++) {
2932 if (!qed_iov_is_valid_vfid(hwfn, i, false))
2933 continue;
2934
2935 rc = qed_iov_init_hw_for_vf(hwfn,
2936 ptt, i, num_sbs / num);
2937 if (rc) {
2938 DP_ERR(cdev, "Failed to enable VF[%d]\n", i);
2939 qed_ptt_release(hwfn, ptt);
2940 goto err;
2941 }
2942 }
2943
2944 qed_ptt_release(hwfn, ptt);
2945 }
2946
2947 /* Enable SRIOV PCIe functions */
2948 rc = pci_enable_sriov(cdev->pdev, num);
2949 if (rc) {
2950 DP_ERR(cdev, "Failed to enable sriov [%d]\n", rc);
2951 goto err;
2952 }
2953
2954 return num;
2955
2956err:
2957 qed_sriov_disable(cdev, false);
2958 return rc;
2959}
2960
2961static int qed_sriov_configure(struct qed_dev *cdev, int num_vfs_param)
2962{
2963 if (!IS_QED_SRIOV(cdev)) {
2964 DP_VERBOSE(cdev, QED_MSG_IOV, "SR-IOV is not supported\n");
2965 return -EOPNOTSUPP;
2966 }
2967
2968 if (num_vfs_param)
2969 return qed_sriov_enable(cdev, num_vfs_param);
2970 else
2971 return qed_sriov_disable(cdev, true);
2972}
2973
Yuval Mintzeff16962016-05-11 16:36:21 +03002974static int qed_sriov_pf_set_mac(struct qed_dev *cdev, u8 *mac, int vfid)
2975{
2976 int i;
2977
2978 if (!IS_QED_SRIOV(cdev) || !IS_PF_SRIOV_ALLOC(&cdev->hwfns[0])) {
2979 DP_VERBOSE(cdev, QED_MSG_IOV,
2980 "Cannot set a VF MAC; Sriov is not enabled\n");
2981 return -EINVAL;
2982 }
2983
2984 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vfid, true)) {
2985 DP_VERBOSE(cdev, QED_MSG_IOV,
2986 "Cannot set VF[%d] MAC (VF is not active)\n", vfid);
2987 return -EINVAL;
2988 }
2989
2990 for_each_hwfn(cdev, i) {
2991 struct qed_hwfn *hwfn = &cdev->hwfns[i];
2992 struct qed_public_vf_info *vf_info;
2993
2994 vf_info = qed_iov_get_public_vf_info(hwfn, vfid, true);
2995 if (!vf_info)
2996 continue;
2997
2998 /* Set the forced MAC, and schedule the IOV task */
2999 ether_addr_copy(vf_info->forced_mac, mac);
3000 qed_schedule_iov(hwfn, QED_IOV_WQ_SET_UNICAST_FILTER_FLAG);
3001 }
3002
3003 return 0;
3004}
3005
Yuval Mintz08feecd2016-05-11 16:36:20 +03003006static int qed_sriov_pf_set_vlan(struct qed_dev *cdev, u16 vid, int vfid)
3007{
3008 int i;
3009
3010 if (!IS_QED_SRIOV(cdev) || !IS_PF_SRIOV_ALLOC(&cdev->hwfns[0])) {
3011 DP_VERBOSE(cdev, QED_MSG_IOV,
3012 "Cannot set a VF MAC; Sriov is not enabled\n");
3013 return -EINVAL;
3014 }
3015
3016 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vfid, true)) {
3017 DP_VERBOSE(cdev, QED_MSG_IOV,
3018 "Cannot set VF[%d] MAC (VF is not active)\n", vfid);
3019 return -EINVAL;
3020 }
3021
3022 for_each_hwfn(cdev, i) {
3023 struct qed_hwfn *hwfn = &cdev->hwfns[i];
3024 struct qed_public_vf_info *vf_info;
3025
3026 vf_info = qed_iov_get_public_vf_info(hwfn, vfid, true);
3027 if (!vf_info)
3028 continue;
3029
3030 /* Set the forced vlan, and schedule the IOV task */
3031 vf_info->forced_vlan = vid;
3032 qed_schedule_iov(hwfn, QED_IOV_WQ_SET_UNICAST_FILTER_FLAG);
3033 }
3034
3035 return 0;
3036}
3037
Yuval Mintz36558c32016-05-11 16:36:17 +03003038void qed_inform_vf_link_state(struct qed_hwfn *hwfn)
3039{
3040 struct qed_mcp_link_capabilities caps;
3041 struct qed_mcp_link_params params;
3042 struct qed_mcp_link_state link;
3043 int i;
3044
3045 if (!hwfn->pf_iov_info)
3046 return;
3047
3048 /* Update bulletin of all future possible VFs with link configuration */
3049 for (i = 0; i < hwfn->cdev->p_iov_info->total_vfs; i++) {
3050 memcpy(&params, qed_mcp_get_link_params(hwfn), sizeof(params));
3051 memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link));
3052 memcpy(&caps, qed_mcp_get_link_capabilities(hwfn),
3053 sizeof(caps));
3054
3055 qed_iov_set_link(hwfn, i, &params, &link, &caps);
3056 }
3057
3058 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
3059}
3060
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003061static void qed_handle_vf_msg(struct qed_hwfn *hwfn)
3062{
3063 u64 events[QED_VF_ARRAY_LENGTH];
3064 struct qed_ptt *ptt;
3065 int i;
3066
3067 ptt = qed_ptt_acquire(hwfn);
3068 if (!ptt) {
3069 DP_VERBOSE(hwfn, QED_MSG_IOV,
3070 "Can't acquire PTT; re-scheduling\n");
3071 qed_schedule_iov(hwfn, QED_IOV_WQ_MSG_FLAG);
3072 return;
3073 }
3074
3075 qed_iov_pf_get_and_clear_pending_events(hwfn, events);
3076
3077 DP_VERBOSE(hwfn, QED_MSG_IOV,
3078 "Event mask of VF events: 0x%llx 0x%llx 0x%llx\n",
3079 events[0], events[1], events[2]);
3080
3081 qed_for_each_vf(hwfn, i) {
3082 /* Skip VFs with no pending messages */
3083 if (!(events[i / 64] & (1ULL << (i % 64))))
3084 continue;
3085
3086 DP_VERBOSE(hwfn, QED_MSG_IOV,
3087 "Handling VF message from VF 0x%02x [Abs 0x%02x]\n",
3088 i, hwfn->cdev->p_iov_info->first_vf_in_pf + i);
3089
3090 /* Copy VF's message to PF's request buffer for that VF */
3091 if (qed_iov_copy_vf_msg(hwfn, ptt, i))
3092 continue;
3093
3094 qed_iov_process_mbx_req(hwfn, ptt, i);
3095 }
3096
3097 qed_ptt_release(hwfn, ptt);
3098}
3099
Yuval Mintz08feecd2016-05-11 16:36:20 +03003100static void qed_handle_pf_set_vf_unicast(struct qed_hwfn *hwfn)
3101{
3102 int i;
3103
3104 qed_for_each_vf(hwfn, i) {
3105 struct qed_public_vf_info *info;
3106 bool update = false;
Yuval Mintzeff16962016-05-11 16:36:21 +03003107 u8 *mac;
Yuval Mintz08feecd2016-05-11 16:36:20 +03003108
3109 info = qed_iov_get_public_vf_info(hwfn, i, true);
3110 if (!info)
3111 continue;
3112
3113 /* Update data on bulletin board */
Yuval Mintzeff16962016-05-11 16:36:21 +03003114 mac = qed_iov_bulletin_get_forced_mac(hwfn, i);
3115 if (is_valid_ether_addr(info->forced_mac) &&
3116 (!mac || !ether_addr_equal(mac, info->forced_mac))) {
3117 DP_VERBOSE(hwfn,
3118 QED_MSG_IOV,
3119 "Handling PF setting of VF MAC to VF 0x%02x [Abs 0x%02x]\n",
3120 i,
3121 hwfn->cdev->p_iov_info->first_vf_in_pf + i);
3122
3123 /* Update bulletin board with forced MAC */
3124 qed_iov_bulletin_set_forced_mac(hwfn,
3125 info->forced_mac, i);
3126 update = true;
3127 }
Yuval Mintz08feecd2016-05-11 16:36:20 +03003128
3129 if (qed_iov_bulletin_get_forced_vlan(hwfn, i) ^
3130 info->forced_vlan) {
3131 DP_VERBOSE(hwfn,
3132 QED_MSG_IOV,
3133 "Handling PF setting of pvid [0x%04x] to VF 0x%02x [Abs 0x%02x]\n",
3134 info->forced_vlan,
3135 i,
3136 hwfn->cdev->p_iov_info->first_vf_in_pf + i);
3137 qed_iov_bulletin_set_forced_vlan(hwfn,
3138 info->forced_vlan, i);
3139 update = true;
3140 }
3141
3142 if (update)
3143 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
3144 }
3145}
3146
Yuval Mintz36558c32016-05-11 16:36:17 +03003147static void qed_handle_bulletin_post(struct qed_hwfn *hwfn)
3148{
3149 struct qed_ptt *ptt;
3150 int i;
3151
3152 ptt = qed_ptt_acquire(hwfn);
3153 if (!ptt) {
3154 DP_NOTICE(hwfn, "Failed allocating a ptt entry\n");
3155 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
3156 return;
3157 }
3158
3159 qed_for_each_vf(hwfn, i)
3160 qed_iov_post_vf_bulletin(hwfn, i, ptt);
3161
3162 qed_ptt_release(hwfn, ptt);
3163}
3164
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003165void qed_iov_pf_task(struct work_struct *work)
3166{
3167 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
3168 iov_task.work);
Yuval Mintz0b55e272016-05-11 16:36:15 +03003169 int rc;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003170
3171 if (test_and_clear_bit(QED_IOV_WQ_STOP_WQ_FLAG, &hwfn->iov_task_flags))
3172 return;
3173
Yuval Mintz0b55e272016-05-11 16:36:15 +03003174 if (test_and_clear_bit(QED_IOV_WQ_FLR_FLAG, &hwfn->iov_task_flags)) {
3175 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
3176
3177 if (!ptt) {
3178 qed_schedule_iov(hwfn, QED_IOV_WQ_FLR_FLAG);
3179 return;
3180 }
3181
3182 rc = qed_iov_vf_flr_cleanup(hwfn, ptt);
3183 if (rc)
3184 qed_schedule_iov(hwfn, QED_IOV_WQ_FLR_FLAG);
3185
3186 qed_ptt_release(hwfn, ptt);
3187 }
3188
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003189 if (test_and_clear_bit(QED_IOV_WQ_MSG_FLAG, &hwfn->iov_task_flags))
3190 qed_handle_vf_msg(hwfn);
Yuval Mintz08feecd2016-05-11 16:36:20 +03003191
3192 if (test_and_clear_bit(QED_IOV_WQ_SET_UNICAST_FILTER_FLAG,
3193 &hwfn->iov_task_flags))
3194 qed_handle_pf_set_vf_unicast(hwfn);
3195
Yuval Mintz36558c32016-05-11 16:36:17 +03003196 if (test_and_clear_bit(QED_IOV_WQ_BULLETIN_UPDATE_FLAG,
3197 &hwfn->iov_task_flags))
3198 qed_handle_bulletin_post(hwfn);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003199}
3200
3201void qed_iov_wq_stop(struct qed_dev *cdev, bool schedule_first)
3202{
3203 int i;
3204
3205 for_each_hwfn(cdev, i) {
3206 if (!cdev->hwfns[i].iov_wq)
3207 continue;
3208
3209 if (schedule_first) {
3210 qed_schedule_iov(&cdev->hwfns[i],
3211 QED_IOV_WQ_STOP_WQ_FLAG);
3212 cancel_delayed_work_sync(&cdev->hwfns[i].iov_task);
3213 }
3214
3215 flush_workqueue(cdev->hwfns[i].iov_wq);
3216 destroy_workqueue(cdev->hwfns[i].iov_wq);
3217 }
3218}
3219
3220int qed_iov_wq_start(struct qed_dev *cdev)
3221{
3222 char name[NAME_SIZE];
3223 int i;
3224
3225 for_each_hwfn(cdev, i) {
3226 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3227
Yuval Mintz36558c32016-05-11 16:36:17 +03003228 /* PFs needs a dedicated workqueue only if they support IOV.
3229 * VFs always require one.
3230 */
3231 if (IS_PF(p_hwfn->cdev) && !IS_PF_SRIOV(p_hwfn))
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003232 continue;
3233
3234 snprintf(name, NAME_SIZE, "iov-%02x:%02x.%02x",
3235 cdev->pdev->bus->number,
3236 PCI_SLOT(cdev->pdev->devfn), p_hwfn->abs_pf_id);
3237
3238 p_hwfn->iov_wq = create_singlethread_workqueue(name);
3239 if (!p_hwfn->iov_wq) {
3240 DP_NOTICE(p_hwfn, "Cannot create iov workqueue\n");
3241 return -ENOMEM;
3242 }
3243
Yuval Mintz36558c32016-05-11 16:36:17 +03003244 if (IS_PF(cdev))
3245 INIT_DELAYED_WORK(&p_hwfn->iov_task, qed_iov_pf_task);
3246 else
3247 INIT_DELAYED_WORK(&p_hwfn->iov_task, qed_iov_vf_task);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003248 }
3249
3250 return 0;
3251}
Yuval Mintz0b55e272016-05-11 16:36:15 +03003252
3253const struct qed_iov_hv_ops qed_iov_ops_pass = {
3254 .configure = &qed_sriov_configure,
Yuval Mintzeff16962016-05-11 16:36:21 +03003255 .set_mac = &qed_sriov_pf_set_mac,
Yuval Mintz08feecd2016-05-11 16:36:20 +03003256 .set_vlan = &qed_sriov_pf_set_vlan,
Yuval Mintz0b55e272016-05-11 16:36:15 +03003257};