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Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02002 * Copyright (c) 2015-2017 QLogic Corporation
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003 *
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030031 */
32
Yuval Mintz36558c32016-05-11 16:36:17 +030033#include <linux/crc32.h>
Yuval Mintzeff16962016-05-11 16:36:21 +030034#include <linux/etherdevice.h>
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030035#include "qed.h"
36#include "qed_sriov.h"
37#include "qed_vf.h"
38
39static void *qed_vf_pf_prep(struct qed_hwfn *p_hwfn, u16 type, u16 length)
40{
41 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
42 void *p_tlv;
43
44 /* This lock is released when we receive PF's response
45 * in qed_send_msg2pf().
46 * So, qed_vf_pf_prep() and qed_send_msg2pf()
47 * must come in sequence.
48 */
49 mutex_lock(&(p_iov->mutex));
50
51 DP_VERBOSE(p_hwfn,
52 QED_MSG_IOV,
53 "preparing to send 0x%04x tlv over vf pf channel\n",
54 type);
55
56 /* Reset Requst offset */
57 p_iov->offset = (u8 *)p_iov->vf2pf_request;
58
59 /* Clear mailbox - both request and reply */
60 memset(p_iov->vf2pf_request, 0, sizeof(union vfpf_tlvs));
61 memset(p_iov->pf2vf_reply, 0, sizeof(union pfvf_tlvs));
62
63 /* Init type and length */
64 p_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, type, length);
65
66 /* Init first tlv header */
67 ((struct vfpf_first_tlv *)p_tlv)->reply_address =
68 (u64)p_iov->pf2vf_reply_phys;
69
70 return p_tlv;
71}
72
Yuval Mintzb0bccb62016-08-22 13:25:12 +030073static void qed_vf_pf_req_end(struct qed_hwfn *p_hwfn, int req_status)
74{
75 union pfvf_tlvs *resp = p_hwfn->vf_iov_info->pf2vf_reply;
76
77 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
78 "VF request status = 0x%x, PF reply status = 0x%x\n",
79 req_status, resp->default_resp.hdr.status);
80
81 mutex_unlock(&(p_hwfn->vf_iov_info->mutex));
82}
83
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030084static int qed_send_msg2pf(struct qed_hwfn *p_hwfn, u8 *done, u32 resp_size)
85{
86 union vfpf_tlvs *p_req = p_hwfn->vf_iov_info->vf2pf_request;
87 struct ustorm_trigger_vf_zone trigger;
88 struct ustorm_vf_zone *zone_data;
89 int rc = 0, time = 100;
90
91 zone_data = (struct ustorm_vf_zone *)PXP_VF_BAR0_START_USDM_ZONE_B;
92
93 /* output tlvs list */
94 qed_dp_tlv_list(p_hwfn, p_req);
95
96 /* need to add the END TLV to the message size */
97 resp_size += sizeof(struct channel_list_end_tlv);
98
99 /* Send TLVs over HW channel */
100 memset(&trigger, 0, sizeof(struct ustorm_trigger_vf_zone));
101 trigger.vf_pf_msg_valid = 1;
102
103 DP_VERBOSE(p_hwfn,
104 QED_MSG_IOV,
105 "VF -> PF [%02x] message: [%08x, %08x] --> %p, %08x --> %p\n",
106 GET_FIELD(p_hwfn->hw_info.concrete_fid,
107 PXP_CONCRETE_FID_PFID),
108 upper_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys),
109 lower_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys),
110 &zone_data->non_trigger.vf_pf_msg_addr,
111 *((u32 *)&trigger), &zone_data->trigger);
112
113 REG_WR(p_hwfn,
114 (uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.lo,
115 lower_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys));
116
117 REG_WR(p_hwfn,
118 (uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.hi,
119 upper_32_bits(p_hwfn->vf_iov_info->vf2pf_request_phys));
120
121 /* The message data must be written first, to prevent trigger before
122 * data is written.
123 */
124 wmb();
125
126 REG_WR(p_hwfn, (uintptr_t)&zone_data->trigger, *((u32 *)&trigger));
127
128 /* When PF would be done with the response, it would write back to the
129 * `done' address. Poll until then.
130 */
131 while ((!*done) && time) {
132 msleep(25);
133 time--;
134 }
135
136 if (!*done) {
137 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
138 "VF <-- PF Timeout [Type %d]\n",
139 p_req->first_tlv.tl.type);
140 rc = -EBUSY;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300141 } else {
142 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
143 "PF response: %d [Type %d]\n",
144 *done, p_req->first_tlv.tl.type);
145 }
146
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300147 return rc;
148}
149
150#define VF_ACQUIRE_THRESH 3
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300151static void qed_vf_pf_acquire_reduce_resc(struct qed_hwfn *p_hwfn,
152 struct vf_pf_resc_request *p_req,
153 struct pf_vf_resc *p_resp)
154{
155 DP_VERBOSE(p_hwfn,
156 QED_MSG_IOV,
157 "PF unwilling to fullill resource request: rxq [%02x/%02x] txq [%02x/%02x] sbs [%02x/%02x] mac [%02x/%02x] vlan [%02x/%02x] mc [%02x/%02x]. Try PF recommended amount\n",
158 p_req->num_rxqs,
159 p_resp->num_rxqs,
160 p_req->num_rxqs,
161 p_resp->num_txqs,
162 p_req->num_sbs,
163 p_resp->num_sbs,
164 p_req->num_mac_filters,
165 p_resp->num_mac_filters,
166 p_req->num_vlan_filters,
167 p_resp->num_vlan_filters,
168 p_req->num_mc_filters, p_resp->num_mc_filters);
169
170 /* humble our request */
171 p_req->num_txqs = p_resp->num_txqs;
172 p_req->num_rxqs = p_resp->num_rxqs;
173 p_req->num_sbs = p_resp->num_sbs;
174 p_req->num_mac_filters = p_resp->num_mac_filters;
175 p_req->num_vlan_filters = p_resp->num_vlan_filters;
176 p_req->num_mc_filters = p_resp->num_mc_filters;
177}
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300178
179static int qed_vf_pf_acquire(struct qed_hwfn *p_hwfn)
180{
181 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
182 struct pfvf_acquire_resp_tlv *resp = &p_iov->pf2vf_reply->acquire_resp;
183 struct pf_vf_pfdev_info *pfdev_info = &resp->pfdev_info;
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300184 struct vf_pf_resc_request *p_resc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300185 bool resources_acquired = false;
186 struct vfpf_acquire_tlv *req;
187 int rc = 0, attempts = 0;
188
189 /* clear mailbox and prep first tlv */
190 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_ACQUIRE, sizeof(*req));
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300191 p_resc = &req->resc_request;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300192
193 /* starting filling the request */
194 req->vfdev_info.opaque_fid = p_hwfn->hw_info.opaque_fid;
195
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300196 p_resc->num_rxqs = QED_MAX_VF_CHAINS_PER_PF;
197 p_resc->num_txqs = QED_MAX_VF_CHAINS_PER_PF;
198 p_resc->num_sbs = QED_MAX_VF_CHAINS_PER_PF;
199 p_resc->num_mac_filters = QED_ETH_VF_NUM_MAC_FILTERS;
200 p_resc->num_vlan_filters = QED_ETH_VF_NUM_VLAN_FILTERS;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300201
202 req->vfdev_info.os_type = VFPF_ACQUIRE_OS_LINUX;
203 req->vfdev_info.fw_major = FW_MAJOR_VERSION;
204 req->vfdev_info.fw_minor = FW_MINOR_VERSION;
205 req->vfdev_info.fw_revision = FW_REVISION_VERSION;
206 req->vfdev_info.fw_engineering = FW_ENGINEERING_VERSION;
Yuval Mintz1fe614d2016-06-05 13:11:11 +0300207 req->vfdev_info.eth_fp_hsi_major = ETH_HSI_VER_MAJOR;
208 req->vfdev_info.eth_fp_hsi_minor = ETH_HSI_VER_MINOR;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300209
210 /* Fill capability field with any non-deprecated config we support */
211 req->vfdev_info.capabilities |= VFPF_ACQUIRE_CAP_100G;
212
213 /* pf 2 vf bulletin board address */
214 req->bulletin_addr = p_iov->bulletin.phys;
215 req->bulletin_size = p_iov->bulletin.size;
216
217 /* add list termination tlv */
218 qed_add_tlv(p_hwfn, &p_iov->offset,
219 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
220
221 while (!resources_acquired) {
222 DP_VERBOSE(p_hwfn,
223 QED_MSG_IOV, "attempting to acquire resources\n");
224
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300225 /* Clear response buffer, as this might be a re-send */
226 memset(p_iov->pf2vf_reply, 0, sizeof(union pfvf_tlvs));
227
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300228 /* send acquire request */
229 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
230 if (rc)
231 return rc;
232
233 /* copy acquire response from buffer to p_hwfn */
234 memcpy(&p_iov->acquire_resp, resp, sizeof(p_iov->acquire_resp));
235
236 attempts++;
237
238 if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
239 /* PF agrees to allocate our resources */
240 if (!(resp->pfdev_info.capabilities &
241 PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE)) {
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300242 /* It's possible legacy PF mistakenly accepted;
243 * but we don't care - simply mark it as
244 * legacy and continue.
245 */
246 req->vfdev_info.capabilities |=
247 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300248 }
249 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "resources acquired\n");
250 resources_acquired = true;
251 } else if (resp->hdr.status == PFVF_STATUS_NO_RESOURCE &&
252 attempts < VF_ACQUIRE_THRESH) {
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300253 qed_vf_pf_acquire_reduce_resc(p_hwfn, p_resc,
254 &resp->resc);
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300255 } else if (resp->hdr.status == PFVF_STATUS_NOT_SUPPORTED) {
256 if (pfdev_info->major_fp_hsi &&
257 (pfdev_info->major_fp_hsi != ETH_HSI_VER_MAJOR)) {
258 DP_NOTICE(p_hwfn,
259 "PF uses an incompatible fastpath HSI %02x.%02x [VF requires %02x.%02x]. Please change to a VF driver using %02x.xx.\n",
260 pfdev_info->major_fp_hsi,
261 pfdev_info->minor_fp_hsi,
262 ETH_HSI_VER_MAJOR,
263 ETH_HSI_VER_MINOR,
264 pfdev_info->major_fp_hsi);
265 rc = -EINVAL;
266 goto exit;
267 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300268
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300269 if (!pfdev_info->major_fp_hsi) {
270 if (req->vfdev_info.capabilities &
271 VFPF_ACQUIRE_CAP_PRE_FP_HSI) {
272 DP_NOTICE(p_hwfn,
273 "PF uses very old drivers. Please change to a VF driver using no later than 8.8.x.x.\n");
274 rc = -EINVAL;
275 goto exit;
276 } else {
277 DP_INFO(p_hwfn,
278 "PF is old - try re-acquire to see if it supports FW-version override\n");
279 req->vfdev_info.capabilities |=
280 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
281 continue;
282 }
283 }
284
285 /* If PF/VF are using same Major, PF must have had
286 * it's reasons. Simply fail.
287 */
288 DP_NOTICE(p_hwfn, "PF rejected acquisition by VF\n");
289 rc = -EINVAL;
290 goto exit;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300291 } else {
292 DP_ERR(p_hwfn,
293 "PF returned error %d to VF acquisition request\n",
294 resp->hdr.status);
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300295 rc = -EAGAIN;
296 goto exit;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300297 }
298 }
299
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300300 /* Mark the PF as legacy, if needed */
301 if (req->vfdev_info.capabilities & VFPF_ACQUIRE_CAP_PRE_FP_HSI)
302 p_iov->b_pre_fp_hsi = true;
303
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300304 /* Update bulletin board size with response from PF */
305 p_iov->bulletin.size = resp->bulletin_size;
306
307 /* get HW info */
308 p_hwfn->cdev->type = resp->pfdev_info.dev_type;
309 p_hwfn->cdev->chip_rev = resp->pfdev_info.chip_rev;
310
311 p_hwfn->cdev->chip_num = pfdev_info->chip_num & 0xffff;
312
313 /* Learn of the possibility of CMT */
314 if (IS_LEAD_HWFN(p_hwfn)) {
315 if (resp->pfdev_info.capabilities & PFVF_ACQUIRE_CAP_100G) {
316 DP_NOTICE(p_hwfn, "100g VF\n");
317 p_hwfn->cdev->num_hwfns = 2;
318 }
319 }
320
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300321 if (!p_iov->b_pre_fp_hsi &&
322 ETH_HSI_VER_MINOR &&
Yuval Mintz1fe614d2016-06-05 13:11:11 +0300323 (resp->pfdev_info.minor_fp_hsi < ETH_HSI_VER_MINOR)) {
324 DP_INFO(p_hwfn,
325 "PF is using older fastpath HSI; %02x.%02x is configured\n",
326 ETH_HSI_VER_MAJOR, resp->pfdev_info.minor_fp_hsi);
327 }
328
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300329exit:
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300330 qed_vf_pf_req_end(p_hwfn, rc);
331
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300332 return rc;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300333}
334
335int qed_vf_hw_prepare(struct qed_hwfn *p_hwfn)
336{
337 struct qed_vf_iov *p_iov;
338 u32 reg;
339
340 /* Set number of hwfns - might be overriden once leading hwfn learns
341 * actual configuration from PF.
342 */
343 if (IS_LEAD_HWFN(p_hwfn))
344 p_hwfn->cdev->num_hwfns = 1;
345
346 /* Set the doorbell bar. Assumption: regview is set */
347 p_hwfn->doorbells = (u8 __iomem *)p_hwfn->regview +
348 PXP_VF_BAR0_START_DQ;
349
350 reg = PXP_VF_BAR0_ME_OPAQUE_ADDRESS;
351 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg);
352
353 reg = PXP_VF_BAR0_ME_CONCRETE_ADDRESS;
354 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);
355
356 /* Allocate vf sriov info */
357 p_iov = kzalloc(sizeof(*p_iov), GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700358 if (!p_iov)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300359 return -ENOMEM;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300360
361 /* Allocate vf2pf msg */
362 p_iov->vf2pf_request = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
363 sizeof(union vfpf_tlvs),
364 &p_iov->vf2pf_request_phys,
365 GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700366 if (!p_iov->vf2pf_request)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300367 goto free_p_iov;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300368
369 p_iov->pf2vf_reply = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
370 sizeof(union pfvf_tlvs),
371 &p_iov->pf2vf_reply_phys,
372 GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700373 if (!p_iov->pf2vf_reply)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300374 goto free_vf2pf_request;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300375
376 DP_VERBOSE(p_hwfn,
377 QED_MSG_IOV,
378 "VF's Request mailbox [%p virt 0x%llx phys], Response mailbox [%p virt 0x%llx phys]\n",
379 p_iov->vf2pf_request,
380 (u64) p_iov->vf2pf_request_phys,
381 p_iov->pf2vf_reply, (u64)p_iov->pf2vf_reply_phys);
382
383 /* Allocate Bulletin board */
384 p_iov->bulletin.size = sizeof(struct qed_bulletin_content);
385 p_iov->bulletin.p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
386 p_iov->bulletin.size,
387 &p_iov->bulletin.phys,
388 GFP_KERNEL);
389 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
390 "VF's bulletin Board [%p virt 0x%llx phys 0x%08x bytes]\n",
391 p_iov->bulletin.p_virt,
392 (u64)p_iov->bulletin.phys, p_iov->bulletin.size);
393
394 mutex_init(&p_iov->mutex);
395
396 p_hwfn->vf_iov_info = p_iov;
397
398 p_hwfn->hw_info.personality = QED_PCI_ETH;
399
400 return qed_vf_pf_acquire(p_hwfn);
401
402free_vf2pf_request:
403 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
404 sizeof(union vfpf_tlvs),
405 p_iov->vf2pf_request, p_iov->vf2pf_request_phys);
406free_p_iov:
407 kfree(p_iov);
408
409 return -ENOMEM;
410}
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300411#define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
412#define MSTORM_QZONE_START(dev) (TSTORM_QZONE_START + \
413 (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300414
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200415int
416qed_vf_pf_rxq_start(struct qed_hwfn *p_hwfn,
417 struct qed_queue_cid *p_cid,
418 u16 bd_max_bytes,
419 dma_addr_t bd_chain_phys_addr,
420 dma_addr_t cqe_pbl_addr,
421 u16 cqe_pbl_size, void __iomem **pp_prod)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300422{
423 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
424 struct pfvf_start_queue_resp_tlv *resp;
425 struct vfpf_start_rxq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200426 u8 rx_qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300427 int rc;
428
429 /* clear mailbox and prep first tlv */
430 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_RXQ, sizeof(*req));
431
432 req->rx_qid = rx_qid;
433 req->cqe_pbl_addr = cqe_pbl_addr;
434 req->cqe_pbl_size = cqe_pbl_size;
435 req->rxq_addr = bd_chain_phys_addr;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200436 req->hw_sb = p_cid->rel.sb;
437 req->sb_index = p_cid->rel.sb_idx;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300438 req->bd_max_bytes = bd_max_bytes;
439 req->stat_id = -1;
440
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300441 /* If PF is legacy, we'll need to calculate producers ourselves
442 * as well as clean them.
443 */
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200444 if (p_iov->b_pre_fp_hsi) {
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300445 u8 hw_qid = p_iov->acquire_resp.resc.hw_qid[rx_qid];
446 u32 init_prod_val = 0;
447
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200448 *pp_prod = (u8 __iomem *)
449 p_hwfn->regview +
450 MSTORM_QZONE_START(p_hwfn->cdev) +
451 hw_qid * MSTORM_QZONE_SIZE;
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300452
453 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
454 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
455 (u32 *)(&init_prod_val));
456 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300457 /* add list termination tlv */
458 qed_add_tlv(p_hwfn, &p_iov->offset,
459 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
460
461 resp = &p_iov->pf2vf_reply->queue_start;
462 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
463 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300464 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300465
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300466 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
467 rc = -EINVAL;
468 goto exit;
469 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300470
471 /* Learn the address of the producer from the response */
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200472 if (!p_iov->b_pre_fp_hsi) {
Yuval Mintzb21290b2016-07-27 14:45:21 +0300473 u32 init_prod_val = 0;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300474
475 *pp_prod = (u8 __iomem *)p_hwfn->regview + resp->offset;
476 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
477 "Rxq[0x%02x]: producer at %p [offset 0x%08x]\n",
478 rx_qid, *pp_prod, resp->offset);
479
480 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
Yuval Mintzb21290b2016-07-27 14:45:21 +0300481 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300482 (u32 *)&init_prod_val);
483 }
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300484exit:
485 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300486
487 return rc;
488}
489
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200490int qed_vf_pf_rxq_stop(struct qed_hwfn *p_hwfn,
491 struct qed_queue_cid *p_cid, bool cqe_completion)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300492{
493 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
494 struct vfpf_stop_rxqs_tlv *req;
495 struct pfvf_def_resp_tlv *resp;
496 int rc;
497
498 /* clear mailbox and prep first tlv */
499 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_RXQS, sizeof(*req));
500
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200501 req->rx_qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300502 req->num_rxqs = 1;
503 req->cqe_completion = cqe_completion;
504
505 /* add list termination tlv */
506 qed_add_tlv(p_hwfn, &p_iov->offset,
507 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
508
509 resp = &p_iov->pf2vf_reply->default_resp;
510 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
511 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300512 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300513
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300514 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
515 rc = -EINVAL;
516 goto exit;
517 }
518
519exit:
520 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300521
522 return rc;
523}
524
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200525int
526qed_vf_pf_txq_start(struct qed_hwfn *p_hwfn,
527 struct qed_queue_cid *p_cid,
528 dma_addr_t pbl_addr,
529 u16 pbl_size, void __iomem **pp_doorbell)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300530{
531 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
Yuval Mintz5040acf2016-06-05 13:11:14 +0300532 struct pfvf_start_queue_resp_tlv *resp;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300533 struct vfpf_start_txq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200534 u16 qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300535 int rc;
536
537 /* clear mailbox and prep first tlv */
538 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_TXQ, sizeof(*req));
539
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200540 req->tx_qid = qid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300541
542 /* Tx */
543 req->pbl_addr = pbl_addr;
544 req->pbl_size = pbl_size;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200545 req->hw_sb = p_cid->rel.sb;
546 req->sb_index = p_cid->rel.sb_idx;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300547
548 /* add list termination tlv */
549 qed_add_tlv(p_hwfn, &p_iov->offset,
550 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
551
Yuval Mintz5040acf2016-06-05 13:11:14 +0300552 resp = &p_iov->pf2vf_reply->queue_start;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300553 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
554 if (rc)
Yuval Mintz5040acf2016-06-05 13:11:14 +0300555 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300556
Yuval Mintz5040acf2016-06-05 13:11:14 +0300557 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
558 rc = -EINVAL;
559 goto exit;
560 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300561
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200562 /* Modern PFs provide the actual offsets, while legacy
563 * provided only the queue id.
564 */
565 if (!p_iov->b_pre_fp_hsi) {
566 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells + resp->offset;
567 } else {
568 u8 cid = p_iov->acquire_resp.resc.cid[qid];
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300569
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200570 *pp_doorbell = (u8 __iomem *)p_hwfn->doorbells +
571 qed_db_addr_vf(cid,
572 DQ_DEMS_LEGACY);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300573 }
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200574
575 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
576 "Txq[0x%02x]: doorbell at %p [offset 0x%08x]\n",
577 qid, *pp_doorbell, resp->offset);
Yuval Mintz5040acf2016-06-05 13:11:14 +0300578exit:
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300579 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300580
581 return rc;
582}
583
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200584int qed_vf_pf_txq_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300585{
586 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
587 struct vfpf_stop_txqs_tlv *req;
588 struct pfvf_def_resp_tlv *resp;
589 int rc;
590
591 /* clear mailbox and prep first tlv */
592 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_TXQS, sizeof(*req));
593
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200594 req->tx_qid = p_cid->rel.queue_id;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300595 req->num_txqs = 1;
596
597 /* add list termination tlv */
598 qed_add_tlv(p_hwfn, &p_iov->offset,
599 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
600
601 resp = &p_iov->pf2vf_reply->default_resp;
602 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
603 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300604 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300605
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300606 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
607 rc = -EINVAL;
608 goto exit;
609 }
610
611exit:
612 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300613
614 return rc;
615}
616
617int qed_vf_pf_vport_start(struct qed_hwfn *p_hwfn,
618 u8 vport_id,
619 u16 mtu,
620 u8 inner_vlan_removal,
621 enum qed_tpa_mode tpa_mode,
Yuval Mintz08feecd2016-05-11 16:36:20 +0300622 u8 max_buffers_per_cqe, u8 only_untagged)
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300623{
624 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
625 struct vfpf_vport_start_tlv *req;
626 struct pfvf_def_resp_tlv *resp;
627 int rc, i;
628
629 /* clear mailbox and prep first tlv */
630 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_START, sizeof(*req));
631
632 req->mtu = mtu;
633 req->vport_id = vport_id;
634 req->inner_vlan_removal = inner_vlan_removal;
635 req->tpa_mode = tpa_mode;
636 req->max_buffers_per_cqe = max_buffers_per_cqe;
Yuval Mintz08feecd2016-05-11 16:36:20 +0300637 req->only_untagged = only_untagged;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300638
639 /* status blocks */
640 for (i = 0; i < p_hwfn->vf_iov_info->acquire_resp.resc.num_sbs; i++)
641 if (p_hwfn->sbs_info[i])
642 req->sb_addr[i] = p_hwfn->sbs_info[i]->sb_phys;
643
644 /* add list termination tlv */
645 qed_add_tlv(p_hwfn, &p_iov->offset,
646 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
647
648 resp = &p_iov->pf2vf_reply->default_resp;
649 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
650 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300651 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300652
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300653 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
654 rc = -EINVAL;
655 goto exit;
656 }
657
658exit:
659 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300660
661 return rc;
662}
663
664int qed_vf_pf_vport_stop(struct qed_hwfn *p_hwfn)
665{
666 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
667 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
668 int rc;
669
670 /* clear mailbox and prep first tlv */
671 qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_TEARDOWN,
672 sizeof(struct vfpf_first_tlv));
673
674 /* add list termination tlv */
675 qed_add_tlv(p_hwfn, &p_iov->offset,
676 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
677
678 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
679 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300680 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300681
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300682 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
683 rc = -EINVAL;
684 goto exit;
685 }
686
687exit:
688 qed_vf_pf_req_end(p_hwfn, rc);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300689
690 return rc;
691}
692
693static bool
694qed_vf_handle_vp_update_is_needed(struct qed_hwfn *p_hwfn,
695 struct qed_sp_vport_update_params *p_data,
696 u16 tlv)
697{
698 switch (tlv) {
699 case CHANNEL_TLV_VPORT_UPDATE_ACTIVATE:
700 return !!(p_data->update_vport_active_rx_flg ||
701 p_data->update_vport_active_tx_flg);
Yuval Mintz17b235c2016-05-11 16:36:18 +0300702 case CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH:
703 return !!p_data->update_tx_switching_flg;
704 case CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP:
705 return !!p_data->update_inner_vlan_removal_flg;
Yuval Mintz08feecd2016-05-11 16:36:20 +0300706 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN:
707 return !!p_data->update_accept_any_vlan_flg;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300708 case CHANNEL_TLV_VPORT_UPDATE_MCAST:
709 return !!p_data->update_approx_mcast_flg;
710 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM:
711 return !!(p_data->accept_flags.update_rx_mode_config ||
712 p_data->accept_flags.update_tx_mode_config);
713 case CHANNEL_TLV_VPORT_UPDATE_RSS:
714 return !!p_data->rss_params;
Yuval Mintz17b235c2016-05-11 16:36:18 +0300715 case CHANNEL_TLV_VPORT_UPDATE_SGE_TPA:
716 return !!p_data->sge_tpa_params;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300717 default:
718 DP_INFO(p_hwfn, "Unexpected vport-update TLV[%d]\n",
719 tlv);
720 return false;
721 }
722}
723
724static void
725qed_vf_handle_vp_update_tlvs_resp(struct qed_hwfn *p_hwfn,
726 struct qed_sp_vport_update_params *p_data)
727{
728 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
729 struct pfvf_def_resp_tlv *p_resp;
730 u16 tlv;
731
732 for (tlv = CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
733 tlv < CHANNEL_TLV_VPORT_UPDATE_MAX; tlv++) {
734 if (!qed_vf_handle_vp_update_is_needed(p_hwfn, p_data, tlv))
735 continue;
736
737 p_resp = (struct pfvf_def_resp_tlv *)
738 qed_iov_search_list_tlvs(p_hwfn, p_iov->pf2vf_reply,
739 tlv);
740 if (p_resp && p_resp->hdr.status)
741 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
742 "TLV[%d] Configuration %s\n",
743 tlv,
744 (p_resp && p_resp->hdr.status) ? "succeeded"
745 : "failed");
746 }
747}
748
749int qed_vf_pf_vport_update(struct qed_hwfn *p_hwfn,
750 struct qed_sp_vport_update_params *p_params)
751{
752 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
753 struct vfpf_vport_update_tlv *req;
754 struct pfvf_def_resp_tlv *resp;
755 u8 update_rx, update_tx;
756 u32 resp_size = 0;
757 u16 size, tlv;
758 int rc;
759
760 resp = &p_iov->pf2vf_reply->default_resp;
761 resp_size = sizeof(*resp);
762
763 update_rx = p_params->update_vport_active_rx_flg;
764 update_tx = p_params->update_vport_active_tx_flg;
765
766 /* clear mailbox and prep header tlv */
767 qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_UPDATE, sizeof(*req));
768
769 /* Prepare extended tlvs */
770 if (update_rx || update_tx) {
771 struct vfpf_vport_update_activate_tlv *p_act_tlv;
772
773 size = sizeof(struct vfpf_vport_update_activate_tlv);
774 p_act_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
775 CHANNEL_TLV_VPORT_UPDATE_ACTIVATE,
776 size);
777 resp_size += sizeof(struct pfvf_def_resp_tlv);
778
779 if (update_rx) {
780 p_act_tlv->update_rx = update_rx;
781 p_act_tlv->active_rx = p_params->vport_active_rx_flg;
782 }
783
784 if (update_tx) {
785 p_act_tlv->update_tx = update_tx;
786 p_act_tlv->active_tx = p_params->vport_active_tx_flg;
787 }
788 }
789
Yuval Mintz831bfb0e2016-05-11 16:36:25 +0300790 if (p_params->update_tx_switching_flg) {
791 struct vfpf_vport_update_tx_switch_tlv *p_tx_switch_tlv;
792
793 size = sizeof(struct vfpf_vport_update_tx_switch_tlv);
794 tlv = CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
795 p_tx_switch_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
796 tlv, size);
797 resp_size += sizeof(struct pfvf_def_resp_tlv);
798
799 p_tx_switch_tlv->tx_switching = p_params->tx_switching_flg;
800 }
801
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300802 if (p_params->update_approx_mcast_flg) {
803 struct vfpf_vport_update_mcast_bin_tlv *p_mcast_tlv;
804
805 size = sizeof(struct vfpf_vport_update_mcast_bin_tlv);
806 p_mcast_tlv = qed_add_tlv(p_hwfn, &p_iov->offset,
807 CHANNEL_TLV_VPORT_UPDATE_MCAST, size);
808 resp_size += sizeof(struct pfvf_def_resp_tlv);
809
810 memcpy(p_mcast_tlv->bins, p_params->bins,
811 sizeof(unsigned long) * ETH_MULTICAST_MAC_BINS_IN_REGS);
812 }
813
814 update_rx = p_params->accept_flags.update_rx_mode_config;
815 update_tx = p_params->accept_flags.update_tx_mode_config;
816
817 if (update_rx || update_tx) {
818 struct vfpf_vport_update_accept_param_tlv *p_accept_tlv;
819
820 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
821 size = sizeof(struct vfpf_vport_update_accept_param_tlv);
822 p_accept_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, tlv, size);
823 resp_size += sizeof(struct pfvf_def_resp_tlv);
824
825 if (update_rx) {
826 p_accept_tlv->update_rx_mode = update_rx;
827 p_accept_tlv->rx_accept_filter =
828 p_params->accept_flags.rx_accept_filter;
829 }
830
831 if (update_tx) {
832 p_accept_tlv->update_tx_mode = update_tx;
833 p_accept_tlv->tx_accept_filter =
834 p_params->accept_flags.tx_accept_filter;
835 }
836 }
837
838 if (p_params->rss_params) {
839 struct qed_rss_params *rss_params = p_params->rss_params;
840 struct vfpf_vport_update_rss_tlv *p_rss_tlv;
841
842 size = sizeof(struct vfpf_vport_update_rss_tlv);
843 p_rss_tlv = qed_add_tlv(p_hwfn,
844 &p_iov->offset,
845 CHANNEL_TLV_VPORT_UPDATE_RSS, size);
846 resp_size += sizeof(struct pfvf_def_resp_tlv);
847
848 if (rss_params->update_rss_config)
849 p_rss_tlv->update_rss_flags |=
850 VFPF_UPDATE_RSS_CONFIG_FLAG;
851 if (rss_params->update_rss_capabilities)
852 p_rss_tlv->update_rss_flags |=
853 VFPF_UPDATE_RSS_CAPS_FLAG;
854 if (rss_params->update_rss_ind_table)
855 p_rss_tlv->update_rss_flags |=
856 VFPF_UPDATE_RSS_IND_TABLE_FLAG;
857 if (rss_params->update_rss_key)
858 p_rss_tlv->update_rss_flags |= VFPF_UPDATE_RSS_KEY_FLAG;
859
860 p_rss_tlv->rss_enable = rss_params->rss_enable;
861 p_rss_tlv->rss_caps = rss_params->rss_caps;
862 p_rss_tlv->rss_table_size_log = rss_params->rss_table_size_log;
863 memcpy(p_rss_tlv->rss_ind_table, rss_params->rss_ind_table,
864 sizeof(rss_params->rss_ind_table));
865 memcpy(p_rss_tlv->rss_key, rss_params->rss_key,
866 sizeof(rss_params->rss_key));
867 }
868
Yuval Mintz08feecd2016-05-11 16:36:20 +0300869 if (p_params->update_accept_any_vlan_flg) {
870 struct vfpf_vport_update_accept_any_vlan_tlv *p_any_vlan_tlv;
871
872 size = sizeof(struct vfpf_vport_update_accept_any_vlan_tlv);
873 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
874 p_any_vlan_tlv = qed_add_tlv(p_hwfn, &p_iov->offset, tlv, size);
875
876 resp_size += sizeof(struct pfvf_def_resp_tlv);
877 p_any_vlan_tlv->accept_any_vlan = p_params->accept_any_vlan;
878 p_any_vlan_tlv->update_accept_any_vlan_flg =
879 p_params->update_accept_any_vlan_flg;
880 }
881
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300882 /* add list termination tlv */
883 qed_add_tlv(p_hwfn, &p_iov->offset,
884 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
885
886 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, resp_size);
887 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300888 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300889
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300890 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
891 rc = -EINVAL;
892 goto exit;
893 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300894
895 qed_vf_handle_vp_update_tlvs_resp(p_hwfn, p_params);
896
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300897exit:
898 qed_vf_pf_req_end(p_hwfn, rc);
899
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300900 return rc;
901}
902
Yuval Mintz0b55e272016-05-11 16:36:15 +0300903int qed_vf_pf_reset(struct qed_hwfn *p_hwfn)
904{
905 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
906 struct pfvf_def_resp_tlv *resp;
907 struct vfpf_first_tlv *req;
908 int rc;
909
910 /* clear mailbox and prep first tlv */
911 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_CLOSE, sizeof(*req));
912
913 /* add list termination tlv */
914 qed_add_tlv(p_hwfn, &p_iov->offset,
915 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
916
917 resp = &p_iov->pf2vf_reply->default_resp;
918 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
919 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300920 goto exit;
Yuval Mintz0b55e272016-05-11 16:36:15 +0300921
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300922 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
923 rc = -EAGAIN;
924 goto exit;
925 }
Yuval Mintz0b55e272016-05-11 16:36:15 +0300926
927 p_hwfn->b_int_enabled = 0;
928
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300929exit:
930 qed_vf_pf_req_end(p_hwfn, rc);
931
932 return rc;
Yuval Mintz0b55e272016-05-11 16:36:15 +0300933}
934
935int qed_vf_pf_release(struct qed_hwfn *p_hwfn)
936{
937 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
938 struct pfvf_def_resp_tlv *resp;
939 struct vfpf_first_tlv *req;
940 u32 size;
941 int rc;
942
943 /* clear mailbox and prep first tlv */
944 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_RELEASE, sizeof(*req));
945
946 /* add list termination tlv */
947 qed_add_tlv(p_hwfn, &p_iov->offset,
948 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
949
950 resp = &p_iov->pf2vf_reply->default_resp;
951 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
952
953 if (!rc && resp->hdr.status != PFVF_STATUS_SUCCESS)
954 rc = -EAGAIN;
955
Yuval Mintzb0bccb62016-08-22 13:25:12 +0300956 qed_vf_pf_req_end(p_hwfn, rc);
957
Yuval Mintz0b55e272016-05-11 16:36:15 +0300958 p_hwfn->b_int_enabled = 0;
959
960 if (p_iov->vf2pf_request)
961 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
962 sizeof(union vfpf_tlvs),
963 p_iov->vf2pf_request,
964 p_iov->vf2pf_request_phys);
965 if (p_iov->pf2vf_reply)
966 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
967 sizeof(union pfvf_tlvs),
968 p_iov->pf2vf_reply, p_iov->pf2vf_reply_phys);
969
970 if (p_iov->bulletin.p_virt) {
971 size = sizeof(struct qed_bulletin_content);
972 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
973 size,
974 p_iov->bulletin.p_virt, p_iov->bulletin.phys);
975 }
976
977 kfree(p_hwfn->vf_iov_info);
978 p_hwfn->vf_iov_info = NULL;
979
980 return rc;
981}
982
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300983void qed_vf_pf_filter_mcast(struct qed_hwfn *p_hwfn,
984 struct qed_filter_mcast *p_filter_cmd)
985{
986 struct qed_sp_vport_update_params sp_params;
987 int i;
988
989 memset(&sp_params, 0, sizeof(sp_params));
990 sp_params.update_approx_mcast_flg = 1;
991
992 if (p_filter_cmd->opcode == QED_FILTER_ADD) {
993 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
994 u32 bit;
995
996 bit = qed_mcast_bin_from_mac(p_filter_cmd->mac[i]);
997 __set_bit(bit, sp_params.bins);
998 }
999 }
1000
1001 qed_vf_pf_vport_update(p_hwfn, &sp_params);
1002}
1003
1004int qed_vf_pf_filter_ucast(struct qed_hwfn *p_hwfn,
1005 struct qed_filter_ucast *p_ucast)
1006{
1007 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1008 struct vfpf_ucast_filter_tlv *req;
1009 struct pfvf_def_resp_tlv *resp;
1010 int rc;
1011
1012 /* clear mailbox and prep first tlv */
1013 req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_UCAST_FILTER, sizeof(*req));
1014 req->opcode = (u8) p_ucast->opcode;
1015 req->type = (u8) p_ucast->type;
1016 memcpy(req->mac, p_ucast->mac, ETH_ALEN);
1017 req->vlan = p_ucast->vlan;
1018
1019 /* add list termination tlv */
1020 qed_add_tlv(p_hwfn, &p_iov->offset,
1021 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1022
1023 resp = &p_iov->pf2vf_reply->default_resp;
1024 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1025 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001026 goto exit;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001027
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001028 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1029 rc = -EAGAIN;
1030 goto exit;
1031 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001032
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001033exit:
1034 qed_vf_pf_req_end(p_hwfn, rc);
1035
1036 return rc;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001037}
1038
Yuval Mintz0b55e272016-05-11 16:36:15 +03001039int qed_vf_pf_int_cleanup(struct qed_hwfn *p_hwfn)
1040{
1041 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1042 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
1043 int rc;
1044
1045 /* clear mailbox and prep first tlv */
1046 qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_INT_CLEANUP,
1047 sizeof(struct vfpf_first_tlv));
1048
1049 /* add list termination tlv */
1050 qed_add_tlv(p_hwfn, &p_iov->offset,
1051 CHANNEL_TLV_LIST_END, sizeof(struct channel_list_end_tlv));
1052
1053 rc = qed_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1054 if (rc)
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001055 goto exit;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001056
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001057 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1058 rc = -EINVAL;
1059 goto exit;
1060 }
Yuval Mintz0b55e272016-05-11 16:36:15 +03001061
Yuval Mintzb0bccb62016-08-22 13:25:12 +03001062exit:
1063 qed_vf_pf_req_end(p_hwfn, rc);
1064
1065 return rc;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001066}
1067
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001068u16 qed_vf_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
1069{
1070 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1071
1072 if (!p_iov) {
1073 DP_NOTICE(p_hwfn, "vf_sriov_info isn't initialized\n");
1074 return 0;
1075 }
1076
1077 return p_iov->acquire_resp.resc.hw_sbs[sb_id].hw_sb_id;
1078}
1079
Yuval Mintz36558c32016-05-11 16:36:17 +03001080int qed_vf_read_bulletin(struct qed_hwfn *p_hwfn, u8 *p_change)
1081{
1082 struct qed_vf_iov *p_iov = p_hwfn->vf_iov_info;
1083 struct qed_bulletin_content shadow;
1084 u32 crc, crc_size;
1085
1086 crc_size = sizeof(p_iov->bulletin.p_virt->crc);
1087 *p_change = 0;
1088
1089 /* Need to guarantee PF is not in the middle of writing it */
1090 memcpy(&shadow, p_iov->bulletin.p_virt, p_iov->bulletin.size);
1091
1092 /* If version did not update, no need to do anything */
1093 if (shadow.version == p_iov->bulletin_shadow.version)
1094 return 0;
1095
1096 /* Verify the bulletin we see is valid */
1097 crc = crc32(0, (u8 *)&shadow + crc_size,
1098 p_iov->bulletin.size - crc_size);
1099 if (crc != shadow.crc)
1100 return -EAGAIN;
1101
1102 /* Set the shadow bulletin and process it */
1103 memcpy(&p_iov->bulletin_shadow, &shadow, p_iov->bulletin.size);
1104
1105 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1106 "Read a bulletin update %08x\n", shadow.version);
1107
1108 *p_change = 1;
1109
1110 return 0;
1111}
1112
1113void __qed_vf_get_link_params(struct qed_hwfn *p_hwfn,
1114 struct qed_mcp_link_params *p_params,
1115 struct qed_bulletin_content *p_bulletin)
1116{
1117 memset(p_params, 0, sizeof(*p_params));
1118
1119 p_params->speed.autoneg = p_bulletin->req_autoneg;
1120 p_params->speed.advertised_speeds = p_bulletin->req_adv_speed;
1121 p_params->speed.forced_speed = p_bulletin->req_forced_speed;
1122 p_params->pause.autoneg = p_bulletin->req_autoneg_pause;
1123 p_params->pause.forced_rx = p_bulletin->req_forced_rx;
1124 p_params->pause.forced_tx = p_bulletin->req_forced_tx;
1125 p_params->loopback_mode = p_bulletin->req_loopback;
1126}
1127
1128void qed_vf_get_link_params(struct qed_hwfn *p_hwfn,
1129 struct qed_mcp_link_params *params)
1130{
1131 __qed_vf_get_link_params(p_hwfn, params,
1132 &(p_hwfn->vf_iov_info->bulletin_shadow));
1133}
1134
1135void __qed_vf_get_link_state(struct qed_hwfn *p_hwfn,
1136 struct qed_mcp_link_state *p_link,
1137 struct qed_bulletin_content *p_bulletin)
1138{
1139 memset(p_link, 0, sizeof(*p_link));
1140
1141 p_link->link_up = p_bulletin->link_up;
1142 p_link->speed = p_bulletin->speed;
1143 p_link->full_duplex = p_bulletin->full_duplex;
1144 p_link->an = p_bulletin->autoneg;
1145 p_link->an_complete = p_bulletin->autoneg_complete;
1146 p_link->parallel_detection = p_bulletin->parallel_detection;
1147 p_link->pfc_enabled = p_bulletin->pfc_enabled;
1148 p_link->partner_adv_speed = p_bulletin->partner_adv_speed;
1149 p_link->partner_tx_flow_ctrl_en = p_bulletin->partner_tx_flow_ctrl_en;
1150 p_link->partner_rx_flow_ctrl_en = p_bulletin->partner_rx_flow_ctrl_en;
1151 p_link->partner_adv_pause = p_bulletin->partner_adv_pause;
1152 p_link->sfp_tx_fault = p_bulletin->sfp_tx_fault;
1153}
1154
1155void qed_vf_get_link_state(struct qed_hwfn *p_hwfn,
1156 struct qed_mcp_link_state *link)
1157{
1158 __qed_vf_get_link_state(p_hwfn, link,
1159 &(p_hwfn->vf_iov_info->bulletin_shadow));
1160}
1161
1162void __qed_vf_get_link_caps(struct qed_hwfn *p_hwfn,
1163 struct qed_mcp_link_capabilities *p_link_caps,
1164 struct qed_bulletin_content *p_bulletin)
1165{
1166 memset(p_link_caps, 0, sizeof(*p_link_caps));
1167 p_link_caps->speed_capabilities = p_bulletin->capability_speed;
1168}
1169
1170void qed_vf_get_link_caps(struct qed_hwfn *p_hwfn,
1171 struct qed_mcp_link_capabilities *p_link_caps)
1172{
1173 __qed_vf_get_link_caps(p_hwfn, p_link_caps,
1174 &(p_hwfn->vf_iov_info->bulletin_shadow));
1175}
1176
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001177void qed_vf_get_num_rxqs(struct qed_hwfn *p_hwfn, u8 *num_rxqs)
1178{
1179 *num_rxqs = p_hwfn->vf_iov_info->acquire_resp.resc.num_rxqs;
1180}
1181
1182void qed_vf_get_port_mac(struct qed_hwfn *p_hwfn, u8 *port_mac)
1183{
1184 memcpy(port_mac,
1185 p_hwfn->vf_iov_info->acquire_resp.pfdev_info.port_mac, ETH_ALEN);
1186}
1187
1188void qed_vf_get_num_vlan_filters(struct qed_hwfn *p_hwfn, u8 *num_vlan_filters)
1189{
1190 struct qed_vf_iov *p_vf;
1191
1192 p_vf = p_hwfn->vf_iov_info;
1193 *num_vlan_filters = p_vf->acquire_resp.resc.num_vlan_filters;
1194}
1195
Mintz, Yuvalb0fca312016-10-31 22:26:54 +02001196void qed_vf_get_num_mac_filters(struct qed_hwfn *p_hwfn, u8 *num_mac_filters)
1197{
1198 struct qed_vf_iov *p_vf = p_hwfn->vf_iov_info;
1199
1200 *num_mac_filters = p_vf->acquire_resp.resc.num_mac_filters;
1201}
1202
Yuval Mintzeff16962016-05-11 16:36:21 +03001203bool qed_vf_check_mac(struct qed_hwfn *p_hwfn, u8 *mac)
1204{
1205 struct qed_bulletin_content *bulletin;
1206
1207 bulletin = &p_hwfn->vf_iov_info->bulletin_shadow;
1208 if (!(bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)))
1209 return true;
1210
1211 /* Forbid VF from changing a MAC enforced by PF */
1212 if (ether_addr_equal(bulletin->mac, mac))
1213 return false;
1214
1215 return false;
1216}
1217
Baoyou Xieba569472016-09-09 09:21:15 +08001218static bool qed_vf_bulletin_get_forced_mac(struct qed_hwfn *hwfn,
1219 u8 *dst_mac, u8 *p_is_forced)
Yuval Mintzeff16962016-05-11 16:36:21 +03001220{
1221 struct qed_bulletin_content *bulletin;
1222
1223 bulletin = &hwfn->vf_iov_info->bulletin_shadow;
1224
1225 if (bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)) {
1226 if (p_is_forced)
1227 *p_is_forced = 1;
1228 } else if (bulletin->valid_bitmap & (1 << VFPF_BULLETIN_MAC_ADDR)) {
1229 if (p_is_forced)
1230 *p_is_forced = 0;
1231 } else {
1232 return false;
1233 }
1234
1235 ether_addr_copy(dst_mac, bulletin->mac);
1236
1237 return true;
1238}
1239
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001240void qed_vf_get_fw_version(struct qed_hwfn *p_hwfn,
1241 u16 *fw_major, u16 *fw_minor,
1242 u16 *fw_rev, u16 *fw_eng)
1243{
1244 struct pf_vf_pfdev_info *info;
1245
1246 info = &p_hwfn->vf_iov_info->acquire_resp.pfdev_info;
1247
1248 *fw_major = info->fw_major;
1249 *fw_minor = info->fw_minor;
1250 *fw_rev = info->fw_rev;
1251 *fw_eng = info->fw_eng;
1252}
Yuval Mintz36558c32016-05-11 16:36:17 +03001253
1254static void qed_handle_bulletin_change(struct qed_hwfn *hwfn)
1255{
Yuval Mintzeff16962016-05-11 16:36:21 +03001256 struct qed_eth_cb_ops *ops = hwfn->cdev->protocol_ops.eth;
1257 u8 mac[ETH_ALEN], is_mac_exist, is_mac_forced;
1258 void *cookie = hwfn->cdev->ops_cookie;
1259
1260 is_mac_exist = qed_vf_bulletin_get_forced_mac(hwfn, mac,
1261 &is_mac_forced);
Yuval Mintzc3aaa402016-10-14 05:19:17 -04001262 if (is_mac_exist && cookie)
1263 ops->force_mac(cookie, mac, !!is_mac_forced);
Yuval Mintzeff16962016-05-11 16:36:21 +03001264
Yuval Mintz36558c32016-05-11 16:36:17 +03001265 /* Always update link configuration according to bulletin */
1266 qed_link_update(hwfn);
1267}
1268
1269void qed_iov_vf_task(struct work_struct *work)
1270{
1271 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
1272 iov_task.work);
1273 u8 change = 0;
1274
1275 if (test_and_clear_bit(QED_IOV_WQ_STOP_WQ_FLAG, &hwfn->iov_task_flags))
1276 return;
1277
1278 /* Handle bulletin board changes */
1279 qed_vf_read_bulletin(hwfn, &change);
1280 if (change)
1281 qed_handle_bulletin_change(hwfn);
1282
1283 /* As VF is polling bulletin board, need to constantly re-schedule */
1284 queue_delayed_work(hwfn->iov_wq, &hwfn->iov_task, HZ);
1285}