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gerrit-public.fairphone.software / kernel / msm-5.4 / f39b7a55a84e34e3074b168e30dc73b66e85261d / . / include / asm-powerpc / cputable.h
blob: 748bc1805da90692e0a8467cb8e362a5bda963ca [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
David Gibson3ddfbcf2005-11-10 12:56:55 +1100[diff] [blame]4#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +1000[diff] [blame]17#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +1100[diff] [blame]18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]22#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidtaa5cb0212006-03-01 15:07:07 +1100[diff] [blame]23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]25#define PPC_FEATURE_ARCH_2_05 0x00001000
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]26
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]27#define PPC_FEATURE_TRUE_LE 0x00000002
28#define PPC_FEATURE_PPC_LE 0x00000001
29
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]30#ifdef __KERNEL__
31#ifndef __ASSEMBLY__
32
33/* This structure can grow, it's real size is used by head.S code
34 * via the mkdefs mechanism.
35 */
36struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]37
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]38typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame^]39typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]40
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]41enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]42 PPC_OPROFILE_INVALID = 0,
43 PPC_OPROFILE_RS64 = 1,
44 PPC_OPROFILE_POWER4 = 2,
45 PPC_OPROFILE_G4 = 3,
46 PPC_OPROFILE_BOOKE = 4,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]47};
48
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]49struct cpu_spec {
50 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
51 unsigned int pvr_mask;
52 unsigned int pvr_value;
53
54 char *cpu_name;
55 unsigned long cpu_features; /* Kernel features */
56 unsigned int cpu_user_features; /* Userland features */
57
58 /* cache line sizes */
59 unsigned int icache_bsize;
60 unsigned int dcache_bsize;
61
62 /* number of performance monitor counters */
63 unsigned int num_pmcs;
64
65 /* this is called to initialize various CPU bits like L1 cache,
66 * BHT, SPD, etc... from head.S before branching to identify_machine
67 */
68 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame^]69 /* Used to restore cpu setup on secondary processors and at resume */
70 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]71
72 /* Used by oprofile userspace to select the right counters */
73 char *oprofile_cpu_type;
74
75 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]76 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]77
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]78 /* Bit locations inside the mmcra change */
79 unsigned long oprofile_mmcra_sihv;
80 unsigned long oprofile_mmcra_sipr;
81
82 /* Bits to clear during an oprofile exception */
83 unsigned long oprofile_mmcra_clear;
84
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]85 /* Name of processor class, for the ELF AT_PLATFORM entry */
86 char *platform;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]87};
88
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]89extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]90
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]91extern void identify_cpu(unsigned long offset, unsigned long cpu);
92extern void do_cpu_ftr_fixups(unsigned long offset);
93
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]94#endif /* __ASSEMBLY__ */
95
96/* CPU kernel features */
97
98/* Retain the 32b definitions all use bottom half of word */
99#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
100#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
101#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
102#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
103#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
104#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
105#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
106#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
107#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
108#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
109#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
110#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
111#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
112#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
113#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
114#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
115#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
116#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
117#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
118#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]119#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]120#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
121#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]122
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]123/*
124 * Add the 64-bit processor unique features in the top half of the word;
125 * on 32-bit, make the names available but defined to be 0.
126 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]127#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]128#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]129#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]130#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]131#endif
132
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]133#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
134#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
135#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
136#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
137#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
138#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
139#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
140#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
141#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
142#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
143#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
144#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
145#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
146
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]147#ifndef __ASSEMBLY__
148
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]149#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
150 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
151 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
152
153/* iSeries doesn't support large pages */
154#ifdef CONFIG_PPC_ISERIES
155#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
156#else
157#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
158#endif /* CONFIG_PPC_ISERIES */
159
160/* We only set the altivec features if the kernel was compiled with altivec
161 * support
162 */
163#ifdef CONFIG_ALTIVEC
164#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
165#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
166#else
167#define CPU_FTR_ALTIVEC_COMP 0
168#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
169#endif
170
171/* We need to mark all pages as being coherent if we're SMP or we
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]172 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
173 * it for PCI "streaming/prefetch" to work properly.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]174 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]175#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
176 || defined(CONFIG_PPC_83xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]177#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
178#else
179#define CPU_FTR_COMMON 0
180#endif
181
182/* The powersave features NAP & DOZE seems to confuse BDI when
183 debugging. So if a BDI is used, disable theses
184 */
185#ifndef CONFIG_BDI_SWITCH
186#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
187#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
188#else
189#define CPU_FTR_MAYBE_CAN_DOZE 0
190#define CPU_FTR_MAYBE_CAN_NAP 0
191#endif
192
193#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
194 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
195 !defined(CONFIG_BOOKE))
196
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]197#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
198#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
199 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]200 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]201#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]202 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
203 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]204#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
205 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]206 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]207#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
208 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]209 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
210 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]211#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
212 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]213 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
214 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]215#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
216 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
217 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]218 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]219#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
220 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
221 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]222 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]223#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
224 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
225 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]226 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]227#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
228 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
229 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]230 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]231#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
232 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
233 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]234 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]235#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
236 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
237 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]238 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]239#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
240 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
241 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]242 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]243#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
244 CPU_FTR_USE_TB | \
245 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
246 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
247 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]248 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]249#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
250 CPU_FTR_USE_TB | \
251 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
252 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]253 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]254#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
255 CPU_FTR_USE_TB | \
256 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
257 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]258 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]259#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
260 CPU_FTR_USE_TB | \
261 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
262 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
263 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]264 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]265#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
266 CPU_FTR_USE_TB | \
267 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
268 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
269 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]270 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]271#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
272 CPU_FTR_USE_TB | \
273 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
274 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
275 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]276 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]277#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
278 CPU_FTR_USE_TB | \
279 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
280 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
281 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]282 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]283#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
284 CPU_FTR_USE_TB | \
285 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
286 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
287 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]288 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]289#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
290 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
291#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
292 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
293#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
294 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
295 CPU_FTR_COMMON)
296#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
297 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]298#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
299#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
300 CPU_FTR_NODSISRALIGN)
301#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
302 CPU_FTR_NODSISRALIGN)
303#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
304#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
305 CPU_FTR_NODSISRALIGN)
306#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
307 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
308#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]309#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]310#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]311 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]312#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
313 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
314 CPU_FTR_MMCRA | CPU_FTR_CTRL)
315#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
316 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA)
317#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
318 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
319 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
320#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
321 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
322 CPU_FTR_MMCRA | CPU_FTR_SMT | \
323 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]324 CPU_FTR_PURR)
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]325#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
326 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
327 CPU_FTR_MMCRA | CPU_FTR_SMT | \
328 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]329 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]330#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
331 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
332 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Arnd Bergmannce221982006-06-15 15:09:16 +0200[diff] [blame]333 CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]334#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
335 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]336#endif
337
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]338#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]339#define CPU_FTRS_POSSIBLE \
340 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]341 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
342 CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]343#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]344enum {
345 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]346#if CLASSIC_PPC
347 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
348 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
349 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
350 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
351 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
352 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
353 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
354 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
355#else
356 CPU_FTRS_GENERIC_32 |
357#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]358#ifdef CONFIG_8xx
359 CPU_FTRS_8XX |
360#endif
361#ifdef CONFIG_40x
362 CPU_FTRS_40X |
363#endif
364#ifdef CONFIG_44x
365 CPU_FTRS_44X |
366#endif
367#ifdef CONFIG_E200
368 CPU_FTRS_E200 |
369#endif
370#ifdef CONFIG_E500
371 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
372#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]373 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]374};
375#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]376
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]377#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]378#define CPU_FTRS_ALWAYS \
379 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]380 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
381 CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]382#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]383enum {
384 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]385#if CLASSIC_PPC
386 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
387 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
388 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
389 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
390 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
391 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
392 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
393 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
394#else
395 CPU_FTRS_GENERIC_32 &
396#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]397#ifdef CONFIG_8xx
398 CPU_FTRS_8XX &
399#endif
400#ifdef CONFIG_40x
401 CPU_FTRS_40X &
402#endif
403#ifdef CONFIG_44x
404 CPU_FTRS_44X &
405#endif
406#ifdef CONFIG_E200
407 CPU_FTRS_E200 &
408#endif
409#ifdef CONFIG_E500
410 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
411#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]412 CPU_FTRS_POSSIBLE,
413};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]414#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]415
416static inline int cpu_has_feature(unsigned long feature)
417{
418 return (CPU_FTRS_ALWAYS & feature) ||
419 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]420 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]421 & feature);
422}
423
424#endif /* !__ASSEMBLY__ */
425
426#ifdef __ASSEMBLY__
427
428#define BEGIN_FTR_SECTION 98:
429
430#ifndef __powerpc64__
431#define END_FTR_SECTION(msk, val) \
43299: \
433 .section __ftr_fixup,"a"; \
434 .align 2; \
435 .long msk; \
436 .long val; \
437 .long 98b; \
438 .long 99b; \
439 .previous
440#else /* __powerpc64__ */
441#define END_FTR_SECTION(msk, val) \
44299: \
443 .section __ftr_fixup,"a"; \
444 .align 3; \
445 .llong msk; \
446 .llong val; \
447 .llong 98b; \
448 .llong 99b; \
449 .previous
450#endif /* __powerpc64__ */
451
452#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
453#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
454#endif /* __ASSEMBLY__ */
455
456#endif /* __KERNEL__ */
457#endif /* __ASM_POWERPC_CPUTABLE_H */