blob: b22baf5e5daf861ecaf164f1df607e975d7cdc4e [file] [log] [blame]
Yuval Mintz32a47e72016-05-11 16:36:12 +03001/* QLogic qed NIC Driver
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02002 * Copyright (c) 2015-2017 QLogic Corporation
Yuval Mintz32a47e72016-05-11 16:36:12 +03003 *
Mintz, Yuvale8f1cb52017-01-01 13:57:00 +02004 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Yuval Mintz32a47e72016-05-11 16:36:12 +030031 */
32
Yuval Mintzdacd88d2016-05-11 16:36:16 +030033#include <linux/etherdevice.h>
Yuval Mintz36558c32016-05-11 16:36:17 +030034#include <linux/crc32.h>
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +020035#include <linux/vmalloc.h>
Yuval Mintz0b55e272016-05-11 16:36:15 +030036#include <linux/qed/qed_iov_if.h>
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030037#include "qed_cxt.h"
38#include "qed_hsi.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030039#include "qed_hw.h"
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030040#include "qed_init_ops.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030041#include "qed_int.h"
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030042#include "qed_mcp.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030043#include "qed_reg_addr.h"
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030044#include "qed_sp.h"
Yuval Mintz32a47e72016-05-11 16:36:12 +030045#include "qed_sriov.h"
46#include "qed_vf.h"
47
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030048/* IOV ramrods */
Yuval Mintz1fe614d2016-06-05 13:11:11 +030049static int qed_sp_vf_start(struct qed_hwfn *p_hwfn, struct qed_vf_info *p_vf)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030050{
51 struct vf_start_ramrod_data *p_ramrod = NULL;
52 struct qed_spq_entry *p_ent = NULL;
53 struct qed_sp_init_data init_data;
54 int rc = -EINVAL;
Yuval Mintz1fe614d2016-06-05 13:11:11 +030055 u8 fp_minor;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030056
57 /* Get SPQ entry */
58 memset(&init_data, 0, sizeof(init_data));
59 init_data.cid = qed_spq_get_cid(p_hwfn);
Yuval Mintz1fe614d2016-06-05 13:11:11 +030060 init_data.opaque_fid = p_vf->opaque_fid;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030061 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
62
63 rc = qed_sp_init_request(p_hwfn, &p_ent,
64 COMMON_RAMROD_VF_START,
65 PROTOCOLID_COMMON, &init_data);
66 if (rc)
67 return rc;
68
69 p_ramrod = &p_ent->ramrod.vf_start;
70
Yuval Mintz1fe614d2016-06-05 13:11:11 +030071 p_ramrod->vf_id = GET_FIELD(p_vf->concrete_fid, PXP_CONCRETE_FID_VFID);
72 p_ramrod->opaque_fid = cpu_to_le16(p_vf->opaque_fid);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +030073
Yuval Mintz1fe614d2016-06-05 13:11:11 +030074 switch (p_hwfn->hw_info.personality) {
75 case QED_PCI_ETH:
76 p_ramrod->personality = PERSONALITY_ETH;
77 break;
78 case QED_PCI_ETH_ROCE:
79 p_ramrod->personality = PERSONALITY_RDMA_AND_ETH;
80 break;
81 default:
82 DP_NOTICE(p_hwfn, "Unknown VF personality %d\n",
83 p_hwfn->hw_info.personality);
84 return -EINVAL;
85 }
86
87 fp_minor = p_vf->acquire.vfdev_info.eth_fp_hsi_minor;
Yuval Mintza044df82016-08-22 13:25:09 +030088 if (fp_minor > ETH_HSI_VER_MINOR &&
89 fp_minor != ETH_HSI_VER_NO_PKT_LEN_TUNN) {
Yuval Mintz1fe614d2016-06-05 13:11:11 +030090 DP_VERBOSE(p_hwfn,
91 QED_MSG_IOV,
92 "VF [%d] - Requested fp hsi %02x.%02x which is slightly newer than PF's %02x.%02x; Configuring PFs version\n",
93 p_vf->abs_vf_id,
94 ETH_HSI_VER_MAJOR,
95 fp_minor, ETH_HSI_VER_MAJOR, ETH_HSI_VER_MINOR);
96 fp_minor = ETH_HSI_VER_MINOR;
97 }
98
Yuval Mintz351a4ded2016-06-02 10:23:29 +030099 p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
Yuval Mintz1fe614d2016-06-05 13:11:11 +0300100 p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = fp_minor;
101
102 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
103 "VF[%d] - Starting using HSI %02x.%02x\n",
104 p_vf->abs_vf_id, ETH_HSI_VER_MAJOR, fp_minor);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300105
106 return qed_spq_post(p_hwfn, p_ent, NULL);
107}
108
Yuval Mintz0b55e272016-05-11 16:36:15 +0300109static int qed_sp_vf_stop(struct qed_hwfn *p_hwfn,
110 u32 concrete_vfid, u16 opaque_vfid)
111{
112 struct vf_stop_ramrod_data *p_ramrod = NULL;
113 struct qed_spq_entry *p_ent = NULL;
114 struct qed_sp_init_data init_data;
115 int rc = -EINVAL;
116
117 /* Get SPQ entry */
118 memset(&init_data, 0, sizeof(init_data));
119 init_data.cid = qed_spq_get_cid(p_hwfn);
120 init_data.opaque_fid = opaque_vfid;
121 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
122
123 rc = qed_sp_init_request(p_hwfn, &p_ent,
124 COMMON_RAMROD_VF_STOP,
125 PROTOCOLID_COMMON, &init_data);
126 if (rc)
127 return rc;
128
129 p_ramrod = &p_ent->ramrod.vf_stop;
130
131 p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
132
133 return qed_spq_post(p_hwfn, p_ent, NULL);
134}
135
Baoyou Xieba569472016-09-09 09:21:15 +0800136static bool qed_iov_is_valid_vfid(struct qed_hwfn *p_hwfn,
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400137 int rel_vf_id,
138 bool b_enabled_only, bool b_non_malicious)
Yuval Mintz32a47e72016-05-11 16:36:12 +0300139{
140 if (!p_hwfn->pf_iov_info) {
141 DP_NOTICE(p_hwfn->cdev, "No iov info\n");
142 return false;
143 }
144
145 if ((rel_vf_id >= p_hwfn->cdev->p_iov_info->total_vfs) ||
146 (rel_vf_id < 0))
147 return false;
148
149 if ((!p_hwfn->pf_iov_info->vfs_array[rel_vf_id].b_init) &&
150 b_enabled_only)
151 return false;
152
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400153 if ((p_hwfn->pf_iov_info->vfs_array[rel_vf_id].b_malicious) &&
154 b_non_malicious)
155 return false;
156
Yuval Mintz32a47e72016-05-11 16:36:12 +0300157 return true;
158}
159
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300160static struct qed_vf_info *qed_iov_get_vf_info(struct qed_hwfn *p_hwfn,
161 u16 relative_vf_id,
162 bool b_enabled_only)
163{
164 struct qed_vf_info *vf = NULL;
165
166 if (!p_hwfn->pf_iov_info) {
167 DP_NOTICE(p_hwfn->cdev, "No iov info\n");
168 return NULL;
169 }
170
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400171 if (qed_iov_is_valid_vfid(p_hwfn, relative_vf_id,
172 b_enabled_only, false))
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300173 vf = &p_hwfn->pf_iov_info->vfs_array[relative_vf_id];
174 else
175 DP_ERR(p_hwfn, "qed_iov_get_vf_info: VF[%d] is not enabled\n",
176 relative_vf_id);
177
178 return vf;
179}
180
Yuval Mintz41086462016-06-05 13:11:13 +0300181static bool qed_iov_validate_rxq(struct qed_hwfn *p_hwfn,
182 struct qed_vf_info *p_vf, u16 rx_qid)
183{
184 if (rx_qid >= p_vf->num_rxqs)
185 DP_VERBOSE(p_hwfn,
186 QED_MSG_IOV,
187 "VF[0x%02x] - can't touch Rx queue[%04x]; Only 0x%04x are allocated\n",
188 p_vf->abs_vf_id, rx_qid, p_vf->num_rxqs);
189 return rx_qid < p_vf->num_rxqs;
190}
191
192static bool qed_iov_validate_txq(struct qed_hwfn *p_hwfn,
193 struct qed_vf_info *p_vf, u16 tx_qid)
194{
195 if (tx_qid >= p_vf->num_txqs)
196 DP_VERBOSE(p_hwfn,
197 QED_MSG_IOV,
198 "VF[0x%02x] - can't touch Tx queue[%04x]; Only 0x%04x are allocated\n",
199 p_vf->abs_vf_id, tx_qid, p_vf->num_txqs);
200 return tx_qid < p_vf->num_txqs;
201}
202
203static bool qed_iov_validate_sb(struct qed_hwfn *p_hwfn,
204 struct qed_vf_info *p_vf, u16 sb_idx)
205{
206 int i;
207
208 for (i = 0; i < p_vf->num_sbs; i++)
209 if (p_vf->igu_sbs[i] == sb_idx)
210 return true;
211
212 DP_VERBOSE(p_hwfn,
213 QED_MSG_IOV,
214 "VF[0%02x] - tried using sb_idx %04x which doesn't exist as one of its 0x%02x SBs\n",
215 p_vf->abs_vf_id, sb_idx, p_vf->num_sbs);
216
217 return false;
218}
219
Baoyou Xieba569472016-09-09 09:21:15 +0800220static int qed_iov_post_vf_bulletin(struct qed_hwfn *p_hwfn,
221 int vfid, struct qed_ptt *p_ptt)
Yuval Mintz36558c32016-05-11 16:36:17 +0300222{
223 struct qed_bulletin_content *p_bulletin;
224 int crc_size = sizeof(p_bulletin->crc);
225 struct qed_dmae_params params;
226 struct qed_vf_info *p_vf;
227
228 p_vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
229 if (!p_vf)
230 return -EINVAL;
231
232 if (!p_vf->vf_bulletin)
233 return -EINVAL;
234
235 p_bulletin = p_vf->bulletin.p_virt;
236
237 /* Increment bulletin board version and compute crc */
238 p_bulletin->version++;
239 p_bulletin->crc = crc32(0, (u8 *)p_bulletin + crc_size,
240 p_vf->bulletin.size - crc_size);
241
242 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
243 "Posting Bulletin 0x%08x to VF[%d] (CRC 0x%08x)\n",
244 p_bulletin->version, p_vf->relative_vf_id, p_bulletin->crc);
245
246 /* propagate bulletin board via dmae to vm memory */
247 memset(&params, 0, sizeof(params));
248 params.flags = QED_DMAE_FLAG_VF_DST;
249 params.dst_vfid = p_vf->abs_vf_id;
250 return qed_dmae_host2host(p_hwfn, p_ptt, p_vf->bulletin.phys,
251 p_vf->vf_bulletin, p_vf->bulletin.size / 4,
252 &params);
253}
254
Yuval Mintz32a47e72016-05-11 16:36:12 +0300255static int qed_iov_pci_cfg_info(struct qed_dev *cdev)
256{
257 struct qed_hw_sriov_info *iov = cdev->p_iov_info;
258 int pos = iov->pos;
259
260 DP_VERBOSE(cdev, QED_MSG_IOV, "sriov ext pos %d\n", pos);
261 pci_read_config_word(cdev->pdev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
262
263 pci_read_config_word(cdev->pdev,
264 pos + PCI_SRIOV_TOTAL_VF, &iov->total_vfs);
265 pci_read_config_word(cdev->pdev,
266 pos + PCI_SRIOV_INITIAL_VF, &iov->initial_vfs);
267
268 pci_read_config_word(cdev->pdev, pos + PCI_SRIOV_NUM_VF, &iov->num_vfs);
269 if (iov->num_vfs) {
270 DP_VERBOSE(cdev,
271 QED_MSG_IOV,
272 "Number of VFs are already set to non-zero value. Ignoring PCI configuration value\n");
273 iov->num_vfs = 0;
274 }
275
276 pci_read_config_word(cdev->pdev,
277 pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
278
279 pci_read_config_word(cdev->pdev,
280 pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
281
282 pci_read_config_word(cdev->pdev,
283 pos + PCI_SRIOV_VF_DID, &iov->vf_device_id);
284
285 pci_read_config_dword(cdev->pdev,
286 pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
287
288 pci_read_config_dword(cdev->pdev, pos + PCI_SRIOV_CAP, &iov->cap);
289
290 pci_read_config_byte(cdev->pdev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
291
292 DP_VERBOSE(cdev,
293 QED_MSG_IOV,
294 "IOV info: nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n",
295 iov->nres,
296 iov->cap,
297 iov->ctrl,
298 iov->total_vfs,
299 iov->initial_vfs,
300 iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz);
301
302 /* Some sanity checks */
303 if (iov->num_vfs > NUM_OF_VFS(cdev) ||
304 iov->total_vfs > NUM_OF_VFS(cdev)) {
305 /* This can happen only due to a bug. In this case we set
306 * num_vfs to zero to avoid memory corruption in the code that
307 * assumes max number of vfs
308 */
309 DP_NOTICE(cdev,
310 "IOV: Unexpected number of vfs set: %d setting num_vf to zero\n",
311 iov->num_vfs);
312
313 iov->num_vfs = 0;
314 iov->total_vfs = 0;
315 }
316
317 return 0;
318}
319
320static void qed_iov_clear_vf_igu_blocks(struct qed_hwfn *p_hwfn,
321 struct qed_ptt *p_ptt)
322{
323 struct qed_igu_block *p_sb;
324 u16 sb_id;
325 u32 val;
326
327 if (!p_hwfn->hw_info.p_igu_info) {
328 DP_ERR(p_hwfn,
329 "qed_iov_clear_vf_igu_blocks IGU Info not initialized\n");
330 return;
331 }
332
333 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
334 sb_id++) {
335 p_sb = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
336 if ((p_sb->status & QED_IGU_STATUS_FREE) &&
337 !(p_sb->status & QED_IGU_STATUS_PF)) {
338 val = qed_rd(p_hwfn, p_ptt,
339 IGU_REG_MAPPING_MEMORY + sb_id * 4);
340 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 0);
341 qed_wr(p_hwfn, p_ptt,
342 IGU_REG_MAPPING_MEMORY + 4 * sb_id, val);
343 }
344 }
345}
346
347static void qed_iov_setup_vfdb(struct qed_hwfn *p_hwfn)
348{
349 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
350 struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
351 struct qed_bulletin_content *p_bulletin_virt;
352 dma_addr_t req_p, rply_p, bulletin_p;
353 union pfvf_tlvs *p_reply_virt_addr;
354 union vfpf_tlvs *p_req_virt_addr;
355 u8 idx = 0;
356
357 memset(p_iov_info->vfs_array, 0, sizeof(p_iov_info->vfs_array));
358
359 p_req_virt_addr = p_iov_info->mbx_msg_virt_addr;
360 req_p = p_iov_info->mbx_msg_phys_addr;
361 p_reply_virt_addr = p_iov_info->mbx_reply_virt_addr;
362 rply_p = p_iov_info->mbx_reply_phys_addr;
363 p_bulletin_virt = p_iov_info->p_bulletins;
364 bulletin_p = p_iov_info->bulletins_phys;
365 if (!p_req_virt_addr || !p_reply_virt_addr || !p_bulletin_virt) {
366 DP_ERR(p_hwfn,
367 "qed_iov_setup_vfdb called without allocating mem first\n");
368 return;
369 }
370
371 for (idx = 0; idx < p_iov->total_vfs; idx++) {
372 struct qed_vf_info *vf = &p_iov_info->vfs_array[idx];
373 u32 concrete;
374
375 vf->vf_mbx.req_virt = p_req_virt_addr + idx;
376 vf->vf_mbx.req_phys = req_p + idx * sizeof(union vfpf_tlvs);
377 vf->vf_mbx.reply_virt = p_reply_virt_addr + idx;
378 vf->vf_mbx.reply_phys = rply_p + idx * sizeof(union pfvf_tlvs);
379
380 vf->state = VF_STOPPED;
381 vf->b_init = false;
382
383 vf->bulletin.phys = idx *
384 sizeof(struct qed_bulletin_content) +
385 bulletin_p;
386 vf->bulletin.p_virt = p_bulletin_virt + idx;
387 vf->bulletin.size = sizeof(struct qed_bulletin_content);
388
389 vf->relative_vf_id = idx;
390 vf->abs_vf_id = idx + p_iov->first_vf_in_pf;
391 concrete = qed_vfid_to_concrete(p_hwfn, vf->abs_vf_id);
392 vf->concrete_fid = concrete;
393 vf->opaque_fid = (p_hwfn->hw_info.opaque_fid & 0xff) |
394 (vf->abs_vf_id << 8);
395 vf->vport_id = idx + 1;
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +0300396
397 vf->num_mac_filters = QED_ETH_VF_NUM_MAC_FILTERS;
398 vf->num_vlan_filters = QED_ETH_VF_NUM_VLAN_FILTERS;
Yuval Mintz32a47e72016-05-11 16:36:12 +0300399 }
400}
401
402static int qed_iov_allocate_vfdb(struct qed_hwfn *p_hwfn)
403{
404 struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
405 void **p_v_addr;
406 u16 num_vfs = 0;
407
408 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
409
410 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
411 "qed_iov_allocate_vfdb for %d VFs\n", num_vfs);
412
413 /* Allocate PF Mailbox buffer (per-VF) */
414 p_iov_info->mbx_msg_size = sizeof(union vfpf_tlvs) * num_vfs;
415 p_v_addr = &p_iov_info->mbx_msg_virt_addr;
416 *p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
417 p_iov_info->mbx_msg_size,
418 &p_iov_info->mbx_msg_phys_addr,
419 GFP_KERNEL);
420 if (!*p_v_addr)
421 return -ENOMEM;
422
423 /* Allocate PF Mailbox Reply buffer (per-VF) */
424 p_iov_info->mbx_reply_size = sizeof(union pfvf_tlvs) * num_vfs;
425 p_v_addr = &p_iov_info->mbx_reply_virt_addr;
426 *p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
427 p_iov_info->mbx_reply_size,
428 &p_iov_info->mbx_reply_phys_addr,
429 GFP_KERNEL);
430 if (!*p_v_addr)
431 return -ENOMEM;
432
433 p_iov_info->bulletins_size = sizeof(struct qed_bulletin_content) *
434 num_vfs;
435 p_v_addr = &p_iov_info->p_bulletins;
436 *p_v_addr = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
437 p_iov_info->bulletins_size,
438 &p_iov_info->bulletins_phys,
439 GFP_KERNEL);
440 if (!*p_v_addr)
441 return -ENOMEM;
442
443 DP_VERBOSE(p_hwfn,
444 QED_MSG_IOV,
445 "PF's Requests mailbox [%p virt 0x%llx phys], Response mailbox [%p virt 0x%llx phys] Bulletins [%p virt 0x%llx phys]\n",
446 p_iov_info->mbx_msg_virt_addr,
447 (u64) p_iov_info->mbx_msg_phys_addr,
448 p_iov_info->mbx_reply_virt_addr,
449 (u64) p_iov_info->mbx_reply_phys_addr,
450 p_iov_info->p_bulletins, (u64) p_iov_info->bulletins_phys);
451
452 return 0;
453}
454
455static void qed_iov_free_vfdb(struct qed_hwfn *p_hwfn)
456{
457 struct qed_pf_iov *p_iov_info = p_hwfn->pf_iov_info;
458
459 if (p_hwfn->pf_iov_info->mbx_msg_virt_addr)
460 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
461 p_iov_info->mbx_msg_size,
462 p_iov_info->mbx_msg_virt_addr,
463 p_iov_info->mbx_msg_phys_addr);
464
465 if (p_hwfn->pf_iov_info->mbx_reply_virt_addr)
466 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
467 p_iov_info->mbx_reply_size,
468 p_iov_info->mbx_reply_virt_addr,
469 p_iov_info->mbx_reply_phys_addr);
470
471 if (p_iov_info->p_bulletins)
472 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
473 p_iov_info->bulletins_size,
474 p_iov_info->p_bulletins,
475 p_iov_info->bulletins_phys);
476}
477
478int qed_iov_alloc(struct qed_hwfn *p_hwfn)
479{
480 struct qed_pf_iov *p_sriov;
481
482 if (!IS_PF_SRIOV(p_hwfn)) {
483 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
484 "No SR-IOV - no need for IOV db\n");
485 return 0;
486 }
487
488 p_sriov = kzalloc(sizeof(*p_sriov), GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700489 if (!p_sriov)
Yuval Mintz32a47e72016-05-11 16:36:12 +0300490 return -ENOMEM;
Yuval Mintz32a47e72016-05-11 16:36:12 +0300491
492 p_hwfn->pf_iov_info = p_sriov;
493
494 return qed_iov_allocate_vfdb(p_hwfn);
495}
496
497void qed_iov_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
498{
499 if (!IS_PF_SRIOV(p_hwfn) || !IS_PF_SRIOV_ALLOC(p_hwfn))
500 return;
501
502 qed_iov_setup_vfdb(p_hwfn);
503 qed_iov_clear_vf_igu_blocks(p_hwfn, p_ptt);
504}
505
506void qed_iov_free(struct qed_hwfn *p_hwfn)
507{
508 if (IS_PF_SRIOV_ALLOC(p_hwfn)) {
509 qed_iov_free_vfdb(p_hwfn);
510 kfree(p_hwfn->pf_iov_info);
511 }
512}
513
514void qed_iov_free_hw_info(struct qed_dev *cdev)
515{
516 kfree(cdev->p_iov_info);
517 cdev->p_iov_info = NULL;
518}
519
520int qed_iov_hw_info(struct qed_hwfn *p_hwfn)
521{
522 struct qed_dev *cdev = p_hwfn->cdev;
523 int pos;
524 int rc;
525
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300526 if (IS_VF(p_hwfn->cdev))
527 return 0;
528
Yuval Mintz32a47e72016-05-11 16:36:12 +0300529 /* Learn the PCI configuration */
530 pos = pci_find_ext_capability(p_hwfn->cdev->pdev,
531 PCI_EXT_CAP_ID_SRIOV);
532 if (!pos) {
533 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "No PCIe IOV support\n");
534 return 0;
535 }
536
537 /* Allocate a new struct for IOV information */
538 cdev->p_iov_info = kzalloc(sizeof(*cdev->p_iov_info), GFP_KERNEL);
Joe Perches2591c282016-09-04 14:24:03 -0700539 if (!cdev->p_iov_info)
Yuval Mintz32a47e72016-05-11 16:36:12 +0300540 return -ENOMEM;
Joe Perches2591c282016-09-04 14:24:03 -0700541
Yuval Mintz32a47e72016-05-11 16:36:12 +0300542 cdev->p_iov_info->pos = pos;
543
544 rc = qed_iov_pci_cfg_info(cdev);
545 if (rc)
546 return rc;
547
548 /* We want PF IOV to be synonemous with the existance of p_iov_info;
549 * In case the capability is published but there are no VFs, simply
550 * de-allocate the struct.
551 */
552 if (!cdev->p_iov_info->total_vfs) {
553 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
554 "IOV capabilities, but no VFs are published\n");
555 kfree(cdev->p_iov_info);
556 cdev->p_iov_info = NULL;
557 return 0;
558 }
559
560 /* Calculate the first VF index - this is a bit tricky; Basically,
561 * VFs start at offset 16 relative to PF0, and 2nd engine VFs begin
562 * after the first engine's VFs.
563 */
564 cdev->p_iov_info->first_vf_in_pf = p_hwfn->cdev->p_iov_info->offset +
565 p_hwfn->abs_pf_id - 16;
566 if (QED_PATH_ID(p_hwfn))
567 cdev->p_iov_info->first_vf_in_pf -= MAX_NUM_VFS_BB;
568
569 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
570 "First VF in hwfn 0x%08x\n",
571 cdev->p_iov_info->first_vf_in_pf);
572
573 return 0;
574}
575
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400576bool _qed_iov_pf_sanity_check(struct qed_hwfn *p_hwfn,
577 int vfid, bool b_fail_malicious)
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300578{
579 /* Check PF supports sriov */
Yuval Mintzb0409fa2016-05-15 14:48:05 +0300580 if (IS_VF(p_hwfn->cdev) || !IS_QED_SRIOV(p_hwfn->cdev) ||
581 !IS_PF_SRIOV_ALLOC(p_hwfn))
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300582 return false;
583
584 /* Check VF validity */
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400585 if (!qed_iov_is_valid_vfid(p_hwfn, vfid, true, b_fail_malicious))
Yuval Mintz37bff2b2016-05-11 16:36:13 +0300586 return false;
587
588 return true;
589}
590
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400591bool qed_iov_pf_sanity_check(struct qed_hwfn *p_hwfn, int vfid)
592{
593 return _qed_iov_pf_sanity_check(p_hwfn, vfid, true);
594}
595
Yuval Mintz0b55e272016-05-11 16:36:15 +0300596static void qed_iov_set_vf_to_disable(struct qed_dev *cdev,
597 u16 rel_vf_id, u8 to_disable)
598{
599 struct qed_vf_info *vf;
600 int i;
601
602 for_each_hwfn(cdev, i) {
603 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
604
605 vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, false);
606 if (!vf)
607 continue;
608
609 vf->to_disable = to_disable;
610 }
611}
612
Baoyou Xieba569472016-09-09 09:21:15 +0800613static void qed_iov_set_vfs_to_disable(struct qed_dev *cdev, u8 to_disable)
Yuval Mintz0b55e272016-05-11 16:36:15 +0300614{
615 u16 i;
616
617 if (!IS_QED_SRIOV(cdev))
618 return;
619
620 for (i = 0; i < cdev->p_iov_info->total_vfs; i++)
621 qed_iov_set_vf_to_disable(cdev, i, to_disable);
622}
623
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300624static void qed_iov_vf_pglue_clear_err(struct qed_hwfn *p_hwfn,
625 struct qed_ptt *p_ptt, u8 abs_vfid)
626{
627 qed_wr(p_hwfn, p_ptt,
628 PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR + (abs_vfid >> 5) * 4,
629 1 << (abs_vfid & 0x1f));
630}
631
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300632static void qed_iov_vf_igu_reset(struct qed_hwfn *p_hwfn,
633 struct qed_ptt *p_ptt, struct qed_vf_info *vf)
634{
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300635 int i;
636
637 /* Set VF masks and configuration - pretend */
638 qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
639
640 qed_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_VF_MSG_SENT, 0);
641
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300642 /* unpretend */
643 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
644
645 /* iterate over all queues, clear sb consumer */
Yuval Mintzb2b897e2016-05-15 14:48:06 +0300646 for (i = 0; i < vf->num_sbs; i++)
647 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
648 vf->igu_sbs[i],
649 vf->opaque_fid, true);
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300650}
651
Yuval Mintz0b55e272016-05-11 16:36:15 +0300652static void qed_iov_vf_igu_set_int(struct qed_hwfn *p_hwfn,
653 struct qed_ptt *p_ptt,
654 struct qed_vf_info *vf, bool enable)
655{
656 u32 igu_vf_conf;
657
658 qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
659
660 igu_vf_conf = qed_rd(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION);
661
662 if (enable)
663 igu_vf_conf |= IGU_VF_CONF_MSI_MSIX_EN;
664 else
665 igu_vf_conf &= ~IGU_VF_CONF_MSI_MSIX_EN;
666
667 qed_wr(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION, igu_vf_conf);
668
669 /* unpretend */
670 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
671}
672
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300673static int qed_iov_enable_vf_access(struct qed_hwfn *p_hwfn,
674 struct qed_ptt *p_ptt,
675 struct qed_vf_info *vf)
676{
677 u32 igu_vf_conf = IGU_VF_CONF_FUNC_EN;
678 int rc;
679
Yuval Mintz0b55e272016-05-11 16:36:15 +0300680 if (vf->to_disable)
681 return 0;
682
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300683 DP_VERBOSE(p_hwfn,
684 QED_MSG_IOV,
685 "Enable internal access for vf %x [abs %x]\n",
686 vf->abs_vf_id, QED_VF_ABS_ID(p_hwfn, vf));
687
688 qed_iov_vf_pglue_clear_err(p_hwfn, p_ptt, QED_VF_ABS_ID(p_hwfn, vf));
689
Yuval Mintzb2b897e2016-05-15 14:48:06 +0300690 qed_iov_vf_igu_reset(p_hwfn, p_ptt, vf);
691
Yuval Mintz7eff82b2016-10-14 05:19:22 -0400692 /* It's possible VF was previously considered malicious */
693 vf->b_malicious = false;
694
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300695 rc = qed_mcp_config_vf_msix(p_hwfn, p_ptt, vf->abs_vf_id, vf->num_sbs);
696 if (rc)
697 return rc;
698
699 qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
700
701 SET_FIELD(igu_vf_conf, IGU_VF_CONF_PARENT, p_hwfn->rel_pf_id);
702 STORE_RT_REG(p_hwfn, IGU_REG_VF_CONFIGURATION_RT_OFFSET, igu_vf_conf);
703
704 qed_init_run(p_hwfn, p_ptt, PHASE_VF, vf->abs_vf_id,
705 p_hwfn->hw_info.hw_mode);
706
707 /* unpretend */
708 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
709
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300710 vf->state = VF_FREE;
711
712 return rc;
713}
714
Yuval Mintz0b55e272016-05-11 16:36:15 +0300715/**
716 * @brief qed_iov_config_perm_table - configure the permission
717 * zone table.
718 * In E4, queue zone permission table size is 320x9. There
719 * are 320 VF queues for single engine device (256 for dual
720 * engine device), and each entry has the following format:
721 * {Valid, VF[7:0]}
722 * @param p_hwfn
723 * @param p_ptt
724 * @param vf
725 * @param enable
726 */
727static void qed_iov_config_perm_table(struct qed_hwfn *p_hwfn,
728 struct qed_ptt *p_ptt,
729 struct qed_vf_info *vf, u8 enable)
730{
731 u32 reg_addr, val;
732 u16 qzone_id = 0;
733 int qid;
734
735 for (qid = 0; qid < vf->num_rxqs; qid++) {
736 qed_fw_l2_queue(p_hwfn, vf->vf_queues[qid].fw_rx_qid,
737 &qzone_id);
738
739 reg_addr = PSWHST_REG_ZONE_PERMISSION_TABLE + qzone_id * 4;
Yuval Mintz1a635e42016-08-15 10:42:43 +0300740 val = enable ? (vf->abs_vf_id | BIT(8)) : 0;
Yuval Mintz0b55e272016-05-11 16:36:15 +0300741 qed_wr(p_hwfn, p_ptt, reg_addr, val);
742 }
743}
744
Yuval Mintzdacd88d2016-05-11 16:36:16 +0300745static void qed_iov_enable_vf_traffic(struct qed_hwfn *p_hwfn,
746 struct qed_ptt *p_ptt,
747 struct qed_vf_info *vf)
748{
749 /* Reset vf in IGU - interrupts are still disabled */
750 qed_iov_vf_igu_reset(p_hwfn, p_ptt, vf);
751
752 qed_iov_vf_igu_set_int(p_hwfn, p_ptt, vf, 1);
753
754 /* Permission Table */
755 qed_iov_config_perm_table(p_hwfn, p_ptt, vf, true);
756}
757
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300758static u8 qed_iov_alloc_vf_igu_sbs(struct qed_hwfn *p_hwfn,
759 struct qed_ptt *p_ptt,
760 struct qed_vf_info *vf, u16 num_rx_queues)
761{
762 struct qed_igu_block *igu_blocks;
763 int qid = 0, igu_id = 0;
764 u32 val = 0;
765
766 igu_blocks = p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks;
767
768 if (num_rx_queues > p_hwfn->hw_info.p_igu_info->free_blks)
769 num_rx_queues = p_hwfn->hw_info.p_igu_info->free_blks;
770 p_hwfn->hw_info.p_igu_info->free_blks -= num_rx_queues;
771
772 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, vf->abs_vf_id);
773 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 1);
774 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, 0);
775
776 while ((qid < num_rx_queues) &&
777 (igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev))) {
778 if (igu_blocks[igu_id].status & QED_IGU_STATUS_FREE) {
779 struct cau_sb_entry sb_entry;
780
781 vf->igu_sbs[qid] = (u16)igu_id;
782 igu_blocks[igu_id].status &= ~QED_IGU_STATUS_FREE;
783
784 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, qid);
785
786 qed_wr(p_hwfn, p_ptt,
787 IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_id,
788 val);
789
790 /* Configure igu sb in CAU which were marked valid */
791 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
792 p_hwfn->rel_pf_id,
793 vf->abs_vf_id, 1);
794 qed_dmae_host2grc(p_hwfn, p_ptt,
795 (u64)(uintptr_t)&sb_entry,
796 CAU_REG_SB_VAR_MEMORY +
797 igu_id * sizeof(u64), 2, 0);
798 qid++;
799 }
800 igu_id++;
801 }
802
803 vf->num_sbs = (u8) num_rx_queues;
804
805 return vf->num_sbs;
806}
807
Yuval Mintz0b55e272016-05-11 16:36:15 +0300808static void qed_iov_free_vf_igu_sbs(struct qed_hwfn *p_hwfn,
809 struct qed_ptt *p_ptt,
810 struct qed_vf_info *vf)
811{
812 struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
813 int idx, igu_id;
814 u32 addr, val;
815
816 /* Invalidate igu CAM lines and mark them as free */
817 for (idx = 0; idx < vf->num_sbs; idx++) {
818 igu_id = vf->igu_sbs[idx];
819 addr = IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_id;
820
821 val = qed_rd(p_hwfn, p_ptt, addr);
822 SET_FIELD(val, IGU_MAPPING_LINE_VALID, 0);
823 qed_wr(p_hwfn, p_ptt, addr, val);
824
825 p_info->igu_map.igu_blocks[igu_id].status |=
826 QED_IGU_STATUS_FREE;
827
828 p_hwfn->hw_info.p_igu_info->free_blks++;
829 }
830
831 vf->num_sbs = 0;
832}
833
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300834static int qed_iov_init_hw_for_vf(struct qed_hwfn *p_hwfn,
835 struct qed_ptt *p_ptt,
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200836 struct qed_iov_vf_init_params *p_params)
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300837{
838 u8 num_of_vf_avaiable_chains = 0;
839 struct qed_vf_info *vf = NULL;
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200840 u16 qid, num_irqs;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300841 int rc = 0;
842 u32 cids;
843 u8 i;
844
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200845 vf = qed_iov_get_vf_info(p_hwfn, p_params->rel_vf_id, false);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300846 if (!vf) {
847 DP_ERR(p_hwfn, "qed_iov_init_hw_for_vf : vf is NULL\n");
848 return -EINVAL;
849 }
850
851 if (vf->b_init) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200852 DP_NOTICE(p_hwfn, "VF[%d] is already active.\n",
853 p_params->rel_vf_id);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300854 return -EINVAL;
855 }
856
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200857 /* Perform sanity checking on the requested queue_id */
858 for (i = 0; i < p_params->num_queues; i++) {
859 u16 min_vf_qzone = FEAT_NUM(p_hwfn, QED_PF_L2_QUE);
860 u16 max_vf_qzone = min_vf_qzone +
861 FEAT_NUM(p_hwfn, QED_VF_L2_QUE) - 1;
862
863 qid = p_params->req_rx_queue[i];
864 if (qid < min_vf_qzone || qid > max_vf_qzone) {
865 DP_NOTICE(p_hwfn,
866 "Can't enable Rx qid [%04x] for VF[%d]: qids [0x%04x,...,0x%04x] available\n",
867 qid,
868 p_params->rel_vf_id,
869 min_vf_qzone, max_vf_qzone);
870 return -EINVAL;
871 }
872
873 qid = p_params->req_tx_queue[i];
874 if (qid > max_vf_qzone) {
875 DP_NOTICE(p_hwfn,
876 "Can't enable Tx qid [%04x] for VF[%d]: max qid 0x%04x\n",
877 qid, p_params->rel_vf_id, max_vf_qzone);
878 return -EINVAL;
879 }
880
881 /* If client *really* wants, Tx qid can be shared with PF */
882 if (qid < min_vf_qzone)
883 DP_VERBOSE(p_hwfn,
884 QED_MSG_IOV,
885 "VF[%d] is using PF qid [0x%04x] for Txq[0x%02x]\n",
886 p_params->rel_vf_id, qid, i);
887 }
888
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300889 /* Limit number of queues according to number of CIDs */
890 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, &cids);
891 DP_VERBOSE(p_hwfn,
892 QED_MSG_IOV,
893 "VF[%d] - requesting to initialize for 0x%04x queues [0x%04x CIDs available]\n",
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200894 vf->relative_vf_id, p_params->num_queues, (u16)cids);
895 num_irqs = min_t(u16, p_params->num_queues, ((u16)cids));
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300896
897 num_of_vf_avaiable_chains = qed_iov_alloc_vf_igu_sbs(p_hwfn,
898 p_ptt,
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200899 vf, num_irqs);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300900 if (!num_of_vf_avaiable_chains) {
901 DP_ERR(p_hwfn, "no available igu sbs\n");
902 return -ENOMEM;
903 }
904
905 /* Choose queue number and index ranges */
906 vf->num_rxqs = num_of_vf_avaiable_chains;
907 vf->num_txqs = num_of_vf_avaiable_chains;
908
909 for (i = 0; i < vf->num_rxqs; i++) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200910 struct qed_vf_q_info *p_queue = &vf->vf_queues[i];
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300911
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200912 p_queue->fw_rx_qid = p_params->req_rx_queue[i];
913 p_queue->fw_tx_qid = p_params->req_tx_queue[i];
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300914
915 /* CIDs are per-VF, so no problem having them 0-based. */
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200916 p_queue->fw_cid = i;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300917
918 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200919 "VF[%d] - Q[%d] SB %04x, qid [Rx %04x Tx %04x] CID %04x\n",
920 vf->relative_vf_id,
921 i, vf->igu_sbs[i],
922 p_queue->fw_rx_qid,
923 p_queue->fw_tx_qid, p_queue->fw_cid);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300924 }
Mintz, Yuval3da7a372016-11-29 16:47:06 +0200925
Yuval Mintz1408cc1f2016-05-11 16:36:14 +0300926 rc = qed_iov_enable_vf_access(p_hwfn, p_ptt, vf);
927 if (!rc) {
928 vf->b_init = true;
929
930 if (IS_LEAD_HWFN(p_hwfn))
931 p_hwfn->cdev->p_iov_info->num_vfs++;
932 }
933
934 return rc;
935}
936
Manish Chopra079d20a2016-05-15 14:48:07 +0300937static void qed_iov_set_link(struct qed_hwfn *p_hwfn,
938 u16 vfid,
939 struct qed_mcp_link_params *params,
940 struct qed_mcp_link_state *link,
941 struct qed_mcp_link_capabilities *p_caps)
942{
943 struct qed_vf_info *p_vf = qed_iov_get_vf_info(p_hwfn,
944 vfid,
945 false);
946 struct qed_bulletin_content *p_bulletin;
947
948 if (!p_vf)
949 return;
950
951 p_bulletin = p_vf->bulletin.p_virt;
952 p_bulletin->req_autoneg = params->speed.autoneg;
953 p_bulletin->req_adv_speed = params->speed.advertised_speeds;
954 p_bulletin->req_forced_speed = params->speed.forced_speed;
955 p_bulletin->req_autoneg_pause = params->pause.autoneg;
956 p_bulletin->req_forced_rx = params->pause.forced_rx;
957 p_bulletin->req_forced_tx = params->pause.forced_tx;
958 p_bulletin->req_loopback = params->loopback_mode;
959
960 p_bulletin->link_up = link->link_up;
961 p_bulletin->speed = link->speed;
962 p_bulletin->full_duplex = link->full_duplex;
963 p_bulletin->autoneg = link->an;
964 p_bulletin->autoneg_complete = link->an_complete;
965 p_bulletin->parallel_detection = link->parallel_detection;
966 p_bulletin->pfc_enabled = link->pfc_enabled;
967 p_bulletin->partner_adv_speed = link->partner_adv_speed;
968 p_bulletin->partner_tx_flow_ctrl_en = link->partner_tx_flow_ctrl_en;
969 p_bulletin->partner_rx_flow_ctrl_en = link->partner_rx_flow_ctrl_en;
970 p_bulletin->partner_adv_pause = link->partner_adv_pause;
971 p_bulletin->sfp_tx_fault = link->sfp_tx_fault;
972
973 p_bulletin->capability_speed = p_caps->speed_capabilities;
974}
975
Yuval Mintz0b55e272016-05-11 16:36:15 +0300976static int qed_iov_release_hw_for_vf(struct qed_hwfn *p_hwfn,
977 struct qed_ptt *p_ptt, u16 rel_vf_id)
978{
Manish Chopra079d20a2016-05-15 14:48:07 +0300979 struct qed_mcp_link_capabilities caps;
980 struct qed_mcp_link_params params;
981 struct qed_mcp_link_state link;
Yuval Mintz0b55e272016-05-11 16:36:15 +0300982 struct qed_vf_info *vf = NULL;
Yuval Mintz0b55e272016-05-11 16:36:15 +0300983
984 vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
985 if (!vf) {
986 DP_ERR(p_hwfn, "qed_iov_release_hw_for_vf : vf is NULL\n");
987 return -EINVAL;
988 }
989
Yuval Mintz36558c32016-05-11 16:36:17 +0300990 if (vf->bulletin.p_virt)
991 memset(vf->bulletin.p_virt, 0, sizeof(*vf->bulletin.p_virt));
992
993 memset(&vf->p_vf_info, 0, sizeof(vf->p_vf_info));
994
Manish Chopra079d20a2016-05-15 14:48:07 +0300995 /* Get the link configuration back in bulletin so
996 * that when VFs are re-enabled they get the actual
997 * link configuration.
998 */
999 memcpy(&params, qed_mcp_get_link_params(p_hwfn), sizeof(params));
1000 memcpy(&link, qed_mcp_get_link_state(p_hwfn), sizeof(link));
1001 memcpy(&caps, qed_mcp_get_link_capabilities(p_hwfn), sizeof(caps));
1002 qed_iov_set_link(p_hwfn, rel_vf_id, &params, &link, &caps);
1003
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001004 /* Forget the VF's acquisition message */
1005 memset(&vf->acquire, 0, sizeof(vf->acquire));
Yuval Mintz0b55e272016-05-11 16:36:15 +03001006
1007 /* disablng interrupts and resetting permission table was done during
1008 * vf-close, however, we could get here without going through vf_close
1009 */
1010 /* Disable Interrupts for VF */
1011 qed_iov_vf_igu_set_int(p_hwfn, p_ptt, vf, 0);
1012
1013 /* Reset Permission table */
1014 qed_iov_config_perm_table(p_hwfn, p_ptt, vf, 0);
1015
1016 vf->num_rxqs = 0;
1017 vf->num_txqs = 0;
1018 qed_iov_free_vf_igu_sbs(p_hwfn, p_ptt, vf);
1019
1020 if (vf->b_init) {
1021 vf->b_init = false;
1022
1023 if (IS_LEAD_HWFN(p_hwfn))
1024 p_hwfn->cdev->p_iov_info->num_vfs--;
1025 }
1026
1027 return 0;
1028}
1029
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001030static bool qed_iov_tlv_supported(u16 tlvtype)
1031{
1032 return CHANNEL_TLV_NONE < tlvtype && tlvtype < CHANNEL_TLV_MAX;
1033}
1034
1035/* place a given tlv on the tlv buffer, continuing current tlv list */
1036void *qed_add_tlv(struct qed_hwfn *p_hwfn, u8 **offset, u16 type, u16 length)
1037{
1038 struct channel_tlv *tl = (struct channel_tlv *)*offset;
1039
1040 tl->type = type;
1041 tl->length = length;
1042
1043 /* Offset should keep pointing to next TLV (the end of the last) */
1044 *offset += length;
1045
1046 /* Return a pointer to the start of the added tlv */
1047 return *offset - length;
1048}
1049
1050/* list the types and lengths of the tlvs on the buffer */
1051void qed_dp_tlv_list(struct qed_hwfn *p_hwfn, void *tlvs_list)
1052{
1053 u16 i = 1, total_length = 0;
1054 struct channel_tlv *tlv;
1055
1056 do {
1057 tlv = (struct channel_tlv *)((u8 *)tlvs_list + total_length);
1058
1059 /* output tlv */
1060 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1061 "TLV number %d: type %d, length %d\n",
1062 i, tlv->type, tlv->length);
1063
1064 if (tlv->type == CHANNEL_TLV_LIST_END)
1065 return;
1066
1067 /* Validate entry - protect against malicious VFs */
1068 if (!tlv->length) {
1069 DP_NOTICE(p_hwfn, "TLV of length 0 found\n");
1070 return;
1071 }
1072
1073 total_length += tlv->length;
1074
1075 if (total_length >= sizeof(struct tlv_buffer_size)) {
1076 DP_NOTICE(p_hwfn, "TLV ==> Buffer overflow\n");
1077 return;
1078 }
1079
1080 i++;
1081 } while (1);
1082}
1083
1084static void qed_iov_send_response(struct qed_hwfn *p_hwfn,
1085 struct qed_ptt *p_ptt,
1086 struct qed_vf_info *p_vf,
1087 u16 length, u8 status)
1088{
1089 struct qed_iov_vf_mbx *mbx = &p_vf->vf_mbx;
1090 struct qed_dmae_params params;
1091 u8 eng_vf_id;
1092
1093 mbx->reply_virt->default_resp.hdr.status = status;
1094
1095 qed_dp_tlv_list(p_hwfn, mbx->reply_virt);
1096
1097 eng_vf_id = p_vf->abs_vf_id;
1098
1099 memset(&params, 0, sizeof(struct qed_dmae_params));
1100 params.flags = QED_DMAE_FLAG_VF_DST;
1101 params.dst_vfid = eng_vf_id;
1102
1103 qed_dmae_host2host(p_hwfn, p_ptt, mbx->reply_phys + sizeof(u64),
1104 mbx->req_virt->first_tlv.reply_address +
1105 sizeof(u64),
1106 (sizeof(union pfvf_tlvs) - sizeof(u64)) / 4,
1107 &params);
1108
1109 qed_dmae_host2host(p_hwfn, p_ptt, mbx->reply_phys,
1110 mbx->req_virt->first_tlv.reply_address,
1111 sizeof(u64) / 4, &params);
1112
1113 REG_WR(p_hwfn,
1114 GTT_BAR0_MAP_REG_USDM_RAM +
1115 USTORM_VF_PF_CHANNEL_READY_OFFSET(eng_vf_id), 1);
1116}
1117
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001118static u16 qed_iov_vport_to_tlv(struct qed_hwfn *p_hwfn,
1119 enum qed_iov_vport_update_flag flag)
1120{
1121 switch (flag) {
1122 case QED_IOV_VP_UPDATE_ACTIVATE:
1123 return CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
Yuval Mintz17b235c2016-05-11 16:36:18 +03001124 case QED_IOV_VP_UPDATE_VLAN_STRIP:
1125 return CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP;
1126 case QED_IOV_VP_UPDATE_TX_SWITCH:
1127 return CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001128 case QED_IOV_VP_UPDATE_MCAST:
1129 return CHANNEL_TLV_VPORT_UPDATE_MCAST;
1130 case QED_IOV_VP_UPDATE_ACCEPT_PARAM:
1131 return CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
1132 case QED_IOV_VP_UPDATE_RSS:
1133 return CHANNEL_TLV_VPORT_UPDATE_RSS;
Yuval Mintz17b235c2016-05-11 16:36:18 +03001134 case QED_IOV_VP_UPDATE_ACCEPT_ANY_VLAN:
1135 return CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
1136 case QED_IOV_VP_UPDATE_SGE_TPA:
1137 return CHANNEL_TLV_VPORT_UPDATE_SGE_TPA;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001138 default:
1139 return 0;
1140 }
1141}
1142
1143static u16 qed_iov_prep_vp_update_resp_tlvs(struct qed_hwfn *p_hwfn,
1144 struct qed_vf_info *p_vf,
1145 struct qed_iov_vf_mbx *p_mbx,
1146 u8 status,
1147 u16 tlvs_mask, u16 tlvs_accepted)
1148{
1149 struct pfvf_def_resp_tlv *resp;
1150 u16 size, total_len, i;
1151
1152 memset(p_mbx->reply_virt, 0, sizeof(union pfvf_tlvs));
1153 p_mbx->offset = (u8 *)p_mbx->reply_virt;
1154 size = sizeof(struct pfvf_def_resp_tlv);
1155 total_len = size;
1156
1157 qed_add_tlv(p_hwfn, &p_mbx->offset, CHANNEL_TLV_VPORT_UPDATE, size);
1158
1159 /* Prepare response for all extended tlvs if they are found by PF */
1160 for (i = 0; i < QED_IOV_VP_UPDATE_MAX; i++) {
Yuval Mintz1a635e42016-08-15 10:42:43 +03001161 if (!(tlvs_mask & BIT(i)))
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001162 continue;
1163
1164 resp = qed_add_tlv(p_hwfn, &p_mbx->offset,
1165 qed_iov_vport_to_tlv(p_hwfn, i), size);
1166
Yuval Mintz1a635e42016-08-15 10:42:43 +03001167 if (tlvs_accepted & BIT(i))
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001168 resp->hdr.status = status;
1169 else
1170 resp->hdr.status = PFVF_STATUS_NOT_SUPPORTED;
1171
1172 DP_VERBOSE(p_hwfn,
1173 QED_MSG_IOV,
1174 "VF[%d] - vport_update response: TLV %d, status %02x\n",
1175 p_vf->relative_vf_id,
1176 qed_iov_vport_to_tlv(p_hwfn, i), resp->hdr.status);
1177
1178 total_len += size;
1179 }
1180
1181 qed_add_tlv(p_hwfn, &p_mbx->offset, CHANNEL_TLV_LIST_END,
1182 sizeof(struct channel_list_end_tlv));
1183
1184 return total_len;
1185}
1186
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001187static void qed_iov_prepare_resp(struct qed_hwfn *p_hwfn,
1188 struct qed_ptt *p_ptt,
1189 struct qed_vf_info *vf_info,
1190 u16 type, u16 length, u8 status)
1191{
1192 struct qed_iov_vf_mbx *mbx = &vf_info->vf_mbx;
1193
1194 mbx->offset = (u8 *)mbx->reply_virt;
1195
1196 qed_add_tlv(p_hwfn, &mbx->offset, type, length);
1197 qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_LIST_END,
1198 sizeof(struct channel_list_end_tlv));
1199
1200 qed_iov_send_response(p_hwfn, p_ptt, vf_info, length, status);
1201}
1202
Baoyou Xieba569472016-09-09 09:21:15 +08001203static struct
1204qed_public_vf_info *qed_iov_get_public_vf_info(struct qed_hwfn *p_hwfn,
1205 u16 relative_vf_id,
1206 bool b_enabled_only)
Yuval Mintz0b55e272016-05-11 16:36:15 +03001207{
1208 struct qed_vf_info *vf = NULL;
1209
1210 vf = qed_iov_get_vf_info(p_hwfn, relative_vf_id, b_enabled_only);
1211 if (!vf)
1212 return NULL;
1213
1214 return &vf->p_vf_info;
1215}
1216
Baoyou Xieba569472016-09-09 09:21:15 +08001217static void qed_iov_clean_vf(struct qed_hwfn *p_hwfn, u8 vfid)
Yuval Mintz0b55e272016-05-11 16:36:15 +03001218{
1219 struct qed_public_vf_info *vf_info;
1220
1221 vf_info = qed_iov_get_public_vf_info(p_hwfn, vfid, false);
1222
1223 if (!vf_info)
1224 return;
1225
1226 /* Clear the VF mac */
1227 memset(vf_info->mac, 0, ETH_ALEN);
1228}
1229
1230static void qed_iov_vf_cleanup(struct qed_hwfn *p_hwfn,
1231 struct qed_vf_info *p_vf)
1232{
1233 u32 i;
1234
1235 p_vf->vf_bulletin = 0;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001236 p_vf->vport_instance = 0;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001237 p_vf->configured_features = 0;
Yuval Mintz0b55e272016-05-11 16:36:15 +03001238
1239 /* If VF previously requested less resources, go back to default */
1240 p_vf->num_rxqs = p_vf->num_sbs;
1241 p_vf->num_txqs = p_vf->num_sbs;
1242
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001243 p_vf->num_active_rxqs = 0;
1244
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001245 for (i = 0; i < QED_MAX_VF_CHAINS_PER_PF; i++) {
1246 struct qed_vf_q_info *p_queue = &p_vf->vf_queues[i];
1247
1248 if (p_queue->p_rx_cid) {
1249 qed_eth_queue_cid_release(p_hwfn, p_queue->p_rx_cid);
1250 p_queue->p_rx_cid = NULL;
1251 }
1252
1253 if (p_queue->p_tx_cid) {
1254 qed_eth_queue_cid_release(p_hwfn, p_queue->p_tx_cid);
1255 p_queue->p_tx_cid = NULL;
1256 }
1257 }
Yuval Mintz0b55e272016-05-11 16:36:15 +03001258
Yuval Mintz08feecd2016-05-11 16:36:20 +03001259 memset(&p_vf->shadow_config, 0, sizeof(p_vf->shadow_config));
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001260 memset(&p_vf->acquire, 0, sizeof(p_vf->acquire));
Yuval Mintz0b55e272016-05-11 16:36:15 +03001261 qed_iov_clean_vf(p_hwfn, p_vf->relative_vf_id);
1262}
1263
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001264static u8 qed_iov_vf_mbx_acquire_resc(struct qed_hwfn *p_hwfn,
1265 struct qed_ptt *p_ptt,
1266 struct qed_vf_info *p_vf,
1267 struct vf_pf_resc_request *p_req,
1268 struct pf_vf_resc *p_resp)
1269{
1270 int i;
1271
1272 /* Queue related information */
1273 p_resp->num_rxqs = p_vf->num_rxqs;
1274 p_resp->num_txqs = p_vf->num_txqs;
1275 p_resp->num_sbs = p_vf->num_sbs;
1276
1277 for (i = 0; i < p_resp->num_sbs; i++) {
1278 p_resp->hw_sbs[i].hw_sb_id = p_vf->igu_sbs[i];
1279 p_resp->hw_sbs[i].sb_qid = 0;
1280 }
1281
1282 /* These fields are filled for backward compatibility.
1283 * Unused by modern vfs.
1284 */
1285 for (i = 0; i < p_resp->num_rxqs; i++) {
1286 qed_fw_l2_queue(p_hwfn, p_vf->vf_queues[i].fw_rx_qid,
1287 (u16 *)&p_resp->hw_qid[i]);
1288 p_resp->cid[i] = p_vf->vf_queues[i].fw_cid;
1289 }
1290
1291 /* Filter related information */
1292 p_resp->num_mac_filters = min_t(u8, p_vf->num_mac_filters,
1293 p_req->num_mac_filters);
1294 p_resp->num_vlan_filters = min_t(u8, p_vf->num_vlan_filters,
1295 p_req->num_vlan_filters);
1296
1297 /* This isn't really needed/enforced, but some legacy VFs might depend
1298 * on the correct filling of this field.
1299 */
1300 p_resp->num_mc_filters = QED_MAX_MC_ADDRS;
1301
1302 /* Validate sufficient resources for VF */
1303 if (p_resp->num_rxqs < p_req->num_rxqs ||
1304 p_resp->num_txqs < p_req->num_txqs ||
1305 p_resp->num_sbs < p_req->num_sbs ||
1306 p_resp->num_mac_filters < p_req->num_mac_filters ||
1307 p_resp->num_vlan_filters < p_req->num_vlan_filters ||
1308 p_resp->num_mc_filters < p_req->num_mc_filters) {
1309 DP_VERBOSE(p_hwfn,
1310 QED_MSG_IOV,
1311 "VF[%d] - Insufficient resources: rxq [%02x/%02x] txq [%02x/%02x] sbs [%02x/%02x] mac [%02x/%02x] vlan [%02x/%02x] mc [%02x/%02x]\n",
1312 p_vf->abs_vf_id,
1313 p_req->num_rxqs,
1314 p_resp->num_rxqs,
1315 p_req->num_rxqs,
1316 p_resp->num_txqs,
1317 p_req->num_sbs,
1318 p_resp->num_sbs,
1319 p_req->num_mac_filters,
1320 p_resp->num_mac_filters,
1321 p_req->num_vlan_filters,
1322 p_resp->num_vlan_filters,
1323 p_req->num_mc_filters, p_resp->num_mc_filters);
Yuval Mintza044df82016-08-22 13:25:09 +03001324
1325 /* Some legacy OSes are incapable of correctly handling this
1326 * failure.
1327 */
1328 if ((p_vf->acquire.vfdev_info.eth_fp_hsi_minor ==
1329 ETH_HSI_VER_NO_PKT_LEN_TUNN) &&
1330 (p_vf->acquire.vfdev_info.os_type ==
1331 VFPF_ACQUIRE_OS_WINDOWS))
1332 return PFVF_STATUS_SUCCESS;
1333
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001334 return PFVF_STATUS_NO_RESOURCE;
1335 }
1336
1337 return PFVF_STATUS_SUCCESS;
1338}
1339
1340static void qed_iov_vf_mbx_acquire_stats(struct qed_hwfn *p_hwfn,
1341 struct pfvf_stats_info *p_stats)
1342{
1343 p_stats->mstats.address = PXP_VF_BAR0_START_MSDM_ZONE_B +
1344 offsetof(struct mstorm_vf_zone,
1345 non_trigger.eth_queue_stat);
1346 p_stats->mstats.len = sizeof(struct eth_mstorm_per_queue_stat);
1347 p_stats->ustats.address = PXP_VF_BAR0_START_USDM_ZONE_B +
1348 offsetof(struct ustorm_vf_zone,
1349 non_trigger.eth_queue_stat);
1350 p_stats->ustats.len = sizeof(struct eth_ustorm_per_queue_stat);
1351 p_stats->pstats.address = PXP_VF_BAR0_START_PSDM_ZONE_B +
1352 offsetof(struct pstorm_vf_zone,
1353 non_trigger.eth_queue_stat);
1354 p_stats->pstats.len = sizeof(struct eth_pstorm_per_queue_stat);
1355 p_stats->tstats.address = 0;
1356 p_stats->tstats.len = 0;
1357}
1358
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001359static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
1360 struct qed_ptt *p_ptt,
1361 struct qed_vf_info *vf)
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001362{
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001363 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1364 struct pfvf_acquire_resp_tlv *resp = &mbx->reply_virt->acquire_resp;
1365 struct pf_vf_pfdev_info *pfdev_info = &resp->pfdev_info;
1366 struct vfpf_acquire_tlv *req = &mbx->req_virt->acquire;
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001367 u8 vfpf_status = PFVF_STATUS_NOT_SUPPORTED;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001368 struct pf_vf_resc *resc = &resp->resc;
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001369 int rc;
1370
1371 memset(resp, 0, sizeof(*resp));
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001372
Yuval Mintz05fafbf2016-08-19 09:33:31 +03001373 /* Write the PF version so that VF would know which version
1374 * is supported - might be later overriden. This guarantees that
1375 * VF could recognize legacy PF based on lack of versions in reply.
1376 */
1377 pfdev_info->major_fp_hsi = ETH_HSI_VER_MAJOR;
1378 pfdev_info->minor_fp_hsi = ETH_HSI_VER_MINOR;
1379
Yuval Mintza044df82016-08-22 13:25:09 +03001380 if (vf->state != VF_FREE && vf->state != VF_STOPPED) {
1381 DP_VERBOSE(p_hwfn,
1382 QED_MSG_IOV,
1383 "VF[%d] sent ACQUIRE but is already in state %d - fail request\n",
1384 vf->abs_vf_id, vf->state);
1385 goto out;
1386 }
1387
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001388 /* Validate FW compatibility */
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001389 if (req->vfdev_info.eth_fp_hsi_major != ETH_HSI_VER_MAJOR) {
Yuval Mintza044df82016-08-22 13:25:09 +03001390 if (req->vfdev_info.capabilities &
1391 VFPF_ACQUIRE_CAP_PRE_FP_HSI) {
1392 struct vf_pf_vfdev_info *p_vfdev = &req->vfdev_info;
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001393
Yuval Mintza044df82016-08-22 13:25:09 +03001394 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1395 "VF[%d] is pre-fastpath HSI\n",
1396 vf->abs_vf_id);
1397 p_vfdev->eth_fp_hsi_major = ETH_HSI_VER_MAJOR;
1398 p_vfdev->eth_fp_hsi_minor = ETH_HSI_VER_NO_PKT_LEN_TUNN;
1399 } else {
1400 DP_INFO(p_hwfn,
1401 "VF[%d] needs fastpath HSI %02x.%02x, which is incompatible with loaded FW's faspath HSI %02x.%02x\n",
1402 vf->abs_vf_id,
1403 req->vfdev_info.eth_fp_hsi_major,
1404 req->vfdev_info.eth_fp_hsi_minor,
1405 ETH_HSI_VER_MAJOR, ETH_HSI_VER_MINOR);
1406
1407 goto out;
1408 }
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001409 }
1410
1411 /* On 100g PFs, prevent old VFs from loading */
1412 if ((p_hwfn->cdev->num_hwfns > 1) &&
1413 !(req->vfdev_info.capabilities & VFPF_ACQUIRE_CAP_100G)) {
1414 DP_INFO(p_hwfn,
1415 "VF[%d] is running an old driver that doesn't support 100g\n",
1416 vf->abs_vf_id);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001417 goto out;
1418 }
1419
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001420 /* Store the acquire message */
1421 memcpy(&vf->acquire, req, sizeof(vf->acquire));
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001422
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001423 vf->opaque_fid = req->vfdev_info.opaque_fid;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001424
1425 vf->vf_bulletin = req->bulletin_addr;
1426 vf->bulletin.size = (vf->bulletin.size < req->bulletin_size) ?
1427 vf->bulletin.size : req->bulletin_size;
1428
1429 /* fill in pfdev info */
1430 pfdev_info->chip_num = p_hwfn->cdev->chip_num;
1431 pfdev_info->db_size = 0;
1432 pfdev_info->indices_per_sb = PIS_PER_SB;
1433
1434 pfdev_info->capabilities = PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED |
1435 PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE;
1436 if (p_hwfn->cdev->num_hwfns > 1)
1437 pfdev_info->capabilities |= PFVF_ACQUIRE_CAP_100G;
1438
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001439 qed_iov_vf_mbx_acquire_stats(p_hwfn, &pfdev_info->stats_info);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001440
1441 memcpy(pfdev_info->port_mac, p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
1442
1443 pfdev_info->fw_major = FW_MAJOR_VERSION;
1444 pfdev_info->fw_minor = FW_MINOR_VERSION;
1445 pfdev_info->fw_rev = FW_REVISION_VERSION;
1446 pfdev_info->fw_eng = FW_ENGINEERING_VERSION;
Yuval Mintza044df82016-08-22 13:25:09 +03001447
1448 /* Incorrect when legacy, but doesn't matter as legacy isn't reading
1449 * this field.
1450 */
Yuval Mintz1a635e42016-08-15 10:42:43 +03001451 pfdev_info->minor_fp_hsi = min_t(u8, ETH_HSI_VER_MINOR,
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001452 req->vfdev_info.eth_fp_hsi_minor);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001453 pfdev_info->os_type = VFPF_ACQUIRE_OS_LINUX;
1454 qed_mcp_get_mfw_ver(p_hwfn, p_ptt, &pfdev_info->mfw_ver, NULL);
1455
1456 pfdev_info->dev_type = p_hwfn->cdev->type;
1457 pfdev_info->chip_rev = p_hwfn->cdev->chip_rev;
1458
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001459 /* Fill resources available to VF; Make sure there are enough to
1460 * satisfy the VF's request.
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001461 */
Yuval Mintz1cf2b1a2016-06-05 13:11:12 +03001462 vfpf_status = qed_iov_vf_mbx_acquire_resc(p_hwfn, p_ptt, vf,
1463 &req->resc_request, resc);
1464 if (vfpf_status != PFVF_STATUS_SUCCESS)
1465 goto out;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001466
Yuval Mintz1fe614d2016-06-05 13:11:11 +03001467 /* Start the VF in FW */
1468 rc = qed_sp_vf_start(p_hwfn, vf);
1469 if (rc) {
1470 DP_NOTICE(p_hwfn, "Failed to start VF[%02x]\n", vf->abs_vf_id);
1471 vfpf_status = PFVF_STATUS_FAILURE;
1472 goto out;
1473 }
1474
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001475 /* Fill agreed size of bulletin board in response */
1476 resp->bulletin_size = vf->bulletin.size;
Yuval Mintz36558c32016-05-11 16:36:17 +03001477 qed_iov_post_vf_bulletin(p_hwfn, vf->relative_vf_id, p_ptt);
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03001478
1479 DP_VERBOSE(p_hwfn,
1480 QED_MSG_IOV,
1481 "VF[%d] ACQUIRE_RESPONSE: pfdev_info- chip_num=0x%x, db_size=%d, idx_per_sb=%d, pf_cap=0x%llx\n"
1482 "resources- n_rxq-%d, n_txq-%d, n_sbs-%d, n_macs-%d, n_vlans-%d\n",
1483 vf->abs_vf_id,
1484 resp->pfdev_info.chip_num,
1485 resp->pfdev_info.db_size,
1486 resp->pfdev_info.indices_per_sb,
1487 resp->pfdev_info.capabilities,
1488 resc->num_rxqs,
1489 resc->num_txqs,
1490 resc->num_sbs,
1491 resc->num_mac_filters,
1492 resc->num_vlan_filters);
1493 vf->state = VF_ACQUIRED;
1494
1495 /* Prepare Response */
1496out:
1497 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_ACQUIRE,
1498 sizeof(struct pfvf_acquire_resp_tlv), vfpf_status);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03001499}
1500
Yuval Mintz6ddc7602016-05-11 16:36:23 +03001501static int __qed_iov_spoofchk_set(struct qed_hwfn *p_hwfn,
1502 struct qed_vf_info *p_vf, bool val)
1503{
1504 struct qed_sp_vport_update_params params;
1505 int rc;
1506
1507 if (val == p_vf->spoof_chk) {
1508 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1509 "Spoofchk value[%d] is already configured\n", val);
1510 return 0;
1511 }
1512
1513 memset(&params, 0, sizeof(struct qed_sp_vport_update_params));
1514 params.opaque_fid = p_vf->opaque_fid;
1515 params.vport_id = p_vf->vport_id;
1516 params.update_anti_spoofing_en_flg = 1;
1517 params.anti_spoofing_en = val;
1518
1519 rc = qed_sp_vport_update(p_hwfn, &params, QED_SPQ_MODE_EBLOCK, NULL);
Yuval Mintzcb1fa082016-07-27 14:45:20 +03001520 if (!rc) {
Yuval Mintz6ddc7602016-05-11 16:36:23 +03001521 p_vf->spoof_chk = val;
1522 p_vf->req_spoofchk_val = p_vf->spoof_chk;
1523 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1524 "Spoofchk val[%d] configured\n", val);
1525 } else {
1526 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1527 "Spoofchk configuration[val:%d] failed for VF[%d]\n",
1528 val, p_vf->relative_vf_id);
1529 }
1530
1531 return rc;
1532}
1533
Yuval Mintz08feecd2016-05-11 16:36:20 +03001534static int qed_iov_reconfigure_unicast_vlan(struct qed_hwfn *p_hwfn,
1535 struct qed_vf_info *p_vf)
1536{
1537 struct qed_filter_ucast filter;
1538 int rc = 0;
1539 int i;
1540
1541 memset(&filter, 0, sizeof(filter));
1542 filter.is_rx_filter = 1;
1543 filter.is_tx_filter = 1;
1544 filter.vport_to_add_to = p_vf->vport_id;
1545 filter.opcode = QED_FILTER_ADD;
1546
1547 /* Reconfigure vlans */
1548 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++) {
1549 if (!p_vf->shadow_config.vlans[i].used)
1550 continue;
1551
1552 filter.type = QED_FILTER_VLAN;
1553 filter.vlan = p_vf->shadow_config.vlans[i].vid;
Yuval Mintz1a635e42016-08-15 10:42:43 +03001554 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
Yuval Mintz08feecd2016-05-11 16:36:20 +03001555 "Reconfiguring VLAN [0x%04x] for VF [%04x]\n",
1556 filter.vlan, p_vf->relative_vf_id);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001557 rc = qed_sp_eth_filter_ucast(p_hwfn, p_vf->opaque_fid,
1558 &filter, QED_SPQ_MODE_CB, NULL);
Yuval Mintz08feecd2016-05-11 16:36:20 +03001559 if (rc) {
1560 DP_NOTICE(p_hwfn,
1561 "Failed to configure VLAN [%04x] to VF [%04x]\n",
1562 filter.vlan, p_vf->relative_vf_id);
1563 break;
1564 }
1565 }
1566
1567 return rc;
1568}
1569
1570static int
1571qed_iov_reconfigure_unicast_shadow(struct qed_hwfn *p_hwfn,
1572 struct qed_vf_info *p_vf, u64 events)
1573{
1574 int rc = 0;
1575
Yuval Mintz1a635e42016-08-15 10:42:43 +03001576 if ((events & BIT(VLAN_ADDR_FORCED)) &&
Yuval Mintz08feecd2016-05-11 16:36:20 +03001577 !(p_vf->configured_features & (1 << VLAN_ADDR_FORCED)))
1578 rc = qed_iov_reconfigure_unicast_vlan(p_hwfn, p_vf);
1579
1580 return rc;
1581}
1582
1583static int qed_iov_configure_vport_forced(struct qed_hwfn *p_hwfn,
1584 struct qed_vf_info *p_vf, u64 events)
1585{
1586 int rc = 0;
1587 struct qed_filter_ucast filter;
1588
1589 if (!p_vf->vport_instance)
1590 return -EINVAL;
1591
Yuval Mintz1a635e42016-08-15 10:42:43 +03001592 if (events & BIT(MAC_ADDR_FORCED)) {
Yuval Mintzeff16962016-05-11 16:36:21 +03001593 /* Since there's no way [currently] of removing the MAC,
1594 * we can always assume this means we need to force it.
1595 */
1596 memset(&filter, 0, sizeof(filter));
1597 filter.type = QED_FILTER_MAC;
1598 filter.opcode = QED_FILTER_REPLACE;
1599 filter.is_rx_filter = 1;
1600 filter.is_tx_filter = 1;
1601 filter.vport_to_add_to = p_vf->vport_id;
1602 ether_addr_copy(filter.mac, p_vf->bulletin.p_virt->mac);
1603
1604 rc = qed_sp_eth_filter_ucast(p_hwfn, p_vf->opaque_fid,
1605 &filter, QED_SPQ_MODE_CB, NULL);
1606 if (rc) {
1607 DP_NOTICE(p_hwfn,
1608 "PF failed to configure MAC for VF\n");
1609 return rc;
1610 }
1611
1612 p_vf->configured_features |= 1 << MAC_ADDR_FORCED;
1613 }
1614
Yuval Mintz1a635e42016-08-15 10:42:43 +03001615 if (events & BIT(VLAN_ADDR_FORCED)) {
Yuval Mintz08feecd2016-05-11 16:36:20 +03001616 struct qed_sp_vport_update_params vport_update;
1617 u8 removal;
1618 int i;
1619
1620 memset(&filter, 0, sizeof(filter));
1621 filter.type = QED_FILTER_VLAN;
1622 filter.is_rx_filter = 1;
1623 filter.is_tx_filter = 1;
1624 filter.vport_to_add_to = p_vf->vport_id;
1625 filter.vlan = p_vf->bulletin.p_virt->pvid;
1626 filter.opcode = filter.vlan ? QED_FILTER_REPLACE :
1627 QED_FILTER_FLUSH;
1628
1629 /* Send the ramrod */
1630 rc = qed_sp_eth_filter_ucast(p_hwfn, p_vf->opaque_fid,
1631 &filter, QED_SPQ_MODE_CB, NULL);
1632 if (rc) {
1633 DP_NOTICE(p_hwfn,
1634 "PF failed to configure VLAN for VF\n");
1635 return rc;
1636 }
1637
1638 /* Update the default-vlan & silent vlan stripping */
1639 memset(&vport_update, 0, sizeof(vport_update));
1640 vport_update.opaque_fid = p_vf->opaque_fid;
1641 vport_update.vport_id = p_vf->vport_id;
1642 vport_update.update_default_vlan_enable_flg = 1;
1643 vport_update.default_vlan_enable_flg = filter.vlan ? 1 : 0;
1644 vport_update.update_default_vlan_flg = 1;
1645 vport_update.default_vlan = filter.vlan;
1646
1647 vport_update.update_inner_vlan_removal_flg = 1;
1648 removal = filter.vlan ? 1
1649 : p_vf->shadow_config.inner_vlan_removal;
1650 vport_update.inner_vlan_removal_flg = removal;
1651 vport_update.silent_vlan_removal_flg = filter.vlan ? 1 : 0;
1652 rc = qed_sp_vport_update(p_hwfn,
1653 &vport_update,
1654 QED_SPQ_MODE_EBLOCK, NULL);
1655 if (rc) {
1656 DP_NOTICE(p_hwfn,
1657 "PF failed to configure VF vport for vlan\n");
1658 return rc;
1659 }
1660
1661 /* Update all the Rx queues */
1662 for (i = 0; i < QED_MAX_VF_CHAINS_PER_PF; i++) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001663 struct qed_queue_cid *p_cid;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001664
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001665 p_cid = p_vf->vf_queues[i].p_rx_cid;
1666 if (!p_cid)
Yuval Mintz08feecd2016-05-11 16:36:20 +03001667 continue;
1668
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001669 rc = qed_sp_eth_rx_queues_update(p_hwfn,
1670 (void **)&p_cid,
Yuval Mintz08feecd2016-05-11 16:36:20 +03001671 1, 0, 1,
1672 QED_SPQ_MODE_EBLOCK,
1673 NULL);
1674 if (rc) {
1675 DP_NOTICE(p_hwfn,
1676 "Failed to send Rx update fo queue[0x%04x]\n",
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001677 p_cid->rel.queue_id);
Yuval Mintz08feecd2016-05-11 16:36:20 +03001678 return rc;
1679 }
1680 }
1681
1682 if (filter.vlan)
1683 p_vf->configured_features |= 1 << VLAN_ADDR_FORCED;
1684 else
Yuval Mintz1a635e42016-08-15 10:42:43 +03001685 p_vf->configured_features &= ~BIT(VLAN_ADDR_FORCED);
Yuval Mintz08feecd2016-05-11 16:36:20 +03001686 }
1687
1688 /* If forced features are terminated, we need to configure the shadow
1689 * configuration back again.
1690 */
1691 if (events)
1692 qed_iov_reconfigure_unicast_shadow(p_hwfn, p_vf, events);
1693
1694 return rc;
1695}
1696
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001697static void qed_iov_vf_mbx_start_vport(struct qed_hwfn *p_hwfn,
1698 struct qed_ptt *p_ptt,
1699 struct qed_vf_info *vf)
1700{
1701 struct qed_sp_vport_start_params params = { 0 };
1702 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1703 struct vfpf_vport_start_tlv *start;
1704 u8 status = PFVF_STATUS_SUCCESS;
1705 struct qed_vf_info *vf_info;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001706 u64 *p_bitmap;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001707 int sb_id;
1708 int rc;
1709
1710 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vf->relative_vf_id, true);
1711 if (!vf_info) {
1712 DP_NOTICE(p_hwfn->cdev,
1713 "Failed to get VF info, invalid vfid [%d]\n",
1714 vf->relative_vf_id);
1715 return;
1716 }
1717
1718 vf->state = VF_ENABLED;
1719 start = &mbx->req_virt->start_vport;
1720
1721 /* Initialize Status block in CAU */
1722 for (sb_id = 0; sb_id < vf->num_sbs; sb_id++) {
1723 if (!start->sb_addr[sb_id]) {
1724 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1725 "VF[%d] did not fill the address of SB %d\n",
1726 vf->relative_vf_id, sb_id);
1727 break;
1728 }
1729
1730 qed_int_cau_conf_sb(p_hwfn, p_ptt,
1731 start->sb_addr[sb_id],
Yuval Mintz1a635e42016-08-15 10:42:43 +03001732 vf->igu_sbs[sb_id], vf->abs_vf_id, 1);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001733 }
1734 qed_iov_enable_vf_traffic(p_hwfn, p_ptt, vf);
1735
1736 vf->mtu = start->mtu;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001737 vf->shadow_config.inner_vlan_removal = start->inner_vlan_removal;
1738
1739 /* Take into consideration configuration forced by hypervisor;
1740 * If none is configured, use the supplied VF values [for old
1741 * vfs that would still be fine, since they passed '0' as padding].
1742 */
1743 p_bitmap = &vf_info->bulletin.p_virt->valid_bitmap;
Yuval Mintz1a635e42016-08-15 10:42:43 +03001744 if (!(*p_bitmap & BIT(VFPF_BULLETIN_UNTAGGED_DEFAULT_FORCED))) {
Yuval Mintz08feecd2016-05-11 16:36:20 +03001745 u8 vf_req = start->only_untagged;
1746
1747 vf_info->bulletin.p_virt->default_only_untagged = vf_req;
1748 *p_bitmap |= 1 << VFPF_BULLETIN_UNTAGGED_DEFAULT;
1749 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001750
1751 params.tpa_mode = start->tpa_mode;
1752 params.remove_inner_vlan = start->inner_vlan_removal;
Yuval Mintz831bfb0e2016-05-11 16:36:25 +03001753 params.tx_switching = true;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001754
Yuval Mintz08feecd2016-05-11 16:36:20 +03001755 params.only_untagged = vf_info->bulletin.p_virt->default_only_untagged;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001756 params.drop_ttl0 = false;
1757 params.concrete_fid = vf->concrete_fid;
1758 params.opaque_fid = vf->opaque_fid;
1759 params.vport_id = vf->vport_id;
1760 params.max_buffers_per_cqe = start->max_buffers_per_cqe;
1761 params.mtu = vf->mtu;
Yuval Mintz11a85d72016-08-22 13:25:10 +03001762 params.check_mac = true;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001763
1764 rc = qed_sp_eth_vport_start(p_hwfn, &params);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001765 if (rc) {
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001766 DP_ERR(p_hwfn,
1767 "qed_iov_vf_mbx_start_vport returned error %d\n", rc);
1768 status = PFVF_STATUS_FAILURE;
1769 } else {
1770 vf->vport_instance++;
Yuval Mintz08feecd2016-05-11 16:36:20 +03001771
1772 /* Force configuration if needed on the newly opened vport */
1773 qed_iov_configure_vport_forced(p_hwfn, vf, *p_bitmap);
Yuval Mintz6ddc7602016-05-11 16:36:23 +03001774
1775 __qed_iov_spoofchk_set(p_hwfn, vf, vf->req_spoofchk_val);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001776 }
1777 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_VPORT_START,
1778 sizeof(struct pfvf_def_resp_tlv), status);
1779}
1780
1781static void qed_iov_vf_mbx_stop_vport(struct qed_hwfn *p_hwfn,
1782 struct qed_ptt *p_ptt,
1783 struct qed_vf_info *vf)
1784{
1785 u8 status = PFVF_STATUS_SUCCESS;
1786 int rc;
1787
1788 vf->vport_instance--;
Yuval Mintz6ddc7602016-05-11 16:36:23 +03001789 vf->spoof_chk = false;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001790
1791 rc = qed_sp_vport_stop(p_hwfn, vf->opaque_fid, vf->vport_id);
Yuval Mintz1a635e42016-08-15 10:42:43 +03001792 if (rc) {
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001793 DP_ERR(p_hwfn, "qed_iov_vf_mbx_stop_vport returned error %d\n",
1794 rc);
1795 status = PFVF_STATUS_FAILURE;
1796 }
1797
Yuval Mintz08feecd2016-05-11 16:36:20 +03001798 /* Forget the configuration on the vport */
1799 vf->configured_features = 0;
1800 memset(&vf->shadow_config, 0, sizeof(vf->shadow_config));
1801
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001802 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_VPORT_TEARDOWN,
1803 sizeof(struct pfvf_def_resp_tlv), status);
1804}
1805
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001806static void qed_iov_vf_mbx_start_rxq_resp(struct qed_hwfn *p_hwfn,
1807 struct qed_ptt *p_ptt,
Yuval Mintza044df82016-08-22 13:25:09 +03001808 struct qed_vf_info *vf,
1809 u8 status, bool b_legacy)
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001810{
1811 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
1812 struct pfvf_start_queue_resp_tlv *p_tlv;
1813 struct vfpf_start_rxq_tlv *req;
Yuval Mintza044df82016-08-22 13:25:09 +03001814 u16 length;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001815
1816 mbx->offset = (u8 *)mbx->reply_virt;
1817
Yuval Mintza044df82016-08-22 13:25:09 +03001818 /* Taking a bigger struct instead of adding a TLV to list was a
1819 * mistake, but one which we're now stuck with, as some older
1820 * clients assume the size of the previous response.
1821 */
1822 if (!b_legacy)
1823 length = sizeof(*p_tlv);
1824 else
1825 length = sizeof(struct pfvf_def_resp_tlv);
1826
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001827 p_tlv = qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_START_RXQ,
Yuval Mintza044df82016-08-22 13:25:09 +03001828 length);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001829 qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_LIST_END,
1830 sizeof(struct channel_list_end_tlv));
1831
1832 /* Update the TLV with the response */
Yuval Mintza044df82016-08-22 13:25:09 +03001833 if ((status == PFVF_STATUS_SUCCESS) && !b_legacy) {
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001834 req = &mbx->req_virt->start_rxq;
Yuval Mintz351a4ded2016-06-02 10:23:29 +03001835 p_tlv->offset = PXP_VF_BAR0_START_MSDM_ZONE_B +
1836 offsetof(struct mstorm_vf_zone,
1837 non_trigger.eth_rx_queue_producers) +
1838 sizeof(struct eth_rx_prod_data) * req->rx_qid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001839 }
1840
Yuval Mintza044df82016-08-22 13:25:09 +03001841 qed_iov_send_response(p_hwfn, p_ptt, vf, length, status);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001842}
1843
1844static void qed_iov_vf_mbx_start_rxq(struct qed_hwfn *p_hwfn,
1845 struct qed_ptt *p_ptt,
1846 struct qed_vf_info *vf)
1847{
1848 struct qed_queue_start_common_params params;
1849 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
Yuval Mintz41086462016-06-05 13:11:13 +03001850 u8 status = PFVF_STATUS_NO_RESOURCE;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001851 struct qed_vf_q_info *p_queue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001852 struct vfpf_start_rxq_tlv *req;
Yuval Mintza044df82016-08-22 13:25:09 +03001853 bool b_legacy_vf = false;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001854 int rc;
1855
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001856 req = &mbx->req_virt->start_rxq;
Yuval Mintz41086462016-06-05 13:11:13 +03001857
1858 if (!qed_iov_validate_rxq(p_hwfn, vf, req->rx_qid) ||
1859 !qed_iov_validate_sb(p_hwfn, vf, req->hw_sb))
1860 goto out;
1861
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001862 /* Acquire a new queue-cid */
1863 p_queue = &vf->vf_queues[req->rx_qid];
1864
1865 memset(&params, 0, sizeof(params));
1866 params.queue_id = p_queue->fw_rx_qid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001867 params.vport_id = vf->vport_id;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001868 params.stats_id = vf->abs_vf_id + 0x10;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001869 params.sb = req->hw_sb;
1870 params.sb_idx = req->sb_index;
1871
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001872 p_queue->p_rx_cid = _qed_eth_queue_to_cid(p_hwfn,
1873 vf->opaque_fid,
1874 p_queue->fw_cid,
1875 req->rx_qid, &params);
1876 if (!p_queue->p_rx_cid)
1877 goto out;
1878
Yuval Mintza044df82016-08-22 13:25:09 +03001879 /* Legacy VFs have their Producers in a different location, which they
1880 * calculate on their own and clean the producer prior to this.
1881 */
1882 if (vf->acquire.vfdev_info.eth_fp_hsi_minor ==
1883 ETH_HSI_VER_NO_PKT_LEN_TUNN) {
1884 b_legacy_vf = true;
1885 } else {
1886 REG_WR(p_hwfn,
1887 GTT_BAR0_MAP_REG_MSDM_RAM +
1888 MSTORM_ETH_VF_PRODS_OFFSET(vf->abs_vf_id, req->rx_qid),
1889 0);
1890 }
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001891 p_queue->p_rx_cid->b_legacy_vf = b_legacy_vf;
Yuval Mintza044df82016-08-22 13:25:09 +03001892
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001893 rc = qed_eth_rxq_start_ramrod(p_hwfn,
1894 p_queue->p_rx_cid,
1895 req->bd_max_bytes,
1896 req->rxq_addr,
1897 req->cqe_pbl_addr, req->cqe_pbl_size);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001898 if (rc) {
1899 status = PFVF_STATUS_FAILURE;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001900 qed_eth_queue_cid_release(p_hwfn, p_queue->p_rx_cid);
1901 p_queue->p_rx_cid = NULL;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001902 } else {
Yuval Mintz41086462016-06-05 13:11:13 +03001903 status = PFVF_STATUS_SUCCESS;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001904 vf->num_active_rxqs++;
1905 }
1906
Yuval Mintz41086462016-06-05 13:11:13 +03001907out:
Yuval Mintza044df82016-08-22 13:25:09 +03001908 qed_iov_vf_mbx_start_rxq_resp(p_hwfn, p_ptt, vf, status, b_legacy_vf);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001909}
1910
Yuval Mintz5040acf2016-06-05 13:11:14 +03001911static void qed_iov_vf_mbx_start_txq_resp(struct qed_hwfn *p_hwfn,
1912 struct qed_ptt *p_ptt,
1913 struct qed_vf_info *p_vf, u8 status)
1914{
1915 struct qed_iov_vf_mbx *mbx = &p_vf->vf_mbx;
1916 struct pfvf_start_queue_resp_tlv *p_tlv;
Yuval Mintza044df82016-08-22 13:25:09 +03001917 bool b_legacy = false;
1918 u16 length;
Yuval Mintz5040acf2016-06-05 13:11:14 +03001919
1920 mbx->offset = (u8 *)mbx->reply_virt;
1921
Yuval Mintza044df82016-08-22 13:25:09 +03001922 /* Taking a bigger struct instead of adding a TLV to list was a
1923 * mistake, but one which we're now stuck with, as some older
1924 * clients assume the size of the previous response.
1925 */
1926 if (p_vf->acquire.vfdev_info.eth_fp_hsi_minor ==
1927 ETH_HSI_VER_NO_PKT_LEN_TUNN)
1928 b_legacy = true;
1929
1930 if (!b_legacy)
1931 length = sizeof(*p_tlv);
1932 else
1933 length = sizeof(struct pfvf_def_resp_tlv);
1934
Yuval Mintz5040acf2016-06-05 13:11:14 +03001935 p_tlv = qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_START_TXQ,
Yuval Mintza044df82016-08-22 13:25:09 +03001936 length);
Yuval Mintz5040acf2016-06-05 13:11:14 +03001937 qed_add_tlv(p_hwfn, &mbx->offset, CHANNEL_TLV_LIST_END,
1938 sizeof(struct channel_list_end_tlv));
1939
1940 /* Update the TLV with the response */
Yuval Mintza044df82016-08-22 13:25:09 +03001941 if ((status == PFVF_STATUS_SUCCESS) && !b_legacy) {
Yuval Mintz5040acf2016-06-05 13:11:14 +03001942 u16 qid = mbx->req_virt->start_txq.tx_qid;
1943
Ram Amrani51ff1722016-10-01 21:59:57 +03001944 p_tlv->offset = qed_db_addr_vf(p_vf->vf_queues[qid].fw_cid,
1945 DQ_DEMS_LEGACY);
Yuval Mintz5040acf2016-06-05 13:11:14 +03001946 }
1947
Yuval Mintza044df82016-08-22 13:25:09 +03001948 qed_iov_send_response(p_hwfn, p_ptt, p_vf, length, status);
Yuval Mintz5040acf2016-06-05 13:11:14 +03001949}
1950
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001951static void qed_iov_vf_mbx_start_txq(struct qed_hwfn *p_hwfn,
1952 struct qed_ptt *p_ptt,
1953 struct qed_vf_info *vf)
1954{
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001955 struct qed_queue_start_common_params params;
1956 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
Yuval Mintz41086462016-06-05 13:11:13 +03001957 u8 status = PFVF_STATUS_NO_RESOURCE;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001958 union qed_qm_pq_params pq_params;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001959 struct vfpf_start_txq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001960 struct qed_vf_q_info *p_queue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001961 int rc;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001962 u16 pq;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001963
1964 /* Prepare the parameters which would choose the right PQ */
1965 memset(&pq_params, 0, sizeof(pq_params));
1966 pq_params.eth.is_vf = 1;
1967 pq_params.eth.vf_id = vf->relative_vf_id;
1968
1969 memset(&params, 0, sizeof(params));
1970 req = &mbx->req_virt->start_txq;
Yuval Mintz41086462016-06-05 13:11:13 +03001971
1972 if (!qed_iov_validate_txq(p_hwfn, vf, req->tx_qid) ||
1973 !qed_iov_validate_sb(p_hwfn, vf, req->hw_sb))
1974 goto out;
1975
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001976 /* Acquire a new queue-cid */
1977 p_queue = &vf->vf_queues[req->tx_qid];
1978
1979 params.queue_id = p_queue->fw_tx_qid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001980 params.vport_id = vf->vport_id;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001981 params.stats_id = vf->abs_vf_id + 0x10;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001982 params.sb = req->hw_sb;
1983 params.sb_idx = req->sb_index;
1984
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001985 p_queue->p_tx_cid = _qed_eth_queue_to_cid(p_hwfn,
1986 vf->opaque_fid,
1987 p_queue->fw_cid,
1988 req->tx_qid, &params);
1989 if (!p_queue->p_tx_cid)
1990 goto out;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001991
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001992 pq = qed_get_qm_pq(p_hwfn, PROTOCOLID_ETH, &pq_params);
1993 rc = qed_eth_txq_start_ramrod(p_hwfn, p_queue->p_tx_cid,
1994 req->pbl_addr, req->pbl_size, pq);
Yuval Mintz41086462016-06-05 13:11:13 +03001995 if (rc) {
Yuval Mintzdacd88d2016-05-11 16:36:16 +03001996 status = PFVF_STATUS_FAILURE;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02001997 qed_eth_queue_cid_release(p_hwfn, p_queue->p_tx_cid);
1998 p_queue->p_tx_cid = NULL;
Yuval Mintz41086462016-06-05 13:11:13 +03001999 } else {
2000 status = PFVF_STATUS_SUCCESS;
Yuval Mintz41086462016-06-05 13:11:13 +03002001 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002002
Yuval Mintz41086462016-06-05 13:11:13 +03002003out:
Yuval Mintz5040acf2016-06-05 13:11:14 +03002004 qed_iov_vf_mbx_start_txq_resp(p_hwfn, p_ptt, vf, status);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002005}
2006
2007static int qed_iov_vf_stop_rxqs(struct qed_hwfn *p_hwfn,
2008 struct qed_vf_info *vf,
2009 u16 rxq_id, u8 num_rxqs, bool cqe_completion)
2010{
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002011 struct qed_vf_q_info *p_queue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002012 int rc = 0;
2013 int qid;
2014
2015 if (rxq_id + num_rxqs > ARRAY_SIZE(vf->vf_queues))
2016 return -EINVAL;
2017
2018 for (qid = rxq_id; qid < rxq_id + num_rxqs; qid++) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002019 p_queue = &vf->vf_queues[qid];
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002020
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002021 if (!p_queue->p_rx_cid)
2022 continue;
2023
2024 rc = qed_eth_rx_queue_stop(p_hwfn,
2025 p_queue->p_rx_cid,
2026 false, cqe_completion);
2027 if (rc)
2028 return rc;
2029
2030 vf->vf_queues[qid].p_rx_cid = NULL;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002031 vf->num_active_rxqs--;
2032 }
2033
2034 return rc;
2035}
2036
2037static int qed_iov_vf_stop_txqs(struct qed_hwfn *p_hwfn,
2038 struct qed_vf_info *vf, u16 txq_id, u8 num_txqs)
2039{
2040 int rc = 0;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002041 struct qed_vf_q_info *p_queue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002042 int qid;
2043
2044 if (txq_id + num_txqs > ARRAY_SIZE(vf->vf_queues))
2045 return -EINVAL;
2046
2047 for (qid = txq_id; qid < txq_id + num_txqs; qid++) {
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002048 p_queue = &vf->vf_queues[qid];
2049 if (!p_queue->p_tx_cid)
2050 continue;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002051
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002052 rc = qed_eth_tx_queue_stop(p_hwfn, p_queue->p_tx_cid);
2053 if (rc)
2054 return rc;
2055
2056 p_queue->p_tx_cid = NULL;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002057 }
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002058
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002059 return rc;
2060}
2061
2062static void qed_iov_vf_mbx_stop_rxqs(struct qed_hwfn *p_hwfn,
2063 struct qed_ptt *p_ptt,
2064 struct qed_vf_info *vf)
2065{
2066 u16 length = sizeof(struct pfvf_def_resp_tlv);
2067 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
2068 u8 status = PFVF_STATUS_SUCCESS;
2069 struct vfpf_stop_rxqs_tlv *req;
2070 int rc;
2071
2072 /* We give the option of starting from qid != 0, in this case we
2073 * need to make sure that qid + num_qs doesn't exceed the actual
2074 * amount of queues that exist.
2075 */
2076 req = &mbx->req_virt->stop_rxqs;
2077 rc = qed_iov_vf_stop_rxqs(p_hwfn, vf, req->rx_qid,
2078 req->num_rxqs, req->cqe_completion);
2079 if (rc)
2080 status = PFVF_STATUS_FAILURE;
2081
2082 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_STOP_RXQS,
2083 length, status);
2084}
2085
2086static void qed_iov_vf_mbx_stop_txqs(struct qed_hwfn *p_hwfn,
2087 struct qed_ptt *p_ptt,
2088 struct qed_vf_info *vf)
2089{
2090 u16 length = sizeof(struct pfvf_def_resp_tlv);
2091 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
2092 u8 status = PFVF_STATUS_SUCCESS;
2093 struct vfpf_stop_txqs_tlv *req;
2094 int rc;
2095
2096 /* We give the option of starting from qid != 0, in this case we
2097 * need to make sure that qid + num_qs doesn't exceed the actual
2098 * amount of queues that exist.
2099 */
2100 req = &mbx->req_virt->stop_txqs;
2101 rc = qed_iov_vf_stop_txqs(p_hwfn, vf, req->tx_qid, req->num_txqs);
2102 if (rc)
2103 status = PFVF_STATUS_FAILURE;
2104
2105 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_STOP_TXQS,
2106 length, status);
2107}
2108
Yuval Mintz17b235c2016-05-11 16:36:18 +03002109static void qed_iov_vf_mbx_update_rxqs(struct qed_hwfn *p_hwfn,
2110 struct qed_ptt *p_ptt,
2111 struct qed_vf_info *vf)
2112{
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002113 struct qed_queue_cid *handlers[QED_MAX_VF_CHAINS_PER_PF];
Yuval Mintz17b235c2016-05-11 16:36:18 +03002114 u16 length = sizeof(struct pfvf_def_resp_tlv);
2115 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
2116 struct vfpf_update_rxq_tlv *req;
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002117 u8 status = PFVF_STATUS_FAILURE;
Yuval Mintz17b235c2016-05-11 16:36:18 +03002118 u8 complete_event_flg;
2119 u8 complete_cqe_flg;
2120 u16 qid;
2121 int rc;
2122 u8 i;
2123
2124 req = &mbx->req_virt->update_rxq;
2125 complete_cqe_flg = !!(req->flags & VFPF_RXQ_UPD_COMPLETE_CQE_FLAG);
2126 complete_event_flg = !!(req->flags & VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG);
2127
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002128 /* Validate inputs */
2129 if (req->num_rxqs + req->rx_qid > QED_MAX_VF_CHAINS_PER_PF ||
2130 !qed_iov_validate_rxq(p_hwfn, vf, req->rx_qid)) {
2131 DP_INFO(p_hwfn, "VF[%d]: Incorrect Rxqs [%04x, %02x]\n",
2132 vf->relative_vf_id, req->rx_qid, req->num_rxqs);
2133 goto out;
Yuval Mintz17b235c2016-05-11 16:36:18 +03002134 }
2135
Mintz, Yuval3da7a372016-11-29 16:47:06 +02002136 for (i = 0; i < req->num_rxqs; i++) {
2137 qid = req->rx_qid + i;
2138 if (!vf->vf_queues[qid].p_rx_cid) {
2139 DP_INFO(p_hwfn,
2140 "VF[%d] rx_qid = %d isn`t active!\n",
2141 vf->relative_vf_id, qid);
2142 goto out;
2143 }
2144
2145 handlers[i] = vf->vf_queues[qid].p_rx_cid;
2146 }
2147
2148 rc = qed_sp_eth_rx_queues_update(p_hwfn, (void **)&handlers,
2149 req->num_rxqs,
2150 complete_cqe_flg,
2151 complete_event_flg,
2152 QED_SPQ_MODE_EBLOCK, NULL);
2153 if (rc)
2154 goto out;
2155
2156 status = PFVF_STATUS_SUCCESS;
2157out:
Yuval Mintz17b235c2016-05-11 16:36:18 +03002158 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_UPDATE_RXQ,
2159 length, status);
2160}
2161
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002162void *qed_iov_search_list_tlvs(struct qed_hwfn *p_hwfn,
2163 void *p_tlvs_list, u16 req_type)
2164{
2165 struct channel_tlv *p_tlv = (struct channel_tlv *)p_tlvs_list;
2166 int len = 0;
2167
2168 do {
2169 if (!p_tlv->length) {
2170 DP_NOTICE(p_hwfn, "Zero length TLV found\n");
2171 return NULL;
2172 }
2173
2174 if (p_tlv->type == req_type) {
2175 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2176 "Extended tlv type %d, length %d found\n",
2177 p_tlv->type, p_tlv->length);
2178 return p_tlv;
2179 }
2180
2181 len += p_tlv->length;
2182 p_tlv = (struct channel_tlv *)((u8 *)p_tlv + p_tlv->length);
2183
2184 if ((len + p_tlv->length) > TLV_BUFFER_SIZE) {
2185 DP_NOTICE(p_hwfn, "TLVs has overrun the buffer size\n");
2186 return NULL;
2187 }
2188 } while (p_tlv->type != CHANNEL_TLV_LIST_END);
2189
2190 return NULL;
2191}
2192
2193static void
2194qed_iov_vp_update_act_param(struct qed_hwfn *p_hwfn,
2195 struct qed_sp_vport_update_params *p_data,
2196 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2197{
2198 struct vfpf_vport_update_activate_tlv *p_act_tlv;
2199 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
2200
2201 p_act_tlv = (struct vfpf_vport_update_activate_tlv *)
2202 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2203 if (!p_act_tlv)
2204 return;
2205
2206 p_data->update_vport_active_rx_flg = p_act_tlv->update_rx;
2207 p_data->vport_active_rx_flg = p_act_tlv->active_rx;
2208 p_data->update_vport_active_tx_flg = p_act_tlv->update_tx;
2209 p_data->vport_active_tx_flg = p_act_tlv->active_tx;
2210 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_ACTIVATE;
2211}
2212
2213static void
Yuval Mintz17b235c2016-05-11 16:36:18 +03002214qed_iov_vp_update_vlan_param(struct qed_hwfn *p_hwfn,
2215 struct qed_sp_vport_update_params *p_data,
2216 struct qed_vf_info *p_vf,
2217 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2218{
2219 struct vfpf_vport_update_vlan_strip_tlv *p_vlan_tlv;
2220 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP;
2221
2222 p_vlan_tlv = (struct vfpf_vport_update_vlan_strip_tlv *)
2223 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2224 if (!p_vlan_tlv)
2225 return;
2226
Yuval Mintz08feecd2016-05-11 16:36:20 +03002227 p_vf->shadow_config.inner_vlan_removal = p_vlan_tlv->remove_vlan;
2228
2229 /* Ignore the VF request if we're forcing a vlan */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002230 if (!(p_vf->configured_features & BIT(VLAN_ADDR_FORCED))) {
Yuval Mintz08feecd2016-05-11 16:36:20 +03002231 p_data->update_inner_vlan_removal_flg = 1;
2232 p_data->inner_vlan_removal_flg = p_vlan_tlv->remove_vlan;
2233 }
Yuval Mintz17b235c2016-05-11 16:36:18 +03002234
2235 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_VLAN_STRIP;
2236}
2237
2238static void
2239qed_iov_vp_update_tx_switch(struct qed_hwfn *p_hwfn,
2240 struct qed_sp_vport_update_params *p_data,
2241 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2242{
2243 struct vfpf_vport_update_tx_switch_tlv *p_tx_switch_tlv;
2244 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
2245
2246 p_tx_switch_tlv = (struct vfpf_vport_update_tx_switch_tlv *)
2247 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt,
2248 tlv);
2249 if (!p_tx_switch_tlv)
2250 return;
2251
2252 p_data->update_tx_switching_flg = 1;
2253 p_data->tx_switching_flg = p_tx_switch_tlv->tx_switching;
2254 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_TX_SWITCH;
2255}
2256
2257static void
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002258qed_iov_vp_update_mcast_bin_param(struct qed_hwfn *p_hwfn,
2259 struct qed_sp_vport_update_params *p_data,
2260 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2261{
2262 struct vfpf_vport_update_mcast_bin_tlv *p_mcast_tlv;
2263 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_MCAST;
2264
2265 p_mcast_tlv = (struct vfpf_vport_update_mcast_bin_tlv *)
2266 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2267 if (!p_mcast_tlv)
2268 return;
2269
2270 p_data->update_approx_mcast_flg = 1;
2271 memcpy(p_data->bins, p_mcast_tlv->bins,
2272 sizeof(unsigned long) * ETH_MULTICAST_MAC_BINS_IN_REGS);
2273 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_MCAST;
2274}
2275
2276static void
2277qed_iov_vp_update_accept_flag(struct qed_hwfn *p_hwfn,
2278 struct qed_sp_vport_update_params *p_data,
2279 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2280{
2281 struct qed_filter_accept_flags *p_flags = &p_data->accept_flags;
2282 struct vfpf_vport_update_accept_param_tlv *p_accept_tlv;
2283 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
2284
2285 p_accept_tlv = (struct vfpf_vport_update_accept_param_tlv *)
2286 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2287 if (!p_accept_tlv)
2288 return;
2289
2290 p_flags->update_rx_mode_config = p_accept_tlv->update_rx_mode;
2291 p_flags->rx_accept_filter = p_accept_tlv->rx_accept_filter;
2292 p_flags->update_tx_mode_config = p_accept_tlv->update_tx_mode;
2293 p_flags->tx_accept_filter = p_accept_tlv->tx_accept_filter;
2294 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_ACCEPT_PARAM;
2295}
2296
2297static void
Yuval Mintz17b235c2016-05-11 16:36:18 +03002298qed_iov_vp_update_accept_any_vlan(struct qed_hwfn *p_hwfn,
2299 struct qed_sp_vport_update_params *p_data,
2300 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2301{
2302 struct vfpf_vport_update_accept_any_vlan_tlv *p_accept_any_vlan;
2303 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
2304
2305 p_accept_any_vlan = (struct vfpf_vport_update_accept_any_vlan_tlv *)
2306 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt,
2307 tlv);
2308 if (!p_accept_any_vlan)
2309 return;
2310
2311 p_data->accept_any_vlan = p_accept_any_vlan->accept_any_vlan;
2312 p_data->update_accept_any_vlan_flg =
2313 p_accept_any_vlan->update_accept_any_vlan_flg;
2314 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_ACCEPT_ANY_VLAN;
2315}
2316
2317static void
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002318qed_iov_vp_update_rss_param(struct qed_hwfn *p_hwfn,
2319 struct qed_vf_info *vf,
2320 struct qed_sp_vport_update_params *p_data,
2321 struct qed_rss_params *p_rss,
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002322 struct qed_iov_vf_mbx *p_mbx,
2323 u16 *tlvs_mask, u16 *tlvs_accepted)
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002324{
2325 struct vfpf_vport_update_rss_tlv *p_rss_tlv;
2326 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_RSS;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002327 bool b_reject = false;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002328 u16 table_size;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002329 u16 i, q_idx;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002330
2331 p_rss_tlv = (struct vfpf_vport_update_rss_tlv *)
2332 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2333 if (!p_rss_tlv) {
2334 p_data->rss_params = NULL;
2335 return;
2336 }
2337
2338 memset(p_rss, 0, sizeof(struct qed_rss_params));
2339
2340 p_rss->update_rss_config = !!(p_rss_tlv->update_rss_flags &
2341 VFPF_UPDATE_RSS_CONFIG_FLAG);
2342 p_rss->update_rss_capabilities = !!(p_rss_tlv->update_rss_flags &
2343 VFPF_UPDATE_RSS_CAPS_FLAG);
2344 p_rss->update_rss_ind_table = !!(p_rss_tlv->update_rss_flags &
2345 VFPF_UPDATE_RSS_IND_TABLE_FLAG);
2346 p_rss->update_rss_key = !!(p_rss_tlv->update_rss_flags &
2347 VFPF_UPDATE_RSS_KEY_FLAG);
2348
2349 p_rss->rss_enable = p_rss_tlv->rss_enable;
2350 p_rss->rss_eng_id = vf->relative_vf_id + 1;
2351 p_rss->rss_caps = p_rss_tlv->rss_caps;
2352 p_rss->rss_table_size_log = p_rss_tlv->rss_table_size_log;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002353 memcpy(p_rss->rss_key, p_rss_tlv->rss_key, sizeof(p_rss->rss_key));
2354
2355 table_size = min_t(u16, ARRAY_SIZE(p_rss->rss_ind_table),
2356 (1 << p_rss_tlv->rss_table_size_log));
2357
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002358 for (i = 0; i < table_size; i++) {
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002359 q_idx = p_rss_tlv->rss_ind_table[i];
2360 if (!qed_iov_validate_rxq(p_hwfn, vf, q_idx)) {
2361 DP_VERBOSE(p_hwfn,
2362 QED_MSG_IOV,
2363 "VF[%d]: Omitting RSS due to wrong queue %04x\n",
2364 vf->relative_vf_id, q_idx);
2365 b_reject = true;
2366 goto out;
2367 }
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002368
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002369 if (!vf->vf_queues[q_idx].p_rx_cid) {
2370 DP_VERBOSE(p_hwfn,
2371 QED_MSG_IOV,
2372 "VF[%d]: Omitting RSS due to inactive queue %08x\n",
2373 vf->relative_vf_id, q_idx);
2374 b_reject = true;
2375 goto out;
2376 }
2377
2378 p_rss->rss_ind_table[i] = vf->vf_queues[q_idx].p_rx_cid;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002379 }
2380
2381 p_data->rss_params = p_rss;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002382out:
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002383 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_RSS;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002384 if (!b_reject)
2385 *tlvs_accepted |= 1 << QED_IOV_VP_UPDATE_RSS;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002386}
2387
Yuval Mintz17b235c2016-05-11 16:36:18 +03002388static void
2389qed_iov_vp_update_sge_tpa_param(struct qed_hwfn *p_hwfn,
2390 struct qed_vf_info *vf,
2391 struct qed_sp_vport_update_params *p_data,
2392 struct qed_sge_tpa_params *p_sge_tpa,
2393 struct qed_iov_vf_mbx *p_mbx, u16 *tlvs_mask)
2394{
2395 struct vfpf_vport_update_sge_tpa_tlv *p_sge_tpa_tlv;
2396 u16 tlv = CHANNEL_TLV_VPORT_UPDATE_SGE_TPA;
2397
2398 p_sge_tpa_tlv = (struct vfpf_vport_update_sge_tpa_tlv *)
2399 qed_iov_search_list_tlvs(p_hwfn, p_mbx->req_virt, tlv);
2400
2401 if (!p_sge_tpa_tlv) {
2402 p_data->sge_tpa_params = NULL;
2403 return;
2404 }
2405
2406 memset(p_sge_tpa, 0, sizeof(struct qed_sge_tpa_params));
2407
2408 p_sge_tpa->update_tpa_en_flg =
2409 !!(p_sge_tpa_tlv->update_sge_tpa_flags & VFPF_UPDATE_TPA_EN_FLAG);
2410 p_sge_tpa->update_tpa_param_flg =
2411 !!(p_sge_tpa_tlv->update_sge_tpa_flags &
2412 VFPF_UPDATE_TPA_PARAM_FLAG);
2413
2414 p_sge_tpa->tpa_ipv4_en_flg =
2415 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_IPV4_EN_FLAG);
2416 p_sge_tpa->tpa_ipv6_en_flg =
2417 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_IPV6_EN_FLAG);
2418 p_sge_tpa->tpa_pkt_split_flg =
2419 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_PKT_SPLIT_FLAG);
2420 p_sge_tpa->tpa_hdr_data_split_flg =
2421 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_HDR_DATA_SPLIT_FLAG);
2422 p_sge_tpa->tpa_gro_consistent_flg =
2423 !!(p_sge_tpa_tlv->sge_tpa_flags & VFPF_TPA_GRO_CONSIST_FLAG);
2424
2425 p_sge_tpa->tpa_max_aggs_num = p_sge_tpa_tlv->tpa_max_aggs_num;
2426 p_sge_tpa->tpa_max_size = p_sge_tpa_tlv->tpa_max_size;
2427 p_sge_tpa->tpa_min_size_to_start = p_sge_tpa_tlv->tpa_min_size_to_start;
2428 p_sge_tpa->tpa_min_size_to_cont = p_sge_tpa_tlv->tpa_min_size_to_cont;
2429 p_sge_tpa->max_buffers_per_cqe = p_sge_tpa_tlv->max_buffers_per_cqe;
2430
2431 p_data->sge_tpa_params = p_sge_tpa;
2432
2433 *tlvs_mask |= 1 << QED_IOV_VP_UPDATE_SGE_TPA;
2434}
2435
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002436static void qed_iov_vf_mbx_vport_update(struct qed_hwfn *p_hwfn,
2437 struct qed_ptt *p_ptt,
2438 struct qed_vf_info *vf)
2439{
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002440 struct qed_rss_params *p_rss_params = NULL;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002441 struct qed_sp_vport_update_params params;
2442 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
Yuval Mintz17b235c2016-05-11 16:36:18 +03002443 struct qed_sge_tpa_params sge_tpa_params;
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002444 u16 tlvs_mask = 0, tlvs_accepted = 0;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002445 u8 status = PFVF_STATUS_SUCCESS;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002446 u16 length;
2447 int rc;
2448
Yuval Mintz41086462016-06-05 13:11:13 +03002449 /* Valiate PF can send such a request */
2450 if (!vf->vport_instance) {
2451 DP_VERBOSE(p_hwfn,
2452 QED_MSG_IOV,
2453 "No VPORT instance available for VF[%d], failing vport update\n",
2454 vf->abs_vf_id);
2455 status = PFVF_STATUS_FAILURE;
2456 goto out;
2457 }
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002458 p_rss_params = vzalloc(sizeof(*p_rss_params));
2459 if (p_rss_params == NULL) {
2460 status = PFVF_STATUS_FAILURE;
2461 goto out;
2462 }
Yuval Mintz41086462016-06-05 13:11:13 +03002463
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002464 memset(&params, 0, sizeof(params));
2465 params.opaque_fid = vf->opaque_fid;
2466 params.vport_id = vf->vport_id;
2467 params.rss_params = NULL;
2468
2469 /* Search for extended tlvs list and update values
2470 * from VF in struct qed_sp_vport_update_params.
2471 */
2472 qed_iov_vp_update_act_param(p_hwfn, &params, mbx, &tlvs_mask);
Yuval Mintz17b235c2016-05-11 16:36:18 +03002473 qed_iov_vp_update_vlan_param(p_hwfn, &params, vf, mbx, &tlvs_mask);
2474 qed_iov_vp_update_tx_switch(p_hwfn, &params, mbx, &tlvs_mask);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002475 qed_iov_vp_update_mcast_bin_param(p_hwfn, &params, mbx, &tlvs_mask);
2476 qed_iov_vp_update_accept_flag(p_hwfn, &params, mbx, &tlvs_mask);
Yuval Mintz17b235c2016-05-11 16:36:18 +03002477 qed_iov_vp_update_accept_any_vlan(p_hwfn, &params, mbx, &tlvs_mask);
2478 qed_iov_vp_update_sge_tpa_param(p_hwfn, vf, &params,
2479 &sge_tpa_params, mbx, &tlvs_mask);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002480
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002481 tlvs_accepted = tlvs_mask;
2482
2483 /* Some of the extended TLVs need to be validated first; In that case,
2484 * they can update the mask without updating the accepted [so that
2485 * PF could communicate to VF it has rejected request].
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002486 */
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002487 qed_iov_vp_update_rss_param(p_hwfn, vf, &params, p_rss_params,
2488 mbx, &tlvs_mask, &tlvs_accepted);
2489
2490 if (!tlvs_accepted) {
2491 if (tlvs_mask)
2492 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2493 "Upper-layer prevents VF vport configuration\n");
2494 else
2495 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2496 "No feature tlvs found for vport update\n");
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002497 status = PFVF_STATUS_NOT_SUPPORTED;
2498 goto out;
2499 }
2500
2501 rc = qed_sp_vport_update(p_hwfn, &params, QED_SPQ_MODE_EBLOCK, NULL);
2502
2503 if (rc)
2504 status = PFVF_STATUS_FAILURE;
2505
2506out:
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002507 vfree(p_rss_params);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002508 length = qed_iov_prep_vp_update_resp_tlvs(p_hwfn, vf, mbx, status,
Mintz, Yuvalf29ffdb2017-01-01 13:57:07 +02002509 tlvs_mask, tlvs_accepted);
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002510 qed_iov_send_response(p_hwfn, p_ptt, vf, length, status);
2511}
2512
Yuval Mintz8246d0b2016-06-05 13:11:15 +03002513static int qed_iov_vf_update_vlan_shadow(struct qed_hwfn *p_hwfn,
2514 struct qed_vf_info *p_vf,
2515 struct qed_filter_ucast *p_params)
Yuval Mintz08feecd2016-05-11 16:36:20 +03002516{
2517 int i;
2518
Yuval Mintz08feecd2016-05-11 16:36:20 +03002519 /* First remove entries and then add new ones */
2520 if (p_params->opcode == QED_FILTER_REMOVE) {
2521 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++)
2522 if (p_vf->shadow_config.vlans[i].used &&
2523 p_vf->shadow_config.vlans[i].vid ==
2524 p_params->vlan) {
2525 p_vf->shadow_config.vlans[i].used = false;
2526 break;
2527 }
2528 if (i == QED_ETH_VF_NUM_VLAN_FILTERS + 1) {
2529 DP_VERBOSE(p_hwfn,
2530 QED_MSG_IOV,
2531 "VF [%d] - Tries to remove a non-existing vlan\n",
2532 p_vf->relative_vf_id);
2533 return -EINVAL;
2534 }
2535 } else if (p_params->opcode == QED_FILTER_REPLACE ||
2536 p_params->opcode == QED_FILTER_FLUSH) {
2537 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++)
2538 p_vf->shadow_config.vlans[i].used = false;
2539 }
2540
2541 /* In forced mode, we're willing to remove entries - but we don't add
2542 * new ones.
2543 */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002544 if (p_vf->bulletin.p_virt->valid_bitmap & BIT(VLAN_ADDR_FORCED))
Yuval Mintz08feecd2016-05-11 16:36:20 +03002545 return 0;
2546
2547 if (p_params->opcode == QED_FILTER_ADD ||
2548 p_params->opcode == QED_FILTER_REPLACE) {
2549 for (i = 0; i < QED_ETH_VF_NUM_VLAN_FILTERS + 1; i++) {
2550 if (p_vf->shadow_config.vlans[i].used)
2551 continue;
2552
2553 p_vf->shadow_config.vlans[i].used = true;
2554 p_vf->shadow_config.vlans[i].vid = p_params->vlan;
2555 break;
2556 }
2557
2558 if (i == QED_ETH_VF_NUM_VLAN_FILTERS + 1) {
2559 DP_VERBOSE(p_hwfn,
2560 QED_MSG_IOV,
2561 "VF [%d] - Tries to configure more than %d vlan filters\n",
2562 p_vf->relative_vf_id,
2563 QED_ETH_VF_NUM_VLAN_FILTERS + 1);
2564 return -EINVAL;
2565 }
2566 }
2567
2568 return 0;
2569}
2570
Yuval Mintz8246d0b2016-06-05 13:11:15 +03002571static int qed_iov_vf_update_mac_shadow(struct qed_hwfn *p_hwfn,
2572 struct qed_vf_info *p_vf,
2573 struct qed_filter_ucast *p_params)
2574{
2575 int i;
2576
2577 /* If we're in forced-mode, we don't allow any change */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002578 if (p_vf->bulletin.p_virt->valid_bitmap & BIT(MAC_ADDR_FORCED))
Yuval Mintz8246d0b2016-06-05 13:11:15 +03002579 return 0;
2580
2581 /* First remove entries and then add new ones */
2582 if (p_params->opcode == QED_FILTER_REMOVE) {
2583 for (i = 0; i < QED_ETH_VF_NUM_MAC_FILTERS; i++) {
2584 if (ether_addr_equal(p_vf->shadow_config.macs[i],
2585 p_params->mac)) {
2586 memset(p_vf->shadow_config.macs[i], 0,
2587 ETH_ALEN);
2588 break;
2589 }
2590 }
2591
2592 if (i == QED_ETH_VF_NUM_MAC_FILTERS) {
2593 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2594 "MAC isn't configured\n");
2595 return -EINVAL;
2596 }
2597 } else if (p_params->opcode == QED_FILTER_REPLACE ||
2598 p_params->opcode == QED_FILTER_FLUSH) {
2599 for (i = 0; i < QED_ETH_VF_NUM_MAC_FILTERS; i++)
2600 memset(p_vf->shadow_config.macs[i], 0, ETH_ALEN);
2601 }
2602
2603 /* List the new MAC address */
2604 if (p_params->opcode != QED_FILTER_ADD &&
2605 p_params->opcode != QED_FILTER_REPLACE)
2606 return 0;
2607
2608 for (i = 0; i < QED_ETH_VF_NUM_MAC_FILTERS; i++) {
2609 if (is_zero_ether_addr(p_vf->shadow_config.macs[i])) {
2610 ether_addr_copy(p_vf->shadow_config.macs[i],
2611 p_params->mac);
2612 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2613 "Added MAC at %d entry in shadow\n", i);
2614 break;
2615 }
2616 }
2617
2618 if (i == QED_ETH_VF_NUM_MAC_FILTERS) {
2619 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "No available place for MAC\n");
2620 return -EINVAL;
2621 }
2622
2623 return 0;
2624}
2625
2626static int
2627qed_iov_vf_update_unicast_shadow(struct qed_hwfn *p_hwfn,
2628 struct qed_vf_info *p_vf,
2629 struct qed_filter_ucast *p_params)
2630{
2631 int rc = 0;
2632
2633 if (p_params->type == QED_FILTER_MAC) {
2634 rc = qed_iov_vf_update_mac_shadow(p_hwfn, p_vf, p_params);
2635 if (rc)
2636 return rc;
2637 }
2638
2639 if (p_params->type == QED_FILTER_VLAN)
2640 rc = qed_iov_vf_update_vlan_shadow(p_hwfn, p_vf, p_params);
2641
2642 return rc;
2643}
2644
Baoyou Xieba569472016-09-09 09:21:15 +08002645static int qed_iov_chk_ucast(struct qed_hwfn *hwfn,
2646 int vfid, struct qed_filter_ucast *params)
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002647{
2648 struct qed_public_vf_info *vf;
2649
2650 vf = qed_iov_get_public_vf_info(hwfn, vfid, true);
2651 if (!vf)
2652 return -EINVAL;
2653
2654 /* No real decision to make; Store the configured MAC */
2655 if (params->type == QED_FILTER_MAC ||
2656 params->type == QED_FILTER_MAC_VLAN)
2657 ether_addr_copy(vf->mac, params->mac);
2658
2659 return 0;
2660}
2661
2662static void qed_iov_vf_mbx_ucast_filter(struct qed_hwfn *p_hwfn,
2663 struct qed_ptt *p_ptt,
2664 struct qed_vf_info *vf)
2665{
Yuval Mintz08feecd2016-05-11 16:36:20 +03002666 struct qed_bulletin_content *p_bulletin = vf->bulletin.p_virt;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002667 struct qed_iov_vf_mbx *mbx = &vf->vf_mbx;
2668 struct vfpf_ucast_filter_tlv *req;
2669 u8 status = PFVF_STATUS_SUCCESS;
2670 struct qed_filter_ucast params;
2671 int rc;
2672
2673 /* Prepare the unicast filter params */
2674 memset(&params, 0, sizeof(struct qed_filter_ucast));
2675 req = &mbx->req_virt->ucast_filter;
2676 params.opcode = (enum qed_filter_opcode)req->opcode;
2677 params.type = (enum qed_filter_ucast_type)req->type;
2678
2679 params.is_rx_filter = 1;
2680 params.is_tx_filter = 1;
2681 params.vport_to_remove_from = vf->vport_id;
2682 params.vport_to_add_to = vf->vport_id;
2683 memcpy(params.mac, req->mac, ETH_ALEN);
2684 params.vlan = req->vlan;
2685
2686 DP_VERBOSE(p_hwfn,
2687 QED_MSG_IOV,
2688 "VF[%d]: opcode 0x%02x type 0x%02x [%s %s] [vport 0x%02x] MAC %02x:%02x:%02x:%02x:%02x:%02x, vlan 0x%04x\n",
2689 vf->abs_vf_id, params.opcode, params.type,
2690 params.is_rx_filter ? "RX" : "",
2691 params.is_tx_filter ? "TX" : "",
2692 params.vport_to_add_to,
2693 params.mac[0], params.mac[1],
2694 params.mac[2], params.mac[3],
2695 params.mac[4], params.mac[5], params.vlan);
2696
2697 if (!vf->vport_instance) {
2698 DP_VERBOSE(p_hwfn,
2699 QED_MSG_IOV,
2700 "No VPORT instance available for VF[%d], failing ucast MAC configuration\n",
2701 vf->abs_vf_id);
2702 status = PFVF_STATUS_FAILURE;
2703 goto out;
2704 }
2705
Yuval Mintz08feecd2016-05-11 16:36:20 +03002706 /* Update shadow copy of the VF configuration */
2707 if (qed_iov_vf_update_unicast_shadow(p_hwfn, vf, &params)) {
2708 status = PFVF_STATUS_FAILURE;
2709 goto out;
2710 }
2711
2712 /* Determine if the unicast filtering is acceptible by PF */
Yuval Mintz1a635e42016-08-15 10:42:43 +03002713 if ((p_bulletin->valid_bitmap & BIT(VLAN_ADDR_FORCED)) &&
Yuval Mintz08feecd2016-05-11 16:36:20 +03002714 (params.type == QED_FILTER_VLAN ||
2715 params.type == QED_FILTER_MAC_VLAN)) {
2716 /* Once VLAN is forced or PVID is set, do not allow
2717 * to add/replace any further VLANs.
2718 */
2719 if (params.opcode == QED_FILTER_ADD ||
2720 params.opcode == QED_FILTER_REPLACE)
2721 status = PFVF_STATUS_FORCED;
2722 goto out;
2723 }
2724
Yuval Mintz1a635e42016-08-15 10:42:43 +03002725 if ((p_bulletin->valid_bitmap & BIT(MAC_ADDR_FORCED)) &&
Yuval Mintzeff16962016-05-11 16:36:21 +03002726 (params.type == QED_FILTER_MAC ||
2727 params.type == QED_FILTER_MAC_VLAN)) {
2728 if (!ether_addr_equal(p_bulletin->mac, params.mac) ||
2729 (params.opcode != QED_FILTER_ADD &&
2730 params.opcode != QED_FILTER_REPLACE))
2731 status = PFVF_STATUS_FORCED;
2732 goto out;
2733 }
2734
Yuval Mintzdacd88d2016-05-11 16:36:16 +03002735 rc = qed_iov_chk_ucast(p_hwfn, vf->relative_vf_id, &params);
2736 if (rc) {
2737 status = PFVF_STATUS_FAILURE;
2738 goto out;
2739 }
2740
2741 rc = qed_sp_eth_filter_ucast(p_hwfn, vf->opaque_fid, &params,
2742 QED_SPQ_MODE_CB, NULL);
2743 if (rc)
2744 status = PFVF_STATUS_FAILURE;
2745
2746out:
2747 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_UCAST_FILTER,
2748 sizeof(struct pfvf_def_resp_tlv), status);
2749}
2750
Yuval Mintz0b55e272016-05-11 16:36:15 +03002751static void qed_iov_vf_mbx_int_cleanup(struct qed_hwfn *p_hwfn,
2752 struct qed_ptt *p_ptt,
2753 struct qed_vf_info *vf)
2754{
2755 int i;
2756
2757 /* Reset the SBs */
2758 for (i = 0; i < vf->num_sbs; i++)
2759 qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2760 vf->igu_sbs[i],
2761 vf->opaque_fid, false);
2762
2763 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_INT_CLEANUP,
2764 sizeof(struct pfvf_def_resp_tlv),
2765 PFVF_STATUS_SUCCESS);
2766}
2767
2768static void qed_iov_vf_mbx_close(struct qed_hwfn *p_hwfn,
2769 struct qed_ptt *p_ptt, struct qed_vf_info *vf)
2770{
2771 u16 length = sizeof(struct pfvf_def_resp_tlv);
2772 u8 status = PFVF_STATUS_SUCCESS;
2773
2774 /* Disable Interrupts for VF */
2775 qed_iov_vf_igu_set_int(p_hwfn, p_ptt, vf, 0);
2776
2777 /* Reset Permission table */
2778 qed_iov_config_perm_table(p_hwfn, p_ptt, vf, 0);
2779
2780 qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_CLOSE,
2781 length, status);
2782}
2783
2784static void qed_iov_vf_mbx_release(struct qed_hwfn *p_hwfn,
2785 struct qed_ptt *p_ptt,
2786 struct qed_vf_info *p_vf)
2787{
2788 u16 length = sizeof(struct pfvf_def_resp_tlv);
Yuval Mintz1fe614d2016-06-05 13:11:11 +03002789 u8 status = PFVF_STATUS_SUCCESS;
2790 int rc = 0;
Yuval Mintz0b55e272016-05-11 16:36:15 +03002791
2792 qed_iov_vf_cleanup(p_hwfn, p_vf);
2793
Yuval Mintz1fe614d2016-06-05 13:11:11 +03002794 if (p_vf->state != VF_STOPPED && p_vf->state != VF_FREE) {
2795 /* Stopping the VF */
2796 rc = qed_sp_vf_stop(p_hwfn, p_vf->concrete_fid,
2797 p_vf->opaque_fid);
2798
2799 if (rc) {
2800 DP_ERR(p_hwfn, "qed_sp_vf_stop returned error %d\n",
2801 rc);
2802 status = PFVF_STATUS_FAILURE;
2803 }
2804
2805 p_vf->state = VF_STOPPED;
2806 }
2807
Yuval Mintz0b55e272016-05-11 16:36:15 +03002808 qed_iov_prepare_resp(p_hwfn, p_ptt, p_vf, CHANNEL_TLV_RELEASE,
Yuval Mintz1fe614d2016-06-05 13:11:11 +03002809 length, status);
Yuval Mintz0b55e272016-05-11 16:36:15 +03002810}
2811
2812static int
2813qed_iov_vf_flr_poll_dorq(struct qed_hwfn *p_hwfn,
2814 struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
2815{
2816 int cnt;
2817 u32 val;
2818
2819 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_vf->concrete_fid);
2820
2821 for (cnt = 0; cnt < 50; cnt++) {
2822 val = qed_rd(p_hwfn, p_ptt, DORQ_REG_VF_USAGE_CNT);
2823 if (!val)
2824 break;
2825 msleep(20);
2826 }
2827 qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
2828
2829 if (cnt == 50) {
2830 DP_ERR(p_hwfn,
2831 "VF[%d] - dorq failed to cleanup [usage 0x%08x]\n",
2832 p_vf->abs_vf_id, val);
2833 return -EBUSY;
2834 }
2835
2836 return 0;
2837}
2838
2839static int
2840qed_iov_vf_flr_poll_pbf(struct qed_hwfn *p_hwfn,
2841 struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
2842{
2843 u32 cons[MAX_NUM_VOQS], distance[MAX_NUM_VOQS];
2844 int i, cnt;
2845
2846 /* Read initial consumers & producers */
2847 for (i = 0; i < MAX_NUM_VOQS; i++) {
2848 u32 prod;
2849
2850 cons[i] = qed_rd(p_hwfn, p_ptt,
2851 PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 +
2852 i * 0x40);
2853 prod = qed_rd(p_hwfn, p_ptt,
2854 PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 +
2855 i * 0x40);
2856 distance[i] = prod - cons[i];
2857 }
2858
2859 /* Wait for consumers to pass the producers */
2860 i = 0;
2861 for (cnt = 0; cnt < 50; cnt++) {
2862 for (; i < MAX_NUM_VOQS; i++) {
2863 u32 tmp;
2864
2865 tmp = qed_rd(p_hwfn, p_ptt,
2866 PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 +
2867 i * 0x40);
2868 if (distance[i] > tmp - cons[i])
2869 break;
2870 }
2871
2872 if (i == MAX_NUM_VOQS)
2873 break;
2874
2875 msleep(20);
2876 }
2877
2878 if (cnt == 50) {
2879 DP_ERR(p_hwfn, "VF[%d] - pbf polling failed on VOQ %d\n",
2880 p_vf->abs_vf_id, i);
2881 return -EBUSY;
2882 }
2883
2884 return 0;
2885}
2886
2887static int qed_iov_vf_flr_poll(struct qed_hwfn *p_hwfn,
2888 struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
2889{
2890 int rc;
2891
2892 rc = qed_iov_vf_flr_poll_dorq(p_hwfn, p_vf, p_ptt);
2893 if (rc)
2894 return rc;
2895
2896 rc = qed_iov_vf_flr_poll_pbf(p_hwfn, p_vf, p_ptt);
2897 if (rc)
2898 return rc;
2899
2900 return 0;
2901}
2902
2903static int
2904qed_iov_execute_vf_flr_cleanup(struct qed_hwfn *p_hwfn,
2905 struct qed_ptt *p_ptt,
2906 u16 rel_vf_id, u32 *ack_vfs)
2907{
2908 struct qed_vf_info *p_vf;
2909 int rc = 0;
2910
2911 p_vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, false);
2912 if (!p_vf)
2913 return 0;
2914
2915 if (p_hwfn->pf_iov_info->pending_flr[rel_vf_id / 64] &
2916 (1ULL << (rel_vf_id % 64))) {
2917 u16 vfid = p_vf->abs_vf_id;
2918
2919 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2920 "VF[%d] - Handling FLR\n", vfid);
2921
2922 qed_iov_vf_cleanup(p_hwfn, p_vf);
2923
2924 /* If VF isn't active, no need for anything but SW */
2925 if (!p_vf->b_init)
2926 goto cleanup;
2927
2928 rc = qed_iov_vf_flr_poll(p_hwfn, p_vf, p_ptt);
2929 if (rc)
2930 goto cleanup;
2931
2932 rc = qed_final_cleanup(p_hwfn, p_ptt, vfid, true);
2933 if (rc) {
2934 DP_ERR(p_hwfn, "Failed handle FLR of VF[%d]\n", vfid);
2935 return rc;
2936 }
2937
Yuval Mintz7eff82b2016-10-14 05:19:22 -04002938 /* Workaround to make VF-PF channel ready, as FW
2939 * doesn't do that as a part of FLR.
2940 */
2941 REG_WR(p_hwfn,
2942 GTT_BAR0_MAP_REG_USDM_RAM +
2943 USTORM_VF_PF_CHANNEL_READY_OFFSET(vfid), 1);
2944
Yuval Mintz0b55e272016-05-11 16:36:15 +03002945 /* VF_STOPPED has to be set only after final cleanup
2946 * but prior to re-enabling the VF.
2947 */
2948 p_vf->state = VF_STOPPED;
2949
2950 rc = qed_iov_enable_vf_access(p_hwfn, p_ptt, p_vf);
2951 if (rc) {
2952 DP_ERR(p_hwfn, "Failed to re-enable VF[%d] acces\n",
2953 vfid);
2954 return rc;
2955 }
2956cleanup:
2957 /* Mark VF for ack and clean pending state */
2958 if (p_vf->state == VF_RESET)
2959 p_vf->state = VF_STOPPED;
Yuval Mintz1a635e42016-08-15 10:42:43 +03002960 ack_vfs[vfid / 32] |= BIT((vfid % 32));
Yuval Mintz0b55e272016-05-11 16:36:15 +03002961 p_hwfn->pf_iov_info->pending_flr[rel_vf_id / 64] &=
2962 ~(1ULL << (rel_vf_id % 64));
2963 p_hwfn->pf_iov_info->pending_events[rel_vf_id / 64] &=
2964 ~(1ULL << (rel_vf_id % 64));
2965 }
2966
2967 return rc;
2968}
2969
Baoyou Xieba569472016-09-09 09:21:15 +08002970static int
2971qed_iov_vf_flr_cleanup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
Yuval Mintz0b55e272016-05-11 16:36:15 +03002972{
2973 u32 ack_vfs[VF_MAX_STATIC / 32];
2974 int rc = 0;
2975 u16 i;
2976
2977 memset(ack_vfs, 0, sizeof(u32) * (VF_MAX_STATIC / 32));
2978
2979 /* Since BRB <-> PRS interface can't be tested as part of the flr
2980 * polling due to HW limitations, simply sleep a bit. And since
2981 * there's no need to wait per-vf, do it before looping.
2982 */
2983 msleep(100);
2984
2985 for (i = 0; i < p_hwfn->cdev->p_iov_info->total_vfs; i++)
2986 qed_iov_execute_vf_flr_cleanup(p_hwfn, p_ptt, i, ack_vfs);
2987
2988 rc = qed_mcp_ack_vf_flr(p_hwfn, p_ptt, ack_vfs);
2989 return rc;
2990}
2991
2992int qed_iov_mark_vf_flr(struct qed_hwfn *p_hwfn, u32 *p_disabled_vfs)
2993{
2994 u16 i, found = 0;
2995
2996 DP_VERBOSE(p_hwfn, QED_MSG_IOV, "Marking FLR-ed VFs\n");
2997 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
2998 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2999 "[%08x,...,%08x]: %08x\n",
3000 i * 32, (i + 1) * 32 - 1, p_disabled_vfs[i]);
3001
3002 if (!p_hwfn->cdev->p_iov_info) {
3003 DP_NOTICE(p_hwfn, "VF flr but no IOV\n");
3004 return 0;
3005 }
3006
3007 /* Mark VFs */
3008 for (i = 0; i < p_hwfn->cdev->p_iov_info->total_vfs; i++) {
3009 struct qed_vf_info *p_vf;
3010 u8 vfid;
3011
3012 p_vf = qed_iov_get_vf_info(p_hwfn, i, false);
3013 if (!p_vf)
3014 continue;
3015
3016 vfid = p_vf->abs_vf_id;
Yuval Mintz1a635e42016-08-15 10:42:43 +03003017 if (BIT((vfid % 32)) & p_disabled_vfs[vfid / 32]) {
Yuval Mintz0b55e272016-05-11 16:36:15 +03003018 u64 *p_flr = p_hwfn->pf_iov_info->pending_flr;
3019 u16 rel_vf_id = p_vf->relative_vf_id;
3020
3021 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3022 "VF[%d] [rel %d] got FLR-ed\n",
3023 vfid, rel_vf_id);
3024
3025 p_vf->state = VF_RESET;
3026
3027 /* No need to lock here, since pending_flr should
3028 * only change here and before ACKing MFw. Since
3029 * MFW will not trigger an additional attention for
3030 * VF flr until ACKs, we're safe.
3031 */
3032 p_flr[rel_vf_id / 64] |= 1ULL << (rel_vf_id % 64);
3033 found = 1;
3034 }
3035 }
3036
3037 return found;
3038}
3039
Yuval Mintz73390ac2016-05-11 16:36:24 +03003040static void qed_iov_get_link(struct qed_hwfn *p_hwfn,
3041 u16 vfid,
3042 struct qed_mcp_link_params *p_params,
3043 struct qed_mcp_link_state *p_link,
3044 struct qed_mcp_link_capabilities *p_caps)
3045{
3046 struct qed_vf_info *p_vf = qed_iov_get_vf_info(p_hwfn,
3047 vfid,
3048 false);
3049 struct qed_bulletin_content *p_bulletin;
3050
3051 if (!p_vf)
3052 return;
3053
3054 p_bulletin = p_vf->bulletin.p_virt;
3055
3056 if (p_params)
3057 __qed_vf_get_link_params(p_hwfn, p_params, p_bulletin);
3058 if (p_link)
3059 __qed_vf_get_link_state(p_hwfn, p_link, p_bulletin);
3060 if (p_caps)
3061 __qed_vf_get_link_caps(p_hwfn, p_caps, p_bulletin);
3062}
3063
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003064static void qed_iov_process_mbx_req(struct qed_hwfn *p_hwfn,
3065 struct qed_ptt *p_ptt, int vfid)
3066{
3067 struct qed_iov_vf_mbx *mbx;
3068 struct qed_vf_info *p_vf;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003069
3070 p_vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3071 if (!p_vf)
3072 return;
3073
3074 mbx = &p_vf->vf_mbx;
3075
3076 /* qed_iov_process_mbx_request */
Yuval Mintz54fdd802016-06-05 13:11:16 +03003077 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3078 "VF[%02x]: Processing mailbox message\n", p_vf->abs_vf_id);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003079
3080 mbx->first_tlv = mbx->req_virt->first_tlv;
3081
3082 /* check if tlv type is known */
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003083 if (qed_iov_tlv_supported(mbx->first_tlv.tl.type) &&
3084 !p_vf->b_malicious) {
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003085 switch (mbx->first_tlv.tl.type) {
3086 case CHANNEL_TLV_ACQUIRE:
3087 qed_iov_vf_mbx_acquire(p_hwfn, p_ptt, p_vf);
3088 break;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03003089 case CHANNEL_TLV_VPORT_START:
3090 qed_iov_vf_mbx_start_vport(p_hwfn, p_ptt, p_vf);
3091 break;
3092 case CHANNEL_TLV_VPORT_TEARDOWN:
3093 qed_iov_vf_mbx_stop_vport(p_hwfn, p_ptt, p_vf);
3094 break;
3095 case CHANNEL_TLV_START_RXQ:
3096 qed_iov_vf_mbx_start_rxq(p_hwfn, p_ptt, p_vf);
3097 break;
3098 case CHANNEL_TLV_START_TXQ:
3099 qed_iov_vf_mbx_start_txq(p_hwfn, p_ptt, p_vf);
3100 break;
3101 case CHANNEL_TLV_STOP_RXQS:
3102 qed_iov_vf_mbx_stop_rxqs(p_hwfn, p_ptt, p_vf);
3103 break;
3104 case CHANNEL_TLV_STOP_TXQS:
3105 qed_iov_vf_mbx_stop_txqs(p_hwfn, p_ptt, p_vf);
3106 break;
Yuval Mintz17b235c2016-05-11 16:36:18 +03003107 case CHANNEL_TLV_UPDATE_RXQ:
3108 qed_iov_vf_mbx_update_rxqs(p_hwfn, p_ptt, p_vf);
3109 break;
Yuval Mintzdacd88d2016-05-11 16:36:16 +03003110 case CHANNEL_TLV_VPORT_UPDATE:
3111 qed_iov_vf_mbx_vport_update(p_hwfn, p_ptt, p_vf);
3112 break;
3113 case CHANNEL_TLV_UCAST_FILTER:
3114 qed_iov_vf_mbx_ucast_filter(p_hwfn, p_ptt, p_vf);
3115 break;
Yuval Mintz0b55e272016-05-11 16:36:15 +03003116 case CHANNEL_TLV_CLOSE:
3117 qed_iov_vf_mbx_close(p_hwfn, p_ptt, p_vf);
3118 break;
3119 case CHANNEL_TLV_INT_CLEANUP:
3120 qed_iov_vf_mbx_int_cleanup(p_hwfn, p_ptt, p_vf);
3121 break;
3122 case CHANNEL_TLV_RELEASE:
3123 qed_iov_vf_mbx_release(p_hwfn, p_ptt, p_vf);
3124 break;
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003125 }
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003126 } else if (qed_iov_tlv_supported(mbx->first_tlv.tl.type)) {
3127 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3128 "VF [%02x] - considered malicious; Ignoring TLV [%04x]\n",
3129 p_vf->abs_vf_id, mbx->first_tlv.tl.type);
3130
3131 qed_iov_prepare_resp(p_hwfn, p_ptt, p_vf,
3132 mbx->first_tlv.tl.type,
3133 sizeof(struct pfvf_def_resp_tlv),
3134 PFVF_STATUS_MALICIOUS);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003135 } else {
3136 /* unknown TLV - this may belong to a VF driver from the future
3137 * - a version written after this PF driver was written, which
3138 * supports features unknown as of yet. Too bad since we don't
3139 * support them. Or this may be because someone wrote a crappy
3140 * VF driver and is sending garbage over the channel.
3141 */
Yuval Mintz54fdd802016-06-05 13:11:16 +03003142 DP_NOTICE(p_hwfn,
3143 "VF[%02x]: unknown TLV. type %04x length %04x padding %08x reply address %llu\n",
3144 p_vf->abs_vf_id,
3145 mbx->first_tlv.tl.type,
3146 mbx->first_tlv.tl.length,
3147 mbx->first_tlv.padding, mbx->first_tlv.reply_address);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003148
Yuval Mintz54fdd802016-06-05 13:11:16 +03003149 /* Try replying in case reply address matches the acquisition's
3150 * posted address.
3151 */
3152 if (p_vf->acquire.first_tlv.reply_address &&
3153 (mbx->first_tlv.reply_address ==
3154 p_vf->acquire.first_tlv.reply_address)) {
3155 qed_iov_prepare_resp(p_hwfn, p_ptt, p_vf,
3156 mbx->first_tlv.tl.type,
3157 sizeof(struct pfvf_def_resp_tlv),
3158 PFVF_STATUS_NOT_SUPPORTED);
3159 } else {
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003160 DP_VERBOSE(p_hwfn,
3161 QED_MSG_IOV,
Yuval Mintz54fdd802016-06-05 13:11:16 +03003162 "VF[%02x]: Can't respond to TLV - no valid reply address\n",
3163 p_vf->abs_vf_id);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003164 }
3165 }
3166}
3167
Baoyou Xieba569472016-09-09 09:21:15 +08003168static void qed_iov_pf_add_pending_events(struct qed_hwfn *p_hwfn, u8 vfid)
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003169{
3170 u64 add_bit = 1ULL << (vfid % 64);
3171
3172 p_hwfn->pf_iov_info->pending_events[vfid / 64] |= add_bit;
3173}
3174
3175static void qed_iov_pf_get_and_clear_pending_events(struct qed_hwfn *p_hwfn,
3176 u64 *events)
3177{
3178 u64 *p_pending_events = p_hwfn->pf_iov_info->pending_events;
3179
3180 memcpy(events, p_pending_events, sizeof(u64) * QED_VF_ARRAY_LENGTH);
3181 memset(p_pending_events, 0, sizeof(u64) * QED_VF_ARRAY_LENGTH);
3182}
3183
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003184static struct qed_vf_info *qed_sriov_get_vf_from_absid(struct qed_hwfn *p_hwfn,
3185 u16 abs_vfid)
3186{
3187 u8 min = (u8) p_hwfn->cdev->p_iov_info->first_vf_in_pf;
3188
3189 if (!_qed_iov_pf_sanity_check(p_hwfn, (int)abs_vfid - min, false)) {
3190 DP_VERBOSE(p_hwfn,
3191 QED_MSG_IOV,
3192 "Got indication for VF [abs 0x%08x] that cannot be handled by PF\n",
3193 abs_vfid);
3194 return NULL;
3195 }
3196
3197 return &p_hwfn->pf_iov_info->vfs_array[(u8) abs_vfid - min];
3198}
3199
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003200static int qed_sriov_vfpf_msg(struct qed_hwfn *p_hwfn,
3201 u16 abs_vfid, struct regpair *vf_msg)
3202{
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003203 struct qed_vf_info *p_vf = qed_sriov_get_vf_from_absid(p_hwfn,
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003204 abs_vfid);
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003205
3206 if (!p_vf)
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003207 return 0;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003208
3209 /* List the physical address of the request so that handler
3210 * could later on copy the message from it.
3211 */
3212 p_vf->vf_mbx.pending_req = (((u64)vf_msg->hi) << 32) | vf_msg->lo;
3213
3214 /* Mark the event and schedule the workqueue */
3215 qed_iov_pf_add_pending_events(p_hwfn, p_vf->relative_vf_id);
3216 qed_schedule_iov(p_hwfn, QED_IOV_WQ_MSG_FLAG);
3217
3218 return 0;
3219}
3220
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003221static void qed_sriov_vfpf_malicious(struct qed_hwfn *p_hwfn,
3222 struct malicious_vf_eqe_data *p_data)
3223{
3224 struct qed_vf_info *p_vf;
3225
3226 p_vf = qed_sriov_get_vf_from_absid(p_hwfn, p_data->vf_id);
3227
3228 if (!p_vf)
3229 return;
3230
3231 DP_INFO(p_hwfn,
3232 "VF [%d] - Malicious behavior [%02x]\n",
3233 p_vf->abs_vf_id, p_data->err_id);
3234
3235 p_vf->b_malicious = true;
3236}
3237
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003238int qed_sriov_eqe_event(struct qed_hwfn *p_hwfn,
3239 u8 opcode, __le16 echo, union event_ring_data *data)
3240{
3241 switch (opcode) {
3242 case COMMON_EVENT_VF_PF_CHANNEL:
3243 return qed_sriov_vfpf_msg(p_hwfn, le16_to_cpu(echo),
3244 &data->vf_pf_channel.msg_addr);
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003245 case COMMON_EVENT_MALICIOUS_VF:
3246 qed_sriov_vfpf_malicious(p_hwfn, &data->malicious_vf);
3247 return 0;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003248 default:
3249 DP_INFO(p_hwfn->cdev, "Unknown sriov eqe event 0x%02x\n",
3250 opcode);
3251 return -EINVAL;
3252 }
3253}
3254
Yuval Mintz32a47e72016-05-11 16:36:12 +03003255u16 qed_iov_get_next_active_vf(struct qed_hwfn *p_hwfn, u16 rel_vf_id)
3256{
3257 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
3258 u16 i;
3259
3260 if (!p_iov)
3261 goto out;
3262
3263 for (i = rel_vf_id; i < p_iov->total_vfs; i++)
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003264 if (qed_iov_is_valid_vfid(p_hwfn, rel_vf_id, true, false))
Yuval Mintz32a47e72016-05-11 16:36:12 +03003265 return i;
3266
3267out:
3268 return MAX_NUM_VFS;
3269}
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003270
3271static int qed_iov_copy_vf_msg(struct qed_hwfn *p_hwfn, struct qed_ptt *ptt,
3272 int vfid)
3273{
3274 struct qed_dmae_params params;
3275 struct qed_vf_info *vf_info;
3276
3277 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3278 if (!vf_info)
3279 return -EINVAL;
3280
3281 memset(&params, 0, sizeof(struct qed_dmae_params));
3282 params.flags = QED_DMAE_FLAG_VF_SRC | QED_DMAE_FLAG_COMPLETION_DST;
3283 params.src_vfid = vf_info->abs_vf_id;
3284
3285 if (qed_dmae_host2host(p_hwfn, ptt,
3286 vf_info->vf_mbx.pending_req,
3287 vf_info->vf_mbx.req_phys,
3288 sizeof(union vfpf_tlvs) / 4, &params)) {
3289 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
3290 "Failed to copy message from VF 0x%02x\n", vfid);
3291
3292 return -EIO;
3293 }
3294
3295 return 0;
3296}
3297
Yuval Mintzeff16962016-05-11 16:36:21 +03003298static void qed_iov_bulletin_set_forced_mac(struct qed_hwfn *p_hwfn,
3299 u8 *mac, int vfid)
3300{
3301 struct qed_vf_info *vf_info;
3302 u64 feature;
3303
3304 vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
3305 if (!vf_info) {
3306 DP_NOTICE(p_hwfn->cdev,
3307 "Can not set forced MAC, invalid vfid [%d]\n", vfid);
3308 return;
3309 }
3310
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003311 if (vf_info->b_malicious) {
3312 DP_NOTICE(p_hwfn->cdev,
3313 "Can't set forced MAC to malicious VF [%d]\n", vfid);
3314 return;
3315 }
3316
Yuval Mintzeff16962016-05-11 16:36:21 +03003317 feature = 1 << MAC_ADDR_FORCED;
3318 memcpy(vf_info->bulletin.p_virt->mac, mac, ETH_ALEN);
3319
3320 vf_info->bulletin.p_virt->valid_bitmap |= feature;
3321 /* Forced MAC will disable MAC_ADDR */
Yuval Mintz1a635e42016-08-15 10:42:43 +03003322 vf_info->bulletin.p_virt->valid_bitmap &= ~BIT(VFPF_BULLETIN_MAC_ADDR);
Yuval Mintzeff16962016-05-11 16:36:21 +03003323
3324 qed_iov_configure_vport_forced(p_hwfn, vf_info, feature);
3325}
3326
Baoyou Xieba569472016-09-09 09:21:15 +08003327static void qed_iov_bulletin_set_forced_vlan(struct qed_hwfn *p_hwfn,
3328 u16 pvid, int vfid)
Yuval Mintz08feecd2016-05-11 16:36:20 +03003329{
3330 struct qed_vf_info *vf_info;
3331 u64 feature;
3332
3333 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3334 if (!vf_info) {
3335 DP_NOTICE(p_hwfn->cdev,
3336 "Can not set forced MAC, invalid vfid [%d]\n", vfid);
3337 return;
3338 }
3339
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003340 if (vf_info->b_malicious) {
3341 DP_NOTICE(p_hwfn->cdev,
3342 "Can't set forced vlan to malicious VF [%d]\n", vfid);
3343 return;
3344 }
3345
Yuval Mintz08feecd2016-05-11 16:36:20 +03003346 feature = 1 << VLAN_ADDR_FORCED;
3347 vf_info->bulletin.p_virt->pvid = pvid;
3348 if (pvid)
3349 vf_info->bulletin.p_virt->valid_bitmap |= feature;
3350 else
3351 vf_info->bulletin.p_virt->valid_bitmap &= ~feature;
3352
3353 qed_iov_configure_vport_forced(p_hwfn, vf_info, feature);
3354}
3355
Yuval Mintz6ddc7602016-05-11 16:36:23 +03003356static bool qed_iov_vf_has_vport_instance(struct qed_hwfn *p_hwfn, int vfid)
3357{
3358 struct qed_vf_info *p_vf_info;
3359
3360 p_vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3361 if (!p_vf_info)
3362 return false;
3363
3364 return !!p_vf_info->vport_instance;
3365}
3366
Baoyou Xieba569472016-09-09 09:21:15 +08003367static bool qed_iov_is_vf_stopped(struct qed_hwfn *p_hwfn, int vfid)
Yuval Mintz0b55e272016-05-11 16:36:15 +03003368{
3369 struct qed_vf_info *p_vf_info;
3370
3371 p_vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3372 if (!p_vf_info)
3373 return true;
3374
3375 return p_vf_info->state == VF_STOPPED;
3376}
3377
Yuval Mintz73390ac2016-05-11 16:36:24 +03003378static bool qed_iov_spoofchk_get(struct qed_hwfn *p_hwfn, int vfid)
3379{
3380 struct qed_vf_info *vf_info;
3381
3382 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3383 if (!vf_info)
3384 return false;
3385
3386 return vf_info->spoof_chk;
3387}
3388
Baoyou Xieba569472016-09-09 09:21:15 +08003389static int qed_iov_spoofchk_set(struct qed_hwfn *p_hwfn, int vfid, bool val)
Yuval Mintz6ddc7602016-05-11 16:36:23 +03003390{
3391 struct qed_vf_info *vf;
3392 int rc = -EINVAL;
3393
3394 if (!qed_iov_pf_sanity_check(p_hwfn, vfid)) {
3395 DP_NOTICE(p_hwfn,
3396 "SR-IOV sanity check failed, can't set spoofchk\n");
3397 goto out;
3398 }
3399
3400 vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3401 if (!vf)
3402 goto out;
3403
3404 if (!qed_iov_vf_has_vport_instance(p_hwfn, vfid)) {
3405 /* After VF VPORT start PF will configure spoof check */
3406 vf->req_spoofchk_val = val;
3407 rc = 0;
3408 goto out;
3409 }
3410
3411 rc = __qed_iov_spoofchk_set(p_hwfn, vf, val);
3412
3413out:
3414 return rc;
3415}
3416
Yuval Mintzeff16962016-05-11 16:36:21 +03003417static u8 *qed_iov_bulletin_get_forced_mac(struct qed_hwfn *p_hwfn,
3418 u16 rel_vf_id)
3419{
3420 struct qed_vf_info *p_vf;
3421
3422 p_vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
3423 if (!p_vf || !p_vf->bulletin.p_virt)
3424 return NULL;
3425
Yuval Mintz1a635e42016-08-15 10:42:43 +03003426 if (!(p_vf->bulletin.p_virt->valid_bitmap & BIT(MAC_ADDR_FORCED)))
Yuval Mintzeff16962016-05-11 16:36:21 +03003427 return NULL;
3428
3429 return p_vf->bulletin.p_virt->mac;
3430}
3431
Baoyou Xieba569472016-09-09 09:21:15 +08003432static u16
3433qed_iov_bulletin_get_forced_vlan(struct qed_hwfn *p_hwfn, u16 rel_vf_id)
Yuval Mintz08feecd2016-05-11 16:36:20 +03003434{
3435 struct qed_vf_info *p_vf;
3436
3437 p_vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
3438 if (!p_vf || !p_vf->bulletin.p_virt)
3439 return 0;
3440
Yuval Mintz1a635e42016-08-15 10:42:43 +03003441 if (!(p_vf->bulletin.p_virt->valid_bitmap & BIT(VLAN_ADDR_FORCED)))
Yuval Mintz08feecd2016-05-11 16:36:20 +03003442 return 0;
3443
3444 return p_vf->bulletin.p_virt->pvid;
3445}
3446
Yuval Mintz733def62016-05-11 16:36:22 +03003447static int qed_iov_configure_tx_rate(struct qed_hwfn *p_hwfn,
3448 struct qed_ptt *p_ptt, int vfid, int val)
3449{
3450 struct qed_vf_info *vf;
3451 u8 abs_vp_id = 0;
3452 int rc;
3453
3454 vf = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
3455 if (!vf)
3456 return -EINVAL;
3457
3458 rc = qed_fw_vport(p_hwfn, vf->vport_id, &abs_vp_id);
3459 if (rc)
3460 return rc;
3461
3462 return qed_init_vport_rl(p_hwfn, p_ptt, abs_vp_id, (u32)val);
3463}
3464
Baoyou Xieba569472016-09-09 09:21:15 +08003465static int
3466qed_iov_configure_min_tx_rate(struct qed_dev *cdev, int vfid, u32 rate)
Yuval Mintz733def62016-05-11 16:36:22 +03003467{
3468 struct qed_vf_info *vf;
3469 u8 vport_id;
3470 int i;
3471
3472 for_each_hwfn(cdev, i) {
3473 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3474
3475 if (!qed_iov_pf_sanity_check(p_hwfn, vfid)) {
3476 DP_NOTICE(p_hwfn,
3477 "SR-IOV sanity check failed, can't set min rate\n");
3478 return -EINVAL;
3479 }
3480 }
3481
3482 vf = qed_iov_get_vf_info(QED_LEADING_HWFN(cdev), (u16)vfid, true);
3483 vport_id = vf->vport_id;
3484
3485 return qed_configure_vport_wfq(cdev, vport_id, rate);
3486}
3487
Yuval Mintz73390ac2016-05-11 16:36:24 +03003488static int qed_iov_get_vf_min_rate(struct qed_hwfn *p_hwfn, int vfid)
3489{
3490 struct qed_wfq_data *vf_vp_wfq;
3491 struct qed_vf_info *vf_info;
3492
3493 vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
3494 if (!vf_info)
3495 return 0;
3496
3497 vf_vp_wfq = &p_hwfn->qm_info.wfq_data[vf_info->vport_id];
3498
3499 if (vf_vp_wfq->configured)
3500 return vf_vp_wfq->min_speed;
3501 else
3502 return 0;
3503}
3504
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003505/**
3506 * qed_schedule_iov - schedules IOV task for VF and PF
3507 * @hwfn: hardware function pointer
3508 * @flag: IOV flag for VF/PF
3509 */
3510void qed_schedule_iov(struct qed_hwfn *hwfn, enum qed_iov_wq_flag flag)
3511{
3512 smp_mb__before_atomic();
3513 set_bit(flag, &hwfn->iov_task_flags);
3514 smp_mb__after_atomic();
3515 DP_VERBOSE(hwfn, QED_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag);
3516 queue_delayed_work(hwfn->iov_wq, &hwfn->iov_task, 0);
3517}
3518
Yuval Mintz1408cc1f2016-05-11 16:36:14 +03003519void qed_vf_start_iov_wq(struct qed_dev *cdev)
3520{
3521 int i;
3522
3523 for_each_hwfn(cdev, i)
3524 queue_delayed_work(cdev->hwfns[i].iov_wq,
3525 &cdev->hwfns[i].iov_task, 0);
3526}
3527
Yuval Mintz0b55e272016-05-11 16:36:15 +03003528int qed_sriov_disable(struct qed_dev *cdev, bool pci_enabled)
3529{
3530 int i, j;
3531
3532 for_each_hwfn(cdev, i)
3533 if (cdev->hwfns[i].iov_wq)
3534 flush_workqueue(cdev->hwfns[i].iov_wq);
3535
3536 /* Mark VFs for disablement */
3537 qed_iov_set_vfs_to_disable(cdev, true);
3538
3539 if (cdev->p_iov_info && cdev->p_iov_info->num_vfs && pci_enabled)
3540 pci_disable_sriov(cdev->pdev);
3541
3542 for_each_hwfn(cdev, i) {
3543 struct qed_hwfn *hwfn = &cdev->hwfns[i];
3544 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
3545
3546 /* Failure to acquire the ptt in 100g creates an odd error
3547 * where the first engine has already relased IOV.
3548 */
3549 if (!ptt) {
3550 DP_ERR(hwfn, "Failed to acquire ptt\n");
3551 return -EBUSY;
3552 }
3553
Yuval Mintz733def62016-05-11 16:36:22 +03003554 /* Clean WFQ db and configure equal weight for all vports */
3555 qed_clean_wfq_db(hwfn, ptt);
3556
Yuval Mintz0b55e272016-05-11 16:36:15 +03003557 qed_for_each_vf(hwfn, j) {
3558 int k;
3559
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003560 if (!qed_iov_is_valid_vfid(hwfn, j, true, false))
Yuval Mintz0b55e272016-05-11 16:36:15 +03003561 continue;
3562
3563 /* Wait until VF is disabled before releasing */
3564 for (k = 0; k < 100; k++) {
3565 if (!qed_iov_is_vf_stopped(hwfn, j))
3566 msleep(20);
3567 else
3568 break;
3569 }
3570
3571 if (k < 100)
3572 qed_iov_release_hw_for_vf(&cdev->hwfns[i],
3573 ptt, j);
3574 else
3575 DP_ERR(hwfn,
3576 "Timeout waiting for VF's FLR to end\n");
3577 }
3578
3579 qed_ptt_release(hwfn, ptt);
3580 }
3581
3582 qed_iov_set_vfs_to_disable(cdev, false);
3583
3584 return 0;
3585}
3586
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003587static void qed_sriov_enable_qid_config(struct qed_hwfn *hwfn,
3588 u16 vfid,
3589 struct qed_iov_vf_init_params *params)
3590{
3591 u16 base, i;
3592
3593 /* Since we have an equal resource distribution per-VF, and we assume
3594 * PF has acquired the QED_PF_L2_QUE first queues, we start setting
3595 * sequentially from there.
3596 */
3597 base = FEAT_NUM(hwfn, QED_PF_L2_QUE) + vfid * params->num_queues;
3598
3599 params->rel_vf_id = vfid;
3600 for (i = 0; i < params->num_queues; i++) {
3601 params->req_rx_queue[i] = base + i;
3602 params->req_tx_queue[i] = base + i;
3603 }
3604}
3605
Yuval Mintz0b55e272016-05-11 16:36:15 +03003606static int qed_sriov_enable(struct qed_dev *cdev, int num)
3607{
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003608 struct qed_iov_vf_init_params params;
Yuval Mintz0b55e272016-05-11 16:36:15 +03003609 int i, j, rc;
3610
3611 if (num >= RESC_NUM(&cdev->hwfns[0], QED_VPORT)) {
3612 DP_NOTICE(cdev, "Can start at most %d VFs\n",
3613 RESC_NUM(&cdev->hwfns[0], QED_VPORT) - 1);
3614 return -EINVAL;
3615 }
3616
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003617 memset(&params, 0, sizeof(params));
3618
Yuval Mintz0b55e272016-05-11 16:36:15 +03003619 /* Initialize HW for VF access */
3620 for_each_hwfn(cdev, j) {
3621 struct qed_hwfn *hwfn = &cdev->hwfns[j];
3622 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
Mintz, Yuval5a1f9652016-10-31 07:14:26 +02003623
3624 /* Make sure not to use more than 16 queues per VF */
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003625 params.num_queues = min_t(int,
3626 FEAT_NUM(hwfn, QED_VF_L2_QUE) / num,
3627 16);
Yuval Mintz0b55e272016-05-11 16:36:15 +03003628
3629 if (!ptt) {
3630 DP_ERR(hwfn, "Failed to acquire ptt\n");
3631 rc = -EBUSY;
3632 goto err;
3633 }
3634
Yuval Mintz0b55e272016-05-11 16:36:15 +03003635 for (i = 0; i < num; i++) {
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003636 if (!qed_iov_is_valid_vfid(hwfn, i, false, true))
Yuval Mintz0b55e272016-05-11 16:36:15 +03003637 continue;
3638
Mintz, Yuval3da7a372016-11-29 16:47:06 +02003639 qed_sriov_enable_qid_config(hwfn, i, &params);
3640 rc = qed_iov_init_hw_for_vf(hwfn, ptt, &params);
Yuval Mintz0b55e272016-05-11 16:36:15 +03003641 if (rc) {
3642 DP_ERR(cdev, "Failed to enable VF[%d]\n", i);
3643 qed_ptt_release(hwfn, ptt);
3644 goto err;
3645 }
3646 }
3647
3648 qed_ptt_release(hwfn, ptt);
3649 }
3650
3651 /* Enable SRIOV PCIe functions */
3652 rc = pci_enable_sriov(cdev->pdev, num);
3653 if (rc) {
3654 DP_ERR(cdev, "Failed to enable sriov [%d]\n", rc);
3655 goto err;
3656 }
3657
3658 return num;
3659
3660err:
3661 qed_sriov_disable(cdev, false);
3662 return rc;
3663}
3664
3665static int qed_sriov_configure(struct qed_dev *cdev, int num_vfs_param)
3666{
3667 if (!IS_QED_SRIOV(cdev)) {
3668 DP_VERBOSE(cdev, QED_MSG_IOV, "SR-IOV is not supported\n");
3669 return -EOPNOTSUPP;
3670 }
3671
3672 if (num_vfs_param)
3673 return qed_sriov_enable(cdev, num_vfs_param);
3674 else
3675 return qed_sriov_disable(cdev, true);
3676}
3677
Yuval Mintzeff16962016-05-11 16:36:21 +03003678static int qed_sriov_pf_set_mac(struct qed_dev *cdev, u8 *mac, int vfid)
3679{
3680 int i;
3681
3682 if (!IS_QED_SRIOV(cdev) || !IS_PF_SRIOV_ALLOC(&cdev->hwfns[0])) {
3683 DP_VERBOSE(cdev, QED_MSG_IOV,
3684 "Cannot set a VF MAC; Sriov is not enabled\n");
3685 return -EINVAL;
3686 }
3687
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003688 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vfid, true, true)) {
Yuval Mintzeff16962016-05-11 16:36:21 +03003689 DP_VERBOSE(cdev, QED_MSG_IOV,
3690 "Cannot set VF[%d] MAC (VF is not active)\n", vfid);
3691 return -EINVAL;
3692 }
3693
3694 for_each_hwfn(cdev, i) {
3695 struct qed_hwfn *hwfn = &cdev->hwfns[i];
3696 struct qed_public_vf_info *vf_info;
3697
3698 vf_info = qed_iov_get_public_vf_info(hwfn, vfid, true);
3699 if (!vf_info)
3700 continue;
3701
3702 /* Set the forced MAC, and schedule the IOV task */
3703 ether_addr_copy(vf_info->forced_mac, mac);
3704 qed_schedule_iov(hwfn, QED_IOV_WQ_SET_UNICAST_FILTER_FLAG);
3705 }
3706
3707 return 0;
3708}
3709
Yuval Mintz08feecd2016-05-11 16:36:20 +03003710static int qed_sriov_pf_set_vlan(struct qed_dev *cdev, u16 vid, int vfid)
3711{
3712 int i;
3713
3714 if (!IS_QED_SRIOV(cdev) || !IS_PF_SRIOV_ALLOC(&cdev->hwfns[0])) {
3715 DP_VERBOSE(cdev, QED_MSG_IOV,
3716 "Cannot set a VF MAC; Sriov is not enabled\n");
3717 return -EINVAL;
3718 }
3719
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003720 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vfid, true, true)) {
Yuval Mintz08feecd2016-05-11 16:36:20 +03003721 DP_VERBOSE(cdev, QED_MSG_IOV,
3722 "Cannot set VF[%d] MAC (VF is not active)\n", vfid);
3723 return -EINVAL;
3724 }
3725
3726 for_each_hwfn(cdev, i) {
3727 struct qed_hwfn *hwfn = &cdev->hwfns[i];
3728 struct qed_public_vf_info *vf_info;
3729
3730 vf_info = qed_iov_get_public_vf_info(hwfn, vfid, true);
3731 if (!vf_info)
3732 continue;
3733
3734 /* Set the forced vlan, and schedule the IOV task */
3735 vf_info->forced_vlan = vid;
3736 qed_schedule_iov(hwfn, QED_IOV_WQ_SET_UNICAST_FILTER_FLAG);
3737 }
3738
3739 return 0;
3740}
3741
Yuval Mintz73390ac2016-05-11 16:36:24 +03003742static int qed_get_vf_config(struct qed_dev *cdev,
3743 int vf_id, struct ifla_vf_info *ivi)
3744{
3745 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
3746 struct qed_public_vf_info *vf_info;
3747 struct qed_mcp_link_state link;
3748 u32 tx_rate;
3749
3750 /* Sanitize request */
3751 if (IS_VF(cdev))
3752 return -EINVAL;
3753
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003754 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vf_id, true, false)) {
Yuval Mintz73390ac2016-05-11 16:36:24 +03003755 DP_VERBOSE(cdev, QED_MSG_IOV,
3756 "VF index [%d] isn't active\n", vf_id);
3757 return -EINVAL;
3758 }
3759
3760 vf_info = qed_iov_get_public_vf_info(hwfn, vf_id, true);
3761
3762 qed_iov_get_link(hwfn, vf_id, NULL, &link, NULL);
3763
3764 /* Fill information about VF */
3765 ivi->vf = vf_id;
3766
3767 if (is_valid_ether_addr(vf_info->forced_mac))
3768 ether_addr_copy(ivi->mac, vf_info->forced_mac);
3769 else
3770 ether_addr_copy(ivi->mac, vf_info->mac);
3771
3772 ivi->vlan = vf_info->forced_vlan;
3773 ivi->spoofchk = qed_iov_spoofchk_get(hwfn, vf_id);
3774 ivi->linkstate = vf_info->link_state;
3775 tx_rate = vf_info->tx_rate;
3776 ivi->max_tx_rate = tx_rate ? tx_rate : link.speed;
3777 ivi->min_tx_rate = qed_iov_get_vf_min_rate(hwfn, vf_id);
3778
3779 return 0;
3780}
3781
Yuval Mintz36558c32016-05-11 16:36:17 +03003782void qed_inform_vf_link_state(struct qed_hwfn *hwfn)
3783{
3784 struct qed_mcp_link_capabilities caps;
3785 struct qed_mcp_link_params params;
3786 struct qed_mcp_link_state link;
3787 int i;
3788
3789 if (!hwfn->pf_iov_info)
3790 return;
3791
3792 /* Update bulletin of all future possible VFs with link configuration */
3793 for (i = 0; i < hwfn->cdev->p_iov_info->total_vfs; i++) {
Yuval Mintz733def62016-05-11 16:36:22 +03003794 struct qed_public_vf_info *vf_info;
3795
3796 vf_info = qed_iov_get_public_vf_info(hwfn, i, false);
3797 if (!vf_info)
3798 continue;
3799
Yuval Mintz36558c32016-05-11 16:36:17 +03003800 memcpy(&params, qed_mcp_get_link_params(hwfn), sizeof(params));
3801 memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link));
3802 memcpy(&caps, qed_mcp_get_link_capabilities(hwfn),
3803 sizeof(caps));
3804
Yuval Mintz733def62016-05-11 16:36:22 +03003805 /* Modify link according to the VF's configured link state */
3806 switch (vf_info->link_state) {
3807 case IFLA_VF_LINK_STATE_DISABLE:
3808 link.link_up = false;
3809 break;
3810 case IFLA_VF_LINK_STATE_ENABLE:
3811 link.link_up = true;
3812 /* Set speed according to maximum supported by HW.
3813 * that is 40G for regular devices and 100G for CMT
3814 * mode devices.
3815 */
3816 link.speed = (hwfn->cdev->num_hwfns > 1) ?
3817 100000 : 40000;
3818 default:
3819 /* In auto mode pass PF link image to VF */
3820 break;
3821 }
3822
3823 if (link.link_up && vf_info->tx_rate) {
3824 struct qed_ptt *ptt;
3825 int rate;
3826
3827 rate = min_t(int, vf_info->tx_rate, link.speed);
3828
3829 ptt = qed_ptt_acquire(hwfn);
3830 if (!ptt) {
3831 DP_NOTICE(hwfn, "Failed to acquire PTT\n");
3832 return;
3833 }
3834
3835 if (!qed_iov_configure_tx_rate(hwfn, ptt, i, rate)) {
3836 vf_info->tx_rate = rate;
3837 link.speed = rate;
3838 }
3839
3840 qed_ptt_release(hwfn, ptt);
3841 }
3842
Yuval Mintz36558c32016-05-11 16:36:17 +03003843 qed_iov_set_link(hwfn, i, &params, &link, &caps);
3844 }
3845
3846 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
3847}
3848
Yuval Mintz733def62016-05-11 16:36:22 +03003849static int qed_set_vf_link_state(struct qed_dev *cdev,
3850 int vf_id, int link_state)
3851{
3852 int i;
3853
3854 /* Sanitize request */
3855 if (IS_VF(cdev))
3856 return -EINVAL;
3857
Yuval Mintz7eff82b2016-10-14 05:19:22 -04003858 if (!qed_iov_is_valid_vfid(&cdev->hwfns[0], vf_id, true, true)) {
Yuval Mintz733def62016-05-11 16:36:22 +03003859 DP_VERBOSE(cdev, QED_MSG_IOV,
3860 "VF index [%d] isn't active\n", vf_id);
3861 return -EINVAL;
3862 }
3863
3864 /* Handle configuration of link state */
3865 for_each_hwfn(cdev, i) {
3866 struct qed_hwfn *hwfn = &cdev->hwfns[i];
3867 struct qed_public_vf_info *vf;
3868
3869 vf = qed_iov_get_public_vf_info(hwfn, vf_id, true);
3870 if (!vf)
3871 continue;
3872
3873 if (vf->link_state == link_state)
3874 continue;
3875
3876 vf->link_state = link_state;
3877 qed_inform_vf_link_state(&cdev->hwfns[i]);
3878 }
3879
3880 return 0;
3881}
3882
Yuval Mintz6ddc7602016-05-11 16:36:23 +03003883static int qed_spoof_configure(struct qed_dev *cdev, int vfid, bool val)
3884{
3885 int i, rc = -EINVAL;
3886
3887 for_each_hwfn(cdev, i) {
3888 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3889
3890 rc = qed_iov_spoofchk_set(p_hwfn, vfid, val);
3891 if (rc)
3892 break;
3893 }
3894
3895 return rc;
3896}
3897
Yuval Mintz733def62016-05-11 16:36:22 +03003898static int qed_configure_max_vf_rate(struct qed_dev *cdev, int vfid, int rate)
3899{
3900 int i;
3901
3902 for_each_hwfn(cdev, i) {
3903 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3904 struct qed_public_vf_info *vf;
3905
3906 if (!qed_iov_pf_sanity_check(p_hwfn, vfid)) {
3907 DP_NOTICE(p_hwfn,
3908 "SR-IOV sanity check failed, can't set tx rate\n");
3909 return -EINVAL;
3910 }
3911
3912 vf = qed_iov_get_public_vf_info(p_hwfn, vfid, true);
3913
3914 vf->tx_rate = rate;
3915
3916 qed_inform_vf_link_state(p_hwfn);
3917 }
3918
3919 return 0;
3920}
3921
3922static int qed_set_vf_rate(struct qed_dev *cdev,
3923 int vfid, u32 min_rate, u32 max_rate)
3924{
3925 int rc_min = 0, rc_max = 0;
3926
3927 if (max_rate)
3928 rc_max = qed_configure_max_vf_rate(cdev, vfid, max_rate);
3929
3930 if (min_rate)
3931 rc_min = qed_iov_configure_min_tx_rate(cdev, vfid, min_rate);
3932
3933 if (rc_max | rc_min)
3934 return -EINVAL;
3935
3936 return 0;
3937}
3938
Yuval Mintz37bff2b2016-05-11 16:36:13 +03003939static void qed_handle_vf_msg(struct qed_hwfn *hwfn)
3940{
3941 u64 events[QED_VF_ARRAY_LENGTH];
3942 struct qed_ptt *ptt;
3943 int i;
3944
3945 ptt = qed_ptt_acquire(hwfn);
3946 if (!ptt) {
3947 DP_VERBOSE(hwfn, QED_MSG_IOV,
3948 "Can't acquire PTT; re-scheduling\n");
3949 qed_schedule_iov(hwfn, QED_IOV_WQ_MSG_FLAG);
3950 return;
3951 }
3952
3953 qed_iov_pf_get_and_clear_pending_events(hwfn, events);
3954
3955 DP_VERBOSE(hwfn, QED_MSG_IOV,
3956 "Event mask of VF events: 0x%llx 0x%llx 0x%llx\n",
3957 events[0], events[1], events[2]);
3958
3959 qed_for_each_vf(hwfn, i) {
3960 /* Skip VFs with no pending messages */
3961 if (!(events[i / 64] & (1ULL << (i % 64))))
3962 continue;
3963
3964 DP_VERBOSE(hwfn, QED_MSG_IOV,
3965 "Handling VF message from VF 0x%02x [Abs 0x%02x]\n",
3966 i, hwfn->cdev->p_iov_info->first_vf_in_pf + i);
3967
3968 /* Copy VF's message to PF's request buffer for that VF */
3969 if (qed_iov_copy_vf_msg(hwfn, ptt, i))
3970 continue;
3971
3972 qed_iov_process_mbx_req(hwfn, ptt, i);
3973 }
3974
3975 qed_ptt_release(hwfn, ptt);
3976}
3977
Yuval Mintz08feecd2016-05-11 16:36:20 +03003978static void qed_handle_pf_set_vf_unicast(struct qed_hwfn *hwfn)
3979{
3980 int i;
3981
3982 qed_for_each_vf(hwfn, i) {
3983 struct qed_public_vf_info *info;
3984 bool update = false;
Yuval Mintzeff16962016-05-11 16:36:21 +03003985 u8 *mac;
Yuval Mintz08feecd2016-05-11 16:36:20 +03003986
3987 info = qed_iov_get_public_vf_info(hwfn, i, true);
3988 if (!info)
3989 continue;
3990
3991 /* Update data on bulletin board */
Yuval Mintzeff16962016-05-11 16:36:21 +03003992 mac = qed_iov_bulletin_get_forced_mac(hwfn, i);
3993 if (is_valid_ether_addr(info->forced_mac) &&
3994 (!mac || !ether_addr_equal(mac, info->forced_mac))) {
3995 DP_VERBOSE(hwfn,
3996 QED_MSG_IOV,
3997 "Handling PF setting of VF MAC to VF 0x%02x [Abs 0x%02x]\n",
3998 i,
3999 hwfn->cdev->p_iov_info->first_vf_in_pf + i);
4000
4001 /* Update bulletin board with forced MAC */
4002 qed_iov_bulletin_set_forced_mac(hwfn,
4003 info->forced_mac, i);
4004 update = true;
4005 }
Yuval Mintz08feecd2016-05-11 16:36:20 +03004006
4007 if (qed_iov_bulletin_get_forced_vlan(hwfn, i) ^
4008 info->forced_vlan) {
4009 DP_VERBOSE(hwfn,
4010 QED_MSG_IOV,
4011 "Handling PF setting of pvid [0x%04x] to VF 0x%02x [Abs 0x%02x]\n",
4012 info->forced_vlan,
4013 i,
4014 hwfn->cdev->p_iov_info->first_vf_in_pf + i);
4015 qed_iov_bulletin_set_forced_vlan(hwfn,
4016 info->forced_vlan, i);
4017 update = true;
4018 }
4019
4020 if (update)
4021 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
4022 }
4023}
4024
Yuval Mintz36558c32016-05-11 16:36:17 +03004025static void qed_handle_bulletin_post(struct qed_hwfn *hwfn)
4026{
4027 struct qed_ptt *ptt;
4028 int i;
4029
4030 ptt = qed_ptt_acquire(hwfn);
4031 if (!ptt) {
4032 DP_NOTICE(hwfn, "Failed allocating a ptt entry\n");
4033 qed_schedule_iov(hwfn, QED_IOV_WQ_BULLETIN_UPDATE_FLAG);
4034 return;
4035 }
4036
4037 qed_for_each_vf(hwfn, i)
4038 qed_iov_post_vf_bulletin(hwfn, i, ptt);
4039
4040 qed_ptt_release(hwfn, ptt);
4041}
4042
Baoyou Xieba569472016-09-09 09:21:15 +08004043static void qed_iov_pf_task(struct work_struct *work)
4044
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004045{
4046 struct qed_hwfn *hwfn = container_of(work, struct qed_hwfn,
4047 iov_task.work);
Yuval Mintz0b55e272016-05-11 16:36:15 +03004048 int rc;
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004049
4050 if (test_and_clear_bit(QED_IOV_WQ_STOP_WQ_FLAG, &hwfn->iov_task_flags))
4051 return;
4052
Yuval Mintz0b55e272016-05-11 16:36:15 +03004053 if (test_and_clear_bit(QED_IOV_WQ_FLR_FLAG, &hwfn->iov_task_flags)) {
4054 struct qed_ptt *ptt = qed_ptt_acquire(hwfn);
4055
4056 if (!ptt) {
4057 qed_schedule_iov(hwfn, QED_IOV_WQ_FLR_FLAG);
4058 return;
4059 }
4060
4061 rc = qed_iov_vf_flr_cleanup(hwfn, ptt);
4062 if (rc)
4063 qed_schedule_iov(hwfn, QED_IOV_WQ_FLR_FLAG);
4064
4065 qed_ptt_release(hwfn, ptt);
4066 }
4067
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004068 if (test_and_clear_bit(QED_IOV_WQ_MSG_FLAG, &hwfn->iov_task_flags))
4069 qed_handle_vf_msg(hwfn);
Yuval Mintz08feecd2016-05-11 16:36:20 +03004070
4071 if (test_and_clear_bit(QED_IOV_WQ_SET_UNICAST_FILTER_FLAG,
4072 &hwfn->iov_task_flags))
4073 qed_handle_pf_set_vf_unicast(hwfn);
4074
Yuval Mintz36558c32016-05-11 16:36:17 +03004075 if (test_and_clear_bit(QED_IOV_WQ_BULLETIN_UPDATE_FLAG,
4076 &hwfn->iov_task_flags))
4077 qed_handle_bulletin_post(hwfn);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004078}
4079
4080void qed_iov_wq_stop(struct qed_dev *cdev, bool schedule_first)
4081{
4082 int i;
4083
4084 for_each_hwfn(cdev, i) {
4085 if (!cdev->hwfns[i].iov_wq)
4086 continue;
4087
4088 if (schedule_first) {
4089 qed_schedule_iov(&cdev->hwfns[i],
4090 QED_IOV_WQ_STOP_WQ_FLAG);
4091 cancel_delayed_work_sync(&cdev->hwfns[i].iov_task);
4092 }
4093
4094 flush_workqueue(cdev->hwfns[i].iov_wq);
4095 destroy_workqueue(cdev->hwfns[i].iov_wq);
4096 }
4097}
4098
4099int qed_iov_wq_start(struct qed_dev *cdev)
4100{
4101 char name[NAME_SIZE];
4102 int i;
4103
4104 for_each_hwfn(cdev, i) {
4105 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4106
Yuval Mintz36558c32016-05-11 16:36:17 +03004107 /* PFs needs a dedicated workqueue only if they support IOV.
4108 * VFs always require one.
4109 */
4110 if (IS_PF(p_hwfn->cdev) && !IS_PF_SRIOV(p_hwfn))
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004111 continue;
4112
4113 snprintf(name, NAME_SIZE, "iov-%02x:%02x.%02x",
4114 cdev->pdev->bus->number,
4115 PCI_SLOT(cdev->pdev->devfn), p_hwfn->abs_pf_id);
4116
4117 p_hwfn->iov_wq = create_singlethread_workqueue(name);
4118 if (!p_hwfn->iov_wq) {
4119 DP_NOTICE(p_hwfn, "Cannot create iov workqueue\n");
4120 return -ENOMEM;
4121 }
4122
Yuval Mintz36558c32016-05-11 16:36:17 +03004123 if (IS_PF(cdev))
4124 INIT_DELAYED_WORK(&p_hwfn->iov_task, qed_iov_pf_task);
4125 else
4126 INIT_DELAYED_WORK(&p_hwfn->iov_task, qed_iov_vf_task);
Yuval Mintz37bff2b2016-05-11 16:36:13 +03004127 }
4128
4129 return 0;
4130}
Yuval Mintz0b55e272016-05-11 16:36:15 +03004131
4132const struct qed_iov_hv_ops qed_iov_ops_pass = {
4133 .configure = &qed_sriov_configure,
Yuval Mintzeff16962016-05-11 16:36:21 +03004134 .set_mac = &qed_sriov_pf_set_mac,
Yuval Mintz08feecd2016-05-11 16:36:20 +03004135 .set_vlan = &qed_sriov_pf_set_vlan,
Yuval Mintz73390ac2016-05-11 16:36:24 +03004136 .get_config = &qed_get_vf_config,
Yuval Mintz733def62016-05-11 16:36:22 +03004137 .set_link_state = &qed_set_vf_link_state,
Yuval Mintz6ddc7602016-05-11 16:36:23 +03004138 .set_spoof = &qed_spoof_configure,
Yuval Mintz733def62016-05-11 16:36:22 +03004139 .set_rate = &qed_set_vf_rate,
Yuval Mintz0b55e272016-05-11 16:36:15 +03004140};