| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
| 10 | #include "am33xx.dtsi" |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 11 | #include <dt-bindings/pwm/pwm.h> |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 12 | |
| 13 | / { |
| 14 | model = "Toby Churchill SL50 Series"; |
| 15 | compatible = "tcl,am335x-sl50", "ti,am33xx"; |
| 16 | |
| 17 | cpus { |
| 18 | cpu@0 { |
| 19 | cpu0-supply = <&dcdc2_reg>; |
| 20 | }; |
| 21 | }; |
| 22 | |
| Javier Martinez Canillas | 278cb79 | 2016-08-31 12:35:30 +0200 | [diff] [blame] | 23 | memory@80000000 { |
| Javier Martinez Canillas | 35852c6 | 2016-08-31 12:35:15 +0200 | [diff] [blame] | 24 | device_type = "memory"; |
| 25 | reg = <0x80000000 0x20000000>; /* 512 MB */ |
| 26 | }; |
| 27 | |
| Enric Balletbo i Serra | 01c37be4 | 2016-01-16 11:51:12 +0100 | [diff] [blame] | 28 | chosen { |
| 29 | stdout-path = &uart0; |
| 30 | }; |
| 31 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 32 | leds { |
| 33 | compatible = "gpio-leds"; |
| 34 | pinctrl-names = "default"; |
| 35 | pinctrl-0 = <&led_pins>; |
| 36 | |
| Javier Martinez Canillas | c731abd | 2016-08-01 12:47:03 -0400 | [diff] [blame] | 37 | led0 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 38 | label = "sl50:green:usr0"; |
| 39 | gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; |
| 40 | default-state = "off"; |
| 41 | }; |
| 42 | |
| Javier Martinez Canillas | c731abd | 2016-08-01 12:47:03 -0400 | [diff] [blame] | 43 | led1 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 44 | label = "sl50:red:usr1"; |
| 45 | gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; |
| 46 | default-state = "off"; |
| 47 | }; |
| 48 | |
| Javier Martinez Canillas | c731abd | 2016-08-01 12:47:03 -0400 | [diff] [blame] | 49 | led2 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 50 | label = "sl50:green:usr2"; |
| 51 | gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; |
| 52 | default-state = "off"; |
| 53 | }; |
| 54 | |
| Javier Martinez Canillas | c731abd | 2016-08-01 12:47:03 -0400 | [diff] [blame] | 55 | led3 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 56 | label = "sl50:red:usr3"; |
| 57 | gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; |
| 58 | default-state = "off"; |
| 59 | }; |
| 60 | }; |
| 61 | |
| 62 | backlight0: disp0 { |
| 63 | compatible = "pwm-backlight"; |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 64 | pinctrl-names = "default"; |
| 65 | pinctrl-0 = <&backlight0_pins>; |
| 66 | pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>; |
| 67 | brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| 68 | 10 11 12 13 14 15 16 17 18 19 |
| 69 | 20 21 22 23 24 25 26 27 28 29 |
| 70 | 30 31 32 33 34 35 36 37 38 39 |
| 71 | 40 41 42 43 44 45 46 47 48 49 |
| 72 | 50 51 52 53 54 55 56 57 58 59 |
| 73 | 60 61 62 63 64 65 66 67 68 69 |
| 74 | 70 71 72 73 74 75 76 77 78 79 |
| 75 | 80 81 82 83 84 85 86 87 88 89 |
| 76 | 90 91 92 93 94 95 96 97 98 99 |
| 77 | 100>; |
| 78 | default-brightness-level = <50>; |
| 79 | enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; |
| 80 | power-supply = <&vdd_sys_reg>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 81 | }; |
| 82 | |
| 83 | backlight1: disp1 { |
| 84 | compatible = "pwm-backlight"; |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 85 | pinctrl-names = "default"; |
| 86 | pinctrl-0 = <&backlight1_pins>; |
| 87 | pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>; |
| 88 | brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| 89 | 10 11 12 13 14 15 16 17 18 19 |
| 90 | 20 21 22 23 24 25 26 27 28 29 |
| 91 | 30 31 32 33 34 35 36 37 38 39 |
| 92 | 40 41 42 43 44 45 46 47 48 49 |
| 93 | 50 51 52 53 54 55 56 57 58 59 |
| 94 | 60 61 62 63 64 65 66 67 68 69 |
| 95 | 70 71 72 73 74 75 76 77 78 79 |
| 96 | 80 81 82 83 84 85 86 87 88 89 |
| 97 | 90 91 92 93 94 95 96 97 98 99 |
| 98 | 100>; |
| 99 | default-brightness-level = <50>; |
| 100 | enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; |
| 101 | power-supply = <&vdd_sys_reg>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 102 | }; |
| 103 | |
| Enric Balletbo i Serra | b328d9b | 2016-01-16 11:51:13 +0100 | [diff] [blame] | 104 | clocks { |
| 105 | compatible = "simple-bus"; |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <0>; |
| 108 | |
| 109 | /* audio external oscillator */ |
| 110 | tlv320aic3x_mclk: oscillator@0 { |
| 111 | compatible = "fixed-clock"; |
| 112 | #clock-cells = <0>; |
| 113 | clock-frequency = <24576000>; /* 24.576MHz */ |
| 114 | }; |
| 115 | }; |
| 116 | |
| Enric Balletbo i Serra | 79932e7 | 2018-06-06 17:54:08 +0200 | [diff] [blame] | 117 | panel: lcd_panel { |
| 118 | compatible = "ti,tilcdc,panel"; |
| 119 | pinctrl-names = "default"; |
| 120 | pinctrl-0 = <&lcd_pins>; |
| 121 | |
| 122 | panel-info { |
| 123 | ac-bias = <255>; |
| 124 | ac-bias-intrpt = <0>; |
| 125 | dma-burst-sz = <16>; |
| 126 | bpp = <16>; |
| 127 | fdd = <0x80>; |
| 128 | tft-alt-mode = <0>; |
| 129 | mono-8bit-mode = <0>; |
| 130 | sync-edge = <0>; |
| 131 | sync-ctrl = <1>; |
| 132 | raster-order = <0>; |
| 133 | fifo-th = <0>; |
| 134 | }; |
| 135 | |
| 136 | display-timings { |
| 137 | native-mode = <&timing0>; |
| 138 | timing0: 960x128 { |
| 139 | clock-frequency = <18000000>; |
| 140 | hactive = <960>; |
| 141 | vactive = <272>; |
| 142 | |
| 143 | hback-porch = <40>; |
| 144 | hfront-porch = <16>; |
| 145 | hsync-len = <24>; |
| 146 | hsync-active = <0>; |
| 147 | |
| 148 | vback-porch = <3>; |
| 149 | vfront-porch = <8>; |
| 150 | vsync-len = <4>; |
| 151 | vsync-active = <0>; |
| 152 | }; |
| 153 | }; |
| 154 | }; |
| 155 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 156 | sound { |
| 157 | compatible = "ti,da830-evm-audio"; |
| 158 | ti,model = "AM335x-SL50"; |
| 159 | ti,audio-codec = <&audio_codec>; |
| 160 | ti,mcasp-controller = <&mcasp0>; |
| Enric Balletbo i Serra | b328d9b | 2016-01-16 11:51:13 +0100 | [diff] [blame] | 161 | |
| 162 | clocks = <&tlv320aic3x_mclk>; |
| 163 | clock-names = "mclk"; |
| 164 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 165 | ti,audio-routing = |
| 166 | "Headphone Jack", "HPLOUT", |
| 167 | "Headphone Jack", "HPROUT", |
| 168 | "LINE1R", "Line In", |
| 169 | "LINE1L", "Line In"; |
| 170 | }; |
| 171 | |
| 172 | emmc_pwrseq: pwrseq@0 { |
| 173 | compatible = "mmc-pwrseq-emmc"; |
| 174 | pinctrl-names = "default"; |
| 175 | pinctrl-0 = <&emmc_pwrseq_pins>; |
| 176 | reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; |
| 177 | }; |
| 178 | |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 179 | vdd_sys_reg: regulator@0 { |
| 180 | compatible = "regulator-fixed"; |
| 181 | regulator-name = "vdd_sys_reg"; |
| 182 | regulator-min-microvolt = <5000000>; |
| 183 | regulator-max-microvolt = <5000000>; |
| 184 | regulator-always-on; |
| 185 | }; |
| 186 | |
| Javier Martinez Canillas | 4c049a5 | 2016-08-01 12:46:58 -0400 | [diff] [blame] | 187 | vmmcsd_fixed: fixedregulator0 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 188 | compatible = "regulator-fixed"; |
| 189 | regulator-name = "vmmcsd_fixed"; |
| 190 | regulator-min-microvolt = <3300000>; |
| 191 | regulator-max-microvolt = <3300000>; |
| 192 | }; |
| 193 | }; |
| 194 | |
| 195 | &am33xx_pinmux { |
| 196 | pinctrl-names = "default"; |
| 197 | pinctrl-0 = <&lwb_pins>; |
| 198 | |
| Enric Balletbo i Serra | 7c12802 | 2018-06-06 17:54:06 +0200 | [diff] [blame] | 199 | backlight0_pins: pinmux_backlight0_pins { |
| 200 | pinctrl-single,pins = < |
| 201 | AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */ |
| 202 | >; |
| 203 | }; |
| 204 | |
| 205 | backlight1_pins: pinmux_backlight1_pins { |
| 206 | pinctrl-single,pins = < |
| 207 | AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* gpmc_ad10.gpio0_26 */ |
| 208 | >; |
| 209 | }; |
| 210 | |
| Enric Balletbo i Serra | 79932e7 | 2018-06-06 17:54:08 +0200 | [diff] [blame] | 211 | lcd_pins: pinmux_lcd_pins { |
| 212 | pinctrl-single,pins = < |
| 213 | AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ |
| 214 | AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ |
| 215 | AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ |
| 216 | AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ |
| 217 | AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ |
| 218 | AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ |
| 219 | AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ |
| 220 | AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ |
| 221 | AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ |
| 222 | AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ |
| 223 | AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ |
| 224 | AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ |
| 225 | AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ |
| 226 | AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ |
| 227 | AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ |
| 228 | AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ |
| 229 | AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ |
| 230 | AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ |
| 231 | AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ |
| 232 | AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ |
| 233 | >; |
| 234 | }; |
| 235 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 236 | led_pins: pinmux_led_pins { |
| 237 | pinctrl-single,pins = < |
| 238 | AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */ |
| 239 | AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */ |
| 240 | AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */ |
| 241 | AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */ |
| 242 | >; |
| 243 | }; |
| 244 | |
| 245 | uart0_pins: pinmux_uart0_pins { |
| 246 | pinctrl-single,pins = < |
| 247 | AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ |
| 248 | AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ |
| 249 | >; |
| 250 | }; |
| 251 | |
| Enric Balletbo i Serra | e9c7beb | 2017-01-16 17:57:32 +0100 | [diff] [blame] | 252 | uart1_pins: pinmux_uart1_pins { |
| 253 | pinctrl-single,pins = < |
| 254 | AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ |
| 255 | AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ |
| 256 | >; |
| 257 | }; |
| 258 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 259 | uart4_pins: pinmux_uart4_pins { |
| 260 | pinctrl-single,pins = < |
| 261 | AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ |
| 262 | AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ |
| 263 | >; |
| 264 | }; |
| 265 | |
| 266 | i2c0_pins: pinmux_i2c0_pins { |
| 267 | pinctrl-single,pins = < |
| 268 | AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 269 | AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
| 270 | >; |
| 271 | }; |
| 272 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 273 | i2c2_pins: pinmux_i2c2_pins { |
| 274 | pinctrl-single,pins = < |
| 275 | AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ |
| 276 | AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ |
| 277 | >; |
| 278 | }; |
| 279 | |
| 280 | cpsw_default: cpsw_default { |
| 281 | pinctrl-single,pins = < |
| 282 | /* Slave 1 */ |
| 283 | AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ |
| 284 | AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ |
| 285 | AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ |
| 286 | AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ |
| 287 | AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ |
| 288 | AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ |
| 289 | AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ |
| 290 | AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ |
| 291 | AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ |
| 292 | AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ |
| 293 | AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ |
| 294 | AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ |
| 295 | AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ |
| 296 | >; |
| 297 | }; |
| 298 | |
| 299 | cpsw_sleep: cpsw_sleep { |
| 300 | pinctrl-single,pins = < |
| 301 | /* Slave 1 reset value */ |
| 302 | AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 303 | AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 304 | AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 305 | AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 306 | AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 307 | AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 308 | AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 309 | AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 310 | AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 311 | AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 312 | AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 313 | AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 314 | AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 315 | >; |
| 316 | }; |
| 317 | |
| 318 | davinci_mdio_default: davinci_mdio_default { |
| 319 | pinctrl-single,pins = < |
| 320 | /* MDIO */ |
| 321 | AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 322 | AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| Enric Balletbo i Serra | 25d2ee9 | 2018-06-06 17:54:07 +0200 | [diff] [blame] | 323 | /* Ethernet */ |
| 324 | AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* Ethernet_nRST - gpmc_ad14.gpio1_14 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 325 | >; |
| 326 | }; |
| 327 | |
| 328 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 329 | pinctrl-single,pins = < |
| 330 | /* MDIO reset value */ |
| 331 | AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 332 | AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 333 | >; |
| 334 | }; |
| 335 | |
| 336 | mmc1_pins: pinmux_mmc1_pins { |
| 337 | pinctrl-single,pins = < |
| Enric Balletbo i Serra | 56b74ed | 2017-05-22 11:01:52 +0200 | [diff] [blame] | 338 | AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 339 | >; |
| 340 | }; |
| 341 | |
| 342 | emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins { |
| 343 | pinctrl-single,pins = < |
| 344 | AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */ |
| 345 | >; |
| 346 | }; |
| 347 | |
| 348 | emmc_pins: pinmux_emmc_pins { |
| 349 | pinctrl-single,pins = < |
| 350 | AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ |
| 351 | AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ |
| 352 | AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ |
| 353 | AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ |
| 354 | AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ |
| 355 | AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ |
| 356 | AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ |
| 357 | AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ |
| 358 | AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ |
| 359 | AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ |
| 360 | >; |
| 361 | }; |
| 362 | |
| 363 | audio_pins: pinmux_audio_pins { |
| 364 | pinctrl-single,pins = < |
| 365 | AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ |
| 366 | AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ |
| 367 | AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ |
| 368 | AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ |
| Enric Balletbo i Serra | b328d9b | 2016-01-16 11:51:13 +0100 | [diff] [blame] | 369 | AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 370 | >; |
| 371 | }; |
| 372 | |
| 373 | ehrpwm1_pins: pinmux_ehrpwm1a_pins { |
| 374 | pinctrl-single,pins = < |
| 375 | AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ |
| 376 | AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */ |
| 377 | >; |
| 378 | }; |
| 379 | |
| Enric Balletbo i Serra | f37f911 | 2017-01-16 17:57:33 +0100 | [diff] [blame] | 380 | spi0_pins: pinmux_spi0_pins { |
| 381 | pinctrl-single,pins = < |
| 382 | AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MOSI - spi0_d0.spi0_d0 */ |
| 383 | AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_MISO - spi0_d1.spi0_d1 */ |
| 384 | AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CLK - spi0_clk.spi0_clk */ |
| 385 | AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */ |
| 386 | AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */ |
| 387 | >; |
| 388 | }; |
| 389 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 390 | lwb_pins: pinmux_lwb_pins { |
| 391 | pinctrl-single,pins = < |
| 392 | AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 393 | AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */ |
| 394 | AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 395 | AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */ |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 396 | /* PDI Bus - Battery system */ |
| 397 | AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */ |
| 398 | AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */ |
| 399 | >; |
| 400 | }; |
| 401 | }; |
| 402 | |
| 403 | &i2c0 { |
| 404 | status = "okay"; |
| 405 | pinctrl-names = "default"; |
| 406 | pinctrl-0 = <&i2c0_pins>; |
| 407 | |
| 408 | clock-frequency = <400000>; |
| 409 | |
| 410 | tps: tps@24 { |
| 411 | reg = <0x24>; |
| 412 | }; |
| 413 | |
| Enric Balletbo i Serra | 1d669a7 | 2017-01-16 17:57:34 +0100 | [diff] [blame] | 414 | bq32000: rtc@68 { |
| 415 | compatible = "ti,bq32000"; |
| 416 | trickle-resistor-ohms = <1120>; |
| 417 | reg = <0x68>; |
| 418 | }; |
| 419 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 420 | eeprom: eeprom@50 { |
| Javier Martinez Canillas | 05e7d62 | 2017-05-23 15:34:31 +0200 | [diff] [blame] | 421 | compatible = "atmel,24c256"; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 422 | reg = <0x50>; |
| 423 | }; |
| Enric Balletbo i Serra | 1d669a7 | 2017-01-16 17:57:34 +0100 | [diff] [blame] | 424 | |
| Enric Balletbo i Serra | 4340f9d | 2017-01-16 17:57:35 +0100 | [diff] [blame] | 425 | gpio_exp: mcp23017@20 { |
| 426 | compatible = "microchip,mcp23017"; |
| 427 | reg = <0x20>; |
| 428 | }; |
| Enric Balletbo i Serra | 1d669a7 | 2017-01-16 17:57:34 +0100 | [diff] [blame] | 429 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 430 | }; |
| 431 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 432 | &i2c2 { |
| 433 | status = "okay"; |
| 434 | pinctrl-names = "default"; |
| 435 | pinctrl-0 = <&i2c2_pins>; |
| 436 | |
| 437 | clock-frequency = <400000>; |
| 438 | |
| 439 | audio_codec: tlv320aic3106@1b { |
| 440 | status = "okay"; |
| 441 | compatible = "ti,tlv320aic3106"; |
| 442 | reg = <0x1b>; |
| 443 | |
| 444 | AVDD-supply = <&ldo4_reg>; |
| 445 | IOVDD-supply = <&ldo4_reg>; |
| 446 | DRVDD-supply = <&ldo4_reg>; |
| 447 | DVDD-supply = <&ldo3_reg>; |
| 448 | }; |
| Enric Balletbo i Serra | 885658f | 2017-01-16 17:57:36 +0100 | [diff] [blame] | 449 | |
| 450 | /* Ambient Light Sensor */ |
| 451 | als: isl29023@44 { |
| 452 | compatible = "isil,isl29023"; |
| 453 | reg = <0x44>; |
| 454 | }; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 455 | }; |
| 456 | |
| Enric Balletbo i Serra | 1d669a7 | 2017-01-16 17:57:34 +0100 | [diff] [blame] | 457 | &rtc { |
| 458 | status = "disabled"; |
| 459 | }; |
| 460 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 461 | &usb { |
| 462 | status = "okay"; |
| 463 | }; |
| 464 | |
| 465 | &usb_ctrl_mod { |
| 466 | status = "okay"; |
| 467 | }; |
| 468 | |
| 469 | &usb0_phy { |
| 470 | status = "okay"; |
| 471 | }; |
| 472 | |
| 473 | &usb1_phy { |
| 474 | status = "okay"; |
| 475 | }; |
| 476 | |
| 477 | &usb0 { |
| 478 | status = "okay"; |
| Enric Balletbo i Serra | f9d1dec | 2018-06-06 17:54:09 +0200 | [diff] [blame^] | 479 | dr_mode = "otg"; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 480 | }; |
| 481 | |
| 482 | &usb1 { |
| 483 | status = "okay"; |
| 484 | dr_mode = "host"; |
| 485 | }; |
| 486 | |
| 487 | &cppi41dma { |
| 488 | status = "okay"; |
| 489 | }; |
| 490 | |
| 491 | &mmc1 { |
| 492 | status = "okay"; |
| 493 | pinctrl-names = "default"; |
| 494 | pinctrl-0 = <&mmc1_pins>; |
| 495 | bus-width = <4>; |
| Enric Balletbo i Serra | 56b74ed | 2017-05-22 11:01:52 +0200 | [diff] [blame] | 496 | cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 497 | vmmc-supply = <&vmmcsd_fixed>; |
| 498 | }; |
| 499 | |
| 500 | &mmc2 { |
| 501 | status = "okay"; |
| 502 | pinctrl-names = "default"; |
| 503 | pinctrl-0 = <&emmc_pins>; |
| 504 | bus-width = <8>; |
| 505 | vmmc-supply = <&vmmcsd_fixed>; |
| 506 | mmc-pwrseq = <&emmc_pwrseq>; |
| 507 | }; |
| 508 | |
| 509 | &mcasp0 { |
| 510 | status = "okay"; |
| 511 | pinctrl-names = "default"; |
| 512 | pinctrl-0 = <&audio_pins>; |
| 513 | |
| 514 | op-mode = <0>; /* MCASP_ISS_MODE */ |
| 515 | tdm-slots = <2>; |
| 516 | serial-dir = < |
| 517 | 2 0 1 0 |
| 518 | 0 0 0 0 |
| 519 | 0 0 0 0 |
| 520 | 0 0 0 0 |
| 521 | >; |
| 522 | tx-num-evt = <1>; |
| 523 | rx-num-evt = <1>; |
| 524 | }; |
| 525 | |
| 526 | &uart0 { |
| 527 | status = "okay"; |
| 528 | pinctrl-names = "default"; |
| 529 | pinctrl-0 = <&uart0_pins>; |
| 530 | }; |
| 531 | |
| Enric Balletbo i Serra | e9c7beb | 2017-01-16 17:57:32 +0100 | [diff] [blame] | 532 | &uart1 { |
| 533 | status = "okay"; |
| 534 | pinctrl-names = "default"; |
| 535 | pinctrl-0 = <&uart1_pins>; |
| 536 | }; |
| 537 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 538 | &uart4 { |
| 539 | status = "okay"; |
| 540 | pinctrl-names = "default"; |
| 541 | pinctrl-0 = <&uart4_pins>; |
| 542 | }; |
| 543 | |
| Enric Balletbo i Serra | f37f911 | 2017-01-16 17:57:33 +0100 | [diff] [blame] | 544 | &spi0 { |
| 545 | status = "okay"; |
| 546 | pinctrl-names = "default"; |
| 547 | pinctrl-0 = <&spi0_pins>; |
| 548 | |
| 549 | flash: n25q032@1 { |
| 550 | #address-cells = <1>; |
| 551 | #size-cells = <1>; |
| 552 | compatible = "micron,n25q032"; |
| 553 | reg = <1>; |
| 554 | spi-max-frequency = <5000000>; |
| 555 | }; |
| 556 | }; |
| 557 | |
| Peter Ujfalusi | e327b3f | 2016-02-19 16:12:19 +0200 | [diff] [blame] | 558 | #include "tps65217.dtsi" |
| 559 | |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 560 | &tps { |
| 561 | ti,pmic-shutdown-controller; |
| 562 | |
| 563 | interrupt-parent = <&intc>; |
| 564 | interrupts = <7>; /* NNMI */ |
| 565 | |
| 566 | regulators { |
| 567 | dcdc1_reg: regulator@0 { |
| 568 | /* VDDS_DDR */ |
| 569 | regulator-min-microvolt = <1500000>; |
| 570 | regulator-max-microvolt = <1500000>; |
| 571 | regulator-always-on; |
| 572 | }; |
| 573 | |
| 574 | dcdc2_reg: regulator@1 { |
| 575 | /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| 576 | regulator-name = "vdd_mpu"; |
| 577 | regulator-min-microvolt = <925000>; |
| 578 | regulator-max-microvolt = <1325000>; |
| 579 | regulator-boot-on; |
| 580 | regulator-always-on; |
| 581 | }; |
| 582 | |
| 583 | dcdc3_reg: regulator@2 { |
| 584 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| 585 | regulator-name = "vdd_core"; |
| 586 | regulator-min-microvolt = <925000>; |
| 587 | regulator-max-microvolt = <1150000>; |
| 588 | regulator-boot-on; |
| 589 | regulator-always-on; |
| 590 | }; |
| 591 | |
| 592 | ldo1_reg: regulator@3 { |
| 593 | /* VRTC / VIO / VDDS*/ |
| 594 | regulator-always-on; |
| 595 | regulator-min-microvolt = <1800000>; |
| 596 | regulator-max-microvolt = <1800000>; |
| 597 | }; |
| 598 | |
| 599 | ldo2_reg: regulator@4 { |
| 600 | /* VDD_3V3AUX */ |
| 601 | regulator-always-on; |
| 602 | regulator-min-microvolt = <3300000>; |
| 603 | regulator-max-microvolt = <3300000>; |
| 604 | }; |
| 605 | |
| 606 | ldo3_reg: regulator@5 { |
| 607 | /* VDD_1V8 */ |
| 608 | regulator-min-microvolt = <1800000>; |
| 609 | regulator-max-microvolt = <1800000>; |
| 610 | regulator-always-on; |
| 611 | }; |
| 612 | |
| 613 | ldo4_reg: regulator@6 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 614 | /* VDD_3V3A */ |
| 615 | regulator-min-microvolt = <3300000>; |
| 616 | regulator-max-microvolt = <3300000>; |
| 617 | regulator-always-on; |
| 618 | }; |
| 619 | }; |
| 620 | }; |
| 621 | |
| 622 | &cpsw_emac0 { |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 623 | phy-mode = "mii"; |
| Enric Balletbo i Serra | 25d2ee9 | 2018-06-06 17:54:07 +0200 | [diff] [blame] | 624 | phy-handle = <ðphy0>; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 625 | }; |
| 626 | |
| 627 | &mac { |
| 628 | status = "okay"; |
| 629 | pinctrl-names = "default", "sleep"; |
| 630 | pinctrl-0 = <&cpsw_default>; |
| 631 | pinctrl-1 = <&cpsw_sleep>; |
| 632 | }; |
| 633 | |
| 634 | &davinci_mdio { |
| 635 | status = "okay"; |
| 636 | pinctrl-names = "default", "sleep"; |
| 637 | pinctrl-0 = <&davinci_mdio_default>; |
| 638 | pinctrl-1 = <&davinci_mdio_sleep>; |
| Enric Balletbo i Serra | 25d2ee9 | 2018-06-06 17:54:07 +0200 | [diff] [blame] | 639 | reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; |
| 640 | reset-delay-us = <100>; /* PHY datasheet states 100us min */ |
| 641 | |
| 642 | ethphy0: ethernet-phy@0 { |
| 643 | reg = <0>; |
| 644 | }; |
| Enric Balletbo i Serra | 8584d4f | 2015-05-28 09:49:50 -0700 | [diff] [blame] | 645 | }; |
| 646 | |
| 647 | &sham { |
| 648 | status = "okay"; |
| 649 | }; |
| 650 | |
| 651 | &aes { |
| 652 | status = "okay"; |
| 653 | }; |
| 654 | |
| 655 | &epwmss1 { |
| 656 | status = "okay"; |
| 657 | }; |
| 658 | |
| 659 | &ehrpwm1 { |
| 660 | status = "okay"; |
| 661 | pinctrl-names = "default"; |
| 662 | pinctrl-0 = <&ehrpwm1_pins>; |
| 663 | }; |
| Enric Balletbo i Serra | 79932e7 | 2018-06-06 17:54:08 +0200 | [diff] [blame] | 664 | |
| 665 | &lcdc { |
| 666 | status = "okay"; |
| 667 | }; |