| Jiri Slaby | fa1c114 | 2007-08-12 17:33:16 +0200 | [diff] [blame^] | 1 | /*- |
| 2 | * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
| 8 | * 1. Redistributions of source code must retain the above copyright |
| 9 | * notice, this list of conditions and the following disclaimer, |
| 10 | * without modification. |
| 11 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
| 12 | * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any |
| 13 | * redistribution must be conditioned upon including a substantially |
| 14 | * similar Disclaimer requirement for further binary redistribution. |
| 15 | * 3. Neither the names of the above-listed copyright holders nor the names |
| 16 | * of any contributors may be used to endorse or promote products derived |
| 17 | * from this software without specific prior written permission. |
| 18 | * |
| 19 | * Alternatively, this software may be distributed under the terms of the |
| 20 | * GNU General Public License ("GPL") version 2 as published by the Free |
| 21 | * Software Foundation. |
| 22 | * |
| 23 | * NO WARRANTY |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 25 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 26 | * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY |
| 27 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL |
| 28 | * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, |
| 29 | * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 30 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 31 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER |
| 32 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 33 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 34 | * THE POSSIBILITY OF SUCH DAMAGES. |
| 35 | * |
| 36 | */ |
| 37 | |
| 38 | /* |
| 39 | * Defintions for the Atheros Wireless LAN controller driver. |
| 40 | */ |
| 41 | #ifndef _DEV_ATH_ATHVAR_H |
| 42 | #define _DEV_ATH_ATHVAR_H |
| 43 | |
| 44 | #include <linux/interrupt.h> |
| 45 | #include <linux/list.h> |
| 46 | #include <linux/wireless.h> |
| 47 | #include <linux/if_ether.h> |
| 48 | |
| 49 | #include "ath5k.h" |
| 50 | #include "debug.h" |
| 51 | |
| 52 | #define ATH_RXBUF 40 /* number of RX buffers */ |
| 53 | #define ATH_TXBUF 200 /* number of TX buffers */ |
| 54 | #define ATH_BCBUF 1 /* number of beacon buffers */ |
| 55 | |
| 56 | struct ath5k_buf { |
| 57 | struct list_head list; |
| 58 | unsigned int flags; /* tx descriptor flags */ |
| 59 | struct ath5k_desc *desc; /* virtual addr of desc */ |
| 60 | dma_addr_t daddr; /* physical addr of desc */ |
| 61 | struct sk_buff *skb; /* skbuff for buf */ |
| 62 | dma_addr_t skbaddr;/* physical addr of skb data */ |
| 63 | struct ieee80211_tx_control ctl; |
| 64 | }; |
| 65 | |
| 66 | /* |
| 67 | * Data transmit queue state. One of these exists for each |
| 68 | * hardware transmit queue. Packets sent to us from above |
| 69 | * are assigned to queues based on their priority. Not all |
| 70 | * devices support a complete set of hardware transmit queues. |
| 71 | * For those devices the array sc_ac2q will map multiple |
| 72 | * priorities to fewer hardware queues (typically all to one |
| 73 | * hardware queue). |
| 74 | */ |
| 75 | struct ath5k_txq { |
| 76 | unsigned int qnum; /* hardware q number */ |
| 77 | u32 *link; /* link ptr in last TX desc */ |
| 78 | struct list_head q; /* transmit queue */ |
| 79 | spinlock_t lock; /* lock on q and link */ |
| 80 | bool setup; |
| 81 | }; |
| 82 | |
| 83 | #if CHAN_DEBUG |
| 84 | #define ATH_CHAN_MAX (26+26+26+200+200) |
| 85 | #else |
| 86 | #define ATH_CHAN_MAX (14+14+14+252+20) /* XXX what's the max? */ |
| 87 | #endif |
| 88 | |
| 89 | /* Software Carrier, keeps track of the driver state |
| 90 | * associated with an instance of a device */ |
| 91 | struct ath5k_softc { |
| 92 | struct pci_dev *pdev; /* for dma mapping */ |
| 93 | void __iomem *iobase; /* address of the device */ |
| 94 | struct mutex lock; /* dev-level lock */ |
| 95 | struct ieee80211_tx_queue_stats tx_stats; |
| 96 | struct ieee80211_low_level_stats ll_stats; |
| 97 | struct ieee80211_hw *hw; /* IEEE 802.11 common */ |
| 98 | struct ieee80211_hw_mode modes[NUM_DRIVER_MODES]; |
| 99 | struct ieee80211_channel channels[ATH_CHAN_MAX]; |
| 100 | struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_DRIVER_MODES]; |
| 101 | enum ieee80211_if_types opmode; |
| 102 | struct ath5k_hw *ah; /* Atheros HW */ |
| 103 | |
| 104 | #if ATH5K_DEBUG |
| 105 | struct ath5k_dbg_info debug; /* debug info */ |
| 106 | #endif |
| 107 | |
| 108 | struct ath5k_buf *bufptr; /* allocated buffer ptr */ |
| 109 | struct ath5k_desc *desc; /* TX/RX descriptors */ |
| 110 | dma_addr_t desc_daddr; /* DMA (physical) address */ |
| 111 | size_t desc_len; /* size of TX/RX descriptors */ |
| 112 | u16 cachelsz; /* cache line size */ |
| 113 | |
| 114 | DECLARE_BITMAP(status, 6); |
| 115 | #define ATH_STAT_INVALID 0 /* disable hardware accesses */ |
| 116 | #define ATH_STAT_MRRETRY 1 /* multi-rate retry support */ |
| 117 | #define ATH_STAT_PROMISC 2 |
| 118 | #define ATH_STAT_LEDBLINKING 3 /* LED blink operation active */ |
| 119 | #define ATH_STAT_LEDENDBLINK 4 /* finish LED blink operation */ |
| 120 | #define ATH_STAT_LEDSOFT 5 /* enable LED gpio status */ |
| 121 | |
| 122 | unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */ |
| 123 | unsigned int curmode; /* current phy mode */ |
| 124 | struct ieee80211_channel *curchan; /* current h/w channel */ |
| 125 | |
| 126 | int iface_id; /* add/remove_interface id */ |
| 127 | |
| 128 | struct { |
| 129 | u8 rxflags; /* radiotap rx flags */ |
| 130 | u8 txflags; /* radiotap tx flags */ |
| 131 | u16 ledon; /* softled on time */ |
| 132 | u16 ledoff; /* softled off time */ |
| 133 | } hwmap[32]; /* h/w rate ix mappings */ |
| 134 | |
| 135 | enum ath5k_int imask; /* interrupt mask copy */ |
| 136 | |
| 137 | DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */ |
| 138 | |
| 139 | u8 bssidmask[ETH_ALEN]; |
| 140 | |
| 141 | unsigned int led_pin, /* GPIO pin for driving LED */ |
| 142 | led_on, /* pin setting for LED on */ |
| 143 | led_off; /* off time for current blink */ |
| 144 | struct timer_list led_tim; /* led off timer */ |
| 145 | u8 led_rxrate; /* current rx rate for LED */ |
| 146 | u8 led_txrate; /* current tx rate for LED */ |
| 147 | |
| 148 | struct tasklet_struct restq; /* reset tasklet */ |
| 149 | |
| 150 | unsigned int rxbufsize; /* rx size based on mtu */ |
| 151 | struct list_head rxbuf; /* receive buffer */ |
| 152 | spinlock_t rxbuflock; |
| 153 | u32 *rxlink; /* link ptr in last RX desc */ |
| 154 | struct tasklet_struct rxtq; /* rx intr tasklet */ |
| 155 | |
| 156 | struct list_head txbuf; /* transmit buffer */ |
| 157 | spinlock_t txbuflock; |
| 158 | unsigned int txbuf_len; /* buf count in txbuf list */ |
| 159 | struct ath5k_txq txqs[2]; /* beacon and tx */ |
| 160 | |
| 161 | struct ath5k_txq *txq; /* beacon and tx*/ |
| 162 | struct tasklet_struct txtq; /* tx intr tasklet */ |
| 163 | |
| 164 | struct ath5k_buf *bbuf; /* beacon buffer */ |
| 165 | unsigned int bhalq, /* SW q for outgoing beacons */ |
| 166 | bmisscount, /* missed beacon transmits */ |
| 167 | bintval, /* beacon interval */ |
| 168 | bsent; |
| 169 | |
| 170 | struct timer_list calib_tim; /* calibration timer */ |
| 171 | }; |
| 172 | |
| 173 | #define ath5k_hw_hasbssidmask(_ah) \ |
| 174 | (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) |
| 175 | #define ath5k_hw_hasveol(_ah) \ |
| 176 | (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) |
| 177 | |
| 178 | #endif |