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Eric Miao64ed2672010-10-13 14:51:25 +08001#ifndef __ASM_MACH_ADDR_MAP_H
2#define __ASM_MACH_ADDR_MAP_H
3
4/*
5 * Chip Selects
6 */
7#define PXA_CS0_PHYS 0x00000000
8#define PXA_CS1_PHYS 0x04000000
9#define PXA_CS2_PHYS 0x08000000
10#define PXA_CS3_PHYS 0x0C000000
11#define PXA_CS4_PHYS 0x10000000
12#define PXA_CS5_PHYS 0x14000000
13
14#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
15#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
16#define PXA3xx_CS2_PHYS 0x10000000
17#define PXA3xx_CS3_PHYS 0x14000000
18
19/*
20 * Peripheral Bus
21 */
22#define PERIPH_PHYS 0x40000000
Arnd Bergmann97b09da2011-10-01 22:03:45 +020023#define PERIPH_VIRT IOMEM(0xf2000000)
Eric Miao64ed2672010-10-13 14:51:25 +080024#define PERIPH_SIZE 0x02000000
25
26/*
27 * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
28 */
29#define PXA2XX_SMEMC_PHYS 0x48000000
30#define PXA3XX_SMEMC_PHYS 0x4a000000
Arnd Bergmann97b09da2011-10-01 22:03:45 +020031#define SMEMC_VIRT IOMEM(0xf6000000)
Eric Miao64ed2672010-10-13 14:51:25 +080032#define SMEMC_SIZE 0x00100000
33
34/*
35 * Dynamic Memory Controller (only on PXA3xx)
36 */
37#define DMEMC_PHYS 0x48100000
Arnd Bergmann97b09da2011-10-01 22:03:45 +020038#define DMEMC_VIRT IOMEM(0xf6100000)
Eric Miao64ed2672010-10-13 14:51:25 +080039#define DMEMC_SIZE 0x00100000
40
41/*
Robert Jarzmikcde7fc82014-10-07 21:18:14 +020042 * Reserved space for low level debug virtual addresses within
43 * 0xf6200000..0xf6201000
44 */
45
46/*
Eric Miao64ed2672010-10-13 14:51:25 +080047 * Internal Memory Controller (PXA27x and later)
48 */
49#define IMEMC_PHYS 0x58000000
Arnd Bergmann97b09da2011-10-01 22:03:45 +020050#define IMEMC_VIRT IOMEM(0xfe000000)
Eric Miao64ed2672010-10-13 14:51:25 +080051#define IMEMC_SIZE 0x00100000
52
53#endif /* __ASM_MACH_ADDR_MAP_H */