blob: dcfcce1dc00e343e6d7360d7c6986ea272799dd2 [file] [log] [blame]
Zhi Wang82d375d2016-07-05 12:40:49 -04001/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Eddie Dong <eddie.dong@intel.com>
25 * Kevin Tian <kevin.tian@intel.com>
26 *
27 * Contributors:
28 * Ping Gao <ping.a.gao@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 *
32 */
33
34#include "i915_drv.h"
Zhenyu Wangfeddf6e2016-10-20 17:15:03 +080035#include "gvt.h"
36#include "i915_pvinfo.h"
Zhi Wang82d375d2016-07-05 12:40:49 -040037
Ping Gao23736d12016-10-26 09:38:52 +080038void populate_pvinfo_page(struct intel_vgpu *vgpu)
Zhi Wang82d375d2016-07-05 12:40:49 -040039{
40 /* setup the ballooning information */
41 vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
42 vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
43 vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
44 vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
45 vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
46 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
47 vgpu_aperture_gmadr_base(vgpu);
48 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
49 vgpu_aperture_sz(vgpu);
50 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
51 vgpu_hidden_gmadr_base(vgpu);
52 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
53 vgpu_hidden_sz(vgpu);
54
55 vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
56
57 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
58 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
59 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
60 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
61 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
62 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
63
64 WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
65}
66
67/**
Zhenyu Wang1f31c822016-11-03 18:38:31 +080068 * intel_gvt_init_vgpu_types - initialize vGPU type list
69 * @gvt : GVT device
70 *
71 * Initialize vGPU type list based on available resource.
72 *
73 */
74int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
75{
76 unsigned int num_types;
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +080077 unsigned int i, low_avail, high_avail;
Zhenyu Wang1f31c822016-11-03 18:38:31 +080078 unsigned int min_low;
79
80 /* vGPU type name is defined as GVTg_Vx_y which contains
81 * physical GPU generation type and 'y' means maximum vGPU
82 * instances user can create on one physical GPU for this
83 * type.
84 *
85 * Depend on physical SKU resource, might see vGPU types like
86 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
87 * different types of vGPU on same physical GPU depending on
88 * available resource. Each vGPU type will have "avail_instance"
89 * to indicate how many vGPU instance can be created for this
90 * type.
91 *
Zhenyu Wang1f31c822016-11-03 18:38:31 +080092 */
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +080093 low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
94 high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
Zhenyu Wang1f31c822016-11-03 18:38:31 +080095 num_types = 4;
96
97 gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
98 GFP_KERNEL);
99 if (!gvt->types)
100 return -ENOMEM;
101
102 min_low = MB_TO_BYTES(32);
103 for (i = 0; i < num_types; ++i) {
104 if (low_avail / min_low == 0)
105 break;
106 gvt->types[i].low_gm_size = min_low;
Zhenyu Wang888530b2017-01-05 10:26:13 +0800107 gvt->types[i].high_gm_size = max((min_low<<3), MB_TO_BYTES(384U));
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800108 gvt->types[i].fence = 4;
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800109 gvt->types[i].max_instance = min(low_avail / min_low,
110 high_avail / gvt->types[i].high_gm_size);
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800111 gvt->types[i].avail_instance = gvt->types[i].max_instance;
112
113 if (IS_GEN8(gvt->dev_priv))
114 sprintf(gvt->types[i].name, "GVTg_V4_%u",
115 gvt->types[i].max_instance);
116 else if (IS_GEN9(gvt->dev_priv))
117 sprintf(gvt->types[i].name, "GVTg_V5_%u",
118 gvt->types[i].max_instance);
119
120 min_low <<= 1;
121 gvt_dbg_core("type[%d]: %s max %u avail %u low %u high %u fence %u\n",
122 i, gvt->types[i].name, gvt->types[i].max_instance,
123 gvt->types[i].avail_instance,
124 gvt->types[i].low_gm_size,
125 gvt->types[i].high_gm_size, gvt->types[i].fence);
126 }
127
128 gvt->num_types = i;
129 return 0;
130}
131
132void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
133{
134 kfree(gvt->types);
135}
136
137static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
138{
139 int i;
140 unsigned int low_gm_avail, high_gm_avail, fence_avail;
141 unsigned int low_gm_min, high_gm_min, fence_min, total_min;
142
143 /* Need to depend on maxium hw resource size but keep on
144 * static config for now.
145 */
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800146 low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800147 gvt->gm.vgpu_allocated_low_gm_size;
Zhenyu Wang2d6ceb82017-01-13 15:36:17 +0800148 high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800149 gvt->gm.vgpu_allocated_high_gm_size;
150 fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
151 gvt->fence.vgpu_allocated_fence_num;
152
153 for (i = 0; i < gvt->num_types; i++) {
154 low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
155 high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
156 fence_min = fence_avail / gvt->types[i].fence;
157 total_min = min(min(low_gm_min, high_gm_min), fence_min);
158 gvt->types[i].avail_instance = min(gvt->types[i].max_instance,
159 total_min);
160
161 gvt_dbg_core("update type[%d]: %s max %u avail %u low %u high %u fence %u\n",
162 i, gvt->types[i].name, gvt->types[i].max_instance,
163 gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
164 gvt->types[i].high_gm_size, gvt->types[i].fence);
165 }
166}
167
168/**
Zhi Wang82d375d2016-07-05 12:40:49 -0400169 * intel_gvt_destroy_vgpu - destroy a virtual GPU
170 * @vgpu: virtual GPU
171 *
172 * This function is called when user wants to destroy a virtual GPU.
173 *
174 */
175void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
176{
177 struct intel_gvt *gvt = vgpu->gvt;
178
179 mutex_lock(&gvt->lock);
180
181 vgpu->active = false;
182 idr_remove(&gvt->vgpu_idr, vgpu->id);
183
Zhi Wang4b639602016-05-01 17:09:58 -0400184 if (atomic_read(&vgpu->running_workload_num)) {
185 mutex_unlock(&gvt->lock);
186 intel_gvt_wait_vgpu_idle(vgpu);
187 mutex_lock(&gvt->lock);
188 }
189
190 intel_vgpu_stop_schedule(vgpu);
191 intel_vgpu_clean_sched_policy(vgpu);
Zhi Wange4734052016-05-01 07:42:16 -0400192 intel_vgpu_clean_gvt_context(vgpu);
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400193 intel_vgpu_clean_execlist(vgpu);
Zhi Wang04d348a2016-04-25 18:28:56 -0400194 intel_vgpu_clean_display(vgpu);
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400195 intel_vgpu_clean_opregion(vgpu);
Zhi Wang2707e442016-03-28 23:23:16 +0800196 intel_vgpu_clean_gtt(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400197 intel_gvt_hypervisor_detach_vgpu(vgpu);
198 intel_vgpu_free_resource(vgpu);
Changbin Ducdcc4342017-01-13 11:16:00 +0800199 intel_vgpu_clean_mmio(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400200 vfree(vgpu);
201
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800202 intel_gvt_update_vgpu_types(gvt);
Zhi Wang82d375d2016-07-05 12:40:49 -0400203 mutex_unlock(&gvt->lock);
204}
205
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800206static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
Zhi Wang82d375d2016-07-05 12:40:49 -0400207 struct intel_vgpu_creation_params *param)
208{
209 struct intel_vgpu *vgpu;
210 int ret;
211
212 gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
213 param->handle, param->low_gm_sz, param->high_gm_sz,
214 param->fence_sz);
215
216 vgpu = vzalloc(sizeof(*vgpu));
217 if (!vgpu)
218 return ERR_PTR(-ENOMEM);
219
220 mutex_lock(&gvt->lock);
221
222 ret = idr_alloc(&gvt->vgpu_idr, vgpu, 1, GVT_MAX_VGPU, GFP_KERNEL);
223 if (ret < 0)
224 goto out_free_vgpu;
225
226 vgpu->id = ret;
227 vgpu->handle = param->handle;
228 vgpu->gvt = gvt;
Zhi Wang17865712016-05-01 19:02:37 -0400229 bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
Zhi Wang82d375d2016-07-05 12:40:49 -0400230
Changbin Du536fc232017-01-13 11:15:58 +0800231 intel_vgpu_init_cfg_space(vgpu, param->primary);
Zhi Wang82d375d2016-07-05 12:40:49 -0400232
Changbin Ducdcc4342017-01-13 11:16:00 +0800233 ret = intel_vgpu_init_mmio(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400234 if (ret)
Jike Song4e537892017-01-06 15:16:22 +0800235 goto out_clean_idr;
Zhi Wang82d375d2016-07-05 12:40:49 -0400236
237 ret = intel_vgpu_alloc_resource(vgpu, param);
238 if (ret)
239 goto out_clean_vgpu_mmio;
240
241 populate_pvinfo_page(vgpu);
242
243 ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
244 if (ret)
245 goto out_clean_vgpu_resource;
246
Zhi Wang2707e442016-03-28 23:23:16 +0800247 ret = intel_vgpu_init_gtt(vgpu);
248 if (ret)
249 goto out_detach_hypervisor_vgpu;
250
Zhi Wang04d348a2016-04-25 18:28:56 -0400251 ret = intel_vgpu_init_display(vgpu);
252 if (ret)
Jike Song8f897432016-11-03 18:38:32 +0800253 goto out_clean_gtt;
Zhi Wang04d348a2016-04-25 18:28:56 -0400254
Zhi Wang8453d672016-05-01 02:48:25 -0400255 ret = intel_vgpu_init_execlist(vgpu);
256 if (ret)
257 goto out_clean_display;
258
Zhi Wange4734052016-05-01 07:42:16 -0400259 ret = intel_vgpu_init_gvt_context(vgpu);
260 if (ret)
261 goto out_clean_execlist;
262
Zhi Wang4b639602016-05-01 17:09:58 -0400263 ret = intel_vgpu_init_sched_policy(vgpu);
264 if (ret)
265 goto out_clean_shadow_ctx;
266
Zhi Wang82d375d2016-07-05 12:40:49 -0400267 vgpu->active = true;
268 mutex_unlock(&gvt->lock);
269
270 return vgpu;
271
Zhi Wang4b639602016-05-01 17:09:58 -0400272out_clean_shadow_ctx:
273 intel_vgpu_clean_gvt_context(vgpu);
Zhi Wange4734052016-05-01 07:42:16 -0400274out_clean_execlist:
275 intel_vgpu_clean_execlist(vgpu);
Zhi Wang8453d672016-05-01 02:48:25 -0400276out_clean_display:
277 intel_vgpu_clean_display(vgpu);
Zhi Wang4d60c5fd2016-07-20 01:14:38 -0400278out_clean_gtt:
279 intel_vgpu_clean_gtt(vgpu);
Zhi Wang2707e442016-03-28 23:23:16 +0800280out_detach_hypervisor_vgpu:
281 intel_gvt_hypervisor_detach_vgpu(vgpu);
Zhi Wang82d375d2016-07-05 12:40:49 -0400282out_clean_vgpu_resource:
283 intel_vgpu_free_resource(vgpu);
284out_clean_vgpu_mmio:
Changbin Ducdcc4342017-01-13 11:16:00 +0800285 intel_vgpu_clean_mmio(vgpu);
Jike Song4e537892017-01-06 15:16:22 +0800286out_clean_idr:
287 idr_remove(&gvt->vgpu_idr, vgpu->id);
Zhi Wang82d375d2016-07-05 12:40:49 -0400288out_free_vgpu:
289 vfree(vgpu);
290 mutex_unlock(&gvt->lock);
291 return ERR_PTR(ret);
292}
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800293
294/**
295 * intel_gvt_create_vgpu - create a virtual GPU
296 * @gvt: GVT device
297 * @type: type of the vGPU to create
298 *
299 * This function is called when user wants to create a virtual GPU.
300 *
301 * Returns:
302 * pointer to intel_vgpu, error pointer if failed.
303 */
304struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
305 struct intel_vgpu_type *type)
306{
307 struct intel_vgpu_creation_params param;
308 struct intel_vgpu *vgpu;
309
310 param.handle = 0;
Du, Changbine992fae2016-11-21 17:08:14 +0800311 param.primary = 1;
Zhenyu Wang1f31c822016-11-03 18:38:31 +0800312 param.low_gm_sz = type->low_gm_size;
313 param.high_gm_sz = type->high_gm_size;
314 param.fence_sz = type->fence;
315
316 /* XXX current param based on MB */
317 param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
318 param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
319
320 vgpu = __intel_gvt_create_vgpu(gvt, &param);
321 if (IS_ERR(vgpu))
322 return vgpu;
323
324 /* calculate left instance change for types */
325 intel_gvt_update_vgpu_types(gvt);
326
327 return vgpu;
328}
Jike Song9ec1e662016-11-03 18:38:35 +0800329
330/**
Changbin Ducfe65f42017-01-13 11:16:02 +0800331 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
332 * @vgpu: virtual GPU
333 * @dmlr: vGPU Device Model Level Reset or GT Reset
334 * @engine_mask: engines to reset for GT reset
335 *
336 * This function is called when user wants to reset a virtual GPU through
337 * device model reset or GT reset. The caller should hold the gvt lock.
338 *
339 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
340 * the whole vGPU to default state as when it is created. This vGPU function
341 * is required both for functionary and security concerns.The ultimate goal
342 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
343 * assign a vGPU to a virtual machine we must isse such reset first.
344 *
345 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
346 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
347 * Unlike the FLR, GT reset only reset particular resource of a vGPU per
348 * the reset request. Guest driver can issue a GT reset by programming the
349 * virtual GDRST register to reset specific virtual GPU engine or all
350 * engines.
351 *
352 * The parameter dev_level is to identify if we will do DMLR or GT reset.
353 * The parameter engine_mask is to specific the engines that need to be
354 * resetted. If value ALL_ENGINES is given for engine_mask, it means
355 * the caller requests a full GT reset that we will reset all virtual
356 * GPU engines. For FLR, engine_mask is ignored.
357 */
358void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
359 unsigned int engine_mask)
360{
361 struct intel_gvt *gvt = vgpu->gvt;
362 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
363
364 gvt_dbg_core("------------------------------------------\n");
365 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
366 vgpu->id, dmlr, engine_mask);
367 vgpu->resetting = true;
368
369 intel_vgpu_stop_schedule(vgpu);
370 /*
371 * The current_vgpu will set to NULL after stopping the
372 * scheduler when the reset is triggered by current vgpu.
373 */
374 if (scheduler->current_vgpu == NULL) {
375 mutex_unlock(&gvt->lock);
376 intel_gvt_wait_vgpu_idle(vgpu);
377 mutex_lock(&gvt->lock);
378 }
379
380 intel_vgpu_reset_execlist(vgpu, dmlr ? ALL_ENGINES : engine_mask);
381
382 /* full GPU reset or device model level reset */
383 if (engine_mask == ALL_ENGINES || dmlr) {
384 intel_vgpu_reset_gtt(vgpu, dmlr);
385 intel_vgpu_reset_resource(vgpu);
386 intel_vgpu_reset_mmio(vgpu);
387 populate_pvinfo_page(vgpu);
Changbin Du6294b612017-02-14 14:50:18 +0800388 intel_vgpu_reset_display(vgpu);
Changbin Ducfe65f42017-01-13 11:16:02 +0800389
Min Hefd64be62017-02-17 15:02:36 +0800390 if (dmlr) {
Changbin Ducfe65f42017-01-13 11:16:02 +0800391 intel_vgpu_reset_cfg_space(vgpu);
Min Hefd64be62017-02-17 15:02:36 +0800392 /* only reset the failsafe mode when dmlr reset */
393 vgpu->failsafe = false;
394 vgpu->pv_notified = false;
395 }
Changbin Ducfe65f42017-01-13 11:16:02 +0800396 }
397
398 vgpu->resetting = false;
399 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
400 gvt_dbg_core("------------------------------------------\n");
401}
402
403/**
404 * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
Jike Song9ec1e662016-11-03 18:38:35 +0800405 * @vgpu: virtual GPU
406 *
407 * This function is called when user wants to reset a virtual GPU.
408 *
409 */
410void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
411{
Changbin Ducfe65f42017-01-13 11:16:02 +0800412 mutex_lock(&vgpu->gvt->lock);
413 intel_gvt_reset_vgpu_locked(vgpu, true, 0);
414 mutex_unlock(&vgpu->gvt->lock);
Jike Song9ec1e662016-11-03 18:38:35 +0800415}