blob: 55c9fdcfa67fc3a02517f9308f752ddf26c67508 [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001/*
2 * Copyright (C) 2006 Ben Skeggs.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28/*
29 * Authors:
30 * Ben Skeggs <darktama@iinet.net.au>
31 */
32
33#include "drmP.h"
34#include "drm.h"
35#include "nouveau_drv.h"
36#include "nouveau_drm.h"
Ben Skeggs479dcae2010-09-01 15:24:28 +100037#include "nouveau_ramht.h"
Ben Skeggs4c1361422010-11-15 11:54:21 +100038#include "nouveau_vm.h"
Ben Skeggs6ee73862009-12-11 19:24:15 +100039
Ben Skeggsb8c157d2010-10-20 10:39:35 +100040struct nouveau_gpuobj_method {
41 struct list_head head;
42 u32 mthd;
43 int (*exec)(struct nouveau_channel *, u32 class, u32 mthd, u32 data);
44};
45
46struct nouveau_gpuobj_class {
47 struct list_head head;
48 struct list_head methods;
49 u32 id;
50 u32 engine;
51};
52
53int
54nouveau_gpuobj_class_new(struct drm_device *dev, u32 class, u32 engine)
55{
56 struct drm_nouveau_private *dev_priv = dev->dev_private;
57 struct nouveau_gpuobj_class *oc;
58
59 oc = kzalloc(sizeof(*oc), GFP_KERNEL);
60 if (!oc)
61 return -ENOMEM;
62
63 INIT_LIST_HEAD(&oc->methods);
64 oc->id = class;
65 oc->engine = engine;
66 list_add(&oc->head, &dev_priv->classes);
67 return 0;
68}
69
70int
71nouveau_gpuobj_mthd_new(struct drm_device *dev, u32 class, u32 mthd,
72 int (*exec)(struct nouveau_channel *, u32, u32, u32))
73{
74 struct drm_nouveau_private *dev_priv = dev->dev_private;
75 struct nouveau_gpuobj_method *om;
76 struct nouveau_gpuobj_class *oc;
77
78 list_for_each_entry(oc, &dev_priv->classes, head) {
79 if (oc->id == class)
80 goto found;
81 }
82
83 return -EINVAL;
84
85found:
86 om = kzalloc(sizeof(*om), GFP_KERNEL);
87 if (!om)
88 return -ENOMEM;
89
90 om->mthd = mthd;
91 om->exec = exec;
92 list_add(&om->head, &oc->methods);
93 return 0;
94}
95
96int
97nouveau_gpuobj_mthd_call(struct nouveau_channel *chan,
98 u32 class, u32 mthd, u32 data)
99{
100 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
101 struct nouveau_gpuobj_method *om;
102 struct nouveau_gpuobj_class *oc;
103
104 list_for_each_entry(oc, &dev_priv->classes, head) {
105 if (oc->id != class)
106 continue;
107
108 list_for_each_entry(om, &oc->methods, head) {
109 if (om->mthd == mthd)
110 return om->exec(chan, class, mthd, data);
111 }
112 }
113
114 return -ENOENT;
115}
116
Ben Skeggs274fec92010-11-03 13:16:18 +1000117int
118nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid,
119 u32 class, u32 mthd, u32 data)
120{
121 struct drm_nouveau_private *dev_priv = dev->dev_private;
122 struct nouveau_channel *chan = NULL;
123 unsigned long flags;
124 int ret = -EINVAL;
125
126 spin_lock_irqsave(&dev_priv->channels.lock, flags);
127 if (chid > 0 && chid < dev_priv->engine.fifo.channels)
128 chan = dev_priv->channels.ptr[chid];
129 if (chan)
130 ret = nouveau_gpuobj_mthd_call(chan, class, mthd, data);
131 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
132 return ret;
133}
134
Ben Skeggs6ee73862009-12-11 19:24:15 +1000135/* NVidia uses context objects to drive drawing operations.
136
137 Context objects can be selected into 8 subchannels in the FIFO,
138 and then used via DMA command buffers.
139
140 A context object is referenced by a user defined handle (CARD32). The HW
141 looks up graphics objects in a hash table in the instance RAM.
142
143 An entry in the hash table consists of 2 CARD32. The first CARD32 contains
144 the handle, the second one a bitfield, that contains the address of the
145 object in instance RAM.
146
147 The format of the second CARD32 seems to be:
148
149 NV4 to NV30:
150
151 15: 0 instance_addr >> 4
152 17:16 engine (here uses 1 = graphics)
153 28:24 channel id (here uses 0)
154 31 valid (use 1)
155
156 NV40:
157
158 15: 0 instance_addr >> 4 (maybe 19-0)
159 21:20 engine (here uses 1 = graphics)
160 I'm unsure about the other bits, but using 0 seems to work.
161
162 The key into the hash table depends on the object handle and channel id and
163 is given as:
164*/
Ben Skeggs6ee73862009-12-11 19:24:15 +1000165
166int
167nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
168 uint32_t size, int align, uint32_t flags,
169 struct nouveau_gpuobj **gpuobj_ret)
170{
171 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggse41115d2010-11-01 11:45:02 +1000172 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000173 struct nouveau_gpuobj *gpuobj;
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000174 struct drm_mm_node *ramin = NULL;
Ben Skeggse41115d2010-11-01 11:45:02 +1000175 int ret, i;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000176
177 NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n",
178 chan ? chan->id : -1, size, align, flags);
179
Ben Skeggs6ee73862009-12-11 19:24:15 +1000180 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
181 if (!gpuobj)
182 return -ENOMEM;
183 NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
Ben Skeggsb3beb162010-09-01 15:24:29 +1000184 gpuobj->dev = dev;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000185 gpuobj->flags = flags;
Ben Skeggseb9bcbd2010-09-01 15:24:37 +1000186 kref_init(&gpuobj->refcount);
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000187 gpuobj->size = size;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000188
Ben Skeggse05d7ea2010-09-01 15:24:38 +1000189 spin_lock(&dev_priv->ramin_lock);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000190 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
Ben Skeggse05d7ea2010-09-01 15:24:38 +1000191 spin_unlock(&dev_priv->ramin_lock);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000192
Ben Skeggs6ee73862009-12-11 19:24:15 +1000193 if (chan) {
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000194 ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0);
195 if (ramin)
196 ramin = drm_mm_get_block(ramin, size, align);
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000197 if (!ramin) {
198 nouveau_gpuobj_ref(NULL, &gpuobj);
199 return -ENOMEM;
200 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000201
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000202 gpuobj->pinst = chan->ramin->pinst;
203 if (gpuobj->pinst != ~0)
Ben Skeggse41115d2010-11-01 11:45:02 +1000204 gpuobj->pinst += ramin->start;
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000205
Francisco Jerezca130c22010-11-20 14:42:57 +0100206 gpuobj->cinst = ramin->start;
Ben Skeggse41115d2010-11-01 11:45:02 +1000207 gpuobj->vinst = ramin->start + chan->ramin->vinst;
208 gpuobj->node = ramin;
209 } else {
210 ret = instmem->get(gpuobj, size, align);
211 if (ret) {
212 nouveau_gpuobj_ref(NULL, &gpuobj);
213 return ret;
214 }
215
216 ret = -ENOSYS;
Ben Skeggsa11c3192010-08-27 10:00:25 +1000217 if (!(flags & NVOBJ_FLAG_DONT_MAP))
Ben Skeggse41115d2010-11-01 11:45:02 +1000218 ret = instmem->map(gpuobj);
219 if (ret)
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000220 gpuobj->pinst = ~0;
Ben Skeggse41115d2010-11-01 11:45:02 +1000221
222 gpuobj->cinst = NVOBJ_CINST_GLOBAL;
Ben Skeggsde3a6c02010-09-01 15:24:30 +1000223 }
224
Ben Skeggs6ee73862009-12-11 19:24:15 +1000225 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000226 for (i = 0; i < gpuobj->size; i += 4)
Ben Skeggsb3beb162010-09-01 15:24:29 +1000227 nv_wo32(gpuobj, i, 0);
Ben Skeggse41115d2010-11-01 11:45:02 +1000228 instmem->flush(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000229 }
230
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000231
Ben Skeggs6ee73862009-12-11 19:24:15 +1000232 *gpuobj_ret = gpuobj;
233 return 0;
234}
235
236int
Ben Skeggsfbd2895e2010-09-01 15:24:34 +1000237nouveau_gpuobj_init(struct drm_device *dev)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000238{
239 struct drm_nouveau_private *dev_priv = dev->dev_private;
240
241 NV_DEBUG(dev, "\n");
242
243 INIT_LIST_HEAD(&dev_priv->gpuobj_list);
Ben Skeggsbd2e5972010-10-19 20:06:01 +1000244 INIT_LIST_HEAD(&dev_priv->classes);
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000245 spin_lock_init(&dev_priv->ramin_lock);
246 dev_priv->ramin_base = ~0;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000247
248 return 0;
249}
250
Ben Skeggs6ee73862009-12-11 19:24:15 +1000251void
252nouveau_gpuobj_takedown(struct drm_device *dev)
253{
254 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggsb8c157d2010-10-20 10:39:35 +1000255 struct nouveau_gpuobj_method *om, *tm;
256 struct nouveau_gpuobj_class *oc, *tc;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000257
258 NV_DEBUG(dev, "\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000259
Ben Skeggsb8c157d2010-10-20 10:39:35 +1000260 list_for_each_entry_safe(oc, tc, &dev_priv->classes, head) {
261 list_for_each_entry_safe(om, tm, &oc->methods, head) {
262 list_del(&om->head);
263 kfree(om);
264 }
265 list_del(&oc->head);
266 kfree(oc);
267 }
268
Ben Skeggseb9bcbd2010-09-01 15:24:37 +1000269 BUG_ON(!list_empty(&dev_priv->gpuobj_list));
Ben Skeggs6ee73862009-12-11 19:24:15 +1000270}
271
Ben Skeggs185abec2010-09-01 15:24:39 +1000272
Ben Skeggseb9bcbd2010-09-01 15:24:37 +1000273static void
274nouveau_gpuobj_del(struct kref *ref)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000275{
Ben Skeggseb9bcbd2010-09-01 15:24:37 +1000276 struct nouveau_gpuobj *gpuobj =
277 container_of(ref, struct nouveau_gpuobj, refcount);
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000278 struct drm_device *dev = gpuobj->dev;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000279 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggse41115d2010-11-01 11:45:02 +1000280 struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000281 int i;
282
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000283 NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000284
Ben Skeggse41115d2010-11-01 11:45:02 +1000285 if (gpuobj->node && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000286 for (i = 0; i < gpuobj->size; i += 4)
Ben Skeggsb3beb162010-09-01 15:24:29 +1000287 nv_wo32(gpuobj, i, 0);
Ben Skeggse41115d2010-11-01 11:45:02 +1000288 instmem->flush(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000289 }
290
291 if (gpuobj->dtor)
292 gpuobj->dtor(dev, gpuobj);
293
Ben Skeggse41115d2010-11-01 11:45:02 +1000294 if (gpuobj->cinst == NVOBJ_CINST_GLOBAL) {
295 if (gpuobj->node) {
296 instmem->unmap(gpuobj);
297 instmem->put(gpuobj);
298 }
299 } else {
300 if (gpuobj->node) {
301 spin_lock(&dev_priv->ramin_lock);
302 drm_mm_put_block(gpuobj->node);
303 spin_unlock(&dev_priv->ramin_lock);
304 }
305 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000306
Ben Skeggse05d7ea2010-09-01 15:24:38 +1000307 spin_lock(&dev_priv->ramin_lock);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000308 list_del(&gpuobj->list);
Ben Skeggse05d7ea2010-09-01 15:24:38 +1000309 spin_unlock(&dev_priv->ramin_lock);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000310
Ben Skeggs6ee73862009-12-11 19:24:15 +1000311 kfree(gpuobj);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000312}
313
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000314void
315nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000316{
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000317 if (ref)
Ben Skeggseb9bcbd2010-09-01 15:24:37 +1000318 kref_get(&ref->refcount);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000319
Ben Skeggseb9bcbd2010-09-01 15:24:37 +1000320 if (*ptr)
321 kref_put(&(*ptr)->refcount, nouveau_gpuobj_del);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000322
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000323 *ptr = ref;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000324}
325
326int
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000327nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst,
328 u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000329{
330 struct drm_nouveau_private *dev_priv = dev->dev_private;
331 struct nouveau_gpuobj *gpuobj = NULL;
332 int i;
333
334 NV_DEBUG(dev,
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000335 "pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n",
336 pinst, vinst, size, flags);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000337
338 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
339 if (!gpuobj)
340 return -ENOMEM;
341 NV_DEBUG(dev, "gpuobj %p\n", gpuobj);
Ben Skeggsb3beb162010-09-01 15:24:29 +1000342 gpuobj->dev = dev;
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000343 gpuobj->flags = flags;
Ben Skeggseb9bcbd2010-09-01 15:24:37 +1000344 kref_init(&gpuobj->refcount);
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000345 gpuobj->size = size;
346 gpuobj->pinst = pinst;
Ben Skeggse41115d2010-11-01 11:45:02 +1000347 gpuobj->cinst = NVOBJ_CINST_GLOBAL;
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000348 gpuobj->vinst = vinst;
Ben Skeggsde3a6c02010-09-01 15:24:30 +1000349
Ben Skeggs6ee73862009-12-11 19:24:15 +1000350 if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000351 for (i = 0; i < gpuobj->size; i += 4)
Ben Skeggsb3beb162010-09-01 15:24:29 +1000352 nv_wo32(gpuobj, i, 0);
Ben Skeggsf56cb862010-07-08 11:29:10 +1000353 dev_priv->engine.instmem.flush(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000354 }
355
Ben Skeggse05d7ea2010-09-01 15:24:38 +1000356 spin_lock(&dev_priv->ramin_lock);
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000357 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
Ben Skeggse05d7ea2010-09-01 15:24:38 +1000358 spin_unlock(&dev_priv->ramin_lock);
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000359 *pgpuobj = gpuobj;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000360 return 0;
361}
362
363
364static uint32_t
365nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
366{
367 struct drm_nouveau_private *dev_priv = dev->dev_private;
368
369 /*XXX: dodgy hack for now */
370 if (dev_priv->card_type >= NV_50)
371 return 24;
372 if (dev_priv->card_type >= NV_40)
373 return 32;
374 return 16;
375}
376
377/*
378 DMA objects are used to reference a piece of memory in the
379 framebuffer, PCI or AGP address space. Each object is 16 bytes big
380 and looks as follows:
381
382 entry[0]
383 11:0 class (seems like I can always use 0 here)
384 12 page table present?
385 13 page entry linear?
386 15:14 access: 0 rw, 1 ro, 2 wo
387 17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
388 31:20 dma adjust (bits 0-11 of the address)
389 entry[1]
390 dma limit (size of transfer)
391 entry[X]
392 1 0 readonly, 1 readwrite
393 31:12 dma frame address of the page (bits 12-31 of the address)
394 entry[N]
395 page table terminator, same value as the first pte, as does nvidia
396 rivatv uses 0xffffffff
397
398 Non linear page tables need a list of frame addresses afterwards,
399 the rivatv project has some info on this.
400
401 The method below creates a DMA object in instance RAM and returns a handle
402 to it that can be used to set up context objects.
403*/
Ben Skeggs6ee73862009-12-11 19:24:15 +1000404
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000405void
406nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class,
407 u64 base, u64 size, int target, int access,
408 u32 type, u32 comp)
409{
410 struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
411 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
412 u32 flags0;
413
414 flags0 = (comp << 29) | (type << 22) | class;
415 flags0 |= 0x00100000;
416
417 switch (access) {
418 case NV_MEM_ACCESS_RO: flags0 |= 0x00040000; break;
419 case NV_MEM_ACCESS_RW:
420 case NV_MEM_ACCESS_WO: flags0 |= 0x00080000; break;
421 default:
422 break;
423 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000424
425 switch (target) {
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000426 case NV_MEM_TARGET_VRAM:
427 flags0 |= 0x00010000;
428 break;
429 case NV_MEM_TARGET_PCI:
430 flags0 |= 0x00020000;
431 break;
432 case NV_MEM_TARGET_PCI_NOSNOOP:
433 flags0 |= 0x00030000;
434 break;
435 case NV_MEM_TARGET_GART:
Ben Skeggsb571fe22010-11-16 10:13:05 +1000436 base += dev_priv->gart_info.aper_base;
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000437 default:
438 flags0 &= ~0x00100000;
439 break;
440 }
441
442 /* convert to base + limit */
443 size = (base + size) - 1;
444
445 nv_wo32(obj, offset + 0x00, flags0);
446 nv_wo32(obj, offset + 0x04, lower_32_bits(size));
447 nv_wo32(obj, offset + 0x08, lower_32_bits(base));
448 nv_wo32(obj, offset + 0x0c, upper_32_bits(size) << 24 |
449 upper_32_bits(base));
450 nv_wo32(obj, offset + 0x10, 0x00000000);
451 nv_wo32(obj, offset + 0x14, 0x00000000);
452
453 pinstmem->flush(obj->dev);
454}
455
456int
457nv50_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base, u64 size,
458 int target, int access, u32 type, u32 comp,
459 struct nouveau_gpuobj **pobj)
460{
461 struct drm_device *dev = chan->dev;
462 int ret;
463
Ben Skeggsa0fd9b92010-11-26 10:32:22 +1000464 ret = nouveau_gpuobj_new(dev, chan, 24, 16, NVOBJ_FLAG_ZERO_FREE, pobj);
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000465 if (ret)
466 return ret;
467
468 nv50_gpuobj_dma_init(*pobj, 0, class, base, size, target,
469 access, type, comp);
470 return 0;
471}
472
473int
474nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
475 u64 size, int access, int target,
476 struct nouveau_gpuobj **pobj)
477{
478 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
479 struct drm_device *dev = chan->dev;
480 struct nouveau_gpuobj *obj;
Francisco Jerezfd70b6c2010-12-08 02:37:12 +0100481 u32 flags0, flags2;
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000482 int ret;
483
484 if (dev_priv->card_type >= NV_50) {
485 u32 comp = (target == NV_MEM_TARGET_VM) ? NV_MEM_COMP_VM : 0;
486 u32 type = (target == NV_MEM_TARGET_VM) ? NV_MEM_TYPE_VM : 0;
487
488 return nv50_gpuobj_dma_new(chan, class, base, size,
489 target, access, type, comp, pobj);
490 }
491
492 if (target == NV_MEM_TARGET_GART) {
493 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
494 target = NV_MEM_TARGET_PCI_NOSNOOP;
495 base += dev_priv->gart_info.aper_base;
496 } else
497 if (base != 0) {
Francisco Jerezfd70b6c2010-12-08 02:37:12 +0100498 base = nouveau_sgdma_get_physical(dev, base);
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000499 target = NV_MEM_TARGET_PCI;
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000500 } else {
501 nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, pobj);
502 return 0;
503 }
504 }
505
506 flags0 = class;
507 flags0 |= 0x00003000; /* PT present, PT linear */
508 flags2 = 0;
509
510 switch (target) {
511 case NV_MEM_TARGET_PCI:
512 flags0 |= 0x00020000;
513 break;
514 case NV_MEM_TARGET_PCI_NOSNOOP:
515 flags0 |= 0x00030000;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000516 break;
517 default:
518 break;
519 }
520
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000521 switch (access) {
522 case NV_MEM_ACCESS_RO:
523 flags0 |= 0x00004000;
524 break;
525 case NV_MEM_ACCESS_WO:
526 flags0 |= 0x00008000;
527 default:
528 flags2 |= 0x00000002;
529 break;
530 }
531
532 flags0 |= (base & 0x00000fff) << 20;
533 flags2 |= (base & 0xfffff000);
534
Ben Skeggsa0fd9b92010-11-26 10:32:22 +1000535 ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000536 if (ret)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000537 return ret;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000538
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000539 nv_wo32(obj, 0x00, flags0);
540 nv_wo32(obj, 0x04, size - 1);
541 nv_wo32(obj, 0x08, flags2);
542 nv_wo32(obj, 0x0c, flags2);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000543
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000544 obj->engine = NVOBJ_ENGINE_SW;
545 obj->class = class;
546 *pobj = obj;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000547 return 0;
548}
549
Ben Skeggs6ee73862009-12-11 19:24:15 +1000550/* Context objects in the instance RAM have the following structure.
551 * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
552
553 NV4 - NV30:
554
555 entry[0]
556 11:0 class
557 12 chroma key enable
558 13 user clip enable
559 14 swizzle enable
560 17:15 patch config:
561 scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
562 18 synchronize enable
563 19 endian: 1 big, 0 little
564 21:20 dither mode
565 23 single step enable
566 24 patch status: 0 invalid, 1 valid
567 25 context_surface 0: 1 valid
568 26 context surface 1: 1 valid
569 27 context pattern: 1 valid
570 28 context rop: 1 valid
571 29,30 context beta, beta4
572 entry[1]
573 7:0 mono format
574 15:8 color format
575 31:16 notify instance address
576 entry[2]
577 15:0 dma 0 instance address
578 31:16 dma 1 instance address
579 entry[3]
580 dma method traps
581
582 NV40:
583 No idea what the exact format is. Here's what can be deducted:
584
585 entry[0]:
586 11:0 class (maybe uses more bits here?)
587 17 user clip enable
588 21:19 patch config
589 25 patch status valid ?
590 entry[1]:
591 15:0 DMA notifier (maybe 20:0)
592 entry[2]:
593 15:0 DMA 0 instance (maybe 20:0)
594 24 big endian
595 entry[3]:
596 15:0 DMA 1 instance (maybe 20:0)
597 entry[4]:
598 entry[5]:
599 set to 0?
600*/
Ben Skeggsa6a1a382010-10-19 19:57:34 +1000601static int
602nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
603 struct nouveau_gpuobj **gpuobj_ret)
604{
Ben Skeggsceac3092010-11-23 10:10:24 +1000605 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
Ben Skeggsa6a1a382010-10-19 19:57:34 +1000606 struct nouveau_gpuobj *gpuobj;
607
Ben Skeggsa6a1a382010-10-19 19:57:34 +1000608 gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
609 if (!gpuobj)
610 return -ENOMEM;
611 gpuobj->dev = chan->dev;
612 gpuobj->engine = NVOBJ_ENGINE_SW;
613 gpuobj->class = class;
614 kref_init(&gpuobj->refcount);
615 gpuobj->cinst = 0x40;
616
617 spin_lock(&dev_priv->ramin_lock);
618 list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
619 spin_unlock(&dev_priv->ramin_lock);
620 *gpuobj_ret = gpuobj;
621 return 0;
622}
623
Ben Skeggs6ee73862009-12-11 19:24:15 +1000624int
Ben Skeggsceac3092010-11-23 10:10:24 +1000625nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000626{
Ben Skeggsa6a1a382010-10-19 19:57:34 +1000627 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000628 struct drm_device *dev = chan->dev;
Ben Skeggsb8c157d2010-10-20 10:39:35 +1000629 struct nouveau_gpuobj_class *oc;
Ben Skeggsceac3092010-11-23 10:10:24 +1000630 struct nouveau_gpuobj *gpuobj;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000631 int ret;
632
633 NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
634
Ben Skeggsb8c157d2010-10-20 10:39:35 +1000635 list_for_each_entry(oc, &dev_priv->classes, head) {
636 if (oc->id == class)
637 goto found;
Ben Skeggsa6a1a382010-10-19 19:57:34 +1000638 }
639
Ben Skeggsb8c157d2010-10-20 10:39:35 +1000640 NV_ERROR(dev, "illegal object class: 0x%x\n", class);
641 return -EINVAL;
Ben Skeggsa6a1a382010-10-19 19:57:34 +1000642
Ben Skeggsb8c157d2010-10-20 10:39:35 +1000643found:
Ben Skeggsf4512e62010-10-20 11:47:09 +1000644 switch (oc->engine) {
Ben Skeggsceac3092010-11-23 10:10:24 +1000645 case NVOBJ_ENGINE_SW:
646 ret = nouveau_gpuobj_sw_new(chan, class, &gpuobj);
647 if (ret)
648 return ret;
649 goto insert;
Ben Skeggsf4512e62010-10-20 11:47:09 +1000650 case NVOBJ_ENGINE_GR:
651 if (dev_priv->card_type >= NV_50 && !chan->ramin_grctx) {
652 struct nouveau_pgraph_engine *pgraph =
653 &dev_priv->engine.graph;
654
655 ret = pgraph->create_context(chan);
656 if (ret)
657 return ret;
658 }
659 break;
660 case NVOBJ_ENGINE_CRYPT:
661 if (!chan->crypt_ctx) {
662 struct nouveau_crypt_engine *pcrypt =
663 &dev_priv->engine.crypt;
664
665 ret = pcrypt->create_context(chan);
666 if (ret)
667 return ret;
668 }
669 break;
670 }
671
Ben Skeggs6ee73862009-12-11 19:24:15 +1000672 ret = nouveau_gpuobj_new(dev, chan,
673 nouveau_gpuobj_class_instmem_size(dev, class),
674 16,
675 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
Ben Skeggsceac3092010-11-23 10:10:24 +1000676 &gpuobj);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000677 if (ret) {
Ben Skeggsa6a1a382010-10-19 19:57:34 +1000678 NV_ERROR(dev, "error creating gpuobj: %d\n", ret);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000679 return ret;
680 }
681
Ben Skeggs6ee73862009-12-11 19:24:15 +1000682 if (dev_priv->card_type >= NV_50) {
Ben Skeggsceac3092010-11-23 10:10:24 +1000683 nv_wo32(gpuobj, 0, class);
684 nv_wo32(gpuobj, 20, 0x00010000);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000685 } else {
686 switch (class) {
687 case NV_CLASS_NULL:
Ben Skeggsceac3092010-11-23 10:10:24 +1000688 nv_wo32(gpuobj, 0, 0x00001030);
689 nv_wo32(gpuobj, 4, 0xFFFFFFFF);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000690 break;
691 default:
692 if (dev_priv->card_type >= NV_40) {
Ben Skeggsceac3092010-11-23 10:10:24 +1000693 nv_wo32(gpuobj, 0, class);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000694#ifdef __BIG_ENDIAN
Ben Skeggsceac3092010-11-23 10:10:24 +1000695 nv_wo32(gpuobj, 8, 0x01000000);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000696#endif
697 } else {
698#ifdef __BIG_ENDIAN
Ben Skeggsceac3092010-11-23 10:10:24 +1000699 nv_wo32(gpuobj, 0, class | 0x00080000);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000700#else
Ben Skeggsceac3092010-11-23 10:10:24 +1000701 nv_wo32(gpuobj, 0, class);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000702#endif
703 }
704 }
705 }
Ben Skeggsf56cb862010-07-08 11:29:10 +1000706 dev_priv->engine.instmem.flush(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000707
Ben Skeggsceac3092010-11-23 10:10:24 +1000708 gpuobj->engine = oc->engine;
709 gpuobj->class = oc->id;
710
711insert:
712 ret = nouveau_ramht_insert(chan, handle, gpuobj);
713 if (ret)
714 NV_ERROR(dev, "error adding gpuobj to RAMHT: %d\n", ret);
715 nouveau_gpuobj_ref(NULL, &gpuobj);
716 return ret;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000717}
718
Ben Skeggs6ee73862009-12-11 19:24:15 +1000719static int
720nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
721{
722 struct drm_device *dev = chan->dev;
723 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000724 uint32_t size;
725 uint32_t base;
726 int ret;
727
728 NV_DEBUG(dev, "ch%d\n", chan->id);
729
730 /* Base amount for object storage (4KiB enough?) */
Ben Skeggsbd2e5972010-10-19 20:06:01 +1000731 size = 0x2000;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000732 base = 0;
733
734 /* PGRAPH context */
Ben Skeggs816544b2010-07-08 13:15:05 +1000735 size += dev_priv->engine.graph.grctx_size;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000736
737 if (dev_priv->card_type == NV_50) {
738 /* Various fixed table thingos */
739 size += 0x1400; /* mostly unknown stuff */
740 size += 0x4000; /* vm pd */
741 base = 0x6000;
742 /* RAMHT, not sure about setting size yet, 32KiB to be safe */
743 size += 0x8000;
744 /* RAMFC */
745 size += 0x1000;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000746 }
747
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000748 ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000749 if (ret) {
750 NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret);
751 return ret;
752 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000753
Ben Skeggsde3a6c02010-09-01 15:24:30 +1000754 ret = drm_mm_init(&chan->ramin_heap, base, size);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000755 if (ret) {
756 NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret);
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000757 nouveau_gpuobj_ref(NULL, &chan->ramin);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000758 return ret;
759 }
760
761 return 0;
762}
763
764int
765nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
766 uint32_t vram_h, uint32_t tt_h)
767{
768 struct drm_device *dev = chan->dev;
769 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000770 struct nouveau_gpuobj *vram = NULL, *tt = NULL;
Ben Skeggs4c1361422010-11-15 11:54:21 +1000771 int ret;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000772
Ben Skeggs6ee73862009-12-11 19:24:15 +1000773 NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
774
Ben Skeggs816544b2010-07-08 13:15:05 +1000775 /* Allocate a chunk of memory for per-channel object storage */
776 ret = nouveau_gpuobj_channel_init_pramin(chan);
777 if (ret) {
778 NV_ERROR(dev, "init pramin\n");
779 return ret;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000780 }
781
Ben Skeggs4c1361422010-11-15 11:54:21 +1000782 /* NV50/NVC0 VM
Ben Skeggs6ee73862009-12-11 19:24:15 +1000783 * - Allocate per-channel page-directory
Ben Skeggs4c1361422010-11-15 11:54:21 +1000784 * - Link with shared channel VM
Ben Skeggs6ee73862009-12-11 19:24:15 +1000785 */
Ben Skeggs4c1361422010-11-15 11:54:21 +1000786 if (dev_priv->chan_vm) {
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000787 u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200;
788 u64 vm_vinst = chan->ramin->vinst + pgd_offs;
789 u32 vm_pinst = chan->ramin->pinst;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000790
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000791 if (vm_pinst != ~0)
792 vm_pinst += pgd_offs;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000793
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000794 ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000,
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000795 0, &chan->vm_pd);
Ben Skeggsf56cb862010-07-08 11:29:10 +1000796 if (ret)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000797 return ret;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000798
Ben Skeggs4c1361422010-11-15 11:54:21 +1000799 nouveau_vm_ref(dev_priv->chan_vm, &chan->vm, chan->vm_pd);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000800 }
801
802 /* RAMHT */
803 if (dev_priv->card_type < NV_50) {
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000804 nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL);
805 } else {
806 struct nouveau_gpuobj *ramht = NULL;
807
808 ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16,
809 NVOBJ_FLAG_ZERO_ALLOC, &ramht);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000810 if (ret)
811 return ret;
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000812
813 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
814 nouveau_gpuobj_ref(NULL, &ramht);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000815 if (ret)
816 return ret;
817 }
818
819 /* VRAM ctxdma */
820 if (dev_priv->card_type >= NV_50) {
821 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
Ben Skeggs4c1361422010-11-15 11:54:21 +1000822 0, (1ULL << 40), NV_MEM_ACCESS_RW,
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000823 NV_MEM_TARGET_VM, &vram);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000824 if (ret) {
825 NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
826 return ret;
827 }
828 } else {
829 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000830 0, dev_priv->fb_available_size,
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000831 NV_MEM_ACCESS_RW,
832 NV_MEM_TARGET_VRAM, &vram);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000833 if (ret) {
834 NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
835 return ret;
836 }
837 }
838
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000839 ret = nouveau_ramht_insert(chan, vram_h, vram);
840 nouveau_gpuobj_ref(NULL, &vram);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000841 if (ret) {
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000842 NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000843 return ret;
844 }
845
846 /* TT memory ctxdma */
847 if (dev_priv->card_type >= NV_50) {
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000848 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
Ben Skeggs4c1361422010-11-15 11:54:21 +1000849 0, (1ULL << 40), NV_MEM_ACCESS_RW,
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000850 NV_MEM_TARGET_VM, &tt);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000851 } else {
Ben Skeggs7f4a1952010-11-16 11:50:09 +1000852 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
853 0, dev_priv->gart_info.aper_size,
854 NV_MEM_ACCESS_RW,
855 NV_MEM_TARGET_GART, &tt);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000856 }
857
858 if (ret) {
859 NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
860 return ret;
861 }
862
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000863 ret = nouveau_ramht_insert(chan, tt_h, tt);
864 nouveau_gpuobj_ref(NULL, &tt);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000865 if (ret) {
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000866 NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000867 return ret;
868 }
869
870 return 0;
871}
872
873void
874nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
875{
Ben Skeggs6ee73862009-12-11 19:24:15 +1000876 struct drm_device *dev = chan->dev;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000877
878 NV_DEBUG(dev, "ch%d\n", chan->id);
879
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000880 if (!chan->ramht)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000881 return;
882
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000883 nouveau_ramht_ref(NULL, &chan->ramht, chan);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000884
Ben Skeggs4c1361422010-11-15 11:54:21 +1000885 nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000886 nouveau_gpuobj_ref(NULL, &chan->vm_pd);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000887
Ben Skeggsb833ac22010-06-01 15:32:24 +1000888 if (chan->ramin_heap.free_stack.next)
889 drm_mm_takedown(&chan->ramin_heap);
Ben Skeggsa8eaebc2010-09-01 15:24:31 +1000890 nouveau_gpuobj_ref(NULL, &chan->ramin);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000891}
892
893int
894nouveau_gpuobj_suspend(struct drm_device *dev)
895{
896 struct drm_nouveau_private *dev_priv = dev->dev_private;
897 struct nouveau_gpuobj *gpuobj;
898 int i;
899
Ben Skeggs6ee73862009-12-11 19:24:15 +1000900 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
Ben Skeggse41115d2010-11-01 11:45:02 +1000901 if (gpuobj->cinst != NVOBJ_CINST_GLOBAL)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000902 continue;
903
Ben Skeggsdc1e5c02010-10-25 15:23:59 +1000904 gpuobj->suspend = vmalloc(gpuobj->size);
905 if (!gpuobj->suspend) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000906 nouveau_gpuobj_resume(dev);
907 return -ENOMEM;
908 }
909
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000910 for (i = 0; i < gpuobj->size; i += 4)
Ben Skeggsdc1e5c02010-10-25 15:23:59 +1000911 gpuobj->suspend[i/4] = nv_ro32(gpuobj, i);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000912 }
913
914 return 0;
915}
916
917void
Ben Skeggs6ee73862009-12-11 19:24:15 +1000918nouveau_gpuobj_resume(struct drm_device *dev)
919{
920 struct drm_nouveau_private *dev_priv = dev->dev_private;
921 struct nouveau_gpuobj *gpuobj;
922 int i;
923
Ben Skeggs6ee73862009-12-11 19:24:15 +1000924 list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) {
Ben Skeggsdc1e5c02010-10-25 15:23:59 +1000925 if (!gpuobj->suspend)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000926 continue;
927
Ben Skeggs43efc9c2010-09-01 15:24:32 +1000928 for (i = 0; i < gpuobj->size; i += 4)
Ben Skeggsdc1e5c02010-10-25 15:23:59 +1000929 nv_wo32(gpuobj, i, gpuobj->suspend[i/4]);
930
931 vfree(gpuobj->suspend);
932 gpuobj->suspend = NULL;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000933 }
934
Ben Skeggsdc1e5c02010-10-25 15:23:59 +1000935 dev_priv->engine.instmem.flush(dev);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000936}
937
938int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
939 struct drm_file *file_priv)
940{
Ben Skeggs6ee73862009-12-11 19:24:15 +1000941 struct drm_nouveau_grobj_alloc *init = data;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000942 struct nouveau_channel *chan;
943 int ret;
944
Ben Skeggs6ee73862009-12-11 19:24:15 +1000945 if (init->handle == ~0)
946 return -EINVAL;
947
Ben Skeggscff5c132010-10-06 16:16:59 +1000948 chan = nouveau_channel_get(dev, file_priv, init->channel);
949 if (IS_ERR(chan))
950 return PTR_ERR(chan);
951
952 if (nouveau_ramht_find(chan, init->handle)) {
953 ret = -EEXIST;
954 goto out;
955 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000956
Ben Skeggsceac3092010-11-23 10:10:24 +1000957 ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000958 if (ret) {
959 NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
960 ret, init->channel, init->handle);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000961 }
962
Ben Skeggscff5c132010-10-06 16:16:59 +1000963out:
964 nouveau_channel_put(&chan);
965 return ret;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000966}
967
968int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
969 struct drm_file *file_priv)
970{
971 struct drm_nouveau_gpuobj_free *objfree = data;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000972 struct nouveau_channel *chan;
Ben Skeggs18a16a72010-10-12 10:11:00 +1000973 int ret;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000974
Ben Skeggscff5c132010-10-06 16:16:59 +1000975 chan = nouveau_channel_get(dev, file_priv, objfree->channel);
976 if (IS_ERR(chan))
977 return PTR_ERR(chan);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000978
Francisco Jerez6dccd312010-11-18 23:57:46 +0100979 /* Synchronize with the user channel */
980 nouveau_channel_idle(chan);
981
Ben Skeggs18a16a72010-10-12 10:11:00 +1000982 ret = nouveau_ramht_remove(chan, objfree->handle);
Ben Skeggscff5c132010-10-06 16:16:59 +1000983 nouveau_channel_put(&chan);
984 return ret;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000985}
Ben Skeggsb3beb162010-09-01 15:24:29 +1000986
987u32
988nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
989{
Ben Skeggs5125bfd2010-09-01 15:24:33 +1000990 struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
991 struct drm_device *dev = gpuobj->dev;
992
993 if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
994 u64 ptr = gpuobj->vinst + offset;
995 u32 base = ptr >> 16;
996 u32 val;
997
998 spin_lock(&dev_priv->ramin_lock);
999 if (dev_priv->ramin_base != base) {
1000 dev_priv->ramin_base = base;
1001 nv_wr32(dev, 0x001700, dev_priv->ramin_base);
1002 }
1003 val = nv_rd32(dev, 0x700000 + (ptr & 0xffff));
1004 spin_unlock(&dev_priv->ramin_lock);
1005 return val;
1006 }
1007
1008 return nv_ri32(dev, gpuobj->pinst + offset);
Ben Skeggsb3beb162010-09-01 15:24:29 +10001009}
1010
1011void
1012nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)
1013{
Ben Skeggs5125bfd2010-09-01 15:24:33 +10001014 struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
1015 struct drm_device *dev = gpuobj->dev;
1016
1017 if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
1018 u64 ptr = gpuobj->vinst + offset;
1019 u32 base = ptr >> 16;
1020
1021 spin_lock(&dev_priv->ramin_lock);
1022 if (dev_priv->ramin_base != base) {
1023 dev_priv->ramin_base = base;
1024 nv_wr32(dev, 0x001700, dev_priv->ramin_base);
1025 }
1026 nv_wr32(dev, 0x700000 + (ptr & 0xffff), val);
1027 spin_unlock(&dev_priv->ramin_lock);
1028 return;
1029 }
1030
1031 nv_wi32(dev, gpuobj->pinst + offset, val);
Ben Skeggsb3beb162010-09-01 15:24:29 +10001032}