| Carlo Caione | 7a29a86 | 2015-06-01 13:13:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Meson8b clock tree IDs |
| 3 | */ |
| 4 | |
| 5 | #ifndef __MESON8B_CLKC_H |
| 6 | #define __MESON8B_CLKC_H |
| 7 | |
| 8 | #define CLKID_UNUSED 0 |
| 9 | #define CLKID_XTAL 1 |
| 10 | #define CLKID_PLL_FIXED 2 |
| 11 | #define CLKID_PLL_VID 3 |
| 12 | #define CLKID_PLL_SYS 4 |
| 13 | #define CLKID_FCLK_DIV2 5 |
| 14 | #define CLKID_FCLK_DIV3 6 |
| 15 | #define CLKID_FCLK_DIV4 7 |
| 16 | #define CLKID_FCLK_DIV5 8 |
| 17 | #define CLKID_FCLK_DIV7 9 |
| 18 | #define CLKID_CLK81 10 |
| 19 | #define CLKID_MALI 11 |
| 20 | #define CLKID_CPUCLK 12 |
| 21 | #define CLKID_ZERO 13 |
| Michael Turquette | c0daa3e | 2016-04-28 12:01:51 -0700 | [diff] [blame] | 22 | #define CLKID_MPEG_SEL 14 |
| 23 | #define CLKID_MPEG_DIV 15 |
| Martin Blumenstingl | 70ad0d0 | 2017-06-11 12:16:32 +0200 | [diff] [blame] | 24 | #define CLKID_SAR_ADC 23 |
| Martin Blumenstingl | 06eff6a | 2017-06-11 12:16:34 +0200 | [diff] [blame] | 25 | #define CLKID_RNG0 25 |
| Martin Blumenstingl | e2e5f32 | 2017-06-11 12:16:33 +0200 | [diff] [blame] | 26 | #define CLKID_SDIO 30 |
| Martin Blumenstingl | c22f06d | 2017-06-11 12:16:36 +0200 | [diff] [blame] | 27 | #define CLKID_ETH 36 |
| Martin Blumenstingl | 677f6af | 2017-06-11 12:16:35 +0200 | [diff] [blame] | 28 | #define CLKID_USB0 50 |
| 29 | #define CLKID_USB1 51 |
| 30 | #define CLKID_USB 55 |
| 31 | #define CLKID_USB1_DDR_BRIDGE 64 |
| 32 | #define CLKID_USB0_DDR_BRIDGE 65 |
| Martin Blumenstingl | 70ad0d0 | 2017-06-11 12:16:32 +0200 | [diff] [blame] | 33 | #define CLKID_SANA 69 |
| Carlo Caione | 7a29a86 | 2015-06-01 13:13:53 +0200 | [diff] [blame] | 34 | |
| Carlo Caione | 7a29a86 | 2015-06-01 13:13:53 +0200 | [diff] [blame] | 35 | #endif /* __MESON8B_CLKC_H */ |