| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 1 | # |
| 2 | # DMA engine configuration for dw |
| 3 | # |
| 4 | |
| Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 5 | config DW_DMAC_CORE |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 6 | tristate "Synopsys DesignWare AHB DMA support" |
| 7 | depends on GENERIC_HARDIRQS |
| 8 | select DMA_ENGINE |
| Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 9 | |
| 10 | config DW_DMAC |
| 11 | tristate "Synopsys DesignWare AHB DMA platform driver" |
| 12 | select DW_DMAC_CORE |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 13 | default y if CPU_AT32AP7000 |
| 14 | help |
| 15 | Support the Synopsys DesignWare AHB DMA controller. This |
| 16 | can be integrated in chips such as the Atmel AT32ap7000. |
| 17 | |
| Andy Shevchenko | fed42c1 | 2013-06-05 15:26:46 +0300 | [diff] [blame^] | 18 | config DW_DMAC_PCI |
| 19 | tristate "Synopsys DesignWare AHB DMA PCI driver" |
| 20 | depends on PCI |
| 21 | select DW_DMAC_CORE |
| 22 | help |
| 23 | Support the Synopsys DesignWare AHB DMA controller on the |
| 24 | platfroms that enumerate it as a PCI device. For example, |
| 25 | Intel Medfield has integrated this GPDMA controller. |
| 26 | |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 27 | config DW_DMAC_BIG_ENDIAN_IO |
| 28 | bool "Use big endian I/O register access" |
| 29 | default y if AVR32 |
| Andy Shevchenko | 9cade1a | 2013-06-05 15:26:45 +0300 | [diff] [blame] | 30 | depends on DW_DMAC_CORE |
| Andy Shevchenko | 61a7649 | 2013-06-05 15:26:44 +0300 | [diff] [blame] | 31 | help |
| 32 | Say yes here to use big endian I/O access when reading and writing |
| 33 | to the DMA controller registers. This is needed on some platforms, |
| 34 | like the Atmel AVR32 architecture. |
| 35 | |
| 36 | If unsure, use the default setting. |