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gerrit-public.fairphone.software / kernel / msm-5.4 / ff4ae5d9319b86f940e410e92659c50f9879ff46 / . / arch / arm / mach-omap2 / cm3xxx.c
blob: 8f92c56e225441187e4743cdbed324c4ac4cb325 [file] [log] [blame]
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]1/*
2 * OMAP2/3 CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]5 * Copyright (C) 2012 Texas Instruments, Inc.
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]14#include <linux/types.h>
15#include <linux/delay.h>
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/io.h>
19
Tony Lindgrendbc04162012-08-31 10:59:07 -0700[diff] [blame]20#include "soc.h"
Tony Lindgrenee0839c2012-02-24 10:34:35 -0800[diff] [blame]21#include "iomap.h"
Tony Lindgren4e653312011-11-10 22:45:17 +0100[diff] [blame]22#include "common.h"
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]23#include "cm.h"
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]24#include "cm3xxx.h"
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]25#include "cm-regbits-34xx.h"
26
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]27static const u8 omap3xxx_cm_idlest_offs[] = {
28 CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]29};
30
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]31/*
32 *
33 */
34
35static void _write_clktrctrl(u8 c, s16 module, u32 mask)
36{
37 u32 v;
38
39 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
40 v &= ~mask;
41 v |= c << __ffs(mask);
42 omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
43}
44
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]45bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]46{
47 u32 v;
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]48
49 v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
50 v &= mask;
51 v >>= __ffs(mask);
52
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]53 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]54}
55
56void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
57{
58 _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
59}
60
61void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
62{
63 _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
64}
65
66void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
67{
68 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
69}
70
71void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
72{
73 _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
74}
75
Paul Walmsley0fd0c212011-02-25 15:49:53 -0700[diff] [blame]76/*
Paul Walmsley55ae3502010-12-21 21:05:15 -0700[diff] [blame]77 *
78 */
79
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]80/**
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]81 * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]82 * @prcm_mod: PRCM module offset
83 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
84 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
85 *
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]86 * Wait for the PRCM to indicate that the module identified by
87 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon
88 * success or -EBUSY if the module doesn't enable in time.
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]89 */
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]90int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]91{
92 int ena = 0, i = 0;
93 u8 cm_idlest_reg;
94 u32 mask;
95
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]96 if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]97 return -EINVAL;
98
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]99 cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]100
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]101 mask = 1 << idlest_shift;
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]102 ena = 0;
Kevin Hilman64056162010-07-26 16:34:28 -0600[diff] [blame]103
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -0600[diff] [blame^]104 omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
105 mask) == ena), MAX_MODULE_READY_TIME, i);
Paul Walmsley71348bc2009-09-03 20:14:02 +0300[diff] [blame]106
107 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
108}
109
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]110/*
111 * Context save/restore code - OMAP3 only
112 */
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]113struct omap3_cm_regs {
114 u32 iva2_cm_clksel1;
115 u32 iva2_cm_clksel2;
116 u32 cm_sysconfig;
117 u32 sgx_cm_clksel;
118 u32 dss_cm_clksel;
119 u32 cam_cm_clksel;
120 u32 per_cm_clksel;
121 u32 emu_cm_clksel;
122 u32 emu_cm_clkstctrl;
Eduardo Valentina8ae6452011-04-13 18:21:07 +0300[diff] [blame]123 u32 pll_cm_autoidle;
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]124 u32 pll_cm_autoidle2;
125 u32 pll_cm_clksel4;
126 u32 pll_cm_clksel5;
127 u32 pll_cm_clken2;
128 u32 cm_polctrl;
129 u32 iva2_cm_fclken;
130 u32 iva2_cm_clken_pll;
131 u32 core_cm_fclken1;
132 u32 core_cm_fclken3;
133 u32 sgx_cm_fclken;
134 u32 wkup_cm_fclken;
135 u32 dss_cm_fclken;
136 u32 cam_cm_fclken;
137 u32 per_cm_fclken;
138 u32 usbhost_cm_fclken;
139 u32 core_cm_iclken1;
140 u32 core_cm_iclken2;
141 u32 core_cm_iclken3;
142 u32 sgx_cm_iclken;
143 u32 wkup_cm_iclken;
144 u32 dss_cm_iclken;
145 u32 cam_cm_iclken;
146 u32 per_cm_iclken;
147 u32 usbhost_cm_iclken;
148 u32 iva2_cm_autoidle2;
149 u32 mpu_cm_autoidle2;
150 u32 iva2_cm_clkstctrl;
151 u32 mpu_cm_clkstctrl;
152 u32 core_cm_clkstctrl;
153 u32 sgx_cm_clkstctrl;
154 u32 dss_cm_clkstctrl;
155 u32 cam_cm_clkstctrl;
156 u32 per_cm_clkstctrl;
157 u32 neon_cm_clkstctrl;
158 u32 usbhost_cm_clkstctrl;
159 u32 core_cm_autoidle1;
160 u32 core_cm_autoidle2;
161 u32 core_cm_autoidle3;
162 u32 wkup_cm_autoidle;
163 u32 dss_cm_autoidle;
164 u32 cam_cm_autoidle;
165 u32 per_cm_autoidle;
166 u32 usbhost_cm_autoidle;
167 u32 sgx_cm_sleepdep;
168 u32 dss_cm_sleepdep;
169 u32 cam_cm_sleepdep;
170 u32 per_cm_sleepdep;
171 u32 usbhost_cm_sleepdep;
172 u32 cm_clkout_ctrl;
173};
174
175static struct omap3_cm_regs cm_context;
176
177void omap3_cm_save_context(void)
178{
179 cm_context.iva2_cm_clksel1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]180 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]181 cm_context.iva2_cm_clksel2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]182 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]183 cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
184 cm_context.sgx_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]185 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]186 cm_context.dss_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]187 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]188 cm_context.cam_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]189 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]190 cm_context.per_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]191 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]192 cm_context.emu_cm_clksel =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]193 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]194 cm_context.emu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]195 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
Eduardo Valentina8ae6452011-04-13 18:21:07 +0300[diff] [blame]196 /*
197 * As per erratum i671, ROM code does not respect the PER DPLL
198 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
199 * In this case, even though this register has been saved in
200 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
201 * by ourselves. So, we need to save it anyway.
202 */
203 cm_context.pll_cm_autoidle =
204 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]205 cm_context.pll_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]206 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]207 cm_context.pll_cm_clksel4 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]208 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]209 cm_context.pll_cm_clksel5 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]210 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]211 cm_context.pll_cm_clken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]212 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]213 cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
214 cm_context.iva2_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]215 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
216 cm_context.iva2_cm_clken_pll =
217 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]218 cm_context.core_cm_fclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]219 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]220 cm_context.core_cm_fclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]221 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]222 cm_context.sgx_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]223 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]224 cm_context.wkup_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]225 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]226 cm_context.dss_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]227 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]228 cm_context.cam_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]229 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]230 cm_context.per_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]231 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]232 cm_context.usbhost_cm_fclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]233 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]234 cm_context.core_cm_iclken1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]235 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]236 cm_context.core_cm_iclken2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]237 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]238 cm_context.core_cm_iclken3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]239 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]240 cm_context.sgx_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]241 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]242 cm_context.wkup_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]243 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]244 cm_context.dss_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]245 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]246 cm_context.cam_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]247 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]248 cm_context.per_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]249 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]250 cm_context.usbhost_cm_iclken =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]251 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]252 cm_context.iva2_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]253 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]254 cm_context.mpu_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]255 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]256 cm_context.iva2_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]257 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]258 cm_context.mpu_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]259 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]260 cm_context.core_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]261 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]262 cm_context.sgx_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]263 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]264 cm_context.dss_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]265 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]266 cm_context.cam_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]267 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]268 cm_context.per_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]269 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]270 cm_context.neon_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]271 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]272 cm_context.usbhost_cm_clkstctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]273 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
274 OMAP2_CM_CLKSTCTRL);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]275 cm_context.core_cm_autoidle1 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]276 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]277 cm_context.core_cm_autoidle2 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]278 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]279 cm_context.core_cm_autoidle3 =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]280 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]281 cm_context.wkup_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]282 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]283 cm_context.dss_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]284 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]285 cm_context.cam_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]286 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]287 cm_context.per_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]288 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]289 cm_context.usbhost_cm_autoidle =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]290 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]291 cm_context.sgx_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]292 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
293 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]294 cm_context.dss_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]295 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]296 cm_context.cam_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]297 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]298 cm_context.per_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]299 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]300 cm_context.usbhost_cm_sleepdep =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]301 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
302 OMAP3430_CM_SLEEPDEP);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]303 cm_context.cm_clkout_ctrl =
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]304 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
305 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]306}
307
308void omap3_cm_restore_context(void)
309{
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]310 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
311 CM_CLKSEL1);
312 omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
313 CM_CLKSEL2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]314 __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]315 omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
316 CM_CLKSEL);
317 omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
318 CM_CLKSEL);
319 omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
320 CM_CLKSEL);
321 omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
322 CM_CLKSEL);
323 omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
324 CM_CLKSEL1);
325 omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
326 OMAP2_CM_CLKSTCTRL);
Eduardo Valentina8ae6452011-04-13 18:21:07 +0300[diff] [blame]327 /*
328 * As per erratum i671, ROM code does not respect the PER DPLL
329 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
330 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
331 */
332 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
333 CM_AUTOIDLE);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]334 omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
335 CM_AUTOIDLE2);
336 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
337 OMAP3430ES2_CM_CLKSEL4);
338 omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
339 OMAP3430ES2_CM_CLKSEL5);
340 omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
341 OMAP3430ES2_CM_CLKEN2);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]342 __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
Paul Walmsleyc4d7e582010-12-21 21:05:14 -0700[diff] [blame]343 omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
344 CM_FCLKEN);
345 omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
346 OMAP3430_CM_CLKEN_PLL);
347 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
348 CM_FCLKEN1);
349 omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
350 OMAP3430ES2_CM_FCLKEN3);
351 omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
352 CM_FCLKEN);
353 omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
354 omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
355 CM_FCLKEN);
356 omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
357 CM_FCLKEN);
358 omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
359 CM_FCLKEN);
360 omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
361 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
362 omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
363 CM_ICLKEN1);
364 omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
365 CM_ICLKEN2);
366 omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
367 CM_ICLKEN3);
368 omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
369 CM_ICLKEN);
370 omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
371 omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
372 CM_ICLKEN);
373 omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
374 CM_ICLKEN);
375 omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
376 CM_ICLKEN);
377 omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
378 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
379 omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
380 CM_AUTOIDLE2);
381 omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
382 CM_AUTOIDLE2);
383 omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
384 OMAP2_CM_CLKSTCTRL);
385 omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
386 OMAP2_CM_CLKSTCTRL);
387 omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
388 OMAP2_CM_CLKSTCTRL);
389 omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
390 OMAP2_CM_CLKSTCTRL);
391 omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
392 OMAP2_CM_CLKSTCTRL);
393 omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
394 OMAP2_CM_CLKSTCTRL);
395 omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
396 OMAP2_CM_CLKSTCTRL);
397 omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
398 OMAP2_CM_CLKSTCTRL);
399 omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
400 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
401 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
402 CM_AUTOIDLE1);
403 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
404 CM_AUTOIDLE2);
405 omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
406 CM_AUTOIDLE3);
407 omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
408 CM_AUTOIDLE);
409 omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
410 CM_AUTOIDLE);
411 omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
412 CM_AUTOIDLE);
413 omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
414 CM_AUTOIDLE);
415 omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
416 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
417 omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
418 OMAP3430_CM_SLEEPDEP);
419 omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
420 OMAP3430_CM_SLEEPDEP);
421 omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
422 OMAP3430_CM_SLEEPDEP);
423 omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
424 OMAP3430_CM_SLEEPDEP);
425 omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
426 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
427 omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
428 OMAP3_CM_CLKOUT_CTRL_OFFSET);
Paul Walmsleyf0611a52010-12-21 15:30:56 -0700[diff] [blame]429}