blob: a56c536089397c2e78cb2f16a1a9291d4d2e920e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-integrator/integrator_cp.c
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10#include <linux/types.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/list.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010014#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/string.h>
Kay Sieversedbaa602011-12-21 16:26:03 -080017#include <linux/device.h>
Russell Kinga62c80e2006-01-07 13:52:45 +000018#include <linux/amba/bus.h>
19#include <linux/amba/kmi.h>
20#include <linux/amba/clcd.h>
Linus Walleij6ef297f2009-09-22 14:29:36 +010021#include <linux/amba/mmci.h>
Russell Kingfced80c2008-09-06 12:10:45 +010022#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090023#include <linux/gfp.h>
Jean-Christop PLAGNIOL-VILLARD6d803ba2010-11-17 10:04:33 +010024#include <linux/clkdev.h>
Marc Zyngier046dfa02011-05-18 10:51:53 +010025#include <linux/mtd/physmap.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Russell Kinga09e64f2008-08-05 16:14:15 +010027#include <mach/hardware.h>
Russell Kinga285edc2010-01-14 19:59:37 +000028#include <mach/platform.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <asm/setup.h>
30#include <asm/mach-types.h>
Russell King5a463342010-01-16 23:52:12 +000031#include <asm/hardware/arm_timer.h>
Russell Kingc5a0adb2010-01-16 20:16:10 +000032#include <asm/hardware/icst.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
Russell Kinga09e64f2008-08-05 16:14:15 +010034#include <mach/cm.h>
35#include <mach/lm.h>
Linus Walleij695436e2012-02-26 10:46:48 +010036#include <mach/irqs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
38#include <asm/mach/arch.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <asm/mach/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <asm/mach/map.h>
41#include <asm/mach/time.h>
42
Rob Herring8a9618f2010-10-06 16:18:08 +010043#include <asm/hardware/timer-sp.h>
Russell King5a463342010-01-16 23:52:12 +000044
Russell King9dfec4f2011-01-18 20:10:10 +000045#include <plat/clcd.h>
Russell Kingc41b16f2011-01-19 15:32:15 +000046#include <plat/fpga-irq.h>
Russell Kingd77e2702011-01-22 11:37:54 +000047#include <plat/sched_clock.h>
Russell King9dfec4f2011-01-18 20:10:10 +000048
Russell King98c672c2010-05-22 18:18:57 +010049#include "common.h"
50
Linus Torvalds1da177e2005-04-16 15:20:36 -070051#define INTCP_PA_FLASH_BASE 0x24000000
52#define INTCP_FLASH_SIZE SZ_32M
53
54#define INTCP_PA_CLCD_BASE 0xc0000000
55
Russell Kingc41b16f2011-01-19 15:32:15 +000056#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
57#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
58#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Linus Torvalds1da177e2005-04-16 15:20:36 -070060#define INTCP_ETH_SIZE 0x10
61
Russell Kingda7ba952010-01-17 19:59:58 +000062#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
Linus Torvalds1da177e2005-04-16 15:20:36 -070063#define INTCP_FLASHPROG 0x04
64#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
65#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
66
67/*
68 * Logical Physical
69 * f1000000 10000000 Core module registers
70 * f1100000 11000000 System controller registers
71 * f1200000 12000000 EBI registers
72 * f1300000 13000000 Counter/Timer
73 * f1400000 14000000 Interrupt controller
74 * f1600000 16000000 UART 0
75 * f1700000 17000000 UART 1
76 * f1a00000 1a000000 Debug LEDs
Russell Kingda7ba952010-01-17 19:59:58 +000077 * fc900000 c9000000 GPIO
78 * fca00000 ca000000 SIC
79 * fcb00000 cb000000 CP system control
Linus Torvalds1da177e2005-04-16 15:20:36 -070080 */
81
82static struct map_desc intcp_io_desc[] __initdata = {
Deepak Saxenac8d27292005-10-28 15:19:10 +010083 {
84 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
85 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
86 .length = SZ_4K,
87 .type = MT_DEVICE
88 }, {
89 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
90 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
91 .length = SZ_4K,
92 .type = MT_DEVICE
93 }, {
94 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
95 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
96 .length = SZ_4K,
97 .type = MT_DEVICE
98 }, {
99 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE
103 }, {
104 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
106 .length = SZ_4K,
107 .type = MT_DEVICE
108 }, {
109 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
110 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
111 .length = SZ_4K,
112 .type = MT_DEVICE
113 }, {
114 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
115 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
116 .length = SZ_4K,
117 .type = MT_DEVICE
118 }, {
119 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
120 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
121 .length = SZ_4K,
122 .type = MT_DEVICE
123 }, {
Russell Kingda7ba952010-01-17 19:59:58 +0000124 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
125 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
Deepak Saxenac8d27292005-10-28 15:19:10 +0100126 .length = SZ_4K,
127 .type = MT_DEVICE
128 }, {
Russell Kingda7ba952010-01-17 19:59:58 +0000129 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
130 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
Deepak Saxenac8d27292005-10-28 15:19:10 +0100131 .length = SZ_4K,
132 .type = MT_DEVICE
133 }, {
Russell Kingda7ba952010-01-17 19:59:58 +0000134 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
135 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
Deepak Saxenac8d27292005-10-28 15:19:10 +0100136 .length = SZ_4K,
137 .type = MT_DEVICE
138 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139};
140
141static void __init intcp_map_io(void)
142{
143 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
144}
145
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146static void __init intcp_init_irq(void)
147{
Linus Walleij3108e6a2012-04-28 14:33:47 +0100148 u32 pic_mask, cic_mask, sic_mask;
Russell Kingc41b16f2011-01-19 15:32:15 +0000149
Linus Walleij3108e6a2012-04-28 14:33:47 +0100150 /* These masks are for the HW IRQ registers */
Russell Kingc41b16f2011-01-19 15:32:15 +0000151 pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
152 pic_mask |= (~((~0u) << (29 - 22))) << 22;
Linus Walleij3108e6a2012-04-28 14:33:47 +0100153 cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
Russell Kingc41b16f2011-01-19 15:32:15 +0000154 sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155
156 /*
157 * Disable all interrupt sources
158 */
Russell Kingc41b16f2011-01-19 15:32:15 +0000159 writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
160 writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
161 writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
162 writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
163 writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
164 writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165
Linus Walleij3108e6a2012-04-28 14:33:47 +0100166 fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
167 -1, pic_mask, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168
Linus Walleij3108e6a2012-04-28 14:33:47 +0100169 fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
170 -1, cic_mask, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171
Linus Walleij3108e6a2012-04-28 14:33:47 +0100172 fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
173 IRQ_CP_CPPLDINT, sic_mask, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174}
175
176/*
177 * Clock handling
178 */
Russell Kingd1914c72010-01-14 20:09:34 +0000179#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
180#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181
Russell King39c0cb02010-01-16 16:27:28 +0000182static const struct icst_params cp_auxvco_params = {
Russell King64fceb12010-01-16 17:28:44 +0000183 .ref = 24000000,
Russell King4de2edb2010-01-16 18:08:47 +0000184 .vco_max = ICST525_VCO_MAX_5V,
Russell Kinge73a46a2010-01-16 19:49:39 +0000185 .vco_min = ICST525_VCO_MIN,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186 .vd_min = 8,
187 .vd_max = 263,
188 .rd_min = 3,
189 .rd_max = 65,
Russell King232eaf72010-01-16 19:46:19 +0000190 .s2div = icst525_s2div,
191 .idx2s = icst525_idx2s,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192};
193
Russell King39c0cb02010-01-16 16:27:28 +0000194static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195{
196 u32 val;
197
Russell Kingd1914c72010-01-14 20:09:34 +0000198 val = readl(clk->vcoreg) & ~0x7ffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199 val |= vco.v | (vco.r << 9) | (vco.s << 16);
200
201 writel(0xa05f, CM_LOCK);
Russell Kingd1914c72010-01-14 20:09:34 +0000202 writel(val, clk->vcoreg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 writel(0, CM_LOCK);
204}
205
Russell King9bf5b2e2010-03-01 16:18:39 +0000206static const struct clk_ops cp_auxclk_ops = {
207 .round = icst_clk_round,
208 .set = icst_clk_set,
209 .setvco = cp_auxvco_set,
210};
211
Russell Kingd72fbdf2008-11-08 20:08:08 +0000212static struct clk cp_auxclk = {
Russell King9bf5b2e2010-03-01 16:18:39 +0000213 .ops = &cp_auxclk_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 .params = &cp_auxvco_params,
Russell Kingd1914c72010-01-14 20:09:34 +0000215 .vcoreg = CM_AUXOSC,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216};
217
Russell King7ff550d2011-05-12 13:31:48 +0100218static struct clk sp804_clk = {
219 .rate = 1000000,
220};
221
Russell Kingd72fbdf2008-11-08 20:08:08 +0000222static struct clk_lookup cp_lookups[] = {
223 { /* CLCD */
224 .dev_id = "mb:c0",
225 .clk = &cp_auxclk,
Russell King7ff550d2011-05-12 13:31:48 +0100226 }, { /* SP804 timers */
227 .dev_id = "sp804",
228 .clk = &sp804_clk,
Russell Kingd72fbdf2008-11-08 20:08:08 +0000229 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700230};
231
232/*
233 * Flash handling.
234 */
Marc Zyngier046dfa02011-05-18 10:51:53 +0100235static int intcp_flash_init(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236{
237 u32 val;
238
239 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
240 val |= CINTEGRATOR_FLASHPROG_FLWREN;
241 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
242
243 return 0;
244}
245
Marc Zyngier046dfa02011-05-18 10:51:53 +0100246static void intcp_flash_exit(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247{
248 u32 val;
249
250 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
251 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
252 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
253}
254
Marc Zyngier667f3902011-05-18 10:51:55 +0100255static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256{
257 u32 val;
258
259 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
260 if (on)
261 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
262 else
263 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
264 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
265}
266
Marc Zyngier046dfa02011-05-18 10:51:53 +0100267static struct physmap_flash_data intcp_flash_data = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 .width = 4,
269 .init = intcp_flash_init,
270 .exit = intcp_flash_exit,
271 .set_vpp = intcp_flash_set_vpp,
272};
273
274static struct resource intcp_flash_resource = {
275 .start = INTCP_PA_FLASH_BASE,
276 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
277 .flags = IORESOURCE_MEM,
278};
279
280static struct platform_device intcp_flash_device = {
Marc Zyngier046dfa02011-05-18 10:51:53 +0100281 .name = "physmap-flash",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 .id = 0,
283 .dev = {
284 .platform_data = &intcp_flash_data,
285 },
286 .num_resources = 1,
287 .resource = &intcp_flash_resource,
288};
289
290static struct resource smc91x_resources[] = {
291 [0] = {
Russell Kingda7ba952010-01-17 19:59:58 +0000292 .start = INTEGRATOR_CP_ETH_BASE,
293 .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 .flags = IORESOURCE_MEM,
295 },
296 [1] = {
297 .start = IRQ_CP_ETHINT,
298 .end = IRQ_CP_ETHINT,
299 .flags = IORESOURCE_IRQ,
300 },
301};
302
303static struct platform_device smc91x_device = {
304 .name = "smc91x",
305 .id = 0,
306 .num_resources = ARRAY_SIZE(smc91x_resources),
307 .resource = smc91x_resources,
308};
309
310static struct platform_device *intcp_devs[] __initdata = {
311 &intcp_flash_device,
312 &smc91x_device,
313};
314
315/*
316 * It seems that the card insertion interrupt remains active after
317 * we've acknowledged it. We therefore ignore the interrupt, and
318 * rely on reading it from the SIC. This also means that we must
319 * clear the latched interrupt.
320 */
321static unsigned int mmc_status(struct device *dev)
322{
Russell Kingb830b9b2010-01-17 20:45:12 +0000323 unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
324 writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325
326 return status & 8;
327}
328
Linus Walleij6ef297f2009-09-22 14:29:36 +0100329static struct mmci_platform_data mmc_data = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
331 .status = mmc_status,
Russell King7fb2bbf2009-07-09 15:15:12 +0100332 .gpio_wp = -1,
333 .gpio_cd = -1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334};
335
Russell King2f64ccd2011-12-18 14:50:51 +0000336#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
337#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
Russell King2f64ccd2011-12-18 14:50:51 +0000339static AMBA_APB_DEVICE(mmc, "mb:1c", 0, INTEGRATOR_CP_MMC_BASE,
340 INTEGRATOR_CP_MMC_IRQS, &mmc_data);
341
342static AMBA_APB_DEVICE(aaci, "mb:1d", 0, INTEGRATOR_CP_AACI_BASE,
343 INTEGRATOR_CP_AACI_IRQS, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344
345
346/*
347 * CLCD support
348 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349/*
350 * Ensure VGA is selected.
351 */
352static void cp_clcd_enable(struct clcd_fb *fb)
353{
Russell Kinge6b9c1f2011-01-22 11:02:10 +0000354 struct fb_var_screeninfo *var = &fb->fb.var;
355 u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
Russell King4774e222005-04-30 23:32:38 +0100356
Russell Kinge6b9c1f2011-01-22 11:02:10 +0000357 if (var->bits_per_pixel <= 8 ||
358 (var->bits_per_pixel == 16 && var->green.length == 5))
359 /* Pseudocolor, RGB555, BGR555 */
360 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
Russell King4774e222005-04-30 23:32:38 +0100361 else if (fb->fb.var.bits_per_pixel <= 16)
Russell Kinge6b9c1f2011-01-22 11:02:10 +0000362 /* truecolor RGB565 */
363 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
Russell King4774e222005-04-30 23:32:38 +0100364 else
365 val = 0; /* no idea for this, don't trust the docs */
366
367 cm_control(CM_CTRL_LCDMUXSEL_MASK|
368 CM_CTRL_LCDEN0|
369 CM_CTRL_LCDEN1|
370 CM_CTRL_STATIC1|
371 CM_CTRL_STATIC2|
372 CM_CTRL_STATIC|
373 CM_CTRL_n24BITEN, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374}
375
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376static int cp_clcd_setup(struct clcd_fb *fb)
377{
Russell King9dfec4f2011-01-18 20:10:10 +0000378 fb->panel = versatile_clcd_get_panel("VGA");
379 if (!fb->panel)
380 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381
Russell King9dfec4f2011-01-18 20:10:10 +0000382 return versatile_clcd_setup_dma(fb, SZ_1M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383}
384
385static struct clcd_board clcd_data = {
386 .name = "Integrator/CP",
Russell King9dfec4f2011-01-18 20:10:10 +0000387 .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 .check = clcdfb_check,
389 .decode = clcdfb_decode,
390 .enable = cp_clcd_enable,
391 .setup = cp_clcd_setup,
Russell King9dfec4f2011-01-18 20:10:10 +0000392 .mmap = versatile_clcd_mmap_dma,
393 .remove = versatile_clcd_remove_dma,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394};
395
Russell King2f64ccd2011-12-18 14:50:51 +0000396static AMBA_AHB_DEVICE(clcd, "mb:c0", 0, INTCP_PA_CLCD_BASE,
397 { IRQ_CP_CLCDCINT }, &clcd_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398
399static struct amba_device *amba_devs[] __initdata = {
400 &mmc_device,
401 &aaci_device,
402 &clcd_device,
403};
404
Russell Kingd77e2702011-01-22 11:37:54 +0000405#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
406
Russell Kingc735c982011-01-11 13:00:04 +0000407static void __init intcp_init_early(void)
408{
409 clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
410
411 integrator_init_early();
Russell Kingd77e2702011-01-22 11:37:54 +0000412
413#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
414 versatile_sched_clock_init(REFCOUNTER, 24000000);
415#endif
Russell Kingc735c982011-01-11 13:00:04 +0000416}
417
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418static void __init intcp_init(void)
419{
420 int i;
421
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
423
424 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
425 struct amba_device *d = amba_devs[i];
426 amba_device_register(d, &iomem_resource);
427 }
428}
429
Russell King5a463342010-01-16 23:52:12 +0000430#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
431#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
432#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433
434static void __init intcp_timer_init(void)
435{
Russell King5a463342010-01-16 23:52:12 +0000436 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
437 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
438 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
439
Russell Kingfb593cf2011-05-12 12:08:23 +0100440 sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
Russell King57cc4f72011-05-12 15:31:13 +0100441 sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442}
443
444static struct sys_timer cp_timer = {
445 .init = intcp_timer_init,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446};
447
448MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
Russell Kinge9dea0c2005-07-03 17:38:58 +0100449 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
Nicolas Pitrec5e587a2011-07-05 22:38:12 -0400450 .atag_offset = 0x100,
Russell King98c672c2010-05-22 18:18:57 +0100451 .reserve = integrator_reserve,
Russell Kingc735c982011-01-11 13:00:04 +0000452 .map_io = intcp_map_io,
Linus Walleij695436e2012-02-26 10:46:48 +0100453 .nr_irqs = NR_IRQS_INTEGRATOR_CP,
Russell Kingc735c982011-01-11 13:00:04 +0000454 .init_early = intcp_init_early,
Russell Kinge9dea0c2005-07-03 17:38:58 +0100455 .init_irq = intcp_init_irq,
Linus Walleij3108e6a2012-04-28 14:33:47 +0100456 .handle_irq = fpga_handle_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 .timer = &cp_timer,
Russell Kinge9dea0c2005-07-03 17:38:58 +0100458 .init_machine = intcp_init,
Russell King6338b662011-11-03 19:54:37 +0000459 .restart = integrator_restart,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460MACHINE_END