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gerrit-public.fairphone.software / kernel / msm-5.4 / 63c53823f00f0ffd13e8c86b05c1486614a2df85 / drivers / clk / mediatek / clk-pll.c
  1. e986211 clk: mediatek: Add MT2701 clock support by Shunli Wang · 8 years ago
  2. 928f3bf clk: mediatek: remove __init from clk registration functions by James Liao · 8 years ago
  3. cdb2bab clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS by James Liao · 10 years ago
  4. 75ce0cd clk: mediatek: Add MT8173 MMPLL change rate support by James Liao · 9 years ago
  5. 196de71 clk: mediatek: Fix calculation of PLL rate settings by James Liao · 9 years ago
  6. b3be457 clk: mediatek: Fix PLL registers setting flow by James Liao · 9 years ago
  7. 95f5898 clk: mediatek: Initialize clk_init_data by Ricky Liang · 10 years ago
  8. 9741b1a clk: mediatek: Add initial common clock support for Mediatek SoCs. by James Liao · 10 years ago