| #include "sm6150.dtsi" |
| #include "sa6155-pmic.dtsi" |
| #include "camera/sa6155p-camera.dtsi" |
| #include "camera/sa6155p-camera-sensor.dtsi" |
| #include "display/sa6155-display.dtsi" |
| |
| / { |
| model = "Qualcomm Technologies, Inc. SA6155P"; |
| qcom,msm-name = "SA6155P"; |
| qcom,msm-id = <377 0>, <380 0>; |
| |
| aliases { |
| pci-domain0 = &pcie0; /* PCIe0 domain */ |
| }; |
| }; |
| |
| /* Delete second instance of pm6155 definitions for APQ version */ |
| &spmi_bus { |
| /delete-node/ qcom,pm6155@4; |
| /delete-node/ qcom,pm6155@5; |
| }; |
| |
| &apps_rsc { |
| /delete-node/ rpmh-regulator-modemlvl; |
| /delete-node/ rpmh-regulator-ldoc2; |
| /delete-node/ rpmh-regulator-ldoc3; |
| /delete-node/ rpmh-regulator-ldoc4; |
| /delete-node/ rpmh-regulator-ldoc13; |
| /delete-node/ rpmh-regulator-ldoc14; |
| /delete-node/ rpmh-regulator-ldoc16; |
| /delete-node/ rpmh-regulator-ldoc17; |
| /delete-node/ rpmh-regulator-ldoc18; |
| /delete-node/ bt_wcn3990; |
| }; |
| |
| &soc { |
| qfprom: qfprom@780130 { |
| compatible = "qcom,qfprom"; |
| reg = <0x00780130 0x4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| read-only; |
| ranges; |
| }; |
| |
| hsi2s: qcom,hsi2s@1b40000 { |
| compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; |
| number-of-interfaces = <2>; |
| reg = <0x1b40000 0x28000>; |
| reg-names = "lpa_if"; |
| interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_SDR_CORE_CLK>, |
| <&gcc GCC_SDR_WR0_MEM_CLK>, |
| <&gcc GCC_SDR_WR1_MEM_CLK>, |
| <&gcc GCC_SDR_WR2_MEM_CLK>, |
| <&gcc GCC_SDR_CSR_HCLK>; |
| clock-names = "core_clk", "wr0_mem_clk", |
| "wr1_mem_clk", "wr2_mem_clk", |
| "csr_hclk"; |
| number-of-rate-detectors = <2>; |
| rate-detector-interfaces = <0 1>; |
| iommus = <&apps_smmu 0x035C 0x1>; |
| qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>; |
| |
| sdr0: qcom,hs0_i2s { |
| compatible = "qcom,hsi2s-interface"; |
| minor-number = <0>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active |
| &hs0_i2s_data1_active>; |
| pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep |
| &hs0_i2s_data1_sleep>; |
| clocks = <&gcc GCC_SDR_PRI_MI2S_CLK>; |
| clock-names = "pri_mi2s_clk"; |
| bit-clock-hz = <12288000>; |
| data-buffer-ms = <10>; |
| bit-depth = <32>; |
| spkr-channel-count = <2>; |
| mic-channel-count = <2>; |
| pcm-rate = <2>; |
| pcm-sync-src = <0>; |
| aux-mode = <0>; |
| rpcm-width = <1>; |
| tpcm-width = <1>; |
| enable-tdm = <1>; |
| tdm-rate = <32>; |
| tdm-rpcm-width = <16>; |
| tdm-tpcm-width = <16>; |
| tdm-sync-delay = <2>; |
| tdm-inv-sync = <0>; |
| pcm-lane-config = <1>; |
| }; |
| |
| sdr1: qcom,hs1_i2s { |
| compatible = "qcom,hsi2s-interface"; |
| minor-number = <1>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active |
| &hs1_i2s_data1_active>; |
| pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep |
| &hs1_i2s_data1_sleep>; |
| clocks = <&gcc GCC_SDR_SEC_MI2S_CLK>; |
| clock-names = "sec_mi2s_clk"; |
| bit-clock-hz = <12288000>; |
| data-buffer-ms = <10>; |
| bit-depth = <32>; |
| spkr-channel-count = <2>; |
| mic-channel-count = <2>; |
| pcm-rate = <2>; |
| pcm-sync-src = <0>; |
| aux-mode = <0>; |
| rpcm-width = <1>; |
| tpcm-width = <1>; |
| enable-tdm = <1>; |
| tdm-rate = <32>; |
| tdm-rpcm-width = <16>; |
| tdm-tpcm-width = <16>; |
| tdm-sync-delay = <2>; |
| tdm-inv-sync = <0>; |
| pcm-lane-config = <1>; |
| }; |
| }; |
| }; |
| |
| &qusb_phy0 { |
| vdd-supply = <&L5A>; |
| vdda18-supply = <&L12A>; |
| vdda33-supply = <&L13A>; |
| }; |
| |
| &usb_qmp_phy { |
| vdd-supply = <&L5A>; |
| core-supply = <&L12A>; |
| }; |
| |
| &qusb_phy1 { |
| vdd-supply = <&L5A>; |
| vdda18-supply = <&L12A>; |
| vdda33-supply = <&L13A>; |
| }; |
| |
| &gcc { |
| compatible = "qcom,sa6155-gcc", "syscon"; |
| /delete-property/ protected-clocks; |
| }; |
| |
| &camcc { |
| compatible = "qcom,sa6155-camcc", "syscon"; |
| vdd_mx-supply = <&VDD_CX_LEVEL>; |
| }; |
| |
| &dispcc { |
| compatible = "qcom,sa6155-dispcc", "syscon"; |
| }; |
| |
| &gpucc { |
| compatible = "qcom,sa6155-gpucc", "syscon"; |
| vdd_mx-supply = <&VDD_CX_LEVEL>; |
| }; |
| |
| &scc { |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &videocc { |
| compatible = "qcom,sa6155-videocc", "syscon"; |
| }; |
| |
| #include "sa6155-pcie.dtsi" |
| &slpi_tlmm { |
| status = "ok"; |
| }; |
| |
| /* GPU power level overrides */ |
| &msm_gpu { |
| /* |
| * Speed-bin zero is default speed bin. |
| * For rest of the speed bins, speed-bin value |
| * is calulated as FMAX/4.8 MHz round up to zero |
| * decimal places. |
| */ |
| |
| /delete-node/qcom,gpu-pwrlevel-bins; |
| qcom,gpu-pwrlevel-bins { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compatible="qcom,gpu-pwrlevel-bins"; |
| |
| qcom,gpu-pwrlevels-0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <0>; |
| |
| qcom,initial-pwrlevel = <4>; |
| qcom,ca-target-pwrlevel = <3>; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <845000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM L1 */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <745000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <650000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <500000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <435000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <0>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <177>; |
| |
| qcom,initial-pwrlevel = <4>; |
| qcom,ca-target-pwrlevel = <3>; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <845000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM L1 */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <745000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <650000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <500000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <435000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <0>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <156>; |
| |
| qcom,initial-pwrlevel = <3>; |
| qcom,ca-target-pwrlevel = <2>; |
| |
| /* NOM L1 */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <745000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <650000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <500000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <435000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <0>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-3 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <136>; |
| |
| qcom,initial-pwrlevel = <2>; |
| qcom,ca-target-pwrlevel = <1>; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <650000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <500000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <435000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <0>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-4 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <105>; |
| |
| qcom,initial-pwrlevel = <1>; |
| qcom,ca-target-pwrlevel = <0>; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <500000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <435000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <0>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-5 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <73>; |
| |
| qcom,initial-pwrlevel = <0>; |
| qcom,ca-target-pwrlevel = <0>; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <350000000>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <0>; |
| qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| }; |
| }; |
| |
| &mdss_dsi0_pll { |
| /delete-property/ qcom,dsi-pll-ssc-en; |
| }; |
| |
| #include "sa6155-audio.dtsi" |