| #include <dt-bindings/interconnect/qcom,sm6150.h> |
| |
| &soc { |
| /* |
| * QUPv3 North & South Instances |
| * North 0 : SE 4 |
| * North 1 : SE 5 |
| * North 2 : SE 6 |
| * North 3 : SE 7 |
| * South 0 : SE 0 |
| * South 1 : SE 1 |
| * South 2 : SE 2 |
| * South 3 : SE 3 |
| */ |
| |
| /* QUPv3 South Instances */ |
| qupv3_0: qcom,qupv3_0_geni_se@8c0000 { |
| compatible = "qcom,qupv3-geni-se"; |
| reg = <0x8c0000 0x6000>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-bus-ids = |
| <MASTER_QUP_0 SLAVE_EBI1>; |
| iommus = <&apps_smmu 0xc3 0x0>; |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; |
| qcom,iommu-geometry = <0x40000000 0x10000000>; |
| qcom,iommu-dma = "fastmap"; |
| status = "ok"; |
| }; |
| |
| /* Debug UART Instance for CDP/MTP platform */ |
| qupv3_se0_2uart: qcom,qup_uart@0x880000 { |
| compatible = "qcom,msm-geni-console"; |
| reg = <0x880000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se0_2uart_active>; |
| pinctrl-1 = <&qupv3_se0_2uart_sleep>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| /* I2C */ |
| qupv3_se1_i2c: i2c@884000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x884000 0x4000>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se1_i2c_active>; |
| pinctrl-1 = <&qupv3_se1_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se2_i2c: i2c@888000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x888000 0x4000>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se2_i2c_active>; |
| pinctrl-1 = <&qupv3_se2_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se3_i2c: i2c@88c000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0x88c000 0x4000>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se3_i2c_active>; |
| pinctrl-1 = <&qupv3_se3_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| /* SPI */ |
| qupv3_se2_spi: spi@888000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x888000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se2_spi_active>; |
| pinctrl-1 = <&qupv3_se2_spi_sleep>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_0>; |
| status = "disabled"; |
| }; |
| |
| /* QUPv3 North instances */ |
| qupv3_1: qcom,qupv3_1_geni_se@ac0000 { |
| compatible = "qcom,qupv3-geni-se"; |
| reg = <0xac0000 0x6000>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-bus-ids = |
| <MASTER_BLSP_1 SLAVE_EBI1>; |
| iommus = <&apps_smmu 0x363 0x0>; |
| qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; |
| qcom,iommu-geometry = <0x40000000 0x10000000>; |
| qcom,iommu-dma = "fastmap"; |
| status = "ok"; |
| }; |
| |
| |
| /* I2C */ |
| qupv3_se4_i2c: i2c@a80000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa80000 0x4000>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se4_i2c_active>; |
| pinctrl-1 = <&qupv3_se4_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se5_i2c: i2c@a84000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa84000 0x4000>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se5_i2c_active>; |
| pinctrl-1 = <&qupv3_se5_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se6_i2c: i2c@a88000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa88000 0x4000>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se6_i2c_active>; |
| pinctrl-1 = <&qupv3_se6_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se7_i2c: i2c@a8c000 { |
| compatible = "qcom,i2c-geni"; |
| reg = <0xa8c000 0x4000>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se7_i2c_active>; |
| pinctrl-1 = <&qupv3_se7_i2c_sleep>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| /* SPI */ |
| qupv3_se4_spi: spi@a80000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa80000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se4_spi_active>; |
| pinctrl-1 = <&qupv3_se4_spi_sleep>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se6_spi: spi@a88000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa88000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se6_spi_active>; |
| pinctrl-1 = <&qupv3_se6_spi_sleep>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| qupv3_se7_spi: spi@a8c000 { |
| compatible = "qcom,spi-geni"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa8c000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se7_spi_active>; |
| pinctrl-1 = <&qupv3_se7_spi_sleep>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| |
| /* |
| * HS UART instances. HS UART usecases can be supported on these |
| * instances only. |
| */ |
| qupv3_se7_4uart: qcom,qup_uart@0xa8c000 { |
| compatible = "qcom,msm-geni-serial-hs"; |
| reg = <0xa8c000 0x4000>; |
| reg-names = "se_phys"; |
| clock-names = "se-clk", "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, |
| <&qupv3_se7_tx>; |
| pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, |
| <&qupv3_se7_tx>; |
| interrupts-extended = <&intc GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, |
| <&tlmm 13 0>; |
| qcom,wakeup-byte = <0xFD>; |
| qcom,wrapper-core = <&qupv3_1>; |
| status = "disabled"; |
| }; |
| }; |