fp5/sm8150.dtsi

#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,camcc-sm8150.h>
#include <dt-bindings/clock/qcom,dispcc-sm8150.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/clock/qcom,npucc-sm8150.h>
#include <dt-bindings/clock/qcom,scc-sm8150.h>
#include <dt-bindings/clock/qcom,videocc-sm8150.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
				opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
				opp-supported-hw = <ddrtype>;}

/ {
	model = "Qualcomm Technologies, Inc. SM8150";
	compatible = "qcom,sm8150";
	qcom,msm-name = "SM8150 V1";
	qcom,msm-id = <339 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;
	memory { device_type = "memory"; reg = <0 0 0 0>; };

	aliases {
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
		pci-domain0 = &pcie0; /* PCIe0 domain */
		pci-domain1 = &pcie1; /* PCIe1 domain */
		serial0 = &qupv3_se12_2uart;
		hsuart0 = &qupv3_se13_4uart;
		hsuart1 = &qupv3_se4_2uart;
		spi22 = &qupv3_se22_spi;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_1>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_2>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			L2_2: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_3>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			L2_3: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x400>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <374>;
			next-level-cache = <&L2_4>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;
			#cooling-cells = <2>;
			L2_4: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x500>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <374>;
			next-level-cache = <&L2_5>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;
			L2_5: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x600>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <374>;
			next-level-cache = <&L2_6>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;
			L2_6: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x700>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <431>;
			next-level-cache = <&L2_7>;
			qcom,freq-domain = <&cpufreq_hw 2 4>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;
			#cooling-cells = <2>;
			L2_7: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	chosen { };

	soc: soc { };

	firmware: firmware {
		android {
			compatible = "android,firmware";
			vbmeta {
				compatible = "android,vbmeta";
				parts = "vbmeta,boot,system,vendor,dtbo";
			};

			fstab {
				compatible = "android,fstab";
				vendor {
					compatible = "android,vendor";
					dev = "/dev/block/platform/soc
						/1d84000.ufshc/by-name/vendor";
					type = "ext4";
					mnt_flags = "ro,barrier=1,discard";
					fsmgr_flags = "wait,slotselect,avb";
					status = "ok";
				};
			};
		};
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: hyp_mem {
			no-map;
			reg = <0x0 0x85700000 0x0 0x600000>;
		};

		xbl_mem: xbl_mem {
			no-map;
			reg = <0x0 0x85e00000 0x0 0x100000>;
		};

		aop_mem: memory@85f00000 {
			reg = <0x0 0x85f00000 0x0 0x20000>;
			no-map;
		};

		aop_cmd_db: memory@85f20000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x85f20000 0x0 0x20000>;
			no-map;
		};

		smem_region: smem {
			no-map;
			reg = <0x0 0x86000000 0x0 0x200000>;
		};

		removed_regions: removed_regions {
			no-map;
			reg = <0x0 0x86200000 0x0 0x5500000>;
		};

		pil_camera_mem: camera_region {
			no-map;
			reg = <0x0 0x8b700000 0x0 0x500000>;
		};

		pil_wlan_fw_mem: pil_wlan_fw_region {
			no-map;
			reg = <0x0 0x8bc00000 0x0 0x180000>;
		};

		pil_npu_mem: pil_npu_region {
			no-map;
			reg = <0x0 0x8bd80000 0x0 0x80000>;
		};

		pil_adsp_mem: pil_adsp_region {
			no-map;
			reg = <0x0 0x8be00000 0x0 0x1a00000>;
		};

		pil_modem_mem: modem_region {
			no-map;
			reg = <0x0 0x8d800000 0x0 0x9600000>;
		};

		pil_video_mem: pil_video_region {
			no-map;
			reg = <0x0 0x96e00000 0x0 0x500000>;
		};

		pil_slpi_mem: pil_slpi_region {
			no-map;
			reg = <0x0 0x97300000 0x0 0x1400000>;
		};

		pil_ipa_fw_mem: pil_ipa_fw_region {
			no-map;
			reg = <0x0 0x98700000 0x0 0x10000>;
		};

		pil_ipa_gsi_mem: pil_ipa_gsi_region {
			no-map;
			reg = <0x0 0x98710000 0x0 0x5000>;
		};

		pil_gpu_mem: pil_gpu_region {
			no-map;
			reg = <0x0 0x98715000 0x0 0x2000>;
		};

		pil_spss_mem: pil_spss_region {
			no-map;
			reg = <0x0 0x98800000 0x0 0x100000>;
		};

		pil_cdsp_mem: cdsp_regions {
			no-map;
			reg = <0x0 0x98900000 0x0 0x1400000>;
		};

		qseecom_mem: qseecom_region {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0x9e400000 0x0 0x1400000>;
		};

		cdsp_sec_mem: cdsp_sec_regions {
			no-map;
			reg = <0x0 0xa4c00000 0x0 0x3c00000>;
		};

		cont_splash_memory: cont_splash_region {
			reg = <0x0 0x9c000000 0x0 0x2400000>;
			label = "cont_splash_region";
		};

		disp_rdump_memory: disp_rdump_region {
			reg = <0x0 0x9c000000 0x0 0x02400000>;
			label = "disp_rdump_region";
		};

		adsp_mem: adsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1000000>;
		};

		cdsp_mem: cdsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x400000>;
		};

		user_contig_mem: user_contig_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1000000>;
		};

		qseecom_ta_mem: qseecom_ta_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1000000>;
		};

		sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x800000>;
		};

		secure_display_memory: secure_display_region { /* Secure UI */
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0xA000000>;
		};

		dump_mem: mem_dump_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			size = <0 0x2800000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x2800000>;
			linux,cma-default;
		};
	};

	vendor: vendor {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";
	};

	qcom-secure-buffer {
		compatible = "qcom,secure-buffer";
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
			clock-output-names = "sleep_clk";
		};
	};
};

#include "display/sm8150-sde.dtsi"
#include "display/sm8150-sde-pll.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,     /* GICD */
		      <0x17a60000 0x100000>;    /* GICR * 8 */
		interrupts = <1 9 4>;
		interrupt-parent = <&intc>;
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,sm8150-pdc";
		reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	timer@17c20000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17c20000 0x1000>;
		clock-frequency = <19200000>;

		frame@17c21000 {
			frame-number = <0>;
			interrupts = <0 8 0x4>,
				     <0 6 0x4>;
			reg = <0x17c21000 0x1000>,
			      <0x17c22000 0x1000>;
		};

		frame@17c23000 {
			frame-number = <1>;
			interrupts = <0 9 0x4>;
			reg = <0x17c23000 0x1000>;
			status = "disabled";
		};

		frame@17c25000 {
			frame-number = <2>;
			interrupts = <0 10 0x4>;
			reg = <0x17c25000 0x1000>;
			status = "disabled";
		};

		frame@17c27000 {
			frame-number = <3>;
			interrupts = <0 11 0x4>;
			reg = <0x17c26000 0x1000>;
			status = "disabled";
		};

		frame@17c29000 {
			frame-number = <4>;
			interrupts = <0 12 0x4>;
			reg = <0x17c29000 0x1000>;
			status = "disabled";
		};

		frame@17c2b000 {
			frame-number = <5>;
			interrupts = <0 13 0x4>;
			reg = <0x17c2b000 0x1000>;
			status = "disabled";
		};

		frame@17c2d000 {
			frame-number = <6>;
			interrupts = <0 14 0x4>;
			reg = <0x17c2d000 0x1000>;
			status = "disabled";
		};
	};

	qcom,mpm2-sleep-counter@c221000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0xc221000 0x1000>;
		clock-frequency = <32768>;
	};

	qcom,msm-imem@146bf000 {
		compatible = "qcom,msm-imem";
		reg = <0x146bf000 0x1000>;
		ranges = <0x0 0x146bf000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};

		pil@94c {
			compatible = "qcom,msm-imem-pil";
			reg = <0x94c 0xc8>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 0xc8>;
		};
	};

	llcc_pmu: llcc-pmu@90cc000 {
		compatible = "qcom,llcc-pmu-ver2";
		reg = <0x090cc000 0x300>;
		reg-names = "lagg-base";
	};

	llcc_bw_opp_table: llcc-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY( 150, 16); /*  2288 MB/s */
		BW_OPP_ENTRY( 200, 16); /*  3051 MB/s */
		BW_OPP_ENTRY( 403, 16); /*  6149 MB/s */
		BW_OPP_ENTRY( 533, 16); /*  8132 MB/s */
		BW_OPP_ENTRY( 666, 16); /* 10162 MB/s */
		BW_OPP_ENTRY( 777, 16); /* 11856 MB/s */
	};

	cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
		compatible = "qcom,devfreq-icc";
		governor = "performance";
		interconnects = <&gem_noc MASTER_APPSS_PROC
				&gem_noc SLAVE_LLCC>;
		qcom,active-only;
		operating-points-v2 = <&llcc_bw_opp_table>;
	};

	cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
		compatible = "qcom,bimc-bwmon4";
		reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&cpu_cpu_llcc_bw>;
		qcom,count-unit = <0x10000>;
	};

	ddr_bw_opp_table: ddr-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY_DDR( 200, 4, 0x80); /*  762 MB/s */
		BW_OPP_ENTRY_DDR( 300, 4, 0x80); /* 1144 MB/s */
		BW_OPP_ENTRY_DDR( 451, 4, 0x80); /* 1720 MB/s */
		BW_OPP_ENTRY_DDR( 547, 4, 0x80); /* 2086 MB/s */
		BW_OPP_ENTRY_DDR( 681, 4, 0x80); /* 2597 MB/s */
		BW_OPP_ENTRY_DDR( 768, 4, 0x80); /* 2929 MB/s */
		BW_OPP_ENTRY_DDR(1017, 4, 0x80); /* 3879 MB/s */
		BW_OPP_ENTRY_DDR(1296, 4, 0x80); /* 4943 MB/s */
		BW_OPP_ENTRY_DDR(1555, 4, 0x80); /* 5931 MB/s */
		BW_OPP_ENTRY_DDR(1804, 4, 0x80); /* 6881 MB/s */
		BW_OPP_ENTRY_DDR(2092, 4, 0x80); /* 7980 MB/s */
	};

	cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 {
		compatible = "qcom,bimc-bwmon5";
		reg = <0x90cd000 0x1000>;
		reg-names = "base";
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&cpu_llcc_ddr_bw>;
		qcom,count-unit = <0x10000>;
	};

	cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
		compatible = "qcom,devfreq-icc-l3";
		reg = <0x18321110 0x500>;
		reg-names = "ftbl-base";
		qcom,ftbl-row-size = <0x20>;
		governor = "performance";
		interconnects = <&osm_l3 MASTER_OSM_L3_APPS
				&osm_l3 SLAVE_OSM_L3_CLUSTER0>;
	};

	cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
		qcom,core-dev-table =
			<  300000  300000000 >,
			<  480000  403200000 >,
			<  672000  480000000 >,
			<  768000  576000000 >,
			<  864000  672000000 >,
			<  979200  768000000 >,
			< 1075200  864000000 >,
			< 1267200  960000000 >;
	};

	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
		compatible = "qcom,devfreq-icc";
		governor = "performance";
		interconnects = <&gem_noc MASTER_APPSS_PROC
				&gem_noc SLAVE_LLCC>;
		qcom,active-only;
		operating-points-v2 = <&llcc_bw_opp_table>;
	};

	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
		compatible = "qcom,arm-memlat-cpugrp";
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
			qcom,target-dev = <&cpu0_cpu_l3_lat>;
			qcom,cachemiss-ev = <0x17>;
			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
		};

		cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,target-dev = <&cpu0_cpu_llcc_lat>;
			qcom,cachemiss-ev = <0x2A>;
			qcom,core-dev-table =
				<  300000 MHZ_TO_MBPS(150, 16) >,
				<  768000 MHZ_TO_MBPS(200, 16) >,
				< 1075200 MHZ_TO_MBPS(403, 16) >,
				< 1267200 MHZ_TO_MBPS(403, 16) >;
		};

		cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
			qcom,target-dev = <&cpu0_llcc_ddr_lat>;
			qcom,cachemiss-ev = <0x1000>;
			qcom,core-dev-table =
				<  300000 MHZ_TO_MBPS( 200, 4) >,
				<  768000 MHZ_TO_MBPS( 451, 4) >,
				< 1075200 MHZ_TO_MBPS( 547, 4) >,
				< 1267200 MHZ_TO_MBPS( 768, 4) >;
		};
	};

	cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {
		compatible = "qcom,devfreq-icc-l3";
		reg = <0x18321110 0x500>;
		reg-names = "ftbl-base";
		qcom,ftbl-row-size = <0x20>;
		governor = "performance";
		interconnects = <&osm_l3 MASTER_OSM_L3_APPS
				&osm_l3 SLAVE_OSM_L3_CLUSTER1>;
	};

	cpu4_cpu_l3_tbl: qcom,cpu4_cpu_l3_tbl {
		qcom,core-dev-table =
			<  300000  300000000 >,
			<  768000  576000000 >,
			< 1152000  768000000 >,
			< 1344000  960000000 >,
			< 1689600 1228800000 >,
			< 2016000 1344000000 >;
	};

	cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {
		compatible = "qcom,devfreq-icc";
		governor = "performance";
		interconnects = <&gem_noc MASTER_APPSS_PROC
				&gem_noc SLAVE_LLCC>;
		qcom,active-only;
		operating-points-v2 = <&llcc_bw_opp_table>;
	};

	cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {
		compatible = "qcom,devfreq-icc-l3";
		reg = <0x18321110 0x500>;
		reg-names = "ftbl-base";
		qcom,ftbl-row-size = <0x20>;
		governor = "performance";
		interconnects = <&osm_l3 MASTER_OSM_L3_APPS
				&osm_l3 SLAVE_OSM_L3_CLUSTER2>;
	};

	cpu7_cpu_l3_tbl: qcom,cpu7_cpu_l3_tbl {
		qcom,core-dev-table =
			<  300000  300000000 >,
			<  768000  576000000 >,
			< 1152000  768000000 >,
			< 1344000  960000000 >,
			< 1689600 1228800000 >,
			< 2016000 1344000000 >;
	};

	cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
		compatible = "qcom,arm-memlat-cpugrp";
		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

		cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
			qcom,target-dev = <&cpu4_cpu_l3_lat>;
			qcom,cachemiss-ev = <0x17>;
			qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
		};

		cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU7>;
			qcom,target-dev = <&cpu7_cpu_l3_lat>;
			qcom,cachemiss-ev = <0x17>;
			qcom,core-dev-table = <&cpu7_cpu_l3_tbl>;
		};

		cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,target-dev = <&cpu4_cpu_llcc_lat>;
			qcom,cachemiss-ev = <0x2A>;
			qcom,core-dev-table =
				<  300000 MHZ_TO_MBPS(150, 16) >,
				<  576000 MHZ_TO_MBPS(200, 16) >,
				<  768000 MHZ_TO_MBPS(403, 16) >,
				<  960000 MHZ_TO_MBPS(403, 16) >,
				< 1248000 MHZ_TO_MBPS(533, 16) >,
				< 1728000 MHZ_TO_MBPS(666, 16) >,
				< 2016000 MHZ_TO_MBPS(777, 16) >;
		};

		cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
			qcom,target-dev = <&cpu4_llcc_ddr_lat>;
			qcom,cachemiss-ev = <0x1000>;
			qcom,core-dev-table =
				<  300000 MHZ_TO_MBPS( 200, 4) >,
				<  576000 MHZ_TO_MBPS( 451, 4) >,
				<  768000 MHZ_TO_MBPS( 547, 4) >,
				<  960000 MHZ_TO_MBPS( 768, 4) >,
				< 1248000 MHZ_TO_MBPS(1017, 4) >,
				< 1728000 MHZ_TO_MBPS(1555, 4) >,
				< 2016000 MHZ_TO_MBPS(1804, 4) >,
				< 2054400 MHZ_TO_MBPS(2092, 4) >;
		};

		cpu4_computemon: qcom,cpu4-computemon {
			compatible = "qcom,arm-compute-mon";
			qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
			qcom,core-dev-table =
				< 1593600 MHZ_TO_MBPS( 200, 4) >,
				< 2016000 MHZ_TO_MBPS(1017, 4) >,
				< 2054400 MHZ_TO_MBPS(2092, 4) >;
		};
	};

	npu_npu_ddr_bw: qcom,npu-npu-ddr-bw {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>;
		operating-points-v2 = <&ddr_bw_opp_table>;
		qcom,active-only;
	};

	npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 {
		compatible = "qcom,bimc-bwmon4";
		reg = <0x9960300 0x300>, <0x9960200 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&npu_npu_ddr_bw>;
		qcom,count-unit = <0x10000>;
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	restart@c264000 {
		compatible = "qcom,pshold";
		reg = <0xc264000 0x4>,
		      <0x1fd3000 0x4>;
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	pil_scm_pas {
		compatible = "qcom,pil-tz-scm-pas";
		interconnects = <&aggre2_noc MASTER_CRYPTO
				&mc_virt SLAVE_EBI1>;
	};

	apps_rsc: rsc@18200000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x18200000 0x10000>,
		      <0x18210000 0x10000>,
		      <0x18220000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0xd00>;
		qcom,drv-id = <2>;
		qcom,tcs-config = <ACTIVE_TCS  2>,
				  <SLEEP_TCS   3>,
				  <WAKE_TCS    3>,
				  <CONTROL_TCS 1>;

		apps_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
		};

		rpmhcc: clock-controller {
			compatible = "qcom,sm8150-rpmh-clk";
			#clock-cells = <1>;
			clock-names = "xo";
			clocks = <&xo_board>;
			status = "okay";
		};

		system_pm {
			compatible = "qcom,system-pm";
		};
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x10000>;
		reg-names = "drv-0";
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0x1c00>;
		qcom,drv-id = <0>;
		qcom,tcs-config = <SLEEP_TCS   1>,
				  <WAKE_TCS    1>,
				  <ACTIVE_TCS  2>,
				  <CONTROL_TCS 0>;

		disp_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
			qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
		};

	};

	aopcc: qcom,aopcc {
		compatible = "qcom,aop-qmp-clk";
		mboxes = <&qmp_aop 0>;
		mbox-names = "qdss_clk";
		#clock-cells = <1>;
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,sm8150-gcc", "syscon";
		reg = <0x100000 0x1f0000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>;
		clock-names = "bi_tcxo", "bi_tcxo_ao";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@ab00000 {
		compatible = "qcom,sm8150-videocc", "syscon";
		reg = <0xab00000 0x10000>;
		reg-names = "cc_base";
		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
		clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "cfg_ahb_clk", "bi_tcxo";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	camcc: clock-controller@ad00000 {
		compatible = "qcom,sm8150-camcc", "syscon";
		reg = <0xad00000 0x10000>;
		reg-names = "cc_base";
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
		clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "cfg_ahb_clk", "bi_tcxo";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,sm8150-dispcc", "syscon";
		reg = <0xaf00000 0x20000>;
		reg-names = "cc_base";
		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
		clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "cfg_ahb_clk", "bi_tcxo";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	npucc: clock-controller@9910000 {
		compatible = "qcom,sm8150-npucc", "syscon";
		reg = <0x9910000 0x10000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_gdsc-supply = <&npu_core_gdsc>;
		clocks =
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
			<&gcc GCC_NPU_GPLL0_CLK_SRC>,
			<&gcc GCC_NPU_AXI_CLK>;
		clock-names =
			"bi_tcxo",
			"gcc_npu_gpll0_div_clk_src",
			"gcc_npu_gpll0_clk_src",
			"gcc_npu_axi_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@2c90000 {
		compatible = "qcom,sm8150-gpucc", "syscon";
		reg = <0x2c90000 0x9000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks =
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_GPU_GPLL0_CLK_SRC>,
			<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
		clock-names = "bi_tcxo",
			"gcc_gpu_gpll0_clk_src",
			"gcc_gpu_gpll0_div_clk_src";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	scc: clock-controller@2b10000 {
		compatible = "qcom,sm8150-scc", "syscon";
		reg = <0x2b10000 0x30000>;
		vdd_scc_cx-supply = <&pm8150_l8_level>;
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "bi_tcxo";
		#clock-cells = <1>;
		status = "disabled";
	};

	cpucc: syscon@182a0000 {
		compatible = "syscon";
		reg = <0x182a0000 0x4>;
	};

	mccc: syscon@90b0000 {
		compatible = "syscon";
		reg = <0x90b0000 0x1000>;
	};

	debugcc: debug-clock-controller@0 {
		compatible = "qcom,sm8150-debugcc";
		qcom,gcc = <&gcc>;
		qcom,videocc = <&videocc>;
		qcom,camcc = <&camcc>;
		qcom,dispcc = <&dispcc>;
		qcom,npucc = <&npucc>;
		qcom,gpucc = <&gpucc>;
		qcom,cpucc = <&cpucc>;
		qcom,mccc = <&mccc>;
		clock-names = "xo_clk_src";
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		#clock-cells = <1>;
	};

	cpufreq_hw: cpufreq@18323000 {
		compatible = "qcom,cpufreq-hw";
		reg = <0x18323000 0x1400>, <0x18325800 0x1400>,
		      <0x18327800 0x1400>;
		reg-names = "freq-domain0", "freq-domain1",
			    "freq-domain2";

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
		clock-names = "xo", "alternate";
		qcom,no-accumulative-counter;

		#freq-domain-cells = <2>;
	};

	qcom_clk_led: qcom_clk_led {
		compatible = "qcom,clk-led-pwm";
		qcom,label = "led_clk_gp2";
		clocks = <&gcc GCC_GP2_CLK>;
		clock-names = "core";
		assigned-clocks = <&gcc GCC_GP2_CLK>;
		assigned-clock-rates = <80000>;
		qcom,max_duty = <53>;
		pinctrl-names = "active", "sleep";
		pinctrl-0 = <&qcom_clk_led_gp2_active>;
		pinctrl-1 = <&qcom_clk_led_gp2_sleep>;
		status = "disabled";
	};

	spmi_bus: qcom,spmi@c440000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc440000 0x1100>,
		      <0xc600000 0x2000000>,
		      <0xe600000 0x100000>,
		      <0xe700000 0xa0000>,
		      <0xc40a000 0x26000>;
		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
	};

	spmi_debug_bus: qcom,spmi-debug@6b22000 {
		compatible = "qcom,spmi-pmic-arb-debug";
		reg = <0x6b22000 0x60>, <0x7820a8 0x4>;
		reg-names = "core", "fuse";
		clocks = <&aopcc QDSS_CLK>;
		clock-names = "core_clk";
		qcom,fuse-disable-bit = <24>;
		#address-cells = <2>;
		#size-cells = <0>;
		status = "disabled";

		qcom,pm8150-debug@0 {
			compatible = "qcom,spmi-pmic";
			reg = <0 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8150-debug@1 {
			compatible = "qcom,spmi-pmic";
			reg = <1 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8150b-debug@2 {
			compatible = "qcom,spmi-pmic";
			reg = <2 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8150b-debug@3 {
			compatible = "qcom,spmi-pmic";
			reg = <3 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8150l-debug@4 {
			compatible = "qcom,spmi-pmic";
			reg = <4 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8150l-debug@5 {
			compatible = "qcom,spmi-pmic";
			reg = <5 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};
	};

	thermal_zones: thermal-zones {
	};

	osm_l3: interconnect@18321000 {
		reg = <0x18321000 0x1400>;
		compatible = "qcom,sm8150-osm-l3";
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
		clock-names = "xo", "alternate";
		#interconnect-cells = <1>;
	};

	config_noc: interconnect@1500000 {
		reg = <0x1500000 0x7400>;
		compatible = "qcom,sm8150-config_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	system_noc: interconnect@1620000 {
		reg = <0x1620000 0x19400>;
		compatible = "qcom,sm8150-system_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	camnoc_virt: interconnect@1630000 {
		compatible = "qcom,sm8150-camnoc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	ipa_virt: interconnect@1640000 {
		compatible = "qcom,sm8150-ipa_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	aggre1_noc: interconnect@16e0000 {
		reg = <0x16E0000 0xD080>;
		compatible = "qcom,sm8150-aggre1_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
			<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
	};

	aggre2_noc: interconnect@1700000 {
		reg = <0x1700000 0x3B100>;
		compatible = "qcom,sm8150-aggre2_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	compute_noc: interconnect@1710000 {
		compatible = "qcom,sm8150-compute_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mmss_noc: interconnect@1740000 {
		reg = <0x1740000 0x1C100>;
		compatible = "qcom,sm8150-mmss_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	dc_noc: interconnect@9160000 {
		reg = <0x9160000 0x3200>;
		compatible = "qcom,sm8150-dc_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	gem_noc: interconnect@9680000 {
		reg = <0x9680000 0x3E200>;
		compatible = "qcom,sm8150-gem_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	mc_virt: interconnect@9690000 {
		compatible = "qcom,sm8150-mc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};


	ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xda8>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_UFS_MEM_CLKREF_CLK>,
			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		resets = <&ufshc_mem 0>;
		status = "disabled";
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x2500>,
			  <0x1d90000 0x8000>;
		reg-names = "ufs_mem", "ufs_ice";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		#reset-cells = <1>;

		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		clocks =
			<&gcc GCC_UFS_PHY_AXI_CLK>,
			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&gcc GCC_UFS_PHY_AHB_CLK>,
			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<37500000 300000000>,
			<0 0>,
			<0 0>,
			<37500000 300000000>,
			<37500000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;
		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
		interconnect-names = "ufs-ddr", "cpu-ufs";

		qcom,ufs-bus-bw,name = "ufshc_mem";
		qcom,ufs-bus-bw,num-cases = <26>;
		qcom,ufs-bus-bw,num-paths = <2>;
		qcom,ufs-bus-bw,vectors-KBps =
		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<0 0>, <0 0>,          /* No vote */
		<922 0>, <1000 0>,     /* PWM G1 */
		<1844 0>, <1000 0>,    /* PWM G2 */
		<3688 0>, <1000 0>,    /* PWM G3 */
		<7376 0>, <1000 0>,    /* PWM G4 */
		<1844 0>, <1000 0>,    /* PWM G1 L2 */
		<3688 0>, <1000 0>,    /* PWM G2 L2 */
		<7376 0>, <1000 0>,    /* PWM G3 L2 */
		<14752 0>, <1000 0>,   /* PWM G4 L2 */
		<127796 0>, <1000 0>,  /* HS G1 RA */
		<255591 0>, <1000 0>,  /* HS G2 RA */
		<2097152 0>, <102400 0>,  /* HS G3 RA */
		<4194304 0>, <204800 0>,  /* HS G4 RA */
		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
		<4194304 0>, <204800 0>, /* HS G3 RA L2 */
		<8388608 0>, <409600 0>, /* HS G4 RA L2 */
		<149422 0>, <1000 0>,  /* HS G1 RB */
		<298189 0>, <1000 0>,  /* HS G2 RB */
		<2097152 0>, <102400 0>,  /* HS G3 RB */
		<4194304 0>, <204800 0>,  /* HS G4 RB */
		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
		/* As UFS working in HS G3 RB L2 mode, aggregated
		 * bandwidth (AB) should take care of providing
		 * optimum throughput requested. However, as tested,
		 * in order to scale up CNOC clock, instantaneous
		 * bindwidth (IB) needs to be given a proper value too.
		 */
		<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
		<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
		<7643136 0>, <307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
		"MAX";

		reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;

		resets = <&gcc GCC_UFS_PHY_BCR>;
		reset-names = "rst";

		status = "disabled";
		qos0 {
			mask = <0xf0>;
			vote = <44>;
		};

		qos1 {
			mask = <0x0f>;
			vote = <44>;
		};
	};

	qcom,rmtfs_sharedmem@0 {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0 0x200000>;
		reg-names = "rmtfs";
		qcom,client-id = <0x00000001>;
		qcom,guard-memory;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock@1f40000 {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem@8600000 {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;
		hwlocks = <&tcsr_mutex 3>;
	};

	apcs: syscon@17c0000c {
		compatible = "syscon";
		reg = <0x17c0000c 0x4>;
	};



	ufs_ice: ufsice@1d90000 {
		compatible = "qcom,ice";
		reg = <0x1d90000 0x8000>;
		qcom,enable-ice-clk;
		clock-names = "ufs_core_clk", "bus_clk",
			      "iface_clk", "ice_core_clk";
		clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
			 <&gcc GCC_UFS_MEM_CLKREF_CLK>,
			 <&gcc GCC_UFS_PHY_AHB_CLK>,
			 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
		vdd-hba-supply = <&ufs_phy_gdsc>;
		qcom,bus-vector-names = "MIN",
					"MAX";
		qcom,instance-type = "ufs";
	};


	apss_shared: mailbox@17c00000 {
		compatible = "qcom,sm8150-apss-shared";
		reg = <0x17c00000 0x1000>;

		#mbox-cells = <1>;
	};

	sp_scsr: mailbox@188501c {
		compatible = "qcom,sm8150-spcs-global";
		reg = <0x188501c 0x4>;

		#mbox-cells = <1>;
	};

	sp_scsr_block: syscon@1880000 {
		compatible = "syscon";
		reg = <0x1880000 0x10000>;
	};

	intsp: qcom,qsee_irq {
		compatible = "qcom,sm8150-qsee-irq";

		syscon = <&sp_scsr_block>;
		interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>,
			     <0 349 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "sp_ipc0",
				  "sp_ipc1";

		interrupt-controller;
		#interrupt-cells = <3>;
	};

	qcom,qsee_irq_bridge {
		compatible = "qcom,qsee-ipc-irq-bridge";

		qcom,qsee-ipc-irq-spss {
			qcom,dev-name = "qsee_ipc_irq_spss";
			label = "spss";
			interrupt-parent = <&intsp>;
			interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	qcom,msm-cdsp-loader {
		compatible = "qcom,cdsp-loader";
		qcom,proc-img-to-load = "cdsp";
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem>;
	};

	msm_fastrpc: qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";
		qcom,fastrpc-adsp-audio-pdr;
		qcom,rpc-latency-us = <235>;

		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1401 0x2040>,
				 <&apps_smmu 0x1421 0x0>,
				 <&apps_smmu 0x2001 0x420>,
				 <&apps_smmu 0x2041 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb4 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x4 0x3440>,
				 <&apps_smmu 0x24 0x3400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb5 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x5 0x3440>,
				 <&apps_smmu 0x25 0x3400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb6 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x6 0x3460>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb7 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x7 0x3460>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb8 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x8 0x3460>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb2 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2 0x3440>,
				 <&apps_smmu 0x22 0x3400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb3 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x3 0x3440>,
				 <&apps_smmu 0x1423 0x0>,
				 <&apps_smmu 0x2023 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb9 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			qcom,secure-context-bank;
			iommus = <&apps_smmu 0x9 0x3460>;
			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb10 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1b23 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb11 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1b24 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb12 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1b25 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb13 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "sdsprpc-smd";
			iommus = <&apps_smmu 0x5a1 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb14 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "sdsprpc-smd";
			iommus = <&apps_smmu 0x5a2 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb15 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "sdsprpc-smd";
			iommus = <&apps_smmu 0x5a3 0x0>;
			shared-cb = <4>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};
	};

	qcom,glink {
		compatible = "qcom,glink";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		glink_modem: modem {
			qcom,remote-pid = <1>;
			transport = "smem";
			mboxes = <&apss_shared 12>;
			mbox-names = "mpss_smem";
			interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;

			label = "modem";
			qcom,glink-label = "mpss";

			qcom,modem_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,low-latency;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,modem_ds {
				qcom,glink-channels = "DS";
				qcom,intents = <0x4000 0x2>;
			};

			qcom,modem_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_adsp>,
						    <&glink_slpi>,
						    <&glink_cdsp>,
						    <&glink_spss>;
			};
		};

		glink_adsp: adsp {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&apss_shared 8>;
			mbox-names = "adsp_smem";
			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";
			cpu-affinity = <1 2>;

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,apr_tal_rpmsg {
				qcom,glink-channels = "apr_audio_svc";
				qcom,intents = <0x200 20>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,adsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>,
						    <&glink_slpi>,
						    <&glink_cdsp>;
			};
		};

		glink_slpi: dsps {
			qcom,remote-pid = <3>;
			transport = "smem";
			mboxes = <&apss_shared 24>;
			mbox-names = "dsps_smem";
			interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;

			label = "slpi";
			qcom,glink-label = "dsps";

			qcom,slpi_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,low-latency;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,slpi_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>,
						    <&glink_adsp>,
						    <&glink_cdsp>;
			};
		};

		glink_cdsp: cdsp {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&apss_shared 4>;
			mbox-names = "cdsp_smem";
			interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,msm_cdsprm_rpmsg {
				compatible = "qcom,msm-cdsprm-rpmsg";
				qcom,glink-channels = "cdsprmglink-apps-dsp";
				qcom,intents = <0x20 12>;

				qcom,cdsp-cdsp-l3-gov {
					compatible = "qcom,cdsp-l3";
				/*	qcom,target-dev = <&cdsp_cdsp_l3_lat>;*/
				};

				msm_cdsp_rm: qcom,msm_cdsp_rm {
					compatible = "qcom,msm-cdsp-rm";
					qcom,qos-latency-us = <44>;
					qcom,qos-maxhold-ms = <20>;
					qcom,compute-cx-limit-en;
					qcom,compute-priority-mode = <2>;
					#cooling-cells = <2>;
				};

				msm_hvx_rm: qcom,msm_hvx_rm {
					compatible = "qcom,msm-hvx-rm";
					#cooling-cells = <2>;
				};
			};

			qcom,cdsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>,
						    <&glink_adsp>,
						    <&glink_slpi>;
			};
		};

		glink_spss: spss {
			qcom,remote-pid = <8>;
			transport = "spss";
			mboxes = <&sp_scsr 0>;
			mbox-names = "spss_spss";
			interrupt-parent = <&intsp>;
			interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x1885008 0x8>,
			      <0x1885010 0x4>;
			reg-names = "qcom,spss-addr",
				    "qcom,spss-size";

			label = "spss";
			qcom,glink-label = "spss";

			qcom,spss_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>;
			};
		};

		glink_spi_xprt_wdsp: wdsp {
			transport = "spi";
			tx-descriptors = <0x12000 0x12004>;
			rx-descriptors = <0x1200c 0x12010>;

			label = "wdsp";
			qcom,glink-label = "wdsp";

			qcom,wdsp_ctrl {
				qcom,glink-channels = "g_glink_ctrl";
				qcom,intents = <0x400 1>;
			};

			qcom,wdsp_ild {
				qcom,glink-channels =
					"g_glink_persistent_data_ild";
			};

			qcom,wdsp_nild {
				qcom,glink-channels =
					"g_glink_persistent_data_nild";
			};

			qcom,wdsp_data {
				qcom,glink-channels = "g_glink_audio_data";
				qcom,intents = <0x1000 2>;
			};

			qcom,diag_data {
				qcom,glink-channels = "DIAG_DATA";
				qcom,intents = <0x4000 2>;
			};

			qcom,diag_ctrl {
				qcom,glink-channels = "DIAG_CTRL";
				qcom,intents = <0x4000 1>;
			};

			qcom,diag_cmd {
				qcom,glink-channels = "DIAG_CMD";
				qcom,intents = <0x4000 1>;
			};
		};
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};

		qcom,glinkpkt-data40-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA40_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl8";
		};

		qcom,glinkpkt-data1 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA1";
			qcom,glinkpkt-dev-name = "smd7";
		};

		qcom,glinkpkt-data4 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA4";
			qcom,glinkpkt-dev-name = "smd8";
		};

		qcom,glinkpkt-data11 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA11";
			qcom,glinkpkt-dev-name = "smd11";
		};
	};

	qmp_aop: qcom,qmp-aop@c300000 {
		compatible = "qcom,qmp-mbox";
		reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;
		reg-names = "msgram", "irq-reg-base";
		qcom,irq-mask = <0x1>;
		interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

		label = "aop";
		qcom,early-boot;
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	sdhc_2: sdhci@8804000 {
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x8804000 0x1000>;
		reg-names = "hc_mem";

		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
			<&gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface", "core";

		bus-width = <4>;
		qcom,restore-after-cx-collapse;

		interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
		interconnect-names = "sdhc-ddr","cpu-sdhc";

		qcom,msm-bus,name = "sdhc2";
		qcom,msm-bus,num-cases = <6>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
			/* No vote */
			<0 0>, <0 0>,
			/* 25 MB/s */
			<65360 100000>,<100000 100000>,
			/* 50 MB/s */
			<130718 200000>,<133320 133320>,
			/* 100 MB/s */
			<261438 200000>,<150000 150000>,
			/* 200 MB/s */
			<261438 400000>,<300000 300000>,
			/* Max. bandwidth */
			<1338562 4096000>,<1338562 4096000>;
		qcom,bus-bw-vectors-bps = <0 25000000 50000000 100750000
				200000000 4294967295>;

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;

		qcom,devfreq,freq-table = <50000000 201500000>;

		status = "disabled";

		qos0 {
			mask = <0x3f>;
			vote = <44>;
		};

		qos1 {
			mask = <0xc0>;
			vote = <44>;
		};
	};

	pil_modem: qcom,mss@4080000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x4080000 0x100>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		vdd_mss-supply = <&pm8150_s1_level>;
		qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		qcom,proxy-reg-names = "vdd_cx", "vdd_mss";

		qcom,firmware-name = "modem";
		memory-region = <&pil_modem_mem>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,sysmon-id = <0>;
		qcom,minidump-id = <3>;
		qcom,aux-minidump-ids = <4>;
		qcom,ssctl-instance-id = <0x12>;
		qcom,pas-id = <4>;
		qcom,smem-id = <421>;
		qcom,signal-aop;
		qcom,complete-ramdump;

		/* Inputs from mss */
		interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				<&modem_smp2p_in 0 0>,
				<&modem_smp2p_in 2 0>,
				<&modem_smp2p_in 1 0>,
				<&modem_smp2p_in 3 0>,
				<&modem_smp2p_in 7 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack",
				"qcom,shutdown-ack";

		/* Outputs to mss */
		qcom,smem-states = <&modem_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		mboxes = <&qmp_aop 0>;
		mbox-names = "mss-pil";
	};

	qcom,lpass@17300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x17300000 0x00100>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		qcom,proxy-reg-names = "vdd_cx","vdd_mx";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <1>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <423>;
		qcom,sysmon-id = <1>;
		qcom,ssctl-instance-id = <0x14>;
		qcom,firmware-name = "adsp";
		memory-region = <&pil_adsp_mem>;
		qcom,signal-aop;
		qcom,complete-ramdump;

		/* Inputs from lpass */
		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
				<&adsp_smp2p_in 0 0>,
				<&adsp_smp2p_in 2 0>,
				<&adsp_smp2p_in 1 0>,
				<&adsp_smp2p_in 3 0>,
				<&adsp_smp2p_in 7 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack",
				"qcom,shutdown-ack";

		/* Outputs to lpass */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		mboxes = <&qmp_aop 0>;
		mbox-names = "adsp-pil";
	};

	pil_ssc: qcom,ssc@5c00000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x5c00000 0x4000>;

		vdd_cx-supply = <&pm8150_l8_level>;
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		vdd_mx-supply = <&pm8150_l4_level>;
		qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;

		qcom,proxy-reg-names = "vdd_cx", "vdd_mx";
		qcom,keep-proxy-regs-on;

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <12>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <424>;
		qcom,sysmon-id = <3>;
		qcom,ssctl-instance-id = <0x16>;
		qcom,firmware-name = "slpi";
		status = "ok";
		memory-region = <&pil_slpi_mem>;
		qcom,signal-aop;
		qcom,complete-ramdump;

		/* Inputs from ssc */
		interrupts-extended = <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
				<&dsps_smp2p_in 0 0>,
				<&dsps_smp2p_in 2 0>,
				<&dsps_smp2p_in 1 0>,
				<&dsps_smp2p_in 3 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack";

		/* Outputs to ssc */
		qcom,smem-states = <&dsps_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		mboxes = <&qmp_aop 0>;
		mbox-names = "slpi-pil";
	};

	qcom,spss@188101c {
		compatible = "qcom,pil-tz-generic";
		reg = <0x188101c 0x4>,
		      <0x1881024 0x4>,
		      <0x1881028 0x4>,
		      <0x188103c 0x4>,
		      <0x1882014 0x4>;
		reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
			    "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";
		interrupts = <0 352 1>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		qcom,pil-generic-irq-handler;
		status = "ok";
		qcom,signal-aop;
		qcom,complete-ramdump;

		qcom,pas-id = <14>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,firmware-name = "spss";
		memory-region = <&pil_spss_mem>;
		qcom,spss-scsr-bits = <24 25>;

		mboxes = <&qmp_aop 0>;
		mbox-names = "spss-pil";
	};

	qcom,npu@9800000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x9800000 0x800000>;

		status = "ok";
		qcom,pas-id = <23>;
		qcom,firmware-name = "npu";

		memory-region = <&pil_npu_mem>;
	};

	qcom,turing@8300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x8300000 0x100000>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <18>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <601>;
		qcom,sysmon-id = <7>;
		qcom,ssctl-instance-id = <0x17>;
		qcom,firmware-name = "cdsp";
		memory-region = <&pil_cdsp_mem>;
		qcom,signal-aop;
		qcom,complete-ramdump;

		qcom,msm-bus,name = "pil-cdsp";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<154 10070 0 0>,
			<154 10070 0 1>;

		/* Inputs from turing */
		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
				<&cdsp_smp2p_in 0 0>,
				<&cdsp_smp2p_in 2 0>,
				<&cdsp_smp2p_in 1 0>,
				<&cdsp_smp2p_in 3 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack";

		/* Outputs to turing */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		mboxes = <&qmp_aop 0>;
		mbox-names = "cdsp-pil";
	};

	qcom,venus@aae0000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0xaae0000 0x4000>;

		vdd-supply = <&mvsc_gdsc>;
		qcom,proxy-reg-names = "vdd";
		qcom,complete-ramdump;

		clocks = <&videocc VIDEO_CC_XO_CLK>,
			<&videocc VIDEO_CC_MVSC_CORE_CLK>,
			<&videocc VIDEO_CC_IRIS_AHB_CLK>;
		clock-names = "xo", "core", "ahb";
		qcom,proxy-clock-names = "xo",  "core", "ahb";

		qcom,core-freq = <200000000>;
		qcom,ahb-freq = <200000000>;

		qcom,pas-id = <9>;
		interconnect-names = "pil-venus";
		interconnects = <&mmss_noc MASTER_VIDEO_P0
				&mc_virt SLAVE_EBI1>;
		qcom,proxy-timeout-ms = <100>;
		qcom,firmware-name = "venus";
		memory-region = <&pil_video_mem>;
	};

	cache-controller@9200000 {
		compatible = "qcom,sm8150-llcc";
		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
		reg-names = "llcc_base", "llcc_broadcast_base";
		cap-based-alloc-and-pwr-collapse;
	};

	wdog: qcom,wdt@17c10000 {
		compatible = "qcom,msm-watchdog";
		reg = <0x17c10000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <9360>;
		qcom,ipi-ping;
		qcom,wakeup-enable;
	};

	qcom,chd_sliver {
		compatible = "qcom,core-hang-detect";
		label = "silver";
		qcom,threshold-arr = <0x18000058 0x18010058
					0x18020058 0x18030058>;
		qcom,config-arr = <0x18000060 0x18010060
					0x18020060 0x18030060>;
	};

	qcom,chd_gold {
		compatible = "qcom,core-hang-detect";
		label = "gold";
		qcom,threshold-arr = <0x18040058 0x18050058
					0x18060058 0x18070058>;
		qcom,config-arr = <0x18040060 0x18050060
					0x18060060 0x18070060>;
	};

	mem_dump {
		compatible = "qcom,mem-dump";
		memory-region = <&dump_mem>;

		rpmh {
			qcom,dump-size = <0x2000000>;
			qcom,dump-id = <0xec>;
		};

		rpm_sw {
			qcom,dump-size = <0x28000>;
			qcom,dump-id = <0xea>;
		};

		pmic {
			qcom,dump-size = <0x80000>;
			qcom,dump-id = <0xe4>;
		};

		fcm {
			qcom,dump-size = <0x8400>;
			qcom,dump-id = <0xee>;
		};

		tmc_etf {
			qcom,dump-size = <0x10000>;
			qcom,dump-id = <0xf0>;
		};

		etf_swao {
			qcom,dump-size = <0x8400>;
			qcom,dump-id = <0xf1>;
		};

		etr_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x100>;
		};

		etf_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x101>;
		};

		etfswao_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x102>;
		};

		misc_data {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xe8>;
		};

		l1_icache0 {
			qcom,dump-size = <0x10900>;
			qcom,dump-id = <0x60>;
		};

		l1_icache100 {
			qcom,dump-size = <0x10900>;
			qcom,dump-id = <0x61>;
		};

		l1_icache200 {
			qcom,dump-size = <0x10900>;
			qcom,dump-id = <0x62>;
		};

		l1_icache300 {
			qcom,dump-size = <0x10900>;
			qcom,dump-id = <0x63>;
		};

		l1_icache400 {
			qcom,dump-size = <0x11100>;
			qcom,dump-id = <0x64>;
		};

		l1_icache500 {
			qcom,dump-size = <0x11100>;
			qcom,dump-id = <0x65>;
		};

		l1_icache600 {
			qcom,dump-size = <0x11100>;
			qcom,dump-id = <0x66>;
		};

		l1_icache700 {
			qcom,dump-size = <0x11100>;
			qcom,dump-id = <0x67>;
		};

		l1_dcache0 {
			qcom,dump-size = <0x9100>;
			qcom,dump-id = <0x80>;
		};

		l1_dcache100 {
			qcom,dump-size = <0x9100>;
			qcom,dump-id = <0x81>;
		};

		l1_dcache200 {
			qcom,dump-size = <0x9100>;
			qcom,dump-id = <0x82>;
		};

		l1_dcache300 {
			qcom,dump-size = <0x9100>;
			qcom,dump-id = <0x83>;
		};

		l1_dcache400 {
			qcom,dump-size = <0x12100>;
			qcom,dump-id = <0x84>;
		};

		l1_dcache500 {
			qcom,dump-size = <0x12100>;
			qcom,dump-id = <0x85>;
		};

		l1_dcache600 {
			qcom,dump-size = <0x12100>;
			qcom,dump-id = <0x86>;
		};

		l1_dcache700 {
			qcom,dump-size = <0x12100>;
			qcom,dump-id = <0x87>;
		};

		l1_itlb400 {
			qcom,dump-size = <0x400>;
			qcom,dump-id = <0x24>;
		};

		l1_itlb500 {
			qcom,dump-size = <0x400>;
			qcom,dump-id = <0x25>;
		};

		l1_itlb600 {
			qcom,dump-size = <0x400>;
			qcom,dump-id = <0x26>;
		};

		l1_itlb700 {
			qcom,dump-size = <0x400>;
			qcom,dump-id = <0x27>;
		};

		l1_dtlb400 {
			qcom,dump-size = <0x580>;
			qcom,dump-id = <0x44>;
		};

		l1_dtlb500 {
			qcom,dump-size = <0x580>;
			qcom,dump-id = <0x45>;
		};

		l1_dtlb600 {
			qcom,dump-size = <0x580>;
			qcom,dump-id = <0x46>;
		};

		l1_dtlb700 {
			qcom,dump-size = <0x580>;
			qcom,dump-id = <0x47>;
		};

		l2_cache400 {
			qcom,dump-size = <0x48100>;
			qcom,dump-id = <0xc4>;
		};

		l2_cache500 {
			qcom,dump-size = <0x48100>;
			qcom,dump-id = <0xc5>;
		};

		l2_cache600 {
			qcom,dump-size = <0x48100>;
			qcom,dump-id = <0xc6>;
		};

		l2_cache700 {
			qcom,dump-size = <0x90100>;
			qcom,dump-id = <0xc7>;
		};

		l2_tlb0 {
			qcom,dump-size = <0x5B00>;
			qcom,dump-id = <0x120>;
		};

		l2_tlb100 {
			qcom,dump-size = <0x5B00>;
			qcom,dump-id = <0x121>;
		};

		l2_tlb200 {
			qcom,dump-size = <0x5B00>;
			qcom,dump-id = <0x122>;
		};

		l2_tlb300 {
			qcom,dump-size = <0x5B00>;
			qcom,dump-id = <0x123>;
		};

		l2_tlb400 {
			qcom,dump-size = <0x7900>;
			qcom,dump-id = <0x124>;
		};

		l2_tlb500 {
			qcom,dump-size = <0x7900>;
			qcom,dump-id = <0x125>;
		};

		l2_tlb600 {
			qcom,dump-size = <0x7900>;
			qcom,dump-id = <0x126>;
		};

		l2_tlb700 {
			qcom,dump-size = <0x7900>;
			qcom,dump-id = <0x127>;
		};
	};
	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
	};

	qcom_qseecom: qseecom@87900000 {
		compatible = "qcom,qseecom";
		reg = <0x87900000 0x2200000>;
		reg-names = "secapp-region";
		memory-region = <&qseecom_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,support-fde;
		qcom,no-clock-support;
		qcom,fde-key-size;
		qcom,appsbl-qseecom-support;
		qcom,commonlib64-loaded-by-uefi;
		qcom,qsee-reentrancy-support = <2>;
	};

	qcom_rng: qrng@793000 {
		compatible = "qcom,msm-rng";
		reg = <0x793000 0x1000>;
		qcom,no-qrng-config;
		interconnect-names = "data_path";
		interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_PRNG>;
		clock-names = "km_clk_src";
		clocks = <&gcc GCC_PRNG_AHB_CLK>;
	};

	qcom_smcinvoke: smcinvoke@87900000 {
		compatible = "qcom,smcinvoke";
		reg = <0x87900000 0x2200000>;
		reg-names = "secapp-region";
	};

	qcom_tzlog: tz-log@146bf720 {
		compatible = "qcom,tz-log";
		reg = <0x146bf720 0x3000>;
		qcom,hyplog-enabled;
		hyplog-address-offset = <0x410>;
		hyplog-size-offset = <0x414>;
	};

	spss_utils: qcom,spss_utils {
		compatible = "qcom,spss-utils";
		/* Boolean property to differentiate supported features*/
		qcom,no-cmac-and-iar-feature-support;
		qcom,no-cmac-support;
		/* spss fuses physical address */
		qcom,spss-fuse1-addr = <0x007841c4>;
		qcom,spss-fuse1-bit = <27>;
		qcom,spss-fuse2-addr = <0x007841c4>;
		qcom,spss-fuse2-bit = <26>;
		qcom,spss-dev-firmware-name  = "spss1d";  /* 8 chars max */
		qcom,spss-test-firmware-name = "spss1t";  /* 8 chars max */
		qcom,spss-prod-firmware-name = "spss1p";  /* 8 chars max */
		qcom,spss-debug-reg-addr = <0x01886020>;
		qcom,spss-emul-type-reg-addr = <0x01fc8004>;
		pil-mem = <&pil_spss_mem>;
		qcom,pil-size = <0x0F0000>; // padding to 960 KB
		status = "ok";
	};

	qcom,spcom {
		compatible = "qcom,spcom";

		/* predefined channels, remote side is server */
		qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
		status = "ok";
	};

};

&firmware {
	scm {
		compatible = "qcom,scm";
	};
};

#include "sm8150-ion.dtsi"
#include "sm8150-pinctrl.dtsi"
#include "sm8150-regulator.dtsi"
#include "sm8150-pm.dtsi"
#include "sm8150-qupv3.dtsi"
#include "sm8150-slpi-pinctrl.dtsi"
#include "sm8150-ssc-qupv3.dtsi"
#include "sm8150-smp2p.dtsi"
#include "sm8150-gdsc.dtsi"
#include "msm-arm-smmu-sm8150.dtsi"
#include "sm8150-vidc.dtsi"
#include "camera/sm8150-camera.dtsi"

&emac_gdsc {
	status = "ok";
};

&pcie_0_gdsc {
	status = "ok";
};

&pcie_1_gdsc {
	status = "ok";
};

&ufs_phy_gdsc {
	status = "ok";
};

&ufs_card_gdsc {
	status = "ok";
};

&usb30_prim_gdsc {
	status = "ok";
};

&usb30_sec_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu0_gdsc {
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu1_gdsc {
	status = "ok";
};

&bps_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&ipe_0_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&ipe_1_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&ife_0_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	status = "ok";
};

&ife_1_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	status = "ok";
};

&titan_top_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	status = "ok";
};

&mdss_core_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_DISP_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	status = "ok";
};

&gpu_cx_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gpu_gx_gdsc {
	parent-supply = <&VDD_GFX_LEVEL>;
	status = "ok";
};

&mvsc_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	status = "ok";
};

&mvs0_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&mvs1_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	parent-supply = <&VDD_MMCX_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&npu_core_gdsc {
	clock-names = "ahb_clk";
	clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
	status = "ok";
};
#include "sm8150-pcie.dtsi"
#include "sm8150-usb.dtsi"
#include "sm8150-gpu.dtsi"
#include "sm8150-npu.dtsi"
#include "sm8150-thermal.dtsi"