Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
diff --git a/arch/mips/sibyte/cfe/Makefile b/arch/mips/sibyte/cfe/Makefile
new file mode 100644
index 0000000..059d84a
--- /dev/null
+++ b/arch/mips/sibyte/cfe/Makefile
@@ -0,0 +1,3 @@
+lib-y = cfe_api.o setup.o
+lib-$(CONFIG_SMP) += smp.o
+lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o
diff --git a/arch/mips/sibyte/cfe/cfe_api.c b/arch/mips/sibyte/cfe/cfe_api.c
new file mode 100644
index 0000000..c021360
--- /dev/null
+++ b/arch/mips/sibyte/cfe/cfe_api.c
@@ -0,0 +1,502 @@
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* *********************************************************************
+ *
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * Device Function stubs File: cfe_api.c
+ *
+ * This module contains device function stubs (small routines to
+ * call the standard "iocb" interface entry point to CFE).
+ * There should be one routine here per iocb function call.
+ *
+ * Authors: Mitch Lichtenberg, Chris Demetriou
+ *
+ ********************************************************************* */
+
+#include "cfe_api.h"
+#include "cfe_api_int.h"
+
+/* Cast from a native pointer to a cfe_xptr_t and back. */
+#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n))
+#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x))
+
+#ifdef CFE_API_IMPL_NAMESPACE
+#define cfe_iocb_dispatch(a) __cfe_iocb_dispatch(a)
+#endif
+int cfe_iocb_dispatch(cfe_xiocb_t * xiocb);
+
+#if defined(CFE_API_common) || defined(CFE_API_ALL)
+/*
+ * Declare the dispatch function with args of "intptr_t".
+ * This makes sure whatever model we're compiling in
+ * puts the pointers in a single register. For example,
+ * combining -mlong64 and -mips1 or -mips2 would lead to
+ * trouble, since the handle and IOCB pointer will be
+ * passed in two registers each, and CFE expects one.
+ */
+
+static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0;
+static cfe_xuint_t cfe_handle = 0;
+
+int cfe_init(cfe_xuint_t handle, cfe_xuint_t ept)
+{
+ cfe_dispfunc = NATIVE_FROM_XPTR(ept);
+ cfe_handle = handle;
+ return 0;
+}
+
+int cfe_iocb_dispatch(cfe_xiocb_t * xiocb)
+{
+ if (!cfe_dispfunc)
+ return -1;
+ return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb);
+}
+#endif /* CFE_API_common || CFE_API_ALL */
+
+#if defined(CFE_API_close) || defined(CFE_API_ALL)
+int cfe_close(int handle)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+
+}
+#endif /* CFE_API_close || CFE_API_ALL */
+
+#if defined(CFE_API_cpu_start) || defined(CFE_API_ALL)
+int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t);
+ xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
+ xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START;
+ xiocb.plist.xiocb_cpuctl.gp_val = gp;
+ xiocb.plist.xiocb_cpuctl.sp_val = sp;
+ xiocb.plist.xiocb_cpuctl.a1_val = a1;
+ xiocb.plist.xiocb_cpuctl.start_addr = (long) fn;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+#endif /* CFE_API_cpu_start || CFE_API_ALL */
+
+#if defined(CFE_API_cpu_stop) || defined(CFE_API_ALL)
+int cfe_cpu_stop(int cpu)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t);
+ xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
+ xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+#endif /* CFE_API_cpu_stop || CFE_API_ALL */
+
+#if defined(CFE_API_enumenv) || defined(CFE_API_ALL)
+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
+ xiocb.plist.xiocb_envbuf.enum_idx = idx;
+ xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_envbuf.name_length = namelen;
+ xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
+ xiocb.plist.xiocb_envbuf.val_length = vallen;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+#endif /* CFE_API_enumenv || CFE_API_ALL */
+
+#if defined(CFE_API_enummem) || defined(CFE_API_ALL)
+int
+cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length,
+ cfe_xuint_t * type)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = flags;
+ xiocb.xiocb_psize = sizeof(xiocb_meminfo_t);
+ xiocb.plist.xiocb_meminfo.mi_idx = idx;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+
+ *start = xiocb.plist.xiocb_meminfo.mi_addr;
+ *length = xiocb.plist.xiocb_meminfo.mi_size;
+ *type = xiocb.plist.xiocb_meminfo.mi_type;
+
+ return 0;
+}
+#endif /* CFE_API_enummem || CFE_API_ALL */
+
+#if defined(CFE_API_exit) || defined(CFE_API_ALL)
+int cfe_exit(int warm, int status)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_RESTART;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0;
+ xiocb.xiocb_psize = sizeof(xiocb_exitstat_t);
+ xiocb.plist.xiocb_exitstat.status = status;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+#endif /* CFE_API_exit || CFE_API_ALL */
+
+#if defined(CFE_API_flushcache) || defined(CFE_API_ALL)
+int cfe_flushcache(int flg)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = flg;
+ xiocb.xiocb_psize = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+#endif /* CFE_API_flushcache || CFE_API_ALL */
+
+#if defined(CFE_API_getdevinfo) || defined(CFE_API_ALL)
+int cfe_getdevinfo(char *name)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
+ xiocb.plist.xiocb_buffer.buf_offset = 0;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name);
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.plist.xiocb_buffer.buf_devflags;
+}
+#endif /* CFE_API_getdevinfo || CFE_API_ALL */
+
+#if defined(CFE_API_getenv) || defined(CFE_API_ALL)
+int cfe_getenv(char *name, char *dest, int destlen)
+{
+ cfe_xiocb_t xiocb;
+
+ *dest = 0;
+
+ xiocb.xiocb_fcode = CFE_CMD_ENV_GET;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
+ xiocb.plist.xiocb_envbuf.enum_idx = 0;
+ xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
+ xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest);
+ xiocb.plist.xiocb_envbuf.val_length = destlen;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+#endif /* CFE_API_getenv || CFE_API_ALL */
+
+#if defined(CFE_API_getfwinfo) || defined(CFE_API_ALL)
+int cfe_getfwinfo(cfe_fwinfo_t * info)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_fwinfo_t);
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+
+ info->fwi_version = xiocb.plist.xiocb_fwinfo.fwi_version;
+ info->fwi_totalmem = xiocb.plist.xiocb_fwinfo.fwi_totalmem;
+ info->fwi_flags = xiocb.plist.xiocb_fwinfo.fwi_flags;
+ info->fwi_boardid = xiocb.plist.xiocb_fwinfo.fwi_boardid;
+ info->fwi_bootarea_va = xiocb.plist.xiocb_fwinfo.fwi_bootarea_va;
+ info->fwi_bootarea_pa = xiocb.plist.xiocb_fwinfo.fwi_bootarea_pa;
+ info->fwi_bootarea_size =
+ xiocb.plist.xiocb_fwinfo.fwi_bootarea_size;
+#if 0
+ info->fwi_reserved1 = xiocb.plist.xiocb_fwinfo.fwi_reserved1;
+ info->fwi_reserved2 = xiocb.plist.xiocb_fwinfo.fwi_reserved2;
+ info->fwi_reserved3 = xiocb.plist.xiocb_fwinfo.fwi_reserved3;
+#endif
+
+ return 0;
+}
+#endif /* CFE_API_getfwinfo || CFE_API_ALL */
+
+#if defined(CFE_API_getstdhandle) || defined(CFE_API_ALL)
+int cfe_getstdhandle(int flg)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = flg;
+ xiocb.xiocb_psize = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.xiocb_handle;
+}
+#endif /* CFE_API_getstdhandle || CFE_API_ALL */
+
+#if defined(CFE_API_getticks) || defined(CFE_API_ALL)
+int64_t
+#ifdef CFE_API_IMPL_NAMESPACE
+__cfe_getticks(void)
+#else
+cfe_getticks(void)
+#endif
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_time_t);
+ xiocb.plist.xiocb_time.ticks = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.plist.xiocb_time.ticks;
+
+}
+#endif /* CFE_API_getticks || CFE_API_ALL */
+
+#if defined(CFE_API_inpstat) || defined(CFE_API_ALL)
+int cfe_inpstat(int handle)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_inpstat_t);
+ xiocb.plist.xiocb_inpstat.inp_status = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.plist.xiocb_inpstat.inp_status;
+}
+#endif /* CFE_API_inpstat || CFE_API_ALL */
+
+#if defined(CFE_API_ioctl) || defined(CFE_API_ALL)
+int
+cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
+ int length, int *retlen, cfe_xuint_t offset)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
+ xiocb.plist.xiocb_buffer.buf_offset = offset;
+ xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
+ xiocb.plist.xiocb_buffer.buf_length = length;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (retlen)
+ *retlen = xiocb.plist.xiocb_buffer.buf_retlen;
+ return xiocb.xiocb_status;
+}
+#endif /* CFE_API_ioctl || CFE_API_ALL */
+
+#if defined(CFE_API_open) || defined(CFE_API_ALL)
+int cfe_open(char *name)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
+ xiocb.plist.xiocb_buffer.buf_offset = 0;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name);
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.xiocb_handle;
+}
+#endif /* CFE_API_open || CFE_API_ALL */
+
+#if defined(CFE_API_read) || defined(CFE_API_ALL)
+int cfe_read(int handle, unsigned char *buffer, int length)
+{
+ return cfe_readblk(handle, 0, buffer, length);
+}
+#endif /* CFE_API_read || CFE_API_ALL */
+
+#if defined(CFE_API_readblk) || defined(CFE_API_ALL)
+int
+cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer,
+ int length)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_READ;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
+ xiocb.plist.xiocb_buffer.buf_offset = offset;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
+ xiocb.plist.xiocb_buffer.buf_length = length;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.plist.xiocb_buffer.buf_retlen;
+}
+#endif /* CFE_API_readblk || CFE_API_ALL */
+
+#if defined(CFE_API_setenv) || defined(CFE_API_ALL)
+int cfe_setenv(char *name, char *val)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
+ xiocb.plist.xiocb_envbuf.enum_idx = 0;
+ xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
+ xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
+ xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val);
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+#endif /* CFE_API_setenv || CFE_API_ALL */
+
+#if (defined(CFE_API_strlen) || defined(CFE_API_ALL)) \
+ && !defined(CFE_API_STRLEN_CUSTOM)
+int cfe_strlen(char *name)
+{
+ int count = 0;
+
+ while (*name++)
+ count++;
+
+ return count;
+}
+#endif /* CFE_API_strlen || CFE_API_ALL */
+
+#if defined(CFE_API_write) || defined(CFE_API_ALL)
+int cfe_write(int handle, unsigned char *buffer, int length)
+{
+ return cfe_writeblk(handle, 0, buffer, length);
+}
+#endif /* CFE_API_write || CFE_API_ALL */
+
+#if defined(CFE_API_writeblk) || defined(CFE_API_ALL)
+int
+cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer,
+ int length)
+{
+ cfe_xiocb_t xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
+ xiocb.plist.xiocb_buffer.buf_offset = offset;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
+ xiocb.plist.xiocb_buffer.buf_length = length;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.plist.xiocb_buffer.buf_retlen;
+}
+#endif /* CFE_API_writeblk || CFE_API_ALL */
diff --git a/arch/mips/sibyte/cfe/cfe_api.h b/arch/mips/sibyte/cfe/cfe_api.h
new file mode 100644
index 0000000..d8230cc
--- /dev/null
+++ b/arch/mips/sibyte/cfe/cfe_api.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* *********************************************************************
+ *
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * Device function prototypes File: cfe_api.h
+ *
+ * This file contains declarations for doing callbacks to
+ * cfe from an application. It should be the only header
+ * needed by the application to use this library
+ *
+ * Authors: Mitch Lichtenberg, Chris Demetriou
+ *
+ ********************************************************************* */
+
+#ifndef CFE_API_H
+#define CFE_API_H
+
+/*
+ * Apply customizations here for different OSes. These need to:
+ * * typedef uint64_t, int64_t, intptr_t, uintptr_t.
+ * * define cfe_strlen() if use of an existing function is desired.
+ * * define CFE_API_IMPL_NAMESPACE if API functions are to use
+ * names in the implementation namespace.
+ * Also, optionally, if the build environment does not do so automatically,
+ * CFE_API_* can be defined here as desired.
+ */
+/* Begin customization. */
+#include <linux/types.h>
+#include <linux/string.h>
+
+typedef long intptr_t;
+
+#define cfe_strlen strlen
+
+#define CFE_API_ALL
+#define CFE_API_STRLEN_CUSTOM
+/* End customization. */
+
+
+/* *********************************************************************
+ * Constants
+ ********************************************************************* */
+
+/* Seal indicating CFE's presence, passed to user program. */
+#define CFE_EPTSEAL 0x43464531
+
+#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */
+#define CFE_MI_AVAILABLE 1 /* memory is available */
+
+#define CFE_FLG_WARMSTART 0x00000001
+#define CFE_FLG_FULL_ARENA 0x00000001
+#define CFE_FLG_ENV_PERMANENT 0x00000001
+
+#define CFE_CPU_CMD_START 1
+#define CFE_CPU_CMD_STOP 0
+
+#define CFE_STDHANDLE_CONSOLE 0
+
+#define CFE_DEV_NETWORK 1
+#define CFE_DEV_DISK 2
+#define CFE_DEV_FLASH 3
+#define CFE_DEV_SERIAL 4
+#define CFE_DEV_CPU 5
+#define CFE_DEV_NVRAM 6
+#define CFE_DEV_CLOCK 7
+#define CFE_DEV_OTHER 8
+#define CFE_DEV_MASK 0x0F
+
+#define CFE_CACHE_FLUSH_D 1
+#define CFE_CACHE_INVAL_I 2
+#define CFE_CACHE_INVAL_D 4
+#define CFE_CACHE_INVAL_L2 8
+
+#define CFE_FWI_64BIT 0x00000001
+#define CFE_FWI_32BIT 0x00000002
+#define CFE_FWI_RELOC 0x00000004
+#define CFE_FWI_UNCACHED 0x00000008
+#define CFE_FWI_MULTICPU 0x00000010
+#define CFE_FWI_FUNCSIM 0x00000020
+#define CFE_FWI_RTLSIM 0x00000040
+
+typedef struct {
+ int64_t fwi_version; /* major, minor, eco version */
+ int64_t fwi_totalmem; /* total installed mem */
+ int64_t fwi_flags; /* various flags */
+ int64_t fwi_boardid; /* board ID */
+ int64_t fwi_bootarea_va; /* VA of boot area */
+ int64_t fwi_bootarea_pa; /* PA of boot area */
+ int64_t fwi_bootarea_size; /* size of boot area */
+} cfe_fwinfo_t;
+
+
+/*
+ * cfe_strlen is handled specially: If already defined, it has been
+ * overridden in this environment with a standard strlen-like function.
+ */
+#ifdef cfe_strlen
+# define CFE_API_STRLEN_CUSTOM
+#else
+# ifdef CFE_API_IMPL_NAMESPACE
+# define cfe_strlen(a) __cfe_strlen(a)
+# endif
+int cfe_strlen(char *name);
+#endif
+
+/*
+ * Defines and prototypes for functions which take no arguments.
+ */
+#ifdef CFE_API_IMPL_NAMESPACE
+int64_t __cfe_getticks(void);
+#define cfe_getticks() __cfe_getticks()
+#else
+int64_t cfe_getticks(void);
+#endif
+
+/*
+ * Defines and prototypes for the rest of the functions.
+ */
+#ifdef CFE_API_IMPL_NAMESPACE
+#define cfe_close(a) __cfe_close(a)
+#define cfe_cpu_start(a,b,c,d,e) __cfe_cpu_start(a,b,c,d,e)
+#define cfe_cpu_stop(a) __cfe_cpu_stop(a)
+#define cfe_enumenv(a,b,d,e,f) __cfe_enumenv(a,b,d,e,f)
+#define cfe_enummem(a,b,c,d,e) __cfe_enummem(a,b,c,d,e)
+#define cfe_exit(a,b) __cfe_exit(a,b)
+#define cfe_flushcache(a) __cfe_cacheflush(a)
+#define cfe_getdevinfo(a) __cfe_getdevinfo(a)
+#define cfe_getenv(a,b,c) __cfe_getenv(a,b,c)
+#define cfe_getfwinfo(a) __cfe_getfwinfo(a)
+#define cfe_getstdhandle(a) __cfe_getstdhandle(a)
+#define cfe_init(a,b) __cfe_init(a,b)
+#define cfe_inpstat(a) __cfe_inpstat(a)
+#define cfe_ioctl(a,b,c,d,e,f) __cfe_ioctl(a,b,c,d,e,f)
+#define cfe_open(a) __cfe_open(a)
+#define cfe_read(a,b,c) __cfe_read(a,b,c)
+#define cfe_readblk(a,b,c,d) __cfe_readblk(a,b,c,d)
+#define cfe_setenv(a,b) __cfe_setenv(a,b)
+#define cfe_write(a,b,c) __cfe_write(a,b,c)
+#define cfe_writeblk(a,b,c,d) __cfe_writeblk(a,b,c,d)
+#endif /* CFE_API_IMPL_NAMESPACE */
+
+int cfe_close(int handle);
+int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1);
+int cfe_cpu_stop(int cpu);
+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
+int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length,
+ uint64_t * type);
+int cfe_exit(int warm, int status);
+int cfe_flushcache(int flg);
+int cfe_getdevinfo(char *name);
+int cfe_getenv(char *name, char *dest, int destlen);
+int cfe_getfwinfo(cfe_fwinfo_t * info);
+int cfe_getstdhandle(int flg);
+int cfe_init(uint64_t handle, uint64_t ept);
+int cfe_inpstat(int handle);
+int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
+ int length, int *retlen, uint64_t offset);
+int cfe_open(char *name);
+int cfe_read(int handle, unsigned char *buffer, int length);
+int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
+ int length);
+int cfe_setenv(char *name, char *val);
+int cfe_write(int handle, unsigned char *buffer, int length);
+int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer,
+ int length);
+
+#endif /* CFE_API_H */
diff --git a/arch/mips/sibyte/cfe/cfe_api_int.h b/arch/mips/sibyte/cfe/cfe_api_int.h
new file mode 100644
index 0000000..f7e5a64
--- /dev/null
+++ b/arch/mips/sibyte/cfe/cfe_api_int.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* *********************************************************************
+ *
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * Device function prototypes File: cfe_api_int.h
+ *
+ * This header defines all internal types and macros for the
+ * library. This is stuff that's not exported to an app
+ * using the library.
+ *
+ * Authors: Mitch Lichtenberg, Chris Demetriou
+ *
+ ********************************************************************* */
+
+#ifndef CFE_API_INT_H
+#define CFE_API_INT_H
+
+/* *********************************************************************
+ * Constants
+ ********************************************************************* */
+
+#define CFE_CMD_FW_GETINFO 0
+#define CFE_CMD_FW_RESTART 1
+#define CFE_CMD_FW_BOOT 2
+#define CFE_CMD_FW_CPUCTL 3
+#define CFE_CMD_FW_GETTIME 4
+#define CFE_CMD_FW_MEMENUM 5
+#define CFE_CMD_FW_FLUSHCACHE 6
+
+#define CFE_CMD_DEV_GETHANDLE 9
+#define CFE_CMD_DEV_ENUM 10
+#define CFE_CMD_DEV_OPEN 11
+#define CFE_CMD_DEV_INPSTAT 12
+#define CFE_CMD_DEV_READ 13
+#define CFE_CMD_DEV_WRITE 14
+#define CFE_CMD_DEV_IOCTL 15
+#define CFE_CMD_DEV_CLOSE 16
+#define CFE_CMD_DEV_GETINFO 17
+
+#define CFE_CMD_ENV_ENUM 20
+#define CFE_CMD_ENV_GET 22
+#define CFE_CMD_ENV_SET 23
+#define CFE_CMD_ENV_DEL 24
+
+#define CFE_CMD_MAX 32
+
+#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */
+
+/* *********************************************************************
+ * Structures
+ ********************************************************************* */
+
+typedef uint64_t cfe_xuint_t;
+typedef int64_t cfe_xint_t;
+typedef int64_t cfe_xptr_t;
+
+typedef struct xiocb_buffer_s {
+ cfe_xuint_t buf_offset; /* offset on device (bytes) */
+ cfe_xptr_t buf_ptr; /* pointer to a buffer */
+ cfe_xuint_t buf_length; /* length of this buffer */
+ cfe_xuint_t buf_retlen; /* returned length (for read ops) */
+ cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */
+} xiocb_buffer_t;
+
+#define buf_devflags buf_ioctlcmd /* returned device info flags */
+
+typedef struct xiocb_inpstat_s {
+ cfe_xuint_t inp_status; /* 1 means input available */
+} xiocb_inpstat_t;
+
+typedef struct xiocb_envbuf_s {
+ cfe_xint_t enum_idx; /* 0-based enumeration index */
+ cfe_xptr_t name_ptr; /* name string buffer */
+ cfe_xint_t name_length; /* size of name buffer */
+ cfe_xptr_t val_ptr; /* value string buffer */
+ cfe_xint_t val_length; /* size of value string buffer */
+} xiocb_envbuf_t;
+
+typedef struct xiocb_cpuctl_s {
+ cfe_xuint_t cpu_number; /* cpu number to control */
+ cfe_xuint_t cpu_command; /* command to issue to CPU */
+ cfe_xuint_t start_addr; /* CPU start address */
+ cfe_xuint_t gp_val; /* starting GP value */
+ cfe_xuint_t sp_val; /* starting SP value */
+ cfe_xuint_t a1_val; /* starting A1 value */
+} xiocb_cpuctl_t;
+
+typedef struct xiocb_time_s {
+ cfe_xint_t ticks; /* current time in ticks */
+} xiocb_time_t;
+
+typedef struct xiocb_exitstat_s {
+ cfe_xint_t status;
+} xiocb_exitstat_t;
+
+typedef struct xiocb_meminfo_s {
+ cfe_xint_t mi_idx; /* 0-based enumeration index */
+ cfe_xint_t mi_type; /* type of memory block */
+ cfe_xuint_t mi_addr; /* physical start address */
+ cfe_xuint_t mi_size; /* block size */
+} xiocb_meminfo_t;
+
+typedef struct xiocb_fwinfo_s {
+ cfe_xint_t fwi_version; /* major, minor, eco version */
+ cfe_xint_t fwi_totalmem; /* total installed mem */
+ cfe_xint_t fwi_flags; /* various flags */
+ cfe_xint_t fwi_boardid; /* board ID */
+ cfe_xint_t fwi_bootarea_va; /* VA of boot area */
+ cfe_xint_t fwi_bootarea_pa; /* PA of boot area */
+ cfe_xint_t fwi_bootarea_size; /* size of boot area */
+ cfe_xint_t fwi_reserved1;
+ cfe_xint_t fwi_reserved2;
+ cfe_xint_t fwi_reserved3;
+} xiocb_fwinfo_t;
+
+typedef struct cfe_xiocb_s {
+ cfe_xuint_t xiocb_fcode; /* IOCB function code */
+ cfe_xint_t xiocb_status; /* return status */
+ cfe_xint_t xiocb_handle; /* file/device handle */
+ cfe_xuint_t xiocb_flags; /* flags for this IOCB */
+ cfe_xuint_t xiocb_psize; /* size of parameter list */
+ union {
+ xiocb_buffer_t xiocb_buffer; /* buffer parameters */
+ xiocb_inpstat_t xiocb_inpstat; /* input status parameters */
+ xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */
+ xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */
+ xiocb_time_t xiocb_time; /* timer parameters */
+ xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */
+ xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */
+ xiocb_exitstat_t xiocb_exitstat; /* Exit Status */
+ } plist;
+} cfe_xiocb_t;
+
+#endif /* CFE_API_INT_H */
diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/arch/mips/sibyte/cfe/cfe_error.h
new file mode 100644
index 0000000..77eb493
--- /dev/null
+++ b/arch/mips/sibyte/cfe/cfe_error.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* *********************************************************************
+ *
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * Error codes File: cfe_error.h
+ *
+ * CFE's global error code list is here.
+ *
+ * Author: Mitch Lichtenberg
+ *
+ ********************************************************************* */
+
+
+#define CFE_OK 0
+#define CFE_ERR -1 /* generic error */
+#define CFE_ERR_INV_COMMAND -2
+#define CFE_ERR_EOF -3
+#define CFE_ERR_IOERR -4
+#define CFE_ERR_NOMEM -5
+#define CFE_ERR_DEVNOTFOUND -6
+#define CFE_ERR_DEVOPEN -7
+#define CFE_ERR_INV_PARAM -8
+#define CFE_ERR_ENVNOTFOUND -9
+#define CFE_ERR_ENVREADONLY -10
+
+#define CFE_ERR_NOTELF -11
+#define CFE_ERR_NOT32BIT -12
+#define CFE_ERR_WRONGENDIAN -13
+#define CFE_ERR_BADELFVERS -14
+#define CFE_ERR_NOTMIPS -15
+#define CFE_ERR_BADELFFMT -16
+#define CFE_ERR_BADADDR -17
+
+#define CFE_ERR_FILENOTFOUND -18
+#define CFE_ERR_UNSUPPORTED -19
+
+#define CFE_ERR_HOSTUNKNOWN -20
+
+#define CFE_ERR_TIMEOUT -21
+
+#define CFE_ERR_PROTOCOLERR -22
+
+#define CFE_ERR_NETDOWN -23
+#define CFE_ERR_NONAMESERVER -24
+
+#define CFE_ERR_NOHANDLES -25
+#define CFE_ERR_ALREADYBOUND -26
+
+#define CFE_ERR_CANNOTSET -27
+#define CFE_ERR_NOMORE -28
+#define CFE_ERR_BADFILESYS -29
+#define CFE_ERR_FSNOTAVAIL -30
+
+#define CFE_ERR_INVBOOTBLOCK -31
+#define CFE_ERR_WRONGDEVTYPE -32
+#define CFE_ERR_BBCHECKSUM -33
+#define CFE_ERR_BOOTPROGCHKSUM -34
+
+#define CFE_ERR_LDRNOTAVAIL -35
+
+#define CFE_ERR_NOTREADY -36
+
+#define CFE_ERR_GETMEM -37
+#define CFE_ERR_SETMEM -38
+
+#define CFE_ERR_NOTCONN -39
+#define CFE_ERR_ADDRINUSE -40
diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c
new file mode 100644
index 0000000..53a5c1e
--- /dev/null
+++ b/arch/mips/sibyte/cfe/console.c
@@ -0,0 +1,80 @@
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/console.h>
+
+#include <asm/sibyte/board.h>
+
+#include "cfe_api.h"
+#include "cfe_error.h"
+
+extern int cfe_cons_handle;
+
+static void cfe_console_write(struct console *cons, const char *str,
+ unsigned int count)
+{
+ int i, last, written;
+
+ for (i=0,last=0; i<count; i++) {
+ if (!str[i])
+ /* XXXKW can/should this ever happen? */
+ return;
+ if (str[i] == '\n') {
+ do {
+ written = cfe_write(cfe_cons_handle, &str[last], i-last);
+ if (written < 0)
+ ;
+ last += written;
+ } while (last < i);
+ while (cfe_write(cfe_cons_handle, "\r", 1) <= 0)
+ ;
+ }
+ }
+ if (last != count) {
+ do {
+ written = cfe_write(cfe_cons_handle, &str[last], count-last);
+ if (written < 0)
+ ;
+ last += written;
+ } while (last < count);
+ }
+
+}
+
+static int cfe_console_setup(struct console *cons, char *str)
+{
+ char consdev[32];
+ /* XXXKW think about interaction with 'console=' cmdline arg */
+ /* If none of the console options are configured, the build will break. */
+ if (cfe_getenv("BOOT_CONSOLE", consdev, 32) >= 0) {
+#ifdef CONFIG_SIBYTE_SB1250_DUART
+ if (!strcmp(consdev, "uart0")) {
+ setleds("u0cn");
+ } else if (!strcmp(consdev, "uart1")) {
+ setleds("u1cn");
+#endif
+#ifdef CONFIG_VGA_CONSOLE
+ } else if (!strcmp(consdev, "pcconsole0")) {
+ setleds("pccn");
+#endif
+ } else
+ return -ENODEV;
+ }
+ return 0;
+}
+
+static struct console sb1250_cfe_cons = {
+ .name = "cfe",
+ .write = cfe_console_write,
+ .setup = cfe_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+};
+
+static int __init sb1250_cfe_console_init(void)
+{
+ register_console(&sb1250_cfe_cons);
+ return 0;
+}
+
+console_initcall(sb1250_cfe_console_init);
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
new file mode 100644
index 0000000..d6d0364
--- /dev/null
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/linkage.h>
+#include <linux/mm.h>
+#include <linux/blkdev.h>
+#include <linux/bootmem.h>
+#include <linux/smp.h>
+
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
+#include <asm/sibyte/board.h>
+
+#include "cfe_api.h"
+#include "cfe_error.h"
+
+/* Max ram addressable in 32-bit segments */
+#ifdef CONFIG_MIPS64
+#define MAX_RAM_SIZE (~0ULL)
+#else
+#ifdef CONFIG_HIGHMEM
+#ifdef CONFIG_64BIT_PHYS_ADDR
+#define MAX_RAM_SIZE (~0ULL)
+#else
+#define MAX_RAM_SIZE (0xffffffffULL)
+#endif
+#else
+#define MAX_RAM_SIZE (0x1fffffffULL)
+#endif
+#endif
+
+#define SIBYTE_MAX_MEM_REGIONS 8
+phys_t board_mem_region_addrs[SIBYTE_MAX_MEM_REGIONS];
+phys_t board_mem_region_sizes[SIBYTE_MAX_MEM_REGIONS];
+unsigned int board_mem_region_count;
+
+int cfe_cons_handle;
+
+#ifdef CONFIG_BLK_DEV_INITRD
+extern unsigned long initrd_start, initrd_end;
+#endif
+
+#ifdef CONFIG_KGDB
+extern int kgdb_port;
+#endif
+
+static void ATTRIB_NORET cfe_linux_exit(void *arg)
+{
+ int warm = *(int *)arg;
+
+ if (smp_processor_id()) {
+ static int reboot_smp;
+
+ /* Don't repeat the process from another CPU */
+ if (!reboot_smp) {
+ /* Get CPU 0 to do the cfe_exit */
+ reboot_smp = 1;
+ smp_call_function(cfe_linux_exit, arg, 1, 0);
+ }
+ } else {
+ printk("Passing control back to CFE...\n");
+ cfe_exit(warm, 0);
+ printk("cfe_exit returned??\n");
+ }
+ while (1);
+}
+
+static void ATTRIB_NORET cfe_linux_restart(char *command)
+{
+ static const int zero;
+
+ cfe_linux_exit((void *)&zero);
+}
+
+static void ATTRIB_NORET cfe_linux_halt(void)
+{
+ static const int one = 1;
+
+ cfe_linux_exit((void *)&one);
+}
+
+static __init void prom_meminit(void)
+{
+ u64 addr, size, type; /* regardless of 64BIT_PHYS_ADDR */
+ int mem_flags = 0;
+ unsigned int idx;
+ int rd_flag;
+#ifdef CONFIG_BLK_DEV_INITRD
+ unsigned long initrd_pstart;
+ unsigned long initrd_pend;
+
+ initrd_pstart = CPHYSADDR(initrd_start);
+ initrd_pend = CPHYSADDR(initrd_end);
+ if (initrd_start &&
+ ((initrd_pstart > MAX_RAM_SIZE)
+ || (initrd_pend > MAX_RAM_SIZE))) {
+ panic("initrd out of addressable memory");
+ }
+
+#endif /* INITRD */
+
+ for (idx = 0; cfe_enummem(idx, mem_flags, &addr, &size, &type) != CFE_ERR_NOMORE;
+ idx++) {
+ rd_flag = 0;
+ if (type == CFE_MI_AVAILABLE) {
+ /*
+ * See if this block contains (any portion of) the
+ * ramdisk
+ */
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start) {
+ if ((initrd_pstart > addr) &&
+ (initrd_pstart < (addr + size))) {
+ add_memory_region(addr,
+ initrd_pstart - addr,
+ BOOT_MEM_RAM);
+ rd_flag = 1;
+ }
+ if ((initrd_pend > addr) &&
+ (initrd_pend < (addr + size))) {
+ add_memory_region(initrd_pend,
+ (addr + size) - initrd_pend,
+ BOOT_MEM_RAM);
+ rd_flag = 1;
+ }
+ }
+#endif
+ if (!rd_flag) {
+ if (addr > MAX_RAM_SIZE)
+ continue;
+ if (addr+size > MAX_RAM_SIZE)
+ size = MAX_RAM_SIZE - (addr+size) + 1;
+ /*
+ * memcpy/__copy_user prefetch, which
+ * will cause a bus error for
+ * KSEG/KUSEG addrs not backed by RAM.
+ * Hence, reserve some padding for the
+ * prefetch distance.
+ */
+ if (size > 512)
+ size -= 512;
+ add_memory_region(addr, size, BOOT_MEM_RAM);
+ }
+ board_mem_region_addrs[board_mem_region_count] = addr;
+ board_mem_region_sizes[board_mem_region_count] = size;
+ board_mem_region_count++;
+ if (board_mem_region_count ==
+ SIBYTE_MAX_MEM_REGIONS) {
+ /*
+ * Too many regions. Need to configure more
+ */
+ while(1);
+ }
+ }
+ }
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start) {
+ add_memory_region(initrd_pstart, initrd_pend - initrd_pstart,
+ BOOT_MEM_RESERVED);
+ }
+#endif
+}
+
+#ifdef CONFIG_BLK_DEV_INITRD
+static int __init initrd_setup(char *str)
+{
+ char rdarg[64];
+ int idx;
+ char *tmp, *endptr;
+ unsigned long initrd_size;
+
+ /* Make a copy of the initrd argument so we can smash it up here */
+ for (idx = 0; idx < sizeof(rdarg)-1; idx++) {
+ if (!str[idx] || (str[idx] == ' ')) break;
+ rdarg[idx] = str[idx];
+ }
+
+ rdarg[idx] = 0;
+ str = rdarg;
+
+ /*
+ *Initrd location comes in the form "<hex size of ramdisk in bytes>@<location in memory>"
+ * e.g. initrd=3abfd@80010000. This is set up by the loader.
+ */
+ for (tmp = str; *tmp != '@'; tmp++) {
+ if (!*tmp) {
+ goto fail;
+ }
+ }
+ *tmp = 0;
+ tmp++;
+ if (!*tmp) {
+ goto fail;
+ }
+ initrd_size = simple_strtoul(str, &endptr, 16);
+ if (*endptr) {
+ *(tmp-1) = '@';
+ goto fail;
+ }
+ *(tmp-1) = '@';
+ initrd_start = simple_strtoul(tmp, &endptr, 16);
+ if (*endptr) {
+ goto fail;
+ }
+ initrd_end = initrd_start + initrd_size;
+ prom_printf("Found initrd of %lx@%lx\n", initrd_size, initrd_start);
+ return 1;
+ fail:
+ prom_printf("Bad initrd argument. Disabling initrd\n");
+ initrd_start = 0;
+ initrd_end = 0;
+ return 1;
+}
+
+#endif
+
+/*
+ * prom_init is called just after the cpu type is determined, from setup_arch()
+ */
+void __init prom_init(void)
+{
+ uint64_t cfe_ept, cfe_handle;
+ unsigned int cfe_eptseal;
+ int argc = fw_arg0;
+ char **envp = (char **) fw_arg2;
+ int *prom_vec = (int *) fw_arg3;
+#ifdef CONFIG_KGDB
+ char *arg;
+#endif
+
+ _machine_restart = cfe_linux_restart;
+ _machine_halt = cfe_linux_halt;
+ _machine_power_off = cfe_linux_halt;
+
+ /*
+ * Check if a loader was used; if NOT, the 4 arguments are
+ * what CFE gives us (handle, 0, EPT and EPTSEAL)
+ */
+ if (argc < 0) {
+ cfe_handle = (uint64_t)(long)argc;
+ cfe_ept = (long)envp;
+ cfe_eptseal = (uint32_t)(unsigned long)prom_vec;
+ } else {
+ if ((int32_t)(long)prom_vec < 0) {
+ /*
+ * Old loader; all it gives us is the handle,
+ * so use the "known" entrypoint and assume
+ * the seal.
+ */
+ cfe_handle = (uint64_t)(long)prom_vec;
+ cfe_ept = (uint64_t)((int32_t)0x9fc00500);
+ cfe_eptseal = CFE_EPTSEAL;
+ } else {
+ /*
+ * Newer loaders bundle the handle/ept/eptseal
+ * Note: prom_vec is in the loader's useg
+ * which is still alive in the TLB.
+ */
+ cfe_handle = (uint64_t)((int32_t *)prom_vec)[0];
+ cfe_ept = (uint64_t)((int32_t *)prom_vec)[2];
+ cfe_eptseal = (unsigned int)((uint32_t *)prom_vec)[3];
+ }
+ }
+ if (cfe_eptseal != CFE_EPTSEAL) {
+ /* too early for panic to do any good */
+ prom_printf("CFE's entrypoint seal doesn't match. Spinning.");
+ while (1) ;
+ }
+ cfe_init(cfe_handle, cfe_ept);
+ /*
+ * Get the handle for (at least) prom_putchar, possibly for
+ * boot console
+ */
+ cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
+ if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) {
+ if (argc < 0) {
+ /*
+ * It's OK for direct boot to not provide a
+ * command line
+ */
+ strcpy(arcs_cmdline, "root=/dev/ram0 ");
+#ifdef CONFIG_SIBYTE_PTSWARM
+ strcat(arcs_cmdline, "console=ttyS0,115200 ");
+#endif
+ } else {
+ /* The loader should have set the command line */
+ /* too early for panic to do any good */
+ prom_printf("LINUX_CMDLINE not defined in cfe.");
+ while (1) ;
+ }
+ }
+
+#ifdef CONFIG_KGDB
+ if ((arg = strstr(arcs_cmdline,"kgdb=duart")) != NULL)
+ kgdb_port = (arg[10] == '0') ? 0 : 1;
+ else
+ kgdb_port = 1;
+#endif
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ {
+ char *ptr;
+ /* Need to find out early whether we've got an initrd. So scan
+ the list looking now */
+ for (ptr = arcs_cmdline; *ptr; ptr++) {
+ while (*ptr == ' ') {
+ ptr++;
+ }
+ if (!strncmp(ptr, "initrd=", 7)) {
+ initrd_setup(ptr+7);
+ break;
+ } else {
+ while (*ptr && (*ptr != ' ')) {
+ ptr++;
+ }
+ }
+ }
+ }
+#endif /* CONFIG_BLK_DEV_INITRD */
+
+ /* Not sure this is needed, but it's the safe way. */
+ arcs_cmdline[CL_SIZE-1] = 0;
+
+ mips_machgroup = MACH_GROUP_SIBYTE;
+ prom_meminit();
+}
+
+unsigned long __init prom_free_prom_memory(void)
+{
+ /* Not sure what I'm supposed to do here. Nothing, I think */
+ return 0;
+}
+
+void prom_putchar(char c)
+{
+ int ret;
+
+ while ((ret = cfe_write(cfe_cons_handle, &c, 1)) == 0)
+ ;
+}
diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c
new file mode 100644
index 0000000..7339219
--- /dev/null
+++ b/arch/mips/sibyte/cfe/smp.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <asm/processor.h>
+
+#include "cfe_api.h"
+#include "cfe_error.h"
+
+/*
+ * Use CFE to find out how many CPUs are available, setting up
+ * phys_cpu_present_map and the logical/physical mappings.
+ * XXXKW will the boot CPU ever not be physical 0?
+ *
+ * Common setup before any secondaries are started
+ */
+void __init prom_prepare_cpus(unsigned int max_cpus)
+{
+ int i, num;
+
+ cpus_clear(phys_cpu_present_map);
+ cpu_set(0, phys_cpu_present_map);
+ __cpu_number_map[0] = 0;
+ __cpu_logical_map[0] = 0;
+
+ for (i=1, num=0; i<NR_CPUS; i++) {
+ if (cfe_cpu_stop(i) == 0) {
+ cpu_set(i, phys_cpu_present_map);
+ __cpu_number_map[i] = ++num;
+ __cpu_logical_map[num] = i;
+ }
+ }
+ printk("Detected %i available secondary CPU(s)\n", num);
+}
+
+/*
+ * Setup the PC, SP, and GP of a secondary processor and start it
+ * running!
+ */
+void prom_boot_secondary(int cpu, struct task_struct *idle)
+{
+ int retval;
+
+ retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
+ __KSTK_TOS(idle),
+ (unsigned long)idle->thread_info, 0);
+ if (retval != 0)
+ printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
+}
+
+/*
+ * Code to run on secondary just after probing the CPU
+ */
+void prom_init_secondary(void)
+{
+ extern void sb1250_smp_init(void);
+ sb1250_smp_init();
+}
+
+/*
+ * Do any tidying up before marking online and running the idle
+ * loop
+ */
+void prom_smp_finish(void)
+{
+ extern void sb1250_smp_finish(void);
+ sb1250_smp_finish();
+}
+
+/*
+ * Final cleanup after all secondaries booted
+ */
+void prom_cpus_done(void)
+{
+}
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
new file mode 100644
index 0000000..a8af846
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -0,0 +1,8 @@
+obj-y := setup.o irq.o irq_handler.o time.o
+
+obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_SIBYTE_TBPROF) += bcm1250_tbprof.o
+obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o
+obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
+
+EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
new file mode 100644
index 0000000..7f813ae
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#define SBPROF_TB_DEBUG 0
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_scd.h>
+#include <asm/sibyte/sb1250_int.h>
+#include <asm/sibyte/trace_prof.h>
+
+#define DEVNAME "bcm1250_tbprof"
+
+static struct sbprof_tb sbp;
+
+#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
+
+/************************************************************************
+ * Support for ZBbus sampling using the trace buffer
+ *
+ * We use the SCD performance counter interrupt, caused by a Zclk counter
+ * overflow, to trigger the start of tracing.
+ *
+ * We set the trace buffer to sample everything and freeze on
+ * overflow.
+ *
+ * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
+ *
+ ************************************************************************/
+
+static u_int64_t tb_period;
+
+static void arm_tb(void)
+{
+ u_int64_t scdperfcnt;
+ u_int64_t next = (1ULL << 40) - tb_period;
+ u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
+ /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
+ trigger start of trace. XXX vary sampling period */
+ bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
+ scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
+ /* Unfortunately, in Pass 2 we must clear all counters to knock down
+ a previous interrupt request. This means that bus profiling
+ requires ALL of the SCD perf counters. */
+ bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is
+ M_SPC_CFG_ENABLE | // enable counting
+ M_SPC_CFG_CLEAR | // clear all counters
+ V_SPC_CFG_SRC1(1), // counter 1 counts cycles
+ IOADDR(A_SCD_PERF_CNT_CFG));
+ bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
+ /* Reset the trace buffer */
+ bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
+#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
+ /* XXXKW may want to expose control to the data-collector */
+ tb_options |= M_SCD_TRACE_CFG_FORCECNT;
+#endif
+ bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
+ sbp.tb_armed = 1;
+}
+
+static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ int i;
+ DBG(printk(DEVNAME ": tb_intr\n"));
+ if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
+ /* XXX should use XKPHYS to make writes bypass L2 */
+ u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
+ /* Read out trace */
+ bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));
+ __asm__ __volatile__ ("sync" : : : "memory");
+ /* Loop runs backwards because bundles are read out in reverse order */
+ for (i = 256 * 6; i > 0; i -= 6) {
+ // Subscripts decrease to put bundle in the order
+ // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
+ p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi
+ p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo
+ p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi
+ p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo
+ p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi
+ p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo
+ }
+ if (!sbp.tb_enable) {
+ DBG(printk(DEVNAME ": tb_intr shutdown\n"));
+ bus_writeq(M_SCD_TRACE_CFG_RESET,
+ IOADDR(A_SCD_TRACE_CFG));
+ sbp.tb_armed = 0;
+ wake_up(&sbp.tb_sync);
+ } else {
+ arm_tb(); // knock down current interrupt and get another one later
+ }
+ } else {
+ /* No more trace buffer samples */
+ DBG(printk(DEVNAME ": tb_intr full\n"));
+ bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
+ sbp.tb_armed = 0;
+ if (!sbp.tb_enable) {
+ wake_up(&sbp.tb_sync);
+ }
+ wake_up(&sbp.tb_read);
+ }
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t sbprof_pc_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ printk(DEVNAME ": unexpected pc_intr");
+ return IRQ_NONE;
+}
+
+int sbprof_zbprof_start(struct file *filp)
+{
+ u_int64_t scdperfcnt;
+
+ if (sbp.tb_enable)
+ return -EBUSY;
+
+ DBG(printk(DEVNAME ": starting\n"));
+
+ sbp.tb_enable = 1;
+ sbp.next_tb_sample = 0;
+ filp->f_pos = 0;
+
+ if (request_irq
+ (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) {
+ return -EBUSY;
+ }
+ /* Make sure there isn't a perf-cnt interrupt waiting */
+ scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
+ /* Disable and clear counters, override SRC_1 */
+ bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
+ M_SPC_CFG_ENABLE |
+ M_SPC_CFG_CLEAR |
+ V_SPC_CFG_SRC1(1),
+ IOADDR(A_SCD_PERF_CNT_CFG));
+
+ /* We grab this interrupt to prevent others from trying to use
+ it, even though we don't want to service the interrupts
+ (they only feed into the trace-on-interrupt mechanism) */
+ if (request_irq
+ (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
+ free_irq(K_INT_TRACE_FREEZE, &sbp);
+ return -EBUSY;
+ }
+
+ /* I need the core to mask these, but the interrupt mapper to
+ pass them through. I am exploiting my knowledge that
+ cp0_status masks out IP[5]. krw */
+ bus_writeq(K_INT_MAP_I3,
+ IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
+ (K_INT_PERF_CNT << 3)));
+
+ /* Initialize address traps */
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
+
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
+
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
+ bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
+
+ /* Initialize Trace Event 0-7 */
+ // when interrupt
+ bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
+
+ /* Initialize Trace Sequence 0-7 */
+ // Start on event 0 (interrupt)
+ bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
+ IOADDR(A_SCD_TRACE_SEQUENCE_0));
+ // dsamp when d used | asamp when a used
+ bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
+ K_SCD_TRSEQ_TRIGGER_ALL,
+ IOADDR(A_SCD_TRACE_SEQUENCE_1));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
+ bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
+
+ /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
+ bus_writeq((1ULL << K_INT_PERF_CNT),
+ IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
+
+ arm_tb();
+
+ DBG(printk(DEVNAME ": done starting\n"));
+
+ return 0;
+}
+
+int sbprof_zbprof_stop(void)
+{
+ DBG(printk(DEVNAME ": stopping\n"));
+
+ if (sbp.tb_enable) {
+ sbp.tb_enable = 0;
+ /* XXXKW there is a window here where the intr handler
+ may run, see the disable, and do the wake_up before
+ this sleep happens. */
+ if (sbp.tb_armed) {
+ DBG(printk(DEVNAME ": wait for disarm\n"));
+ interruptible_sleep_on(&sbp.tb_sync);
+ DBG(printk(DEVNAME ": disarm complete\n"));
+ }
+ free_irq(K_INT_TRACE_FREEZE, &sbp);
+ free_irq(K_INT_PERF_CNT, &sbp);
+ }
+
+ DBG(printk(DEVNAME ": done stopping\n"));
+
+ return 0;
+}
+
+static int sbprof_tb_open(struct inode *inode, struct file *filp)
+{
+ int minor;
+
+ minor = iminor(inode);
+ if (minor != 0) {
+ return -ENODEV;
+ }
+ if (sbp.open) {
+ return -EBUSY;
+ }
+
+ memset(&sbp, 0, sizeof(struct sbprof_tb));
+ sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
+ if (!sbp.sbprof_tbbuf) {
+ return -ENOMEM;
+ }
+ memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
+ init_waitqueue_head(&sbp.tb_sync);
+ init_waitqueue_head(&sbp.tb_read);
+ sbp.open = 1;
+
+ return 0;
+}
+
+static int sbprof_tb_release(struct inode *inode, struct file *filp)
+{
+ int minor;
+
+ minor = iminor(inode);
+ if (minor != 0 || !sbp.open) {
+ return -ENODEV;
+ }
+
+ if (sbp.tb_armed || sbp.tb_enable) {
+ sbprof_zbprof_stop();
+ }
+
+ vfree(sbp.sbprof_tbbuf);
+ sbp.open = 0;
+
+ return 0;
+}
+
+static ssize_t sbprof_tb_read(struct file *filp, char *buf,
+ size_t size, loff_t *offp)
+{
+ int cur_sample, sample_off, cur_count, sample_left;
+ char *src;
+ int count = 0;
+ char *dest = buf;
+ long cur_off = *offp;
+
+ count = 0;
+ cur_sample = cur_off / TB_SAMPLE_SIZE;
+ sample_off = cur_off % TB_SAMPLE_SIZE;
+ sample_left = TB_SAMPLE_SIZE - sample_off;
+ while (size && (cur_sample < sbp.next_tb_sample)) {
+ cur_count = size < sample_left ? size : sample_left;
+ src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
+ copy_to_user(dest, src, cur_count);
+ DBG(printk(DEVNAME ": read from sample %d, %d bytes\n",
+ cur_sample, cur_count));
+ size -= cur_count;
+ sample_left -= cur_count;
+ if (!sample_left) {
+ cur_sample++;
+ sample_off = 0;
+ sample_left = TB_SAMPLE_SIZE;
+ } else {
+ sample_off += cur_count;
+ }
+ cur_off += cur_count;
+ dest += cur_count;
+ count += cur_count;
+ }
+ *offp = cur_off;
+
+ return count;
+}
+
+static int sbprof_tb_ioctl(struct inode *inode,
+ struct file *filp,
+ unsigned int command,
+ unsigned long arg)
+{
+ int error = 0;
+
+ switch (command) {
+ case SBPROF_ZBSTART:
+ error = sbprof_zbprof_start(filp);
+ break;
+ case SBPROF_ZBSTOP:
+ error = sbprof_zbprof_stop();
+ break;
+ case SBPROF_ZBWAITFULL:
+ interruptible_sleep_on(&sbp.tb_read);
+ /* XXXKW check if interrupted? */
+ return put_user(TB_FULL, (int *) arg);
+ default:
+ error = -EINVAL;
+ break;
+ }
+
+ return error;
+}
+
+static struct file_operations sbprof_tb_fops = {
+ .owner = THIS_MODULE,
+ .open = sbprof_tb_open,
+ .release = sbprof_tb_release,
+ .read = sbprof_tb_read,
+ .ioctl = sbprof_tb_ioctl,
+ .mmap = NULL,
+};
+
+static int __init sbprof_tb_init(void)
+{
+ if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
+ printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
+ SBPROF_TB_MAJOR);
+ return -EIO;
+ }
+ sbp.open = 0;
+ tb_period = zbbus_mhz * 10000LL;
+ printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period);
+ return 0;
+}
+
+static void __exit sbprof_tb_cleanup(void)
+{
+ unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
+}
+
+module_init(sbprof_tb_init);
+module_exit(sbprof_tb_cleanup);
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
new file mode 100644
index 0000000..182a16f
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2002,2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/*
+ * The Bus Watcher monitors internal bus transactions and maintains
+ * counts of transactions with error status, logging details and
+ * causing one of several interrupts. This driver provides a handler
+ * for those interrupts which aggregates the counts (to avoid
+ * saturating the 8-bit counters) and provides a presence in
+ * /proc/bus_watcher if PROC_FS is on.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/proc_fs.h>
+#include <asm/system.h>
+#include <asm/io.h>
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_int.h>
+#include <asm/sibyte/sb1250_scd.h>
+
+
+struct bw_stats_struct {
+ uint64_t status;
+ uint32_t l2_err;
+ uint32_t memio_err;
+ int status_printed;
+ unsigned long l2_cor_d;
+ unsigned long l2_bad_d;
+ unsigned long l2_cor_t;
+ unsigned long l2_bad_t;
+ unsigned long mem_cor_d;
+ unsigned long mem_bad_d;
+ unsigned long bus_error;
+} bw_stats;
+
+
+static void print_summary(uint32_t status, uint32_t l2_err,
+ uint32_t memio_err)
+{
+ printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
+ printk("\nLast recorded signature:\n");
+ printk("Request %02x from %d, answered by %d with Dcode %d\n",
+ (unsigned int)(G_SCD_BERR_TID(status) & 0x3f),
+ (int)(G_SCD_BERR_TID(status) >> 6),
+ (int)G_SCD_BERR_RID(status),
+ (int)G_SCD_BERR_DCODE(status));
+}
+
+/*
+ * check_bus_watcher is exported for use in situations where we want
+ * to see the most recent status of the bus watcher, which might have
+ * already been destructively read out of the registers.
+ *
+ * notes: this is currently used by the cache error handler
+ * should provide locking against the interrupt handler
+ */
+void check_bus_watcher(void)
+{
+ u32 status, l2_err, memio_err;
+
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+ /* Destructive read, clears register and interrupt */
+ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
+#else
+ /* Use non-destructive register */
+ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));
+#endif
+ if (!(status & 0x7fffffff)) {
+ printk("Using last values reaped by bus watcher driver\n");
+ status = bw_stats.status;
+ l2_err = bw_stats.l2_err;
+ memio_err = bw_stats.memio_err;
+ } else {
+ l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
+ memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
+ }
+ if (status & ~(1UL << 31))
+ print_summary(status, l2_err, memio_err);
+ else
+ printk("Bus watcher indicates no error\n");
+}
+
+static int bw_print_buffer(char *page, struct bw_stats_struct *stats)
+{
+ int len;
+
+ len = sprintf(page, "SiByte Bus Watcher statistics\n");
+ len += sprintf(page+len, "-----------------------------\n");
+ len += sprintf(page+len, "L2-d-cor %8ld\nL2-d-bad %8ld\n",
+ stats->l2_cor_d, stats->l2_bad_d);
+ len += sprintf(page+len, "L2-t-cor %8ld\nL2-t-bad %8ld\n",
+ stats->l2_cor_t, stats->l2_bad_t);
+ len += sprintf(page+len, "MC-d-cor %8ld\nMC-d-bad %8ld\n",
+ stats->mem_cor_d, stats->mem_bad_d);
+ len += sprintf(page+len, "IO-err %8ld\n", stats->bus_error);
+ len += sprintf(page+len, "\nLast recorded signature:\n");
+ len += sprintf(page+len, "Request %02x from %d, answered by %d with Dcode %d\n",
+ (unsigned int)(G_SCD_BERR_TID(stats->status) & 0x3f),
+ (int)(G_SCD_BERR_TID(stats->status) >> 6),
+ (int)G_SCD_BERR_RID(stats->status),
+ (int)G_SCD_BERR_DCODE(stats->status));
+ /* XXXKW indicate multiple errors between printings, or stats
+ collection (or both)? */
+ if (stats->status & M_SCD_BERR_MULTERRS)
+ len += sprintf(page+len, "Multiple errors observed since last check.\n");
+ if (stats->status_printed) {
+ len += sprintf(page+len, "(no change since last printing)\n");
+ } else {
+ stats->status_printed = 1;
+ }
+
+ return len;
+}
+
+#ifdef CONFIG_PROC_FS
+
+/* For simplicity, I want to assume a single read is required each
+ time */
+static int bw_read_proc(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ int len;
+
+ if (off == 0) {
+ len = bw_print_buffer(page, data);
+ *start = page;
+ } else {
+ len = 0;
+ *eof = 1;
+ }
+ return len;
+}
+
+static void create_proc_decoder(struct bw_stats_struct *stats)
+{
+ struct proc_dir_entry *ent;
+
+ ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL,
+ bw_read_proc, stats);
+ if (!ent) {
+ printk(KERN_INFO "Unable to initialize bus_watcher /proc entry\n");
+ return;
+ }
+}
+
+#endif /* CONFIG_PROC_FS */
+
+/*
+ * sibyte_bw_int - handle bus watcher interrupts and accumulate counts
+ *
+ * notes: possible re-entry due to multiple sources
+ * should check/indicate saturation
+ */
+static irqreturn_t sibyte_bw_int(int irq, void *data, struct pt_regs *regs)
+{
+ struct bw_stats_struct *stats = data;
+ unsigned long cntr;
+#ifdef CONFIG_SIBYTE_BW_TRACE
+ int i;
+#endif
+#ifndef CONFIG_PROC_FS
+ char bw_buf[1024];
+#endif
+
+#ifdef CONFIG_SIBYTE_BW_TRACE
+ csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
+ csr_out32(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));
+
+ for (i=0; i<256*6; i++)
+ printk("%016llx\n",
+ (unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ)));
+
+ csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
+ csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));
+#endif
+
+ /* Destructive read, clears register and interrupt */
+ stats->status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
+ stats->status_printed = 0;
+
+ stats->l2_err = cntr = csr_in32(IOADDR(A_BUS_L2_ERRORS));
+ stats->l2_cor_d += G_SCD_L2ECC_CORR_D(cntr);
+ stats->l2_bad_d += G_SCD_L2ECC_BAD_D(cntr);
+ stats->l2_cor_t += G_SCD_L2ECC_CORR_T(cntr);
+ stats->l2_bad_t += G_SCD_L2ECC_BAD_T(cntr);
+ csr_out32(0, IOADDR(A_BUS_L2_ERRORS));
+
+ stats->memio_err = cntr = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
+ stats->mem_cor_d += G_SCD_MEM_ECC_CORR(cntr);
+ stats->mem_bad_d += G_SCD_MEM_ECC_BAD(cntr);
+ stats->bus_error += G_SCD_MEM_BUSERR(cntr);
+ csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS));
+
+#ifndef CONFIG_PROC_FS
+ bw_print_buffer(bw_buf, stats);
+ printk(bw_buf);
+#endif
+
+ return IRQ_HANDLED;
+}
+
+int __init sibyte_bus_watcher(void)
+{
+ memset(&bw_stats, 0, sizeof(struct bw_stats_struct));
+ bw_stats.status_printed = 1;
+
+ if (request_irq(K_INT_BAD_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) {
+ printk("Failed to register bus watcher BAD_ECC irq\n");
+ return -1;
+ }
+ if (request_irq(K_INT_COR_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) {
+ free_irq(K_INT_BAD_ECC, &bw_stats);
+ printk("Failed to register bus watcher COR_ECC irq\n");
+ return -1;
+ }
+ if (request_irq(K_INT_IO_BUS, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) {
+ free_irq(K_INT_BAD_ECC, &bw_stats);
+ free_irq(K_INT_COR_ECC, &bw_stats);
+ printk("Failed to register bus watcher IO_BUS irq\n");
+ return -1;
+ }
+
+#ifdef CONFIG_PROC_FS
+ create_proc_decoder(&bw_stats);
+#endif
+
+#ifdef CONFIG_SIBYTE_BW_TRACE
+ csr_out32((M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
+ K_SCD_TRSEQ_TRIGGER_ALL),
+ IOADDR(A_SCD_TRACE_SEQUENCE_0));
+ csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
+ csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));
+#endif
+
+ return 0;
+}
+
+__initcall(sibyte_bus_watcher);
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
new file mode 100644
index 0000000..2728abb
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -0,0 +1,431 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/smp.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/kernel_stat.h>
+
+#include <asm/errno.h>
+#include <asm/signal.h>
+#include <asm/system.h>
+#include <asm/ptrace.h>
+#include <asm/io.h>
+
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_int.h>
+#include <asm/sibyte/sb1250_uart.h>
+#include <asm/sibyte/sb1250_scd.h>
+#include <asm/sibyte/sb1250.h>
+
+/*
+ * These are the routines that handle all the low level interrupt stuff.
+ * Actions handled here are: initialization of the interrupt map, requesting of
+ * interrupt lines by handlers, dispatching if interrupts to handlers, probing
+ * for interrupt lines
+ */
+
+
+#define shutdown_sb1250_irq disable_sb1250_irq
+static void end_sb1250_irq(unsigned int irq);
+static void enable_sb1250_irq(unsigned int irq);
+static void disable_sb1250_irq(unsigned int irq);
+static unsigned int startup_sb1250_irq(unsigned int irq);
+static void ack_sb1250_irq(unsigned int irq);
+#ifdef CONFIG_SMP
+static void sb1250_set_affinity(unsigned int irq, unsigned long mask);
+#endif
+
+#ifdef CONFIG_SIBYTE_HAS_LDT
+extern unsigned long ldt_eoi_space;
+#endif
+
+#ifdef CONFIG_KGDB
+static int kgdb_irq;
+
+/* Default to UART1 */
+int kgdb_port = 1;
+#ifdef CONFIG_SIBYTE_SB1250_DUART
+extern char sb1250_duart_present[];
+#endif
+#endif
+
+static struct hw_interrupt_type sb1250_irq_type = {
+ "SB1250-IMR",
+ startup_sb1250_irq,
+ shutdown_sb1250_irq,
+ enable_sb1250_irq,
+ disable_sb1250_irq,
+ ack_sb1250_irq,
+ end_sb1250_irq,
+#ifdef CONFIG_SMP
+ sb1250_set_affinity
+#else
+ NULL
+#endif
+};
+
+/* Store the CPU id (not the logical number) */
+int sb1250_irq_owner[SB1250_NR_IRQS];
+
+DEFINE_SPINLOCK(sb1250_imr_lock);
+
+void sb1250_mask_irq(int cpu, int irq)
+{
+ unsigned long flags;
+ u64 cur_ints;
+
+ spin_lock_irqsave(&sb1250_imr_lock, flags);
+ cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
+ R_IMR_INTERRUPT_MASK));
+ cur_ints |= (((u64) 1) << irq);
+ __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
+ R_IMR_INTERRUPT_MASK));
+ spin_unlock_irqrestore(&sb1250_imr_lock, flags);
+}
+
+void sb1250_unmask_irq(int cpu, int irq)
+{
+ unsigned long flags;
+ u64 cur_ints;
+
+ spin_lock_irqsave(&sb1250_imr_lock, flags);
+ cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
+ R_IMR_INTERRUPT_MASK));
+ cur_ints &= ~(((u64) 1) << irq);
+ __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
+ R_IMR_INTERRUPT_MASK));
+ spin_unlock_irqrestore(&sb1250_imr_lock, flags);
+}
+
+#ifdef CONFIG_SMP
+static void sb1250_set_affinity(unsigned int irq, unsigned long mask)
+{
+ int i = 0, old_cpu, cpu, int_on;
+ u64 cur_ints;
+ irq_desc_t *desc = irq_desc + irq;
+ unsigned long flags;
+
+ while (mask) {
+ if (mask & 1) {
+ mask >>= 1;
+ break;
+ }
+ mask >>= 1;
+ i++;
+ }
+
+ if (mask) {
+ printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
+ return;
+ }
+
+ /* Convert logical CPU to physical CPU */
+ cpu = cpu_logical_map(i);
+
+ /* Protect against other affinity changers and IMR manipulation */
+ spin_lock_irqsave(&desc->lock, flags);
+ spin_lock(&sb1250_imr_lock);
+
+ /* Swizzle each CPU's IMR (but leave the IP selection alone) */
+ old_cpu = sb1250_irq_owner[irq];
+ cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
+ R_IMR_INTERRUPT_MASK));
+ int_on = !(cur_ints & (((u64) 1) << irq));
+ if (int_on) {
+ /* If it was on, mask it */
+ cur_ints |= (((u64) 1) << irq);
+ __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
+ R_IMR_INTERRUPT_MASK));
+ }
+ sb1250_irq_owner[irq] = cpu;
+ if (int_on) {
+ /* unmask for the new CPU */
+ cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
+ R_IMR_INTERRUPT_MASK));
+ cur_ints &= ~(((u64) 1) << irq);
+ __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
+ R_IMR_INTERRUPT_MASK));
+ }
+ spin_unlock(&sb1250_imr_lock);
+ spin_unlock_irqrestore(&desc->lock, flags);
+}
+#endif
+
+
+/* Defined in arch/mips/sibyte/sb1250/irq_handler.S */
+extern void sb1250_irq_handler(void);
+
+/*****************************************************************************/
+
+static unsigned int startup_sb1250_irq(unsigned int irq)
+{
+ sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
+
+ return 0; /* never anything pending */
+}
+
+
+static void disable_sb1250_irq(unsigned int irq)
+{
+ sb1250_mask_irq(sb1250_irq_owner[irq], irq);
+}
+
+static void enable_sb1250_irq(unsigned int irq)
+{
+ sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
+}
+
+
+static void ack_sb1250_irq(unsigned int irq)
+{
+#ifdef CONFIG_SIBYTE_HAS_LDT
+ u64 pending;
+
+ /*
+ * If the interrupt was an HT interrupt, now is the time to
+ * clear it. NOTE: we assume the HT bridge was set up to
+ * deliver the interrupts to all CPUs (which makes affinity
+ * changing easier for us)
+ */
+ pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
+ R_IMR_LDT_INTERRUPT)));
+ pending &= ((u64)1 << (irq));
+ if (pending) {
+ int i;
+ for (i=0; i<NR_CPUS; i++) {
+ int cpu;
+#ifdef CONFIG_SMP
+ cpu = cpu_logical_map(i);
+#else
+ cpu = i;
+#endif
+ /*
+ * Clear for all CPUs so an affinity switch
+ * doesn't find an old status
+ */
+ bus_writeq(pending,
+ IOADDR(A_IMR_REGISTER(cpu,
+ R_IMR_LDT_INTERRUPT_CLR)));
+ }
+
+ /*
+ * Generate EOI. For Pass 1 parts, EOI is a nop. For
+ * Pass 2, the LDT world may be edge-triggered, but
+ * this EOI shouldn't hurt. If they are
+ * level-sensitive, the EOI is required.
+ */
+ *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
+ }
+#endif
+ sb1250_mask_irq(sb1250_irq_owner[irq], irq);
+}
+
+
+static void end_sb1250_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
+ sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
+ }
+}
+
+
+void __init init_sb1250_irqs(void)
+{
+ int i;
+
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = 0;
+ irq_desc[i].depth = 1;
+ if (i < SB1250_NR_IRQS) {
+ irq_desc[i].handler = &sb1250_irq_type;
+ sb1250_irq_owner[i] = 0;
+ } else {
+ irq_desc[i].handler = &no_irq_type;
+ }
+ }
+}
+
+
+static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ return IRQ_NONE;
+}
+
+static struct irqaction sb1250_dummy_action = {
+ .handler = sb1250_dummy_handler,
+ .flags = 0,
+ .mask = CPU_MASK_NONE,
+ .name = "sb1250-private",
+ .next = NULL,
+ .dev_id = 0
+};
+
+int sb1250_steal_irq(int irq)
+{
+ irq_desc_t *desc = irq_desc + irq;
+ unsigned long flags;
+ int retval = 0;
+
+ if (irq >= SB1250_NR_IRQS)
+ return -EINVAL;
+
+ spin_lock_irqsave(&desc->lock,flags);
+ /* Don't allow sharing at all for these */
+ if (desc->action != NULL)
+ retval = -EBUSY;
+ else {
+ desc->action = &sb1250_dummy_action;
+ desc->depth = 0;
+ }
+ spin_unlock_irqrestore(&desc->lock,flags);
+ return 0;
+}
+
+/*
+ * arch_init_irq is called early in the boot sequence from init/main.c via
+ * init_IRQ. It is responsible for setting up the interrupt mapper and
+ * installing the handler that will be responsible for dispatching interrupts
+ * to the "right" place.
+ */
+/*
+ * For now, map all interrupts to IP[2]. We could save
+ * some cycles by parceling out system interrupts to different
+ * IP lines, but keep it simple for bringup. We'll also direct
+ * all interrupts to a single CPU; we should probably route
+ * PCI and LDT to one cpu and everything else to the other
+ * to balance the load a bit.
+ *
+ * On the second cpu, everything is set to IP5, which is
+ * ignored, EXCEPT the mailbox interrupt. That one is
+ * set to IP[2] so it is handled. This is needed so we
+ * can do cross-cpu function calls, as requred by SMP
+ */
+
+#define IMR_IP2_VAL K_INT_MAP_I0
+#define IMR_IP3_VAL K_INT_MAP_I1
+#define IMR_IP4_VAL K_INT_MAP_I2
+#define IMR_IP5_VAL K_INT_MAP_I3
+#define IMR_IP6_VAL K_INT_MAP_I4
+
+void __init arch_init_irq(void)
+{
+
+ unsigned int i;
+ u64 tmp;
+ unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
+ STATUSF_IP1 | STATUSF_IP0;
+
+ /* Default everything to IP2 */
+ for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
+ bus_writeq(IMR_IP2_VAL,
+ IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
+ (i << 3)));
+ bus_writeq(IMR_IP2_VAL,
+ IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
+ (i << 3)));
+ }
+
+ init_sb1250_irqs();
+
+ /*
+ * Map the high 16 bits of the mailbox registers to IP[3], for
+ * inter-cpu messages
+ */
+ /* Was I1 */
+ bus_writeq(IMR_IP3_VAL,
+ IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
+ (K_INT_MBOX_0 << 3)));
+ bus_writeq(IMR_IP3_VAL,
+ IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
+ (K_INT_MBOX_0 << 3)));
+
+ /* Clear the mailboxes. The firmware may leave them dirty */
+ bus_writeq(0xffffffffffffffffULL,
+ IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
+ bus_writeq(0xffffffffffffffffULL,
+ IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
+
+ /* Mask everything except the mailbox registers for both cpus */
+ tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
+ bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
+ bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
+
+ sb1250_steal_irq(K_INT_MBOX_0);
+
+ /*
+ * Note that the timer interrupts are also mapped, but this is
+ * done in sb1250_time_init(). Also, the profiling driver
+ * does its own management of IP7.
+ */
+
+#ifdef CONFIG_KGDB
+ imask |= STATUSF_IP6;
+#endif
+ /* Enable necessary IPs, disable the rest */
+ change_c0_status(ST0_IM, imask);
+ set_except_vector(0, sb1250_irq_handler);
+
+#ifdef CONFIG_KGDB
+ if (kgdb_flag) {
+ kgdb_irq = K_INT_UART_0 + kgdb_port;
+
+#ifdef CONFIG_SIBYTE_SB1250_DUART
+ sb1250_duart_present[kgdb_port] = 0;
+#endif
+ /* Setup uart 1 settings, mapper */
+ bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
+
+ sb1250_steal_irq(kgdb_irq);
+ bus_writeq(IMR_IP6_VAL,
+ IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
+ (kgdb_irq<<3)));
+ sb1250_unmask_irq(0, kgdb_irq);
+ }
+#endif
+}
+
+#ifdef CONFIG_KGDB
+
+#include <linux/delay.h>
+
+#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
+#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
+
+void sb1250_kgdb_interrupt(struct pt_regs *regs)
+{
+ /*
+ * Clear break-change status (allow some time for the remote
+ * host to stop the break, since we would see another
+ * interrupt on the end-of-break too)
+ */
+ kstat_this_cpu.irqs[kgdb_irq]++;
+ mdelay(500);
+ duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
+ M_DUART_RX_EN | M_DUART_TX_EN);
+ set_async_breakpoint(®s->cp0_epc);
+}
+
+#endif /* CONFIG_KGDB */
diff --git a/arch/mips/sibyte/sb1250/irq_handler.S b/arch/mips/sibyte/sb1250/irq_handler.S
new file mode 100644
index 0000000..60edc8f
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/irq_handler.S
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/*
+ * sb1250_handle_int() is the routine that is actually called when an interrupt
+ * occurs. It is installed as the exception vector handler in arch_init_irq()
+ * in arch/mips/sibyte/sb1250/irq.c
+ *
+ * In the handle we figure out which interrupts need handling, and use that to
+ * call the dispatcher, which will take care of actually calling registered
+ * handlers
+ *
+ * Note that we take care of all raised interrupts in one go at the handler.
+ * This is more BSDish than the Indy code, and also, IMHO, more sane.
+ */
+#include <linux/config.h>
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+#include <asm/sibyte/sb1250_defs.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_int.h>
+
+/*
+ * What a pain. We have to be really careful saving the upper 32 bits of any
+ * register across function calls if we don't want them trashed--since were
+ * running in -o32, the calling routing never saves the full 64 bits of a
+ * register across a function call. Being the interrupt handler, we're
+ * guaranteed that interrupts are disabled during this code so we don't have
+ * to worry about random interrupts blasting the high 32 bits.
+ */
+
+ .text
+ .set push
+ .set noreorder
+ .set noat
+ .set mips64
+ .align 5
+ NESTED(sb1250_irq_handler, PT_SIZE, sp)
+ SAVE_ALL
+ CLI
+
+#ifdef CONFIG_SIBYTE_SB1250_PROF
+ /* Set compare to count to silence count/compare timer interrupts */
+ mfc0 t1, CP0_COUNT
+ mtc0 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
+#endif
+ /* Read cause */
+ mfc0 s0, CP0_CAUSE
+
+#ifdef CONFIG_SIBYTE_SB1250_PROF
+ /* Cpu performance counter interrupt is routed to IP[7] */
+ andi t1, s0, CAUSEF_IP7
+ beqz t1, 0f
+ srl t1, s0, (CAUSEB_BD-2) /* Shift BD bit to bit 2 */
+ and t1, t1, 0x4 /* mask to get just BD bit */
+ mfc0 a0, CP0_EPC
+ jal sbprof_cpu_intr
+ addu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
+ j ret_from_irq
+ nop
+0:
+#endif
+
+ /* Timer interrupt is routed to IP[4] */
+ andi t1, s0, CAUSEF_IP4
+ beqz t1, 1f
+ nop
+ jal sb1250_timer_interrupt
+ move a0, sp /* Pass the registers along */
+ j ret_from_irq
+ nop # delay slot
+1:
+
+#ifdef CONFIG_SMP
+ /* Mailbox interrupt is routed to IP[3] */
+ andi t1, s0, CAUSEF_IP3
+ beqz t1, 2f
+ nop
+ jal sb1250_mailbox_interrupt
+ move a0, sp
+ j ret_from_irq
+ nop # delay slot
+2:
+#endif
+
+#ifdef CONFIG_KGDB
+ /* KGDB (uart 1) interrupt is routed to IP[6] */
+ andi t1, s0, CAUSEF_IP6
+ beqz t1, 1f
+ nop # delay slot
+ jal sb1250_kgdb_interrupt
+ move a0, sp
+ j ret_from_irq
+ nop # delay slot
+1:
+#endif
+
+ and t1, s0, CAUSEF_IP2
+ beqz t1, 4f
+ nop
+
+ /*
+ * Default...we've hit an IP[2] interrupt, which means we've got to
+ * check the 1250 interrupt registers to figure out what to do
+ * Need to detect which CPU we're on, now that smp_affinity is supported.
+ */
+ PTR_LA v0, CKSEG1 + A_IMR_CPU0_BASE
+#ifdef CONFIG_SMP
+ lw t1, TI_CPU($28)
+ sll t1, IMR_REGISTER_SPACING_SHIFT
+ addu v0, t1
+#endif
+ ld s0, R_IMR_INTERRUPT_STATUS_BASE(v0) /* read IP[2] status */
+
+ beqz s0, 4f /* No interrupts. Return */
+ move a1, sp
+
+3: dclz s1, s0 /* Find the next interrupt */
+ dsubu a0, zero, s1
+ daddiu a0, a0, 63
+ jal do_IRQ
+ nop
+
+4: j ret_from_irq
+ nop
+
+ .set pop
+ END(sb1250_irq_handler)
diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c
new file mode 100644
index 0000000..de62ab0
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/prom.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/blkdev.h>
+#include <linux/bootmem.h>
+#include <linux/smp.h>
+#include <linux/initrd.h>
+
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
+
+#define MAX_RAM_SIZE ((CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - 1)
+
+static __init void prom_meminit(void)
+{
+#ifdef CONFIG_BLK_DEV_INITRD
+ unsigned long initrd_pstart;
+ unsigned long initrd_pend;
+
+ initrd_pstart = __pa(initrd_start);
+ initrd_pend = __pa(initrd_end);
+ if (initrd_start &&
+ ((initrd_pstart > MAX_RAM_SIZE)
+ || (initrd_pend > MAX_RAM_SIZE))) {
+ panic("initrd out of addressable memory");
+ }
+
+ add_memory_region(0, initrd_pstart,
+ BOOT_MEM_RAM);
+ add_memory_region(initrd_pstart, initrd_pend - initrd_pstart,
+ BOOT_MEM_RESERVED);
+ add_memory_region(initrd_pend,
+ (CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - initrd_pend,
+ BOOT_MEM_RAM);
+#else
+ add_memory_region(0, CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024,
+ BOOT_MEM_RAM);
+#endif
+}
+
+void prom_cpu0_exit(void *unused)
+{
+ while (1) ;
+}
+
+static void prom_linux_exit(void)
+{
+#ifdef CONFIG_SMP
+ if (smp_processor_id()) {
+ smp_call_function(prom_cpu0_exit,NULL,1,1);
+ }
+#endif
+ while(1);
+}
+
+/*
+ * prom_init is called just after the cpu type is determined, from setup_arch()
+ */
+void __init prom_init(void)
+{
+ _machine_restart = (void (*)(char *))prom_linux_exit;
+ _machine_halt = prom_linux_exit;
+ _machine_power_off = prom_linux_exit;
+
+ strcpy(arcs_cmdline, "root=/dev/ram0 ");
+
+ mips_machgroup = MACH_GROUP_SIBYTE;
+ prom_meminit();
+}
+
+unsigned long __init prom_free_prom_memory(void)
+{
+ /* Not sure what I'm supposed to do here. Nothing, I think */
+ return 0;
+}
+
+void prom_putchar(char c)
+{
+}
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
new file mode 100644
index 0000000..f8c605b
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_scd.h>
+
+unsigned int sb1_pass;
+unsigned int soc_pass;
+unsigned int soc_type;
+unsigned int periph_rev;
+unsigned int zbbus_mhz;
+
+static char *soc_str;
+static char *pass_str;
+static unsigned int war_pass; /* XXXKW don't overload PASS defines? */
+
+static inline int setup_bcm1250(void);
+static inline int setup_bcm112x(void);
+
+/* Setup code likely to be common to all SiByte platforms */
+
+static inline int sys_rev_decode(void)
+{
+ int ret = 0;
+
+ war_pass = soc_pass;
+ switch (soc_type) {
+ case K_SYS_SOC_TYPE_BCM1250:
+ case K_SYS_SOC_TYPE_BCM1250_ALT:
+ case K_SYS_SOC_TYPE_BCM1250_ALT2:
+ soc_str = "BCM1250";
+ ret = setup_bcm1250();
+ break;
+ case K_SYS_SOC_TYPE_BCM1120:
+ soc_str = "BCM1120";
+ ret = setup_bcm112x();
+ break;
+ case K_SYS_SOC_TYPE_BCM1125:
+ soc_str = "BCM1125";
+ ret = setup_bcm112x();
+ break;
+ case K_SYS_SOC_TYPE_BCM1125H:
+ soc_str = "BCM1125H";
+ ret = setup_bcm112x();
+ break;
+ default:
+ prom_printf("Unknown SOC type %x\n", soc_type);
+ ret = 1;
+ break;
+ }
+ return ret;
+}
+
+static inline int setup_bcm1250(void)
+{
+ int ret = 0;
+
+ switch (soc_pass) {
+ case K_SYS_REVISION_BCM1250_PASS1:
+ periph_rev = 1;
+ pass_str = "Pass 1";
+ break;
+ case K_SYS_REVISION_BCM1250_A10:
+ periph_rev = 2;
+ pass_str = "A8/A10";
+ /* XXXKW different war_pass? */
+ war_pass = K_SYS_REVISION_BCM1250_PASS2;
+ break;
+ case K_SYS_REVISION_BCM1250_PASS2_2:
+ periph_rev = 2;
+ pass_str = "B1";
+ break;
+ case K_SYS_REVISION_BCM1250_B2:
+ periph_rev = 2;
+ pass_str = "B2";
+ war_pass = K_SYS_REVISION_BCM1250_PASS2_2;
+ break;
+ case K_SYS_REVISION_BCM1250_PASS3:
+ periph_rev = 3;
+ pass_str = "C0";
+ break;
+ case K_SYS_REVISION_BCM1250_C1:
+ periph_rev = 3;
+ pass_str = "C1";
+ break;
+ default:
+ if (soc_pass < K_SYS_REVISION_BCM1250_PASS2_2) {
+ periph_rev = 2;
+ pass_str = "A0-A6";
+ war_pass = K_SYS_REVISION_BCM1250_PASS2;
+ } else {
+ prom_printf("Unknown BCM1250 rev %x\n", soc_pass);
+ ret = 1;
+ }
+ break;
+ }
+ return ret;
+}
+
+static inline int setup_bcm112x(void)
+{
+ int ret = 0;
+
+ switch (soc_pass) {
+ case 0:
+ /* Early build didn't have revid set */
+ periph_rev = 3;
+ pass_str = "A1";
+ war_pass = K_SYS_REVISION_BCM112x_A1;
+ break;
+ case K_SYS_REVISION_BCM112x_A1:
+ periph_rev = 3;
+ pass_str = "A1";
+ break;
+ case K_SYS_REVISION_BCM112x_A2:
+ periph_rev = 3;
+ pass_str = "A2";
+ break;
+ default:
+ prom_printf("Unknown %s rev %x\n", soc_str, soc_pass);
+ ret = 1;
+ }
+ return ret;
+}
+
+void sb1250_setup(void)
+{
+ uint64_t sys_rev;
+ int plldiv;
+ int bad_config = 0;
+
+ sb1_pass = read_c0_prid() & 0xff;
+ sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION));
+ soc_type = SYS_SOC_TYPE(sys_rev);
+ soc_pass = G_SYS_REVISION(sys_rev);
+
+ if (sys_rev_decode()) {
+ prom_printf("Restart after failure to identify SiByte chip\n");
+ machine_restart(NULL);
+ }
+
+ plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG)));
+ zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
+
+ prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n",
+ soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
+ prom_printf("Board type: %s\n", get_system_type());
+
+ switch(war_pass) {
+ case K_SYS_REVISION_BCM1250_PASS1:
+#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
+ prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
+ bad_config = 1;
+#endif
+ break;
+ case K_SYS_REVISION_BCM1250_PASS2:
+ /* Pass 2 - easiest as default for now - so many numbers */
+#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
+ prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
+ bad_config = 1;
+#endif
+#ifdef CONFIG_CPU_HAS_PREFETCH
+ prom_printf("@@@@ Prefetches may be enabled in this kernel, but are buggy on this board. @@@@\n");
+ bad_config = 1;
+#endif
+ break;
+ case K_SYS_REVISION_BCM1250_PASS2_2:
+#ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
+ prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
+ bad_config = 1;
+#endif
+#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || !defined(CONFIG_CPU_HAS_PREFETCH)
+ prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is conservatively configured for an 'A' stepping. @@@@\n");
+#endif
+ break;
+ default:
+ break;
+ }
+ if (bad_config) {
+ prom_printf("Invalid configuration for this chip.\n");
+ machine_restart(NULL);
+ }
+}
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
new file mode 100644
index 0000000..be91b39
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/kernel_stat.h>
+
+#include <asm/mmu_context.h>
+#include <asm/io.h>
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_int.h>
+
+static void *mailbox_set_regs[] = {
+ (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
+ (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
+};
+
+static void *mailbox_clear_regs[] = {
+ (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
+ (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
+};
+
+static void *mailbox_regs[] = {
+ (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
+ (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
+};
+
+/*
+ * SMP init and finish on secondary CPUs
+ */
+void sb1250_smp_init(void)
+{
+ unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
+ STATUSF_IP1 | STATUSF_IP0;
+
+ /* Set interrupt mask, but don't enable */
+ change_c0_status(ST0_IM, imask);
+}
+
+void sb1250_smp_finish(void)
+{
+ extern void sb1250_time_init(void);
+ sb1250_time_init();
+ local_irq_enable();
+}
+
+/*
+ * These are routines for dealing with the sb1250 smp capabilities
+ * independent of board/firmware
+ */
+
+/*
+ * Simple enough; everything is set up, so just poke the appropriate mailbox
+ * register, and we should be set
+ */
+void core_send_ipi(int cpu, unsigned int action)
+{
+ bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
+}
+
+void sb1250_mailbox_interrupt(struct pt_regs *regs)
+{
+ int cpu = smp_processor_id();
+ unsigned int action;
+
+ kstat_this_cpu.irqs[K_INT_MBOX_0]++;
+ /* Load the mailbox register to figure out what we're supposed to do */
+ action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
+
+ /* Clear the mailbox to clear the interrupt */
+ __bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
+
+ /*
+ * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the
+ * interrupt will do the reschedule for us
+ */
+
+ if (action & SMP_CALL_FUNCTION)
+ smp_call_function_interrupt();
+}
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
new file mode 100644
index 0000000..8b4c848
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/*
+ * These are routines to set up and handle interrupts from the
+ * sb1250 general purpose timer 0. We're using the timer as a
+ * system clock, so we set it up to run at 100 Hz. On every
+ * interrupt, we update our idea of what the time of day is,
+ * then call do_timer() in the architecture-independent kernel
+ * code to do general bookkeeping (e.g. update jiffies, run
+ * bottom halves, etc.)
+ */
+#include <linux/config.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/kernel_stat.h>
+
+#include <asm/irq.h>
+#include <asm/ptrace.h>
+#include <asm/addrspace.h>
+#include <asm/time.h>
+#include <asm/io.h>
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_int.h>
+#include <asm/sibyte/sb1250_scd.h>
+
+
+#define IMR_IP2_VAL K_INT_MAP_I0
+#define IMR_IP3_VAL K_INT_MAP_I1
+#define IMR_IP4_VAL K_INT_MAP_I2
+
+extern int sb1250_steal_irq(int irq);
+
+void sb1250_time_init(void)
+{
+ int cpu = smp_processor_id();
+ int irq = K_INT_TIMER_0+cpu;
+
+ /* Only have 4 general purpose timers */
+ if (cpu > 3) {
+ BUG();
+ }
+
+ if (!cpu) {
+ /* Use our own gettimeoffset() routine */
+ do_gettimeoffset = sb1250_gettimeoffset;
+ }
+
+ sb1250_mask_irq(cpu, irq);
+
+ /* Map the timer interrupt to ip[4] of this cpu */
+ bus_writeq(IMR_IP4_VAL,
+ IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
+ (irq << 3)));
+
+ /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
+ /* Disable the timer and set up the count */
+ bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+#ifdef CONFIG_SIMULATION
+ bus_writeq(50000 / HZ,
+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
+#else
+ bus_writeq(1000000/HZ,
+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
+#endif
+
+ /* Set the timer running */
+ bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+
+ sb1250_unmask_irq(cpu, irq);
+ sb1250_steal_irq(irq);
+ /*
+ * This interrupt is "special" in that it doesn't use the request_irq
+ * way to hook the irq line. The timer interrupt is initialized early
+ * enough to make this a major pain, and it's also firing enough to
+ * warrant a bit of special case code. sb1250_timer_interrupt is
+ * called directly from irq_handler.S when IP[4] is set during an
+ * interrupt
+ */
+}
+
+void sb1250_timer_interrupt(struct pt_regs *regs)
+{
+ extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
+ int cpu = smp_processor_id();
+ int irq = K_INT_TIMER_0 + cpu;
+
+ /* Reset the timer */
+ __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
+ IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
+
+ /*
+ * CPU 0 handles the global timer interrupt job
+ */
+ if (cpu == 0) {
+ ll_timer_interrupt(irq, regs);
+ }
+
+ /*
+ * every CPU should do profiling and process accouting
+ */
+ ll_local_timer_interrupt(irq, regs);
+}
+
+/*
+ * We use our own do_gettimeoffset() instead of the generic one,
+ * because the generic one does not work for SMP case.
+ * In addition, since we use general timer 0 for system time,
+ * we can get accurate intra-jiffy offset without calibration.
+ */
+unsigned long sb1250_gettimeoffset(void)
+{
+ unsigned long count =
+ bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
+
+ return 1000000/HZ - count;
+ }
diff --git a/arch/mips/sibyte/swarm/Makefile b/arch/mips/sibyte/swarm/Makefile
new file mode 100644
index 0000000..2d62603
--- /dev/null
+++ b/arch/mips/sibyte/swarm/Makefile
@@ -0,0 +1,3 @@
+lib-y = setup.o rtc_xicor1241.o rtc_m41t81.o
+
+lib-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c
new file mode 100644
index 0000000..75ce14c
--- /dev/null
+++ b/arch/mips/sibyte/swarm/dbg_io.c
@@ -0,0 +1,76 @@
+/*
+ * kgdb debug routines for SiByte boards.
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+/* -------------------- BEGINNING OF CONFIG --------------------- */
+
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_uart.h>
+#include <asm/sibyte/sb1250_int.h>
+#include <asm/addrspace.h>
+
+/*
+ * We use the second serial port for kgdb traffic.
+ * 115200, 8, N, 1.
+ */
+
+#define BAUD_RATE 115200
+#define CLK_DIVISOR V_DUART_BAUD_RATE(BAUD_RATE)
+#define DATA_BITS V_DUART_BITS_PER_CHAR_8 /* or 7 */
+#define PARITY V_DUART_PARITY_MODE_NONE /* or even */
+#define STOP_BITS M_DUART_STOP_BIT_LEN_1 /* or 2 */
+
+static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */
+
+/* -------------------- END OF CONFIG --------------------- */
+extern int kgdb_port;
+
+#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
+#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
+
+void putDebugChar(unsigned char c);
+unsigned char getDebugChar(void);
+static void
+duart_init(int clk_divisor, int data, int parity, int stop)
+{
+ duart_out(R_DUART_MODE_REG_1, data | parity);
+ duart_out(R_DUART_MODE_REG_2, stop);
+ duart_out(R_DUART_CLK_SEL, clk_divisor);
+
+ duart_out(R_DUART_CMD, M_DUART_RX_EN | M_DUART_TX_EN); /* enable rx and tx */
+}
+
+void
+putDebugChar(unsigned char c)
+{
+ if (!duart_initialized) {
+ duart_initialized = 1;
+ duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
+ }
+ while ((duart_in(R_DUART_STATUS) & M_DUART_TX_RDY) == 0);
+ duart_out(R_DUART_TX_HOLD, c);
+}
+
+unsigned char
+getDebugChar(void)
+{
+ if (!duart_initialized) {
+ duart_initialized = 1;
+ duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
+ }
+ while ((duart_in(R_DUART_STATUS) & M_DUART_RX_RDY) == 0) ;
+ return duart_in(R_DUART_RX_HOLD);
+}
+
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c
new file mode 100644
index 0000000..0e633ee
--- /dev/null
+++ b/arch/mips/sibyte/swarm/rtc_m41t81.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ *
+ * Copyright (C) 2002 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/bcd.h>
+#include <linux/types.h>
+#include <linux/time.h>
+
+#include <asm/time.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_smbus.h>
+
+
+/* M41T81 definitions */
+
+/*
+ * Register bits
+ */
+
+#define M41T81REG_SC_ST 0x80 /* stop bit */
+#define M41T81REG_HR_CB 0x40 /* century bit */
+#define M41T81REG_HR_CEB 0x80 /* century enable bit */
+#define M41T81REG_CTL_S 0x20 /* sign bit */
+#define M41T81REG_CTL_FT 0x40 /* frequency test bit */
+#define M41T81REG_CTL_OUT 0x80 /* output level */
+#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */
+#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */
+#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */
+#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */
+#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */
+#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */
+#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */
+#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */
+#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */
+#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */
+#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */
+#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */
+#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */
+#define M41T81REG_AHR_HT 0x40 /* halt update bit */
+#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */
+#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */
+#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */
+#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */
+#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */
+#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */
+#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */
+#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */
+
+
+/*
+ * Register numbers
+ */
+
+#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */
+#define M41T81REG_SC 0x01 /* seconds */
+#define M41T81REG_MN 0x02 /* minute */
+#define M41T81REG_HR 0x03 /* hour/century */
+#define M41T81REG_DY 0x04 /* day of week */
+#define M41T81REG_DT 0x05 /* date of month */
+#define M41T81REG_MO 0x06 /* month */
+#define M41T81REG_YR 0x07 /* year */
+#define M41T81REG_CTL 0x08 /* control */
+#define M41T81REG_WD 0x09 /* watchdog */
+#define M41T81REG_AMO 0x0A /* alarm: month */
+#define M41T81REG_ADT 0x0B /* alarm: date */
+#define M41T81REG_AHR 0x0C /* alarm: hour */
+#define M41T81REG_AMN 0x0D /* alarm: minute */
+#define M41T81REG_ASC 0x0E /* alarm: second */
+#define M41T81REG_FLG 0x0F /* flags */
+#define M41T81REG_SQW 0x13 /* square wave register */
+
+#define M41T81_CCR_ADDRESS 0x68
+#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg))))
+
+static int m41t81_read(uint8_t addr)
+{
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
+ bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE),
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+ /* Clear error bit by writing a 1 */
+ bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+ return -1;
+ }
+
+ return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
+}
+
+static int m41t81_write(uint8_t addr, int b)
+{
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD));
+ bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA));
+ bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+ /* Clear error bit by writing a 1 */
+ bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+ return -1;
+ }
+
+ /* read the same byte again to make sure it is written */
+ bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ return 0;
+}
+
+int m41t81_set_time(unsigned long t)
+{
+ struct rtc_time tm;
+
+ to_tm(t, &tm);
+
+ /*
+ * Note the write order matters as it ensures the correctness.
+ * When we write sec, 10th sec is clear. It is reasonable to
+ * believe we should finish writing min within a second.
+ */
+
+ tm.tm_sec = BIN2BCD(tm.tm_sec);
+ m41t81_write(M41T81REG_SC, tm.tm_sec);
+
+ tm.tm_min = BIN2BCD(tm.tm_min);
+ m41t81_write(M41T81REG_MN, tm.tm_min);
+
+ tm.tm_hour = BIN2BCD(tm.tm_hour);
+ tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0);
+ m41t81_write(M41T81REG_HR, tm.tm_hour);
+
+ /* tm_wday starts from 0 to 6 */
+ if (tm.tm_wday == 0) tm.tm_wday = 7;
+ tm.tm_wday = BIN2BCD(tm.tm_wday);
+ m41t81_write(M41T81REG_DY, tm.tm_wday);
+
+ tm.tm_mday = BIN2BCD(tm.tm_mday);
+ m41t81_write(M41T81REG_DT, tm.tm_mday);
+
+ /* tm_mon starts from 0, *ick* */
+ tm.tm_mon ++;
+ tm.tm_mon = BIN2BCD(tm.tm_mon);
+ m41t81_write(M41T81REG_MO, tm.tm_mon);
+
+ /* we don't do century, everything is beyond 2000 */
+ tm.tm_year %= 100;
+ tm.tm_year = BIN2BCD(tm.tm_year);
+ m41t81_write(M41T81REG_YR, tm.tm_year);
+
+ return 0;
+}
+
+unsigned long m41t81_get_time(void)
+{
+ unsigned int year, mon, day, hour, min, sec;
+
+ /*
+ * min is valid if two reads of sec are the same.
+ */
+ for (;;) {
+ sec = m41t81_read(M41T81REG_SC);
+ min = m41t81_read(M41T81REG_MN);
+ if (sec == m41t81_read(M41T81REG_SC)) break;
+ }
+ hour = m41t81_read(M41T81REG_HR) & 0x3f;
+ day = m41t81_read(M41T81REG_DT);
+ mon = m41t81_read(M41T81REG_MO);
+ year = m41t81_read(M41T81REG_YR);
+
+ sec = BCD2BIN(sec);
+ min = BCD2BIN(min);
+ hour = BCD2BIN(hour);
+ day = BCD2BIN(day);
+ mon = BCD2BIN(mon);
+ year = BCD2BIN(year);
+
+ year += 2000;
+
+ return mktime(year, mon, day, hour, min, sec);
+}
+
+int m41t81_probe(void)
+{
+ unsigned int tmp;
+
+ /* enable chip if it is not enabled yet */
+ tmp = m41t81_read(M41T81REG_SC);
+ m41t81_write(M41T81REG_SC, tmp & 0x7f);
+
+ return (m41t81_read(M41T81REG_SC) != -1);
+}
diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c
new file mode 100644
index 0000000..981d21f
--- /dev/null
+++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ *
+ * Copyright (C) 2002 MontaVista Software Inc.
+ * Author: jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/bcd.h>
+#include <linux/types.h>
+#include <linux/time.h>
+
+#include <asm/time.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_smbus.h>
+
+
+/* Xicor 1241 definitions */
+
+/*
+ * Register bits
+ */
+
+#define X1241REG_SR_BAT 0x80 /* currently on battery power */
+#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
+#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */
+#define X1241REG_SR_RTCF 0x01 /* clock failed */
+#define X1241REG_BL_BP2 0x80 /* block protect 2 */
+#define X1241REG_BL_BP1 0x40 /* block protect 1 */
+#define X1241REG_BL_BP0 0x20 /* block protect 0 */
+#define X1241REG_BL_WD1 0x10
+#define X1241REG_BL_WD0 0x08
+#define X1241REG_HR_MIL 0x80 /* military time format */
+
+/*
+ * Register numbers
+ */
+
+#define X1241REG_BL 0x10 /* block protect bits */
+#define X1241REG_INT 0x11 /* */
+#define X1241REG_SC 0x30 /* Seconds */
+#define X1241REG_MN 0x31 /* Minutes */
+#define X1241REG_HR 0x32 /* Hours */
+#define X1241REG_DT 0x33 /* Day of month */
+#define X1241REG_MO 0x34 /* Month */
+#define X1241REG_YR 0x35 /* Year */
+#define X1241REG_DW 0x36 /* Day of Week */
+#define X1241REG_Y2K 0x37 /* Year 2K */
+#define X1241REG_SR 0x3F /* Status register */
+
+#define X1241_CCR_ADDRESS 0x6F
+
+#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg))))
+
+static int xicor_read(uint8_t addr)
+{
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
+ bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA));
+ bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE),
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+ /* Clear error bit by writing a 1 */
+ bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+ return -1;
+ }
+
+ return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
+}
+
+static int xicor_write(uint8_t addr, int b)
+{
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ bus_writeq(addr, SMB_CSR(R_SMB_CMD));
+ bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
+ bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+ /* Clear error bit by writing a 1 */
+ bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+int xicor_set_time(unsigned long t)
+{
+ struct rtc_time tm;
+ int tmp;
+
+ to_tm(t, &tm);
+
+ /* unlock writes to the CCR */
+ xicor_write(X1241REG_SR, X1241REG_SR_WEL);
+ xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
+
+ /* trivial ones */
+ tm.tm_sec = BIN2BCD(tm.tm_sec);
+ xicor_write(X1241REG_SC, tm.tm_sec);
+
+ tm.tm_min = BIN2BCD(tm.tm_min);
+ xicor_write(X1241REG_MN, tm.tm_min);
+
+ tm.tm_mday = BIN2BCD(tm.tm_mday);
+ xicor_write(X1241REG_DT, tm.tm_mday);
+
+ /* tm_mon starts from 0, *ick* */
+ tm.tm_mon ++;
+ tm.tm_mon = BIN2BCD(tm.tm_mon);
+ xicor_write(X1241REG_MO, tm.tm_mon);
+
+ /* year is split */
+ tmp = tm.tm_year / 100;
+ tm.tm_year %= 100;
+ xicor_write(X1241REG_YR, tm.tm_year);
+ xicor_write(X1241REG_Y2K, tmp);
+
+ /* hour is the most tricky one */
+ tmp = xicor_read(X1241REG_HR);
+ if (tmp & X1241REG_HR_MIL) {
+ /* 24 hour format */
+ tm.tm_hour = BIN2BCD(tm.tm_hour);
+ tmp = (tmp & ~0x3f) | (tm.tm_hour & 0x3f);
+ } else {
+ /* 12 hour format, with 0x2 for pm */
+ tmp = tmp & ~0x3f;
+ if (tm.tm_hour >= 12) {
+ tmp |= 0x20;
+ tm.tm_hour -= 12;
+ }
+ tm.tm_hour = BIN2BCD(tm.tm_hour);
+ tmp |= tm.tm_hour;
+ }
+ xicor_write(X1241REG_HR, tmp);
+
+ xicor_write(X1241REG_SR, 0);
+
+ return 0;
+}
+
+unsigned long xicor_get_time(void)
+{
+ unsigned int year, mon, day, hour, min, sec, y2k;
+
+ sec = xicor_read(X1241REG_SC);
+ min = xicor_read(X1241REG_MN);
+ hour = xicor_read(X1241REG_HR);
+
+ if (hour & X1241REG_HR_MIL) {
+ hour &= 0x3f;
+ } else {
+ if (hour & 0x20)
+ hour = (hour & 0xf) + 0x12;
+ }
+
+ day = xicor_read(X1241REG_DT);
+ mon = xicor_read(X1241REG_MO);
+ year = xicor_read(X1241REG_YR);
+ y2k = xicor_read(X1241REG_Y2K);
+
+ sec = BCD2BIN(sec);
+ min = BCD2BIN(min);
+ hour = BCD2BIN(hour);
+ day = BCD2BIN(day);
+ mon = BCD2BIN(mon);
+ year = BCD2BIN(year);
+ y2k = BCD2BIN(y2k);
+
+ year += (y2k * 100);
+
+ return mktime(year, mon, day, hour, min, sec);
+}
+
+int xicor_probe(void)
+{
+ return (xicor_read(X1241REG_SC) != -1);
+}
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
new file mode 100644
index 0000000..457aeb7
--- /dev/null
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/*
+ * Setup code for the SWARM board
+ */
+
+#include <linux/config.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/blkdev.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/tty.h>
+#include <linux/initrd.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/bootinfo.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/time.h>
+#include <asm/traps.h>
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_genbus.h>
+#include <asm/sibyte/board.h>
+
+extern void sb1250_setup(void);
+
+extern int xicor_probe(void);
+extern int xicor_set_time(unsigned long);
+extern unsigned long xicor_get_time(void);
+
+extern int m41t81_probe(void);
+extern int m41t81_set_time(unsigned long);
+extern unsigned long m41t81_get_time(void);
+
+const char *get_system_type(void)
+{
+ return "SiByte " SIBYTE_BOARD_NAME;
+}
+
+void __init swarm_timer_setup(struct irqaction *irq)
+{
+ /*
+ * we don't set up irqaction, because we will deliver timer
+ * interrupts through low-level (direct) meachanism.
+ */
+
+ /* We only need to setup the generic timer */
+ sb1250_time_init();
+}
+
+int swarm_be_handler(struct pt_regs *regs, int is_fixup)
+{
+ if (!is_fixup && (regs->cp0_cause & 4)) {
+ /* Data bus error - print PA */
+#ifdef CONFIG_MIPS64
+ printk("DBE physical address: %010lx\n",
+ __read_64bit_c0_register($26, 1));
+#else
+ printk("DBE physical address: %010llx\n",
+ __read_64bit_c0_split($26, 1));
+#endif
+ }
+ return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
+}
+
+static int __init swarm_setup(void)
+{
+ sb1250_setup();
+
+ panic_timeout = 5; /* For debug. */
+
+ board_timer_setup = swarm_timer_setup;
+ board_be_handler = swarm_be_handler;
+
+ if (xicor_probe()) {
+ printk("swarm setup: Xicor 1241 RTC detected.\n");
+ rtc_get_time = xicor_get_time;
+ rtc_set_time = xicor_set_time;
+ }
+
+ if (m41t81_probe()) {
+ printk("swarm setup: M41T81 RTC detected.\n");
+ rtc_get_time = m41t81_get_time;
+ rtc_set_time = m41t81_set_time;
+ }
+
+ printk("This kernel optimized for "
+#ifdef CONFIG_SIMULATION
+ "simulation"
+#else
+ "board"
+#endif
+ " runs "
+#ifdef CONFIG_SIBYTE_CFE
+ "with"
+#else
+ "without"
+#endif
+ " CFE\n");
+
+#ifdef CONFIG_VT
+ screen_info = (struct screen_info) {
+ 0, 0, /* orig-x, orig-y */
+ 0, /* unused */
+ 52, /* orig_video_page */
+ 3, /* orig_video_mode */
+ 80, /* orig_video_cols */
+ 4626, 3, 9, /* unused, ega_bx, unused */
+ 25, /* orig_video_lines */
+ 0x22, /* orig_video_isVGA */
+ 16 /* orig_video_points */
+ };
+ /* XXXKW for CFE, get lines/cols from environment */
+#endif
+
+ return 0;
+}
+
+early_initcall(swarm_setup);
+
+#ifdef LEDS_PHYS
+
+#ifdef CONFIG_SIBYTE_CARMEL
+/* XXXKW need to detect Monterey/LittleSur/etc */
+#undef LEDS_PHYS
+#define LEDS_PHYS MLEDS_PHYS
+#endif
+
+#define setled(index, c) \
+ ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c)
+void setleds(char *str)
+{
+ int i;
+ for (i = 0; i < 4; i++) {
+ if (!str[i]) {
+ setled(i, ' ');
+ } else {
+ setled(i, str[i]);
+ }
+ }
+}
+#endif
diff --git a/arch/mips/sibyte/swarm/time.c b/arch/mips/sibyte/swarm/time.c
new file mode 100644
index 0000000..c1f1a9d
--- /dev/null
+++ b/arch/mips/sibyte/swarm/time.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2000, 2001 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/*
+ * Time routines for the swarm board. We pass all the hard stuff
+ * through to the sb1250 handling code. Only thing we really keep
+ * track of here is what time of day we think it is. And we don't
+ * really even do a good job of that...
+ */
+
+
+#include <linux/bcd.h>
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <asm/system.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+
+#include <asm/sibyte/sb1250.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_smbus.h>
+
+static unsigned long long sec_bias = 0;
+static unsigned int usec_bias = 0;
+
+/* Xicor 1241 definitions */
+
+/*
+ * Register bits
+ */
+
+#define X1241REG_SR_BAT 0x80 /* currently on battery power */
+#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
+#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */
+#define X1241REG_SR_RTCF 0x01 /* clock failed */
+#define X1241REG_BL_BP2 0x80 /* block protect 2 */
+#define X1241REG_BL_BP1 0x40 /* block protect 1 */
+#define X1241REG_BL_BP0 0x20 /* block protect 0 */
+#define X1241REG_BL_WD1 0x10
+#define X1241REG_BL_WD0 0x08
+#define X1241REG_HR_MIL 0x80 /* military time format */
+
+/*
+ * Register numbers
+ */
+
+#define X1241REG_BL 0x10 /* block protect bits */
+#define X1241REG_INT 0x11 /* */
+#define X1241REG_SC 0x30 /* Seconds */
+#define X1241REG_MN 0x31 /* Minutes */
+#define X1241REG_HR 0x32 /* Hours */
+#define X1241REG_DT 0x33 /* Day of month */
+#define X1241REG_MO 0x34 /* Month */
+#define X1241REG_YR 0x35 /* Year */
+#define X1241REG_DW 0x36 /* Day of Week */
+#define X1241REG_Y2K 0x37 /* Year 2K */
+#define X1241REG_SR 0x3F /* Status register */
+
+#define X1241_CCR_ADDRESS 0x6F
+
+#define SMB_CSR(reg) (IOADDR(A_SMB_REGISTER(1, reg)))
+
+static int xicor_read(uint8_t addr)
+{
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
+ bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA));
+ bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE),
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+ /* Clear error bit by writing a 1 */
+ bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+ return -1;
+ }
+
+ return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
+}
+
+static int xicor_write(uint8_t addr, int b)
+{
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ bus_writeq(addr, SMB_CSR(R_SMB_CMD));
+ bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
+ bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
+ SMB_CSR(R_SMB_START));
+
+ while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+ ;
+
+ if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+ /* Clear error bit by writing a 1 */
+ bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+ return -1;
+ } else {
+ return 0;
+ }
+}
+
+/*
+ * In order to set the CMOS clock precisely, set_rtc_mmss has to be
+ * called 500 ms after the second nowtime has started, because when
+ * nowtime is written into the registers of the CMOS clock, it will
+ * jump to the next second precisely 500 ms later. Check the Motorola
+ * MC146818A or Dallas DS12887 data sheet for details.
+ *
+ * BUG: This routine does not handle hour overflow properly; it just
+ * sets the minutes. Usually you'll only notice that after reboot!
+ */
+int set_rtc_mmss(unsigned long nowtime)
+{
+ int retval = 0;
+ int real_seconds, real_minutes, cmos_minutes;
+
+ cmos_minutes = xicor_read(X1241REG_MN);
+ cmos_minutes = BCD2BIN(cmos_minutes);
+
+ /*
+ * since we're only adjusting minutes and seconds,
+ * don't interfere with hour overflow. This avoids
+ * messing with unknown time zones but requires your
+ * RTC not to be off by more than 15 minutes
+ */
+ real_seconds = nowtime % 60;
+ real_minutes = nowtime / 60;
+ if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
+ real_minutes += 30; /* correct for half hour time zone */
+ real_minutes %= 60;
+
+ /* unlock writes to the CCR */
+ xicor_write(X1241REG_SR, X1241REG_SR_WEL);
+ xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
+
+ if (abs(real_minutes - cmos_minutes) < 30) {
+ real_seconds = BIN2BCD(real_seconds);
+ real_minutes = BIN2BCD(real_minutes);
+ xicor_write(X1241REG_SC, real_seconds);
+ xicor_write(X1241REG_MN, real_minutes);
+ } else {
+ printk(KERN_WARNING
+ "set_rtc_mmss: can't update from %d to %d\n",
+ cmos_minutes, real_minutes);
+ retval = -1;
+ }
+
+ xicor_write(X1241REG_SR, 0);
+
+ printk("set_rtc_mmss: %02d:%02d\n", real_minutes, real_seconds);
+
+ return retval;
+}
+
+static unsigned long __init get_swarm_time(void)
+{
+ unsigned int year, mon, day, hour, min, sec, y2k;
+
+ sec = xicor_read(X1241REG_SC);
+ min = xicor_read(X1241REG_MN);
+ hour = xicor_read(X1241REG_HR);
+
+ if (hour & X1241REG_HR_MIL) {
+ hour &= 0x3f;
+ } else {
+ if (hour & 0x20)
+ hour = (hour & 0xf) + 0x12;
+ }
+
+ sec = BCD2BIN(sec);
+ min = BCD2BIN(min);
+ hour = BCD2BIN(hour);
+
+ day = xicor_read(X1241REG_DT);
+ mon = xicor_read(X1241REG_MO);
+ year = xicor_read(X1241REG_YR);
+ y2k = xicor_read(X1241REG_Y2K);
+
+ day = BCD2BIN(day);
+ mon = BCD2BIN(mon);
+ year = BCD2BIN(year);
+ y2k = BCD2BIN(y2k);
+
+ year += (y2k * 100);
+
+ return mktime(year, mon, day, hour, min, sec);
+}
+
+/*
+ * Bring up the timer at 100 Hz.
+ */
+void __init swarm_time_init(void)
+{
+ unsigned int flags;
+ int status;
+
+ /* Set up the scd general purpose timer 0 to cpu 0 */
+ sb1250_time_init();
+
+ /* Establish communication with the Xicor 1241 RTC */
+ /* XXXKW how do I share the SMBus with the I2C subsystem? */
+
+ bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
+ bus_writeq(0, SMB_CSR(R_SMB_CONTROL));
+
+ if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) {
+ printk("x1241: couldn't detect on SWARM SMBus 1\n");
+ } else {
+ if (status & X1241REG_SR_RTCF)
+ printk("x1241: battery failed -- time is probably wrong\n");
+ write_seqlock_irqsave(&xtime_lock, flags);
+ xtime.tv_sec = get_swarm_time();
+ xtime.tv_nsec = 0;
+ write_sequnlock_irqrestore(&xtime_lock, flags);
+ }
+}