| /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| /include/ "skeleton.dtsi" |
| /include/ "msm-iommu-v0.dtsi" |
| /include/ "msm8610-ion.dtsi" |
| /include/ "msm-gdsc.dtsi" |
| /include/ "msm8610-coresight.dtsi" |
| /include/ "msm8610-pm.dtsi" |
| |
| / { |
| model = "Qualcomm MSM 8610"; |
| compatible = "qcom,msm8610"; |
| interrupt-parent = <&intc>; |
| |
| intc: interrupt-controller@f9000000 { |
| compatible = "qcom,msm-qgic2"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0xf9000000 0x1000>, |
| <0xf9002000 0x1000>; |
| }; |
| |
| msmgpio: gpio@fd510000 { |
| compatible = "qcom,msm-gpio"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| reg = <0xfd510000 0x4000>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpio = <102>; |
| interrupts = <0 208 0>; |
| qcom,direct-connect-irqs = <8>; |
| }; |
| |
| aliases { |
| spi0 = &spi_0; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <1 2 0 1 3 0>; |
| clock-frequency = <19200000>; |
| }; |
| |
| qcom,msm-adsp-loader { |
| compatible = "qcom,adsp-loader"; |
| qcom,adsp-state = <0>; |
| }; |
| |
| qcom,msm-imem@fe805000 { |
| compatible = "qcom,msm-imem"; |
| reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ |
| }; |
| |
| serial@f991f000 { |
| compatible = "qcom,msm-lsuart-v14"; |
| reg = <0xf991f000 0x1000>; |
| interrupts = <0 109 0>; |
| status = "disabled"; |
| }; |
| |
| qcom,vidc@fdc00000 { |
| compatible = "qcom,msm-vidc"; |
| qcom,vidc-ns-map = <0x40000000 0x40000000>; |
| qcom,iommu-groups = <&q6_domain_ns>; |
| qcom,iommu-group-buffer-types = <0xfff>; |
| qcom,buffer-type-tz-usage-map = <0x1 0x1>, |
| <0x1fe 0x2>; |
| qcom,hfi = "q6"; |
| qcom,max-hw-load = <97200>; /* FWVGA @ 30 * 2 */ |
| }; |
| |
| usb@f9a55000 { |
| compatible = "qcom,hsusb-otg"; |
| reg = <0xf9a55000 0x400>; |
| interrupts = <0 134 0>, <0 140 0>; |
| interrupt-names = "core_irq", "async_irq"; |
| HSUSB_VDDCX-supply = <&pm8110_s1>; |
| HSUSB_1p8-supply = <&pm8110_l10>; |
| HSUSB_3p3-supply = <&pm8110_l20>; |
| |
| qcom,hsusb-otg-phy-type = <2>; |
| qcom,hsusb-otg-mode = <1>; |
| qcom,hsusb-otg-otg-control = <1>; |
| qcom,hsusb-otg-disable-reset; |
| }; |
| |
| android_usb@fe8050c8 { |
| compatible = "qcom,android-usb"; |
| reg = <0xfe8050c8 0xc8>; |
| }; |
| |
| sdcc1: qcom,sdcc@f9824000 { |
| cell-index = <1>; /* SDC1 eMMC slot */ |
| compatible = "qcom,msm-sdcc"; |
| reg = <0xf9824000 0x800>, |
| <0xf9824800 0x100>, |
| <0xf9804000 0x7000>; |
| reg-names = "core_mem", "dml_mem", "bam_mem"; |
| interrupts = <0 123 0>, <0 137 0>; |
| interrupt-names = "core_irq", "bam_irq"; |
| |
| vdd-supply = <&pm8110_l17>; |
| qcom,vdd-always-on; |
| qcom,vdd-lpm-sup; |
| qcom,vdd-voltage-level = <2900000 2900000>; |
| qcom,vdd-current-level = <9000 400000>; |
| |
| vdd-io-supply = <&pm8110_l6>; |
| qcom,vdd-io-always-on; |
| qcom,vdd-io-lpm-sup; |
| qcom,vdd-io-voltage-level = <1800000 1800000>; |
| qcom,vdd-io-current-level = <9000 60000>; |
| |
| qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ |
| qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ |
| qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ |
| qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ |
| |
| qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; |
| qcom,sup-voltages = <2900 2900>; |
| qcom,bus-width = <8>; |
| qcom,nonremovable; |
| qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; |
| }; |
| |
| sdcc2: qcom,sdcc@f98a4000 { |
| cell-index = <2>; /* SDC2 SD card slot */ |
| compatible = "qcom,msm-sdcc"; |
| reg = <0xf98a4000 0x800>, |
| <0xf98a4800 0x100>, |
| <0xf9884000 0x7000>; |
| reg-names = "core_mem", "dml_mem", "bam_mem"; |
| interrupts = <0 125 0>, <0 220 0>; |
| interrupt-names = "core_irq", "bam_irq"; |
| |
| vdd-supply = <&pm8110_l18>; |
| qcom,vdd-voltage-level = <2950000 2950000>; |
| qcom,vdd-current-level = <9000 400000>; |
| |
| vdd-io-supply = <&pm8110_l21>; |
| qcom,vdd-io-voltage-level = <1800000 2950000>; |
| qcom,vdd-io-current-level = <9000 50000>; |
| |
| qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ |
| qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */ |
| qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */ |
| qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */ |
| |
| qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>; |
| qcom,sup-voltages = <2950 2950>; |
| qcom,bus-width = <4>; |
| qcom,xpc; |
| qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; |
| qcom,current-limit = <800>; |
| }; |
| |
| qcom,sps { |
| compatible = "qcom,msm_sps"; |
| qcom,device-type = <3>; |
| }; |
| |
| qcom,smem@d600000 { |
| compatible = "qcom,smem"; |
| reg = <0xd600000 0x200000>, |
| <0xf9011000 0x1000>, |
| <0xfc428000 0x4000>; |
| reg-names = "smem", "irq-reg-base", "aux-mem1"; |
| |
| qcom,smd-modem { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <0>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x1000>; |
| qcom,pil-string = "modem"; |
| interrupts = <0 25 1>; |
| }; |
| |
| qcom,smsm-modem { |
| compatible = "qcom,smsm"; |
| qcom,smsm-edge = <0>; |
| qcom,smsm-irq-offset = <0x8>; |
| qcom,smsm-irq-bitmask = <0x2000>; |
| interrupts = <0 26 1>; |
| }; |
| |
| qcom,smd-adsp { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <1>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x100>; |
| qcom,pil-string = "adsp"; |
| interrupts = <0 156 1>; |
| }; |
| |
| qcom,smsm-adsp { |
| compatible = "qcom,smsm"; |
| qcom,smsm-edge = <1>; |
| qcom,smsm-irq-offset = <0x8>; |
| qcom,smsm-irq-bitmask = <0x200>; |
| interrupts = <0 157 1>; |
| }; |
| |
| qcom,smd-wcnss { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <6>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x20000>; |
| qcom,pil-string = "wcnss"; |
| interrupts = <0 142 1>; |
| }; |
| |
| qcom,smsm-wcnss { |
| compatible = "qcom,smsm"; |
| qcom,smsm-edge = <6>; |
| qcom,smsm-irq-offset = <0x8>; |
| qcom,smsm-irq-bitmask = <0x80000>; |
| interrupts = <0 144 1>; |
| }; |
| |
| qcom,smd-rpm { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <15>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x1>; |
| interrupts = <0 168 1>; |
| qcom,irq-no-suspend; |
| }; |
| }; |
| |
| rpm_bus: qcom,rpm-smd { |
| compatible = "qcom,rpm-smd"; |
| rpm-channel-name = "rpm_requests"; |
| rpm-channel-type = <15>; /* SMD_APPS_RPM */ |
| rpm-standalone; |
| }; |
| |
| qcom,msm-mem-hole { |
| compatible = "qcom,msm-mem-hole"; |
| qcom,memblock-remove = <0x07C00000 0x6000000>; /* Address and Size of Hole */ |
| }; |
| |
| qcom,wdt@f9017000 { |
| compatible = "qcom,msm-watchdog"; |
| reg = <0xf9017000 0x1000>; |
| interrupts = <0 3 0>, <0 4 0>; |
| qcom,bark-time = <11000>; |
| qcom,pet-time = <10000>; |
| qcom,ipi-ping; |
| }; |
| |
| qcom,acpuclk@f9011050 { |
| compatible = "qcom,acpuclk-a7"; |
| reg = <0xf9011050 0x8>; |
| reg-names = "rcg_base"; |
| a7_cpu-supply = <&pm8110_s2>; |
| a7_mem-supply = <&pm8110_l3>; |
| }; |
| |
| spmi_bus: qcom,spmi@fc4c0000 { |
| cell-index = <0>; |
| compatible = "qcom,spmi-pmic-arb"; |
| reg-names = "core", "intr", "cnfg"; |
| reg = <0xfc4cf000 0x1000>, |
| <0Xfc4cb000 0x1000>, |
| <0Xfc4ca000 0x1000>; |
| /* 190,ee0_krait_hlos_spmi_periph_irq */ |
| /* 187,channel_0_krait_hlos_trans_done_irq */ |
| interrupts = <0 190 0>, <0 187 0>; |
| qcom,not-wakeup; |
| qcom,pmic-arb-ee = <0>; |
| qcom,pmic-arb-channel = <0>; |
| }; |
| |
| i2c@f9925000 { /* BLSP-1 QUP-3 */ |
| cell-index = <0>; |
| compatible = "qcom,i2c-qup"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg-names = "qup_phys_addr"; |
| reg = <0xf9925000 0x1000>; |
| interrupt-names = "qup_err_intr"; |
| interrupts = <0 97 0>; |
| qcom,i2c-bus-freq = <100000>; |
| }; |
| |
| |
| spi_0: spi@f9923000 { /* BLSP1 QUP1 */ |
| compatible = "qcom,spi-qup-v2"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg-names = "spi_physical", "spi_bam_physical"; |
| reg = <0xf9923000 0x1000>, |
| <0xf9904000 0xF000>; |
| interrupt-names = "spi_irq", "spi_bam_irq"; |
| interrupts = <0 95 0>, <0 238 0>; |
| spi-max-frequency = <19200000>; |
| |
| gpios = <&msmgpio 3 0>, /* CLK */ |
| <&msmgpio 1 0>, /* MISO */ |
| <&msmgpio 0 0>; /* MOSI */ |
| cs-gpios = <&msmgpio 2 0>; |
| |
| qcom,infinite-mode = <0>; |
| qcom,use-bam; |
| qcom,ver-reg-exists; |
| qcom,bam-consumer-pipe-index = <12>; |
| qcom,bam-producer-pipe-index = <13>; |
| }; |
| |
| qcom,pronto@fb21b000 { |
| compatible = "qcom,pil-pronto"; |
| reg = <0xfb21b000 0x3000>, |
| <0xfc401700 0x4>, |
| <0xfd485300 0xc>; |
| reg-names = "pmu_base", "clk_base", "halt_base"; |
| interrupts = <0 149 1>; |
| vdd_pronto_pll-supply = <&pm8110_l10>; |
| |
| qcom,firmware-name = "wcnss"; |
| }; |
| |
| sound { |
| compatible = "qcom,msm8x10-audio-codec"; |
| qcom,model = "msm8x10-snd-card"; |
| }; |
| |
| qcom,msm-pcm { |
| compatible = "qcom,msm-pcm-dsp"; |
| }; |
| |
| qcom,msm-pcm-routing { |
| compatible = "qcom,msm-pcm-routing"; |
| }; |
| |
| qcom,msm-pcm-lpa { |
| compatible = "qcom,msm-pcm-lpa"; |
| }; |
| |
| qcom,msm-compr-dsp { |
| compatible = "qcom,msm-compr-dsp"; |
| }; |
| |
| qcom,msm-voip-dsp { |
| compatible = "qcom,msm-voip-dsp"; |
| }; |
| |
| qcom,msm-pcm-voice { |
| compatible = "qcom,msm-pcm-voice"; |
| }; |
| |
| qcom,msm-stub-codec { |
| compatible = "qcom,msm-stub-codec"; |
| }; |
| |
| qcom,msm-dai-fe { |
| compatible = "qcom,msm-dai-fe"; |
| }; |
| |
| qcom,msm-pcm-afe { |
| compatible = "qcom,msm-pcm-afe"; |
| }; |
| |
| qcom,msm-dai-mi2s { |
| compatible = "qcom,msm-dai-mi2s"; |
| qcom,msm-dai-q6-mi2s-prim { |
| compatible = "qcom,msm-dai-q6-mi2s"; |
| qcom,msm-dai-q6-mi2s-dev-id = <0>; |
| qcom,msm-mi2s-rx-lines = <1>; |
| qcom,msm-mi2s-tx-lines = <0>; |
| }; |
| |
| qcom,msm-dai-q6-mi2s-sec { |
| compatible = "qcom,msm-dai-q6-mi2s"; |
| qcom,msm-dai-q6-mi2s-dev-id = <1>; |
| qcom,msm-mi2s-rx-lines = <0>; |
| qcom,msm-mi2s-tx-lines = <3>; |
| }; |
| }; |
| |
| qcom,msm-dai-q6 { |
| compatible = "qcom,msm-dai-q6"; |
| qcom,msm-dai-q6-bt-sco-rx { |
| compatible = "qcom,msm-dai-q6-dev"; |
| qcom,msm-dai-q6-dev-id = <12288>; |
| }; |
| |
| qcom,msm-dai-q6-bt-sco-tx { |
| compatible = "qcom,msm-dai-q6-dev"; |
| qcom,msm-dai-q6-dev-id = <12289>; |
| }; |
| |
| qcom,msm-dai-q6-int-fm-rx { |
| compatible = "qcom,msm-dai-q6-dev"; |
| qcom,msm-dai-q6-dev-id = <12292>; |
| }; |
| |
| qcom,msm-dai-q6-int-fm-tx { |
| compatible = "qcom,msm-dai-q6-dev"; |
| qcom,msm-dai-q6-dev-id = <12293>; |
| }; |
| |
| qcom,msm-dai-q6-be-afe-pcm-rx { |
| compatible = "qcom,msm-dai-q6-dev"; |
| qcom,msm-dai-q6-dev-id = <224>; |
| }; |
| |
| qcom,msm-dai-q6-be-afe-pcm-tx { |
| compatible = "qcom,msm-dai-q6-dev"; |
| qcom,msm-dai-q6-dev-id = <225>; |
| }; |
| |
| qcom,msm-dai-q6-afe-proxy-rx { |
| compatible = "qcom,msm-dai-q6-dev"; |
| qcom,msm-dai-q6-dev-id = <241>; |
| }; |
| |
| qcom,msm-dai-q6-afe-proxy-tx { |
| compatible = "qcom,msm-dai-q6-dev"; |
| qcom,msm-dai-q6-dev-id = <240>; |
| }; |
| }; |
| |
| qcom,msm-pcm-hostless { |
| compatible = "qcom,msm-pcm-hostless"; |
| }; |
| |
| qcom,mss@fc880000 { |
| compatible = "qcom,pil-q6v5-mss"; |
| reg = <0xfc880000 0x100>, |
| <0xfd485000 0x400>, |
| <0xfc820000 0x020>, |
| <0xfc401680 0x004>, |
| <0x0d1fc000 0x4000>, |
| <0xfd485194 0x4>; |
| reg-names = "qdsp6_base", "halt_base", "rmb_base", |
| "restart_reg", "metadata_base", "cxrail_bhs_reg"; |
| |
| interrupts = <0 24 1>; |
| vdd_mss-supply = <&pm8110_s1>; |
| vdd_cx-supply = <&pm8110_s1_corner>; |
| vdd_mx-supply = <&pm8110_l3>; |
| vdd_pll-supply = <&pm8110_l10>; |
| qcom,vdd_pll = <1800000>; |
| qcom,is-loadable; |
| qcom,firmware-name = "mba"; |
| qcom,pil-self-auth; |
| }; |
| |
| qcom,lpass@fe200000 { |
| compatible = "qcom,pil-q6v5-lpass"; |
| reg = <0xfe200000 0x00100>, |
| <0xfd485100 0x00010>, |
| <0xfc4016c0 0x00004>; |
| reg-names = "qdsp6_base", "halt_base", "restart_reg"; |
| interrupts = <0 162 1>; |
| vdd_cx-supply = <&pm8110_s1_corner>; |
| qcom,firmware-name = "adsp"; |
| }; |
| |
| tsens: tsens@fc4a8000 { |
| compatible = "qcom,msm-tsens"; |
| reg = <0xfc4a8000 0x2000>, |
| <0xfc4b8000 0x1000>; |
| reg-names = "tsens_physical", "tsens_eeprom_physical"; |
| interrupts = <0 184 0>; |
| qcom,sensors = <2>; |
| qcom,slope = <2901 2846>; |
| qcom,calib-mode = "fuse_map2"; |
| qcom,calibration-less-mode; |
| qcom,tsens-local-init; |
| }; |
| |
| }; |
| |
| &gdsc_vfe { |
| status = "ok"; |
| }; |
| |
| &gdsc_oxili_cx { |
| status = "ok"; |
| }; |
| |
| &lpass_iommu { |
| status = "ok"; |
| }; |
| |
| &copss_iommu { |
| status = "ok"; |
| }; |
| |
| &mdpe_iommu { |
| status = "ok"; |
| }; |
| |
| &mdps_iommu { |
| status = "ok"; |
| }; |
| |
| &gfx_iommu { |
| status = "ok"; |
| }; |
| |
| &vfe_iommu { |
| status = "ok"; |
| }; |
| |
| /include/ "msm8610-iommu-domains.dtsi" |
| |
| /include/ "msm-pm8110.dtsi" |
| /include/ "msm8610-regulator.dtsi" |
| |
| &pm8110_vadc { |
| chan@0 { |
| label = "usb_in"; |
| reg = <0>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <4>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <0>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@2 { |
| label = "vchg_sns"; |
| reg = <2>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <3>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <0>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@5 { |
| label = "vcoin"; |
| reg = <5>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <1>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <0>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@6 { |
| label = "vbat_sns"; |
| reg = <6>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <1>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <0>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@7 { |
| label = "vph_pwr"; |
| reg = <7>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <1>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <0>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@30 { |
| label = "batt_therm"; |
| reg = <0x30>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "ratiometric"; |
| qcom,scale-function = <1>; |
| qcom,hw-settle-time = <2>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@31 { |
| label = "batt_id"; |
| reg = <0x31>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "ratiometric"; |
| qcom,scale-function = <0>; |
| qcom,hw-settle-time = <2>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@b2 { |
| label = "xo_therm_pu2"; |
| reg = <0xb2>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "ratiometric"; |
| qcom,scale-function = <4>; |
| qcom,hw-settle-time = <2>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| }; |
| |
| |