Merge "msm: camera: Add YUV formats for IO format to BPP mapping"
diff --git a/Documentation/cpuidle/driver.txt b/Documentation/cpuidle/driver.txt
index 7a9e09e..1b0d81d 100644
--- a/Documentation/cpuidle/driver.txt
+++ b/Documentation/cpuidle/driver.txt
@@ -15,11 +15,17 @@
cpuidle driver initializes the cpuidle_device structure for each CPU device
and registers with cpuidle using cpuidle_register_device.
+If all the idle states are the same, the wrapper function cpuidle_register
+could be used instead.
+
It can also support the dynamic changes (like battery <-> AC), by using
cpuidle_pause_and_lock, cpuidle_disable_device and cpuidle_enable_device,
cpuidle_resume_and_unlock.
Interfaces:
+extern int cpuidle_register(struct cpuidle_driver *drv,
+ const struct cpumask *const coupled_cpus);
+extern int cpuidle_unregister(struct cpuidle_driver *drv);
extern int cpuidle_register_driver(struct cpuidle_driver *drv);
extern void cpuidle_unregister_driver(struct cpuidle_driver *drv);
extern int cpuidle_register_device(struct cpuidle_device *dev);
diff --git a/Documentation/devicetree/bindings/arm/msm/acpuclock/clock-a7.txt b/Documentation/devicetree/bindings/arm/msm/acpuclock/clock-a7.txt
new file mode 100644
index 0000000..10eb0fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/acpuclock/clock-a7.txt
@@ -0,0 +1,37 @@
+* Qualcomm Application CPU clock driver
+
+clock-a7 is the driver for the Root Clock Generator (rcg) hw which controls
+the cpu rate. RCGs support selecting one of several clock inputs, as well as
+a configurable divider. This hw is different than normal rcgs in that it may
+optionally have a register which encodes the maximum rate supported by hw.
+
+Required properties:
+- compatible: "qcom,clock-a7-8226"
+- reg: pairs of physical address and region size
+- reg-names: "rcg-base" is expected
+- clock-names: list of names of clock inputs
+- qcom,speedX-bin-vZ:
+ A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
+ Format: <freq uV>
+ This represents the max frequency possible for each possible
+ power configuration for a CPU that's binned as speed bin X,
+ speed bin revision Z. Speed bin values can be between [0-7]
+ and the version can be between [0-3].
+
+- cpu-vdd-supply: regulator phandle for cpu power domain.
+
+Optional properties:
+- reg-names: "efuse"
+
+Example:
+ qcom,acpuclk@f9011050 {
+ compatible = "qcom,clock-a7-8226";
+ reg = <0xf9011050 0x8>;
+ reg-names = "rcg_base";
+ cpu-vdd-supply = <&apc_vreg_corner>;
+
+ clock-names = "clk-4", "clk-5";
+ qcom,speed0-bin-v0 =
+ <384000000 1150000>,
+ <600000000 1200000>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/msm/cpr-regulator.txt b/Documentation/devicetree/bindings/arm/msm/cpr-regulator.txt
index a0b2f6d..99de826 100644
--- a/Documentation/devicetree/bindings/arm/msm/cpr-regulator.txt
+++ b/Documentation/devicetree/bindings/arm/msm/cpr-regulator.txt
@@ -11,7 +11,7 @@
bits to indicate what bin (and voltage range) a chip is in.
Required properties:
-- compatible: Must be "qcom,cpr-regulator"
+- compatible: Must be "qti,cpr-regulator"
- reg: Register addresses for RBCPR, RBCPR clock
select, PVS and CPR eFuse address
- reg-names: Register names. Must be "rbcpr", "rbcpr_clk",
@@ -22,91 +22,106 @@
should be 1 for SVS corner
- regulator-max-microvolt: Maximum corner value as max constraint, which
should be 4 for SUPER_TURBO or 3 for TURBO
-- qcom,pvs-init-voltage: A list of integers whose length is equal to 2
- to the power of qcom,pvs-fuse[num-of-bits]. The
+- qti,pvs-init-voltage: A list of integers whose length is equal to 2
+ to the power of qti,pvs-fuse[num-of-bits]. The
location or 0-based index of an element in the
list corresponds to the bin number. The value of
each integer corresponds to the initial voltage
of the PVS bin in turbo mode in microvolts.
-- qcom,pvs-corner-ceiling-slow: Ceiling voltages of all corners for APC_PVS_SLOW
-- qcom,pvs-corner-ceiling-nom: Ceiling voltages of all corners for APC_PVS_NOM
-- qcom,pvs-corner-ceiling-fast: Ceiling voltages of all corners for APC_PVS_FAST
+- qti,pvs-corner-ceiling-slow: Ceiling voltages of all corners for APC_PVS_SLOW
+- qti,pvs-corner-ceiling-nom: Ceiling voltages of all corners for APC_PVS_NOM
+- qti,pvs-corner-ceiling-fast: Ceiling voltages of all corners for APC_PVS_FAST
The ceiling voltages for each of above three
properties may look like this:
0 (SVS voltage): 1050000 uV
1 (NORMAL voltage): 1150000 uV
2 (TURBO voltage): 1275000 uV
- vdd-apc-supply: Regulator to supply VDD APC power
-- qcom,vdd-apc-step-up-limit: Limit of vdd-apc-supply steps for scaling up.
-- qcom,vdd-apc-step-down-limit: Limit of vdd-apc-supply steps for scaling down.
-- qcom,cpr-ref-clk: The reference clock in kHz.
-- qcom,cpr-timer-delay: The delay in microseconds for the timer interval.
-- qcom,cpr-timer-cons-up: Consecutive number of timer interval (qcom,cpr-timer-delay)
+- qti,vdd-apc-step-up-limit: Limit of vdd-apc-supply steps for scaling up.
+- qti,vdd-apc-step-down-limit: Limit of vdd-apc-supply steps for scaling down.
+- qti,cpr-ref-clk: The reference clock in kHz.
+- qti,cpr-timer-delay: The delay in microseconds for the timer interval.
+- qti,cpr-timer-cons-up: Consecutive number of timer interval (qti,cpr-timer-delay)
occurred before issuing UP interrupt.
-- qcom,cpr-timer-cons-down: Consecutive number of timer interval (qcom,cpr-timer-delay)
+- qti,cpr-timer-cons-down: Consecutive number of timer interval (qti,cpr-timer-delay)
occurred before issuing DOWN interrupt.
-- qcom,cpr-irq-line: Internal interrupt route signal of RBCPR, one of 0, 1 or 2.
-- qcom,cpr-step-quotient: Number of CPR quotient (Ring Oscillator(RO) count) per vdd-apc-supply step
+- qti,cpr-irq-line: Internal interrupt route signal of RBCPR, one of 0, 1 or 2.
+- qti,cpr-step-quotient: Number of CPR quotient (Ring Oscillator(RO) count) per vdd-apc-supply step
to issue error_steps.
-- qcom,cpr-up-threshold: The threshold for CPR to issue interrupt when
+- qti,cpr-up-threshold: The threshold for CPR to issue interrupt when
error_steps is greater than it when stepping up.
-- qcom,cpr-down-threshold: The threshold for CPR to issue interrupt when
+- qti,cpr-down-threshold: The threshold for CPR to issue interrupt when
error_steps is greater than it when stepping down.
-- qcom,cpr-idle-clocks: Idle clock cycles RO can be in.
-- qcom,cpr-gcnt-time: The time for gate count in microseconds.
-- qcom,cpr-apc-volt-step: The voltage in microvolt per CPR step, such as 5000uV.
+- qti,cpr-idle-clocks: Idle clock cycles RO can be in.
+- qti,cpr-gcnt-time: The time for gate count in microseconds.
+- qti,cpr-apc-volt-step: The voltage in microvolt per CPR step, such as 5000uV.
-- qcom,pvs-fuse-redun-sel: Array of 4 elements to indicate where to read the bits and what value to
+- qti,pvs-fuse-redun-sel: Array of 5 elements to indicate where to read the bits, what value to
compare with in order to decide if the redundant PVS fuse bits would be
- used instead of the original bits. The 4 elements with index [0..3] are:
+ used instead of the original bits and method to read fuse row, reading
+ register through SCM or directly. The 5 elements with index [0..4] are:
[0] => the fuse row number of the selector
[1] => LSB bit position of the bits
[2] => number of bits
[3] => the value to indicate redundant selection
+ [4] => fuse reading method, 0 for direct reading or 1 for SCM reading
When the value of the fuse bits specified by first 3 elements equals to
the value in 4th element, redundant PVS fuse bits should be selected.
- Otherwise, the original PVS bits should be selected.
-- qcom,pvs-fuse: Array of three elements to indicate the bits for PVS fuse. The array
- should have index and value like this:
+ Otherwise, the original PVS bits should be selected. If the 5th
+ element is 0, read the fuse row from register directly. Otherwise,
+ read it through SCM.
+- qti,pvs-fuse: Array of 4 elements to indicate the bits for PVS fuse and read method.
+ The array should have index and value like this:
[0] => the PVS fuse row number
[1] => LSB bit position of the bits
[2] => number of bits
-- qcom,pvs-fuse-redun: Array of three elements to indicate the bits for redundant PVS fuse.
+ [3] => fuse reading method, 0 for direct reading or 1 for SCM reading
+- qti,pvs-fuse-redun: Array of 4 elements to indicate the bits for redundant PVS fuse.
The array should have index and value like this:
[0] => the redundant PVS fuse row number
[1] => LSB bit position of the bits
[2] => number of bits
-
-- qcom,cpr-fuse-redun-sel: Array of 4 elements to indicate where to read the bits and what value to
+ [3] => fuse reading method, 0 for direct reading or 1 for SCM reading
+- qti,cpr-fuse-redun-sel: Array of 5 elements to indicate where to read the bits, what value to
compare with in order to decide if the redundant CPR fuse bits would be
- used instead of the original bits. The 4 elements with index [0..3] are:
+ used instead of the original bits and method to read fuse row, using SCM
+ to read or read register directly. The 5 elements with index [0..4] are:
[0] => the fuse row number of the selector
[1] => LSB bit position of the bits
[2] => number of bits
[3] => the value to indicate redundant selection
+ [4] => fuse reading method, 0 for direct reading or 1 for SCM reading
When the value of the fuse bits specified by first 3 elements equals to
the value in 4th element, redundant CPR fuse bits should be selected.
- Otherwise, the original CPR bits should be selected.
-- qcom,cpr-fuse-row: Row number of CPR fuse
-- qcom,cpr-fuse-bp-cpr-disable: Bit position of the bit to indicate if CPR should be disable
-- qcom,cpr-fuse-bp-scheme: Bit position of the bit to indicate if it's a global/local scheme
-- qcom,cpr-fuse-target-quot: Array of bit positions in fuse for Target Quotient of all corners.
+ Otherwise, the original CPR bits should be selected. If the 5th element
+ is 0, read the fuse row from register directly. Otherwise, read it through
+ SCM.
+- qti,cpr-fuse-row: Array of row number of CPR fuse and method to read that row. It should have
+ index and value like this:
+ [0] => the fuse row number
+ [1] => fuse reading method, 0 for direct reading or 1 for SCM reading
+- qti,cpr-fuse-bp-cpr-disable: Bit position of the bit to indicate if CPR should be disable
+- qti,cpr-fuse-bp-scheme: Bit position of the bit to indicate if it's a global/local scheme
+- qti,cpr-fuse-target-quot: Array of bit positions in fuse for Target Quotient of all corners.
It should have index and value like this:
[0] => bit position of the LSB bit for SVS target quotient
[1] => bit position of the LSB bit for NOMINAL target quotient
[2] => bit position of the LSB bit for TURBO target quotient
-- qcom,cpr-fuse-ro-sel: Array of bit positions in fuse for RO select of all corners.
+- qti,cpr-fuse-ro-sel: Array of bit positions in fuse for RO select of all corners.
It should have index and value like this:
[0] => bit position of the LSB bit for SVS RO select bits
[1] => bit position of the LSB bit for NOMINAL RO select bits
[2] => bit position of the LSB bit for TURBO RO select bits
-- qcom,cpr-fuse-redun-row: Row number of the redundant CPR fuse
-- qcom,cpr-fuse-redun-target-quot: Array of bit positions in fuse for redundant Target Quotient of all corners.
+- qti,cpr-fuse-redun-row: Array of row number of redundant CPR fuse and method to read that
+ row. It should have index and value like this:
+ [0] => the redundant fuse row number
+ [1] => the value to indicate reading the fuse row directly or using SCM
+- qti,cpr-fuse-redun-target-quot: Array of bit positions in fuse for redundant Target Quotient of all corners.
It should have index and value like this:
[0] => bit position of the LSB bit for redundant SVS target quotient
[1] => bit position of the LSB bit for redundant NOMINAL target quotient
[2] => bit position of the LSB bit for redundant TURBO target quotient
-- qcom,cpr-fuse-redun-ro-sel: Array of bit positions in eFuse for redundant RO select.
+- qti,cpr-fuse-redun-ro-sel: Array of bit positions in eFuse for redundant RO select.
It should have index and value like this:
[0] => bit position of the LSB bit for redundant SVS RO select bits
[1] => bit position of the LSB bit for redundant NOMINAL RO select bits
@@ -116,30 +131,88 @@
Optional properties:
- vdd-mx-supply: Regulator to supply memory power as dependency
of VDD APC.
-- qcom,vdd-mx-vmax: The maximum voltage in uV for vdd-mx-supply. This
+- qti,vdd-mx-vmax: The maximum voltage in uV for vdd-mx-supply. This
is required when vdd-mx-supply is present.
-- qcom,vdd-mx-vmin-method: The method to determine the minimum voltage for
+- qti,vdd-mx-vmin-method: The method to determine the minimum voltage for
vdd-mx-supply, which can be one of following
choices compared with VDD APC:
0 => equal to the voltage(vmin) of VDD APC
1 => equal to PVS corner ceiling voltage
2 => equal to slow speed corner ceiling
- 3 => equal to qcom,vdd-mx-vmax
+ 3 => equal to qti,vdd-mx-vmax
This is required when vdd-mx-supply is present.
-- qcom,cpr-fuse-redun-bp-cpr-disable: Redundant bit position of the bit to indicate if CPR should be disable
-- qcom,cpr-fuse-redun-bp-scheme: Redundant bit position of the bit to indicate if it's a global/local scheme
+- qti,cpr-fuse-redun-bp-cpr-disable: Redundant bit position of the bit to indicate if CPR should be disable
+- qti,cpr-fuse-redun-bp-scheme: Redundant bit position of the bit to indicate if it's a global/local scheme
This property is required if cpr-fuse-redun-bp-cpr-disable
is present, and vise versa.
-- qcom,cpr-enable: Present: CPR enabled by default.
+- qti,cpr-enable: Present: CPR enabled by default.
Not Present: CPR disable by default.
-- qcom,use-tz-api: Present: CPR reads efuse parameters through trustzone API.
- Not Present: CPR reads efuse parameters directly.
-
+- qti,cpr-fuse-cond-min-volt-sel: Array of 5 elements to indicate where to read the bits, what value to
+ compare with in order to decide if the conditional minimum apc voltage needs
+ to be applied and the fuse reading method.
+ The 5 elements with index[0..4] are:
+ [0] => the fuse row number;
+ [1] => LSB bit position of the bits;
+ [2] => number of the bits;
+ [3] => the expected data to read;
+ [4] => fuse reading method, 0 for direct reading or 1 for SCM reading;
+ When the value of the fuse bits specified by first 3 elements is not equal to
+ the value in 4th element, then set the apc voltage for all parts running
+ at each voltage corner to be not lower than the voltage defined
+ using "qti,cpr-cond-min-voltage".
+- qti,cpr-cond-min-voltage: Minimum voltage in microvolts for SVS, NOM and TURBO mode if the fuse bits
+ defined in qti,cpr-fuse-cond-min-volt-sel have not been programmed with the
+ expected data. This is required if cpr-fuse-cond-min-volt-sel is present.
+- qti,cpr-fuse-uplift-sel: Array of 5 elements to indicate where to read the bits, what value to
+ compare with in order to enable or disable the pvs voltage uplift workaround,
+ and the fuse reading method.
+ The 5 elements with index[0..4] are:
+ [0]: => the fuse row number of the selector;
+ [1]: => LSB bit position of the bits;
+ [2]: => number of the bits;
+ [3]: => the value to indicate if the apc pvs voltage uplift workaround will
+ be enabled;
+ [4]: => fuse reading method, 0 for direct reading or 1 for SCM reading.
+ When the value of the fuse bits specified by first 3 elements equals to the
+ value in 4th element, the pvs voltage uplift workaround will be enabled.
+- qti,speed-bin-fuse-sel: Array of 4 elements to indicate where to read the speed bin of the processor,
+ and the fuse reading method.
+ The 4 elements with index[0..3] are:
+ [0]: => the fuse row number of the selector;
+ [1]: => LSB bit position of the bits;
+ [2]: => number of the bits;
+ [3]: => fuse reading method, 0 for direct reading or 1 for SCM reading.
+ This is required if cpr-fuse-uplift-disable-sel is present.
+- qti,cpr-uplift-voltage: Uplift in microvolts used for increasing pvs init voltage. If this property is present,
+ This is required if cpr-fuse-uplift-disable-sel is present.
+- qti,cpr-uplift-max-volt: Maximum voltage in microvolts used for pvs voltage uplift workaround to limit
+ the maximum pvs voltage.
+ This is required if cpr-fuse-uplift-disable-sel is present.
+- qti,cpr-uplift-quotient: Three numbers used for pvs voltage uplift workaround to be added to the target
+ quotient for each corner.
+ The 3 quotient increment with index[0..2] are:
+ [0]: => for SVS corner target quotient;
+ [1]: => for NORM corner target quotient;
+ [2]: => for TURBO corner target quotient;
+ This is required if cpr-fuse-uplift-disable-sel is present.
+- qti,cpr-uplift-speed-bin: The speed bin value corresponding to one type of processor which needs to apply the
+ pvs voltage uplift workaround.
+ This is required if cpr-fuse-uplift-disable-sel is present.
+- qti,cpr-quot-adjust-table: Array of 4-tuples in which each 4-tuple indicates the speed bin
+ of the CPU, the frequency of the CPU, the quotient adjustment and the voltage corner to use.
+ The 4 elements in one 4-tuple are:
+ [0]: => the speed bin of the CPU;
+ [1]: => the frequency in kHz of the CPU;
+ [2]: => the quotient adjustment of the corresponding frequency;
+ [3]: => the voltage corner to use.
+ If the speed bin in a tuple is eqaul to the speed bin of the CPU, then the quotient
+ adjustment would be subtracted from the quotient value of the voltage corner
+ when the CPU is running at that frequency.
Example:
apc_vreg_corner: regulator@f9018000 {
status = "okay";
- compatible = "qcom,cpr-regulator";
+ compatible = "qti,cpr-regulator";
reg = <0xf9018000 0x1000>, <0xfc4b8000 0x1000>;
reg-names = "rbcpr", "efuse_addr";
interrupts = <0 15 0>;
@@ -147,11 +220,11 @@
regulator-min-microvolt = <1>;
regulator-max-microvolt = <3>;
- qcom,pvs-fuse = <22 6 5>;
- qcom,pvs-fuse-redun-sel = <22 24 3 2>;
- qcom,pvs-fuse-redun = <22 27 5>;
+ qti,pvs-fuse = <22 6 5 1>;
+ qti,pvs-fuse-redun-sel = <22 24 3 2 1>;
+ qti,pvs-fuse-redun = <22 27 5 1>;
- qcom,pvs-init-voltage = <1330000 1330000 1330000 1320000
+ qti,pvs-init-voltage = <1330000 1330000 1330000 1320000
1310000 1300000 1290000 1280000
1270000 1260000 1250000 1240000
1230000 1220000 1210000 1200000
@@ -159,35 +232,47 @@
1150000 1140000 1140000 1140000
1140000 1140000 1140000 1140000
1140000 1140000 1140000 1140000>;
- qcom,pvs-corner-ceiling-slow = <1050000 1160000 1275000>;
- qcom,pvs-corner-ceiling-nom = <975000 1075000 1200000>;
- qcom,pvs-corner-ceiling-fast = <900000 1000000 1140000>;
+ qti,pvs-corner-ceiling-slow = <1050000 1160000 1275000>;
+ qti,pvs-corner-ceiling-nom = <975000 1075000 1200000>;
+ qti,pvs-corner-ceiling-fast = <900000 1000000 1140000>;
vdd-apc-supply = <&pm8226_s2>;
vdd-mx-supply = <&pm8226_l3_ao>;
- qcom,vdd-mx-vmax = <1350000>;
- qcom,vdd-mx-vmin-method = <1>;
- qcom,vdd-apc-step-up-limit = <1>;
- qcom,vdd-apc-step-down-limit = <1>;
- qcom,cpr-ref-clk = <19200>;
- qcom,cpr-timer-delay = <5000>;
- qcom,cpr-timer-cons-up = <1>;
- qcom,cpr-timer-cons-down = <2>;
- qcom,cpr-irq-line = <0>;
- qcom,cpr-step-quotient = <15>;
- qcom,cpr-up-threshold = <1>;
- qcom,cpr-down-threshold = <2>;
- qcom,cpr-idle-clocks = <5>;
- qcom,cpr-gcnt-time = <1>;
- qcom,cpr-apc-volt-step = <5000>;
+ qti,vdd-mx-vmax = <1350000>;
+ qti,vdd-mx-vmin-method = <1>;
+ qti,vdd-apc-step-up-limit = <1>;
+ qti,vdd-apc-step-down-limit = <1>;
+ qti,cpr-ref-clk = <19200>;
+ qti,cpr-timer-delay = <5000>;
+ qti,cpr-timer-cons-up = <1>;
+ qti,cpr-timer-cons-down = <2>;
+ qti,cpr-irq-line = <0>;
+ qti,cpr-step-quotient = <15>;
+ qti,cpr-up-threshold = <1>;
+ qti,cpr-down-threshold = <2>;
+ qti,cpr-idle-clocks = <5>;
+ qti,cpr-gcnt-time = <1>;
+ qti,cpr-apc-volt-step = <5000>;
- qcom,cpr-fuse-row = <138>;
- qcom,cpr-fuse-bp-cpr-disable = <36>;
- qcom,cpr-fuse-bp-scheme = <37>;
- qcom,cpr-fuse-target-quot = <24 12 0>;
- qcom,cpr-fuse-ro-sel = <54 38 41>;
- qcom,cpr-fuse-redun-sel = <138 57 1 1>;
- qcom,cpr-fuse-redun-row = <139>;
- qcom,cpr-fuse-redun-target-quot = <24 12 0>;
- qcom,cpr-fuse-redun-ro-sel = <46 36 39>;
+ qti,cpr-fuse-row = <138 1>;
+ qti,cpr-fuse-bp-cpr-disable = <36>;
+ qti,cpr-fuse-bp-scheme = <37>;
+ qti,cpr-fuse-target-quot = <24 12 0>;
+ qti,cpr-fuse-ro-sel = <54 38 41>;
+ qti,cpr-fuse-redun-sel = <138 57 1 1 1>;
+ qti,cpr-fuse-redun-row = <139 1>;
+ qti,cpr-fuse-redun-target-quot = <24 12 0>;
+ qti,cpr-fuse-redun-ro-sel = <46 36 39>;
+ qti,cpr-fuse-cond-min-volt-sel = <54 42 6 7 1>;
+ qti,cpr-cond-min-voltage = <1140000>;
+ qti,cpr-fuse-uplift-sel = <22 53 1 0 0>;
+ qti,cpr-uplift-voltage = <50000>;
+ qti,cpr-uplift-quotient = <0 0 120>;
+ qti,cpr-uplift-max-volt = <1350000>;
+ qti,cpr-uplift-speed-bin = <1>;
+ qti,speed-bin-fuse-sel = <22 0 3 0>;
+ qti,cpr-quot-adjust-table = <1 998400 450 3>,
+ <1 1094400 375 3>, <1 1190400 300 3>,
+ <1 1305600 225 3>, <1 1344000 187 3>,
+ <1 1401600 150 3>, <1 1497600 75 3>;
};
diff --git a/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt b/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
index 917ea75..0696730 100644
--- a/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
+++ b/Documentation/devicetree/bindings/arm/msm/lpm-levels.txt
@@ -1,52 +1,106 @@
* Low Power Management Levels
The application processor in MSM can do a variety of C-States for low power
-management. These C-States are invoked by the CPUIdle framework when the core
-becomes idle. But based on the time available until the next scheduled wakeup,
-the system can do several low power modes. The combination is captured in the
-device tree as lpm-level.
+management. The LPM module performs the CPU and System low power modes based
+on it latency and residency information of the individual CPU/System low power
+levels.
-The required nodes for lpm-levels are:
+The first level node represents the properties of the system and includes
+second level node to represent the low power modes of cpu and system.
+
+[First Level Nodes]
+Required properties:
- compatible: "qcom,lpm-levels"
-- reg: The numeric level id
+
+The optional nodes for the First level nodes are:
+- qcom,no-l2-saw: Indicates if this target has an L2 SAW (SPM and AVS wrapper).
+- qcom,default-l2-state: Indicates what the default low power state of the L2
+ SAW should be. This property should be mentioned when there is
+ a L2 saw.
+- qcom,allow-synced-levels: Indicates if certain low power modes should be
+ synchronized across all cores so as to configure a system
+ low power mode.
+
+[Second Level Nodes]
+Required properties to define CPU low power modes :
+- compatible = "qcom,cpu-modes";
- qcom,mode: The sleep mode of the processor, values for the property are:
"wfi" - Wait for Interrupt
- "ramp_down_and_wfi" - Ramp down and wait for interrupt
+ "retention" - Retention
"standalone_pc" - Standalone power collapse
"pc" - Power Collapse
- "retention" - Retention
- "pc_suspend" - Suspended Power Collapse
- "pc_no_xo_shutdown" - Power Collapse with no XO shutdown
+- qcom,latency-us: The latency in handling the interrupt if this level was
+ chosen, in uSec
+- qcom,ss-power: The steady state power expelled when the processor is in this
+ level in mWatts
+- qcom,energy-overhead: The energy used up in entering and exiting this level
+ in mWatts.uSec
+- qcom,time-overhead: The time spent in entering and exiting this level in uS
+
+Required propertieis to define System low power mode :
+- compatible: "qcom,system-modes"
- qcom,l2: The state of L2 cache. Values are:
"l2_cache_pc" - L2 cache in power collapse
- "l2_cache_pc_no_rpm" - L2 cache in power collapse. This mode wouldn't inform the RPM
+ "l2_cache_pc_no_rpm" - L2 cache in power collapse. This mode
+ wouldn't inform the RPM
"l2_cache_retenetion" - L2 cache in retention
"l2_cache_gdhs" - L2 cache in GDHS
"l2_cache_active" - L2 cache in active mode
-- qcom,latency-us: The latency in handling the interrupt if this level was
- chosen, in uSec
-- qcom,ss-power: The steady state power expelled when the processor is in this
- level in mWatts
-- qcom,energy-overhead: The energy used up in entering and exiting this level
- in mWatts.uSec
-- qcom,time-overhead: The time spent in entering and exiting this level in uS
-The optional nodes for lpm-levels are :
-- qcom,no-l2-saw: Indicates if this target has an L2 SAW (SPM and AVS wrapper).
-- qcom,default-l2-state: Indicates what the default low power state of the L2 SAW should be. This property is used only when there is an L2 SAW.
+- qcom,latency-us: The latency in handling the interrupt if this level was
+ chosen, in uSec
+- qcom,ss-power: The steady state power expelled when the processor is in this
+ level in mWatts
+- qcom,energy-overhead: The energy used up in entering and exiting this level
+ in mWatts.uSec
+- qcom,time-overhead: The time spent in entering and exiting this level in uS
+- qcom,min-cpu-mode: The min cpu sleep mode at which the given system level is
+ valid. All cpus should have entered this low power mode before
+ this system level can be chosen.
Example:
-
qcom,lpm-levels {
- qcom,no-l2-saw;
- qcom,lpm-level@0 {
- reg = <0>;
- qcom,mode = "wfi";
- qcom,l2 = "l2_cache_active";
- qcom,latency-us = <100>;
- qcom,ss-power = <650>;
- qcom,energy-overhead = <801>;
- qcom,time-overhead = <200>;
- };
+ compatible = "qcom,lpm-levels";
+ qcom,default-l2-state = "l2_cache_retention";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,cpu-modes {
+ compatible = "qcom,cpu-modes";
+ qcom,cpu-mode@0 {
+ qcom,mode = "wfi";
+ qcom,latency-us = <1>;
+ qcom,ss-power = <715>;
+ qcom,energy-overhead = <17700>;
+ qcom,time-overhead = <2>;
+ };
+
+ qcom,cpu-mode@1 {
+ qcom,mode = "retention";
+ qcom,latency-us = <35>;
+ qcom,ss-power = <542>;
+ qcom,energy-overhead = <34920>;
+ qcom,time-overhead = <40>;
+ };
+ };
+ qcom,system-modes {
+ compatible = "qcom,system-modes";
+
+ qcom,system-mode@0 {
+ qcom,l2 = "l2_cache_gdhs";
+ qcom,latency-us = <20000>;
+ qcom,ss-power = <163>;
+ qcom,energy-overhead = <1577736>;
+ qcom,time-overhead = <5067>;
+ };
+
+ qcom,system-mode@1 {
+ qcom,l2 = "l2_cache_pc";
+ qcom,latency-us = <30000>;
+ qcom,ss-power = <83>;
+ qcom,energy-overhead = <2274420>;
+ qcom,time-overhead = <6605>;
+ };
+ };
};
diff --git a/Documentation/devicetree/bindings/arm/msm/msm_ion.txt b/Documentation/devicetree/bindings/arm/msm/msm_ion.txt
index f3cf8f3..d2e0916 100644
--- a/Documentation/devicetree/bindings/arm/msm/msm_ion.txt
+++ b/Documentation/devicetree/bindings/arm/msm/msm_ion.txt
@@ -37,6 +37,8 @@
- qcom,memory-reservation-size: size of reserved memory for the ION heap.
- qcom,memory-reservation-type: type of memory to be reserved
(see memory-reserve.txt for information about memory reservations)
+- qcom,default-prefetch-size: Based value to be used for prefetching
+ optimizations. Ignored if the heap does not support prefetching.
Example:
qcom,ion {
diff --git a/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt b/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt
index 3947f75..15b94ca 100644
--- a/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt
+++ b/Documentation/devicetree/bindings/arm/msm/msm_thermal.txt
@@ -43,6 +43,29 @@
- qcpm,cpu-sensors: List of type names in thermal zone device struct which maps
to cpu0, cpu1, cpu2, cpu3 in sequence depending on how many
cpus there are.
+- qcom,freq-mitigation-temp: Threshold temperature to mitigate
+ the CPU max frequency in degC. This will be
+ used when polling based frequency control is disabled.
+ The difference between freq-mitigation-temp
+ and limit-temp is that limit-temp is used during
+ early boot prior to thermal_sys being available for registering
+ temperature thresholds. Also, this emergency frequency
+ mitigation is a single step frequency mitigation to a predefined value
+ as opposed to the step by step frequency mitigation during boot-up.
+- qcom,freq-mitigation-temp-hysteresis: Degrees C below which thermal will not mitigate the
+ cpu max frequency.
+- qcom,freq-mitigation-value: The frequency value (in kHz) to which the thermal
+ should mitigate the CPU, when the freq-mitigation-temp
+ threshold is reached.
+- qcom,freq-mitigation-control-mask: The frequency mitigation bitmask that will be
+ used to determine if KTM should do emergency frequency
+ mitigation for a core or not. A mask of 0x00 indicates the
+ mitigation is disabled for all the cores and a mask of 0x05
+ indicates this mitigation is enabled for cpu-0 and cpu-2.
+ Note: For KTM's frequency mitigation to work, the data for all the
+ above four properties (qcom,freq-mitigation-temp; qcom,
+ freq-mitigation-temp-hysteresis; qcom,freq-mitigation-value and
+ qcom,freq-mitigation-control-mask) should be populated.
- qcom,vdd-restriction-temp: When temperature is below this threshold, will
enable vdd restriction which will set higher voltage on
key voltage rails, in degC.
@@ -67,6 +90,20 @@
phandle_of_regulator is defined by reuglator device tree.
Optional child nodes
+- qti,pmic-opt-curr-temp: Threshold temperature for requesting optimum current (request
+ dual phase) for rails with PMIC, in degC. If this property exists,
+ then the properties, qti,pmic-opt-curr-temp-hysteresis and
+ qti,pmic-opt-curr-regs should also be defined to enable this
+ feature.
+- qti,pmic-opt-curr-temp-hysteresis: Degree below the threshold to disable the optimum
+ current request for a rail, in degC. If this property exists,
+ then the properties, qti,pmic-opt-curr-temp and
+ qti,pmic-opt-curr-regs should also be defined to enable
+ this feature.
+- qti,pmic-opt-curr-regs: Name of the rails for which the optimum current should be
+ requested. If this property exists, then the properties,
+ qti,pmic-opt-curr-temp and qti,pmic-opt-curr-temp-hysteresis
+ should also be defined to enable this feature.
- qcom,<vdd restriction child node name>: Define the name of the child node.
If this property exisits, qcom,vdd-rstr-reg, qcom,levels
need to exist. qcom,min-level is optional if qcom,freq-req
@@ -97,11 +134,18 @@
qcom,hotplug-temp-hysteresis = <20>;
qcom,cpu-sensors = "tsens_tz_sensor5", "tsens_tz_sensor6",
"tsens_tz_sensor7", "tsens_tz_sensor8";
+ qcom,freq-mitigation-temp = <110>;
+ qcom,freq-mitigation-temp-hysteresis = <20>;
+ qcom,freq-mitigation-value = <960000>;
+ qcom,freq-mitigation-control-mask = <0x01>;
qcom,pmic-sw-mode-temp = <90>;
qcom,pmic-sw-mode-temp-hysteresis = <80>;
qcom,pmic-sw-mode-regs = "vdd-dig";
qcom,vdd-restriction-temp = <5>;
qcom,vdd-restriction-temp-hysteresis = <10>;
+ qti,pmic-opt-curr-temp = <85>;
+ qti,pmic-opt-curr-temp-hysteresis = <10>;
+ qti,pmic-opt-curr-regs = "vdd-dig";
vdd-dig-supply=<&pm8841_s2_floor_corner>
qcom,vdd-dig-rstr{
diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
index 08d2c2d..0e236f2 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
@@ -178,34 +178,33 @@
- qcom,mdss-dsi-bllp-power-mode: Boolean to determine DSI lane state during
blanking low power period (BLLP) mode.
- qcom,mdss-dsi-traffic-mode: Specifies the panel traffic mode.
- 0 = non burst with sync pulses (default mode).
- 1 = non burst with sync start event.
- 2 = burst mode.
+ "non_burst_sync_pulse" = non burst with sync pulses (default).
+ "non_burst_sync_event" = non burst with sync start event.
+ "burst_mode" = burst mode.
- qcom,mdss-dsi-pixel-packing: Specifies if pixel packing is used (in case of RGB666).
- 0 = Tight packing (default value).
- 1 = Loose packing.
+ "tight" = Tight packing (default value).
+ "loose" = Loose packing.
- qcom,mdss-dsi-virtual-channel-id: Specifies the virtual channel identefier.
0 = default value.
- qcom,mdss-dsi-color-order: Specifies the R, G and B channel ordering.
- 0 = DSI_RGB_SWAP_RGB (default value)
- 1 = DSI_RGB_SWAP_RBG
- 2 = DSI_RGB_SWAP_BGR
- 3 = DSI_RGB_SWAP_BRG
- 4 = DSI_RGB_SWAP_GRB
- 5 = DSI_RGB_SWAP_GBR
+ "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value)
+ "rgb_swap_rbg" = DSI_RGB_SWAP_RBG
+ "rgb_swap_brg" = DSI_RGB_SWAP_BRG
+ "rgb_swap_grb" = DSI_RGB_SWAP_GRB
+ "rgb_swap_gbr" = DSI_RGB_SWAP_GBR
- qcom,mdss-dsi-lane-0-state: Boolean that specifies whether data lane 0 is enabled.
- qcom,mdss-dsi-lane-1-state: Boolean that specifies whether data lane 1 is enabled.
- qcom,mdss-dsi-lane-2-state: Boolean that specifies whether data lane 2 is enabled.
- qcom,mdss-dsi-lane-3-state: Boolean that specifies whether data lane 3 is enabled.
- qcom,mdss-dsi-lane-map: Specifies the data lane swap configuration.
- 0 = <0 1 2 3> (default value)
- 1 = <3 0 1 2>
- 2 = <2 3 0 1>
- 3 = <1 2 3 0>
- 4 = <0 3 2 1>
- 5 = <1 0 3 2>
- 6 = <2 1 0 3>
- 7 = <3 2 1 0>
+ "lane_map_0123" = <0 1 2 3> (default value)
+ "lane_map_3012" = <3 0 1 2>
+ "lane_map_2301" = <2 3 0 1>
+ "lane_map_1230" = <1 2 3 0>
+ "lane_map_0321" = <0 3 2 1>
+ "lane_map_1032" = <1 0 3 2>
+ "lane_map_2103" = <2 1 0 3>
+ "lane_map_3210" = <3 2 1 0>
- qcom,mdss-dsi-t-clk-post: Specifies the byte clock cycles after mode switch.
0x03 = default value.
- qcom,mdss-dsi-t-clk-pre: Specifies the byte clock cycles before mode switch.
@@ -214,16 +213,16 @@
0 = stream 0 (default)
1 = stream 1
- qcom,mdss-dsi-mdp-trigger: Specifies the trigger mechanism to be used for MDP path.
- 0 = no trigger
- 2 = Tear check signal line used for trigger
- 4 = Triggered by software (default)
- 6 = Software trigger and TE
+ "none" = no trigger
+ "trigger_te" = Tear check signal line used for trigger
+ "trigger_sw" = Triggered by software (default)
+ "trigger_sw_te" = Software trigger and TE
- qcom,mdss-dsi-dma-trigger: Specifies the trigger mechanism to be used for DMA path.
- 0 = no trigger
- 2 = Tear check signal line used for trigger
- 4 = Triggered by software (default)
- 5 = Software trigger and start/end of frame trigger.
- 6 = Software trigger and TE
+ "none" = no trigger
+ "trigger_te" = Tear check signal line used for trigger
+ "trigger_sw" = Triggered by software (default)
+ "trigger_sw_seof" = Software trigger and start/end of frame trigger.
+ "trigger_sw_te" = Software trigger and TE
- qcom,mdss-dsi-panel-framerate: Specifies the frame rate for the panel.
60 = 60 frames per second (default)
- qcom,mdss-dsi-panel-clockrate: Specifies the panel clock speed in Hz.
diff --git a/Documentation/devicetree/bindings/fb/mdss-edp.txt b/Documentation/devicetree/bindings/fb/mdss-edp.txt
index e564cd5..2070c64 100644
--- a/Documentation/devicetree/bindings/fb/mdss-edp.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-edp.txt
@@ -23,6 +23,10 @@
interface is mapped.
- gpio-panel-hpd : gpio pin use for edp hpd
+
+Optional properties:
+- qcom,cont-splash-enabled: Boolean used to enable continuous splash mode.
+
Example:
mdss_edp: qcom,mdss_edp@fd923400 {
compatible = "qcom,mdss-edp";
diff --git a/Documentation/devicetree/bindings/fb/mdss-mdp.txt b/Documentation/devicetree/bindings/fb/mdss-mdp.txt
index a4e61e8..9530c62 100644
--- a/Documentation/devicetree/bindings/fb/mdss-mdp.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-mdp.txt
@@ -146,7 +146,18 @@
total numbers of MMBs per pipe while values, if
any, following first one denotes indexes of MMBs
to that RGB pipe.
-
+- qcom,max-bandwidth-low-kbps: This value indicates the max bandwidth in KB
+ that can be supported without underflow.
+ This is a low bandwidth threshold which should
+ be applied in most scenarios to be safe from
+ underflows when unable to satisfy bandwith
+ requirements.
+- qcom,max-bandwidth-high-kbps: This value indicates the max bandwidth in KB
+ that can be supported without underflow.
+ This is a high bandwidth threshold which can be
+ applied in scenarios where panel interface can
+ be more tolerant to memory latency such as
+ command mode panels.
Optional subnodes:
Child nodes representing the frame buffer virtual devices.
@@ -186,6 +197,10 @@
vdd-supply = <&gdsc_mdss>;
vdd-cx-supply = <&pm8841_s2_corner>;
batfet-supply = <&pm8941_chg_batif>;
+
+ qcom,max-bandwidth-low-kbps = <2300000>;
+ qcom,max-bandwidth-high-kbps = <3000000>;
+
qcom,max-clk-rate = <320000000>;
qcom,vbif-settings = <0x0004 0x00000001>,
<0x00D8 0x00000707>;
diff --git a/Documentation/devicetree/bindings/gpu/adreno.txt b/Documentation/devicetree/bindings/gpu/adreno.txt
index aa0aa8c..656f3a4 100644
--- a/Documentation/devicetree/bindings/gpu/adreno.txt
+++ b/Documentation/devicetree/bindings/gpu/adreno.txt
@@ -64,7 +64,7 @@
Optional Properties:
- qcom,initial-powerlevel: This value indicates which qcom,gpu-pwrlevel should be used at start time
and when coming back out of resume
-- qcom,step-pwrlevel: How many qcom,gpu-pwrlevel should be decremented at once
+- qcom,bus-control: Boolean. Enables an independent bus vote from the gpu frequency
- qcom,idle-timeout: This property represents the time in microseconds for idle timeout.
- qcom,chipid: If it exists this property is used to replace
the chip identification read from the GPU hardware.
diff --git a/Documentation/devicetree/bindings/nfc/nfc-nci.txt b/Documentation/devicetree/bindings/nfc/nfc-nci.txt
index 5c53470..dca7d5c 100644
--- a/Documentation/devicetree/bindings/nfc/nfc-nci.txt
+++ b/Documentation/devicetree/bindings/nfc/nfc-nci.txt
@@ -8,7 +8,7 @@
- reg: NCI i2c slave address.
- qcom,dis-gpio: specific gpio for hardware reset.
- qcom,irq-gpio: specific gpio for read interrupt.
-- qcom,clk-src: nfc clock source ("BBCLK2", "RFCLK3", "GPCLK", ...)
+- qcom,clk-src: nfc clock source ("BBCLK2", "RFCLK3", "GPCLK","GPCLK2" ...)
- qcom,clk-en-gpio: msm gpio clock,used ony if clock source is msm gpio
- vlogic-supply: LDO for power supply
- interrupt-parent: Should be phandle for the interrupt controller
diff --git a/Documentation/devicetree/bindings/power/qpnp-charger.txt b/Documentation/devicetree/bindings/power/qpnp-charger.txt
index 584a76d..7d8fe0a 100644
--- a/Documentation/devicetree/bindings/power/qpnp-charger.txt
+++ b/Documentation/devicetree/bindings/power/qpnp-charger.txt
@@ -93,10 +93,16 @@
set, the charger ovp status is monitored in software.
- qcom,ext-ovp-present Indicates if an external OVP exists which reduces the
overall input resistance of the charge path.
+- qcom,ibat-calibration-enabled Indicates if ibat calibration is enabled. This is
+ required for devices which have a ibat trim error
+ causing ibatmax to go out of spec.
- qcom,power-stage-reduced Indicates if power stage workaround is enabled. This work
around reduces the power stage segments while charging
under high load during low battery voltages. It's for
improving IADC accuracy while board has a bad layout.
+- qcom,use-external-rsense A boolean that controls whether BMS will use
+ an external sensor resistor instead of the default
+ RDS of the batfet.
Sub node required structure:
- A qcom,chg node must be a child of an SPMI node that has specified
diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
index 56bdc59..a77b5ff 100644
--- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
+++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
@@ -102,6 +102,12 @@
- compatible : "qcom,msm-lsm-client"
+* msm-pcm-loopback
+
+Required properties:
+
+ - compatible : "qti,msm-pcm-loopback"
+
* msm-dai-q6
[First Level Nodes]
diff --git a/Documentation/devicetree/bindings/usb/msm-hsusb.txt b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
index 714311e..623a23c 100644
--- a/Documentation/devicetree/bindings/usb/msm-hsusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-hsusb.txt
@@ -91,6 +91,8 @@
runs using PNOC clock and synchronous to it. Hence it is must to have proper
"qcom,msm_bus,vectors" to have high bus frequency. User shouldn't try to
enable this feature without proper bus voting.
+-qcom,disable-retention-with-vdd-min: If present dont allow phy retention but allow
+ vdd min.
Example HSUSB OTG controller device node :
usb@f9690000 {
@@ -115,6 +117,7 @@
HSUSB_3p3-supply = <&pm8226_l20>;
qcom,vdd-voltage-level = <1 5 7>;
qcom,dp-manual-pullup;
+ qcom,disable-retention-with-vdd-min;
qcom,hsusb-otg-dpsehv-int = <49>;
qcom,hsusb-otg-dmsehv-int = <58>;
qcom,msm_bus,name = "usb2";
diff --git a/Documentation/sysctl/vm.txt b/Documentation/sysctl/vm.txt
index 96f0ee8..9c11d97 100644
--- a/Documentation/sysctl/vm.txt
+++ b/Documentation/sysctl/vm.txt
@@ -28,6 +28,7 @@
- dirty_writeback_centisecs
- drop_caches
- extfrag_threshold
+- extra_free_kbytes
- hugepages_treat_as_movable
- hugetlb_shm_group
- laptop_mode
@@ -168,6 +169,21 @@
==============================================================
+extra_free_kbytes
+
+This parameter tells the VM to keep extra free memory between the threshold
+where background reclaim (kswapd) kicks in, and the threshold where direct
+reclaim (by allocating processes) kicks in.
+
+This is useful for workloads that require low latency memory allocations
+and have a bounded burstiness in memory allocations, for example a
+realtime application that receives and transmits network traffic
+(causing in-kernel memory allocations) with a maximum total message burst
+size of 200MB may need 200MB of extra free memory to avoid direct reclaim
+related latencies.
+
+==============================================================
+
hugepages_treat_as_movable
This parameter is only useful when kernelcore= is specified at boot time to
diff --git a/arch/arm/boot/dts/apq8074-dragonboard.dtsi b/arch/arm/boot/dts/apq8074-dragonboard.dtsi
index 824b0ab..c7e24d9 100644
--- a/arch/arm/boot/dts/apq8074-dragonboard.dtsi
+++ b/arch/arm/boot/dts/apq8074-dragonboard.dtsi
@@ -13,6 +13,7 @@
/include/ "dsi-panel-sharp-qhd-video.dtsi"
/include/ "msm8974-camera-sensor-dragonboard.dtsi"
/include/ "msm8974-leds.dtsi"
+/include/ "msm-rdbg.dtsi"
&vph_pwr_vreg {
status = "ok";
diff --git a/arch/arm/boot/dts/apq8084-mdss.dtsi b/arch/arm/boot/dts/apq8084-mdss.dtsi
index 5c5cd1b..15d5018 100644
--- a/arch/arm/boot/dts/apq8084-mdss.dtsi
+++ b/arch/arm/boot/dts/apq8084-mdss.dtsi
@@ -21,6 +21,9 @@
status = "disabled";
+ qcom,max-bandwidth-low-kbps = <6000000>;
+ qcom,max-bandwidth-high-kbps = <6000000>;
+
qcom,max-clk-rate = <320000000>;
qcom,mdss-pipe-vig-off = <0x00001200 0x00001600
diff --git a/arch/arm/boot/dts/batterydata-qrd-4v2-2200mah.dtsi b/arch/arm/boot/dts/batterydata-qrd-4v2-2200mah.dtsi
new file mode 100644
index 0000000..53aa781
--- /dev/null
+++ b/arch/arm/boot/dts/batterydata-qrd-4v2-2200mah.dtsi
@@ -0,0 +1,105 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+qcom,qrd-4v2-2200mah-data {
+ qcom,default-rbatt-mohm = <163>;
+ qcom,max-voltage-uv = <4200>;
+ qcom,fcc-mah = <2200>;
+ qcom,rbatt-capacitive-mohm = <0>;
+ qcom,v-cutoff-uv = <3400000>;
+ qcom,chg-term-ua = <100000>;
+ qcom,batt-id-kohm = <10>;
+ qcom,flat-ocv-threshold-uv = <3800000>;
+
+ qcom,fcc-temp-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-data = <2167 2179 2234 2178 2164>;
+ };
+
+ qcom,pc-temp-ocv-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-row-legend = <100 95 90 85 80>,
+ <75 70 65 60 55>,
+ <50 45 40 35 30>,
+ <25 20 15 10 9>,
+ <8 7 6 5 4>,
+ <3 2 1 0>;
+ qcom,lut-data = <4188 4184 4199 4176 4170>,
+ <4109 4124 4145 4124 4118>,
+ <4051 4082 4097 4077 4072>,
+ <3963 4024 4055 4034 4029>,
+ <3920 3971 4002 3993 3989>,
+ <3880 3932 3963 3957 3952>,
+ <3846 3892 3920 3913 3910>,
+ <3822 3859 3881 3873 3871>,
+ <3805 3834 3851 3845 3844>,
+ <3790 3813 3828 3823 3822>,
+ <3777 3796 3808 3805 3803>,
+ <3764 3784 3792 3790 3788>,
+ <3750 3775 3778 3777 3774>,
+ <3736 3766 3766 3761 3751>,
+ <3721 3752 3755 3745 3732>,
+ <3704 3733 3737 3729 3716>,
+ <3684 3707 3713 3707 3694>,
+ <3655 3686 3688 3682 3672>,
+ <3598 3661 3677 3671 3659>,
+ <3585 3655 3673 3669 3656>,
+ <3571 3644 3664 3663 3650>,
+ <3551 3626 3643 3648 3631>,
+ <3523 3598 3609 3618 3600>,
+ <3489 3561 3565 3578 3561>,
+ <3445 3514 3510 3529 3512>,
+ <3389 3453 3440 3468 3450>,
+ <3313 3372 3345 3386 3366>,
+ <3207 3252 3209 3262 3239>,
+ <3000 3000 3000 3000 3000>;
+ };
+
+ qcom,rbatt-sf-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-row-legend = <100 95 90 85 80>,
+ <75 70 65 60 55>,
+ <50 45 40 35 30>,
+ <25 20 15 10 9>,
+ <8 7 6 5 4>,
+ <3 2 1 0>;
+ qcom,lut-data = <1371 224 100 79 74>,
+ <1358 242 100 80 74>,
+ <1358 242 103 80 74>,
+ <1195 257 107 82 75>,
+ <1171 256 112 84 77>,
+ <1149 250 119 89 79>,
+ <1144 232 114 90 79>,
+ <1150 225 101 83 76>,
+ <1175 227 98 81 76>,
+ <1210 232 98 82 76>,
+ <1260 236 98 82 77>,
+ <1329 242 100 84 77>,
+ <1421 251 100 86 79>,
+ <1536 263 101 81 76>,
+ <1671 280 100 80 74>,
+ <1830 304 100 81 75>,
+ <2036 338 101 82 76>,
+ <2326 443 103 82 76>,
+ <2788 708 112 88 79>,
+ <2890 747 115 90 80>,
+ <2755 676 117 89 79>,
+ <2750 716 118 87 78>,
+ <2916 765 119 87 79>,
+ <3336 833 123 89 80>,
+ <4214 920 133 92 81>,
+ <5615 1031 151 96 83>,
+ <7923 1188 192 104 89>,
+ <13252 1886 585 137 122>,
+ <43764 20050 47711 3680 16847>;
+ };
+};
diff --git a/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi b/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi
index 2963d15..17e6e94 100644
--- a/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-generic-720p-cmd.dtsi
@@ -37,7 +37,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [05 01 00 00 78 00 01 11
@@ -52,8 +51,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
- qcom,mdss-dsi-traffic-mode = <1>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -73,8 +71,8 @@
qcom,mdss-dsi-bl-max-level = <255>;
qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
qcom,mdss-dsi-bl-pmic-bank-select = <7>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
diff --git a/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi b/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi
index 92e6fc1..88ccd08 100644
--- a/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-hx8379a-wvga-video.dtsi
@@ -38,7 +38,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [
@@ -137,8 +136,8 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <1>;
- qcom,mdss-dsi-traffic-mode = <2>;
- qcom,mdss-dsi-lane-map = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-lane-map = "lane_map_3012";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -148,8 +147,8 @@
qcom,mdss-dsi-t-clk-pre = <0x1b>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <255>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
diff --git a/arch/arm/boot/dts/dsi-panel-hx8389b-qhd-video.dtsi b/arch/arm/boot/dts/dsi-panel-hx8389b-qhd-video.dtsi
index 8f94502..25e5072 100755
--- a/arch/arm/boot/dts/dsi-panel-hx8389b-qhd-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-hx8389b-qhd-video.dtsi
@@ -17,7 +17,7 @@
*---------------------------------------------------------------------------*/
&mdss_mdp {
dsi_hx8389b_qhd_vid: qcom,mdss_dsi_hx8389b_qhd_video {
- qcom,mdss-dsi-panel-name = "HX8389b qhd video mode dsi panel";
+ qcom,mdss-dsi-panel-name = "hx8389b qhd video mode dsi panel";
qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
qcom,mdss-dsi-panel-type = "dsi_video_mode";
qcom,mdss-dsi-panel-destination = "display_1";
@@ -26,13 +26,13 @@
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-panel-width = <540>;
qcom,mdss-dsi-panel-height = <960>;
- qcom,mdss-dsi-h-front-porch = <48>;
- qcom,mdss-dsi-h-back-porch = <96>;
- qcom,mdss-dsi-h-pulse-width = <96>;
+ qcom,mdss-dsi-h-front-porch = <60>;
+ qcom,mdss-dsi-h-back-porch = <39>;
+ qcom,mdss-dsi-h-pulse-width = <39>;
qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <13>;
qcom,mdss-dsi-v-front-porch = <9>;
qcom,mdss-dsi-v-pulse-width = <3>;
- qcom,mdss-dsi-v-back-porch = <13>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
@@ -41,95 +41,39 @@
qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
- qcom,mdss-dsi-on-command = [
- 39 01 00 00 00 00 04
- B9 FF 83 89
- 39 01 00 00 00 00 08
- BA 41 93 00
- 16 A4 10 18
- 23 01 00 00 00 00 02
- C6 08
- 39 01 00 00 00 00 03
- BC 02 00
- 23 01 00 00 00 00 02
- CC 02
- 39 01 00 00 00 00 14
- B1 00 00 07
- E8 50 10 11
- 98 f8 21 29
- 27 27 43 01
- 58 F0 00 E6
- 39 01 00 00 00 00 08
- B2 00 00 78
- 0C 07 3F 80
- 39 01 00 00 00 00 18
- b4 82 08 00
- 32 10 04 32
- 10 00 32 10
- 00 37 0a 40
- 08 37 0a 40
- 14 46 50 0a
- 39 01 00 00 00 00 39
- d5 00 00 00
- 00 01 00 00
- 00 60 00 99
- 88 AA BB 88
- 23 88 01 88
- 67 88 45 01
- 23 88 88 88
- 88 88 88 99
- BB AA 88 54
- 88 76 88 10
- 88 32 32 10
- 88 88 88 88
- 88 00 04 00
- 00 00 00 00
- 00
- 39 01 00 00 00 00 03
- CB 07 07
- 39 01 00 00 00 00 05
- BB 00 00 FF
- 80
- 39 01 00 00 00 00 04
- DE 05 58 10
- 39 01 00 00 00 00 05
- B6 00 8A 00
- 8A
- 39 01 00 00 00 00 23
- E0 01 08 0C
- 1F 25 36 12
- 35 05 09 0D
- 10 11 0F 0F
- 1C 1D 01 08
- 0C 1F 25 36
- 12 35 05 09
- 0D 10 11 0F
- 0F 1C 1D
- 05 01 00 00 96 00 02
- 11 00
- 05 01 00 00 96 00 02
- 29 00
- ];
+ qcom,mdss-dsi-on-command = [39 01 00 00 0A 00 04 B9 FF 83 89
+ 15 01 00 00 01 00 02 CC 02
+ 39 01 00 00 01 00 03 C0 43 17
+ 39 01 00 00 01 00 08 BA 41 93 00 16 A4 10 18
+ 39 01 00 00 01 00 14 B1 00 00 06 EB 59 10 11 EE EE 3A 42 3F 3F 43 01 5A F6 00 E6
+ 39 01 00 00 01 00 08 B2 00 00 78 0C 07 3F 80
+ 39 01 00 00 01 00 04 b7 00 00 50
+ 39 01 00 00 01 00 18 B4 80 08 00 32 10 04 32 10 00 32 10 00 37 0a 40 08 37 00 46 02 58 58 02
+ 39 01 00 00 01 00 39 D5 00 00 00 00 01 00 00 00 60 00 99 88 AA BB 88 23 88 01 88 67 88 45 01 23 88 88 88 88 88 88 99 BB AA 88 54 88 76 88 10 88 32 32 10 88 88 88 88 88 3C 04 00 00 00 00 00 00
+ 39 01 00 00 01 00 23 E0 05 11 16 35 3F 3F 21 43 07 0C 0F 11 12 10 10 1D 18 05 11 16 35 3F 3F 21 43 07 0C 0F 11 12 10 10 1D 18
+ 39 01 00 00 05 00 80 C1 01 00 07 13 21 29 2F 34 3B 42 48 50 58 61 69 71 79 81 88 90 98 A0 A9 B1 B9 C1 C8 CE D6 DF E6 EF F7 FF 0E 5A 73 69 36 8E 69 5F C0 00 07 13 21 29 2F 34 3B 42 48 50 58 61 69 71 79 81 88 90 98 A0 A9 B1 B9 C1 C8 CE D6 DF E6 EF F7 FF 0E 5A 73 69 36 8E 69 5F C0 00 07 13 21 29 2F 34 3B 42 48 50 58 61 69 71 79 81 88 90 98 A0 A9 B1 B9 C1 C8 CE D6 DF E6 EF F7 FF 0E 5A 73 69 36 8E 69 5F C0
+ 39 01 00 00 01 00 05 B6 00 88 00 88
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00
05 01 00 00 78 00 02 10 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <1>;
- qcom,mdss-dsi-traffic-mode = <2>;
- qcom,mdss-dsi-lane-map = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-lane-map = "lane_map_3012";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
qcom,mdss-dsi-lane-1-state;
- qcom,mdss-dsi-panel-timings = [97 23 17 00 4B 53 1C 27 27 03 04 00];
+ qcom,mdss-dsi-panel-timings = [87 1E 14 00 44 4B 19 21 22 03 04 00];
qcom,mdss-dsi-t-clk-post = <0x04>;
qcom,mdss-dsi-t-clk-pre = <0x1b>;
qcom,mdss-dsi-bl-min-level = <26>;
qcom,mdss-dsi-bl-max-level = <255>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
-
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi
index 83351ca..5302d8ae 100644
--- a/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-hx8394a-720p-video.dtsi
@@ -38,7 +38,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 b9 ff 83 94
@@ -62,8 +61,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <1>;
- qcom,mdss-dsi-traffic-mode = <2>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -75,8 +73,8 @@
qcom,mdss-dsi-t-clk-pre = <0x2d>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
diff --git a/arch/arm/boot/dts/dsi-panel-jdi-1080p-video.dtsi b/arch/arm/boot/dts/dsi-panel-jdi-1080p-video.dtsi
index 1b64cf7..be42509 100644
--- a/arch/arm/boot/dts/dsi-panel-jdi-1080p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-jdi-1080p-video.dtsi
@@ -38,7 +38,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 55 00
@@ -51,8 +50,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
- qcom,mdss-dsi-traffic-mode = <2>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -64,8 +62,8 @@
qcom,mdss-dsi-t-clk-pre = <0x1b>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
- qcom,mdss-dsi-dma-trigger = <0x04>;
- qcom,mdss-dsi-mdp-trigger = <0x0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
};
diff --git a/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi
index 9bb11da..8be4e34 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35521-720p-video.dtsi
@@ -38,10 +38,9 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
- qcom,mdss-dsi-pixel-packing = <0>;
+ qcom,mdss-dsi-pixel-packing = "tight";
qcom,mdss-dsi-on-command = [29 01 00 00 00 00 06 F0 55 AA 52 08 00
29 01 00 00 00 00 03 B1 68 21
23 01 00 00 00 00 02 B5 C8
@@ -252,8 +251,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <1>;
- qcom,mdss-dsi-traffic-mode = <2>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -265,8 +263,8 @@
qcom,mdss-dsi-t-clk-pre = <0x2D>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <255>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
diff --git a/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi b/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi
index a24cb58..d3547d8 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35590-720p-cmd.dtsi
@@ -38,7 +38,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 FF EE
@@ -510,8 +509,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <1>;
- qcom,mdss-dsi-traffic-mode = <2>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -528,8 +526,8 @@
qcom,mdss-dsi-t-clk-pre = <0x2c>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
qcom,mdss-pan-physical-width-dimension = <59>;
diff --git a/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi
index 79618b9..8d28996 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35590-720p-video.dtsi
@@ -38,7 +38,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 FF EE
@@ -511,8 +510,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <1>;
- qcom,mdss-dsi-traffic-mode = <2>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -524,8 +522,8 @@
qcom,mdss-dsi-t-clk-pre = <0x2c>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
qcom,mdss-pan-physical-width-dimension = <59>;
diff --git a/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi b/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi
index 2312b37..770bac4 100644
--- a/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-nt35596-1080p-video.dtsi
@@ -38,7 +38,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 FF EE
@@ -566,8 +565,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <1>;
- qcom,mdss-dsi-traffic-mode = <2>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -579,8 +577,8 @@
qcom,mdss-dsi-t-clk-pre = <0x38>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
diff --git a/arch/arm/boot/dts/dsi-panel-orise-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-orise-720p-video.dtsi
index 30eda91..5393756 100644
--- a/arch/arm/boot/dts/dsi-panel-orise-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-orise-720p-video.dtsi
@@ -34,7 +34,7 @@
qcom,mdss-pan-dsi-stream = <0>;
qcom,mdss-pan-dsi-mdp-tr = <0x0>;
qcom,mdss-pan-dsi-dma-tr = <0x04>;
- qcom,mdss-pan-dsi-frame-rate = <60>;
+ qcom,mdss-pan-dsi-framerate = <60>;
qcom,panel-phy-regulatorSettings = [03 01 01 00 /* Regualotor settings */
20 00 01];
qcom,panel-phy-timingSettings = [69 29 1f 00 55 55
diff --git a/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi b/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi
index 393419b..8d6e703 100644
--- a/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-otm8018b-fwvga-video.dtsi
@@ -38,7 +38,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [
@@ -247,8 +246,8 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
- qcom,mdss-dsi-traffic-mode = <1>;
- qcom,mdss-dsi-lane-map = <1>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_3012";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -258,8 +257,8 @@
qcom,mdss-dsi-t-clk-pre = <0x1b>;
qcom,mdss-dsi-bl-min-level = <26>;
qcom,mdss-dsi-bl-max-level = <255>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
diff --git a/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi b/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi
index 285d8fc..d23e3de 100644
--- a/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-sharp-qhd-video.dtsi
@@ -38,7 +38,7 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <2>;
+ qcom,mdss-dsi-color-order = "rgb_swap_bgr";
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [05 01 00 00 32 00 02 01 00
@@ -53,8 +53,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <1>;
- qcom,mdss-dsi-traffic-mode = <0>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -64,8 +63,8 @@
qcom,mdss-dsi-t-clk-pre = <0x1c>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <4>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "trigger_sw";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
diff --git a/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi
index b510e6b..60bba5d 100644
--- a/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-ssd2080m-720p-video.dtsi
@@ -31,16 +31,17 @@
qcom,mdss-dsi-h-pulse-width = <14>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <14>;
- qcom,mdss-dsi-v-front-porch = <11>;
+ qcom,mdss-dsi-v-front-porch = <30>;
qcom,mdss-dsi-v-pulse-width = <2>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-pixel-packing = "tight";
qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 FF 01
29 01 00 00 00 00 05 C6 63 00 81 31
29 01 00 00 00 00 05 CB E7 80 73 33
@@ -81,40 +82,38 @@
29 01 00 00 00 00 05 F6 00 00 00 00
29 01 00 00 00 00 05 F7 00 00 00 00
29 01 00 00 00 00 03 E1 90 00
- 29 01 00 00 00 00 03 DE 95 CF
+ 29 01 00 00 00 00 07 DE 95 CF E2 CE 11 15
29 01 00 00 00 00 02 CF 46
29 01 00 00 00 00 03 C5 77 47
29 01 00 00 00 00 03 ED 00 20
05 01 00 00 B4 00 02 11 00
05 01 00 00 82 00 02 29 00
15 01 00 00 00 00 02 53 2c];
-
- qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 10 00
- 05 01 00 00 32 00 02 53 00
- 05 01 00 00 00 00 02 c2 00
+ qcom,mdss-dsi-off-command = [15 01 00 00 32 00 02 10 00
+ 15 01 00 00 32 00 02 53 00
+ 15 01 00 00 00 00 02 c2 00
39 01 00 00 00 00 02 cf 40
- 05 01 00 00 50 00 03 de 84 00
+ 15 01 00 00 50 00 03 de 84 00
39 01 00 00 00 00 02 cb 22
- 05 01 00 00 00 00 02 c3 00];
-
+ 15 01 00 00 00 00 02 c3 00];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <1>;
- qcom,mdss-dsi-traffic-mode = <2>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-lane-0-state;
qcom,mdss-dsi-lane-1-state;
qcom,mdss-dsi-lane-2-state;
qcom,mdss-dsi-lane-3-state;
- qcom,mdss-dsi-panel-timings = [a8 1f 17 00 2f 2d 1c 21 29 03 04 00];
+ qcom,mdss-dsi-panel-timings = [68 1d 15 00 2e 2d 19 1f 24 03 04 00];
qcom,mdss-dsi-t-clk-post = <0x20>;
qcom,mdss-dsi-t-clk-pre = <0x2f>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
- qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
};
diff --git a/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi b/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi
index f7de416..10f53b9 100644
--- a/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-toshiba-720p-video.dtsi
@@ -38,7 +38,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [23 01 00 00 0a 00 02 b0 00
@@ -74,8 +73,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
- qcom,mdss-dsi-traffic-mode = <1>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -87,8 +85,8 @@
qcom,mdss-dsi-t-clk-pre = <0x1b>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
- qcom,mdss-dsi-dma-trigger = <0x04>;
- qcom,mdss-dsi-mdp-trigger = <0x0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-pan-enable-dynamic-fps;
qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode";
diff --git a/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi b/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi
index d170833..168dda4 100644
--- a/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-truly-wvga-cmd.dtsi
@@ -39,7 +39,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [
@@ -146,8 +145,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
- qcom,mdss-dsi-traffic-mode = <1>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -163,8 +161,8 @@
qcom,mdss-dsi-t-clk-pre = <0x1b>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <255>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <2>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "trigger_te";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
diff --git a/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi b/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi
index 546a90f..121e54d 100644
--- a/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi
+++ b/arch/arm/boot/dts/dsi-panel-truly-wvga-video.dtsi
@@ -39,7 +39,6 @@
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
- qcom,mdss-dsi-color-order = <0>;
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-on-command = [
@@ -150,8 +149,7 @@
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
qcom,mdss-dsi-h-sync-pulse = <0>;
- qcom,mdss-dsi-traffic-mode = <1>;
- qcom,mdss-dsi-lane-map = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
@@ -161,8 +159,8 @@
qcom,mdss-dsi-t-clk-pre = <0x1b>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <255>;
- qcom,mdss-dsi-dma-trigger = <4>;
- qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
};
diff --git a/arch/arm/boot/dts/msm-pm8110.dtsi b/arch/arm/boot/dts/msm-pm8110.dtsi
index 2ccb1fb..20e8a96 100644
--- a/arch/arm/boot/dts/msm-pm8110.dtsi
+++ b/arch/arm/boot/dts/msm-pm8110.dtsi
@@ -328,7 +328,7 @@
qcom,low-voltage-threshold = <3420000>;
qcom,tm-temp-margin = <5000>;
qcom,low-ocv-correction-limit-uv = <100>;
- qcom,high-ocv-correction-limit-uv = <50>;
+ qcom,high-ocv-correction-limit-uv = <250>;
qcom,hold-soc-est = <3>;
qcom,bms-vadc = <&pm8110_vadc>;
qcom,bms-iadc = <&pm8110_iadc>;
diff --git a/arch/arm/boot/dts/msm-pm8226.dtsi b/arch/arm/boot/dts/msm-pm8226.dtsi
index b9bcd0c..6d506cc 100644
--- a/arch/arm/boot/dts/msm-pm8226.dtsi
+++ b/arch/arm/boot/dts/msm-pm8226.dtsi
@@ -206,7 +206,7 @@
qcom,batt-type = <0>;
qcom,tm-temp-margin = <5000>;
qcom,low-ocv-correction-limit-uv = <100>;
- qcom,high-ocv-correction-limit-uv = <50>;
+ qcom,high-ocv-correction-limit-uv = <250>;
qcom,hold-soc-est = <3>;
qcom,low-voltage-threshold = <3420000>;
qcom,bms-vadc = <&pm8226_vadc>;
diff --git a/arch/arm/boot/dts/msm-pm8941.dtsi b/arch/arm/boot/dts/msm-pm8941.dtsi
index b540063..520decd 100644
--- a/arch/arm/boot/dts/msm-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm-pm8941.dtsi
@@ -135,7 +135,7 @@
qcom,low-voltage-threshold = <3420000>;
qcom,tm-temp-margin = <5000>;
qcom,low-ocv-correction-limit-uv = <100>;
- qcom,high-ocv-correction-limit-uv = <50>;
+ qcom,high-ocv-correction-limit-uv = <250>;
qcom,hold-soc-est = <3>;
qcom,bms-vadc = <&pm8941_vadc>;
qcom,bms-iadc = <&pm8941_iadc>;
@@ -209,7 +209,9 @@
qcom,resume-soc = <99>;
qcom,tchg-mins = <150>;
qcom,chg-vadc = <&pm8941_vadc>;
+ qcom,chg-iadc = <&pm8941_iadc>;
qcom,chg-adc_tm = <&pm8941_adc_tm>;
+ qcom,ibat-calibration-enabled;
qcom,chgr@1000 {
status = "disabled";
diff --git a/arch/arm/boot/dts/msm-rdbg.dtsi b/arch/arm/boot/dts/msm-rdbg.dtsi
new file mode 100644
index 0000000..f7f52be
--- /dev/null
+++ b/arch/arm/boot/dts/msm-rdbg.dtsi
@@ -0,0 +1,75 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+ smp2pgpio_rdbg_2_in: qcom,smp2pgpio-rdbg-2-in {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "rdbg";
+ qcom,remote-pid = <2>;
+ qcom,is-inbound;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_client_rdbg_2_in {
+ compatible = "qcom,smp2pgpio_client_rdbg_2_in";
+ gpios = <&smp2pgpio_rdbg_2_in 0 0>;
+ };
+
+ smp2pgpio_rdbg_2_out: qcom,smp2pgpio-rdbg-2-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "rdbg";
+ qcom,remote-pid = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_client_rdbg_2_out {
+ compatible = "qcom,smp2pgpio_client_rdbg_2_out";
+ gpios = <&smp2pgpio_rdbg_2_out 0 0>;
+ };
+
+ smp2pgpio_rdbg_1_in: qcom,smp2pgpio-rdbg-1-in {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "rdbg";
+ qcom,remote-pid = <1>;
+ qcom,is-inbound;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_client_rdbg_1_in {
+ compatible = "qcom,smp2pgpio_client_rdbg_1_in";
+ gpios = <&smp2pgpio_rdbg_1_in 0 0>;
+ };
+
+ smp2pgpio_rdbg_1_out: qcom,smp2pgpio-rdbg-1-out {
+ compatible = "qcom,smp2pgpio";
+ qcom,entry-name = "rdbg";
+ qcom,remote-pid = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,smp2pgpio_client_rdbg_1_out {
+ compatible = "qcom,smp2pgpio_client_rdbg_1_out";
+ gpios = <&smp2pgpio_rdbg_1_out 0 0>;
+ };
+};
diff --git a/arch/arm/boot/dts/msm8226-720p-cdp.dtsi b/arch/arm/boot/dts/msm8226-720p-cdp.dtsi
index 3ebe225..9a1eb36 100644
--- a/arch/arm/boot/dts/msm8226-720p-cdp.dtsi
+++ b/arch/arm/boot/dts/msm8226-720p-cdp.dtsi
@@ -28,6 +28,7 @@
synaptics,reset-gpio = <&msmgpio 16 0x00>;
synaptics,irq-gpio = <&msmgpio 17 0x2008>;
synaptics,button-map = <139 102 158>;
+ synaptics,fw-image-name = "PR1468813.img";
synaptics,i2c-pull-up;
synaptics,power-down;
synaptics,disable-gpios;
diff --git a/arch/arm/boot/dts/msm8226-720p-mtp.dtsi b/arch/arm/boot/dts/msm8226-720p-mtp.dtsi
index a4bd8fd..7f4f8fc 100644
--- a/arch/arm/boot/dts/msm8226-720p-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8226-720p-mtp.dtsi
@@ -28,6 +28,7 @@
synaptics,reset-gpio = <&msmgpio 16 0x00>;
synaptics,irq-gpio = <&msmgpio 17 0x2008>;
synaptics,button-map = <139 102 158>;
+ synaptics,fw-image-name = "PR1468813.img";
synaptics,i2c-pull-up;
synaptics,power-down;
synaptics,disable-gpios;
diff --git a/arch/arm/boot/dts/msm8226-camera.dtsi b/arch/arm/boot/dts/msm8226-camera.dtsi
index 4987dae..3e8444f 100644
--- a/arch/arm/boot/dts/msm8226-camera.dtsi
+++ b/arch/arm/boot/dts/msm8226-camera.dtsi
@@ -136,29 +136,29 @@
};
&master0 {
- qcom,hw-thigh = <78>;
- qcom,hw-tlow = <114>;
- qcom,hw-tsu-sto = <28>;
- qcom,hw-tsu-sta = <28>;
- qcom,hw-thd-dat = <10>;
- qcom,hw-thd-sta = <77>;
- qcom,hw-tbuf = <118>;
+ qcom,hw-thigh = <20>;
+ qcom,hw-tlow = <28>;
+ qcom,hw-tsu-sto = <21>;
+ qcom,hw-tsu-sta = <21>;
+ qcom,hw-thd-dat = <13>;
+ qcom,hw-thd-sta = <18>;
+ qcom,hw-tbuf = <25>;
qcom,hw-scl-stretch-en = <0>;
qcom,hw-trdhld = <6>;
- qcom,hw-tsp = <1>;
+ qcom,hw-tsp = <3>;
status = "ok";
};
&master1 {
- qcom,hw-thigh = <78>;
- qcom,hw-tlow = <114>;
- qcom,hw-tsu-sto = <28>;
- qcom,hw-tsu-sta = <28>;
- qcom,hw-thd-dat = <10>;
- qcom,hw-thd-sta = <77>;
- qcom,hw-tbuf = <118>;
+ qcom,hw-thigh = <20>;
+ qcom,hw-tlow = <28>;
+ qcom,hw-tsu-sto = <21>;
+ qcom,hw-tsu-sta = <21>;
+ qcom,hw-thd-dat = <13>;
+ qcom,hw-thd-sta = <18>;
+ qcom,hw-tbuf = <25>;
qcom,hw-scl-stretch-en = <0>;
qcom,hw-trdhld = <6>;
- qcom,hw-tsp = <1>;
+ qcom,hw-tsp = <3>;
status = "ok";
};
diff --git a/arch/arm/boot/dts/msm8226-ion.dtsi b/arch/arm/boot/dts/msm8226-ion.dtsi
index 06e2779..443334e 100644
--- a/arch/arm/boot/dts/msm8226-ion.dtsi
+++ b/arch/arm/boot/dts/msm8226-ion.dtsi
@@ -32,6 +32,7 @@
qcom,heap-align = <0x1000>;
linux,contiguous-region = <&secure_mem>;
qcom,ion-heap-type = "SECURE_DMA";
+ qcom,default-prefetch-size = <0x3c00000>;
};
qcom,ion-heap@22 { /* adsp heap */
diff --git a/arch/arm/boot/dts/msm8226-mdss.dtsi b/arch/arm/boot/dts/msm8226-mdss.dtsi
index e2891d1..38cfe66 100644
--- a/arch/arm/boot/dts/msm8226-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8226-mdss.dtsi
@@ -19,6 +19,8 @@
interrupts = <0 72 0>;
vdd-supply = <&gdsc_mdss>;
+ qcom,max-bandwidth-low-kbps = <1660000>;
+ qcom,max-bandwidth-high-kbps = <1660000>;
qcom,max-clk-rate = <200000000>;
qcom,mdss-pipe-vig-off = <0x00001200>;
qcom,mdss-pipe-rgb-off = <0x00001E00>;
diff --git a/arch/arm/boot/dts/msm8226-qrd-skuf.dtsi b/arch/arm/boot/dts/msm8226-qrd-skuf.dtsi
index 76bd262..2e32ac4 100755
--- a/arch/arm/boot/dts/msm8226-qrd-skuf.dtsi
+++ b/arch/arm/boot/dts/msm8226-qrd-skuf.dtsi
@@ -85,25 +85,25 @@
goodix,button-map= <158 102 139>;
goodix,product-id = "915";
goodix,cfg-data0 = [
- 41 D0 02 00 05 05 35 01 01 0F
- 2D 06 50 32 03 05 00 00 00 00
- 00 00 05 18 1A 1E 14 8C 0E 0E
- 3F 3D 2A 09 00 00 00 99 04 1D
- 00 00 00 00 00 00 00 00 00 00
- 00 32 6E 94 D5 01 05 00 00 04
- CE 36 00 B5 3F 00 9E 4A 00 8B
- 57 00 7C 65 00 7C 10 38 68 00
- 56 50 35 66 66 27 00 00 00 00
+ 41 D0 02 00 05 05 35 11 01 0F
+ 2D 06 50 32 03 02 00 00 00 00
+ 00 00 05 18 1A 1E 14 8C 2E 0E
+ 59 5B B2 04 00 00 00 99 03 11
+ 00 1C 00 00 00 00 00 00 00 00
+ 00 53 A6 94 C5 01 05 00 00 08
+ 7F 59 00 71 66 00 64 75 00 58
+ 87 00 4E 9B 00 4E 10 38 68 00
+ 56 45 30 66 66 27 00 00 00 00
00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00
00 00 02 04 06 08 0A 0C 0E 10
- 12 14 16 18 1A 1C 00 00 00 00
- 00 00 00 00 00 00 00 00 00 00
- 00 00 00 02 04 06 08 0A 0C 0F
+ 12 14 16 18 1A 1C FF FF FF FF
+ FF FF FF FF FF FF FF FF FF FF
+ FF FF 00 02 04 06 08 0A 0C 0F
10 12 13 14 16 18 1C 1D 1E 1F
- 20 21 22 24 26 28 29 2A 00 00
- 00 FF FF FF FF FF FF FF FF FF
- FF FF FF FF A3 01];
+ 20 21 22 24 26 28 29 2A FF FF
+ FF FF FF FF FF FF FF FF FF FF
+ FF FF FF FF 03 01];
goodix,cfg-data1 = [
41 D0 02 00 05 05 35 01 01 C3
2D 06 55 32 03 03 00 00 00 00
diff --git a/arch/arm/boot/dts/msm8226-qrd.dtsi b/arch/arm/boot/dts/msm8226-qrd.dtsi
index eac0bb6..7ff97f6 100644
--- a/arch/arm/boot/dts/msm8226-qrd.dtsi
+++ b/arch/arm/boot/dts/msm8226-qrd.dtsi
@@ -28,6 +28,7 @@
synaptics,reset-gpio = <&msmgpio 16 0x00>;
synaptics,irq-gpio = <&msmgpio 17 0x2008>;
synaptics,button-map = <139 102 158>;
+ synaptics,fw-image-name = "PR1468813.img";
synaptics,i2c-pull-up;
synaptics,power-down;
synaptics,disable-gpios;
diff --git a/arch/arm/boot/dts/msm8226-regulator.dtsi b/arch/arm/boot/dts/msm8226-regulator.dtsi
index 9764982..63da606 100644
--- a/arch/arm/boot/dts/msm8226-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8226-regulator.dtsi
@@ -20,6 +20,7 @@
reg = <0x1700 0x100>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1275000>;
+ qcom,mode = "auto";
};
};
};
@@ -29,7 +30,7 @@
&soc {
apc_vreg_corner: regulator@f9018000 {
status = "okay";
- compatible = "qcom,cpr-regulator";
+ compatible = "qti,cpr-regulator";
reg = <0xf9018000 0x1000>, <0xf9011064 4>, <0xfc4b8000 0x1000>;
reg-names = "rbcpr", "rbcpr_clk", "efuse_addr";
interrupts = <0 15 0>;
@@ -37,51 +38,66 @@
regulator-min-microvolt = <1>;
regulator-max-microvolt = <3>;
- qcom,pvs-fuse-redun-sel = <22 24 3 2>;
- qcom,pvs-fuse = <22 6 5>;
- qcom,pvs-fuse-redun = <22 27 5>;
+ qti,pvs-fuse-redun-sel = <22 24 3 2 0>;
+ qti,pvs-fuse = <22 6 5 0>;
+ qti,pvs-fuse-redun = <22 27 5 0>;
- qcom,pvs-init-voltage = <1275000 1275000 1275000 1275000 1275000
+ qti,pvs-init-voltage = <1275000 1275000 1275000 1275000 1275000
1275000 1260000 1245000 1230000 1215000
1200000 1185000 1170000 1155000 1140000
1140000 1140000 1140000 1140000 1140000
1150000 1140000 1140000 1140000 1140000
1140000 1140000 1140000 1275000 1275000
1275000 1275000>;
- qcom,pvs-corner-ceiling-slow = <1050000 1150000 1275000>;
- qcom,pvs-corner-ceiling-nom = <1050000 1075000 1200000>;
- qcom,pvs-corner-ceiling-fast = <1050000 1050000 1140000>;
+ qti,pvs-corner-ceiling-slow = <1050000 1150000 1275000>;
+ qti,pvs-corner-ceiling-nom = <1050000 1075000 1200000>;
+ qti,pvs-corner-ceiling-fast = <1050000 1050000 1100000>;
vdd-apc-supply = <&pm8226_s2>;
vdd-mx-supply = <&pm8226_l3_ao>;
- qcom,vdd-mx-vmax = <1350000>;
- qcom,vdd-mx-vmin-method = <1>;
+ qti,vdd-mx-vmax = <1350000>;
+ qti,vdd-mx-vmin-method = <1>;
- qcom,cpr-ref-clk = <19200>;
- qcom,cpr-timer-delay = <5000>;
- qcom,cpr-timer-cons-up = <0>;
- qcom,cpr-timer-cons-down = <2>;
- qcom,cpr-irq-line = <0>;
- qcom,cpr-step-quotient = <15>;
- qcom,cpr-up-threshold = <0>;
- qcom,cpr-down-threshold = <10>;
- qcom,cpr-idle-clocks = <0>;
- qcom,cpr-gcnt-time = <1>;
- qcom,vdd-apc-step-up-limit = <1>;
- qcom,vdd-apc-step-down-limit = <1>;
- qcom,cpr-apc-volt-step = <5000>;
+ qti,cpr-ref-clk = <19200>;
+ qti,cpr-timer-delay = <5000>;
+ qti,cpr-timer-cons-up = <0>;
+ qti,cpr-timer-cons-down = <2>;
+ qti,cpr-irq-line = <0>;
+ qti,cpr-step-quotient = <15>;
+ qti,cpr-up-threshold = <0>;
+ qti,cpr-down-threshold = <10>;
+ qti,cpr-idle-clocks = <0>;
+ qti,cpr-gcnt-time = <1>;
+ qti,vdd-apc-step-up-limit = <1>;
+ qti,vdd-apc-step-down-limit = <1>;
+ qti,cpr-apc-volt-step = <5000>;
- qcom,cpr-fuse-redun-sel = <138 57 1 1>;
- qcom,cpr-fuse-row = <138>;
- qcom,cpr-fuse-bp-cpr-disable = <36>;
- qcom,cpr-fuse-bp-scheme = <37>;
- qcom,cpr-fuse-target-quot = <24 12 0>;
- qcom,cpr-fuse-ro-sel = <54 38 41>;
- qcom,cpr-fuse-redun-row = <139>;
- qcom,cpr-fuse-redun-target-quot = <24 12 0>;
- qcom,cpr-fuse-redun-ro-sel = <46 36 39>;
+ qti,cpr-fuse-redun-sel = <138 57 1 1 0>;
+ qti,cpr-fuse-row = <138 0>;
+ qti,cpr-fuse-bp-cpr-disable = <36>;
+ qti,cpr-fuse-bp-scheme = <37>;
+ qti,cpr-fuse-target-quot = <24 12 0>;
+ qti,cpr-fuse-ro-sel = <54 38 41>;
+ qti,cpr-fuse-redun-row = <139 0>;
+ qti,cpr-fuse-redun-target-quot = <24 12 0>;
+ qti,cpr-fuse-redun-ro-sel = <46 36 39>;
- qcom,cpr-enable;
+ qti,cpr-enable;
+ qti,cpr-fuse-cond-min-volt-sel = <54 42 6 7 1>;
+ qti,cpr-cond-min-voltage = <1140000>;
+ qti,cpr-fuse-uplift-sel = <22 53 1 0 0>;
+ qti,cpr-uplift-voltage = <50000>;
+ qti,cpr-uplift-quotient = <0 0 120>;
+ qti,cpr-uplift-max-volt = <1350000>;
+ qti,cpr-uplift-speed-bin = <1>;
+ qti,speed-bin-fuse-sel = <22 0 3 0>;
+ qti,cpr-quot-adjust-table = <1 300000 0 1>,
+ <1 384000 0 1>, <1 600000 0 2>,
+ <1 787200 0 2>, <1 998400 450 3>,
+ <1 1094400 375 3>, <1 1190400 300 3>,
+ <1 1305600 225 3>, <1 1344000 187 3>,
+ <1 1401600 150 3>, <1 1497600 75 3>,
+ <1 1593600 0 3>;
};
};
diff --git a/arch/arm/boot/dts/msm8226-v1-pm.dtsi b/arch/arm/boot/dts/msm8226-v1-pm.dtsi
index 02feec8..a1a8480 100644
--- a/arch/arm/boot/dts/msm8226-v1-pm.dtsi
+++ b/arch/arm/boot/dts/msm8226-v1-pm.dtsi
@@ -111,44 +111,68 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,lpm-level@0 {
- reg = <0x0>;
- qcom,mode = "wfi";
- qcom,l2 = "l2_cache_active";
- qcom,latency-us = <1>;
- qcom,ss-power = <530>;
- qcom,energy-overhead = <52800>;
- qcom,time-overhead = <100>;
+ qcm,cpu-modes {
+ compatible = "qcom,cpu-modes";
+
+ qcom,cpu-modes@0 {
+ qcom,mode = "wfi";
+ qcom,latency-us = <1>;
+ qcom,ss-power = <530>;
+ qcom,energy-overhead = <52800>;
+ qcom,time-overhead = <100>;
+ };
+
+ qcom,cpu-modes@1 {
+ qcom,mode = "standalone_pc";
+ qcom,latency-us = <500>;
+ qcom,ss-power = <410>;
+ qcom,energy-overhead = <603400>;
+ qcom,time-overhead = <1200>;
+ qcom,use-broadcast-timer;
+ };
+
+ qcom,cpu-modes@2 {
+ qcom,mode = "pc";
+ qcom,latency-us = <550>;
+ qcom,ss-power = <372>;
+ qcom,energy-overhead = <700000>;
+ qcom,time-overhead = <1410>;
+ qcom,use-broadcast-timer;
+ };
};
- qcom,lpm-level@1 {
- reg = <0x1>;
- qcom,mode = "standalone_pc";
- qcom,l2 = "l2_cache_active";
- qcom,latency-us = <500>;
- qcom,ss-power = <410>;
- qcom,energy-overhead = <603400>;
- qcom,time-overhead = <1200>;
- };
+ qcom,system-modes {
+ compatible = "qcom,system-modes";
- qcom,lpm-level@2 {
- reg = <0x2>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc_no_rpm";
- qcom,latency-us = <1000>;
- qcom,ss-power = <315>;
- qcom,energy-overhead = <1027150>;
- qcom,time-overhead = <2400>;
- };
+ qcom,system-modes@0 {
+ qcom,l2 = "l2_cache_gdhs";
+ qcom,latency-us = <10700>;
+ qcom,ss-power = <372>;
+ qcom,energy-overhead = <738750>;
+ qcom,time-overhead = <1410>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
- qcom,lpm-level@3 {
- reg = <0x3>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc";
- qcom,latency-us = <11000>;
- qcom,ss-power = <315>;
- qcom,energy-overhead = <1027150>;
- qcom,time-overhead = <2400>;
+ qcom,system-modes@1 {
+ qcom,l2 = "l2_cache_pc_no_rpm";
+ qcom,latency-us = <1000>;
+ qcom,ss-power = <315>;
+ qcom,energy-overhead = <1027150>;
+ qcom,time-overhead = <2400>;
+ qcom,min-cpu-mode= "standalone_pc";
+ qcom,sync-cpus;
+ };
+
+ qcom,system-modes@2 {
+ qcom,l2 = "l2_cache_pc";
+ qcom,latency-us = <12700>;
+ qcom,ss-power = <315>;
+ qcom,energy-overhead = <1027150>;
+ qcom,time-overhead = <2400>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
};
};
@@ -280,6 +304,8 @@
qcom,pc-mode = "tz_l2_int";
qcom,use-sync-timer;
qcom,pc-resets-timer;
+ qcom,cpus-as-clocks;
+ qcom,synced-clocks;
};
qcom,cpu-sleep-status@f9088008{
diff --git a/arch/arm/boot/dts/msm8226-v2-pm.dtsi b/arch/arm/boot/dts/msm8226-v2-pm.dtsi
index 31d5a8f..2e9f6db 100644
--- a/arch/arm/boot/dts/msm8226-v2-pm.dtsi
+++ b/arch/arm/boot/dts/msm8226-v2-pm.dtsi
@@ -113,54 +113,68 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,lpm-level@0 {
- reg = <0x0>;
- qcom,mode = "wfi";
- qcom,l2 = "l2_cache_active";
- qcom,latency-us = <1>;
- qcom,ss-power = <530>;
- qcom,energy-overhead = <52800>;
- qcom,time-overhead = <100>;
+ qcm,cpu-modes {
+ compatible = "qcom,cpu-modes";
+
+ qcom,cpu-modes@0 {
+ qcom,mode = "wfi";
+ qcom,latency-us = <1>;
+ qcom,ss-power = <530>;
+ qcom,energy-overhead = <52800>;
+ qcom,time-overhead = <100>;
+ };
+
+ qcom,cpu-modes@1 {
+ qcom,mode = "standalone_pc";
+ qcom,latency-us = <500>;
+ qcom,ss-power = <410>;
+ qcom,energy-overhead = <603400>;
+ qcom,time-overhead = <1200>;
+ qcom,use-broadcast-timer;
+ };
+
+ qcom,cpu-modes@2 {
+ qcom,mode = "pc";
+ qcom,latency-us = <550>;
+ qcom,ss-power = <372>;
+ qcom,energy-overhead = <700000>;
+ qcom,time-overhead = <1410>;
+ qcom,use-broadcast-timer;
+ };
};
- qcom,lpm-level@1 {
- reg = <0x1>;
- qcom,mode = "standalone_pc";
- qcom,l2 = "l2_cache_active";
- qcom,latency-us = <500>;
- qcom,ss-power = <410>;
- qcom,energy-overhead = <603400>;
- qcom,time-overhead = <1200>;
- };
+ qcom,system-modes {
+ compatible = "qcom,system-modes";
- qcom,lpm-level@2 {
- reg = <0x2>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_gdhs";
- qcom,latency-us = <10700>;
- qcom,ss-power = <372>;
- qcom,energy-overhead = <738750>;
- qcom,time-overhead = <1410>;
- };
+ qcom,system-modes@0 {
+ qcom,l2 = "l2_cache_gdhs";
+ qcom,latency-us = <10700>;
+ qcom,ss-power = <372>;
+ qcom,energy-overhead = <738750>;
+ qcom,time-overhead = <1410>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
- qcom,lpm-level@3 {
- reg = <0x3>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc_no_rpm";
- qcom,latency-us = <1000>;
- qcom,ss-power = <315>;
- qcom,energy-overhead = <1027150>;
- qcom,time-overhead = <2400>;
- };
+ qcom,system-modes@1 {
+ qcom,l2 = "l2_cache_pc_no_rpm";
+ qcom,latency-us = <1000>;
+ qcom,ss-power = <315>;
+ qcom,energy-overhead = <1027150>;
+ qcom,time-overhead = <2400>;
+ qcom,min-cpu-mode= "standalone_pc";
+ qcom,sync-cpus;
+ };
- qcom,lpm-level@4 {
- reg = <0x4>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc";
- qcom,latency-us = <11000>;
- qcom,ss-power = <315>;
- qcom,energy-overhead = <1027150>;
- qcom,time-overhead = <2400>;
+ qcom,system-modes@2 {
+ qcom,l2 = "l2_cache_pc";
+ qcom,latency-us = <12700>;
+ qcom,ss-power = <315>;
+ qcom,energy-overhead = <1027150>;
+ qcom,time-overhead = <2400>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
};
};
@@ -292,6 +306,8 @@
qcom,pc-mode = "tz_l2_int";
qcom,use-sync-timer;
qcom,pc-resets-timer;
+ qcom,cpus-as-clocks;
+ qcom,synced-clocks;
};
qcom,cpu-sleep-status@f9088008{
diff --git a/arch/arm/boot/dts/msm8226-v2.dtsi b/arch/arm/boot/dts/msm8226-v2.dtsi
index a57adcd..ddba542 100644
--- a/arch/arm/boot/dts/msm8226-v2.dtsi
+++ b/arch/arm/boot/dts/msm8226-v2.dtsi
@@ -52,20 +52,20 @@
};
&apc_vreg_corner {
- qcom,pvs-init-voltage = <1330000 1330000 1330000 1320000 1310000
+ qti,pvs-init-voltage = <1330000 1330000 1330000 1320000 1310000
1300000 1290000 1280000 1270000 1260000
1250000 1240000 1230000 1220000 1210000
1200000 1190000 1180000 1170000 1160000
1150000 1140000 1140000 1140000 1140000
1140000 1140000 1140000 1140000 1140000
1140000 1140000>;
- qcom,pvs-corner-ceiling-slow = <1050000 1150000 1280000>;
- qcom,pvs-corner-ceiling-nom = <1050000 1080000 1200000>;
- qcom,pvs-corner-ceiling-fast = <1050000 1050000 1140000>;
- qcom,cpr-step-quotient = <30>;
- qcom,cpr-up-threshold = <0>;
- qcom,cpr-down-threshold = <5>;
- qcom,cpr-apc-volt-step = <10000>;
+ qti,pvs-corner-ceiling-slow = <1050000 1150000 1280000>;
+ qti,pvs-corner-ceiling-nom = <1050000 1080000 1200000>;
+ qti,pvs-corner-ceiling-fast = <1050000 1050000 1100000>;
+ qti,cpr-step-quotient = <30>;
+ qti,cpr-up-threshold = <0>;
+ qti,cpr-down-threshold = <5>;
+ qti,cpr-apc-volt-step = <10000>;
};
&msm_gpu {
@@ -74,10 +74,45 @@
};
&soc {
- qcom,acpuclk@f9011050 {
+ qcom,clock-a7@f9011050 {
reg = <0xf9011050 0x8>,
<0xfc4b80b0 0x8>;
- reg-names = "rcg_base", "pte_efuse";
+ reg-names = "rcg-base", "efuse";
+ qcom,speed0-bin-v2 =
+ < 0 0>,
+ < 384000000 1>,
+ < 787200000 2>,
+ <1190400000 3>;
+ qcom,speed6-bin-v2 =
+ < 0 0>,
+ < 384000000 1>,
+ < 787200000 2>,
+ <1190400000 3>;
+ qcom,speed2-bin-v2 =
+ < 0 0>,
+ < 384000000 1>,
+ < 787200000 2>,
+ <1401600000 3>;
+ qcom,speed5-bin-v2 =
+ < 0 0>,
+ < 384000000 1>,
+ < 787200000 2>,
+ <1401600000 3>;
+ qcom,speed4-bin-v2 =
+ < 0 0>,
+ < 384000000 1>,
+ < 787200000 2>,
+ <149700000 3>;
+ qcom,speed7-bin-v2 =
+ < 0 0>,
+ < 384000000 1>,
+ < 787200000 2>,
+ <1497600000 3>;
+ qcom,speed1-bin-v2 =
+ < 0 0>,
+ < 384000000 1>,
+ < 787200000 2>,
+ <1593600000 3>;
};
};
diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index c78dacd..1250ed2 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -57,6 +57,7 @@
/include/ "msm8226-mdss.dtsi"
/include/ "msm8226-coresight.dtsi"
/include/ "msm8226-iommu-domains.dtsi"
+/include/ "msm-rdbg.dtsi"
&soc {
#address-cells = <1>;
@@ -216,13 +217,13 @@
reg = <0xf991f000 0x1000>;
interrupts = <0 109 0>;
status = "disabled";
- };
- serial@f995e000 {
- compatible = "qcom,msm-lsuart-v14";
- reg = <0xf995e000 0x1000>;
- interrupts = <0 114 0>;
- status = "disabled";
+ qcom,msm-bus,name = "blsp1_uart2";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <86 512 0 0>,
+ <86 512 500 800>;
};
qcom,msm-imem@fe805000 {
@@ -281,7 +282,6 @@
qcom,hsusb-otg-phy-type = <2>;
qcom,hsusb-otg-mode = <1>;
qcom,hsusb-otg-otg-control = <2>;
- qcom,hsusb-otg-disable-reset;
qcom,dp-manual-pullup;
qcom,ahb-async-bridge-bypass;
@@ -972,6 +972,9 @@
interrupt-names = "qup_err_intr";
qcom,i2c-bus-freq = <400000>;
qcom,i2c-src-freq = <19200000>;
+ qcom,sda-gpio = <&msmgpio 10 0>;
+ qcom,scl-gpio = <&msmgpio 11 0>;
+ qcom,master-id = <86>;
};
i2c@f9926000 { /* BLSP-1 QUP-4 */
cell-index = <0>;
@@ -1000,11 +1003,37 @@
qcom,scl-gpio = <&msmgpio 19 0>;
};
- qcom,acpuclk@f9011050 {
- compatible = "qcom,acpuclk-a7";
+ qcom,clock-a7@f9011050 {
+ compatible = "qcom,clock-a7-8226";
reg = <0xf9011050 0x8>;
- reg-names = "rcg_base";
- a7_cpu-supply = <&apc_vreg_corner>;
+ reg-names = "rcg-base";
+ clock-names = "clk-4", "clk-5";
+ qcom,speed0-bin-v0 =
+ < 0 0>,
+ < 384000000 1>,
+ < 787200000 2>,
+ <1190400000 3>;
+
+ cpu-vdd-supply = <&apc_vreg_corner>;
+ };
+
+ qcom,msm-cpufreq@0 {
+ reg = <0 4>;
+ compatible = "qcom,msm-cpufreq";
+ qcom,cpu-mem-ports = <1 512>;
+ qcom,cpufreq-table =
+ < 300000 1600 /* 200 MHz */ >,
+ < 384000 1600 /* 200 MHz */ >,
+ < 600000 3200 /* 320 MHz */ >,
+ < 787200 4264 /* 533 MHz */ >,
+ < 998400 4264 /* 533 MHz */ >,
+ < 1094400 4264 /* 533 MHz */ >,
+ < 1190400 4264 /* 533 MHz */ >,
+ < 1305600 4264 /* 533 MHz */ >,
+ < 1344000 4264 /* 533 MHz */ >,
+ < 1401600 4264 /* 533 MHz */ >,
+ < 1497600 4264 /* 533 MHz */ >,
+ < 1593600 4264 /* 533 MHz */ >;
};
qcom,ocmem@fdd00000 {
diff --git a/arch/arm/boot/dts/msm8610-cdp.dtsi b/arch/arm/boot/dts/msm8610-cdp.dtsi
index d63c6e5..04eca14 100644
--- a/arch/arm/boot/dts/msm8610-cdp.dtsi
+++ b/arch/arm/boot/dts/msm8610-cdp.dtsi
@@ -143,7 +143,11 @@
"MIC BIAS External", "Handset Mic",
"MIC BIAS Internal2", "Headset Mic",
"AMIC1", "MIC BIAS External",
- "AMIC2", "MIC BIAS Internal2";
+ "AMIC2", "MIC BIAS Internal2",
+ "MIC BIAS External", "Digital Mic1",
+ "MIC BIAS External", "Digital Mic2",
+ "DMIC1", "MIC BIAS External",
+ "DMIC2", "MIC BIAS External";
qcom,headset-jack-type-NC;
};
};
diff --git a/arch/arm/boot/dts/msm8610-mtp.dtsi b/arch/arm/boot/dts/msm8610-mtp.dtsi
index 6ce0109..3b0f2a2 100644
--- a/arch/arm/boot/dts/msm8610-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8610-mtp.dtsi
@@ -142,7 +142,7 @@
0x2800>;
capella,ps_close_thd_set = <0xa>;
capella,ps_away_thd_set = <0x5>;
- capella,ls_cmd = <0x44>; /* PS_IT=160ms, INT_PERS=2*/
+ capella,ls_cmd = <0x04>; /* ALS_IT=80ms, INT_PERS=2*/
capella,ps_conf1_val = <0x0006>;
capella,ps_conf3_val = <0x3010>;
};
diff --git a/arch/arm/boot/dts/msm8610-qrd-skuaa.dtsi b/arch/arm/boot/dts/msm8610-qrd-skuaa.dtsi
index bb866b2..719830e 100644
--- a/arch/arm/boot/dts/msm8610-qrd-skuaa.dtsi
+++ b/arch/arm/boot/dts/msm8610-qrd-skuaa.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ /* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -33,18 +33,17 @@
<0x44 0x80 0x6a 0x81 0x34 0x82 0x13 0x83 0xffffffff>;
};
- i2c@f9925000 { /* BLSP-1 QUP-3 */
+ i2c@f9924000 { /* BLSP-1 QUP-2 */
nfc-nci@e {
compatible = "qcom,nfc-nci";
reg = <0x0e>;
qcom,irq-gpio = <&msmgpio 77 0x00>;
qcom,dis-gpio = <&msmgpio 93 0x00>;
qcom,clk-en-gpio = <&msmgpio 78 0x00>;
- qcom,clk-src = "GPCLK";
+ qcom,clk-src = "GPCLK2";
interrupt-parent = <&msmgpio>;
interrupts = <77 0>;
qcom,clk-gpio = <&msmgpio 75 0x00>;
- vlogic-supply = <&pm8110_l14>;
};
};
};
diff --git a/arch/arm/boot/dts/msm8610-qrd.dtsi b/arch/arm/boot/dts/msm8610-qrd.dtsi
index 85bd746..92d1a77 100644
--- a/arch/arm/boot/dts/msm8610-qrd.dtsi
+++ b/arch/arm/boot/dts/msm8610-qrd.dtsi
@@ -102,6 +102,10 @@
linux,default-trigger = "flashlight-trigger";
};
+ qcom,wdt@f9017000 {
+ qcom,bark-time = <13000>;
+ };
+
gpio_keys {
compatible = "gpio-keys";
input-name = "gpio-keys";
diff --git a/arch/arm/boot/dts/msm8610-regulator.dtsi b/arch/arm/boot/dts/msm8610-regulator.dtsi
index 7eb6a22..f9bafb4 100644
--- a/arch/arm/boot/dts/msm8610-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8610-regulator.dtsi
@@ -30,7 +30,7 @@
&soc {
apc_vreg_corner: regulator@f9018000 {
status = "okay";
- compatible = "qcom,cpr-regulator";
+ compatible = "qti,cpr-regulator";
reg = <0xf9018000 0x1000>, <0xf9011064 4>, <0xfc4b8000 0x1000>;
reg-names = "rbcpr", "rbcpr_clk", "efuse_addr";
interrupts = <0 15 0>;
@@ -38,54 +38,53 @@
regulator-min-microvolt = <1>;
regulator-max-microvolt = <3>;
- qcom,pvs-fuse-redun-sel = <53 25 3 2>;
- qcom,pvs-fuse = <23 6 5>;
- qcom,pvs-fuse-redun = <61 47 5>;
+ qti,pvs-fuse-redun-sel = <53 25 3 2 1>;
+ qti,pvs-fuse = <23 6 5 1>;
+ qti,pvs-fuse-redun = <61 47 5 1>;
- qcom,pvs-init-voltage = <1275000 1275000 1275000 1275000 1275000
+ qti,pvs-init-voltage = <1275000 1275000 1275000 1275000 1275000
1275000 1275000 1275000 1275000 1275000
1275000 1275000 1275000 1275000 1275000
1275000 1275000 1275000 1275000 1275000
1275000 1275000 1275000 1275000 1275000
1275000 1275000 1275000 1275000 1275000
1275000 1275000>;
- qcom,pvs-corner-ceiling-slow = <1150000 1150000 1275000>;
- qcom,pvs-corner-ceiling-nom = <1075000 1075000 1200000>;
- qcom,pvs-corner-ceiling-fast = <1050000 1050000 1140000>;
+ qti,pvs-corner-ceiling-slow = <1150000 1150000 1275000>;
+ qti,pvs-corner-ceiling-nom = <1075000 1075000 1200000>;
+ qti,pvs-corner-ceiling-fast = <1050000 1050000 1140000>;
vdd-apc-supply = <&pm8110_s2>;
vdd-mx-supply = <&pm8110_l3_ao>;
- qcom,vdd-mx-vmax = <1350000>;
- qcom,vdd-mx-vmin-method = <1>;
+ qti,vdd-mx-vmax = <1350000>;
+ qti,vdd-mx-vmin-method = <1>;
- qcom,cpr-ref-clk = <19200>;
- qcom,cpr-timer-delay = <5000>;
- qcom,cpr-timer-cons-up = <0>;
- qcom,cpr-timer-cons-down = <2>;
- qcom,cpr-irq-line = <0>;
- qcom,cpr-step-quotient = <15>;
- qcom,cpr-up-threshold = <0>;
- qcom,cpr-down-threshold = <10>;
- qcom,cpr-idle-clocks = <5>;
- qcom,cpr-gcnt-time = <1>;
- qcom,vdd-apc-step-up-limit = <1>;
- qcom,vdd-apc-step-down-limit = <1>;
- qcom,cpr-apc-volt-step = <5000>;
+ qti,cpr-ref-clk = <19200>;
+ qti,cpr-timer-delay = <5000>;
+ qti,cpr-timer-cons-up = <0>;
+ qti,cpr-timer-cons-down = <2>;
+ qti,cpr-irq-line = <0>;
+ qti,cpr-step-quotient = <15>;
+ qti,cpr-up-threshold = <0>;
+ qti,cpr-down-threshold = <10>;
+ qti,cpr-idle-clocks = <5>;
+ qti,cpr-gcnt-time = <1>;
+ qti,vdd-apc-step-up-limit = <1>;
+ qti,vdd-apc-step-down-limit = <1>;
+ qti,cpr-apc-volt-step = <5000>;
- qcom,cpr-fuse-redun-sel = <53 25 3 2>;
- qcom,cpr-fuse-row = <61>;
- qcom,cpr-fuse-bp-cpr-disable = <39>;
- qcom,cpr-fuse-bp-scheme = <40>;
- qcom,cpr-fuse-target-quot = <27 15 3>;
- qcom,cpr-fuse-ro-sel = <47 41 44>;
- qcom,cpr-fuse-redun-row = <52>;
- qcom,cpr-fuse-redun-bp-cpr-disable = <24>;
- qcom,cpr-fuse-redun-bp-scheme = <25>;
- qcom,cpr-fuse-redun-target-quot = <32 12 0>;
- qcom,cpr-fuse-redun-ro-sel = <44 26 29>;
+ qti,cpr-fuse-redun-sel = <53 25 3 2 1>;
+ qti,cpr-fuse-row = <61 1>;
+ qti,cpr-fuse-bp-cpr-disable = <39>;
+ qti,cpr-fuse-bp-scheme = <40>;
+ qti,cpr-fuse-target-quot = <27 15 3>;
+ qti,cpr-fuse-ro-sel = <47 41 44>;
+ qti,cpr-fuse-redun-row = <52 1>;
+ qti,cpr-fuse-redun-bp-cpr-disable = <24>;
+ qti,cpr-fuse-redun-bp-scheme = <25>;
+ qti,cpr-fuse-redun-target-quot = <32 12 0>;
+ qti,cpr-fuse-redun-ro-sel = <44 26 29>;
- qcom,cpr-enable;
- qcom,use-tz-api;
+ qti,cpr-enable;
};
};
diff --git a/arch/arm/boot/dts/msm8610-rumi.dts b/arch/arm/boot/dts/msm8610-rumi.dts
index 7f06485..c22b4f28 100644
--- a/arch/arm/boot/dts/msm8610-rumi.dts
+++ b/arch/arm/boot/dts/msm8610-rumi.dts
@@ -17,7 +17,7 @@
/ {
model = "Qualcomm MSM 8610 Rumi";
compatible = "qcom,msm8610-rumi", "qcom,msm8610", "qcom,rumi";
- qcom,msm-id = <147 15 0>;
+ qcom,board-id = <15 0>;
};
&soc {
diff --git a/arch/arm/boot/dts/msm8610-sim.dts b/arch/arm/boot/dts/msm8610-sim.dts
index 33176b9..531ee4b 100644
--- a/arch/arm/boot/dts/msm8610-sim.dts
+++ b/arch/arm/boot/dts/msm8610-sim.dts
@@ -17,7 +17,7 @@
/ {
model = "Qualcomm MSM 8610 Simulator";
compatible = "qcom,msm8610-sim", "qcom,msm8610", "qcom,sim";
- qcom,msm-id = <147 16 0>;
+ qcom,board-id = <16 0>;
};
&soc {
diff --git a/arch/arm/boot/dts/msm8610-v1-cdp.dts b/arch/arm/boot/dts/msm8610-v1-cdp.dts
index beb3976..5a70379 100644
--- a/arch/arm/boot/dts/msm8610-v1-cdp.dts
+++ b/arch/arm/boot/dts/msm8610-v1-cdp.dts
@@ -19,8 +19,7 @@
/ {
model = "Qualcomm MSM 8610 CDP";
compatible = "qcom,msm8610-cdp", "qcom,msm8610", "qcom,cdp";
- qcom,msm-id = <147 1 0>, <165 1 0>, <161 1 0>, <162 1 0>,
- <163 1 0>, <164 1 0>, <166 1 0>;
+ qcom,board-id = <1 0>;
};
diff --git a/arch/arm/boot/dts/msm8610-v1-mtp.dts b/arch/arm/boot/dts/msm8610-v1-mtp.dts
index 82992a3..c8c8d09 100644
--- a/arch/arm/boot/dts/msm8610-v1-mtp.dts
+++ b/arch/arm/boot/dts/msm8610-v1-mtp.dts
@@ -19,8 +19,7 @@
/ {
model = "Qualcomm MSM 8610 MTP";
compatible = "qcom,msm8610-mtp", "qcom,msm8610", "qcom,mtp";
- qcom,msm-id = <147 8 0>, <165 8 0>, <161 8 0>, <162 8 0>,
- <163 8 0>, <164 8 0>, <166 8 0>;
+ qcom,board-id = <8 0>;
};
diff --git a/arch/arm/boot/dts/msm8610-v1-pm.dtsi b/arch/arm/boot/dts/msm8610-v1-pm.dtsi
index 62aa0f4..ea37413 100644
--- a/arch/arm/boot/dts/msm8610-v1-pm.dtsi
+++ b/arch/arm/boot/dts/msm8610-v1-pm.dtsi
@@ -111,46 +111,69 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,lpm-level@0 {
- reg = <0x0>;
- qcom,mode = "wfi";
- qcom,l2 = "l2_cache_active";
- qcom,latency-us = <1>;
- qcom,ss-power = <530>;
- qcom,energy-overhead = <52800>;
- qcom,time-overhead = <100>;
+ qcm,cpu-modes {
+ compatible = "qcom,cpu-modes";
+
+ qcom,cpu-modes@0 {
+ qcom,mode = "wfi";
+ qcom,latency-us = <1>;
+ qcom,ss-power = <530>;
+ qcom,energy-overhead = <52800>;
+ qcom,time-overhead = <100>;
+ };
+
+ qcom,cpu-modes@1 {
+ qcom,mode = "standalone_pc";
+ qcom,latency-us = <500>;
+ qcom,ss-power = <410>;
+ qcom,energy-overhead = <603400>;
+ qcom,time-overhead = <1200>;
+ qcom,use-broadcast-timer;
+ };
+
+ qcom,cpu-modes@2 {
+ qcom,mode = "pc";
+ qcom,latency-us = <550>;
+ qcom,ss-power = <372>;
+ qcom,energy-overhead = <700000>;
+ qcom,time-overhead = <1410>;
+ qcom,use-broadcast-timer;
+ };
};
- qcom,lpm-level@1 {
- reg = <0x1>;
- qcom,mode = "standalone_pc";
- qcom,l2 = "l2_cache_active";
- qcom,latency-us = <500>;
- qcom,ss-power = <410>;
- qcom,energy-overhead = <603400>;
- qcom,time-overhead = <1410>;
- };
+ qcom,system-modes {
+ compatible = "qcom,system-modes";
- qcom,lpm-level@2 {
- reg = <0x2>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc_no_rpm";
- qcom,latency-us = <1000>;
- qcom,ss-power = <315>;
- qcom,energy-overhead = <1027150>;
- qcom,time-overhead = <2400>;
- };
+ qcom,system-modes@0 {
+ qcom,l2 = "l2_cache_gdhs";
+ qcom,latency-us = <10700>;
+ qcom,ss-power = <372>;
+ qcom,energy-overhead = <738750>;
+ qcom,time-overhead = <1410>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
- qcom,lpm-level@3 {
- reg = <0x3>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc";
- qcom,latency-us = <12700>;
- qcom,ss-power = <315>;
- qcom,energy-overhead = <1027150>;
- qcom,time-overhead = <2400>;
- };
+ qcom,system-modes@1 {
+ qcom,l2 = "l2_cache_pc_no_rpm";
+ qcom,latency-us = <1000>;
+ qcom,ss-power = <315>;
+ qcom,energy-overhead = <1027150>;
+ qcom,time-overhead = <2400>;
+ qcom,min-cpu-mode= "standalone_pc";
+ qcom,sync-cpus;
+ };
+ qcom,system-modes@2 {
+ qcom,l2 = "l2_cache_pc";
+ qcom,latency-us = <12700>;
+ qcom,ss-power = <315>;
+ qcom,energy-overhead = <1027150>;
+ qcom,time-overhead = <2400>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
+ };
};
qcom,pm-boot {
diff --git a/arch/arm/boot/dts/msm8610-v2-cdp.dts b/arch/arm/boot/dts/msm8610-v2-cdp.dts
index a6d1d9c..447161f 100644
--- a/arch/arm/boot/dts/msm8610-v2-cdp.dts
+++ b/arch/arm/boot/dts/msm8610-v2-cdp.dts
@@ -19,8 +19,7 @@
/ {
model = "Qualcomm MSM 8610v2 CDP";
compatible = "qcom,msm8610-cdp", "qcom,msm8610", "qcom,cdp";
- qcom,msm-id = <147 1 0x10001>, <165 1 0x10001>, <161 1 0x10001>, <162 1 0x10001>,
- <163 1 0x10001>, <164 1 0x10001>, <166 1 0x10001>;
+ qcom,board-id = <1 0>;
};
diff --git a/arch/arm/boot/dts/msm8610-v2-mtp.dts b/arch/arm/boot/dts/msm8610-v2-mtp.dts
index 405a775..77f5276 100644
--- a/arch/arm/boot/dts/msm8610-v2-mtp.dts
+++ b/arch/arm/boot/dts/msm8610-v2-mtp.dts
@@ -19,8 +19,7 @@
/ {
model = "Qualcomm MSM 8610v2 MTP";
compatible = "qcom,msm8610-mtp", "qcom,msm8610", "qcom,mtp";
- qcom,msm-id = <147 8 0x10001>, <165 8 0x10001>, <161 8 0x10001>, <162 8 0x10001>,
- <163 8 0x10001>, <164 8 0x10001>, <166 8 0x10001>;
+ qcom,board-id = <8 0>;
};
diff --git a/arch/arm/boot/dts/msm8610-v2-pm.dtsi b/arch/arm/boot/dts/msm8610-v2-pm.dtsi
index e401f7a..19fb185 100644
--- a/arch/arm/boot/dts/msm8610-v2-pm.dtsi
+++ b/arch/arm/boot/dts/msm8610-v2-pm.dtsi
@@ -113,54 +113,68 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,lpm-level@0 {
- reg = <0x0>;
- qcom,mode = "wfi";
- qcom,l2 = "l2_cache_active";
- qcom,latency-us = <1>;
- qcom,ss-power = <530>;
- qcom,energy-overhead = <52800>;
- qcom,time-overhead = <100>;
+ qcm,cpu-modes {
+ compatible = "qcom,cpu-modes";
+
+ qcom,cpu-modes@0 {
+ qcom,mode = "wfi";
+ qcom,latency-us = <1>;
+ qcom,ss-power = <530>;
+ qcom,energy-overhead = <52800>;
+ qcom,time-overhead = <100>;
+ };
+
+ qcom,cpu-modes@1 {
+ qcom,mode = "standalone_pc";
+ qcom,latency-us = <500>;
+ qcom,ss-power = <410>;
+ qcom,energy-overhead = <603400>;
+ qcom,time-overhead = <1200>;
+ qcom,use-broadcast-timer;
+ };
+
+ qcom,cpu-modes@2 {
+ qcom,mode = "pc";
+ qcom,latency-us = <550>;
+ qcom,ss-power = <372>;
+ qcom,energy-overhead = <700000>;
+ qcom,time-overhead = <1410>;
+ qcom,use-broadcast-timer;
+ };
};
- qcom,lpm-level@1 {
- reg = <0x1>;
- qcom,mode = "standalone_pc";
- qcom,l2 = "l2_cache_active";
- qcom,latency-us = <500>;
- qcom,ss-power = <410>;
- qcom,energy-overhead = <603400>;
- qcom,time-overhead = <1200>;
- };
+ qcom,system-modes {
+ compatible = "qcom,system-modes";
- qcom,lpm-level@2 {
- reg = <0x2>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_gdhs";
- qcom,latency-us = <11700>;
- qcom,ss-power = <372>;
- qcom,energy-overhead = <738750>;
- qcom,time-overhead = <1410>;
- };
+ qcom,system-modes@0 {
+ qcom,l2 = "l2_cache_gdhs";
+ qcom,latency-us = <10700>;
+ qcom,ss-power = <372>;
+ qcom,energy-overhead = <738750>;
+ qcom,time-overhead = <1410>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
- qcom,lpm-level@3 {
- reg = <0x3>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc_no_rpm";
- qcom,latency-us = <1000>;
- qcom,ss-power = <315>;
- qcom,energy-overhead = <1027150>;
- qcom,time-overhead = <2400>;
- };
+ qcom,system-modes@1 {
+ qcom,l2 = "l2_cache_pc_no_rpm";
+ qcom,latency-us = <1000>;
+ qcom,ss-power = <315>;
+ qcom,energy-overhead = <1027150>;
+ qcom,time-overhead = <2400>;
+ qcom,min-cpu-mode= "standalone_pc";
+ qcom,sync-cpus;
+ };
- qcom,lpm-level@4 {
- reg = <0x4>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc";
- qcom,latency-us = <12700>;
- qcom,ss-power = <315>;
- qcom,energy-overhead = <1027150>;
- qcom,time-overhead = <2400>;
+ qcom,system-modes@2 {
+ qcom,l2 = "l2_cache_pc";
+ qcom,latency-us = <12700>;
+ qcom,ss-power = <315>;
+ qcom,energy-overhead = <1027150>;
+ qcom,time-overhead = <2400>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
};
};
@@ -184,24 +198,40 @@
<62 222>, /* ee0_krait_hlos_spmi_periph_irq */
<2 216>, /* tsens_upper_lower_int */
<41 63>, /* dino_gen_purpose_irq35 */
+ <0xff 18>, /* APC_qgicQTmrSecPhysIrptReq */
+ <0xff 19>, /* APC_qgicQTmrNonSecPhysIrptReq */
+ <0xff 35>, /* WDT_barkInt */
+ <0xff 40>, /* qtmr_phy_irq[0] */
+ <0xff 47>, /* rbif_irq[0] */
<0xff 56>, /* q6_wdog_expired_irq */
<0xff 57>, /* mss_to_apps_irq(0) */
<0xff 58>, /* mss_to_apps_irq(1) */
<0xff 59>, /* mss_to_apps_irq(2) */
<0xff 60>, /* mss_to_apps_irq(3) */
<0xff 61>, /* mss_a2_bam_irq */
+ <0xff 65>, /* o_gc_sys_irq[0] */
+ <0xff 74>, /* venus0_mmu_cirpt[1] */
+ <0xff 75>, /* venus0_mmu_cirpt[0] */
+ <0xff 78>, /* mdss_mmu_cirpt[0] */
+ <0xff 79>, /* mdss_mmu_cirpt[1] */
+ <0xff 97>, /* camss_vfe_mmu_cirpt[1] */
+ <0xff 102>, /* camss_jpeg_mmu_cirpt[1] */
+ <0xff 109>, /* ocmem_dm_nonsec_irq */
+ <0xff 131>, /* blsp1_qup_5_irq */
+ <0xff 141>, /* blsp1_uart_3_irq */
+ <0xff 155>, /* sdc1_irq(0) */
+ <0xff 157>, /* sdc2_irq(0) */
+ <0xff 161>, /* lpass_irq_out_spare[4] */
+ <0xff 162>, /* lpass_irq_out_spare[5]*/
+ <0xff 170>, /* sdc1_pwr_cmd_irq */
<0xff 173>, /* o_wcss_apss_smd_hi */
<0xff 174>, /* o_wcss_apss_smd_med */
<0xff 175>, /* o_wcss_apss_smd_low */
<0xff 176>, /* o_wcss_apss_smsm_irq */
<0xff 177>, /* o_wcss_apss_wlan_data_xfer_done */
<0xff 178>, /* o_wcss_apss_wlan_rx_data_avail */
- <0xff 179>, /* o_wcss_apss_asic_intr
+ <0xff 179>, /* o_wcss_apss_asic_intr */
<0xff 181>, /* o_wcss_apss_wdog_bite_and_reset_rdy */
- <0xff 161>, /* lpass_irq_out_spare[4] /
- <0xff 162>, /* lpass_irq_out_spare[5]*/
- <0xff 234>, /* lpass_irq_out_spare[6]*/
- <0xff 235>, /* lpass_irq_out_spare[7]*/
<0xff 188>, /* lpass_irq_out_apcs(0) */
<0xff 189>, /* lpass_irq_out_apcs(1) */
<0xff 190>, /* lpass_irq_out_apcs(2) */
@@ -216,12 +246,16 @@
<0xff 205>, /* rpm_ipc(25) */
<0xff 206>, /* rpm_ipc(26) */
<0xff 207>, /* rpm_ipc(27) */
+ <0xff 234>, /* lpass_irq_out_spare[6]*/
+ <0xff 235>, /* lpass_irq_out_spare[7]*/
+ <0xff 240>, /* summary_irq_kpss */
+ <0xff 253>, /* sdc2_pwr_cmd_irq */
<0xff 258>, /* rpm_ipc(28) */
<0xff 259>, /* rpm_ipc(29) */
- <0xff 275>, /* rpm_ipc(30) */
- <0xff 276>, /* rpm_ipc(31) */
<0xff 269>, /* rpm_wdog_expired_irq */
- <0xff 240>; /* summary_irq_kpss */
+ <0xff 270>, /* blsp1_bam_irq[0] */
+ <0xff 275>, /* rpm_ipc(30) */
+ <0xff 276>; /* rpm_ipc(31) */
qcom,gpio-parent = <&msmgpio>;
qcom,gpio-map = <3 1>,
diff --git a/arch/arm/boot/dts/msm8610-v2-qrd-skuab-dvt2.dts b/arch/arm/boot/dts/msm8610-v2-qrd-skuab-dvt2.dts
index 95a5da5..2547148 100644
--- a/arch/arm/boot/dts/msm8610-v2-qrd-skuab-dvt2.dts
+++ b/arch/arm/boot/dts/msm8610-v2-qrd-skuab-dvt2.dts
@@ -56,10 +56,26 @@
&dsi_hx8389b_qhd_vid {
qcom,cont-splash-enabled;
};
+
&soc {
i2c@f9925000 {
fsl@1c {
fsl,sensors-position = <7>;
};
};
-};
\ No newline at end of file
+};
+
+&qrd_batterydata {
+ qcom,rpull-up-kohm = <100>;
+ qcom,vref-batt-therm = <1800000>;
+
+ /include/ "batterydata-qrd-4v2-2200mah.dtsi"
+};
+
+&pm8110_bms {
+ qcom,battery-data = <&qrd_batterydata>;
+};
+
+&pm8110_chg {
+ qcom,battery-data = <&qrd_batterydata>;
+};
diff --git a/arch/arm/boot/dts/msm8610.dtsi b/arch/arm/boot/dts/msm8610.dtsi
index 26efa78..94a9db0 100644
--- a/arch/arm/boot/dts/msm8610.dtsi
+++ b/arch/arm/boot/dts/msm8610.dtsi
@@ -43,6 +43,7 @@
/include/ "msm8610-smp2p.dtsi"
/include/ "msm8610-bus.dtsi"
/include/ "msm8610-mdss.dtsi"
+/include/ "msm-rdbg.dtsi"
&soc {
#address-cells = <1>;
@@ -240,6 +241,7 @@
qcom,hsusb-otg-disable-reset;
qcom,dp-manual-pullup;
qcom,ahb-async-bridge-bypass;
+ qcom,disable-retention-with-vdd-min;
qcom,msm-bus,name = "usb2";
qcom,msm-bus,num-cases = <2>;
@@ -529,6 +531,21 @@
qcom,master-id = <86>;
};
+
+ i2c@f9924000 { /* BLSP-1 QUP-3 */
+ cell-index = <2>;
+ compatible = "qcom,i2c-qup";
+ reg-names = "qup_phys_addr";
+ reg = <0xf9924000 0x1000>;
+ interrupt-names = "qup_err_intr";
+ interrupts = <0 96 0>;
+ qcom,i2c-bus-freq = <100000>;
+ qcom,i2c-src-freq = <19200000>;
+ qcom,sda-gpio = <&msmgpio 8 0>;
+ qcom,scl-gpio = <&msmgpio 9 0>;
+ qcom,master-id = <86>;
+ };
+
i2c@f9925000 { /* BLSP-1 QUP-3 */
cell-index = <0>;
compatible = "qcom,i2c-qup";
@@ -876,8 +893,8 @@
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
- <1 618 0 0>,
- <1 618 0 800>;
+ <54 618 0 0>,
+ <54 618 0 800>;
};
qcom,msm-rtb {
diff --git a/arch/arm/boot/dts/msm8926.dtsi b/arch/arm/boot/dts/msm8926.dtsi
index bbddec3..0b876a1 100644
--- a/arch/arm/boot/dts/msm8926.dtsi
+++ b/arch/arm/boot/dts/msm8926.dtsi
@@ -116,20 +116,20 @@
};
&apc_vreg_corner {
- qcom,pvs-init-voltage = <1350000 1340000 1330000 1320000 1310000
+ qti,pvs-init-voltage = <1350000 1340000 1330000 1320000 1310000
1300000 1290000 1280000 1270000 1260000
1250000 1240000 1230000 1220000 1210000
1200000 1190000 1180000 1170000 1160000
1150000 1140000 1140000 1140000 1140000
1140000 1140000 1140000 1140000 1140000
1140000 1140000>;
- qcom,pvs-corner-ceiling-slow = <1050000 1150000 1280000>;
- qcom,pvs-corner-ceiling-nom = <1050000 1080000 1200000>;
- qcom,pvs-corner-ceiling-fast = <1050000 1050000 1140000>;
- qcom,cpr-step-quotient = <30>;
- qcom,cpr-up-threshold = <0>;
- qcom,cpr-down-threshold = <5>;
- qcom,cpr-apc-volt-step = <10000>;
+ qti,pvs-corner-ceiling-slow = <1050000 1150000 1280000>;
+ qti,pvs-corner-ceiling-nom = <1050000 1080000 1200000>;
+ qti,pvs-corner-ceiling-fast = <1050000 1050000 1100000>;
+ qti,cpr-step-quotient = <30>;
+ qti,cpr-up-threshold = <0>;
+ qti,cpr-down-threshold = <5>;
+ qti,cpr-apc-volt-step = <10000>;
};
&tsens {
diff --git a/arch/arm/boot/dts/msm8974-gpu.dtsi b/arch/arm/boot/dts/msm8974-gpu.dtsi
index 06b9c18..695e452 100644
--- a/arch/arm/boot/dts/msm8974-gpu.dtsi
+++ b/arch/arm/boot/dts/msm8974-gpu.dtsi
@@ -22,8 +22,7 @@
qcom,chipid = <0x03030000>;
- qcom,initial-pwrlevel = <2>;
- qcom,step-pwrlevel = <2>;
+ qcom,initial-pwrlevel = <1>;
qcom,idle-timeout = <8>; //<HZ/12>
qcom,strtstp-sleepwake;
@@ -31,14 +30,17 @@
/* Bus Scale Settings */
qcom,msm-bus,name = "grp3d";
- qcom,msm-bus,num-cases = <6>;
+ qcom,msm-bus,num-cases = <9>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
<26 512 0 0>, <89 604 0 0>,
+ <26 512 0 1600000>, <89 604 0 3000000>,
<26 512 0 2200000>, <89 604 0 3000000>,
<26 512 0 4000000>, <89 604 0 3000000>,
+ <26 512 0 2200000>, <89 604 0 4500000>,
<26 512 0 4000000>, <89 604 0 4500000>,
<26 512 0 6400000>, <89 604 0 4500000>,
+ <26 512 0 4000000>, <89 604 0 7600000>,
<26 512 0 6400000>, <89 604 0 7600000>;
/* GDSC oxili regulators */
@@ -67,40 +69,26 @@
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <450000000>;
- qcom,bus-freq = <5>;
+ qcom,bus-freq = <8>;
qcom,io-fraction = <33>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <320000000>;
- qcom,bus-freq = <4>;
+ qcom,bus-freq = <5>;
qcom,io-fraction = <66>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
- qcom,gpu-freq = <320000000>;
- qcom,bus-freq = <3>;
- qcom,io-fraction = <66>;
- };
-
- qcom,gpu-pwrlevel@3 {
- reg = <3>;
qcom,gpu-freq = <200000000>;
qcom,bus-freq = <2>;
qcom,io-fraction = <100>;
};
- qcom,gpu-pwrlevel@4 {
- reg = <4>;
- qcom,gpu-freq = <200000000>;
- qcom,bus-freq = <1>;
- qcom,io-fraction = <100>;
- };
-
- qcom,gpu-pwrlevel@5 {
- reg = <5>;
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
qcom,gpu-freq = <27000000>;
qcom,bus-freq = <0>;
qcom,io-fraction = <0>;
diff --git a/arch/arm/boot/dts/msm8974-ion.dtsi b/arch/arm/boot/dts/msm8974-ion.dtsi
index 5829f05..6ecb7d3 100644
--- a/arch/arm/boot/dts/msm8974-ion.dtsi
+++ b/arch/arm/boot/dts/msm8974-ion.dtsi
@@ -32,6 +32,7 @@
qcom,heap-align = <0x1000>;
linux,contiguous-region = <&secure_mem>;
qcom,ion-heap-type = "SECURE_DMA";
+ qcom,default-prefetch-size = <0x6c00000>;
};
qcom,ion-heap@22 { /* adsp heap */
diff --git a/arch/arm/boot/dts/msm8974-liquid.dtsi b/arch/arm/boot/dts/msm8974-liquid.dtsi
index ba085a0..922e3e0 100644
--- a/arch/arm/boot/dts/msm8974-liquid.dtsi
+++ b/arch/arm/boot/dts/msm8974-liquid.dtsi
@@ -30,6 +30,11 @@
qcom,panel-pwm-period = <53>;
};
+ qcom,mdss_edp@fd923400 {
+ status = "ok";
+ qcom,cont-splash-enabled;
+ };
+
i2c@f9967000 {
battery@b {
compatible = "ti,bq28400-battery";
diff --git a/arch/arm/boot/dts/msm8974-mdss.dtsi b/arch/arm/boot/dts/msm8974-mdss.dtsi
index c866de7..e409c94 100644
--- a/arch/arm/boot/dts/msm8974-mdss.dtsi
+++ b/arch/arm/boot/dts/msm8974-mdss.dtsi
@@ -19,6 +19,8 @@
interrupts = <0 72 0>;
vdd-supply = <&gdsc_mdss>;
+ qcom,max-bandwidth-low-kbps = <2300000>;
+ qcom,max-bandwidth-high-kbps = <3000000>;
qcom,max-clk-rate = <320000000>;
qcom,mdss-pipe-vig-off = <0x00001200 0x00001600
0x00001A00>;
diff --git a/arch/arm/boot/dts/msm8974-v2-pm.dtsi b/arch/arm/boot/dts/msm8974-v2-pm.dtsi
index eba053f..e2d40f7 100644
--- a/arch/arm/boot/dts/msm8974-v2-pm.dtsi
+++ b/arch/arm/boot/dts/msm8974-v2-pm.dtsi
@@ -130,68 +130,65 @@
compatible = "qcom,lpm-levels";
qcom,default-l2-state = "l2_cache_retention";
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
- qcom,lpm-level@0 {
- reg = <0x0>;
- qcom,mode = "wfi";
- qcom,l2 = "l2_cache_retention";
- qcom,latency-us = <1>;
- qcom,ss-power = <715>;
- qcom,energy-overhead = <17700>;
- qcom,time-overhead = <2>;
+ qcom,cpu-modes {
+ compatible = "qcom,cpu-modes";
+ qcom,cpu-mode@0 {
+ qcom,mode = "wfi";
+ qcom,latency-us = <1>;
+ qcom,ss-power = <715>;
+ qcom,energy-overhead = <17700>;
+ qcom,time-overhead = <2>;
+ };
+
+ qcom,cpu-mode@1 {
+ qcom,mode = "retention";
+ qcom,latency-us = <35>;
+ qcom,ss-power = <542>;
+ qcom,energy-overhead = <34920>;
+ qcom,time-overhead = <40>;
+ };
+
+ qcom,cpu-mode@2 {
+ qcom,mode = "standalone_pc";
+ qcom,latency-us = <300>;
+ qcom,ss-power = <476>;
+ qcom,energy-overhead = <225300>;
+ qcom,time-overhead = <350>;
+ };
+
+ qcom,cpu-mode@3 {
+ qcom,mode = "pc";
+ qcom,latency-us = <500>;
+ qcom,ss-power = <400>;
+ qcom,energy-overhead = <280000>;
+ qcom,time-overhead = <500>;
+ };
+
};
+ qcom,system-modes {
+ compatible = "qcom,system-modes";
- qcom,lpm-level@1 {
- reg = <0x1>;
- qcom,mode = "retention";
- qcom,l2 = "l2_cache_retention";
- qcom,latency-us = <35>;
- qcom,ss-power = <542>;
- qcom,energy-overhead = <34920>;
- qcom,time-overhead = <40>;
- };
+ qcom,system-mode@0 {
+ qcom,l2 = "l2_cache_gdhs";
+ qcom,latency-us = <20000>;
+ qcom,ss-power = <163>;
+ qcom,energy-overhead = <1577736>;
+ qcom,time-overhead = <5067>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
-
- qcom,lpm-level@2 {
- reg = <0x2>;
- qcom,mode = "standalone_pc";
- qcom,l2 = "l2_cache_retention";
- qcom,latency-us = <300>;
- qcom,ss-power = <476>;
- qcom,energy-overhead = <225300>;
- qcom,time-overhead = <350>;
- };
-
- qcom,lpm-level@3 {
- reg = <0x3>;
- qcom,mode = "standalone_pc";
- qcom,l2 = "l2_cache_gdhs";
- qcom,latency-us = <320>;
- qcom,ss-power = <476>;
- qcom,energy-overhead = <225300>;
- qcom,time-overhead = <375>;
- };
-
- qcom,lpm-level@4 {
- reg = <0x4>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_gdhs";
- qcom,gpio-detectable;
- qcom,latency-us = <20000>;
- qcom,ss-power = <163>;
- qcom,energy-overhead = <1577736>;
- qcom,time-overhead = <5067>;
- };
-
- qcom,lpm-level@5 {
- reg = <0x5>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc";
- qcom,latency-us = <30000>;
- qcom,ss-power = <83>;
- qcom,energy-overhead = <2274420>;
- qcom,time-overhead = <6605>;
+ qcom,system-mode@1 {
+ qcom,l2 = "l2_cache_pc";
+ qcom,latency-us = <30000>;
+ qcom,ss-power = <83>;
+ qcom,energy-overhead = <2274420>;
+ qcom,time-overhead = <6605>;
+ qcom,min-cpu-mode = "pc";
+ qcom,sync-cpus;
+ };
};
};
diff --git a/arch/arm/boot/dts/msm8974-v2.2.dtsi b/arch/arm/boot/dts/msm8974-v2.2.dtsi
index 0ca021b..3ed5720 100644
--- a/arch/arm/boot/dts/msm8974-v2.2.dtsi
+++ b/arch/arm/boot/dts/msm8974-v2.2.dtsi
@@ -23,20 +23,26 @@
/* Updated chip ID */
qcom,chipid = <0x03030001>;
- qcom,initial-pwrlevel = <4>;
+ qcom,initial-pwrlevel = <2>;
/* Updated bus bandwidth requirements */
qcom,msm-bus,vectors-KBps =
/* Off */
<26 512 0 0>, <89 604 0 0>,
+ /* Sub-SVS / SVS */
+ <26 512 0 1600000>, <89 604 0 3000000>,
/* SVS */
<26 512 0 2400000>, <89 604 0 3000000>,
/* Nominal / SVS */
<26 512 0 4656000>, <89 604 0 3000000>,
+ /* SVS / Nominal */
+ <26 512 0 2400000>, <89 604 0 5120000>,
/* Nominal */
<26 512 0 4656000>, <89 604 0 5120000>,
/* Turbo / Nominal */
<26 512 0 7464000>, <89 604 0 5120000>,
+ /* Nominal / Turbo */
+ <26 512 0 4656000>, <89 604 0 6400000>,
/* Turbo */
<26 512 0 7464000>, <89 604 0 6400000>;
@@ -49,54 +55,33 @@
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <450000000>;
- qcom,bus-freq = <5>;
+ qcom,bus-freq = <8>;
qcom,io-fraction = <33>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <389000000>;
- qcom,bus-freq = <4>;
+ qcom,bus-freq = <5>;
qcom,io-fraction = <33>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
- qcom,gpu-freq = <389000000>;
- qcom,bus-freq = <3>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <5>;
qcom,io-fraction = <66>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
- qcom,gpu-freq = <320000000>;
- qcom,bus-freq = <4>;
- qcom,io-fraction = <66>;
- };
-
- qcom,gpu-pwrlevel@4 {
- reg = <4>;
- qcom,gpu-freq = <320000000>;
- qcom,bus-freq = <3>;
- qcom,io-fraction = <66>;
- };
-
- qcom,gpu-pwrlevel@5 {
- reg = <5>;
qcom,gpu-freq = <200000000>;
qcom,bus-freq = <2>;
qcom,io-fraction = <100>;
};
- qcom,gpu-pwrlevel@6 {
- reg = <6>;
- qcom,gpu-freq = <200000000>;
- qcom,bus-freq = <1>;
- qcom,io-fraction = <100>;
- };
-
- qcom,gpu-pwrlevel@7 {
- reg = <7>;
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
qcom,gpu-freq = <27000000>;
qcom,bus-freq = <0>;
qcom,io-fraction = <0>;
diff --git a/arch/arm/boot/dts/msm8974-v2.dtsi b/arch/arm/boot/dts/msm8974-v2.dtsi
index 0da5658..9176117 100644
--- a/arch/arm/boot/dts/msm8974-v2.dtsi
+++ b/arch/arm/boot/dts/msm8974-v2.dtsi
@@ -58,14 +58,20 @@
qcom,msm-bus,vectors-KBps =
/* Off */
<26 512 0 0>, <89 604 0 0>,
+ /* Sub-SVS / SVS */
+ <26 512 0 1600000>, <89 604 0 3000000>,
/* SVS */
<26 512 0 2400000>, <89 604 0 3000000>,
/* Nominal / SVS */
- <26 512 0 4656000>, <89 604 0 3000000>,
+ <26 512 0 4912000>, <89 604 0 3000000>,
+ /* SVS / Nominal */
+ <26 512 0 2400000>, <89 604 0 5120000>,
/* Nominal */
- <26 512 0 4656000>, <89 604 0 5120000>,
+ <26 512 0 4912000>, <89 604 0 5120000>,
/* Turbo / Nominal */
<26 512 0 7464000>, <89 604 0 5120000>,
+ /* Nominal / Turbo */
+ <26 512 0 4912000>, <89 604 0 6400000>,
/* Turbo */
<26 512 0 7464000>, <89 604 0 6400000>;
};
@@ -81,6 +87,7 @@
qcom,mdss-has-bwc;
qcom,mdss-has-decimation;
qcom,mdss-ad-off = <0x0013100 0x00013300>;
+ vdd-cx-supply = <&pm8841_s2_corner>;
};
&mdss_hdmi_tx {
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 0412c73..b4a3e55 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -100,6 +100,7 @@
/include/ "msm8974-mdss.dtsi"
/include/ "msm8974-smp2p.dtsi"
/include/ "msm8974-bus.dtsi"
+/include/ "msm-rdbg.dtsi"
&soc {
#address-cells = <1>;
@@ -1683,6 +1684,10 @@
compatible = "qcom,msm-lsm-client";
};
+ qti,msm-pcm-loopback {
+ compatible = "qti,msm-pcm-loopback";
+ };
+
qcom,msm-dai-q6 {
compatible = "qcom,msm-dai-q6";
qcom,msm-dai-q6-sb-0-rx {
@@ -1985,14 +1990,15 @@
qcom,disk-encrypt-pipe-pair = <2>;
qcom,hlos-ce-hw-instance = <1>;
qcom,qsee-ce-hw-instance = <0>;
+ qcom,support-bus-scaling = <1>;
qcom,msm-bus,name = "qseecom-noc";
qcom,msm-bus,num-cases = <4>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
- <55 512 3936000 393600>,
- <55 512 3936000 393600>,
- <55 512 3936000 393600>;
+ <55 512 0 0>,
+ <55 512 120000 1200000>,
+ <55 512 393600 3936000>;
};
qcom,wdt@f9017000 {
@@ -2177,6 +2183,10 @@
qcom,hotplug-temp-hysteresis = <20>;
qcom,cpu-sensors = "tsens_tz_sensor5", "tsens_tz_sensor6",
"tsens_tz_sensor7", "tsens_tz_sensor8";
+ qcom,freq-mitigation-temp = <110>;
+ qcom,freq-mitigation-temp-hysteresis = <20>;
+ qcom,freq-mitigation-value = <960000>;
+ qcom,freq-mitigation-control-mask = <0x01>;
qcom,vdd-restriction-temp = <5>;
qcom,vdd-restriction-temp-hysteresis = <10>;
qcom,pmic-sw-mode-temp = <85>;
diff --git a/arch/arm/boot/dts/msm8974pro-pm.dtsi b/arch/arm/boot/dts/msm8974pro-pm.dtsi
index 5769446..938a2cc 100644
--- a/arch/arm/boot/dts/msm8974pro-pm.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-pm.dtsi
@@ -128,60 +128,69 @@
qcom,lpm-levels {
compatible = "qcom,lpm-levels";
+ qcom,allow-synced-levels;
qcom,default-l2-state = "l2_cache_retention";
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
- qcom,lpm-level@0 {
- reg = <0x0>;
- qcom,mode = "wfi";
- qcom,l2 = "l2_cache_retention";
- qcom,latency-us = <1>;
- qcom,ss-power = <715>;
- qcom,energy-overhead = <17700>;
- qcom,time-overhead = <2>;
+ qcom,cpu-modes {
+ compatible = "qcom,cpu-modes";
+ qcom,cpu-mode@0 {
+ qcom,mode = "wfi";
+ qcom,latency-us = <1>;
+ qcom,ss-power = <715>;
+ qcom,energy-overhead = <17700>;
+ qcom,time-overhead = <2>;
+ };
+
+ qcom,cpu-mode@1 {
+ qcom,mode = "retention";
+ qcom,latency-us = <35>;
+ qcom,ss-power = <542>;
+ qcom,energy-overhead = <34920>;
+ qcom,time-overhead = <40>;
+ };
+
+ qcom,cpu-mode@2 {
+ qcom,mode = "standalone_pc";
+ qcom,latency-us = <300>;
+ qcom,ss-power = <476>;
+ qcom,energy-overhead = <225300>;
+ qcom,time-overhead = <350>;
+ };
+
+ qcom,cpu-mode@3 {
+ qcom,mode = "pc";
+ qcom,latency-us = <500>;
+ qcom,ss-power = <400>;
+ qcom,energy-overhead = <280000>;
+ qcom,time-overhead = <500>;
+ qcom,use-broadcast-timer;
+ };
+
};
+ qcom,system-modes {
+ compatible = "qcom,system-modes";
- qcom,lpm-level@1 {
- reg = <0x1>;
- qcom,mode = "retention";
- qcom,l2 = "l2_cache_retention";
- qcom,latency-us = <35>;
- qcom,ss-power = <542>;
- qcom,energy-overhead = <34920>;
- qcom,time-overhead = <40>;
- };
+ qcom,system-mode@0 {
+ qcom,l2 = "l2_cache_gdhs";
+ qcom,latency-us = <20000>;
+ qcom,ss-power = <163>;
+ qcom,energy-overhead = <1577736>;
+ qcom,time-overhead = <5067>;
+ qcom,min-cpu-mode= "pc";
+ qcom,sync-cpus;
+ };
-
- qcom,lpm-level@2 {
- reg = <0x2>;
- qcom,mode = "standalone_pc";
- qcom,l2 = "l2_cache_retention";
- qcom,latency-us = <300>;
- qcom,ss-power = <476>;
- qcom,energy-overhead = <225300>;
- qcom,time-overhead = <350>;
- };
-
- qcom,lpm-level@3 {
- reg = <0x3>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_gdhs";
- qcom,gpio-detectable;
- qcom,latency-us = <20000>;
- qcom,ss-power = <163>;
- qcom,energy-overhead = <1577736>;
- qcom,time-overhead = <5067>;
- };
-
- qcom,lpm-level@4 {
- reg = <0x4>;
- qcom,mode = "pc";
- qcom,l2 = "l2_cache_pc";
- qcom,latency-us = <30000>;
- qcom,ss-power = <83>;
- qcom,energy-overhead = <2274420>;
- qcom,time-overhead = <6605>;
+ qcom,system-mode@1 {
+ qcom,l2 = "l2_cache_pc";
+ qcom,latency-us = <30000>;
+ qcom,ss-power = <83>;
+ qcom,energy-overhead = <2274420>;
+ qcom,time-overhead = <6605>;
+ qcom,min-cpu-mode = "pc";
+ qcom,sync-cpus;
+ };
};
};
@@ -205,6 +214,7 @@
<50 172>, /* usb1_hs_async_wakeup_irq */
<53 104>, /* mdss_irq */
<62 222>, /* ee0_krait_hlos_spmi_periph_irq */
+ <0xff 33>, /*l2_perf_mon*/
<0xff 34>, /* APCC_qgicL2ErrorIrptReq */
<0xff 35>, /* WDT_barkInt */
<0xff 40>, /* qtimer_phy_irq */
@@ -313,7 +323,6 @@
ranges;
reg = <0xfe805664 0x40>;
qcom,pc-mode = "tz_l2_int";
- qcom,use-sync-timer;
qcom,cpus-as-clocks;
qcom,pm-snoc-client {
diff --git a/arch/arm/boot/dts/msm8974pro-pma8084-mtp.dtsi b/arch/arm/boot/dts/msm8974pro-pma8084-mtp.dtsi
old mode 100644
new mode 100755
index d5c1143..a22d806
--- a/arch/arm/boot/dts/msm8974pro-pma8084-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-pma8084-mtp.dtsi
@@ -63,6 +63,20 @@
};
};
+ i2c@f9928000 { /* BLSP1 QUP6 */
+ nfc-nci@e {
+ compatible = "qcom,nfc-nci";
+ reg = <0x0e>;
+ qcom,irq-gpio = <&msmgpio 59 0x00>;
+ qcom,dis-gpio = <&pma8084_mpps 7 0>;
+ qcom,clk-src = "BBCLK2";
+ qcom,clk-en-gpio = <&msmgpio 0 0x00>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <59 0>;
+ qcom,clk-gpio = <&pma8084_gpios 10 0>;
+ };
+ };
+
qcom,ssusb@f9200000 {
vbus_dwc3-supply = <&pm8941_mvs1>;
};
@@ -173,9 +187,11 @@
};
gpio@c900 { /* GPIO 10 */
- /* NFC clock request */
- qcom,mode = <0>; /* Digital input */
- qcom,pull = <4>; /* Pull down */
+ /* NFC clk request */
+ qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */
+ qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
+ qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
+ qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */
qcom,master-en = <1>;
};
@@ -188,10 +204,11 @@
};
gpio@cb00 { /* GPIO 12 */
- /* Unused */
- qcom,mode = <1>; /* Digital output */
- qcom,out-strength = <1>; /* Low */
- qcom,src-sel = <2>; /* Function 1 */
+ /* NFC clk request */
+ qcom,mode = <0>; /* QPNP_PIN_MODE_DIG_IN */
+ qcom,pull = <5>; /* QPNP_PIN_PULL_NO */
+ qcom,vin-sel = <2>; /* QPNP_PIN_VIN2 */
+ qcom,src-sel = <2>; /* QPNP_PIN_SEL_FUNC_1 */
qcom,master-en = <1>;
};
diff --git a/arch/arm/boot/dts/msm8974pro-pma8084.dtsi b/arch/arm/boot/dts/msm8974pro-pma8084.dtsi
index 2693642..8b13387 100644
--- a/arch/arm/boot/dts/msm8974pro-pma8084.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-pma8084.dtsi
@@ -152,6 +152,9 @@
qcom,msm-thermal {
vdd-dig-supply = <&pma8084_s2_floor_corner>;
vdd-gfx-supply = <&pma8084_s7_floor_corner>;
+ qti,pmic-opt-curr-temp = <85>;
+ qti,pmic-opt-curr-temp-hysteresis = <10>;
+ qti,pmic-opt-curr-regs = "vdd-dig";
/delete-property/ qcom,pmic-sw-mode-temp;
/delete-property/ qcom,pmic-sw-mode-temp-hysteresis;
/delete-property/ qcom,pmic-sw-mode-regs;
diff --git a/arch/arm/boot/dts/msm8974pro.dtsi b/arch/arm/boot/dts/msm8974pro.dtsi
old mode 100644
new mode 100755
index 6b53562..41f02fe
--- a/arch/arm/boot/dts/msm8974pro.dtsi
+++ b/arch/arm/boot/dts/msm8974pro.dtsi
@@ -1566,37 +1566,63 @@
< 2265600 1728000 300 /* 37.5 MHz */ >,
< 2496000 1728000 300 /* 37.5 MHz */ >;
};
+
+ i2c@f9928000 { /* BLSP-1 QUP-6 */
+ cell-index = <3>;
+ compatible = "qcom,i2c-qup";
+ reg = <0xf9928000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ interrupts = <0 100 0>;
+ interrupt-names = "qup_err_intr";
+ qcom,i2c-bus-freq = <400000>;
+ qcom,i2c-src-freq = <19200000>;
+ qcom,sda-gpio = <&msmgpio 29 0>;
+ qcom,scl-gpio = <&msmgpio 30 0>;
+ qcom,master-id = <86>;
+ };
};
/* GPU overrides */
&msm_gpu {
/* Updated chip ID */
qcom,chipid = <0x03030002>;
+ qcom,msm-bus,num-cases = <15>;
+ qcom,bus-control;
+ qcom,initial-pwrlevel = <3>;
- qcom,initial-pwrlevel = <6>;
-
- qcom,msm-bus,num-cases = <10>;
/* Updated bus bandwidth requirements */
qcom,msm-bus,vectors-KBps =
/* Off */
<26 512 0 0>, <89 604 0 0>,
+ /* Sub-SVS / SVS */
+ <26 512 0 1600000>, <89 604 0 3200000>,
/* SVS */
- <26 512 0 2400000>, <89 604 0 3200000>,
- /* Nominal / SVS */
+ <26 512 0 2456000>, <89 604 0 3200000>,
+ /* low Nominal / SVS */
<26 512 0 3680000>, <89 604 0 3200000>,
- /* Nominal / Nominal */
+ /* SVS / low Nominal */
+ <26 512 0 2456000>, <89 604 0 5280000>,
+ /* low Nominal / low Nominal */
<26 512 0 3680000>, <89 604 0 5280000>,
- /* Nominal / Nominal */
+ /* Nominal / low Nominal */
<26 512 0 4912000>, <89 604 0 5280000>,
- /* Nominal / Turbo */
+ /* low Nominal / Nominal */
+ <26 512 0 3680000>, <89 604 0 6224000>,
+ /* Nominal / Nominal */
<26 512 0 4912000>, <89 604 0 6224000>,
- /* Turbo / Turbo */
- <26 512 0 7464000>, <89 604 0 6224000>,
+ /* low Turbo / Nominal */
+ <26 512 0 6400000>, <89 604 0 6224000>,
+ /* Nominal / low Turbo */
+ <26 512 0 4912000>, <89 604 0 7398000>,
+ /* low Turbo / low Turbo */
+ <26 512 0 6400000>, <89 604 0 7398000>,
+ /* Turbo / low Turbo */
+ <26 512 0 7464000>, <89 604 0 7398000>,
/* Nominal / Turbo */
- <26 512 0 4912000>, <89 604 0 7400000>,
- /* Turbo */
- <26 512 0 7464000>, <89 604 0 7400000>,
- /* Turbo */
+ <26 512 0 4912000>, <89 604 0 9248000>,
+ /* Turbo / Turbo */
<26 512 0 7464000>, <89 604 0 9248000>;
qcom,gpu-pwrlevels {
@@ -1608,68 +1634,40 @@
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <578000000>;
- qcom,bus-freq = <9>;
+ qcom,bus-freq = <14>;
qcom,io-fraction = <33>;
};
- qcom,gpu-pwrlevel@1 {
- reg = <1>;
- qcom,gpu-freq = <462400000>;
- qcom,bus-freq = <8>;
- qcom,io-fraction = <33>;
- };
-
- qcom,gpu-pwrlevel@2 {
- reg = <2>;
- qcom,gpu-freq = <462400000>;
- qcom,bus-freq = <7>;
- qcom,io-fraction = <66>;
- };
-
- qcom,gpu-pwrlevel@3 {
- reg = <3>;
- qcom,gpu-freq = <389000000>;
- qcom,bus-freq = <6>;
- qcom,io-fraction = <66>;
- };
-
- qcom,gpu-pwrlevel@4 {
- reg = <4>;
- qcom,gpu-freq = <389000000>;
- qcom,bus-freq = <5>;
- qcom,io-fraction = <66>;
- };
-
- qcom,gpu-pwrlevel@5 {
- reg = <5>;
- qcom,gpu-freq = <330000000>;
- qcom,bus-freq = <4>;
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <462400000>;
+ qcom,bus-freq = <11>;
qcom,io-fraction = <66>;
};
- qcom,gpu-pwrlevel@6 {
- reg = <6>;
- qcom,gpu-freq = <330000000>;
- qcom,bus-freq = <3>;
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <389000000>;
+ qcom,bus-freq = <8>;
qcom,io-fraction = <66>;
};
- qcom,gpu-pwrlevel@7 {
- reg = <7>;
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <5>;
+ qcom,io-fraction = <100>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
qcom,gpu-freq = <200000000>;
qcom,bus-freq = <2>;
qcom,io-fraction = <100>;
};
- qcom,gpu-pwrlevel@8 {
- reg = <8>;
- qcom,gpu-freq = <200000000>;
- qcom,bus-freq = <1>;
- qcom,io-fraction = <100>;
- };
-
- qcom,gpu-pwrlevel@9 {
- reg = <9>;
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
qcom,gpu-freq = <27000000>;
qcom,bus-freq = <0>;
qcom,io-fraction = <0>;
diff --git a/arch/arm/configs/apq8084_defconfig b/arch/arm/configs/apq8084_defconfig
index cda1e59..968a5ee 100644
--- a/arch/arm/configs/apq8084_defconfig
+++ b/arch/arm/configs/apq8084_defconfig
@@ -378,6 +378,7 @@
CONFIG_MAGIC_SYSRQ=y
CONFIG_LOCKUP_DETECTOR=y
# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_KMEMLEAK=y
diff --git a/arch/arm/configs/msm8226-perf_defconfig b/arch/arm/configs/msm8226-perf_defconfig
index dac2286..2a82d5b 100644
--- a/arch/arm/configs/msm8226-perf_defconfig
+++ b/arch/arm/configs/msm8226-perf_defconfig
@@ -270,6 +270,7 @@
CONFIG_DIAG_CHAR=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MSM=y
+CONFIG_MSM_ADSPRPC=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_QUP=y
@@ -428,6 +429,7 @@
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_INFO=y
@@ -455,4 +457,4 @@
CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y
CONFIG_TOUCHSCREEN_GT9XX=y
CONFIG_GT9XX_TOUCHPANEL_DRIVER=y
-CONFIG_DEFAULT_ROW=y
+CONFIG_MSM_RDBG=m
diff --git a/arch/arm/configs/msm8226_defconfig b/arch/arm/configs/msm8226_defconfig
index 9d4d37b..cedb6dc 100644
--- a/arch/arm/configs/msm8226_defconfig
+++ b/arch/arm/configs/msm8226_defconfig
@@ -271,6 +271,7 @@
CONFIG_DIAG_CHAR=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MSM=y
+CONFIG_MSM_ADSPRPC=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_QUP=y
@@ -467,6 +468,7 @@
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_KMEMLEAK=y
@@ -509,4 +511,4 @@
CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y
CONFIG_TOUCHSCREEN_GT9XX=y
CONFIG_GT9XX_TOUCHPANEL_DRIVER=y
-CONFIG_DEFAULT_ROW=y
+CONFIG_MSM_RDBG=m
diff --git a/arch/arm/configs/msm8610-perf_defconfig b/arch/arm/configs/msm8610-perf_defconfig
index 0d443a6..76c0f6a 100644
--- a/arch/arm/configs/msm8610-perf_defconfig
+++ b/arch/arm/configs/msm8610-perf_defconfig
@@ -80,7 +80,9 @@
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_COMPACTION=y
+CONFIG_KSM=y
CONFIG_CC_STACKPROTECTOR=y
+CONFIG_KSM=y
CONFIG_ENABLE_VMALLOC_SAVING=y
CONFIG_CP_ACCESS=y
CONFIG_USE_OF=y
@@ -211,6 +213,7 @@
CONFIG_CFG80211=y
CONFIG_NL80211_TESTMODE=y
CONFIG_CMA=y
+CONFIG_CMA_SIZE_MBYTES=4
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_QSEECOM=y
@@ -246,6 +249,7 @@
CONFIG_DIAG_CHAR=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MSM=y
+CONFIG_MSM_ADSPRPC=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_QUP=y
@@ -316,6 +320,7 @@
CONFIG_FB_MSM=y
# CONFIG_FB_MSM_BACKLIGHT is not set
CONFIG_FB_MSM_MDSS=y
+CONFIG_FB_MSM_MDSS_MDP3=y
CONFIG_FB_MSM_MDSS_WRITEBACK=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
@@ -374,6 +379,7 @@
CONFIG_QPNP_VIBRATOR=y
CONFIG_QPNP_REVID=y
CONFIG_MSM_IOMMU_V0=y
+CONFIG_SENSORS=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
@@ -388,6 +394,7 @@
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_INFO=y
@@ -423,3 +430,4 @@
CONFIG_LOGCAT_SIZE=64
CONFIG_SENSORS_CAPELLA_CM36283=y
CONFIG_NFC_QNCI=y
+CONFIG_MSM_RDBG=m
diff --git a/arch/arm/configs/msm8610_defconfig b/arch/arm/configs/msm8610_defconfig
index f467b95..ff0c498 100644
--- a/arch/arm/configs/msm8610_defconfig
+++ b/arch/arm/configs/msm8610_defconfig
@@ -81,7 +81,9 @@
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_COMPACTION=y
+CONFIG_KSM=y
CONFIG_CC_STACKPROTECTOR=y
+CONFIG_KSM=y
CONFIG_ENABLE_VMALLOC_SAVING=y
CONFIG_CP_ACCESS=y
CONFIG_USE_OF=y
@@ -213,6 +215,7 @@
CONFIG_CFG80211_INTERNAL_REGDB=y
CONFIG_NL80211_TESTMODE=y
CONFIG_CMA=y
+CONFIG_CMA_SIZE_MBYTES=4
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_QSEECOM=y
@@ -248,6 +251,7 @@
CONFIG_DIAG_CHAR=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MSM=y
+CONFIG_MSM_ADSPRPC=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_QUP=y
@@ -339,6 +343,7 @@
CONFIG_FB_MSM=y
# CONFIG_FB_MSM_BACKLIGHT is not set
CONFIG_FB_MSM_MDSS=y
+CONFIG_FB_MSM_MDSS_MDP3=y
CONFIG_FB_MSM_MDSS_WRITEBACK=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
@@ -412,6 +417,7 @@
CONFIG_CORESIGHT_WCN_ETM=y
CONFIG_CORESIGHT_RPM_ETM=y
CONFIG_CORESIGHT_EVENT=m
+CONFIG_SENSORS=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
@@ -426,6 +432,7 @@
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_KMEMLEAK=y
@@ -476,3 +483,4 @@
CONFIG_SENSORS_STK3X1X=y
CONFIG_SENSORS_MMA8X5X=y
CONFIG_SENSORS_CAPELLA_CM36283=y
+CONFIG_MSM_RDBG=m
diff --git a/arch/arm/configs/msm8974-perf_defconfig b/arch/arm/configs/msm8974-perf_defconfig
old mode 100644
new mode 100755
index 83920bd..4132e44
--- a/arch/arm/configs/msm8974-perf_defconfig
+++ b/arch/arm/configs/msm8974-perf_defconfig
@@ -98,12 +98,14 @@
CONFIG_CC_STACKPROTECTOR=y
CONFIG_CP_ACCESS=y
CONFIG_USE_OF=y
+CONFIG_SECURE_TOUCH=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_BOOST=y
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
@@ -298,6 +300,7 @@
CONFIG_DIAG_CHAR=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MSM=y
+CONFIG_MSM_ADSPRPC=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_QUP=y
@@ -474,6 +477,7 @@
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set
@@ -494,8 +498,10 @@
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_TWOFISH=y
+CONFIG_NFC_QNCI=y
CONFIG_CRYPTO_DEV_QCRYPTO=m
CONFIG_CRYPTO_DEV_QCE=y
CONFIG_CRYPTO_DEV_QCEDEV=y
CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=y
CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y
+CONFIG_MSM_RDBG=m
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
old mode 100644
new mode 100755
index 47347c4..0b9ba76
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -104,12 +104,14 @@
CONFIG_CC_STACKPROTECTOR=y
CONFIG_CP_ACCESS=y
CONFIG_USE_OF=y
+CONFIG_SECURE_TOUCH=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_BOOST=y
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
@@ -306,6 +308,7 @@
CONFIG_DIAG_CHAR=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_MSM=y
+CONFIG_MSM_ADSPRPC=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_QUP=y
@@ -500,6 +503,7 @@
CONFIG_MAGIC_SYSRQ=y
CONFIG_LOCKUP_DETECTOR=y
# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
CONFIG_DEBUG_KMEMLEAK=y
@@ -534,8 +538,10 @@
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_TWOFISH=y
+CONFIG_NFC_QNCI=y
CONFIG_CRYPTO_DEV_QCRYPTO=m
CONFIG_CRYPTO_DEV_QCE=y
CONFIG_CRYPTO_DEV_QCEDEV=y
CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=y
CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y
+CONFIG_MSM_RDBG=m
diff --git a/arch/arm/configs/msmkrypton_defconfig b/arch/arm/configs/msmkrypton_defconfig
index b04acb5..380a730 100644
--- a/arch/arm/configs/msmkrypton_defconfig
+++ b/arch/arm/configs/msmkrypton_defconfig
@@ -133,6 +133,7 @@
CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SYSRQ_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 9ba1436..0e8f4916 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -49,6 +49,13 @@
*
* Unconditionally clean and invalidate the entire cache.
*
+ * flush_kern_louis()
+ *
+ * Flush data cache levels up to the level of unification
+ * inner shareable and invalidate the I-cache.
+ * Only needed from v7 onwards, falls back to flush_cache_all()
+ * for all other processor versions.
+ *
* flush_user_all()
*
* Clean and invalidate all user space cache entries
@@ -112,6 +119,7 @@
struct cpu_cache_fns {
void (*flush_icache_all)(void);
void (*flush_kern_all)(void);
+ void (*flush_kern_louis)(void);
void (*flush_user_all)(void);
void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
@@ -136,6 +144,7 @@
#define __cpuc_flush_icache_all cpu_cache.flush_icache_all
#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
+#define __cpuc_flush_kern_louis cpu_cache.flush_kern_louis
#define __cpuc_flush_user_all cpu_cache.flush_user_all
#define __cpuc_flush_user_range cpu_cache.flush_user_range
#define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
@@ -158,6 +167,7 @@
extern void __cpuc_flush_icache_all(void);
extern void __cpuc_flush_kern_all(void);
+extern void __cpuc_flush_kern_louis(void);
extern void __cpuc_flush_user_all(void);
extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
@@ -225,6 +235,11 @@
__flush_icache_preferred();
}
+/*
+ * Flush caches up to Level of Unification Inner Shareable
+ */
+#define flush_cache_louis() __cpuc_flush_kern_louis()
+
#define flush_cache_all() __cpuc_flush_kern_all()
static inline void vivt_flush_cache_mm(struct mm_struct *mm)
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index 7e30874..2d6a7de 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -132,6 +132,7 @@
#ifndef MULTI_CACHE
#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
+#define __cpuc_flush_kern_louis __glue(_CACHE,_flush_kern_cache_louis)
#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index 92e4f18..8c0a923 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -480,7 +480,7 @@
if (!clk)
return -ENOMEM;
- clk->features = CLOCK_EVT_FEAT_ONESHOT;
+ clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
clk->name = "arch_mem_timer";
clk->rating = 400;
clk->set_mode = arch_timer_set_mode_mem;
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index 1794cc3..358bca3 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -17,6 +17,8 @@
*/
void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
{
+ u32 *ctx = ptr;
+
*save_ptr = virt_to_phys(ptr);
/* This must correspond to the LDM in cpu_resume() assembly */
@@ -26,7 +28,20 @@
cpu_do_suspend(ptr);
- flush_cache_all();
+ flush_cache_louis();
+
+ /*
+ * flush_cache_louis does not guarantee that
+ * save_ptr and ptr are cleaned to main memory,
+ * just up to the Level of Unification Inner Shareable.
+ * Since the context pointer and context itself
+ * are to be retrieved with the MMU off that
+ * data must be cleaned from all cache levels
+ * to main memory using "area" cache primitives.
+ */
+ __cpuc_flush_dcache_area(ctx, ptrsz);
+ __cpuc_flush_dcache_area(save_ptr, sizeof(*save_ptr));
+
outer_clean_range(*save_ptr, *save_ptr + ptrsz);
outer_clean_range(virt_to_phys(save_ptr),
virt_to_phys(save_ptr) + sizeof(*save_ptr));
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index a341c23..4b8d443 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -266,7 +266,7 @@
select MSM_L2_SPM
select MSM_NATIVE_RESTART
select MSM_RESTART_V2
- select MSM_PM8X60 if PM
+ select MSM_PM if PM
select MAY_HAVE_SPARSE_IRQ
select SPARSE_IRQ
select MSM_RPM_SMD
@@ -297,7 +297,7 @@
select MULTI_IRQ_HANDLER
select MSM_NATIVE_RESTART
select MSM_RESTART_V2
- select MSM_PM8X60 if PM
+ select MSM_PM if PM
select MAY_HAVE_SPARSE_IRQ
select SPARSE_IRQ
select REGULATOR
@@ -308,7 +308,6 @@
select QMI_ENCDEC
select MSM_SPM_V2
select MSM_L2_SPM
- select MSM_PM8X60 if PM
select MSM_RPM_SMD
select ENABLE_VMALLOC_SAVINGS
@@ -428,13 +427,14 @@
select MSM_NATIVE_RESTART
select MSM_RESTART_V2
select MSM_SPM_V2
- select MSM_PM8X60 if PM
+ select MSM_PM if PM
select MULTI_IRQ_HANDLER
select GPIO_MSM_V3
select MAY_HAVE_SPARSE_IRQ
select SPARSE_IRQ
select MEMORY_HOLE_CARVEOUT
select QMI_ENCDEC
+ select MSM_CORTEX_A7
config ARCH_MSM8610
bool "MSM8610"
@@ -458,9 +458,10 @@
select MSM_RPM_SMD
select MSM_SPM_V2
select MSM_L2_SPM
- select MSM_PM8X60 if PM
+ select MSM_PM if PM
select MEMORY_HOLE_CARVEOUT
select MSM_BUS_SCALING
+ select MSM_CORTEX_A7
select CPU_FREQ_MSM
select CPU_FREQ
select MSM_PIL
@@ -498,9 +499,10 @@
select MSM_RPM_SMD
select MSM_SPM_V2
select MSM_L2_SPM
- select MSM_PM8X60 if PM
+ select MSM_PM if PM
select MEMORY_HOLE_CARVEOUT
select MSM_BUS_SCALING
+ select MSM_CORTEX_A7
select CPU_FREQ_MSM
select CPU_FREQ
select MSM_PIL
@@ -530,7 +532,7 @@
select MSM_L2_SPM
select MSM_NATIVE_RESTART
select MSM_RESTART_V2
- select MSM_PM8X60 if PM
+ select MSM_PM if PM
select MAY_HAVE_SPARSE_IRQ
select SPARSE_IRQ
select ARM_HAS_SG_CHAIN
@@ -573,6 +575,9 @@
bool
select ARM_L1_CACHE_SHIFT_6
+config MSM_CORTEX_A7
+ bool
+
config MSM_SMP
select HAVE_SMP
bool
@@ -655,7 +660,7 @@
config MSM_LPM_TEST
bool "Low Power Mode test framework"
depends on MSM_RPM || MSM_RPM_SMD
- depends on MSM_PM8X60
+ depends on MSM_PM
help
LPM_TEST is a test framework that assists in exercising the low
power mode algorithm on MSM targets. This test framework tracks
@@ -2431,7 +2436,7 @@
depends on PM
bool
-config MSM_PM8X60
+config MSM_PM
depends on PM
bool
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 3079b64..4e60414 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -23,11 +23,9 @@
endif
obj-y += acpuclock.o
+obj-$(CONFIG_MSM_CORTEX_A7) += clock-a7.o
obj-$(CONFIG_HW_PERF_EVENTS) += perf_trace_counters.o
-obj-$(CONFIG_ARCH_MSM_KRAIT) += acpuclock-krait.o clock-krait.o
-ifdef CONFIG_ARCH_MSM_KRAIT
-obj-$(CONFIG_DEBUG_FS) += acpuclock-krait-debug.o
-endif
+obj-$(CONFIG_ARCH_MSM_KRAIT) += clock-krait.o
obj-$(CONFIG_ARCH_MSM7X27) += acpuclock-7627.o acpuclock-8625q.o clock-pll.o
obj-$(CONFIG_ARCH_MSM_SCORPIONMP) += perf_event_msm_l2.o
ifndef CONFIG_OF
@@ -206,7 +204,7 @@
endif
obj-$(CONFIG_MSM_SYSMON_COMM) += sysmon.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
+#obj-$(CONFIG_CPU_IDLE) += cpuidle.o
ifdef CONFIG_MSM_CAMERA_V4L2
obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60-camera.o
@@ -257,12 +255,10 @@
obj-$(CONFIG_MACH_MSM7X25_FFA) += board-msm7x27.o devices-msm7x25.o
obj-$(CONFIG_ARCH_MSM8960) += clock-local.o clock-dss-8960.o clock-8960.o clock-rpm.o clock-pll.o
obj-$(CONFIG_ARCH_MSM8960) += footswitch-8x60.o
-obj-$(CONFIG_ARCH_MSM8960) += acpuclock-8960.o acpuclock-8960ab.o
obj-$(CONFIG_ARCH_MSM8960) += memory_topology.o
obj-$(CONFIG_ARCH_MSM8960) += saw-regulator.o
obj-$(CONFIG_ARCH_MSM8960) += devices-8960.o
obj-$(CONFIG_ARCH_APQ8064) += devices-8960.o devices-8064.o
-obj-$(CONFIG_ARCH_APQ8064) += acpuclock-8064.o
board-8960-all-objs += board-8960.o board-8960-camera.o board-8960-display.o board-8960-pmic.o board-8960-storage.o board-8960-gpiomux.o
board-8930-all-objs += board-8930.o board-8930-camera.o board-8930-display.o board-8930-pmic.o board-8930-storage.o board-8930-gpiomux.o devices-8930.o board-8930-gpu.o
board-8064-all-objs += board-8064.o board-8064-pmic.o board-8064-storage.o board-8064-gpiomux.o board-8064-camera.o board-8064-display.o board-8064-gpu.o
@@ -285,7 +281,7 @@
obj-$(CONFIG_ARCH_APQ8084) += board-8084.o board-8084-gpiomux.o
obj-$(CONFIG_ARCH_APQ8084) += clock-8084.o
obj-$(CONFIG_ARCH_MSM8974) += board-8974.o board-8974-gpiomux.o
-obj-$(CONFIG_ARCH_MSM8974) += acpuclock-8974.o clock-krait-8974.o
+obj-$(CONFIG_ARCH_MSM8974) += clock-krait-8974.o
obj-$(CONFIG_ARCH_MSM8974) += clock-local2.o clock-pll.o clock-8974.o clock-rpm.o clock-voter.o clock-mdss-8974.o
obj-$(CONFIG_ARCH_MSM8974) += gdsc.o
obj-$(CONFIG_ARCH_MSM9625) += gdsc.o
@@ -298,7 +294,6 @@
obj-$(CONFIG_ARCH_MSMSAMARIUM) += board-samarium.o board-samarium-gpiomux.o
obj-$(CONFIG_ARCH_MSM9625) += board-9625.o board-9625-gpiomux.o
obj-$(CONFIG_ARCH_MSM9625) += clock-local2.o clock-pll.o clock-9625.o clock-rpm.o clock-voter.o acpuclock-9625.o acpuclock-cortex.o
-obj-$(CONFIG_ARCH_MSM8930) += acpuclock-8930.o acpuclock-8627.o acpuclock-8930aa.o acpuclock-8930ab.o
obj-$(CONFIG_ARCH_MPQ8092) += board-8092.o board-8092-gpiomux.o
obj-$(CONFIG_ARCH_MPQ8092) += clock-8092.o
obj-$(CONFIG_ARCH_MSM8226) += board-8226.o board-8226-gpiomux.o
@@ -310,7 +305,7 @@
obj-$(CONFIG_ARCH_MSM8610) += clock-dsi-8610.o
obj-$(CONFIG_ARCH_MSMKRYPTON) += clock-local2.o clock-pll.o clock-krypton.o clock-rpm.o clock-voter.o
-obj-$(CONFIG_MSM_PM8X60) += pm-8x60.o pm-data.o
+obj-$(CONFIG_MSM_PM) += msm-pm.o pm-data.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire.o board-sapphire-gpio.o
obj-$(CONFIG_MACH_SAPPHIRE) += board-sapphire-keypad.o board-sapphire-panel.o
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
deleted file mode 100644
index 8262946..0000000
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ /dev/null
@@ -1,679 +0,0 @@
-/*
- * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/rpm-regulator.h>
-#include <mach/msm_bus_board.h>
-#include <mach/msm_bus.h>
-
-#include "mach/socinfo.h"
-#include "acpuclock.h"
-#include "acpuclock-krait.h"
-
-static struct hfpll_data hfpll_data __initdata = {
- .mode_offset = 0x00,
- .l_offset = 0x08,
- .m_offset = 0x0C,
- .n_offset = 0x10,
- .config_offset = 0x04,
- .config_val = 0x7845C665,
- .has_droop_ctl = true,
- .droop_offset = 0x14,
- .droop_val = 0x0108C000,
- .low_vdd_l_max = 22,
- .nom_vdd_l_max = 42,
- .vdd[HFPLL_VDD_NONE] = 0,
- .vdd[HFPLL_VDD_LOW] = 945000,
- .vdd[HFPLL_VDD_NOM] = 1050000,
- .vdd[HFPLL_VDD_HIGH] = 1150000,
-};
-
-static struct scalable scalable[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0x00903200,
- .aux_clk_sel_phys = 0x02088014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0x00903240,
- .aux_clk_sel_phys = 0x02098014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
- },
- [CPU2] = {
- .hfpll_phys_base = 0x00903280,
- .aux_clk_sel_phys = 0x020A8014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x6501,
- .vreg[VREG_CORE] = { "krait2", 1300000 },
- .vreg[VREG_MEM] = { "krait2_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait2_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 },
- },
- [CPU3] = {
- .hfpll_phys_base = 0x009032C0,
- .aux_clk_sel_phys = 0x020B8014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x7501,
- .vreg[VREG_CORE] = { "krait3", 1300000 },
- .vreg[VREG_MEM] = { "krait3_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait3_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0x00903300,
- .aux_clk_sel_phys = 0x02011028,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x0500,
- .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
- },
-};
-
-/*
- * The correct maximum rate for 8064ab in 600 MHZ.
- * We rely on the RPM rounding requests up here.
-*/
-static struct msm_bus_paths bw_level_tbl[] __initdata = {
- [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
- [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
- [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
- [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
- [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
- [5] = BW_MBPS(4264), /* At least 533 MHz on bus. */
-};
-
-static struct msm_bus_scale_pdata bus_scale_data __initdata = {
- .usecase = bw_level_tbl,
- .num_usecases = ARRAY_SIZE(bw_level_tbl),
- .active_only = 1,
- .name = "acpuclk-8064",
-};
-
-static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0x1A }, 1150000, 1150000, 4 },
- [7] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 },
- [11] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 5 },
- [12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
- [13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 },
- [14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
- { }
-};
-
-static struct acpu_level tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_nom[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 975000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 975000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1025000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1025000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1050000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1050000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1075000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1125000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1125000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1150000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1150000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1175000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1175000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 975000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1025000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1075000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1100000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1100000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1125000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_faster[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 962500 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 975000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1000000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1000000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1050000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1050000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1075000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1075000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1100000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1100000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1125000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS0_1512MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1037500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1087500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1150000 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1162500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS1_1512MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1012500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1037500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1050000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1087500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1125000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS2_1512MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 937500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 950000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 975000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1000000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1012500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1037500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1075000 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1087500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS3_1512MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 987500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1000000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1037500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1050000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS4_1512MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 950000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 962500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 975000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1000000 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1012500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS5_1512MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 987500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1000000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS6_1512MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 987500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1037500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1087500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1150000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1175000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1225000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1250000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS1_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1012500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1037500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1050000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1087500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1150000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1187500 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1200000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 937500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 950000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 975000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1000000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1012500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1037500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1075000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1100000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1137500 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1162500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 987500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1000000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1037500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1062500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1100000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1125000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 950000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 962500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 975000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1000000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1037500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1075000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1100000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS5_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 987500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1012500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1050000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1075000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS6_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS0_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 962500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1000000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1025000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1037500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1062500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1100000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1125000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1175000 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(14), 1225000 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1287500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS1_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 937500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 950000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 975000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1000000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1012500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1037500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1075000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1100000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1137500 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(14), 1187500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1250000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS2_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 912500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 987500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1012500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1050000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1075000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1112500 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(14), 1162500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1212500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS3_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 912500 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 937500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 962500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 975000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1000000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1025000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1050000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1087500 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(14), 1137500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1175000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS4_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 950000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 962500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 975000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1000000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1037500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1075000 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(14), 1112500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1150000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS5_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 987500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1012500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1050000 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(14), 1087500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1125000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS6_2000MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
- { 1, { 1782000, HFPLL, 1, 0x42 }, L2(14), 1062500 },
- { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1100000 },
- { 0, { 0 } }
-};
-
-static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
- [0][PVS_SLOW] = {tbl_slow, sizeof(tbl_slow), 0 },
- [0][PVS_NOMINAL] = {tbl_nom, sizeof(tbl_nom), 25000 },
- [0][PVS_FAST] = {tbl_fast, sizeof(tbl_fast), 25000 },
- [0][PVS_FASTER] = {tbl_faster, sizeof(tbl_faster), 25000 },
-
- [1][0] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
- [1][1] = { tbl_PVS1_1700MHz, sizeof(tbl_PVS1_1700MHz), 25000 },
- [1][2] = { tbl_PVS2_1700MHz, sizeof(tbl_PVS2_1700MHz), 25000 },
- [1][3] = { tbl_PVS3_1700MHz, sizeof(tbl_PVS3_1700MHz), 25000 },
- [1][4] = { tbl_PVS4_1700MHz, sizeof(tbl_PVS4_1700MHz), 25000 },
- [1][5] = { tbl_PVS5_1700MHz, sizeof(tbl_PVS5_1700MHz), 25000 },
- [1][6] = { tbl_PVS6_1700MHz, sizeof(tbl_PVS6_1700MHz), 25000 },
-
- [2][0] = { tbl_PVS0_2000MHz, sizeof(tbl_PVS0_2000MHz), 0 },
- [2][1] = { tbl_PVS1_2000MHz, sizeof(tbl_PVS1_2000MHz), 25000 },
- [2][2] = { tbl_PVS2_2000MHz, sizeof(tbl_PVS2_2000MHz), 25000 },
- [2][3] = { tbl_PVS3_2000MHz, sizeof(tbl_PVS3_2000MHz), 25000 },
- [2][4] = { tbl_PVS4_2000MHz, sizeof(tbl_PVS4_2000MHz), 25000 },
- [2][5] = { tbl_PVS5_2000MHz, sizeof(tbl_PVS5_2000MHz), 25000 },
- [2][6] = { tbl_PVS6_2000MHz, sizeof(tbl_PVS6_2000MHz), 25000 },
-
- [14][0] = { tbl_PVS0_1512MHz, sizeof(tbl_PVS0_1512MHz), 0 },
- [14][1] = { tbl_PVS1_1512MHz, sizeof(tbl_PVS1_1512MHz), 25000 },
- [14][2] = { tbl_PVS2_1512MHz, sizeof(tbl_PVS2_1512MHz), 25000 },
- [14][3] = { tbl_PVS3_1512MHz, sizeof(tbl_PVS3_1512MHz), 25000 },
- [14][4] = { tbl_PVS4_1512MHz, sizeof(tbl_PVS4_1512MHz), 25000 },
- [14][5] = { tbl_PVS5_1512MHz, sizeof(tbl_PVS5_1512MHz), 25000 },
- [14][6] = { tbl_PVS6_1512MHz, sizeof(tbl_PVS6_1512MHz), 25000 },
-};
-
-static struct acpuclk_krait_params acpuclk_8064_params __initdata = {
- .scalable = scalable,
- .scalable_size = sizeof(scalable),
- .hfpll_data = &hfpll_data,
- .pvs_tables = pvs_tables,
- .l2_freq_tbl = l2_freq_tbl,
- .l2_freq_tbl_size = sizeof(l2_freq_tbl),
- .bus_scale = &bus_scale_data,
- .pte_efuse_phys = 0x007000C0,
- .get_bin_info = get_krait_bin_format_a,
- .stby_khz = 384000,
-};
-
-static int __init acpuclk_8064_probe(struct platform_device *pdev)
-{
- if (cpu_is_apq8064ab() ||
- SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
- acpuclk_8064_params.hfpll_data->low_vdd_l_max = 37;
- acpuclk_8064_params.hfpll_data->nom_vdd_l_max = 74;
- }
-
- return acpuclk_krait_init(&pdev->dev, &acpuclk_8064_params);
-}
-
-static struct platform_driver acpuclk_8064_driver = {
- .driver = {
- .name = "acpuclk-8064",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init acpuclk_8064_init(void)
-{
- return platform_driver_probe(&acpuclk_8064_driver,
- acpuclk_8064_probe);
-}
-device_initcall(acpuclk_8064_init);
diff --git a/arch/arm/mach-msm/acpuclock-8627.c b/arch/arm/mach-msm/acpuclock-8627.c
deleted file mode 100644
index 405b26b..0000000
--- a/arch/arm/mach-msm/acpuclock-8627.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/rpm-regulator.h>
-#include <mach/msm_bus_board.h>
-#include <mach/msm_bus.h>
-
-#include "acpuclock.h"
-#include "acpuclock-krait.h"
-
-/* Corner type vreg VDD values */
-#define LVL_NONE RPM_VREG_CORNER_NONE
-#define LVL_LOW RPM_VREG_CORNER_LOW
-#define LVL_NOM RPM_VREG_CORNER_NOMINAL
-#define LVL_HIGH RPM_VREG_CORNER_HIGH
-
-static struct hfpll_data hfpll_data __initdata = {
- .mode_offset = 0x00,
- .l_offset = 0x08,
- .m_offset = 0x0C,
- .n_offset = 0x10,
- .config_offset = 0x04,
- .config_val = 0x7845C665,
- .has_droop_ctl = true,
- .droop_offset = 0x14,
- .droop_val = 0x0108C000,
- .low_vdd_l_max = 22,
- .nom_vdd_l_max = 42,
- .vdd[HFPLL_VDD_NONE] = LVL_NONE,
- .vdd[HFPLL_VDD_LOW] = LVL_LOW,
- .vdd[HFPLL_VDD_NOM] = LVL_NOM,
- .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
-};
-
-static struct scalable scalable[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0x00903200,
- .aux_clk_sel_phys = 0x02088014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0x00903300,
- .aux_clk_sel_phys = 0x02098014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0x00903400,
- .aux_clk_sel_phys = 0x02011028,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x0500,
- .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
- },
-};
-
-static struct msm_bus_paths bw_level_tbl[] __initdata = {
- [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
- [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
- [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
- [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
- [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
-};
-
-static struct msm_bus_scale_pdata bus_scale_data __initdata = {
- .usecase = bw_level_tbl,
- .num_usecases = ARRAY_SIZE(bw_level_tbl),
- .active_only = 1,
- .name = "acpuclk-8627",
-};
-
-/* TODO: Update vdd_dig, vdd_mem and bw when data is available. */
-static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_NOM, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 1 },
- [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 1 },
- [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 2 },
- [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 3 },
- [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 3 },
- [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 3 },
- [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 4 },
- [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 4 },
- { }
-};
-
-/* TODO: Update core voltages when data is available. */
-static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 432000, HFPLL, 2, 0x20 }, L2(4), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 925000 },
- { 1, { 540000, HFPLL, 2, 0x28 }, L2(4), 937500 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 962500 },
- { 1, { 648000, HFPLL, 1, 0x18 }, L2(8), 987500 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(8), 1000000 },
- { 1, { 756000, HFPLL, 1, 0x1C }, L2(8), 1025000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(8), 1062500 },
- { 1, { 864000, HFPLL, 1, 0x20 }, L2(11), 1062500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(11), 1087500 },
- { 1, { 972000, HFPLL, 1, 0x24 }, L2(11), 1100000 },
- { 0, { 0 } }
-};
-
-static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
- [0][PVS_SLOW] = { acpu_freq_tbl, sizeof(acpu_freq_tbl), 0 },
- [0][PVS_NOMINAL] = { acpu_freq_tbl, sizeof(acpu_freq_tbl), 25000 },
- [0][PVS_FAST] = { acpu_freq_tbl, sizeof(acpu_freq_tbl), 25000 },
-};
-
-static struct acpuclk_krait_params acpuclk_8627_params __initdata = {
- .scalable = scalable,
- .scalable_size = sizeof(scalable),
- .hfpll_data = &hfpll_data,
- .pvs_tables = pvs_tables,
- .l2_freq_tbl = l2_freq_tbl,
- .l2_freq_tbl_size = sizeof(l2_freq_tbl),
- .bus_scale = &bus_scale_data,
- .pte_efuse_phys = 0x007000C0,
- .get_bin_info = get_krait_bin_format_a,
- .stby_khz = 384000,
-};
-
-static int __init acpuclk_8627_probe(struct platform_device *pdev)
-{
- return acpuclk_krait_init(&pdev->dev, &acpuclk_8627_params);
-}
-
-static struct platform_driver acpuclk_8627_driver = {
- .driver = {
- .name = "acpuclk-8627",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init acpuclk_8627_init(void)
-{
- return platform_driver_probe(&acpuclk_8627_driver,
- acpuclk_8627_probe);
-}
-device_initcall(acpuclk_8627_init);
diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
deleted file mode 100644
index e29d6fe..0000000
--- a/arch/arm/mach-msm/acpuclock-8930.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/rpm-regulator.h>
-#include <mach/msm_bus_board.h>
-#include <mach/msm_bus.h>
-
-#include "acpuclock.h"
-#include "acpuclock-krait.h"
-
-/* Corner type vreg VDD values */
-#define LVL_NONE RPM_VREG_CORNER_NONE
-#define LVL_LOW RPM_VREG_CORNER_LOW
-#define LVL_NOM RPM_VREG_CORNER_NOMINAL
-#define LVL_HIGH RPM_VREG_CORNER_HIGH
-
-static struct hfpll_data hfpll_data __initdata = {
- .mode_offset = 0x00,
- .l_offset = 0x08,
- .m_offset = 0x0C,
- .n_offset = 0x10,
- .config_offset = 0x04,
- .config_val = 0x7845C665,
- .has_droop_ctl = true,
- .droop_offset = 0x14,
- .droop_val = 0x0108C000,
- .low_vdd_l_max = 22,
- .nom_vdd_l_max = 42,
- .vdd[HFPLL_VDD_NONE] = LVL_NONE,
- .vdd[HFPLL_VDD_LOW] = LVL_LOW,
- .vdd[HFPLL_VDD_NOM] = LVL_NOM,
- .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
-};
-
-static struct scalable scalable_pm8917[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0x00903200,
- .aux_clk_sel_phys = 0x02088014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0x00903300,
- .aux_clk_sel_phys = 0x02098014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0x00903400,
- .aux_clk_sel_phys = 0x02011028,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x0500,
- .vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
- },
-};
-
-static struct scalable scalable[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0x00903200,
- .aux_clk_sel_phys = 0x02088014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0x00903300,
- .aux_clk_sel_phys = 0x02098014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0x00903400,
- .aux_clk_sel_phys = 0x02011028,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x0500,
- .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
- },
-};
-
-static struct msm_bus_paths bw_level_tbl[] __initdata = {
- [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
- [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
- [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
- [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
- [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
- [5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
- [6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
- [7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
-};
-
-static struct msm_bus_scale_pdata bus_scale_data __initdata = {
- .usecase = bw_level_tbl,
- .num_usecases = ARRAY_SIZE(bw_level_tbl),
- .active_only = 1,
- .name = "acpuclk-8930",
-};
-
-static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
- [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 },
- [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 },
- [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 },
- [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 },
- [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 },
- [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 },
- { }
-};
-
-static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 975000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 975000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1000000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1000000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1050000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1050000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1075000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1075000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1100000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1000000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1000000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1025000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1025000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1050000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
- { 0, { 0 } }
-};
-
-static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
-[0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
-[0][PVS_NOMINAL] = { acpu_freq_tbl_nom, sizeof(acpu_freq_tbl_nom), 25000 },
-[0][PVS_FAST] = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast), 25000 },
-};
-
-static struct acpuclk_krait_params acpuclk_8930_params __initdata = {
- .scalable = scalable,
- .scalable_size = sizeof(scalable),
- .hfpll_data = &hfpll_data,
- .pvs_tables = pvs_tables,
- .l2_freq_tbl = l2_freq_tbl,
- .l2_freq_tbl_size = sizeof(l2_freq_tbl),
- .bus_scale = &bus_scale_data,
- .pte_efuse_phys = 0x007000C0,
- .get_bin_info = get_krait_bin_format_a,
- .stby_khz = 384000,
-};
-
-static int __init acpuclk_8930_probe(struct platform_device *pdev)
-{
- struct acpuclk_platform_data *pdata = pdev->dev.platform_data;
- if (pdata && pdata->uses_pm8917)
- acpuclk_8930_params.scalable = scalable_pm8917;
-
- return acpuclk_krait_init(&pdev->dev, &acpuclk_8930_params);
-}
-
-static struct platform_driver acpuclk_8930_driver = {
- .driver = {
- .name = "acpuclk-8930",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init acpuclk_8930_init(void)
-{
- return platform_driver_probe(&acpuclk_8930_driver,
- acpuclk_8930_probe);
-}
-device_initcall(acpuclk_8930_init);
diff --git a/arch/arm/mach-msm/acpuclock-8930aa.c b/arch/arm/mach-msm/acpuclock-8930aa.c
deleted file mode 100644
index c824323..0000000
--- a/arch/arm/mach-msm/acpuclock-8930aa.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/rpm-regulator.h>
-#include <mach/msm_bus_board.h>
-#include <mach/msm_bus.h>
-
-#include "acpuclock.h"
-#include "acpuclock-krait.h"
-
-/* Corner type vreg VDD values */
-#define LVL_NONE RPM_VREG_CORNER_NONE
-#define LVL_LOW RPM_VREG_CORNER_LOW
-#define LVL_NOM RPM_VREG_CORNER_NOMINAL
-#define LVL_HIGH RPM_VREG_CORNER_HIGH
-
-static struct hfpll_data hfpll_data __initdata = {
- .mode_offset = 0x00,
- .l_offset = 0x08,
- .m_offset = 0x0C,
- .n_offset = 0x10,
- .config_offset = 0x04,
- .config_val = 0x7845C665,
- .has_droop_ctl = true,
- .droop_offset = 0x14,
- .droop_val = 0x0108C000,
- .low_vdd_l_max = 22,
- .nom_vdd_l_max = 42,
- .vdd[HFPLL_VDD_NONE] = LVL_NONE,
- .vdd[HFPLL_VDD_LOW] = LVL_LOW,
- .vdd[HFPLL_VDD_NOM] = LVL_NOM,
- .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
-};
-
-static struct scalable scalable[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0x00903200,
- .aux_clk_sel_phys = 0x02088014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0x00903300,
- .aux_clk_sel_phys = 0x02098014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0x00903400,
- .aux_clk_sel_phys = 0x02011028,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x0500,
- .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
- },
-};
-
-static struct msm_bus_paths bw_level_tbl[] __initdata = {
- [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
- [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
- [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
- [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
- [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
- [5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
- [6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
- [7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
-};
-
-static struct msm_bus_scale_pdata bus_scale_data __initdata = {
- .usecase = bw_level_tbl,
- .num_usecases = ARRAY_SIZE(bw_level_tbl),
- .active_only = 1,
- .name = "acpuclk-8930aa",
-};
-
-static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
- [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 },
- [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 },
- [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 },
- [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 },
- [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 },
- [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 },
- { }
-};
-
-static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
- { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 975000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 975000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1000000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1000000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1050000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1050000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1075000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1075000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1100000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1175000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1200000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1200000 },
- { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1212500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1000000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1000000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1025000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1025000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1050000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1125000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1150000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1150000 },
- { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1162500 },
- { 0, { 0 } }
-};
-
-static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
-[0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
-[0][PVS_NOMINAL] = { acpu_freq_tbl_nom, sizeof(acpu_freq_tbl_nom), 25000 },
-[0][PVS_FAST] = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast), 25000 },
-};
-
-static struct acpuclk_krait_params acpuclk_8930aa_params __initdata = {
- .scalable = scalable,
- .scalable_size = sizeof(scalable),
- .hfpll_data = &hfpll_data,
- .pvs_tables = pvs_tables,
- .l2_freq_tbl = l2_freq_tbl,
- .l2_freq_tbl_size = sizeof(l2_freq_tbl),
- .bus_scale = &bus_scale_data,
- .pte_efuse_phys = 0x007000C0,
- .get_bin_info = get_krait_bin_format_a,
- .stby_khz = 384000,
-};
-
-static int __init acpuclk_8930aa_probe(struct platform_device *pdev)
-{
- return acpuclk_krait_init(&pdev->dev, &acpuclk_8930aa_params);
-}
-
-static struct platform_driver acpuclk_8930aa_driver = {
- .driver = {
- .name = "acpuclk-8930aa",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init acpuclk_8930aa_init(void)
-{
- return platform_driver_probe(&acpuclk_8930aa_driver,
- acpuclk_8930aa_probe);
-}
-device_initcall(acpuclk_8930aa_init);
diff --git a/arch/arm/mach-msm/acpuclock-8930ab.c b/arch/arm/mach-msm/acpuclock-8930ab.c
deleted file mode 100644
index 7ec267b..0000000
--- a/arch/arm/mach-msm/acpuclock-8930ab.c
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/rpm-regulator.h>
-#include <mach/msm_bus_board.h>
-#include <mach/msm_bus.h>
-
-#include "acpuclock.h"
-#include "acpuclock-krait.h"
-
-/* Corner type vreg VDD values */
-#define LVL_NONE RPM_VREG_CORNER_NONE
-#define LVL_LOW RPM_VREG_CORNER_LOW
-#define LVL_NOM RPM_VREG_CORNER_NOMINAL
-#define LVL_HIGH RPM_VREG_CORNER_HIGH
-
-static struct hfpll_data hfpll_data __initdata = {
- .mode_offset = 0x00,
- .l_offset = 0x08,
- .m_offset = 0x0C,
- .n_offset = 0x10,
- .config_offset = 0x04,
- .config_val = 0x7845C665,
- .has_droop_ctl = true,
- .droop_offset = 0x14,
- .droop_val = 0x0108C000,
- .low_vdd_l_max = 37,
- .nom_vdd_l_max = 74,
- .vdd[HFPLL_VDD_NONE] = LVL_NONE,
- .vdd[HFPLL_VDD_LOW] = LVL_LOW,
- .vdd[HFPLL_VDD_NOM] = LVL_NOM,
- .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
-};
-
-static struct scalable scalable_pm8917[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0x00903200,
- .aux_clk_sel_phys = 0x02088014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0x00903300,
- .aux_clk_sel_phys = 0x02098014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0x00903400,
- .aux_clk_sel_phys = 0x02011028,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x0500,
- .vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
- },
-};
-
-static struct scalable scalable[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0x00903200,
- .aux_clk_sel_phys = 0x02088014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0x00903300,
- .aux_clk_sel_phys = 0x02098014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH},
- .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0x00903400,
- .aux_clk_sel_phys = 0x02011028,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x0500,
- .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
- },
-};
-
-static struct msm_bus_paths bw_level_tbl[] __initdata = {
- [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
- [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
- [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
- [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
- [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
- [5] = BW_MBPS(4800), /* At least 600 MHz on bus. */
-};
-
-static struct msm_bus_scale_pdata bus_scale_data __initdata = {
- .usecase = bw_level_tbl,
- .num_usecases = ARRAY_SIZE(bw_level_tbl),
- .active_only = 1,
- .name = "acpuclk-8930ab",
-};
-
-static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
- [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 5 },
- [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 5 },
- [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 5 },
- [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 5 },
- [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 5 },
- [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 5 },
- { }
-};
-
-static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 1000000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1050000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1125000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1150000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1175000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1200000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1225000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1250000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1275000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS1_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1000000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1025000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1050000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1075000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1125000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1150000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1175000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1200000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1225000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 975000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1075000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1100000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1125000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1150000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1175000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1200000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1225000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 975000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1000000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1025000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1050000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1075000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1100000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1125000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1150000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1175000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 950000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 975000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1000000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1025000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1050000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1075000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1100000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1125000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1150000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1175000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS5_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 925000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 950000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 975000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1000000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1025000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1050000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1075000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1100000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1125000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1150000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS6_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 900000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 925000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 950000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 975000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1000000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1025000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1050000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1075000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1100000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1125000 },
- { 0, { 0 } }
-};
-
-static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
- [0][0] = { tbl_PVS0_1700MHz, sizeof(tbl_PVS0_1700MHz), 0 },
- [0][1] = { tbl_PVS1_1700MHz, sizeof(tbl_PVS1_1700MHz), 25000 },
- [0][2] = { tbl_PVS2_1700MHz, sizeof(tbl_PVS2_1700MHz), 25000 },
- [0][3] = { tbl_PVS3_1700MHz, sizeof(tbl_PVS3_1700MHz), 25000 },
- [0][4] = { tbl_PVS4_1700MHz, sizeof(tbl_PVS4_1700MHz), 25000 },
- [0][5] = { tbl_PVS5_1700MHz, sizeof(tbl_PVS5_1700MHz), 25000 },
- [0][6] = { tbl_PVS6_1700MHz, sizeof(tbl_PVS6_1700MHz), 25000 },
-};
-
-static struct acpuclk_krait_params acpuclk_8930ab_params __initdata = {
- .scalable = scalable,
- .scalable_size = sizeof(scalable),
- .hfpll_data = &hfpll_data,
- .pvs_tables = pvs_tables,
- .l2_freq_tbl = l2_freq_tbl,
- .l2_freq_tbl_size = sizeof(l2_freq_tbl),
- .bus_scale = &bus_scale_data,
- .pte_efuse_phys = 0x007000C0,
- .get_bin_info = get_krait_bin_format_a,
- .stby_khz = 384000,
-};
-
-static int __init acpuclk_8930ab_probe(struct platform_device *pdev)
-{
- struct acpuclk_platform_data *pdata = pdev->dev.platform_data;
- if (pdata && pdata->uses_pm8917)
- acpuclk_8930ab_params.scalable = scalable_pm8917;
-
- return acpuclk_krait_init(&pdev->dev, &acpuclk_8930ab_params);
-}
-
-static struct platform_driver acpuclk_8930ab_driver = {
- .driver = {
- .name = "acpuclk-8930ab",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init acpuclk_8930ab_init(void)
-{
- return platform_driver_probe(&acpuclk_8930ab_driver,
- acpuclk_8930ab_probe);
-}
-device_initcall(acpuclk_8930ab_init);
diff --git a/arch/arm/mach-msm/acpuclock-8960.c b/arch/arm/mach-msm/acpuclock-8960.c
deleted file mode 100644
index 317729f..0000000
--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/rpm-regulator.h>
-#include <mach/msm_bus_board.h>
-#include <mach/msm_bus.h>
-
-#include "acpuclock.h"
-#include "acpuclock-krait.h"
-
-static struct hfpll_data hfpll_data __initdata = {
- .mode_offset = 0x00,
- .l_offset = 0x08,
- .m_offset = 0x0C,
- .n_offset = 0x10,
- .config_offset = 0x04,
- .config_val = 0x7845C665,
- .has_droop_ctl = true,
- .droop_offset = 0x14,
- .droop_val = 0x0108C000,
- .low_vdd_l_max = 22,
- .nom_vdd_l_max = 42,
- .vdd[HFPLL_VDD_NONE] = 0,
- .vdd[HFPLL_VDD_LOW] = 945000,
- .vdd[HFPLL_VDD_NOM] = 1050000,
- .vdd[HFPLL_VDD_HIGH] = 1150000,
-};
-
-static struct scalable scalable[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0x00903200,
- .aux_clk_sel_phys = 0x02088014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0x00903300,
- .aux_clk_sel_phys = 0x02098014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0x00903400,
- .aux_clk_sel_phys = 0x02011028,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x0500,
- .vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
- },
-};
-
-static struct msm_bus_paths bw_level_tbl[] __initdata = {
- [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
- [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
- [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
- [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
- [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
- [5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
- [6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
-};
-
-static struct msm_bus_scale_pdata bus_scale_data __initdata = {
- .usecase = bw_level_tbl,
- .num_usecases = ARRAY_SIZE(bw_level_tbl),
- .active_only = 1,
- .name = "acpuclk-8960",
-};
-
-static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 0x00 }, 1050000, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0x1A }, 1050000, 1050000, 4 },
- [7] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 6 },
- [11] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 6 },
- [12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 6 },
- [13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 6 },
- [14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 6 },
- [15] = { { 1188000, HFPLL, 1, 0x2C }, 1150000, 1150000, 6 },
- [16] = { { 1242000, HFPLL, 1, 0x2E }, 1150000, 1150000, 6 },
- [17] = { { 1296000, HFPLL, 1, 0x30 }, 1150000, 1150000, 6 },
- [18] = { { 1350000, HFPLL, 1, 0x32 }, 1150000, 1150000, 6 },
- { }
-};
-
-#define AVS(x) .avsdscr_setting = (x)
-
-static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000, AVS(0x40001F) },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(18), 1175000, AVS(0x400015) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(18), 1175000, AVS(0x400015) },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(18), 1200000, AVS(0x400015) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1200000, AVS(0x400015) },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1225000, AVS(0x400015) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1225000, AVS(0x400015) },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1237500, AVS(0x400015) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1237500, AVS(0x100018) },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1250000, AVS(0x400012) },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000, AVS(0x40007F) },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 925000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 950000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 975000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 975000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 1025000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 1025000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1050000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1050000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1075000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(18), 1125000, AVS(0x400015) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(18), 1125000, AVS(0x400015) },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(18), 1150000, AVS(0x400015) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1150000, AVS(0x400015) },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1175000, AVS(0x400015) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1175000, AVS(0x400015) },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1187500, AVS(0x400015) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1187500, AVS(0x100018) },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1200000, AVS(0x400012) },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000, AVS(0x4000FF) },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(6), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(6), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(6), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(6), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(6), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(6), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(6), 975000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(6), 975000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(6), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(6), 1000000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(6), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(6), 1025000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(18), 1075000, AVS(0x10001B) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(18), 1075000, AVS(0x10001B) },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(18), 1100000, AVS(0x10001B) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1100000, AVS(0x10001B) },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1125000, AVS(0x10001B) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1125000, AVS(0x400012) },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1137500, AVS(0x400012) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1137500, AVS(0x400012) },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1150000, AVS(0x400012) },
- { 0, { 0 } }
-};
-
-static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
-[0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
-[0][PVS_NOMINAL] = { acpu_freq_tbl_nom, sizeof(acpu_freq_tbl_nom), 25000 },
-[0][PVS_FAST] = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast), 25000 },
-};
-
-static struct acpuclk_krait_params acpuclk_8960_params __initdata = {
- .scalable = scalable,
- .scalable_size = sizeof(scalable),
- .hfpll_data = &hfpll_data,
- .pvs_tables = pvs_tables,
- .l2_freq_tbl = l2_freq_tbl,
- .l2_freq_tbl_size = sizeof(l2_freq_tbl),
- .bus_scale = &bus_scale_data,
- .pte_efuse_phys = 0x007000C0,
- .get_bin_info = get_krait_bin_format_a,
- .stby_khz = 384000,
-};
-
-static int __init acpuclk_8960_probe(struct platform_device *pdev)
-{
- return acpuclk_krait_init(&pdev->dev, &acpuclk_8960_params);
-}
-
-static struct platform_driver acpuclk_8960_driver = {
- .driver = {
- .name = "acpuclk-8960",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init acpuclk_8960_init(void)
-{
- return platform_driver_probe(&acpuclk_8960_driver, acpuclk_8960_probe);
-}
-device_initcall(acpuclk_8960_init);
diff --git a/arch/arm/mach-msm/acpuclock-8960ab.c b/arch/arm/mach-msm/acpuclock-8960ab.c
deleted file mode 100644
index 0fa2cde..0000000
--- a/arch/arm/mach-msm/acpuclock-8960ab.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <mach/rpm-regulator.h>
-#include <mach/msm_bus_board.h>
-#include <mach/msm_bus.h>
-
-#include "acpuclock.h"
-#include "acpuclock-krait.h"
-
-static struct hfpll_data hfpll_data __initdata = {
- .mode_offset = 0x00,
- .l_offset = 0x08,
- .m_offset = 0x0C,
- .n_offset = 0x10,
- .config_offset = 0x04,
- .config_val = 0x7845C665,
- .has_droop_ctl = true,
- .droop_offset = 0x14,
- .droop_val = 0x0108C000,
- .low_vdd_l_max = 37,
- .nom_vdd_l_max = 74,
- .vdd[HFPLL_VDD_NONE] = 0,
- .vdd[HFPLL_VDD_LOW] = 945000,
- .vdd[HFPLL_VDD_NOM] = 1050000,
- .vdd[HFPLL_VDD_HIGH] = 1150000,
-};
-
-static struct scalable scalable[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0x00903200,
- .aux_clk_sel_phys = 0x02088014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0x00903300,
- .aux_clk_sel_phys = 0x02098014,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
- .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
- .vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0x00903400,
- .aux_clk_sel_phys = 0x02011028,
- .aux_clk_sel = 3,
- .sec_clk_sel = 2,
- .l2cpmr_iaddr = 0x0500,
- .vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
- .vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
- },
-};
-
-static struct msm_bus_paths bw_level_tbl[] __initdata = {
- [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
- [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
- [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
- [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
- [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
- [5] = BW_MBPS(4264), /* At least 533 MHz on bus. */
-};
-
-static struct msm_bus_scale_pdata bus_scale_data __initdata = {
- .usecase = bw_level_tbl,
- .num_usecases = ARRAY_SIZE(bw_level_tbl),
- .active_only = 1,
- .name = "acpuclk-8960ab",
-};
-
-static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 0x00 }, 1050000, 1050000, 1 },
- [1] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
- [2] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
- [3] = { { 702000, HFPLL, 1, 0x1A }, 1050000, 1050000, 4 },
- [4] = { { 810000, HFPLL, 1, 0x1E }, 1050000, 1050000, 4 },
- [5] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 },
- [6] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
- [7] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
- [8] = { { 1242000, HFPLL, 1, 0x2E }, 1150000, 1150000, 5 },
- [9] = { { 1350000, HFPLL, 1, 0x32 }, 1150000, 1150000, 5 },
- { }
-};
-
-#define AVS(x) .avsdscr_setting = (x)
-
-static struct acpu_level freq_tbl_PVS0[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000, AVS(0x70001F) },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 950000, AVS(0x0) },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 975000, AVS(0x0) },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(4), 1000000, AVS(0x0) },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(4), 1025000, AVS(0x0) },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(4), 1050000, AVS(0x0) },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(4), 1075000, AVS(0x0) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1100000, AVS(0x70000D) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1125000, AVS(0x0) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1150000, AVS(0x0) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1175000, AVS(0x0) },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1200000, AVS(0x0) },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1225000, AVS(0x0) },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1250000, AVS(0x70000B) },
- { 0, { 0 } }
-};
-
-static struct acpu_level freq_tbl_PVS1[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000, AVS(0x70001F) },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 925000, AVS(0x0) },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 950000, AVS(0x0) },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(4), 975000, AVS(0x0) },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(4), 1000000, AVS(0x0) },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(4), 1025000, AVS(0x0) },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(4), 1050000, AVS(0x0) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1075000, AVS(0x70000D) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1100000, AVS(0x0) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1125000, AVS(0x0) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1150000, AVS(0x0) },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1175000, AVS(0x0) },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1200000, AVS(0x0) },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1225000, AVS(0x70000B) },
- { 0, { 0 } }
-};
-
-static struct acpu_level freq_tbl_PVS2[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000, AVS(0x70001F) },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 900000, AVS(0x0) },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 925000, AVS(0x0) },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(4), 950000, AVS(0x0) },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(4), 975000, AVS(0x0) },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(4), 1000000, AVS(0x0) },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(4), 1025000, AVS(0x0) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1050000, AVS(0x70000D) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1075000, AVS(0x0) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1100000, AVS(0x0) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1125000, AVS(0x0) },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1150000, AVS(0x0) },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1175000, AVS(0x0) },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1200000, AVS(0x70000B) },
- { 0, { 0 } }
-};
-
-static struct acpu_level freq_tbl_PVS3[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000, AVS(0x70001F) },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 900000, AVS(0x0) },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 900000, AVS(0x0) },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(4), 925000, AVS(0x0) },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(4), 950000, AVS(0x0) },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(4), 975000, AVS(0x0) },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(4), 1000000, AVS(0x0) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1025000, AVS(0x70000D) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1050000, AVS(0x0) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1075000, AVS(0x0) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1100000, AVS(0x0) },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1125000, AVS(0x0) },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1150000, AVS(0x0) },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1175000, AVS(0x70000B) },
- { 0, { 0 } }
-};
-
-static struct acpu_level freq_tbl_PVS4[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000, AVS(0x70001F) },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 875000, AVS(0x0) },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 875000, AVS(0x0) },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(4), 900000, AVS(0x0) },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(4), 925000, AVS(0x0) },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(4), 950000, AVS(0x0) },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(4), 975000, AVS(0x0) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 1000000, AVS(0x70000D) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1025000, AVS(0x0) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1050000, AVS(0x0) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1075000, AVS(0x0) },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1100000, AVS(0x0) },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1125000, AVS(0x0) },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1150000, AVS(0x70000B) },
- { 0, { 0 } }
-};
-
-static struct acpu_level freq_tbl_PVS5[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000, AVS(0x70001F) },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 875000, AVS(0x0) },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 875000, AVS(0x0) },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(4), 875000, AVS(0x0) },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(4), 900000, AVS(0x0) },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(4), 925000, AVS(0x0) },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(4), 950000, AVS(0x0) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 975000, AVS(0x70000D) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 1000000, AVS(0x0) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1025000, AVS(0x0) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1050000, AVS(0x0) },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1075000, AVS(0x0) },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1100000, AVS(0x0) },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1125000, AVS(0x70000B) },
- { 0, { 0 } }
-};
-
-static struct acpu_level freq_tbl_PVS6[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000, AVS(0x70001F) },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(4), 850000, AVS(0x0) },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(4), 850000, AVS(0x0) },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(4), 850000, AVS(0x0) },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(4), 875000, AVS(0x0) },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(4), 900000, AVS(0x0) },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(4), 925000, AVS(0x0) },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(9), 950000, AVS(0x70000D) },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(9), 975000, AVS(0x0) },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(9), 1000000, AVS(0x0) },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(9), 1025000, AVS(0x0) },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(9), 1050000, AVS(0x0) },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(9), 1075000, AVS(0x0) },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(9), 1100000, AVS(0x70000B) },
- { 0, { 0 } }
-};
-
-static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
-[0][0] = { freq_tbl_PVS0, sizeof(freq_tbl_PVS0), 0 },
-[0][1] = { freq_tbl_PVS1, sizeof(freq_tbl_PVS1), 25000 },
-[0][2] = { freq_tbl_PVS2, sizeof(freq_tbl_PVS2), 25000 },
-[0][3] = { freq_tbl_PVS3, sizeof(freq_tbl_PVS3), 25000 },
-[0][4] = { freq_tbl_PVS4, sizeof(freq_tbl_PVS4), 25000 },
-[0][5] = { freq_tbl_PVS5, sizeof(freq_tbl_PVS5), 25000 },
-[0][6] = { freq_tbl_PVS6, sizeof(freq_tbl_PVS6), 25000 },
-};
-
-static struct acpuclk_krait_params acpuclk_8960ab_params __initdata = {
- .scalable = scalable,
- .scalable_size = sizeof(scalable),
- .hfpll_data = &hfpll_data,
- .pvs_tables = pvs_tables,
- .l2_freq_tbl = l2_freq_tbl,
- .l2_freq_tbl_size = sizeof(l2_freq_tbl),
- .bus_scale = &bus_scale_data,
- .pte_efuse_phys = 0x007000C0,
- .get_bin_info = get_krait_bin_format_a,
- .stby_khz = 384000,
-};
-
-static int __init acpuclk_8960ab_probe(struct platform_device *pdev)
-{
- return acpuclk_krait_init(&pdev->dev, &acpuclk_8960ab_params);
-}
-
-static struct platform_driver acpuclk_8960ab_driver = {
- .driver = {
- .name = "acpuclk-8960ab",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init acpuclk_8960ab_init(void)
-{
- return platform_driver_probe(&acpuclk_8960ab_driver,
- acpuclk_8960ab_probe);
-}
-device_initcall(acpuclk_8960ab_init);
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
deleted file mode 100644
index 5117949..0000000
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ /dev/null
@@ -1,2451 +0,0 @@
-/*
- * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <mach/rpm-regulator-smd.h>
-#include <mach/msm_bus_board.h>
-#include <mach/msm_bus.h>
-#include <mach/socinfo.h>
-
-#include "acpuclock.h"
-#include "acpuclock-krait.h"
-
-/* Corner type vreg VDD values */
-#define LVL_NONE RPM_REGULATOR_CORNER_NONE
-#define LVL_LOW RPM_REGULATOR_CORNER_SVS_SOC
-#define LVL_NOM RPM_REGULATOR_CORNER_NORMAL
-#define LVL_HIGH RPM_REGULATOR_CORNER_SUPER_TURBO
-
-static struct hfpll_data hfpll_data __initdata = {
- .mode_offset = 0x00,
- .l_offset = 0x04,
- .m_offset = 0x08,
- .n_offset = 0x0C,
- .has_user_reg = true,
- .user_offset = 0x10,
- .config_offset = 0x14,
- .user_val = 0x8,
- .user_vco_mask = BIT(20),
- .config_val = 0x04D0405D,
- .has_lock_status = true,
- .status_offset = 0x1C,
- .low_vco_l_max = 65,
- .low_vdd_l_max = 52,
- .nom_vdd_l_max = 104,
- .vdd[HFPLL_VDD_NONE] = LVL_NONE,
- .vdd[HFPLL_VDD_LOW] = LVL_LOW,
- .vdd[HFPLL_VDD_NOM] = LVL_NOM,
- .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
-};
-
-static struct scalable scalable[] __initdata = {
- [CPU0] = {
- .hfpll_phys_base = 0xF908A000,
- .l2cpmr_iaddr = 0x4501,
- .sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait0", 1120000 },
- .vreg[VREG_MEM] = { "krait0_mem", 1050000 },
- .vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH },
- .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
- },
- [CPU1] = {
- .hfpll_phys_base = 0xF909A000,
- .l2cpmr_iaddr = 0x5501,
- .sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait1", 1120000 },
- .vreg[VREG_MEM] = { "krait1_mem", 1050000 },
- .vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH },
- .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
- },
- [CPU2] = {
- .hfpll_phys_base = 0xF90AA000,
- .l2cpmr_iaddr = 0x6501,
- .sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait2", 1120000 },
- .vreg[VREG_MEM] = { "krait2_mem", 1050000 },
- .vreg[VREG_DIG] = { "krait2_dig", LVL_HIGH },
- .vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 },
- },
- [CPU3] = {
- .hfpll_phys_base = 0xF90BA000,
- .l2cpmr_iaddr = 0x7501,
- .sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait3", 1120000 },
- .vreg[VREG_MEM] = { "krait3_mem", 1050000 },
- .vreg[VREG_DIG] = { "krait3_dig", LVL_HIGH },
- .vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 },
- },
- [L2] = {
- .hfpll_phys_base = 0xF9016000,
- .l2cpmr_iaddr = 0x0500,
- .sec_clk_sel = 2,
- .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
- },
-};
-
-static struct msm_bus_paths bw_level_tbl[] __initdata = {
- [0] = BW_MBPS(600), /* At least 75 MHz on bus. */
- [1] = BW_MBPS(800), /* At least 100 MHz on bus. */
- [2] = BW_MBPS(1200), /* At least 150 MHz on bus. */
- [3] = BW_MBPS(1600), /* At least 200 MHz on bus. */
- [4] = BW_MBPS(2456), /* At least 307 MHz on bus. */
- [5] = BW_MBPS(3680), /* At least 460 MHz on bus. */
- [6] = BW_MBPS(4912), /* At least 614 MHz on bus. */
- [7] = BW_MBPS(6400), /* At least 800 MHz on bus. */
- [8] = BW_MBPS(7448), /* At least 931 MHz on bus. */
-};
-
-static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
- [1] = { { 345600, HFPLL, 2, 36 }, LVL_LOW, 950000, 1 },
- [2] = { { 422400, HFPLL, 2, 44 }, LVL_LOW, 950000, 2 },
- [3] = { { 499200, HFPLL, 2, 52 }, LVL_LOW, 950000, 3 },
- [4] = { { 576000, HFPLL, 1, 30 }, LVL_LOW, 950000, 4 },
- [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 4 },
- [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 4 },
- [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 4 },
- [8] = { { 883200, HFPLL, 1, 46 }, LVL_NOM, 950000, 5 },
- [9] = { { 960000, HFPLL, 1, 50 }, LVL_NOM, 950000, 5 },
- [10] = { { 1036800, HFPLL, 1, 54 }, LVL_NOM, 950000, 5 },
- [11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 6 },
- [12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 6 },
- [13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 6 },
- [14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 6 },
- [15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 6 },
- [16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 6 },
- [17] = { { 1574400, HFPLL, 1, 82 }, LVL_HIGH, 1050000, 7 },
- [18] = { { 1651200, HFPLL, 1, 86 }, LVL_HIGH, 1050000, 7 },
- [19] = { { 1728000, HFPLL, 1, 90 }, LVL_HIGH, 1050000, 8 },
- { }
-};
-
-static struct acpu_level acpu_freq_tbl_2g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 815000, 73 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 825000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 835000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 845000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 855000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 865000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 875000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 890000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 900000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 915000, 252 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 925000, 275 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 940000, 298 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 950000, 321 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 965000, 346 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 980000, 371 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 995000, 397 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1010000, 423 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 1025000, 450 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 1040000, 477 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1055000, 506 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1070000, 536 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1085000, 567 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1100000, 598 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 73 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 810000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 820000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 830000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 840000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 850000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 860000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 875000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 885000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 895000, 252 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 910000, 275 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 920000, 298 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 930000, 321 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 945000, 346 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 960000, 371 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 975000, 397 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 990000, 423 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 1005000, 450 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 1020000, 477 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1030000, 506 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1045000, 536 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1060000, 567 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1075000, 598 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 785000, 73 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 795000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 805000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 815000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 825000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 835000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 845000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 855000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 865000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 875000, 252 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 890000, 275 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 900000, 298 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 910000, 321 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 925000, 346 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 940000, 371 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 955000, 397 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 970000, 423 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 980000, 450 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 995000, 477 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1005000, 506 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1020000, 536 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1035000, 567 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1050000, 598 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 73 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 780000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 790000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 252 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 875000, 275 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 885000, 298 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 895000, 321 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 346 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 925000, 371 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 935000, 397 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 950000, 423 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 960000, 450 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 970000, 477 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 985000, 506 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 995000, 536 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1010000, 567 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1025000, 598 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 73 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 780000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 790000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 252 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 275 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 298 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 321 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 895000, 346 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 371 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 920000, 397 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 423 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 450 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 950000, 477 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 960000, 506 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 975000, 536 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 985000, 567 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1000000, 598 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 73 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 760000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 770000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 780000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 790000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 252 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 275 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 860000, 298 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 870000, 321 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 880000, 346 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 371 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 900000, 397 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 423 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 450 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 930000, 477 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 940000, 506 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 955000, 536 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 965000, 567 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 975000, 598 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 73 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 760000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 770000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 780000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 790000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 252 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 275 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 298 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 321 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 346 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 875000, 371 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 885000, 397 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 423 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 905000, 450 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 915000, 477 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 920000, 506 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 536 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 940000, 567 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 598 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p2g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 805000, 102 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 815000, 121 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 825000, 141 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 835000, 161 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 845000, 181 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 855000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 865000, 223 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 875000, 245 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 890000, 267 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 900000, 289 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 915000, 313 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 925000, 336 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 940000, 360 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 950000, 383 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 965000, 409 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 980000, 435 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 995000, 461 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1010000, 488 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1025000, 516 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1040000, 543 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1055000, 573 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1070000, 604 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1085000, 636 },
- { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1100000, 656 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p2g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 102 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 121 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 141 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 161 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 181 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 223 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 245 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 875000, 267 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 885000, 289 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 895000, 313 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 336 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 920000, 360 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 930000, 383 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 945000, 409 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 960000, 435 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 975000, 461 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 990000, 488 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1005000, 516 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1020000, 543 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1030000, 573 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1045000, 604 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1060000, 636 },
- { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1075000, 656 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p2g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 102 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 785000, 121 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 795000, 141 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 805000, 161 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 815000, 181 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 825000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 835000, 223 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 845000, 245 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 855000, 267 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 865000, 289 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 875000, 313 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 336 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 360 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 910000, 383 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 925000, 409 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 435 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 955000, 461 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 970000, 488 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 980000, 516 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 995000, 543 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1005000, 573 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1020000, 604 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1035000, 636 },
- { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1050000, 656 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p2g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 102 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 121 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 780000, 141 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 790000, 161 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 181 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 223 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 245 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 267 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 289 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 313 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 875000, 336 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 360 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 383 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 409 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 925000, 435 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 461 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 488 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 960000, 516 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 970000, 543 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 985000, 573 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 995000, 604 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1010000, 636 },
- { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1025000, 656 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p2g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 102 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 121 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 141 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 780000, 161 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 790000, 181 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 223 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 245 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 267 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 289 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 313 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 336 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 870000, 360 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 880000, 383 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 409 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 910000, 435 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 920000, 461 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 930000, 488 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 940000, 516 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 950000, 543 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 573 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 975000, 604 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 985000, 636 },
- { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 1000000, 656 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p2g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 102 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 121 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 760000, 141 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 770000, 161 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 181 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 223 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 245 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 267 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 289 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 313 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 336 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 360 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 870000, 383 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 409 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 890000, 435 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 461 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 488 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 920000, 516 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 543 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 940000, 573 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 955000, 604 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 965000, 636 },
- { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 975000, 656 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p2g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 102 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 121 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 141 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 760000, 161 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 770000, 181 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 202 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 223 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 245 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 267 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 289 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 313 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 336 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 360 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 383 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 409 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 875000, 435 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 461 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 488 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 516 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 543 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 920000, 573 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 930000, 604 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 636 },
- { 1, { 2150400, HFPLL, 1, 112 }, L2(19), 950000, 656 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p3g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 805000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 815000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 825000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 835000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 845000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 855000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 865000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 875000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 890000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 900000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 915000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 925000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 940000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 950000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 965000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 980000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 995000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1010000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1025000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1040000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1055000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1070000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1085000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1100000, 691 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p3g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 875000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 885000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 895000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 920000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 945000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 960000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 975000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 990000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1005000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1020000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 691 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p3g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 785000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 795000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 805000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 815000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 825000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 835000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 845000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 855000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 865000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 875000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 900000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 925000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 940000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 955000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 970000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p3g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 780000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 790000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 875000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 885000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 910000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 925000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 935000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 950000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 960000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 985000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 691 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p3g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 870000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 895000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 910000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 920000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 940000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p3g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 760000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 770000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 880000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 890000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 910000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 920000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 930000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 965000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691 },
- { 0, { 0 } }
-};
-
-static struct acpu_level acpu_freq_tbl_2p3g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 72 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 83 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 101 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 120 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 139 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 159 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 760000, 180 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 770000, 200 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 780000, 221 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 790000, 242 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 264 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 810000, 287 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 820000, 308 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 830000, 333 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 840000, 356 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 850000, 380 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 860000, 404 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 430 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 875000, 456 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 885000, 482 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 510 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 905000, 538 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 915000, 565 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 920000, 596 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p3g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 74 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 780000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 790000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 184 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 206 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 227 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 249 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 271 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 865000, 295 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 875000, 318 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 915000, 392 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 925000, 416 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 442 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 955000, 469 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 970000, 497 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 985000, 525 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1000000, 554 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1015000, 583 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 613 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 642 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1060000, 663 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 675 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 708 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p3g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 74 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 785000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 795000, 184 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 206 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 227 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 249 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 271 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 295 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 318 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 885000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 392 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 905000, 416 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 442 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 469 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 497 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 525 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 554 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 583 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 613 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 642 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1035000, 663 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 675 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 708 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p3g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 74 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 760000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 770000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 184 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 206 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 227 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 249 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 271 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 295 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 318 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 865000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 875000, 392 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 885000, 416 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 900000, 442 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 915000, 469 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 930000, 497 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 945000, 525 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 955000, 554 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 583 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 613 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 642 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1010000, 663 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 675 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 708 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p3g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 74 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 755000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 765000, 184 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 206 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 785000, 227 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 795000, 249 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 805000, 271 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 815000, 295 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 825000, 318 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 835000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 392 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 416 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 442 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 469 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 497 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 525 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 554 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 583 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 613 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 642 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 985000, 663 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 675 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 708 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p3g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 74 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 755000, 184 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 765000, 206 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 227 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 785000, 249 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 795000, 271 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 805000, 295 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 815000, 318 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 825000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 835000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 392 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 855000, 416 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 442 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 469 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 497 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 525 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 554 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 583 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 613 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 642 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 960000, 663 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 675 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 708 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p3g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 74 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 735000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 745000, 184 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 755000, 206 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 765000, 227 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 249 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 271 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 295 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 318 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 392 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 416 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 442 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 469 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 497 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 525 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 554 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 583 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 915000, 613 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 642 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 940000, 663 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 675 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 708 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p3g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 725000, 74 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 725000, 85 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 725000, 104 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 725000, 124 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 725000, 144 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 725000, 164 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 735000, 184 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 745000, 206 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 755000, 227 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 765000, 249 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 271 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 785000, 295 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 795000, 318 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 805000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 815000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 392 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 835000, 416 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 442 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 469 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 497 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 870000, 525 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 554 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 890000, 583 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 613 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 642 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 915000, 663 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 915000, 675 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 925000, 708 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p5g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 251 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 273 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 296 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 319 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 910000, 390 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 920000, 415 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 930000, 439 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 945000, 465 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 960000, 493 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 975000, 521 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 990000, 549 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1005000, 579 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1020000, 608 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1035000, 638 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1050000, 667 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1050000, 667 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1065000, 700 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1080000, 734 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1095000, 769 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1100000, 785 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p5g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 125 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 805000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 815000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 825000, 251 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 835000, 273 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 845000, 296 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 855000, 319 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 865000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 875000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 885000, 390 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 895000, 415 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 905000, 439 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 920000, 465 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 935000, 493 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 950000, 521 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 965000, 549 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 980000, 579 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 995000, 608 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1010000, 638 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1025000, 667 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1025000, 667 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 700 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1055000, 734 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1070000, 769 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1075000, 785 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p5g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 251 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 273 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 296 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 319 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 390 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 415 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 880000, 439 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 895000, 465 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 493 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 521 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 940000, 549 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 955000, 579 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 970000, 608 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 985000, 638 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1000000, 667 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1000000, 667 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 700 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1030000, 734 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1045000, 769 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1050000, 785 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p5g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 780000, 251 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 785000, 273 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 795000, 296 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 805000, 319 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 815000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 825000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 390 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 845000, 415 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 439 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 870000, 465 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 885000, 493 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 900000, 521 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 549 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 930000, 579 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 945000, 608 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 960000, 638 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 975000, 667 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 975000, 667 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 700 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1005000, 734 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1020000, 769 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1025000, 785 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p5g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 125 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 251 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 273 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 775000, 296 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 319 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 390 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 415 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 439 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 845000, 465 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 493 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 875000, 521 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 890000, 549 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 579 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 920000, 608 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 935000, 638 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 950000, 667 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 950000, 667 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 965000, 700 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 980000, 734 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 995000, 769 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1000000, 785 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p5g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 251 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 273 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 296 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 760000, 319 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 770000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 780000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 790000, 390 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 800000, 415 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 810000, 439 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 820000, 465 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 835000, 493 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 850000, 521 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 865000, 549 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 880000, 579 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 895000, 608 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 910000, 638 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 925000, 667 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 925000, 667 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 940000, 700 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 955000, 734 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 970000, 769 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 975000, 785 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev0_2p5g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 125 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 145 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 165 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 186 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 208 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 229 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 251 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 273 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 296 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 750000, 319 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 755000, 342 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 765000, 365 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 775000, 390 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 785000, 415 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 795000, 439 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 805000, 465 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 815000, 493 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 825000, 521 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 840000, 549 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 855000, 579 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 870000, 608 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 885000, 638 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 900000, 667 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 900000, 667 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 915000, 700 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 930000, 734 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 945000, 769 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 950000, 785 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 810000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 820000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 830000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 840000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 850000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 860000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 870000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 880000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 890000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 900000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 920000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 930000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 940000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 950000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 965000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 980000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 995000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1010000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1025000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1040000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1055000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1070000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1070000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1085000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1100000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1115000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1120000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 870000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 880000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 890000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 900000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 920000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 940000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 955000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 970000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 985000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1000000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1015000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1030000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1060000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1090000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1105000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1110000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 910000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 920000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 930000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 945000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 960000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 975000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 990000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1005000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1020000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1035000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1050000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1050000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1065000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1080000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1095000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1100000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 860000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 870000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 880000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 900000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 920000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 935000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 950000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 965000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 980000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 995000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1010000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1025000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1040000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1040000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1055000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1070000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1085000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1090000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 880000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 890000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 900000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 910000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 925000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 940000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 955000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 970000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 985000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1000000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1015000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1030000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1030000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1045000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1060000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1075000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1080000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 870000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 880000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 890000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 900000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 915000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 930000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 945000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 960000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 975000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 990000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1005000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1020000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1020000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1035000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1050000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1065000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1070000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 870000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 890000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 905000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 920000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 935000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 950000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 965000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 980000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1010000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1040000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1060000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs7[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 860000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 880000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 895000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 910000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 925000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 940000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 955000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 970000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 985000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1000000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1000000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1015000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1030000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1045000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1050000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs8[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 780000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 790000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 810000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 820000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 830000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 840000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 850000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 860000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 870000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 885000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 900000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 915000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 930000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 945000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 960000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 990000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 990000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1005000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1020000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1035000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1040000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs9[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 780000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 790000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 800000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 810000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 820000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 830000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 840000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 850000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 860000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 875000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 890000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 905000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 920000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 935000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 950000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 965000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 980000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 980000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 995000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1010000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1025000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1030000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs10[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 830000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 850000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 865000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 880000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 895000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 910000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 925000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 940000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 970000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 970000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 985000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 1000000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1015000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1020000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs11[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 820000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 840000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 855000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 870000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 885000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 900000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 915000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 930000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 945000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 960000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 960000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 990000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1010000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs12[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 775000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 810000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 830000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 845000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 860000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 875000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 890000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 905000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 920000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 935000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 950000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 950000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 965000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 980000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 995000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 1000000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs13[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 775000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 775000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 800000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 810000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 820000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 835000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 850000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 865000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 880000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 895000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 910000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 925000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 940000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 955000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 970000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 985000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 990000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs14[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 760000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 770000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 780000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 790000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 800000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 810000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 825000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 840000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 855000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 870000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 885000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 900000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 915000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 930000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 930000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 945000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 960000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 975000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 980000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p5g_pvs15[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 106 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 126 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 147 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 168 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 189 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 211 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 233 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 256 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 278 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 750000, 301 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 750000, 324 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 760000, 348 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 770000, 372 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 780000, 396 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 790000, 421 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 800000, 446 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 815000, 473 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 830000, 501 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 845000, 529 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 860000, 558 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 875000, 588 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 890000, 617 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 905000, 649 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 920000, 682 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 920000, 682 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 935000, 716 },
- { 0, { 2342400, HFPLL, 1, 122 }, L2(19), 950000, 751 },
- { 0, { 2419200, HFPLL, 1, 126 }, L2(19), 965000, 786 },
- { 1, { 2457600, HFPLL, 1, 128 }, L2(19), 970000, 802 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs0[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 810000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 820000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 830000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 840000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 850000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 860000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 870000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 880000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 890000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 900000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 910000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 920000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 930000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 940000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 955000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 970000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 985000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 1000000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1015000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1030000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1045000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1060000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1075000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1090000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1105000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1105000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1120000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs1[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 810000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 820000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 830000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 840000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 850000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 860000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 870000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 880000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 890000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 900000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 910000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 920000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 930000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 945000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 960000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 975000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 990000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 1005000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1020000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1035000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1050000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1065000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1080000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1095000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1095000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1110000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs2[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 810000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 820000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 830000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 840000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 850000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 860000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 870000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 880000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 890000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 900000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 910000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 920000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 935000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 950000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 965000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 980000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 995000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1010000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1025000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1040000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1055000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1070000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1085000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1085000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1100000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs3[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 810000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 820000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 830000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 840000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 850000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 860000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 870000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 880000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 890000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 900000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 910000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 925000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 940000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 955000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 970000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 985000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 1000000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1015000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1030000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1045000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1060000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1075000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1075000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1090000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs4[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 810000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 820000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 830000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 840000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 850000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 860000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 870000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 880000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 890000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 900000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 915000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 930000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 945000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 960000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 975000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 990000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 1005000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1020000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1035000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1050000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1065000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1065000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1080000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs5[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 800000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 800000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 800000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 800000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 800000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 800000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 810000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 820000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 830000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 840000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 850000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 860000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 870000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 880000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 890000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 905000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 920000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 935000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 950000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 965000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 980000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 995000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1010000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1025000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1040000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1055000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1055000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1070000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs6[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 780000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 790000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 800000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 810000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 820000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 830000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 840000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 850000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 860000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 870000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 880000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 895000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 910000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 925000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 940000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 955000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 970000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 985000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 1000000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1015000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1030000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1045000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1045000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1060000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs7[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 780000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 790000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 800000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 810000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 820000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 830000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 840000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 850000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 860000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 870000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 885000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 900000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 915000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 930000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 945000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 960000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 975000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 990000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 1005000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1035000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs8[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 780000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 790000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 800000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 810000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 820000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 830000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 840000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 850000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 860000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 875000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 890000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 905000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 920000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 935000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 950000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 965000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 980000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 995000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1010000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1025000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1025000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1040000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs9[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 780000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 790000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 800000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 810000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 820000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 830000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 840000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 850000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 865000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 880000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 895000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 910000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 925000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 940000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 955000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 970000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 985000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1000000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1015000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1015000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1030000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs10[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 780000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 790000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 800000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 810000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 820000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 830000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 840000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 855000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 870000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 885000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 900000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 915000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 930000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 945000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 960000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 975000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 990000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 1005000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1005000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1020000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs11[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 780000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 790000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 800000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 810000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 820000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 830000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 845000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 860000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 875000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 890000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 905000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 920000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 935000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 950000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 965000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 980000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 995000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 995000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1010000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs12[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 780000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 790000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 800000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 810000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 820000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 835000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 850000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 865000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 880000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 895000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 910000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 925000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 940000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 955000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 970000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 985000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs13[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 775000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 775000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 775000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 775000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 775000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 775000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 775000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 775000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 775000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 775000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 775000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 780000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 790000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 800000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 810000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 825000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 840000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 855000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 870000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 885000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 900000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 915000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 930000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 945000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 960000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 975000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 975000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 990000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs14[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 760000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 770000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 780000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 790000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 800000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 815000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 830000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 845000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 860000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 875000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 890000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 905000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 920000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 935000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 950000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 965000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 965000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 980000, 738 },
- { 0, { 0 } }
-};
-
-static struct acpu_level pro_rev1_2p3g_pvs15[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 750000, 76 },
- { 0, { 345600, HFPLL, 2, 36 }, L2(1), 750000, 87 },
- { 1, { 422400, HFPLL, 2, 44 }, L2(2), 750000, 108 },
- { 0, { 499200, HFPLL, 2, 52 }, L2(2), 750000, 129 },
- { 0, { 576000, HFPLL, 1, 30 }, L2(3), 750000, 150 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(3), 750000, 171 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(4), 750000, 193 },
- { 0, { 806400, HFPLL, 1, 42 }, L2(4), 750000, 215 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(4), 750000, 237 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(9), 750000, 260 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(10), 750000, 282 },
- { 0, { 1113600, HFPLL, 1, 58 }, L2(10), 760000, 306 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(10), 770000, 330 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(13), 780000, 354 },
- { 0, { 1344000, HFPLL, 1, 70 }, L2(14), 790000, 378 },
- { 0, { 1420800, HFPLL, 1, 74 }, L2(15), 805000, 404 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 820000, 431 },
- { 1, { 1574400, HFPLL, 1, 82 }, L2(17), 835000, 458 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(17), 850000, 486 },
- { 1, { 1728000, HFPLL, 1, 90 }, L2(18), 865000, 515 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(18), 880000, 543 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(18), 895000, 572 },
- { 1, { 1958400, HFPLL, 1, 102 }, L2(19), 910000, 604 },
- { 0, { 2035200, HFPLL, 1, 106 }, L2(19), 925000, 636 },
- { 0, { 2112000, HFPLL, 1, 110 }, L2(19), 940000, 669 },
- { 0, { 2150400, HFPLL, 1, 112 }, L2(19), 955000, 703 },
- { 0, { 2188800, HFPLL, 1, 114 }, L2(19), 955000, 703 },
- { 1, { 2265600, HFPLL, 1, 118 }, L2(19), 970000, 738 },
- { 0, { 0 } }
-};
-
-static struct pvs_table pvs_v2[NUM_PVS_REVS][NUM_SPEED_BINS][NUM_PVS] __initdata = {
- /* 8974v2 2.0GHz Parts */
- [0][0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
- [0][0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
- [0][0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
- [0][0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
- [0][0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
- [0][0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
- [0][0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
-
- /* 8974v2 2.3GHz Parts */
- [0][1][0] = { acpu_freq_tbl_2p3g_pvs0, sizeof(acpu_freq_tbl_2p3g_pvs0) },
- [0][1][1] = { acpu_freq_tbl_2p3g_pvs1, sizeof(acpu_freq_tbl_2p3g_pvs1) },
- [0][1][2] = { acpu_freq_tbl_2p3g_pvs2, sizeof(acpu_freq_tbl_2p3g_pvs2) },
- [0][1][3] = { acpu_freq_tbl_2p3g_pvs3, sizeof(acpu_freq_tbl_2p3g_pvs3) },
- [0][1][4] = { acpu_freq_tbl_2p3g_pvs4, sizeof(acpu_freq_tbl_2p3g_pvs4) },
- [0][1][5] = { acpu_freq_tbl_2p3g_pvs5, sizeof(acpu_freq_tbl_2p3g_pvs5) },
- [0][1][6] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
- [0][1][7] = { acpu_freq_tbl_2p3g_pvs6, sizeof(acpu_freq_tbl_2p3g_pvs6) },
-
- /* 8974v2 2.2GHz Parts */
- [0][2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
- [0][2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
- [0][2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
- [0][2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
- [0][2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
- [0][2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
- [0][2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
- [0][2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
-};
-
-static struct pvs_table pvs_pro[NUM_PVS_REVS][NUM_SPEED_BINS][NUM_PVS] __initdata = {
- /* 2.0 GHz is not used on 8974Pro */
- [0][0][0] = { acpu_freq_tbl_2g_pvs0, sizeof(acpu_freq_tbl_2g_pvs0) },
- [0][0][1] = { acpu_freq_tbl_2g_pvs1, sizeof(acpu_freq_tbl_2g_pvs1) },
- [0][0][2] = { acpu_freq_tbl_2g_pvs2, sizeof(acpu_freq_tbl_2g_pvs2) },
- [0][0][3] = { acpu_freq_tbl_2g_pvs3, sizeof(acpu_freq_tbl_2g_pvs3) },
- [0][0][4] = { acpu_freq_tbl_2g_pvs4, sizeof(acpu_freq_tbl_2g_pvs4) },
- [0][0][5] = { acpu_freq_tbl_2g_pvs5, sizeof(acpu_freq_tbl_2g_pvs5) },
- [0][0][6] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
- [0][0][7] = { acpu_freq_tbl_2g_pvs6, sizeof(acpu_freq_tbl_2g_pvs6) },
-
- /* 8974Pro AB 2.3GHz */
- [0][1][0] = { pro_rev0_2p3g_pvs0, sizeof(pro_rev0_2p3g_pvs0) },
- [0][1][1] = { pro_rev0_2p3g_pvs1, sizeof(pro_rev0_2p3g_pvs1) },
- [0][1][2] = { pro_rev0_2p3g_pvs2, sizeof(pro_rev0_2p3g_pvs2) },
- [0][1][3] = { pro_rev0_2p3g_pvs3, sizeof(pro_rev0_2p3g_pvs3) },
- [0][1][4] = { pro_rev0_2p3g_pvs4, sizeof(pro_rev0_2p3g_pvs4) },
- [0][1][5] = { pro_rev0_2p3g_pvs5, sizeof(pro_rev0_2p3g_pvs5) },
- [0][1][6] = { pro_rev0_2p3g_pvs6, sizeof(pro_rev0_2p3g_pvs6) },
- [0][1][7] = { pro_rev0_2p3g_pvs6, sizeof(pro_rev0_2p3g_pvs6) },
-
- /* 2.2GHz is not used on 8974Pro */
- [0][2][0] = { acpu_freq_tbl_2p2g_pvs0, sizeof(acpu_freq_tbl_2p2g_pvs0) },
- [0][2][1] = { acpu_freq_tbl_2p2g_pvs1, sizeof(acpu_freq_tbl_2p2g_pvs1) },
- [0][2][2] = { acpu_freq_tbl_2p2g_pvs2, sizeof(acpu_freq_tbl_2p2g_pvs2) },
- [0][2][3] = { acpu_freq_tbl_2p2g_pvs3, sizeof(acpu_freq_tbl_2p2g_pvs3) },
- [0][2][4] = { acpu_freq_tbl_2p2g_pvs4, sizeof(acpu_freq_tbl_2p2g_pvs4) },
- [0][2][5] = { acpu_freq_tbl_2p2g_pvs5, sizeof(acpu_freq_tbl_2p2g_pvs5) },
- [0][2][6] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
- [0][2][7] = { acpu_freq_tbl_2p2g_pvs6, sizeof(acpu_freq_tbl_2p2g_pvs6) },
-
- /* 8974Pro AC 2.5GHz */
- [0][3][0] = { pro_rev0_2p5g_pvs0, sizeof(pro_rev0_2p5g_pvs0) },
- [0][3][1] = { pro_rev0_2p5g_pvs1, sizeof(pro_rev0_2p5g_pvs1) },
- [0][3][2] = { pro_rev0_2p5g_pvs2, sizeof(pro_rev0_2p5g_pvs2) },
- [0][3][3] = { pro_rev0_2p5g_pvs3, sizeof(pro_rev0_2p5g_pvs3) },
- [0][3][4] = { pro_rev0_2p5g_pvs4, sizeof(pro_rev0_2p5g_pvs4) },
- [0][3][5] = { pro_rev0_2p5g_pvs5, sizeof(pro_rev0_2p5g_pvs5) },
- [0][3][6] = { pro_rev0_2p5g_pvs6, sizeof(pro_rev0_2p5g_pvs6) },
- [0][3][7] = { pro_rev0_2p5g_pvs6, sizeof(pro_rev0_2p5g_pvs6) },
-
- /* 8974Pro AB 2.3GHz */
- [1][1][0] = { pro_rev1_2p3g_pvs0, sizeof(pro_rev1_2p3g_pvs0) },
- [1][1][1] = { pro_rev1_2p3g_pvs1, sizeof(pro_rev1_2p3g_pvs1) },
- [1][1][2] = { pro_rev1_2p3g_pvs2, sizeof(pro_rev1_2p3g_pvs2) },
- [1][1][3] = { pro_rev1_2p3g_pvs3, sizeof(pro_rev1_2p3g_pvs3) },
- [1][1][4] = { pro_rev1_2p3g_pvs4, sizeof(pro_rev1_2p3g_pvs4) },
- [1][1][5] = { pro_rev1_2p3g_pvs5, sizeof(pro_rev1_2p3g_pvs5) },
- [1][1][6] = { pro_rev1_2p3g_pvs6, sizeof(pro_rev1_2p3g_pvs6) },
- [1][1][7] = { pro_rev1_2p3g_pvs7, sizeof(pro_rev1_2p3g_pvs7) },
- [1][1][8] = { pro_rev1_2p3g_pvs8, sizeof(pro_rev1_2p3g_pvs8) },
- [1][1][9] = { pro_rev1_2p3g_pvs9, sizeof(pro_rev1_2p3g_pvs9) },
- [1][1][10] = { pro_rev1_2p3g_pvs10, sizeof(pro_rev1_2p3g_pvs10) },
- [1][1][11] = { pro_rev1_2p3g_pvs11, sizeof(pro_rev1_2p3g_pvs11) },
- [1][1][12] = { pro_rev1_2p3g_pvs12, sizeof(pro_rev1_2p3g_pvs12) },
- [1][1][13] = { pro_rev1_2p3g_pvs13, sizeof(pro_rev1_2p3g_pvs13) },
- [1][1][14] = { pro_rev1_2p3g_pvs14, sizeof(pro_rev1_2p3g_pvs14) },
- [1][1][15] = { pro_rev1_2p3g_pvs15, sizeof(pro_rev1_2p3g_pvs15) },
-
- /* 8974Pro AC 2.5GHz */
- [1][3][0] = { pro_rev1_2p5g_pvs0, sizeof(pro_rev1_2p5g_pvs0) },
- [1][3][1] = { pro_rev1_2p5g_pvs1, sizeof(pro_rev1_2p5g_pvs1) },
- [1][3][2] = { pro_rev1_2p5g_pvs2, sizeof(pro_rev1_2p5g_pvs2) },
- [1][3][3] = { pro_rev1_2p5g_pvs3, sizeof(pro_rev1_2p5g_pvs3) },
- [1][3][4] = { pro_rev1_2p5g_pvs4, sizeof(pro_rev1_2p5g_pvs4) },
- [1][3][5] = { pro_rev1_2p5g_pvs5, sizeof(pro_rev1_2p5g_pvs5) },
- [1][3][6] = { pro_rev1_2p5g_pvs6, sizeof(pro_rev1_2p5g_pvs6) },
- [1][3][7] = { pro_rev1_2p5g_pvs7, sizeof(pro_rev1_2p5g_pvs7) },
- [1][3][8] = { pro_rev1_2p5g_pvs8, sizeof(pro_rev1_2p5g_pvs8) },
- [1][3][9] = { pro_rev1_2p5g_pvs9, sizeof(pro_rev1_2p5g_pvs9) },
- [1][3][10] = { pro_rev1_2p5g_pvs10, sizeof(pro_rev1_2p5g_pvs10) },
- [1][3][11] = { pro_rev1_2p5g_pvs11, sizeof(pro_rev1_2p5g_pvs11) },
- [1][3][12] = { pro_rev1_2p5g_pvs12, sizeof(pro_rev1_2p5g_pvs12) },
- [1][3][13] = { pro_rev1_2p5g_pvs13, sizeof(pro_rev1_2p5g_pvs13) },
- [1][3][14] = { pro_rev1_2p5g_pvs14, sizeof(pro_rev1_2p5g_pvs14) },
- [1][3][15] = { pro_rev1_2p5g_pvs15, sizeof(pro_rev1_2p5g_pvs15) },
-};
-
-static struct msm_bus_scale_pdata bus_scale_data __initdata = {
- .usecase = bw_level_tbl,
- .num_usecases = ARRAY_SIZE(bw_level_tbl),
- .active_only = 1,
- .name = "acpuclk-8974",
-};
-
-static struct acpuclk_krait_params acpuclk_8974_params __initdata = {
- .scalable = scalable,
- .scalable_size = sizeof(scalable),
- .hfpll_data = &hfpll_data,
- .l2_freq_tbl = l2_freq_tbl,
- .l2_freq_tbl_size = sizeof(l2_freq_tbl),
- .bus_scale = &bus_scale_data,
- .pte_efuse_phys = 0xFC4B80B0,
- .get_bin_info = get_krait_bin_format_b,
- .stby_khz = 300000,
-};
-
-#define cpu_is_msm8974pro() (cpu_is_msm8974pro_aa() || cpu_is_msm8974pro_ab() \
- || cpu_is_msm8974pro_ac())
-
-static int __init acpuclk_8974_probe(struct platform_device *pdev)
-{
- if (cpu_is_msm8974pro())
- acpuclk_8974_params.pvs_tables = pvs_pro;
- else
- acpuclk_8974_params.pvs_tables = pvs_v2;
-
- return acpuclk_krait_init(&pdev->dev, &acpuclk_8974_params);
-}
-
-static struct of_device_id acpuclk_8974_match_table[] = {
- { .compatible = "qcom,acpuclk-8974" },
- {}
-};
-
-static struct platform_driver acpuclk_8974_driver = {
- .driver = {
- .name = "acpuclk-8974",
- .of_match_table = acpuclk_8974_match_table,
- .owner = THIS_MODULE,
- },
-};
-
-static int __init acpuclk_8974_init(void)
-{
- return platform_driver_probe(&acpuclk_8974_driver,
- acpuclk_8974_probe);
-}
-device_initcall(acpuclk_8974_init);
diff --git a/arch/arm/mach-msm/acpuclock-cortex.c b/arch/arm/mach-msm/acpuclock-cortex.c
index baa1c7b..f2818af 100644
--- a/arch/arm/mach-msm/acpuclock-cortex.c
+++ b/arch/arm/mach-msm/acpuclock-cortex.c
@@ -340,7 +340,7 @@
/* Construct the freq_table tables from priv->freq_tbl. */
for (i = 0; priv->freq_tbl[i].khz != 0
- && freq_cnt < ARRAY_SIZE(freq_table); i++) {
+ && freq_cnt < ARRAY_SIZE(freq_table) - 1; i++) {
if (!priv->freq_tbl[i].use_for_scaling)
continue;
freq_table[freq_cnt].index = freq_cnt;
diff --git a/arch/arm/mach-msm/acpuclock-krait-debug.c b/arch/arm/mach-msm/acpuclock-krait-debug.c
deleted file mode 100644
index f11b9fc..0000000
--- a/arch/arm/mach-msm/acpuclock-krait-debug.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define pr_fmt(fmt) "%s: " fmt, __func__
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/debugfs.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-
-#include <mach/msm_bus.h>
-#include <mach/msm-krait-l2-accessors.h>
-
-#include "acpuclock-krait.h"
-
-static struct drv_data *drv;
-static DEFINE_MUTEX(debug_lock);
-
-struct acg_action {
- bool set;
- bool enable;
-};
-static int l2_acg_en_val;
-static struct dentry *base_dir;
-static struct dentry *sc_dir[MAX_SCALABLES];
-
-static void cpu_action(void *info)
-{
- struct acg_action *action = info;
-
- u32 val;
- asm volatile ("mrc p15, 7, %[cpmr0], c15, c0, 5\n\t"
- : [cpmr0]"=r" (val));
- if (action->set) {
- if (action->enable)
- val &= ~BIT(0);
- else
- val |= BIT(0);
- asm volatile ("mcr p15, 7, %[cpmr0], c15, c0, 5\n\t"
- : : [cpmr0]"r" (val));
- } else {
- action->enable = !(val & BIT(0));
- }
-}
-
-/* Disable auto clock-gating for a scalable. */
-static void disable_acg(int sc_id)
-{
- u32 regval;
-
- if (sc_id == L2) {
- regval = get_l2_indirect_reg(drv->scalable[sc_id].l2cpmr_iaddr);
- l2_acg_en_val = regval & (0x3 << 10);
- regval |= (0x3 << 10);
- set_l2_indirect_reg(drv->scalable[sc_id].l2cpmr_iaddr, regval);
- } else {
- struct acg_action action = { .set = true, .enable = false };
- smp_call_function_single(sc_id, cpu_action, &action, 1);
- }
-}
-
-/* Enable auto clock-gating for a scalable. */
-static void enable_acg(int sc_id)
-{
- u32 regval;
-
- if (sc_id == L2) {
- regval = get_l2_indirect_reg(drv->scalable[sc_id].l2cpmr_iaddr);
- regval &= ~(0x3 << 10);
- regval |= l2_acg_en_val;
- set_l2_indirect_reg(drv->scalable[sc_id].l2cpmr_iaddr, regval);
- } else {
- struct acg_action action = { .set = true, .enable = true };
- smp_call_function_single(sc_id, cpu_action, &action, 1);
- }
-}
-
-/* Check if auto clock-gating for a scalable. */
-static bool acg_is_enabled(int sc_id)
-{
- u32 regval;
-
- if (sc_id == L2) {
- regval = get_l2_indirect_reg(drv->scalable[sc_id].l2cpmr_iaddr);
- return ((regval >> 10) & 0x3) != 0x3;
- } else {
- struct acg_action action = { .set = false };
- smp_call_function_single(sc_id, cpu_action, &action, 1);
- return action.enable;
- }
-}
-
-/* Enable/Disable auto clock gating. */
-static int acg_set(void *data, u64 val)
-{
- int ret = 0;
- int sc_id = (int)data;
-
- mutex_lock(&debug_lock);
- get_online_cpus();
- if (!sc_dir[sc_id]) {
- ret = -ENODEV;
- goto out;
- }
-
- if (val == 0 && acg_is_enabled(sc_id))
- disable_acg(sc_id);
- else if (val == 1)
- enable_acg(sc_id);
-out:
- put_online_cpus();
- mutex_unlock(&debug_lock);
-
- return ret;
-}
-
-/* Get auto clock-gating state. */
-static int acg_get(void *data, u64 *val)
-{
- int ret = 0;
- int sc_id = (int)data;
-
- mutex_lock(&debug_lock);
- get_online_cpus();
- if (!sc_dir[sc_id]) {
- ret = -ENODEV;
- goto out;
- }
-
- *val = acg_is_enabled(sc_id);
-out:
- put_online_cpus();
- mutex_unlock(&debug_lock);
-
- return ret;
-}
-DEFINE_SIMPLE_ATTRIBUTE(acgd_fops, acg_get, acg_set, "%lld\n");
-
-/* Get the rate */
-static int rate_get(void *data, u64 *val)
-{
- int sc_id = (int)data;
- *val = drv->scalable[sc_id].cur_speed->khz;
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, NULL, "%lld\n");
-
-/* Get the HFPLL's L-value. */
-static int hfpll_l_get(void *data, u64 *val)
-{
- int sc_id = (int)data;
- *val = drv->scalable[sc_id].cur_speed->pll_l_val;
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(hfpll_l_fops, hfpll_l_get, NULL, "%lld\n");
-
-/* Get the L2 rate vote. */
-static int l2_vote_get(void *data, u64 *val)
-{
- int level, sc_id = (int)data;
-
- level = drv->scalable[sc_id].l2_vote;
- *val = drv->l2_freq_tbl[level].speed.khz;
-
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(l2_vote_fops, l2_vote_get, NULL, "%lld\n");
-
-/* Get the bandwidth vote. */
-static int bw_vote_get(void *data, u64 *val)
-{
- struct l2_level *l;
-
- l = container_of(drv->scalable[L2].cur_speed,
- struct l2_level, speed);
- *val = drv->bus_scale->usecase[l->bw_level].vectors->ib;
-
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(bw_vote_fops, bw_vote_get, NULL, "%lld\n");
-
-/* Get the name of the currently-selected clock source. */
-static int src_name_show(struct seq_file *m, void *unused)
-{
- const char *const src_names[NUM_SRC_ID] = {
- [PLL_0] = "PLL0",
- [HFPLL] = "HFPLL",
- [PLL_8] = "PLL8",
- };
- int src, sc_id = (int)m->private;
-
- src = drv->scalable[sc_id].cur_speed->src;
- if (src > ARRAY_SIZE(src_names))
- return -EINVAL;
-
- seq_printf(m, "%s\n", src_names[src]);
-
- return 0;
-}
-
-static int src_name_open(struct inode *inode, struct file *file)
-{
- return single_open(file, src_name_show, inode->i_private);
-}
-
-static const struct file_operations src_name_fops = {
- .open = src_name_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = seq_release,
-};
-
-/* Get speed_bin ID */
-static int speed_bin_get(void *data, u64 *val)
-{
- *val = drv->speed_bin;
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(speed_bin_fops, speed_bin_get, NULL, "%lld\n");
-
-/* Get pvs_bin ID */
-static int pvs_bin_get(void *data, u64 *val)
-{
- *val = drv->pvs_bin;
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(pvs_bin_fops, pvs_bin_get, NULL, "%lld\n");
-
-/* Get boost_uv */
-static int boost_get(void *data, u64 *val)
-{
- *val = drv->boost_uv;
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(boost_fops, boost_get, NULL, "%lld\n");
-
-static int acpu_table_show(struct seq_file *m, void *unused)
-{
- const struct acpu_level *level;
-
- seq_printf(m, "CPU_KHz PLL_L_Val L2_KHz VDD_Dig VDD_Mem ");
- seq_printf(m, "BW_Mbps VDD_Core UA_Core AVS\n");
-
- for (level = drv->acpu_freq_tbl; level->speed.khz != 0; level++) {
-
- const struct l2_level *l2 =
- &drv->l2_freq_tbl[level->l2_level];
- u32 bw = drv->bus_scale->usecase[l2->bw_level].vectors[0].ib;
-
- if (!level->use_for_scaling)
- continue;
-
- /* CPU speed information */
- seq_printf(m, "%7lu %9u ",
- level->speed.khz,
- level->speed.pll_l_val);
-
- /* L2 level information */
- seq_printf(m, "%7lu %7d %7d %7u ",
- l2->speed.khz,
- l2->vdd_dig,
- l2->vdd_mem,
- bw / 1000000);
-
- /* Core voltage information */
- seq_printf(m, "%8d %7d %3d\n",
- level->vdd_core,
- level->ua_core,
- level->avsdscr_setting);
- }
-
- return 0;
-}
-
-static int acpu_table_open(struct inode *inode, struct file *file)
-{
- return single_open(file, acpu_table_show, inode->i_private);
-}
-
-static const struct file_operations acpu_table_fops = {
- .open = acpu_table_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = seq_release,
-};
-
-static void __cpuinit add_scalable_dir(int sc_id)
-{
- char sc_name[8];
-
- if (sc_id == L2)
- snprintf(sc_name, sizeof(sc_name), "l2");
- else
- snprintf(sc_name, sizeof(sc_name), "cpu%d", sc_id);
-
- sc_dir[sc_id] = debugfs_create_dir(sc_name, base_dir);
- if (!sc_dir[sc_id])
- return;
-
- debugfs_create_file("auto_gating", S_IRUGO | S_IWUSR,
- sc_dir[sc_id], (void *)sc_id, &acgd_fops);
-
- debugfs_create_file("rate", S_IRUGO,
- sc_dir[sc_id], (void *)sc_id, &rate_fops);
-
- debugfs_create_file("hfpll_l", S_IRUGO,
- sc_dir[sc_id], (void *)sc_id, &hfpll_l_fops);
-
- debugfs_create_file("src", S_IRUGO,
- sc_dir[sc_id], (void *)sc_id, &src_name_fops);
-
- if (sc_id == L2)
- debugfs_create_file("bw_ib_vote", S_IRUGO,
- sc_dir[sc_id], (void *)sc_id, &bw_vote_fops);
- else
- debugfs_create_file("l2_vote", S_IRUGO,
- sc_dir[sc_id], (void *)sc_id, &l2_vote_fops);
-}
-
-static void __cpuinit remove_scalable_dir(int sc_id)
-{
- debugfs_remove_recursive(sc_dir[sc_id]);
- sc_dir[sc_id] = NULL;
-}
-
-static int __cpuinit debug_cpu_callback(struct notifier_block *nfb,
- unsigned long action, void *hcpu)
-{
- int cpu = (int)hcpu;
-
- switch (action & ~CPU_TASKS_FROZEN) {
- case CPU_DOWN_FAILED:
- case CPU_UP_PREPARE:
- add_scalable_dir(cpu);
- break;
- case CPU_UP_CANCELED:
- case CPU_DOWN_PREPARE:
- remove_scalable_dir(cpu);
- break;
- default:
- break;
- }
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block __cpuinitdata debug_cpu_notifier = {
- .notifier_call = debug_cpu_callback,
-};
-
-void __init acpuclk_krait_debug_init(struct drv_data *drv_data)
-{
- int cpu;
- drv = drv_data;
-
- base_dir = debugfs_create_dir("acpuclk", NULL);
- if (!base_dir)
- return;
-
- debugfs_create_file("speed_bin", S_IRUGO, base_dir, NULL,
- &speed_bin_fops);
- debugfs_create_file("pvs_bin", S_IRUGO, base_dir, NULL, &pvs_bin_fops);
- debugfs_create_file("boost_uv", S_IRUGO, base_dir, NULL, &boost_fops);
- debugfs_create_file("acpu_table", S_IRUGO, base_dir, NULL,
- &acpu_table_fops);
-
- for_each_online_cpu(cpu)
- add_scalable_dir(cpu);
- add_scalable_dir(L2);
-
- register_hotcpu_notifier(&debug_cpu_notifier);
-}
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
deleted file mode 100644
index c5b1deb..0000000
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ /dev/null
@@ -1,1250 +0,0 @@
-/*
- * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/mutex.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/cpufreq.h>
-#include <linux/cpu.h>
-#include <linux/regulator/consumer.h>
-#include <linux/iopoll.h>
-
-#include <asm/mach-types.h>
-#include <asm/cpu.h>
-
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-#include <mach/socinfo.h>
-#include <mach/msm-krait-l2-accessors.h>
-#include <mach/rpm-regulator.h>
-#include <mach/rpm-regulator-smd.h>
-#include <mach/msm_bus.h>
-#include <mach/msm_dcvs.h>
-
-#include "acpuclock.h"
-#include "acpuclock-krait.h"
-#include "avs.h"
-
-/* MUX source selects. */
-#define PRI_SRC_SEL_SEC_SRC 0
-#define PRI_SRC_SEL_HFPLL 1
-#define PRI_SRC_SEL_HFPLL_DIV2 2
-
-static DEFINE_MUTEX(driver_lock);
-static DEFINE_SPINLOCK(l2_lock);
-
-static struct drv_data drv;
-
-static unsigned long acpuclk_krait_get_rate(int cpu)
-{
- return drv.scalable[cpu].cur_speed->khz;
-}
-
-struct set_clk_src_args {
- struct scalable *sc;
- u32 src_sel;
-};
-
-static void __set_pri_clk_src(struct scalable *sc, u32 pri_src_sel)
-{
- u32 regval;
-
- regval = get_l2_indirect_reg(sc->l2cpmr_iaddr);
- regval &= ~0x3;
- regval |= pri_src_sel;
- if (sc != &drv.scalable[L2]) {
- regval &= ~(0x3 << 8);
- regval |= pri_src_sel << 8;
- }
- set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
- /* Wait for switch to complete. */
- mb();
- udelay(1);
-}
-
-static void __set_cpu_pri_clk_src(void *data)
-{
- struct set_clk_src_args *args = data;
- __set_pri_clk_src(args->sc, args->src_sel);
-}
-
-/* Select a source on the primary MUX. */
-static void set_pri_clk_src(struct scalable *sc, u32 pri_src_sel)
-{
- int cpu = sc - drv.scalable;
- if (sc != &drv.scalable[L2] && cpu_online(cpu)) {
- struct set_clk_src_args args = {
- .sc = sc,
- .src_sel = pri_src_sel,
- };
- smp_call_function_single(cpu, __set_cpu_pri_clk_src, &args, 1);
- } else {
- __set_pri_clk_src(sc, pri_src_sel);
- }
-}
-
-/* Select a source on the secondary MUX. */
-static void __cpuinit set_sec_clk_src(struct scalable *sc, u32 sec_src_sel)
-{
- u32 regval;
-
- regval = get_l2_indirect_reg(sc->l2cpmr_iaddr);
- regval &= ~(0x3 << 2);
- regval |= sec_src_sel << 2;
- if (sc != &drv.scalable[L2]) {
- regval &= ~(0x3 << 10);
- regval |= sec_src_sel << 10;
- }
- set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
- /* Wait for switch to complete. */
- mb();
- udelay(1);
-}
-
-static int enable_rpm_vreg(struct vreg *vreg)
-{
- int ret = 0;
-
- if (vreg->rpm_reg) {
- ret = rpm_regulator_enable(vreg->rpm_reg);
- if (ret)
- dev_err(drv.dev, "%s regulator enable failed (%d)\n",
- vreg->name, ret);
- }
-
- return ret;
-}
-
-static void disable_rpm_vreg(struct vreg *vreg)
-{
- int rc;
-
- if (vreg->rpm_reg) {
- rc = rpm_regulator_disable(vreg->rpm_reg);
- if (rc)
- dev_err(drv.dev, "%s regulator disable failed (%d)\n",
- vreg->name, rc);
- }
-}
-
-/* Enable an already-configured HFPLL. */
-static void hfpll_enable(struct scalable *sc, bool skip_regulators)
-{
- if (!skip_regulators) {
- /* Enable regulators required by the HFPLL. */
- enable_rpm_vreg(&sc->vreg[VREG_HFPLL_A]);
- enable_rpm_vreg(&sc->vreg[VREG_HFPLL_B]);
- }
-
- /* Disable PLL bypass mode. */
- writel_relaxed(0x2, sc->hfpll_base + drv.hfpll_data->mode_offset);
-
- /*
- * H/W requires a 5us delay between disabling the bypass and
- * de-asserting the reset. Delay 10us just to be safe.
- */
- mb();
- udelay(10);
-
- /* De-assert active-low PLL reset. */
- writel_relaxed(0x6, sc->hfpll_base + drv.hfpll_data->mode_offset);
-
- /* Wait for PLL to lock. */
- if (drv.hfpll_data->has_lock_status) {
- u32 regval;
- readl_tight_poll(sc->hfpll_base + drv.hfpll_data->status_offset,
- regval, regval & BIT(16));
- } else {
- mb();
- udelay(60);
- }
-
- /* Enable PLL output. */
- writel_relaxed(0x7, sc->hfpll_base + drv.hfpll_data->mode_offset);
-}
-
-/* Disable a HFPLL for power-savings or while it's being reprogrammed. */
-static void hfpll_disable(struct scalable *sc, bool skip_regulators)
-{
- /*
- * Disable the PLL output, disable test mode, enable the bypass mode,
- * and assert the reset.
- */
- writel_relaxed(0, sc->hfpll_base + drv.hfpll_data->mode_offset);
-
- if (!skip_regulators) {
- /* Remove voltage votes required by the HFPLL. */
- disable_rpm_vreg(&sc->vreg[VREG_HFPLL_B]);
- disable_rpm_vreg(&sc->vreg[VREG_HFPLL_A]);
- }
-}
-
-/* Program the HFPLL rate. Assumes HFPLL is already disabled. */
-static void hfpll_set_rate(struct scalable *sc, const struct core_speed *tgt_s)
-{
- void __iomem *base = sc->hfpll_base;
- u32 regval;
-
- writel_relaxed(tgt_s->pll_l_val, base + drv.hfpll_data->l_offset);
-
- if (drv.hfpll_data->has_user_reg) {
- regval = readl_relaxed(base + drv.hfpll_data->user_offset);
- if (tgt_s->pll_l_val <= drv.hfpll_data->low_vco_l_max)
- regval &= ~drv.hfpll_data->user_vco_mask;
- else
- regval |= drv.hfpll_data->user_vco_mask;
- writel_relaxed(regval, base + drv.hfpll_data->user_offset);
- }
-}
-
-/* Return the L2 speed that should be applied. */
-static unsigned int compute_l2_level(struct scalable *sc, unsigned int vote_l)
-{
- unsigned int new_l = 0;
- int cpu;
-
- /* Find max L2 speed vote. */
- sc->l2_vote = vote_l;
- for_each_present_cpu(cpu)
- new_l = max(new_l, drv.scalable[cpu].l2_vote);
-
- return new_l;
-}
-
-/* Update the bus bandwidth request. */
-static void set_bus_bw(unsigned int bw)
-{
- int ret;
-
- /* Update bandwidth if request has changed. This may sleep. */
- ret = msm_bus_scale_client_update_request(drv.bus_perf_client, bw);
- if (ret)
- dev_err(drv.dev, "bandwidth request failed (%d)\n", ret);
-}
-
-/* Set the CPU or L2 clock speed. */
-static void set_speed(struct scalable *sc, const struct core_speed *tgt_s,
- bool skip_regulators)
-{
- const struct core_speed *strt_s = sc->cur_speed;
-
- if (strt_s == tgt_s)
- return;
-
- if (strt_s->src == HFPLL && tgt_s->src == HFPLL) {
- /*
- * Move to an always-on source running at a frequency
- * that does not require an elevated CPU voltage.
- */
- set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
-
- /* Re-program HFPLL. */
- hfpll_disable(sc, true);
- hfpll_set_rate(sc, tgt_s);
- hfpll_enable(sc, true);
-
- /* Move to HFPLL. */
- set_pri_clk_src(sc, tgt_s->pri_src_sel);
- } else if (strt_s->src == HFPLL && tgt_s->src != HFPLL) {
- set_pri_clk_src(sc, tgt_s->pri_src_sel);
- hfpll_disable(sc, skip_regulators);
- } else if (strt_s->src != HFPLL && tgt_s->src == HFPLL) {
- hfpll_set_rate(sc, tgt_s);
- hfpll_enable(sc, skip_regulators);
- set_pri_clk_src(sc, tgt_s->pri_src_sel);
- }
-
- sc->cur_speed = tgt_s;
-}
-
-struct vdd_data {
- int vdd_mem;
- int vdd_dig;
- int vdd_core;
- int ua_core;
-};
-
-/* Apply any per-cpu voltage increases. */
-static int increase_vdd(int cpu, struct vdd_data *data,
- enum setrate_reason reason)
-{
- struct scalable *sc = &drv.scalable[cpu];
- int rc;
-
- /*
- * Increase vdd_mem active-set before vdd_dig.
- * vdd_mem should be >= vdd_dig.
- */
- if (data->vdd_mem > sc->vreg[VREG_MEM].cur_vdd) {
- rc = rpm_regulator_set_voltage(sc->vreg[VREG_MEM].rpm_reg,
- data->vdd_mem, sc->vreg[VREG_MEM].max_vdd);
- if (rc) {
- dev_err(drv.dev,
- "vdd_mem (cpu%d) increase failed (%d)\n",
- cpu, rc);
- return rc;
- }
- sc->vreg[VREG_MEM].cur_vdd = data->vdd_mem;
- }
-
- /* Increase vdd_dig active-set vote. */
- if (data->vdd_dig > sc->vreg[VREG_DIG].cur_vdd) {
- rc = rpm_regulator_set_voltage(sc->vreg[VREG_DIG].rpm_reg,
- data->vdd_dig, sc->vreg[VREG_DIG].max_vdd);
- if (rc) {
- dev_err(drv.dev,
- "vdd_dig (cpu%d) increase failed (%d)\n",
- cpu, rc);
- return rc;
- }
- sc->vreg[VREG_DIG].cur_vdd = data->vdd_dig;
- }
-
- /* Increase current request. */
- if (data->ua_core > sc->vreg[VREG_CORE].cur_ua) {
- rc = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
- data->ua_core);
- if (rc < 0) {
- dev_err(drv.dev, "regulator_set_optimum_mode(%s) failed (%d)\n",
- sc->vreg[VREG_CORE].name, rc);
- return rc;
- }
- sc->vreg[VREG_CORE].cur_ua = data->ua_core;
- }
-
- /*
- * Update per-CPU core voltage. Don't do this for the hotplug path for
- * which it should already be correct. Attempting to set it is bad
- * because we don't know what CPU we are running on at this point, but
- * the CPU regulator API requires we call it from the affected CPU.
- */
- if (data->vdd_core > sc->vreg[VREG_CORE].cur_vdd
- && reason != SETRATE_HOTPLUG) {
- rc = regulator_set_voltage(sc->vreg[VREG_CORE].reg,
- data->vdd_core, sc->vreg[VREG_CORE].max_vdd);
- if (rc) {
- dev_err(drv.dev,
- "vdd_core (cpu%d) increase failed (%d)\n",
- cpu, rc);
- return rc;
- }
- sc->vreg[VREG_CORE].cur_vdd = data->vdd_core;
- }
-
- return 0;
-}
-
-/* Apply any per-cpu voltage decreases. */
-static void decrease_vdd(int cpu, struct vdd_data *data,
- enum setrate_reason reason)
-{
- struct scalable *sc = &drv.scalable[cpu];
- int ret;
-
- /*
- * Update per-CPU core voltage. This must be called on the CPU
- * that's being affected. Don't do this in the hotplug remove path,
- * where the rail is off and we're executing on the other CPU.
- */
- if (data->vdd_core < sc->vreg[VREG_CORE].cur_vdd
- && reason != SETRATE_HOTPLUG) {
- ret = regulator_set_voltage(sc->vreg[VREG_CORE].reg,
- data->vdd_core, sc->vreg[VREG_CORE].max_vdd);
- if (ret) {
- dev_err(drv.dev,
- "vdd_core (cpu%d) decrease failed (%d)\n",
- cpu, ret);
- return;
- }
- sc->vreg[VREG_CORE].cur_vdd = data->vdd_core;
- }
-
- /* Decrease current request. */
- if (data->ua_core < sc->vreg[VREG_CORE].cur_ua) {
- ret = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
- data->ua_core);
- if (ret < 0) {
- dev_err(drv.dev, "regulator_set_optimum_mode(%s) failed (%d)\n",
- sc->vreg[VREG_CORE].name, ret);
- return;
- }
- sc->vreg[VREG_CORE].cur_ua = data->ua_core;
- }
-
- /* Decrease vdd_dig active-set vote. */
- if (data->vdd_dig < sc->vreg[VREG_DIG].cur_vdd) {
- ret = rpm_regulator_set_voltage(sc->vreg[VREG_DIG].rpm_reg,
- data->vdd_dig, sc->vreg[VREG_DIG].max_vdd);
- if (ret) {
- dev_err(drv.dev,
- "vdd_dig (cpu%d) decrease failed (%d)\n",
- cpu, ret);
- return;
- }
- sc->vreg[VREG_DIG].cur_vdd = data->vdd_dig;
- }
-
- /*
- * Decrease vdd_mem active-set after vdd_dig.
- * vdd_mem should be >= vdd_dig.
- */
- if (data->vdd_mem < sc->vreg[VREG_MEM].cur_vdd) {
- ret = rpm_regulator_set_voltage(sc->vreg[VREG_MEM].rpm_reg,
- data->vdd_mem, sc->vreg[VREG_MEM].max_vdd);
- if (ret) {
- dev_err(drv.dev,
- "vdd_mem (cpu%d) decrease failed (%d)\n",
- cpu, ret);
- return;
- }
- sc->vreg[VREG_MEM].cur_vdd = data->vdd_mem;
- }
-}
-
-static int calculate_vdd_mem(const struct acpu_level *tgt)
-{
- return drv.l2_freq_tbl[tgt->l2_level].vdd_mem;
-}
-
-static int get_src_dig(const struct core_speed *s)
-{
- const int *hfpll_vdd = drv.hfpll_data->vdd;
- const u32 low_vdd_l_max = drv.hfpll_data->low_vdd_l_max;
- const u32 nom_vdd_l_max = drv.hfpll_data->nom_vdd_l_max;
-
- if (s->src != HFPLL)
- return hfpll_vdd[HFPLL_VDD_NONE];
- else if (s->pll_l_val > nom_vdd_l_max)
- return hfpll_vdd[HFPLL_VDD_HIGH];
- else if (s->pll_l_val > low_vdd_l_max)
- return hfpll_vdd[HFPLL_VDD_NOM];
- else
- return hfpll_vdd[HFPLL_VDD_LOW];
-}
-
-static int calculate_vdd_dig(const struct acpu_level *tgt)
-{
- int l2_pll_vdd_dig, cpu_pll_vdd_dig;
-
- l2_pll_vdd_dig = get_src_dig(&drv.l2_freq_tbl[tgt->l2_level].speed);
- cpu_pll_vdd_dig = get_src_dig(&tgt->speed);
-
- return max(drv.l2_freq_tbl[tgt->l2_level].vdd_dig,
- max(l2_pll_vdd_dig, cpu_pll_vdd_dig));
-}
-
-static bool enable_boost = true;
-module_param_named(boost, enable_boost, bool, S_IRUGO | S_IWUSR);
-
-static int calculate_vdd_core(const struct acpu_level *tgt)
-{
- return tgt->vdd_core + (enable_boost ? drv.boost_uv : 0);
-}
-
-static DEFINE_MUTEX(l2_regulator_lock);
-static int l2_vreg_count;
-
-static int enable_l2_regulators(void)
-{
- int ret = 0;
-
- mutex_lock(&l2_regulator_lock);
- if (l2_vreg_count == 0) {
- ret = enable_rpm_vreg(&drv.scalable[L2].vreg[VREG_HFPLL_A]);
- if (ret)
- goto out;
- ret = enable_rpm_vreg(&drv.scalable[L2].vreg[VREG_HFPLL_B]);
- if (ret) {
- disable_rpm_vreg(&drv.scalable[L2].vreg[VREG_HFPLL_A]);
- goto out;
- }
- }
- l2_vreg_count++;
-out:
- mutex_unlock(&l2_regulator_lock);
-
- return ret;
-}
-
-static void disable_l2_regulators(void)
-{
- mutex_lock(&l2_regulator_lock);
-
- if (WARN(!l2_vreg_count, "L2 regulator votes are unbalanced!"))
- goto out;
-
- if (l2_vreg_count == 1) {
- disable_rpm_vreg(&drv.scalable[L2].vreg[VREG_HFPLL_B]);
- disable_rpm_vreg(&drv.scalable[L2].vreg[VREG_HFPLL_A]);
- }
- l2_vreg_count--;
-out:
- mutex_unlock(&l2_regulator_lock);
-}
-
-/* Set the CPU's clock rate and adjust the L2 rate, voltage and BW requests. */
-static int acpuclk_krait_set_rate(int cpu, unsigned long rate,
- enum setrate_reason reason)
-{
- const struct core_speed *strt_acpu_s, *tgt_acpu_s;
- const struct acpu_level *tgt;
- int tgt_l2_l;
- enum src_id prev_l2_src = NUM_SRC_ID;
- struct vdd_data vdd_data;
- bool skip_regulators;
- int rc = 0;
-
- if (cpu > num_possible_cpus())
- return -EINVAL;
-
- if (reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG)
- mutex_lock(&driver_lock);
-
- strt_acpu_s = drv.scalable[cpu].cur_speed;
-
- /* Return early if rate didn't change. */
- if (rate == strt_acpu_s->khz)
- goto out;
-
- /* Find target frequency. */
- for (tgt = drv.acpu_freq_tbl; tgt->speed.khz != 0; tgt++) {
- if (tgt->speed.khz == rate) {
- tgt_acpu_s = &tgt->speed;
- break;
- }
- }
- if (tgt->speed.khz == 0) {
- rc = -EINVAL;
- goto out;
- }
-
- /* Calculate voltage requirements for the current CPU. */
- vdd_data.vdd_mem = calculate_vdd_mem(tgt);
- vdd_data.vdd_dig = calculate_vdd_dig(tgt);
- vdd_data.vdd_core = calculate_vdd_core(tgt);
- vdd_data.ua_core = tgt->ua_core;
-
- /* Disable AVS before voltage switch */
- if (reason == SETRATE_CPUFREQ && drv.scalable[cpu].avs_enabled) {
- AVS_DISABLE(cpu);
- drv.scalable[cpu].avs_enabled = false;
- }
-
- /* Increase VDD levels if needed. */
- if (reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG) {
- rc = increase_vdd(cpu, &vdd_data, reason);
- if (rc)
- goto out;
-
- prev_l2_src =
- drv.l2_freq_tbl[drv.scalable[cpu].l2_vote].speed.src;
- /* Vote for the L2 regulators here if necessary. */
- if (drv.l2_freq_tbl[tgt->l2_level].speed.src == HFPLL) {
- rc = enable_l2_regulators();
- if (rc)
- goto out;
- }
- }
-
- dev_dbg(drv.dev, "Switching from ACPU%d rate %lu KHz -> %lu KHz\n",
- cpu, strt_acpu_s->khz, tgt_acpu_s->khz);
-
- /*
- * If we are setting the rate as part of power collapse or in the resume
- * path after power collapse, skip the vote for the HFPLL regulators,
- * which are active-set-only votes that will be removed when apps enters
- * its sleep set. This is needed to avoid voting for regulators with
- * sleeping APIs from an atomic context.
- */
- skip_regulators = (reason == SETRATE_PC);
-
- /* Set the new CPU speed. */
- set_speed(&drv.scalable[cpu], tgt_acpu_s, skip_regulators);
-
- /*
- * Update the L2 vote and apply the rate change. A spinlock is
- * necessary to ensure L2 rate is calculated and set atomically
- * with the CPU frequency, even if acpuclk_krait_set_rate() is
- * called from an atomic context and the driver_lock mutex is not
- * acquired.
- */
- spin_lock(&l2_lock);
- tgt_l2_l = compute_l2_level(&drv.scalable[cpu], tgt->l2_level);
- set_speed(&drv.scalable[L2],
- &drv.l2_freq_tbl[tgt_l2_l].speed, true);
- spin_unlock(&l2_lock);
-
- /* Nothing else to do for power collapse or SWFI. */
- if (reason == SETRATE_PC || reason == SETRATE_SWFI)
- goto out;
-
- /*
- * Remove the vote for the L2 HFPLL regulators only if the L2
- * was already on an HFPLL source.
- */
- if (prev_l2_src == HFPLL)
- disable_l2_regulators();
-
- /* Update bus bandwith request. */
- set_bus_bw(drv.l2_freq_tbl[tgt_l2_l].bw_level);
-
- /* Drop VDD levels if we can. */
- decrease_vdd(cpu, &vdd_data, reason);
-
- /* Re-enable AVS */
- if (reason == SETRATE_CPUFREQ && tgt->avsdscr_setting) {
- AVS_ENABLE(cpu, tgt->avsdscr_setting);
- drv.scalable[cpu].avs_enabled = true;
- }
-
- dev_dbg(drv.dev, "ACPU%d speed change complete\n", cpu);
-
-out:
- if (reason == SETRATE_CPUFREQ || reason == SETRATE_HOTPLUG)
- mutex_unlock(&driver_lock);
- return rc;
-}
-
-static struct acpuclk_data acpuclk_krait_data = {
- .set_rate = acpuclk_krait_set_rate,
- .get_rate = acpuclk_krait_get_rate,
-};
-
-/* Initialize a HFPLL at a given rate and enable it. */
-static void __cpuinit hfpll_init(struct scalable *sc,
- const struct core_speed *tgt_s)
-{
- dev_dbg(drv.dev, "Initializing HFPLL%d\n", sc - drv.scalable);
-
- /* Disable the PLL for re-programming. */
- hfpll_disable(sc, true);
-
- /* Configure PLL parameters for integer mode. */
- writel_relaxed(drv.hfpll_data->config_val,
- sc->hfpll_base + drv.hfpll_data->config_offset);
- writel_relaxed(0, sc->hfpll_base + drv.hfpll_data->m_offset);
- writel_relaxed(1, sc->hfpll_base + drv.hfpll_data->n_offset);
- if (drv.hfpll_data->has_user_reg)
- writel_relaxed(drv.hfpll_data->user_val,
- sc->hfpll_base + drv.hfpll_data->user_offset);
-
- /* Program droop controller, if supported */
- if (drv.hfpll_data->has_droop_ctl)
- writel_relaxed(drv.hfpll_data->droop_val,
- sc->hfpll_base + drv.hfpll_data->droop_offset);
-
- /* Set an initial PLL rate. */
- hfpll_set_rate(sc, tgt_s);
-}
-
-static int __cpuinit rpm_regulator_init(struct scalable *sc, enum vregs vreg,
- int vdd, bool enable)
-{
- int ret;
-
- if (!sc->vreg[vreg].name)
- return 0;
-
- sc->vreg[vreg].rpm_reg = rpm_regulator_get(drv.dev,
- sc->vreg[vreg].name);
- if (IS_ERR(sc->vreg[vreg].rpm_reg)) {
- ret = PTR_ERR(sc->vreg[vreg].rpm_reg);
- dev_err(drv.dev, "rpm_regulator_get(%s) failed (%d)\n",
- sc->vreg[vreg].name, ret);
- goto err_get;
- }
-
- ret = rpm_regulator_set_voltage(sc->vreg[vreg].rpm_reg, vdd,
- sc->vreg[vreg].max_vdd);
- if (ret) {
- dev_err(drv.dev, "%s initialization failed (%d)\n",
- sc->vreg[vreg].name, ret);
- goto err_conf;
- }
- sc->vreg[vreg].cur_vdd = vdd;
-
- if (enable) {
- ret = enable_rpm_vreg(&sc->vreg[vreg]);
- if (ret)
- goto err_conf;
- }
-
- return 0;
-
-err_conf:
- rpm_regulator_put(sc->vreg[vreg].rpm_reg);
-err_get:
- return ret;
-}
-
-static void __cpuinit rpm_regulator_cleanup(struct scalable *sc,
- enum vregs vreg)
-{
- if (!sc->vreg[vreg].rpm_reg)
- return;
-
- disable_rpm_vreg(&sc->vreg[vreg]);
- rpm_regulator_put(sc->vreg[vreg].rpm_reg);
-}
-
-/* Voltage regulator initialization. */
-static int __cpuinit regulator_init(struct scalable *sc,
- const struct acpu_level *acpu_level)
-{
- int ret, vdd_mem, vdd_dig, vdd_core;
-
- vdd_mem = calculate_vdd_mem(acpu_level);
- ret = rpm_regulator_init(sc, VREG_MEM, vdd_mem, true);
- if (ret)
- goto err_mem;
-
- vdd_dig = calculate_vdd_dig(acpu_level);
- ret = rpm_regulator_init(sc, VREG_DIG, vdd_dig, true);
- if (ret)
- goto err_dig;
-
- ret = rpm_regulator_init(sc, VREG_HFPLL_A,
- sc->vreg[VREG_HFPLL_A].max_vdd, false);
- if (ret)
- goto err_hfpll_a;
- ret = rpm_regulator_init(sc, VREG_HFPLL_B,
- sc->vreg[VREG_HFPLL_B].max_vdd, false);
- if (ret)
- goto err_hfpll_b;
-
- /* Setup Krait CPU regulators and initial core voltage. */
- sc->vreg[VREG_CORE].reg = regulator_get(drv.dev,
- sc->vreg[VREG_CORE].name);
- if (IS_ERR(sc->vreg[VREG_CORE].reg)) {
- ret = PTR_ERR(sc->vreg[VREG_CORE].reg);
- dev_err(drv.dev, "regulator_get(%s) failed (%d)\n",
- sc->vreg[VREG_CORE].name, ret);
- goto err_core_get;
- }
- ret = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
- acpu_level->ua_core);
- if (ret < 0) {
- dev_err(drv.dev, "regulator_set_optimum_mode(%s) failed (%d)\n",
- sc->vreg[VREG_CORE].name, ret);
- goto err_core_conf;
- }
- sc->vreg[VREG_CORE].cur_ua = acpu_level->ua_core;
- vdd_core = calculate_vdd_core(acpu_level);
- ret = regulator_set_voltage(sc->vreg[VREG_CORE].reg, vdd_core,
- sc->vreg[VREG_CORE].max_vdd);
- if (ret) {
- dev_err(drv.dev, "regulator_set_voltage(%s) (%d)\n",
- sc->vreg[VREG_CORE].name, ret);
- goto err_core_conf;
- }
- sc->vreg[VREG_CORE].cur_vdd = vdd_core;
- ret = regulator_enable(sc->vreg[VREG_CORE].reg);
- if (ret) {
- dev_err(drv.dev, "regulator_enable(%s) failed (%d)\n",
- sc->vreg[VREG_CORE].name, ret);
- goto err_core_conf;
- }
-
- /*
- * Vote for the L2 HFPLL regulators if _this_ CPU's frequency requires
- * a corresponding target L2 frequency that needs the L2 an HFPLL.
- */
- if (drv.l2_freq_tbl[acpu_level->l2_level].speed.src == HFPLL) {
- ret = enable_l2_regulators();
- if (ret) {
- dev_err(drv.dev, "enable_l2_regulators() failed (%d)\n",
- ret);
- goto err_l2_regs;
- }
- }
-
- return 0;
-
-err_l2_regs:
- regulator_disable(sc->vreg[VREG_CORE].reg);
-err_core_conf:
- regulator_put(sc->vreg[VREG_CORE].reg);
-err_core_get:
- rpm_regulator_cleanup(sc, VREG_HFPLL_B);
-err_hfpll_b:
- rpm_regulator_cleanup(sc, VREG_HFPLL_A);
-err_hfpll_a:
- rpm_regulator_cleanup(sc, VREG_DIG);
-err_dig:
- rpm_regulator_cleanup(sc, VREG_MEM);
-err_mem:
- return ret;
-}
-
-static void __cpuinit regulator_cleanup(struct scalable *sc)
-{
- regulator_disable(sc->vreg[VREG_CORE].reg);
- regulator_put(sc->vreg[VREG_CORE].reg);
- rpm_regulator_cleanup(sc, VREG_HFPLL_B);
- rpm_regulator_cleanup(sc, VREG_HFPLL_A);
- rpm_regulator_cleanup(sc, VREG_DIG);
- rpm_regulator_cleanup(sc, VREG_MEM);
-}
-
-/* Set initial rate for a given core. */
-static int __cpuinit init_clock_sources(struct scalable *sc,
- const struct core_speed *tgt_s)
-{
- u32 regval;
- void __iomem *aux_reg;
-
- /* Program AUX source input to the secondary MUX. */
- if (sc->aux_clk_sel_phys) {
- aux_reg = ioremap(sc->aux_clk_sel_phys, 4);
- if (!aux_reg)
- return -ENOMEM;
- writel_relaxed(sc->aux_clk_sel, aux_reg);
- iounmap(aux_reg);
- }
-
- /* Switch away from the HFPLL while it's re-initialized. */
- set_sec_clk_src(sc, sc->sec_clk_sel);
- set_pri_clk_src(sc, PRI_SRC_SEL_SEC_SRC);
- hfpll_init(sc, tgt_s);
-
- /* Set PRI_SRC_SEL_HFPLL_DIV2 divider to div-2. */
- regval = get_l2_indirect_reg(sc->l2cpmr_iaddr);
- regval &= ~(0x3 << 6);
- if (sc != &drv.scalable[L2])
- regval &= ~(0x3 << 14);
- set_l2_indirect_reg(sc->l2cpmr_iaddr, regval);
-
- /* Enable and switch to the target clock source. */
- if (tgt_s->src == HFPLL)
- hfpll_enable(sc, false);
- set_pri_clk_src(sc, tgt_s->pri_src_sel);
- sc->cur_speed = tgt_s;
-
- return 0;
-}
-
-static void __cpuinit fill_cur_core_speed(struct core_speed *s,
- struct scalable *sc)
-{
- s->pri_src_sel = get_l2_indirect_reg(sc->l2cpmr_iaddr) & 0x3;
- s->pll_l_val = readl_relaxed(sc->hfpll_base + drv.hfpll_data->l_offset);
-}
-
-static bool __cpuinit speed_equal(const struct core_speed *s1,
- const struct core_speed *s2)
-{
- return (s1->pri_src_sel == s2->pri_src_sel &&
- s1->pll_l_val == s2->pll_l_val);
-}
-
-static const struct acpu_level __cpuinit *find_cur_acpu_level(int cpu)
-{
- struct scalable *sc = &drv.scalable[cpu];
- const struct acpu_level *l;
- struct core_speed cur_speed;
-
- fill_cur_core_speed(&cur_speed, sc);
- for (l = drv.acpu_freq_tbl; l->speed.khz != 0; l++)
- if (speed_equal(&l->speed, &cur_speed))
- return l;
- return NULL;
-}
-
-static const struct l2_level __init *find_cur_l2_level(void)
-{
- struct scalable *sc = &drv.scalable[L2];
- const struct l2_level *l;
- struct core_speed cur_speed;
-
- fill_cur_core_speed(&cur_speed, sc);
- for (l = drv.l2_freq_tbl; l->speed.khz != 0; l++)
- if (speed_equal(&l->speed, &cur_speed))
- return l;
- return NULL;
-}
-
-static const struct acpu_level __cpuinit *find_min_acpu_level(void)
-{
- struct acpu_level *l;
-
- for (l = drv.acpu_freq_tbl; l->speed.khz != 0; l++)
- if (l->use_for_scaling)
- return l;
-
- return NULL;
-}
-
-static int __cpuinit per_cpu_init(int cpu)
-{
- struct scalable *sc = &drv.scalable[cpu];
- const struct acpu_level *acpu_level;
- int ret;
-
- sc->hfpll_base = ioremap(sc->hfpll_phys_base, SZ_32);
- if (!sc->hfpll_base) {
- ret = -ENOMEM;
- goto err_ioremap;
- }
-
- acpu_level = find_cur_acpu_level(cpu);
- if (!acpu_level) {
- acpu_level = find_min_acpu_level();
- if (!acpu_level) {
- ret = -ENODEV;
- goto err_table;
- }
- dev_warn(drv.dev, "CPU%d is running at an unknown rate. Defaulting to %lu KHz.\n",
- cpu, acpu_level->speed.khz);
- } else {
- dev_dbg(drv.dev, "CPU%d is running at %lu KHz\n", cpu,
- acpu_level->speed.khz);
- }
-
- ret = regulator_init(sc, acpu_level);
- if (ret)
- goto err_regulators;
-
- ret = init_clock_sources(sc, &acpu_level->speed);
- if (ret)
- goto err_clocks;
-
- sc->l2_vote = acpu_level->l2_level;
- sc->initialized = true;
-
- return 0;
-
-err_clocks:
- regulator_cleanup(sc);
-err_regulators:
-err_table:
- iounmap(sc->hfpll_base);
-err_ioremap:
- return ret;
-}
-
-/* Register with bus driver. */
-static void __init bus_init(const struct l2_level *l2_level)
-{
- int ret;
-
- drv.bus_perf_client = msm_bus_scale_register_client(drv.bus_scale);
- if (!drv.bus_perf_client) {
- dev_err(drv.dev, "unable to register bus client\n");
- BUG();
- }
-
- ret = msm_bus_scale_client_update_request(drv.bus_perf_client,
- l2_level->bw_level);
- if (ret)
- dev_err(drv.dev, "initial bandwidth req failed (%d)\n", ret);
-}
-
-#ifdef CONFIG_CPU_FREQ_MSM
-static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
-
-static void __init cpufreq_table_init(void)
-{
- int cpu;
- int freq_cnt = 0;
-
- for_each_possible_cpu(cpu) {
- int i;
- /* Construct the freq_table tables from acpu_freq_tbl. */
- for (i = 0, freq_cnt = 0; drv.acpu_freq_tbl[i].speed.khz != 0
- && freq_cnt < ARRAY_SIZE(*freq_table); i++) {
- if (drv.acpu_freq_tbl[i].use_for_scaling) {
- freq_table[cpu][freq_cnt].index = freq_cnt;
- freq_table[cpu][freq_cnt].frequency
- = drv.acpu_freq_tbl[i].speed.khz;
- freq_cnt++;
- }
- }
- /* freq_table not big enough to store all usable freqs. */
- BUG_ON(drv.acpu_freq_tbl[i].speed.khz != 0);
-
- freq_table[cpu][freq_cnt].index = freq_cnt;
- freq_table[cpu][freq_cnt].frequency = CPUFREQ_TABLE_END;
-
- /* Register table with CPUFreq. */
- cpufreq_frequency_table_get_attr(freq_table[cpu], cpu);
- }
-
- dev_info(drv.dev, "CPU Frequencies Supported: %d\n", freq_cnt);
-}
-#else
-static void __init cpufreq_table_init(void) {}
-#endif
-
-static void __init dcvs_freq_init(void)
-{
- int i;
-
- for (i = 0; drv.acpu_freq_tbl[i].speed.khz != 0; i++)
- if (drv.acpu_freq_tbl[i].use_for_scaling)
- msm_dcvs_register_cpu_freq(
- drv.acpu_freq_tbl[i].speed.khz,
- drv.acpu_freq_tbl[i].vdd_core / 1000);
-}
-
-static int __cpuinit acpuclk_cpu_callback(struct notifier_block *nfb,
- unsigned long action, void *hcpu)
-{
- static int prev_khz[NR_CPUS];
- int rc, cpu = (int)hcpu;
- struct scalable *sc = &drv.scalable[cpu];
- unsigned long hot_unplug_khz = acpuclk_krait_data.power_collapse_khz;
-
- switch (action & ~CPU_TASKS_FROZEN) {
- case CPU_DEAD:
- prev_khz[cpu] = acpuclk_krait_get_rate(cpu);
- /* Fall through. */
- case CPU_UP_CANCELED:
- acpuclk_krait_set_rate(cpu, hot_unplug_khz, SETRATE_HOTPLUG);
-
- regulator_disable(sc->vreg[VREG_CORE].reg);
- regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg, 0);
- regulator_set_voltage(sc->vreg[VREG_CORE].reg, 0,
- sc->vreg[VREG_CORE].max_vdd);
- break;
- case CPU_UP_PREPARE:
- if (!sc->initialized) {
- rc = per_cpu_init(cpu);
- if (rc)
- return NOTIFY_BAD;
- break;
- }
- if (WARN_ON(!prev_khz[cpu]))
- return NOTIFY_BAD;
-
- rc = regulator_set_voltage(sc->vreg[VREG_CORE].reg,
- sc->vreg[VREG_CORE].cur_vdd,
- sc->vreg[VREG_CORE].max_vdd);
- if (rc < 0)
- return NOTIFY_BAD;
- rc = regulator_set_optimum_mode(sc->vreg[VREG_CORE].reg,
- sc->vreg[VREG_CORE].cur_ua);
- if (rc < 0)
- return NOTIFY_BAD;
- rc = regulator_enable(sc->vreg[VREG_CORE].reg);
- if (rc < 0)
- return NOTIFY_BAD;
-
- acpuclk_krait_set_rate(cpu, prev_khz[cpu], SETRATE_HOTPLUG);
- break;
- default:
- break;
- }
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block __cpuinitdata acpuclk_cpu_notifier = {
- .notifier_call = acpuclk_cpu_callback,
-};
-
-static const int __init krait_needs_vmin(void)
-{
- switch (read_cpuid_id()) {
- case 0x511F04D0: /* KR28M2A20 */
- case 0x511F04D1: /* KR28M2A21 */
- case 0x510F06F0: /* KR28M4A10 */
- return 1;
- default:
- return 0;
- };
-}
-
-static void __init krait_apply_vmin(struct acpu_level *tbl)
-{
- for (; tbl->speed.khz != 0; tbl++) {
- if (tbl->vdd_core < 1150000)
- tbl->vdd_core = 1150000;
- tbl->avsdscr_setting = 0;
- }
-}
-
-void __init get_krait_bin_format_a(void __iomem *base, struct bin_info *bin)
-{
- u32 pte_efuse = readl_relaxed(base);
-
- bin->speed = pte_efuse & 0xF;
- if (bin->speed == 0xF)
- bin->speed = (pte_efuse >> 4) & 0xF;
- bin->speed_valid = bin->speed != 0xF;
-
- bin->pvs = (pte_efuse >> 10) & 0x7;
- if (bin->pvs == 0x7)
- bin->pvs = (pte_efuse >> 13) & 0x7;
- bin->pvs_valid = bin->pvs != 0x7;
-}
-
-void __init get_krait_bin_format_b(void __iomem *base, struct bin_info *bin)
-{
- u32 pte_efuse, redundant_sel;
-
- pte_efuse = readl_relaxed(base);
- redundant_sel = (pte_efuse >> 24) & 0x7;
- bin->pvs_rev = (pte_efuse >> 4) & 0x3;
- bin->speed = pte_efuse & 0x7;
- /* PVS number is in bits 31, 8, 7, 6 */
- bin->pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
-
- switch (redundant_sel) {
- case 1:
- bin->speed = (pte_efuse >> 27) & 0xF;
- break;
- case 2:
- bin->pvs = (pte_efuse >> 27) & 0xF;
- break;
- }
- bin->speed_valid = true;
-
- /* Check PVS_BLOW_STATUS */
- pte_efuse = readl_relaxed(base + 0x4);
- bin->pvs_valid = !!(pte_efuse & BIT(21));
-}
-
-static struct pvs_table * __init select_freq_plan(
- const struct acpuclk_krait_params *params)
-{
- void __iomem *pte_efuse_base;
- struct bin_info bin;
-
- pte_efuse_base = ioremap(params->pte_efuse_phys, 8);
- if (!pte_efuse_base) {
- dev_err(drv.dev, "Unable to map PTE eFuse base\n");
- return NULL;
- }
- params->get_bin_info(pte_efuse_base, &bin);
- iounmap(pte_efuse_base);
-
- if (bin.speed_valid) {
- drv.speed_bin = bin.speed;
- dev_info(drv.dev, "SPEED BIN: %d\n", drv.speed_bin);
- } else {
- drv.speed_bin = 0;
- dev_warn(drv.dev, "SPEED BIN: Defaulting to %d\n",
- drv.speed_bin);
- }
-
- if (bin.pvs_valid) {
- drv.pvs_bin = bin.pvs;
- dev_info(drv.dev, "ACPU PVS: %d\n", drv.pvs_bin);
- drv.pvs_rev = bin.pvs_rev;
- dev_info(drv.dev, "ACPU PVS REVISION: %d\n", drv.pvs_rev);
- } else {
- drv.pvs_bin = 0;
- dev_warn(drv.dev, "ACPU PVS: Defaulting to %d\n",
- drv.pvs_bin);
- }
-
- return ¶ms->pvs_tables[drv.pvs_rev][drv.speed_bin][drv.pvs_bin];
-}
-
-static void __init drv_data_init(struct device *dev,
- const struct acpuclk_krait_params *params)
-{
- struct pvs_table *pvs;
-
- drv.dev = dev;
- drv.scalable = kmemdup(params->scalable, params->scalable_size,
- GFP_KERNEL);
- BUG_ON(!drv.scalable);
-
- drv.hfpll_data = kmemdup(params->hfpll_data, sizeof(*drv.hfpll_data),
- GFP_KERNEL);
- BUG_ON(!drv.hfpll_data);
-
- drv.l2_freq_tbl = kmemdup(params->l2_freq_tbl, params->l2_freq_tbl_size,
- GFP_KERNEL);
- BUG_ON(!drv.l2_freq_tbl);
-
- drv.bus_scale = kmemdup(params->bus_scale, sizeof(*drv.bus_scale),
- GFP_KERNEL);
- BUG_ON(!drv.bus_scale);
- drv.bus_scale->usecase = kmemdup(drv.bus_scale->usecase,
- drv.bus_scale->num_usecases * sizeof(*drv.bus_scale->usecase),
- GFP_KERNEL);
- BUG_ON(!drv.bus_scale->usecase);
-
- pvs = select_freq_plan(params);
- BUG_ON(!pvs->table);
-
- drv.acpu_freq_tbl = kmemdup(pvs->table, pvs->size, GFP_KERNEL);
- BUG_ON(!drv.acpu_freq_tbl);
- drv.boost_uv = pvs->boost_uv;
-
- acpuclk_krait_data.power_collapse_khz = params->stby_khz;
- acpuclk_krait_data.wait_for_irq_khz = params->stby_khz;
-}
-
-static void __init hw_init(void)
-{
- struct scalable *l2 = &drv.scalable[L2];
- const struct l2_level *l2_level;
- int cpu, rc;
-
- if (krait_needs_vmin())
- krait_apply_vmin(drv.acpu_freq_tbl);
-
- l2->hfpll_base = ioremap(l2->hfpll_phys_base, SZ_32);
- BUG_ON(!l2->hfpll_base);
-
- rc = rpm_regulator_init(l2, VREG_HFPLL_A,
- l2->vreg[VREG_HFPLL_A].max_vdd, false);
- BUG_ON(rc);
- rc = rpm_regulator_init(l2, VREG_HFPLL_B,
- l2->vreg[VREG_HFPLL_B].max_vdd, false);
- BUG_ON(rc);
-
- l2_level = find_cur_l2_level();
- if (!l2_level) {
- l2_level = drv.l2_freq_tbl;
- dev_warn(drv.dev, "L2 is running at an unknown rate. Defaulting to %lu KHz.\n",
- l2_level->speed.khz);
- } else {
- dev_dbg(drv.dev, "L2 is running at %lu KHz\n",
- l2_level->speed.khz);
- }
-
- rc = init_clock_sources(l2, &l2_level->speed);
- BUG_ON(rc);
-
- for_each_online_cpu(cpu) {
- rc = per_cpu_init(cpu);
- BUG_ON(rc);
- }
-
- bus_init(l2_level);
-}
-
-int __init acpuclk_krait_init(struct device *dev,
- const struct acpuclk_krait_params *params)
-{
- drv_data_init(dev, params);
- hw_init();
-
- cpufreq_table_init();
- dcvs_freq_init();
- acpuclk_register(&acpuclk_krait_data);
- register_hotcpu_notifier(&acpuclk_cpu_notifier);
-
- acpuclk_krait_debug_init(&drv);
-
- return 0;
-}
diff --git a/arch/arm/mach-msm/acpuclock-krait.h b/arch/arm/mach-msm/acpuclock-krait.h
deleted file mode 100644
index 4eff45d..0000000
--- a/arch/arm/mach-msm/acpuclock-krait.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_KRAIT_H
-#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_KRAIT_H
-
-#define L2(x) (x)
-#define BW_MBPS(_bw) \
- { \
- .vectors = (struct msm_bus_vectors[]){ \
- {\
- .src = MSM_BUS_MASTER_AMPSS_M0, \
- .dst = MSM_BUS_SLAVE_EBI_CH0, \
- .ib = (_bw) * 1000000ULL, \
- }, \
- { \
- .src = MSM_BUS_MASTER_AMPSS_M1, \
- .dst = MSM_BUS_SLAVE_EBI_CH0, \
- .ib = (_bw) * 1000000ULL, \
- }, \
- }, \
- .num_paths = 2, \
- }
-
-/**
- * src_id - Clock source IDs.
- */
-enum src_id {
- PLL_0 = 0,
- HFPLL,
- PLL_8,
- NUM_SRC_ID
-};
-
-/**
- * enum pvs - IDs to distinguish between CPU frequency tables.
- */
-enum pvs {
- PVS_SLOW = 0,
- PVS_NOMINAL = 1,
- PVS_FAST = 3,
- PVS_FASTER = 4,
- NUM_PVS = 16
-};
-
-/**
- * The maximum number of PVS revisions.
- */
-#define NUM_PVS_REVS (4)
-
-/**
- * The maximum number of speed bins.
- */
-#define NUM_SPEED_BINS (16)
-
-/**
- * enum scalables - IDs of frequency scalable hardware blocks.
- */
-enum scalables {
- CPU0 = 0,
- CPU1,
- CPU2,
- CPU3,
- L2,
- MAX_SCALABLES
-};
-
-
-/**
- * enum hfpll_vdd_level - IDs of HFPLL voltage levels.
- */
-enum hfpll_vdd_levels {
- HFPLL_VDD_NONE,
- HFPLL_VDD_LOW,
- HFPLL_VDD_NOM,
- HFPLL_VDD_HIGH,
- NUM_HFPLL_VDD
-};
-
-/**
- * enum vregs - IDs of voltage regulators.
- */
-enum vregs {
- VREG_CORE,
- VREG_MEM,
- VREG_DIG,
- VREG_HFPLL_A,
- VREG_HFPLL_B,
- NUM_VREG
-};
-
-/**
- * struct vreg - Voltage regulator data.
- * @name: Name of requlator.
- * @max_vdd: Limit the maximum-settable voltage.
- * @reg: Regulator handle.
- * @rpm_reg: RPM Regulator handle.
- * @cur_vdd: Last-set voltage in uV.
- * @cur_ua: Last-set current in uA.
- */
-struct vreg {
- const char *name;
- const int max_vdd;
- struct regulator *reg;
- struct rpm_regulator *rpm_reg;
- int cur_vdd;
- int cur_ua;
-};
-
-/**
- * struct core_speed - Clock tree and configuration parameters.
- * @khz: Clock rate in KHz.
- * @src: Clock source ID.
- * @pri_src_sel: Input to select on the primary MUX.
- * @pll_l_val: HFPLL "L" value to be applied when an HFPLL source is selected.
- */
-struct core_speed {
- unsigned long khz;
- int src;
- u32 pri_src_sel;
- u32 pll_l_val;
-};
-
-/**
- * struct l2_level - L2 clock rate and associated voltage and b/w requirements.
- * @speed: L2 clock configuration.
- * @vdd_dig: vdd_dig voltage in uV.
- * @vdd_mem: vdd_mem voltage in uV.
- * @bw_level: Bandwidth performance level number.
- */
-struct l2_level {
- const struct core_speed speed;
- const int vdd_dig;
- const int vdd_mem;
- const unsigned int bw_level;
-};
-
-/**
- * struct acpu_level - CPU clock rate and L2 rate and voltage requirements.
- * @use_for_scaling: Flag indicating whether or not the level should be used.
- * @speed: CPU clock configuration.
- * @l2_level: L2 configuration to use.
- * @vdd_core: CPU core voltage in uV.
- * @ua_core: CPU core current consumption in uA.
- * @avsdscr_setting: AVS DSCR configuration.
- */
-struct acpu_level {
- const int use_for_scaling;
- const struct core_speed speed;
- unsigned int l2_level;
- int vdd_core;
- int ua_core;
- unsigned int avsdscr_setting;
-};
-
-/**
- * struct hfpll_data - Descriptive data of HFPLL hardware.
- * @mode_offset: Mode register offset from base address.
- * @l_offset: "L" value register offset from base address.
- * @m_offset: "M" value register offset from base address.
- * @n_offset: "N" value register offset from base address.
- * @config_offset: Configuration register offset from base address.
- * @config_val: Value to initialize the @config_offset register to.
- * @has_user_reg: Indicates the presence of an addition config register.
- * @user_offset: User register offset from base address, if applicable.
- * @user_val: Value to initialize the @user_offset register to.
- * @user_vco_mask: Bit in the @user_offset to enable high-frequency VCO mode.
- * @has_droop_ctl: Indicates the presence of a voltage droop controller.
- * @has_lock_status: Indicates the presence of a lock status bit.
- * @droop_offset: Droop controller register offset from base address.
- * @droop_val: Value to initialize the @config_offset register to.
- * @status_offset: PLL status register offset.
- * @low_vdd_l_max: Maximum "L" value supported at HFPLL_VDD_LOW.
- * @nom_vdd_l_max: Maximum "L" value supported at HFPLL_VDD_NOM.
- * @low_vco_l_max: Maximum "L" value supported in low-frequency VCO mode.
- * @vdd: voltage requirements for each VDD level for the L2 PLL.
- */
-struct hfpll_data {
- const u32 mode_offset;
- const u32 l_offset;
- const u32 m_offset;
- const u32 n_offset;
- const u32 config_offset;
- const u32 config_val;
- const bool has_user_reg;
- const u32 user_offset;
- const u32 user_val;
- const u32 user_vco_mask;
- const bool has_droop_ctl;
- const bool has_lock_status;
- const u32 droop_offset;
- const u32 droop_val;
- const u32 status_offset;
- u32 low_vdd_l_max;
- u32 nom_vdd_l_max;
- const u32 low_vco_l_max;
- const int vdd[NUM_HFPLL_VDD];
-};
-
-/**
- * struct scalable - Register locations and state associated with a scalable HW.
- * @hfpll_phys_base: Physical base address of HFPLL register.
- * @hfpll_base: Virtual base address of HFPLL registers.
- * @aux_clk_sel_phys: Physical address of auxiliary MUX.
- * @aux_clk_sel: Auxiliary mux input to select at boot.
- * @sec_clk_sel: Secondary mux input to select at boot.
- * @l2cpmr_iaddr: Indirect address of the CPMR MUX/divider CP15 register.
- * @cur_speed: Pointer to currently-set speed.
- * @l2_vote: L2 performance level vote associate with the current CPU speed.
- * @vreg: Array of voltage regulators needed by the scalable.
- * @initialized: Flag set to true when per_cpu_init() has been called.
- * @avs_enabled: True if avs is enabled for the scalabale. False otherwise.
- */
-struct scalable {
- const phys_addr_t hfpll_phys_base;
- void __iomem *hfpll_base;
- const phys_addr_t aux_clk_sel_phys;
- const u32 aux_clk_sel;
- const u32 sec_clk_sel;
- const u32 l2cpmr_iaddr;
- const struct core_speed *cur_speed;
- unsigned int l2_vote;
- struct vreg vreg[NUM_VREG];
- bool initialized;
- bool avs_enabled;
-};
-
-/**
- * struct bin_info - Hardware speed and voltage binning info.
- * @speed_valid: @speed field is valid
- * @pvs_valid: @pvs field is valid
- * @speed: Speed bin ID
- * @pvs: PVS bin ID
- * @pvs_rev: PVS revision ID
- */
-struct bin_info {
- bool speed_valid;
- bool pvs_valid;
- int speed;
- int pvs;
- int pvs_rev;
-};
-
-/**
- * struct pvs_table - CPU performance level table and size.
- * @table: CPU performance level table
- * @size: sizeof(@table)
- * @boost_uv: Voltage boost amount
- */
-struct pvs_table {
- struct acpu_level *table;
- size_t size;
- int boost_uv;
-};
-
-/**
- * struct acpuclk_krait_params - SoC specific driver parameters.
- * @scalable: Array of scalables.
- * @scalable_size: Size of @scalable.
- * @hfpll_data: HFPLL configuration data.
- * @pvs_tables: 2D array of CPU frequency tables.
- * @l2_freq_tbl: L2 frequency table.
- * @l2_freq_tbl_size: Size of @l2_freq_tbl.
- * @pte_efuse_phys: Physical address of PTE EFUSE.
- * @get_bin_info: Function to populate bin_info from pte_efuse.
- * @bus_scale: MSM bus driver parameters.
- * @stby_khz: KHz value corresponding to an always-on clock source.
- */
-struct acpuclk_krait_params {
- struct scalable *scalable;
- size_t scalable_size;
- struct hfpll_data *hfpll_data;
- struct pvs_table (*pvs_tables)[NUM_SPEED_BINS][NUM_PVS];
- struct l2_level *l2_freq_tbl;
- size_t l2_freq_tbl_size;
- phys_addr_t pte_efuse_phys;
- void (*get_bin_info)(void __iomem *base, struct bin_info *bin);
- struct msm_bus_scale_pdata *bus_scale;
- unsigned long stby_khz;
-};
-
-/**
- * struct drv_data - Driver state
- * @acpu_freq_tbl: CPU frequency table.
- * @l2_freq_tbl: L2 frequency table.
- * @scalable: Array of scalables (CPUs and L2).
- * @hfpll_data: High-frequency PLL data.
- * @bus_perf_client: Bus driver client handle.
- * @bus_scale: Bus driver scaling data.
- * @boost_uv: Voltage boost amount
- * @speed_bin: Speed bin ID.
- * @pvs_bin: PVS bin ID.
- * @pvs_bin: PVS revision ID.
- * @dev: Device.
- */
-struct drv_data {
- struct acpu_level *acpu_freq_tbl;
- const struct l2_level *l2_freq_tbl;
- struct scalable *scalable;
- struct hfpll_data *hfpll_data;
- u32 bus_perf_client;
- struct msm_bus_scale_pdata *bus_scale;
- int boost_uv;
- int speed_bin;
- int pvs_bin;
- int pvs_rev;
- struct device *dev;
-};
-
-/**
- * struct acpuclk_platform_data - PMIC configuration data.
- * @uses_pm8917: Boolean indicates presence of pm8917.
- */
-struct acpuclk_platform_data {
- bool uses_pm8917;
-};
-
-/**
- * get_krait_bin_format_a - Populate bin_info from a 'Format A' pte_efuse
- */
-void __init get_krait_bin_format_a(void __iomem *base, struct bin_info *bin);
-
-/**
- * get_krait_bin_format_b - Populate bin_info from a 'Format B' pte_efuse
- */
-void __init get_krait_bin_format_b(void __iomem *base, struct bin_info *bin);
-
-/**
- * acpuclk_krait_init - Initialize the Krait CPU clock driver give SoC params.
- */
-extern int acpuclk_krait_init(struct device *dev,
- const struct acpuclk_krait_params *params);
-
-#ifdef CONFIG_DEBUG_FS
-/**
- * acpuclk_krait_debug_init - Initialize debugfs interface.
- */
-extern void __init acpuclk_krait_debug_init(struct drv_data *drv);
-#else
-static inline void acpuclk_krait_debug_init(void) { }
-#endif
-
-#endif
diff --git a/arch/arm/mach-msm/board-8610-gpiomux.c b/arch/arm/mach-msm/board-8610-gpiomux.c
index b5ea3a5..affe6bd 100644
--- a/arch/arm/mach-msm/board-8610-gpiomux.c
+++ b/arch/arm/mach-msm/board-8610-gpiomux.c
@@ -252,6 +252,30 @@
},
};
+static struct gpiomux_setting gpio_i2c_nfc_pvt_config = {
+ .func = GPIOMUX_FUNC_5, /*active 1*/ /* 0 */
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_NONE,
+ };
+
+static struct msm_gpiomux_config msm_nfc_configs[] __initdata = {
+ {
+ .gpio = 8, /* BLSP1 QUP2 I2C_SDA */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &gpio_i2c_nfc_pvt_config,
+ [GPIOMUX_SUSPENDED] = &gpio_i2c_nfc_pvt_config,
+ },
+ },
+ {
+ .gpio = 9, /* BLSP1 QUP2 I2C_SCL */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &gpio_i2c_nfc_pvt_config,
+ [GPIOMUX_SUSPENDED] = &gpio_i2c_nfc_pvt_config,
+ },
+ },
+};
+
+
static struct msm_gpiomux_config msm_atmel_configs[] __initdata = {
{
.gpio = 0, /* TOUCH RESET */
@@ -427,6 +451,16 @@
},
};
+static struct msm_gpiomux_config msm_non_qrd_configs[] __initdata = {
+ {
+ .gpio = 8, /* CAM1_STANDBY_N */
+ .settings = {
+ [GPIOMUX_ACTIVE] = &cam_settings[3],
+ [GPIOMUX_SUSPENDED] = &gpio_suspend_config[1],
+ },
+ },
+};
+
static struct msm_gpiomux_config msm_sensor_configs[] __initdata = {
{
.gpio = 13, /* CAM_MCLK0 */
@@ -597,6 +631,28 @@
},
};
+static struct gpiomux_setting gpio_cdc_dmic_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_4MA,
+ .pull = GPIOMUX_PULL_NONE,
+};
+
+
+static struct msm_gpiomux_config msm_cdc_dmic_configs[] __initdata = {
+ {
+ .gpio = 100, /* DMIC CLK */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_cdc_dmic_cfg,
+ },
+ },
+ {
+ .gpio = 101, /* DMIC DATA */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_cdc_dmic_cfg,
+ },
+ },
+};
+
void __init msm8610_init_gpiomux(void)
{
int rc;
@@ -625,7 +681,16 @@
msm_gpiomux_install(msm_sensor_configs, ARRAY_SIZE(msm_sensor_configs));
msm_gpiomux_install(msm_gpio_int_configs,
ARRAY_SIZE(msm_gpio_int_configs));
- if (of_board_is_qrd())
+ if (of_board_is_qrd()) {
msm_gpiomux_install(msm_interrupt_configs,
ARRAY_SIZE(msm_interrupt_configs));
+ msm_gpiomux_install(msm_nfc_configs,
+ ARRAY_SIZE(msm_nfc_configs));
+ } else {
+ msm_gpiomux_install(msm_non_qrd_configs,
+ ARRAY_SIZE(msm_non_qrd_configs));
+ }
+ if (of_board_is_cdp())
+ msm_gpiomux_install(msm_cdc_dmic_configs,
+ ARRAY_SIZE(msm_cdc_dmic_configs));
}
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index d79464a..2050f38 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -98,7 +98,6 @@
#include "pm-boot.h"
#include "msm_watchdog.h"
#include "board-8930.h"
-#include "acpuclock-krait.h"
#include "platsmp.h"
static struct platform_device msm_fm_platform_init = {
@@ -2655,8 +2654,6 @@
/* Modify platform data values to match requirements for PM8917. */
static void __init msm8930_pm8917_pdata_fixup(void)
{
- struct acpuclk_platform_data *pdata;
-
msm8930_pm8917_wcd9xxx_pdata_fixup(&sitar_platform_data);
msm8930_pm8917_wcd9xxx_pdata_fixup(&sitar1p1_platform_data);
@@ -2672,12 +2669,6 @@
msm8930_device_rpm_regulator.dev.platform_data
= &msm8930_pm8917_rpm_regulator_pdata;
-
- pdata = msm8930_device_acpuclk.dev.platform_data;
- pdata->uses_pm8917 = true;
-
- pdata = msm8930ab_device_acpuclk.dev.platform_data;
- pdata->uses_pm8917 = true;
}
static void __init msm8930ab_update_retention_spm(void)
diff --git a/arch/arm/mach-msm/board-8974-gpiomux.c b/arch/arm/mach-msm/board-8974-gpiomux.c
old mode 100644
new mode 100755
index c35a607..8ab916c
--- a/arch/arm/mach-msm/board-8974-gpiomux.c
+++ b/arch/arm/mach-msm/board-8974-gpiomux.c
@@ -640,6 +640,18 @@
[GPIOMUX_SUSPENDED] = &gpio_uart_config,
},
},
+ { /* NFC */
+ .gpio = 29, /* BLSP1 QUP6 I2C_DAT */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_i2c_config,
+ },
+ },
+ { /* NFC */
+ .gpio = 30, /* BLSP1 QUP6 I2C_CLK */
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &gpio_i2c_config,
+ },
+ },
{
.gpio = 53, /* BLSP2 QUP4 SPI_DATA_MOSI */
.settings = {
diff --git a/arch/arm/mach-msm/board-8974.c b/arch/arm/mach-msm/board-8974.c
index 80a957f..7b13bbc 100644
--- a/arch/arm/mach-msm/board-8974.c
+++ b/arch/arm/mach-msm/board-8974.c
@@ -108,6 +108,11 @@
msm_thermal_device_init();
}
+static struct of_dev_auxdata msm_hsic_host_adata[] = {
+ OF_DEV_AUXDATA("qcom,hsic-host", 0xF9A00000, "msm_hsic_host", NULL),
+ {}
+};
+
static struct of_dev_auxdata msm8974_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("qcom,hsusb-otg", 0xF9A55000, \
"msm_otg", NULL),
@@ -148,6 +153,8 @@
"qcrypto.0", NULL),
OF_DEV_AUXDATA("qcom,hsic-host", 0xF9A00000, \
"msm_hsic_host", NULL),
+ OF_DEV_AUXDATA("qcom,hsic-smsc-hub", 0, "msm_smsc_hub",
+ msm_hsic_host_adata),
{}
};
diff --git a/arch/arm/mach-msm/clock-8226.c b/arch/arm/mach-msm/clock-8226.c
index a883e39..3a0c152 100644
--- a/arch/arm/mach-msm/clock-8226.c
+++ b/arch/arm/mach-msm/clock-8226.c
@@ -694,6 +694,7 @@
F_GCC( 56000000, gpll0, 1, 7, 75),
F_GCC( 58982400, gpll0, 1, 1536, 15625),
F_GCC( 60000000, gpll0, 10, 0, 0),
+ F_GCC( 63160000, gpll0, 9.5, 0, 0),
F_END
};
@@ -1278,6 +1279,7 @@
.en_mask = BIT(5),
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &ce1_clk_src.c,
.dbg_name = "gcc_ce1_clk",
.ops = &clk_ops_vote,
CLK_INIT(gcc_ce1_clk.c),
@@ -3148,7 +3150,7 @@
CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"),
CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"),
/* NFC */
- CLK_LOOKUP("ref_clk", cxo_d1_a_pin.c, "2-000e"),
+ CLK_LOOKUP("ref_clk", cxo_d1_pin.c, "2-000e"),
/* PIL-PRONTO */
CLK_LOOKUP("xo", cxo_pil_pronto_clk.c, "fb21b000.qcom,pronto"),
@@ -3163,6 +3165,8 @@
CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"),
CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"),
CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"),
+ CLK_LOOKUP("clk-4", gpll0_ao.c, "f9011050.qcom,clock-a7"),
+ CLK_LOOKUP("clk-5", a7sspll.c, "f9011050.qcom,clock-a7"),
CLK_LOOKUP("kpss_ahb", kpss_ahb_clk_src.c, ""),
/* WCNSS CLOCKS */
diff --git a/arch/arm/mach-msm/clock-8610.c b/arch/arm/mach-msm/clock-8610.c
index 665c040..c7bf92c 100644
--- a/arch/arm/mach-msm/clock-8610.c
+++ b/arch/arm/mach-msm/clock-8610.c
@@ -677,6 +677,7 @@
F( 960000, gcc_xo, 10, 1, 2),
F( 4800000, gcc_xo, 4, 0, 0),
F( 9600000, gcc_xo, 2, 0, 0),
+ F(12000000, gpll0, 10, 1, 5),
F(15000000, gpll0, 10, 1, 4),
F(19200000, gcc_xo, 1, 0, 0),
F(25000000, gpll0, 12, 1, 2),
@@ -783,6 +784,7 @@
F(56000000, gpll0, 1, 7, 75),
F(58982400, gpll0, 1, 1536, 15625),
F(60000000, gpll0, 10, 0, 0),
+ F(63160000, gpll0, 9.5, 0, 0),
F_END,
};
@@ -1284,6 +1286,7 @@
.en_mask = BIT(5),
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &ce1_clk_src.c,
.dbg_name = "gcc_ce1_clk",
.ops = &clk_ops_vote,
CLK_INIT(gcc_ce1_clk.c),
@@ -2893,12 +2896,13 @@
CLK_LOOKUP("core_clk_src", sdcc2_apps_clk_src.c, ""),
CLK_LOOKUP("core_clk_src", usb_hs_system_clk_src.c, ""),
CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.i2c"),
+ CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9924000.i2c"),
CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9925000.i2c"),
CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9927000.i2c"),
CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.spi"),
CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, "f9923000.i2c"),
CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, ""),
- CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""),
+ CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, "f9924000.i2c"),
CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, "f9925000.i2c"),
CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""),
@@ -2923,6 +2927,7 @@
CLK_LOOKUP("iface_clk", gcc_copss_smmu_ahb_clk.c, ""),
CLK_LOOKUP("iface_clk", gcc_lpss_smmu_ahb_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_gp1_clk.c, "0-000e"),
+ CLK_LOOKUP("core_clk_pvt", gcc_gp1_clk.c, "2-000e"),
CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_lpass_q6_axi_clk.c, ""),
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
old mode 100644
new mode 100755
index 9feb2f0..0051578
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -541,7 +541,8 @@
#define gpll1_hsic_source_val 4
#define cxo_lpass_source_val 0
#define gpll0_lpass_source_val 5
-#define edppll_270_mm_source_val 4
+#define edp_mainlink_mm_source_val 4
+#define edp_pixel_mm_source_val 5
#define edppll_350_mm_source_val 4
#define dsipll_750_mm_source_val 1
#define dsipll0_byte_mm_source_val 1
@@ -589,6 +590,17 @@
| BVAL(10, 8, s##_mm_source_val), \
}
+#define F_EDP(f, s, div, m, n) \
+ { \
+ .freq_hz = (f), \
+ .src_clk = &s##_clk_src.c, \
+ .m_val = (m), \
+ .n_val = ~((n)-(m)) * !!(n), \
+ .d_val = ~(n),\
+ .div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
+ | BVAL(10, 8, s##_mm_source_val), \
+ }
+
#define F_MDSS(f, s, div, m, n) \
{ \
.freq_hz = (f), \
@@ -3181,40 +3193,42 @@
};
static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = {
- F_MDSS(162000000, edppll_270, 2, 0, 0),
- F_MDSS(270000000, edppll_270, 11, 0, 0),
+ F_EDP(162000000, edp_mainlink, 1, 0, 0),
+ F_EDP(270000000, edp_mainlink, 1, 0, 0),
F_END
};
static struct rcg_clk edplink_clk_src = {
.cmd_rcgr_reg = EDPLINK_CMD_RCGR,
- .set_rate = set_rate_hid,
.freq_tbl = ftbl_mdss_edplink_clk,
.current_freq = &rcg_dummy_freq,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "edplink_clk_src",
- .ops = &clk_ops_rcg,
+ .ops = &clk_ops_rcg_edp,
VDD_DIG_FMAX_MAP2(LOW, 135000000, NOMINAL, 270000000),
CLK_INIT(edplink_clk_src.c),
},
};
-static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
- F_MDSS(138500000, edppll_350, 2, 0, 0),
- F_MDSS(350000000, edppll_350, 11, 0, 0),
+static struct clk_freq_tbl edp_pixel_freq_tbl[] = {
+ {
+ .src_clk = &edp_pixel_clk_src.c,
+ .div_src_val = BVAL(10, 8, edp_pixel_mm_source_val)
+ | BVAL(4, 0, 0),
+ },
F_END
};
static struct rcg_clk edppixel_clk_src = {
.cmd_rcgr_reg = EDPPIXEL_CMD_RCGR,
.set_rate = set_rate_mnd,
- .freq_tbl = ftbl_mdss_edppixel_clk,
- .current_freq = &rcg_dummy_freq,
+ .current_freq = edp_pixel_freq_tbl,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &edp_pixel_clk_src.c,
.dbg_name = "edppixel_clk_src",
- .ops = &clk_ops_rcg_mnd,
+ .ops = &clk_ops_edppixel,
VDD_DIG_FMAX_MAP2(LOW, 175000000, NOMINAL, 350000000),
CLK_INIT(edppixel_clk_src.c),
},
@@ -4950,7 +4964,8 @@
CLK_LOOKUP("xo", cxo_dwc3_clk.c, "msm_dwc3"),
CLK_LOOKUP("xo", cxo_ehci_host_clk.c, "msm_ehci_host"),
CLK_LOOKUP("xo", cxo_lpm_clk.c, "fc4281d0.qcom,mpm"),
-
+ CLK_LOOKUP("ref_clk", cxo_d1_a_pin.c, "3-000e"),
+ CLK_LOOKUP("ref_clk_rf", cxo_a2_a_pin.c, "3-000e"),
CLK_LOOKUP("measure", measure_clk.c, "debug"),
CLK_LOOKUP("hfpll_src", cxo_a_clk_src.c, "f9016000.qcom,clock-krait"),
@@ -4974,7 +4989,11 @@
CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""),
- CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""),
+
+ /* I2C Clocks nfc */
+ CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9928000.i2c"),
+ CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, "f9928000.i2c"),
+
CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""),
CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f991e000.serial"),
diff --git a/arch/arm/mach-msm/clock-a7.c b/arch/arm/mach-msm/clock-a7.c
new file mode 100644
index 0000000..5b8dc4e
--- /dev/null
+++ b/arch/arm/mach-msm/clock-a7.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/of.h>
+
+#include <mach/clock-generic.h>
+#include "clock-local2.h"
+
+#define UPDATE_CHECK_MAX_LOOPS 200
+
+struct cortex_reg_data {
+ u32 cmd_offset;
+ u32 update_mask;
+ u32 poll_mask;
+};
+
+#define DIV_REG(x) ((x)->base + (x)->div_offset)
+#define SRC_REG(x) ((x)->base + (x)->src_offset)
+#define CMD_REG(x) ((x)->base + \
+ ((struct cortex_reg_data *)(x)->priv)->cmd_offset)
+
+static int update_config(struct mux_div_clk *md)
+{
+ u32 regval, count;
+ struct cortex_reg_data *r = md->priv;
+
+ /* Update the configuration */
+ regval = readl_relaxed(CMD_REG(md));
+ regval |= r->update_mask;
+ writel_relaxed(regval, CMD_REG(md));
+
+ /* Wait for update to take effect */
+ for (count = UPDATE_CHECK_MAX_LOOPS; count > 0; count--) {
+ if (!(readl_relaxed(CMD_REG(md)) &
+ r->poll_mask))
+ return 0;
+ udelay(1);
+ }
+
+ CLK_WARN(&md->c, true, "didn't update its configuration.");
+
+ return -EINVAL;
+}
+
+static void cortex_get_config(struct mux_div_clk *md, u32 *src_sel, u32 *div)
+{
+ u32 regval;
+
+ regval = readl_relaxed(DIV_REG(md));
+ regval &= (md->div_mask << md->div_shift);
+ *div = regval >> md->div_shift;
+ *div = max((u32)1, (*div + 1) / 2);
+
+ regval = readl_relaxed(SRC_REG(md));
+ regval &= (md->src_mask << md->src_shift);
+ *src_sel = regval >> md->src_shift;
+}
+
+static int cortex_set_config(struct mux_div_clk *md, u32 src_sel, u32 div)
+{
+ u32 regval;
+
+ div = div ? ((2 * div) - 1) : 0;
+ regval = readl_relaxed(DIV_REG(md));
+ regval &= ~(md->div_mask << md->div_shift);
+ regval |= div << md->div_shift;
+ writel_relaxed(regval, DIV_REG(md));
+
+ regval = readl_relaxed(SRC_REG(md));
+ regval &= ~(md->src_mask << md->src_shift);
+ regval |= src_sel << md->src_shift;
+ writel_relaxed(regval, SRC_REG(md));
+
+ return update_config(md);
+}
+
+static int cortex_enable(struct mux_div_clk *md)
+{
+ u32 src_sel = parent_to_src_sel(md->parents, md->num_parents,
+ md->c.parent);
+ return cortex_set_config(md, src_sel, md->data.div);
+}
+
+static void cortex_disable(struct mux_div_clk *md)
+{
+ u32 src_sel = parent_to_src_sel(md->parents, md->num_parents,
+ md->safe_parent);
+ cortex_set_config(md, src_sel, md->safe_div);
+}
+
+static bool cortex_is_enabled(struct mux_div_clk *md)
+{
+ return true;
+}
+
+struct mux_div_ops cortex_mux_div_ops = {
+ .set_src_div = cortex_set_config,
+ .get_src_div = cortex_get_config,
+ .is_enabled = cortex_is_enabled,
+ .enable = cortex_enable,
+ .disable = cortex_disable,
+};
+
+static struct cortex_reg_data a7ssmux_priv = {
+ .cmd_offset = 0x0,
+ .update_mask = BIT(0),
+ .poll_mask = BIT(0),
+};
+
+DEFINE_VDD_REGS_INIT(vdd_cpu, 1);
+
+static struct mux_div_clk a7ssmux = {
+ .ops = &cortex_mux_div_ops,
+ .safe_freq = 300000000,
+ .data = {
+ .max_div = 8,
+ .min_div = 1,
+ },
+ .c = {
+ .dbg_name = "a7ssmux",
+ .ops = &clk_ops_mux_div_clk,
+ .vdd_class = &vdd_cpu,
+ CLK_INIT(a7ssmux.c),
+ },
+ .parents = (struct clk_src[8]) {},
+ .priv = &a7ssmux_priv,
+ .div_offset = 0x4,
+ .div_mask = BM(4, 0),
+ .div_shift = 0,
+ .src_offset = 0x4,
+ .src_mask = BM(10, 8) >> 8,
+ .src_shift = 8,
+};
+
+static struct clk_lookup clock_tbl_a7[] = {
+ CLK_LOOKUP("cpu0_clk", a7ssmux.c, "0.qcom,msm-cpufreq"),
+ CLK_LOOKUP("cpu0_clk", a7ssmux.c, "fe805664.qcom,pm-8x60"),
+};
+
+static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c,
+ char *prop_name)
+{
+ struct device_node *of = pdev->dev.of_node;
+ int prop_len, i;
+ struct clk_vdd_class *vdd = c->vdd_class;
+ u32 *array;
+
+ if (!of_find_property(of, prop_name, &prop_len)) {
+ dev_err(&pdev->dev, "missing %s\n", prop_name);
+ return -EINVAL;
+ }
+
+ prop_len /= sizeof(u32);
+ if (prop_len % 2) {
+ dev_err(&pdev->dev, "bad length %d\n", prop_len);
+ return -EINVAL;
+ }
+
+ prop_len /= 2;
+ vdd->level_votes = devm_kzalloc(&pdev->dev, prop_len * sizeof(int),
+ GFP_KERNEL);
+ if (!vdd->level_votes)
+ return -ENOMEM;
+
+ vdd->vdd_uv = devm_kzalloc(&pdev->dev, prop_len * sizeof(int),
+ GFP_KERNEL);
+ if (!vdd->vdd_uv)
+ return -ENOMEM;
+
+ c->fmax = devm_kzalloc(&pdev->dev, prop_len * sizeof(unsigned long),
+ GFP_KERNEL);
+ if (!c->fmax)
+ return -ENOMEM;
+
+ array = devm_kzalloc(&pdev->dev, prop_len * sizeof(u32), GFP_KERNEL);
+ if (!array)
+ return -ENOMEM;
+
+ of_property_read_u32_array(of, prop_name, array, prop_len * 2);
+ for (i = 0; i < prop_len; i++) {
+ c->fmax[i] = array[2 * i];
+ vdd->vdd_uv[i] = array[2 * i + 1];
+ }
+
+ devm_kfree(&pdev->dev, array);
+ vdd->num_levels = prop_len;
+ vdd->cur_level = prop_len;
+ c->num_fmax = prop_len;
+ return 0;
+}
+
+static void get_speed_bin(struct platform_device *pdev, int *bin, int *version)
+{
+ struct resource *res;
+ void __iomem *base;
+ u32 pte_efuse, redundant_sel, valid;
+
+ *bin = 0;
+ *version = 0;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
+ if (!res) {
+ dev_info(&pdev->dev,
+ "No speed/PVS binning available. Defaulting to 0!\n");
+ return;
+ }
+
+ base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!base) {
+ dev_warn(&pdev->dev,
+ "Unable to read efuse data. Defaulting to 0!\n");
+ return;
+ }
+
+ pte_efuse = readl_relaxed(base);
+ devm_iounmap(&pdev->dev, base);
+
+ redundant_sel = (pte_efuse >> 24) & 0x7;
+ *bin = pte_efuse & 0x7;
+ valid = (pte_efuse >> 3) & 0x1;
+ *version = (pte_efuse >> 4) & 0x3;
+
+ if (redundant_sel == 1)
+ *bin = (pte_efuse >> 27) & 0x7;
+
+ if (!valid) {
+ dev_info(&pdev->dev, "Speed bin not set. Defaulting to 0!\n");
+ *bin = 0;
+ } else {
+ dev_info(&pdev->dev, "Speed bin: %d\n", *bin);
+ }
+
+ dev_info(&pdev->dev, "PVS version: %d\n", *version);
+
+ return;
+}
+
+static int of_get_clk_src(struct platform_device *pdev, struct clk_src *parents)
+{
+ struct device_node *of = pdev->dev.of_node;
+ int num_parents, i, j, index;
+ struct clk *c;
+ char clk_name[] = "clk-x";
+
+ num_parents = of_property_count_strings(of, "clock-names");
+ if (num_parents <= 0 || num_parents > 8) {
+ dev_err(&pdev->dev, "missing clock-names\n");
+ return -EINVAL;
+ }
+
+ j = 0;
+ for (i = 0; i < 8; i++) {
+ snprintf(clk_name, ARRAY_SIZE(clk_name), "clk-%d", i);
+ index = of_property_match_string(of, "clock-names", clk_name);
+ if (IS_ERR_VALUE(index))
+ continue;
+
+ parents[j].sel = i;
+ parents[j].src = c = devm_clk_get(&pdev->dev, clk_name);
+ if (IS_ERR(c)) {
+ if (c != ERR_PTR(-EPROBE_DEFER))
+ dev_err(&pdev->dev, "clk_get: %s\n fail",
+ clk_name);
+ return PTR_ERR(c);
+ }
+ j++;
+ }
+
+ return num_parents;
+}
+
+static int clock_a7_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ int speed_bin = 0, version = 0, rc;
+ unsigned long rate, aux_rate;
+ struct clk *aux_clk, *main_pll;
+ char prop_name[] = "qcom,speedX-bin-vX";
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rcg-base");
+ if (!res) {
+ dev_err(&pdev->dev, "missing rcg-base\n");
+ return -EINVAL;
+ }
+ a7ssmux.base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!a7ssmux.base) {
+ dev_err(&pdev->dev, "ioremap failed for rcg-base\n");
+ return -ENOMEM;
+ }
+
+ vdd_cpu.regulator[0] = devm_regulator_get(&pdev->dev, "cpu-vdd");
+ if (IS_ERR(vdd_cpu.regulator[0])) {
+ if (PTR_ERR(vdd_cpu.regulator[0]) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "unable to get regulator\n");
+ return PTR_ERR(vdd_cpu.regulator[0]);
+ }
+
+ a7ssmux.num_parents = of_get_clk_src(pdev, a7ssmux.parents);
+ if (IS_ERR_VALUE(a7ssmux.num_parents))
+ return a7ssmux.num_parents;
+
+ get_speed_bin(pdev, &speed_bin, &version);
+
+ snprintf(prop_name, ARRAY_SIZE(prop_name),
+ "qcom,speed%d-bin-v%d", speed_bin, version);
+ rc = of_get_fmax_vdd_class(pdev, &a7ssmux.c, prop_name);
+ if (rc) {
+ /* Fall back to most conservative PVS table */
+ dev_err(&pdev->dev, "Unable to load voltage plan %s!\n",
+ prop_name);
+ rc = of_get_fmax_vdd_class(pdev, &a7ssmux.c,
+ "qcom,speed0-bin-v0");
+ if (rc) {
+ dev_err(&pdev->dev,
+ "Unable to load safe voltage plan\n");
+ return rc;
+ }
+ dev_info(&pdev->dev, "Safe voltage plan loaded.\n");
+ }
+
+ rc = msm_clock_register(clock_tbl_a7, ARRAY_SIZE(clock_tbl_a7));
+ if (rc) {
+ dev_err(&pdev->dev, "msm_clock_register failed\n");
+ return rc;
+ }
+
+ /* Force a PLL reconfiguration */
+ aux_clk = a7ssmux.parents[0].src;
+ main_pll = a7ssmux.parents[1].src;
+
+ aux_rate = clk_get_rate(aux_clk);
+ rate = clk_get_rate(&a7ssmux.c);
+ clk_set_rate(&a7ssmux.c, aux_rate);
+ clk_set_rate(main_pll, clk_round_rate(main_pll, 1));
+ clk_set_rate(&a7ssmux.c, rate);
+
+ /*
+ * We don't want the CPU clocks to be turned off at late init
+ * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
+ * refcount of these clocks. Any cpufreq/hotplug manager can assume
+ * that the clocks have already been prepared and enabled by the time
+ * they take over.
+ */
+ WARN(clk_prepare_enable(&a7ssmux.c),
+ "Unable to turn on CPU clock");
+ return 0;
+}
+
+static struct of_device_id clock_a7_match_table[] = {
+ {.compatible = "qcom,clock-a7-8226"},
+ {}
+};
+
+static struct platform_driver clock_a7_driver = {
+ .driver = {
+ .name = "clock-a7",
+ .of_match_table = clock_a7_match_table,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init clock_a7_init(void)
+{
+ return platform_driver_probe(&clock_a7_driver, clock_a7_probe);
+}
+device_initcall(clock_a7_init);
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
index 35917c3..c3b7229 100644
--- a/arch/arm/mach-msm/clock-debug.c
+++ b/arch/arm/mach-msm/clock-debug.c
@@ -23,6 +23,7 @@
#include <linux/clkdev.h>
#include <linux/uaccess.h>
#include <linux/mutex.h>
+#include <linux/io.h>
#include <mach/clk-provider.h>
@@ -412,6 +413,56 @@
.write = clock_parent_write,
};
+void clk_debug_print_hw(struct clk *clk, struct seq_file *f)
+{
+ void __iomem *base;
+ struct clk_register_data *regs;
+ u32 i, j, size;
+
+ if (IS_ERR_OR_NULL(clk))
+ return;
+
+ clk_debug_print_hw(clk->parent, f);
+
+ clock_debug_output(f, false, "%s\n", clk->dbg_name);
+
+ if (!clk->ops->list_registers)
+ return;
+
+ j = 0;
+ base = clk->ops->list_registers(clk, j, ®s, &size);
+ while (!IS_ERR(base)) {
+ for (i = 0; i < size; i++) {
+ u32 val = readl_relaxed(base + regs[i].offset);
+ clock_debug_output(f, false, "%20s: 0x%.8x\n",
+ regs[i].name, val);
+ }
+ j++;
+ base = clk->ops->list_registers(clk, j, ®s, &size);
+ }
+}
+
+static int print_hw_show(struct seq_file *m, void *unused)
+{
+ struct clk *c = m->private;
+ clk_debug_print_hw(c, m);
+
+ return 0;
+}
+
+static int print_hw_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, print_hw_show, inode->i_private);
+}
+
+static const struct file_operations clock_print_hw_fops = {
+ .open = print_hw_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = seq_release,
+};
+
+
static int clock_debug_add(struct clk *clock)
{
char temp[50], *ptr;
@@ -463,6 +514,10 @@
&clock_parent_fops))
goto error;
+ if (!debugfs_create_file("print", S_IRUGO, clk_dir, clock,
+ &clock_print_hw_fops))
+ goto error;
+
return 0;
error:
debugfs_remove_recursive(clk_dir);
diff --git a/arch/arm/mach-msm/clock-krait-8974.c b/arch/arm/mach-msm/clock-krait-8974.c
index 6ada01f..24fe303 100644
--- a/arch/arm/mach-msm/clock-krait-8974.c
+++ b/arch/arm/mach-msm/clock-krait-8974.c
@@ -732,8 +732,8 @@
* that the clocks have already been prepared and enabled by the time
* they take over.
*/
- clk_prepare_enable(&l2_clk.c);
for_each_online_cpu(cpu) {
+ clk_prepare_enable(&l2_clk.c);
WARN(clk_prepare_enable(cpu_clk[cpu]),
"Unable to turn on CPU%d clock", cpu);
}
diff --git a/arch/arm/mach-msm/clock-krypton.c b/arch/arm/mach-msm/clock-krypton.c
index 176dc32..2b529b0 100644
--- a/arch/arm/mach-msm/clock-krypton.c
+++ b/arch/arm/mach-msm/clock-krypton.c
@@ -515,6 +515,7 @@
F( 56000000, gpll0, 1, 7, 75),
F( 58982400, gpll0, 1, 1536, 15625),
F( 60000000, gpll0, 10, 0, 0),
+ F( 63160000, gpll0, 9.5, 0, 0),
F_END
};
diff --git a/arch/arm/mach-msm/clock-local2.c b/arch/arm/mach-msm/clock-local2.c
index 01ecba2..cc6f290 100644
--- a/arch/arm/mach-msm/clock-local2.c
+++ b/arch/arm/mach-msm/clock-local2.c
@@ -641,6 +641,74 @@
return HANDOFF_ENABLED_CLK;
}
+struct frac_entry {
+ int num;
+ int den;
+};
+
+static struct frac_entry frac_table_675m[] = { /* link rate of 270M */
+ {52, 295}, /* 119 M */
+ {11, 57}, /* 130.25 M */
+ {63, 307}, /* 138.50 M */
+ {11, 50}, /* 148.50 M */
+ {47, 206}, /* 154 M */
+ {31, 100}, /* 205.25 M */
+ {107, 269}, /* 268.50 M */
+ {0, 0},
+};
+
+static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
+ {31, 211}, /* 119 M */
+ {32, 199}, /* 130.25 M */
+ {63, 307}, /* 138.50 M */
+ {11, 60}, /* 148.50 M */
+ {50, 263}, /* 154 M */
+ {31, 120}, /* 205.25 M */
+ {119, 359}, /* 268.50 M */
+ {0, 0},
+};
+
+static int set_rate_edp_pixel(struct clk *clk, unsigned long rate)
+{
+ struct rcg_clk *rcg = to_rcg_clk(clk);
+ struct clk_freq_tbl *pixel_freq = rcg->current_freq;
+ struct frac_entry *frac;
+ int delta = 100000;
+ s64 request;
+ s64 src_rate;
+
+ src_rate = clk_get_rate(clk->parent);
+
+ if (src_rate == 810000000)
+ frac = frac_table_810m;
+ else
+ frac = frac_table_675m;
+
+ while (frac->num) {
+ request = rate;
+ request *= frac->den;
+ request = div_s64(request, frac->num);
+ if ((src_rate < (request - delta)) ||
+ (src_rate > (request + delta))) {
+ frac++;
+ continue;
+ }
+
+ pixel_freq->div_src_val &= ~BM(4, 0);
+ if (frac->den == frac->num) {
+ pixel_freq->m_val = 0;
+ pixel_freq->n_val = 0;
+ } else {
+ pixel_freq->m_val = frac->num;
+ pixel_freq->n_val = ~(frac->den - frac->num);
+ pixel_freq->d_val = ~frac->den;
+ }
+ set_rate_mnd(rcg, pixel_freq);
+ return 0;
+ }
+ return -EINVAL;
+}
+
enum handoff byte_rcg_handoff(struct clk *clk)
{
struct rcg_clk *rcg = to_rcg_clk(clk);
@@ -796,6 +864,37 @@
return rc;
}
+static struct clk *edp_clk_get_parent(struct clk *c)
+{
+ struct rcg_clk *rcg = to_rcg_clk(c);
+ struct clk *clk;
+ struct clk_freq_tbl *freq;
+ uint32_t rate;
+ u32 cmd_rcgr_regval;
+
+ /* Is there a pending configuration? */
+ cmd_rcgr_regval = readl_relaxed(CMD_RCGR_REG(rcg));
+ if (cmd_rcgr_regval & CMD_RCGR_CONFIG_DIRTY_MASK)
+ return NULL;
+
+ /* Figure out what rate the rcg is running at */
+ for (freq = rcg->freq_tbl; freq->freq_hz != FREQ_END; freq++) {
+ clk = freq->src_clk;
+ if (clk && clk->ops->get_rate) {
+ rate = clk->ops->get_rate(clk);
+ if (rate == freq->freq_hz)
+ break;
+ }
+ }
+
+ /* No known frequency found */
+ if (freq->freq_hz == FREQ_END)
+ return NULL;
+
+ rcg->current_freq = freq;
+ return freq->src_clk;
+}
+
static DEFINE_SPINLOCK(mux_reg_lock);
@@ -886,6 +985,14 @@
.handoff = pixel_rcg_handoff,
};
+struct clk_ops clk_ops_edppixel = {
+ .enable = rcg_clk_prepare,
+ .set_rate = set_rate_edp_pixel,
+ .list_rate = rcg_clk_list_rate,
+ .round_rate = rcg_clk_round_rate,
+ .handoff = pixel_rcg_handoff,
+};
+
struct clk_ops clk_ops_byte = {
.enable = rcg_clk_prepare,
.set_rate = set_rate_byte,
@@ -903,6 +1010,15 @@
.get_parent = rcg_clk_get_parent,
};
+struct clk_ops clk_ops_rcg_edp = {
+ .enable = rcg_clk_prepare,
+ .set_rate = rcg_clk_set_rate_hdmi,
+ .list_rate = rcg_clk_list_rate,
+ .round_rate = rcg_clk_round_rate,
+ .handoff = rcg_clk_handoff,
+ .get_parent = edp_clk_get_parent,
+};
+
struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
diff --git a/arch/arm/mach-msm/clock-local2.h b/arch/arm/mach-msm/clock-local2.h
index 8724f63..35fb6fa 100644
--- a/arch/arm/mach-msm/clock-local2.h
+++ b/arch/arm/mach-msm/clock-local2.h
@@ -174,9 +174,11 @@
extern struct clk_ops clk_ops_branch;
extern struct clk_ops clk_ops_vote;
extern struct clk_ops clk_ops_rcg_hdmi;
+extern struct clk_ops clk_ops_rcg_edp;
extern struct clk_ops clk_ops_byte;
extern struct clk_ops clk_ops_pixel;
extern struct clk_mux_ops mux_reg_ops;
+extern struct clk_ops clk_ops_edppixel;
enum handoff pixel_rcg_handoff(struct clk *clk);
enum handoff byte_rcg_handoff(struct clk *clk);
diff --git a/arch/arm/mach-msm/clock-mdss-8974.c b/arch/arm/mach-msm/clock-mdss-8974.c
index 2fa921a..b500e1d 100644
--- a/arch/arm/mach-msm/clock-mdss-8974.c
+++ b/arch/arm/mach-msm/clock-mdss-8974.c
@@ -37,6 +37,9 @@
#define DSI_PHY_PHYS 0xFD922A00
#define DSI_PHY_SIZE 0x000000D4
+#define EDP_PHY_PHYS 0xFD923A00
+#define EDP_PHY_SIZE 0x000000D4
+
#define HDMI_PHY_PHYS 0xFD922500
#define HDMI_PHY_SIZE 0x0000007C
@@ -153,6 +156,7 @@
static unsigned char *mdss_dsi_base;
static unsigned char *gdsc_base;
static struct clk *mdss_ahb_clk;
+static unsigned char *mdss_edp_base;
static void __iomem *hdmi_phy_base;
static void __iomem *hdmi_phy_pll_base;
@@ -1669,6 +1673,459 @@
},
};
+static inline struct edp_pll_vco_clk *to_edp_vco_clk(struct clk *clk)
+{
+ return container_of(clk, struct edp_pll_vco_clk, c);
+}
+
+static int edp_vco_set_rate(struct clk *c, unsigned long vco_rate)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+ int rc = 0;
+
+ pr_debug("%s: vco_rate=%d\n", __func__, (int)vco_rate);
+
+ rc = mdss_ahb_clk_enable(1);
+ if (rc) {
+ pr_err("%s: failed to enable mdss ahb clock. rc=%d\n",
+ __func__, rc);
+ rc = -EINVAL;
+ }
+ if (vco_rate == 810000000) {
+ DSS_REG_W(mdss_edp_base, 0x0c, 0x18);
+ /* UNIPHY_PLL_LKDET_CFG2 */
+ DSS_REG_W(mdss_edp_base, 0x64, 0x05);
+ /* UNIPHY_PLL_REFCLK_CFG */
+ DSS_REG_W(mdss_edp_base, 0x00, 0x00);
+ /* UNIPHY_PLL_SDM_CFG0 */
+ DSS_REG_W(mdss_edp_base, 0x38, 0x36);
+ /* UNIPHY_PLL_SDM_CFG1 */
+ DSS_REG_W(mdss_edp_base, 0x3c, 0x69);
+ /* UNIPHY_PLL_SDM_CFG2 */
+ DSS_REG_W(mdss_edp_base, 0x40, 0xff);
+ /* UNIPHY_PLL_SDM_CFG3 */
+ DSS_REG_W(mdss_edp_base, 0x44, 0x2f);
+ /* UNIPHY_PLL_SDM_CFG4 */
+ DSS_REG_W(mdss_edp_base, 0x48, 0x00);
+ /* UNIPHY_PLL_SSC_CFG0 */
+ DSS_REG_W(mdss_edp_base, 0x4c, 0x80);
+ /* UNIPHY_PLL_SSC_CFG1 */
+ DSS_REG_W(mdss_edp_base, 0x50, 0x00);
+ /* UNIPHY_PLL_SSC_CFG2 */
+ DSS_REG_W(mdss_edp_base, 0x54, 0x00);
+ /* UNIPHY_PLL_SSC_CFG3 */
+ DSS_REG_W(mdss_edp_base, 0x58, 0x00);
+ /* UNIPHY_PLL_CAL_CFG0 */
+ DSS_REG_W(mdss_edp_base, 0x6c, 0x0a);
+ /* UNIPHY_PLL_CAL_CFG2 */
+ DSS_REG_W(mdss_edp_base, 0x74, 0x01);
+ /* UNIPHY_PLL_CAL_CFG6 */
+ DSS_REG_W(mdss_edp_base, 0x84, 0x5a);
+ /* UNIPHY_PLL_CAL_CFG7 */
+ DSS_REG_W(mdss_edp_base, 0x88, 0x0);
+ /* UNIPHY_PLL_CAL_CFG8 */
+ DSS_REG_W(mdss_edp_base, 0x8c, 0x60);
+ /* UNIPHY_PLL_CAL_CFG9 */
+ DSS_REG_W(mdss_edp_base, 0x90, 0x0);
+ /* UNIPHY_PLL_CAL_CFG10 */
+ DSS_REG_W(mdss_edp_base, 0x94, 0x2a);
+ /* UNIPHY_PLL_CAL_CFG11 */
+ DSS_REG_W(mdss_edp_base, 0x98, 0x3);
+ /* UNIPHY_PLL_LKDET_CFG0 */
+ DSS_REG_W(mdss_edp_base, 0x5c, 0x10);
+ /* UNIPHY_PLL_LKDET_CFG1 */
+ DSS_REG_W(mdss_edp_base, 0x60, 0x1a);
+ /* UNIPHY_PLL_POSTDIV1_CFG */
+ DSS_REG_W(mdss_edp_base, 0x04, 0x00);
+ /* UNIPHY_PLL_POSTDIV3_CFG */
+ DSS_REG_W(mdss_edp_base, 0x28, 0x00);
+ } else if (vco_rate == 1350000000) {
+ /* UNIPHY_PLL_LKDET_CFG2 */
+ DSS_REG_W(mdss_edp_base, 0x64, 0x05);
+ /* UNIPHY_PLL_REFCLK_CFG */
+ DSS_REG_W(mdss_edp_base, 0x00, 0x01);
+ /* UNIPHY_PLL_SDM_CFG0 */
+ DSS_REG_W(mdss_edp_base, 0x38, 0x36);
+ /* UNIPHY_PLL_SDM_CFG1 */
+ DSS_REG_W(mdss_edp_base, 0x3c, 0x62);
+ /* UNIPHY_PLL_SDM_CFG2 */
+ DSS_REG_W(mdss_edp_base, 0x40, 0x00);
+ /* UNIPHY_PLL_SDM_CFG3 */
+ DSS_REG_W(mdss_edp_base, 0x44, 0x28);
+ /* UNIPHY_PLL_SDM_CFG4 */
+ DSS_REG_W(mdss_edp_base, 0x48, 0x00);
+ /* UNIPHY_PLL_SSC_CFG0 */
+ DSS_REG_W(mdss_edp_base, 0x4c, 0x80);
+ /* UNIPHY_PLL_SSC_CFG1 */
+ DSS_REG_W(mdss_edp_base, 0x50, 0x00);
+ /* UNIPHY_PLL_SSC_CFG2 */
+ DSS_REG_W(mdss_edp_base, 0x54, 0x00);
+ /* UNIPHY_PLL_SSC_CFG3 */
+ DSS_REG_W(mdss_edp_base, 0x58, 0x00);
+ /* UNIPHY_PLL_CAL_CFG0 */
+ DSS_REG_W(mdss_edp_base, 0x6c, 0x0a);
+ /* UNIPHY_PLL_CAL_CFG2 */
+ DSS_REG_W(mdss_edp_base, 0x74, 0x01);
+ /* UNIPHY_PLL_CAL_CFG6 */
+ DSS_REG_W(mdss_edp_base, 0x84, 0x5a);
+ /* UNIPHY_PLL_CAL_CFG7 */
+ DSS_REG_W(mdss_edp_base, 0x88, 0x0);
+ /* UNIPHY_PLL_CAL_CFG8 */
+ DSS_REG_W(mdss_edp_base, 0x8c, 0x60);
+ /* UNIPHY_PLL_CAL_CFG9 */
+ DSS_REG_W(mdss_edp_base, 0x90, 0x0);
+ /* UNIPHY_PLL_CAL_CFG10 */
+ DSS_REG_W(mdss_edp_base, 0x94, 0x46);
+ /* UNIPHY_PLL_CAL_CFG11 */
+ DSS_REG_W(mdss_edp_base, 0x98, 0x5);
+ /* UNIPHY_PLL_LKDET_CFG0 */
+ DSS_REG_W(mdss_edp_base, 0x5c, 0x10);
+ /* UNIPHY_PLL_LKDET_CFG1 */
+ DSS_REG_W(mdss_edp_base, 0x60, 0x1a);
+ /* UNIPHY_PLL_POSTDIV1_CFG */
+ DSS_REG_W(mdss_edp_base, 0x04, 0x00);
+ /* UNIPHY_PLL_POSTDIV3_CFG */
+ DSS_REG_W(mdss_edp_base, 0x28, 0x00);
+ } else {
+ pr_err("%s: rate=%d is NOT supported\n", __func__,
+ (int)vco_rate);
+ vco_rate = 0;
+ rc = -EINVAL;
+ }
+
+ DSS_REG_W(mdss_edp_base, 0x20, 0x01); /* UNIPHY_PLL_GLB_CFG */
+ udelay(100);
+ DSS_REG_W(mdss_edp_base, 0x20, 0x05); /* UNIPHY_PLL_GLB_CFG */
+ udelay(100);
+ DSS_REG_W(mdss_edp_base, 0x20, 0x07); /* UNIPHY_PLL_GLB_CFG */
+ udelay(100);
+ DSS_REG_W(mdss_edp_base, 0x20, 0x0f); /* UNIPHY_PLL_GLB_CFG */
+ udelay(100);
+ mdss_ahb_clk_enable(0);
+
+ vco->rate = vco_rate;
+
+ return rc;
+}
+
+static int edp_pll_ready_poll(void)
+{
+ int cnt;
+ u32 status;
+
+ /* ahb clock should be enabled by caller */
+ cnt = 100;
+ while (cnt--) {
+ udelay(100);
+ status = DSS_REG_R(mdss_edp_base, 0xc0);
+ status &= 0x01;
+ if (status)
+ break;
+ }
+ pr_debug("%s: cnt=%d status=%d\n", __func__, cnt, (int)status);
+
+ if (status)
+ return 1;
+
+ pr_err("%s: PLL NOT ready\n", __func__);
+ return 0;
+}
+
+static int edp_vco_enable(struct clk *c)
+{
+ int i, ready;
+ int rc = 0;
+
+ if (!mdss_gdsc_enabled()) {
+ pr_err("%s: mdss GDSC is not enabled\n", __func__);
+ return -EPERM;
+ }
+
+ /* called from enable, irq disable. can not call clk_prepare */
+ rc = clk_enable(mdss_ahb_clk);
+ if (rc) {
+ pr_err("%s: failed to enable mdss ahb clock. rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+
+ for (i = 0; i < 3; i++) {
+ ready = edp_pll_ready_poll();
+ if (ready)
+ break;
+ DSS_REG_W(mdss_edp_base, 0x20, 0x01); /* UNIPHY_PLL_GLB_CFG */
+ udelay(100);
+ DSS_REG_W(mdss_edp_base, 0x20, 0x05); /* UNIPHY_PLL_GLB_CFG */
+ udelay(100);
+ DSS_REG_W(mdss_edp_base, 0x20, 0x07); /* UNIPHY_PLL_GLB_CFG */
+ udelay(100);
+ DSS_REG_W(mdss_edp_base, 0x20, 0x0f); /* UNIPHY_PLL_GLB_CFG */
+ udelay(100);
+ }
+ clk_disable(mdss_ahb_clk);
+
+ if (ready) {
+ pr_debug("%s: EDP PLL locked\n", __func__);
+ return 0;
+ }
+
+ pr_err("%s: EDP PLL failed to lock\n", __func__);
+ return -EINVAL;
+}
+
+static void edp_vco_disable(struct clk *c)
+{
+ int rc = 0;
+
+ if (!mdss_gdsc_enabled()) {
+ pr_err("%s: mdss GDSC is not enabled\n", __func__);
+ return;
+ }
+
+ /* called from unprepare which is not atomic */
+ rc = mdss_ahb_clk_enable(1);
+ if (rc) {
+ pr_err("%s: failed to enable mdss ahb clock. rc=%d\n",
+ __func__, rc);
+ return;
+ }
+
+ DSS_REG_W(mdss_edp_base, 0x20, 0x00);
+
+ mdss_ahb_clk_enable(0);
+
+ pr_debug("%s: EDP PLL Disabled\n", __func__);
+ return;
+}
+
+static unsigned long edp_vco_get_rate(struct clk *c)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+ u32 pll_status, div2;
+ int rc;
+
+ rc = mdss_ahb_clk_enable(1);
+ if (rc) {
+ pr_err("%s: failed to enable mdss ahb clock. rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ if (vco->rate == 0) {
+ pll_status = DSS_REG_R(mdss_edp_base, 0xc0);
+ if (pll_status & 0x01) {
+ div2 = DSS_REG_R(mdss_edp_base, 0x24);
+ if (div2 & 0x01)
+ vco->rate = 1350000000;
+ else
+ vco->rate = 810000000;
+ }
+ }
+ mdss_ahb_clk_enable(0);
+
+ pr_debug("%s: rate=%d\n", __func__, (int)vco->rate);
+
+ return vco->rate;
+}
+
+static long edp_vco_round_rate(struct clk *c, unsigned long rate)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+ unsigned long rrate = -ENOENT;
+ unsigned long *lp;
+
+ lp = vco->rate_list;
+ while (*lp) {
+ rrate = *lp;
+ if (rate <= rrate)
+ break;
+ lp++;
+ }
+
+ pr_debug("%s: rrate=%d\n", __func__, (int)rrate);
+
+ return rrate;
+}
+
+static int edp_vco_prepare(struct clk *c)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+
+ pr_debug("%s: rate=%d\n", __func__, (int)vco->rate);
+
+ return edp_vco_set_rate(c, vco->rate);
+}
+
+static void edp_vco_unprepare(struct clk *c)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+
+ pr_debug("%s: rate=%d\n", __func__, (int)vco->rate);
+
+ edp_vco_disable(c);
+}
+
+static int edp_pll_lock_status(void)
+{
+ u32 status;
+ int pll_locked = 0;
+ int rc;
+
+ rc = mdss_ahb_clk_enable(1);
+ if (rc) {
+ pr_err("%s: failed to enable mdss ahb clock. rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+ /* poll for PLL ready status */
+ if (readl_poll_timeout_noirq((mdss_edp_base + 0xc0),
+ status, ((status & BIT(0)) == 1),
+ PLL_POLL_MAX_READS, PLL_POLL_TIMEOUT_US)) {
+ pr_debug("%s: EDP PLL status=%x failed to Lock\n",
+ __func__, status);
+ pll_locked = 0;
+ } else {
+ pll_locked = 1;
+ }
+ mdss_ahb_clk_enable(0);
+
+ return pll_locked;
+}
+
+static enum handoff edp_vco_handoff(struct clk *c)
+{
+ enum handoff ret = HANDOFF_DISABLED_CLK;
+
+ if (edp_pll_lock_status()) {
+ c->rate = edp_vco_get_rate(c);
+ ret = HANDOFF_ENABLED_CLK;
+ }
+
+ pr_debug("%s: done, ret=%d\n", __func__, ret);
+ return ret;
+}
+
+/* edp vco rate */
+static unsigned long edp_vco_rate_list[] = {
+ 810000000, 1350000000, 0};
+
+struct clk_ops edp_vco_clk_ops = {
+ .enable = edp_vco_enable,
+ .set_rate = edp_vco_set_rate,
+ .get_rate = edp_vco_get_rate,
+ .round_rate = edp_vco_round_rate,
+ .prepare = edp_vco_prepare,
+ .unprepare = edp_vco_unprepare,
+ .handoff = edp_vco_handoff,
+};
+
+struct edp_pll_vco_clk edp_vco_clk = {
+ .ref_clk_rate = 19200000,
+ .rate = 0,
+ .rate_list = edp_vco_rate_list,
+ .c = {
+ .dbg_name = "edp_vco_clk",
+ .ops = &edp_vco_clk_ops,
+ CLK_INIT(edp_vco_clk.c),
+ },
+};
+
+static unsigned long edp_mainlink_get_rate(struct clk *c)
+{
+ struct div_clk *mclk = to_div_clk(c);
+ struct clk *pclk;
+ unsigned long rate = 0;
+
+ pclk = clk_get_parent(c);
+
+ if (pclk->ops->get_rate) {
+ rate = pclk->ops->get_rate(pclk);
+ rate /= mclk->data.div;
+ }
+
+ pr_debug("%s: rate=%d div=%d\n", __func__, (int)rate, mclk->data.div);
+
+ return rate;
+}
+
+static struct clk_ops edp_mainlink_clk_src_ops;
+static struct clk_div_ops fixed_5div_ops; /* null ops */
+
+struct div_clk edp_mainlink_clk_src = {
+ .ops = &fixed_5div_ops,
+ .data = {
+ .div = 5,
+ },
+ .c = {
+ .parent = &edp_vco_clk.c,
+ .dbg_name = "edp_mainlink_clk_src",
+ .ops = &edp_mainlink_clk_src_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(edp_mainlink_clk_src.c),
+ }
+};
+
+
+static struct clk_ops edp_pixel_clk_ops;
+
+/*
+ * this rate is from pll to clock controller
+ * output from pll to CC has two possibilities
+ * 1: if mainlink rate is 270M, then 675M
+ * 2: if mainlink rate is 162M, then 810M
+ */
+static int edp_pixel_set_div(struct div_clk *clk, int div)
+{
+ int rc = 0;
+
+ rc = mdss_ahb_clk_enable(1);
+ if (rc) {
+ pr_err("%s: failed to enable mdss ahb clock. rc=%d\n",
+ __func__, rc);
+ return rc;
+ }
+
+ pr_debug("%s: div=%d\n", __func__, div);
+ DSS_REG_W(mdss_edp_base, 0x24, (div - 1)); /* UNIPHY_PLL_POSTDIV2_CFG */
+
+ mdss_ahb_clk_enable(0);
+ return 0;
+}
+
+static int edp_pixel_get_div(struct div_clk *clk)
+{
+ int div = 0;
+
+ if (mdss_ahb_clk_enable(1)) {
+ pr_debug("%s: Failed to enable mdss ahb clock\n", __func__);
+ return 1;
+ }
+ div = DSS_REG_R(mdss_edp_base, 0x24); /* UNIPHY_PLL_POSTDIV2_CFG */
+ div &= 0x01;
+ pr_debug("%s: div=%d\n", __func__, div);
+ mdss_ahb_clk_enable(0);
+ return div + 1;
+}
+
+static struct clk_div_ops edp_pixel_ops = {
+ .set_div = edp_pixel_set_div,
+ .get_div = edp_pixel_get_div,
+};
+
+struct div_clk edp_pixel_clk_src = {
+ .data = {
+ .max_div = 2,
+ .min_div = 1,
+ },
+ .ops = &edp_pixel_ops,
+ .c = {
+ .parent = &edp_vco_clk.c,
+ .dbg_name = "edp_pixel_clk_src",
+ .ops = &edp_pixel_clk_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(edp_pixel_clk_src.c),
+ },
+};
+
void __init mdss_clk_ctrl_pre_init(struct clk *ahb_clk)
{
BUG_ON(ahb_clk == NULL);
@@ -1691,6 +2148,10 @@
if (!hdmi_phy_pll_base)
pr_err("%s: unable to ioremap hdmi phy pll base", __func__);
+ mdss_edp_base = ioremap(EDP_PHY_PHYS, EDP_PHY_SIZE);
+ if (!mdss_edp_base)
+ pr_err("%s: unable to remap edp base", __func__);
+
pixel_clk_src_ops = clk_ops_slave_div;
pixel_clk_src_ops.prepare = div_prepare;
@@ -1702,5 +2163,11 @@
byte_mux_clk_ops = clk_ops_gen_mux;
byte_mux_clk_ops.prepare = mux_prepare;
-}
+ edp_mainlink_clk_src_ops = clk_ops_div;
+ edp_mainlink_clk_src_ops.get_parent = clk_get_parent;
+ edp_mainlink_clk_src_ops.get_rate = edp_mainlink_get_rate;
+
+ edp_pixel_clk_ops = clk_ops_slave_div;
+ edp_pixel_clk_ops.prepare = div_prepare;
+}
diff --git a/arch/arm/mach-msm/clock-mdss-8974.h b/arch/arm/mach-msm/clock-mdss-8974.h
index 9fd3026..da24b0d 100644
--- a/arch/arm/mach-msm/clock-mdss-8974.h
+++ b/arch/arm/mach-msm/clock-mdss-8974.h
@@ -26,6 +26,14 @@
void hdmi_pll_disable(void);
int hdmi_pll_set_rate(unsigned long rate);
+struct edp_pll_vco_clk {
+ unsigned long ref_clk_rate;
+ unsigned long rate; /* vco rate */
+ unsigned long *rate_list;
+
+ struct clk c;
+};
+
struct lpfr_cfg {
unsigned long vco_rate;
u32 r;
@@ -57,4 +65,7 @@
extern struct mux_clk byte_mux_8226;
extern struct div_clk byte_clk_src_8226;
+extern struct div_clk edp_mainlink_clk_src;
+extern struct div_clk edp_pixel_clk_src;
+
#endif
diff --git a/arch/arm/mach-msm/clock-pll.c b/arch/arm/mach-msm/clock-pll.c
index a251784..c08df46 100644
--- a/arch/arm/mach-msm/clock-pll.c
+++ b/arch/arm/mach-msm/clock-pll.c
@@ -304,6 +304,22 @@
return HANDOFF_ENABLED_CLK;
}
+static long local_pll_clk_round_rate(struct clk *c, unsigned long rate)
+{
+ struct pll_freq_tbl *nf;
+ struct pll_clk *pll = to_pll_clk(c);
+
+ if (!pll->freq_tbl)
+ return -EINVAL;
+
+ for (nf = pll->freq_tbl; nf->freq_hz != PLL_FREQ_END; nf++)
+ if (nf->freq_hz >= rate)
+ return nf->freq_hz;
+
+ nf--;
+ return nf->freq_hz;
+}
+
static int local_pll_clk_set_rate(struct clk *c, unsigned long rate)
{
struct pll_freq_tbl *nf;
@@ -426,6 +442,7 @@
.enable = sr2_pll_clk_enable,
.disable = local_pll_clk_disable,
.set_rate = local_pll_clk_set_rate,
+ .round_rate = local_pll_clk_round_rate,
.handoff = local_pll_clk_handoff,
};
diff --git a/arch/arm/mach-msm/cpr-regulator.c b/arch/arm/mach-msm/cpr-regulator.c
index 6ddf340..1cf2e41 100644
--- a/arch/arm/mach-msm/cpr-regulator.c
+++ b/arch/arm/mach-msm/cpr-regulator.c
@@ -25,6 +25,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
+#include <linux/cpufreq.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>
#include <linux/regulator/cpr-regulator.h>
@@ -130,6 +131,16 @@
#define BYTES_PER_FUSE_ROW 8
+#define FLAGS_SET_MIN_VOLTAGE BIT(1)
+#define FLAGS_UPLIFT_QUOT_VOLT BIT(2)
+#define FLAGS_QUOT_ADJUST_WITH_FREQ BIT(3)
+
+struct cpufreq_mapping_info {
+ int freq;
+ int quot_adjust;
+ int corner;
+};
+
enum voltage_change_dir {
NO_CHANGE,
DOWN,
@@ -153,10 +164,7 @@
/* Process voltage variables */
u32 pvs_bin;
u32 process;
-
- /* Control parameter to read efuse parameters by trustzone API */
- bool use_tz_api;
-
+ u32 speed_bin;
/* APC voltage regulator */
struct regulator *vdd_apc;
@@ -171,6 +179,7 @@
bool cpr_fuse_disable;
bool cpr_fuse_local;
int cpr_fuse_target_quot[CPR_CORNER_MAX];
+ int cpr_fuse_original_quot[CPR_CORNER_MAX];
int cpr_fuse_ro_sel[CPR_CORNER_MAX];
int gcnt;
@@ -204,6 +213,11 @@
u32 gcnt_time_us;
u32 vdd_apc_step_up_limit;
u32 vdd_apc_step_down_limit;
+ u32 flags;
+ struct notifier_block freq_transition;
+ unsigned int freq;
+ struct cpufreq_mapping_info *cpufreq_mapping;
+ u32 cpufreq_mapping_size;
};
#define CPR_DEBUG_MASK_IRQ BIT(0)
@@ -228,7 +242,8 @@
} while (0)
-static u64 cpr_read_efuse_row(struct cpr_regulator *cpr_vreg, u32 row_num)
+static u64 cpr_read_efuse_row(struct cpr_regulator *cpr_vreg, u32 row_num,
+ bool use_tz_api)
{
int rc;
u64 efuse_bits;
@@ -242,7 +257,7 @@
u32 status;
} rsp;
- if (cpr_vreg->use_tz_api != true) {
+ if (!use_tz_api) {
efuse_bits = readll_relaxed(cpr_vreg->efuse_base
+ row_num * BYTES_PER_FUSE_ROW);
return efuse_bits;
@@ -265,6 +280,28 @@
return efuse_bits;
}
+static int cpr_get_freq_corner(struct cpr_regulator *cpr_vreg, int freq)
+{
+ int i;
+
+ for (i = 0; i < cpr_vreg->cpufreq_mapping_size; i++) {
+ if (freq == cpr_vreg->cpufreq_mapping[i].freq)
+ return cpr_vreg->cpufreq_mapping[i].corner;
+ }
+
+ return -EINVAL;
+}
+
+static int cpr_get_freq_quot_adjust(struct cpr_regulator *cpr_vreg, int freq)
+{
+ int i;
+
+ for (i = 0; i < cpr_vreg->cpufreq_mapping_size; i++) {
+ if (freq == cpr_vreg->cpufreq_mapping[i].freq)
+ return cpr_vreg->cpufreq_mapping[i].quot_adjust;
+ }
+ return 0;
+}
static bool cpr_is_allowed(struct cpr_regulator *cpr_vreg)
{
@@ -339,6 +376,13 @@
cpr_ctl_modify(cpr_vreg, RBCPR_CTL_LOOP_EN, 0);
}
+static bool cpr_ctl_is_enabled(struct cpr_regulator *cpr_vreg)
+{
+ u32 val;
+ val = cpr_read(cpr_vreg, REG_RBCPR_CTL);
+ return ((val & RBCPR_CTL_LOOP_EN) == RBCPR_CTL_LOOP_EN);
+}
+
static void cpr_regs_save(struct cpr_regulator *cpr_vreg)
{
int i, offset;
@@ -371,6 +415,13 @@
static void cpr_corner_restore(struct cpr_regulator *cpr_vreg, int corner)
{
u32 gcnt, ctl, irq, ro_sel;
+ int adjust;
+
+ if (cpr_vreg->flags & FLAGS_QUOT_ADJUST_WITH_FREQ) {
+ adjust = cpr_get_freq_quot_adjust(cpr_vreg, cpr_vreg->freq);
+ cpr_vreg->cpr_fuse_target_quot[corner] =
+ cpr_vreg->cpr_fuse_original_quot[corner] - adjust;
+ }
ro_sel = cpr_vreg->cpr_fuse_ro_sel[corner];
gcnt = cpr_vreg->gcnt | cpr_vreg->cpr_fuse_target_quot[corner];
@@ -973,23 +1024,54 @@
return 0;
}
-static int __devinit cpr_is_fuse_redundant(struct cpr_regulator *cpr_vreg,
- u32 redun_sel[4])
+static int __devinit cpr_fuse_is_setting_expected(struct cpr_regulator *cpr_vreg,
+ u32 sel_array[5])
{
u64 fuse_bits;
- int redundant;
+ u32 ret;
- fuse_bits = cpr_read_efuse_row(cpr_vreg, redun_sel[0]);
- fuse_bits = (fuse_bits >> redun_sel[1]) & ((1 << redun_sel[2]) - 1);
- if (fuse_bits == redun_sel[3])
- redundant = 1;
+ fuse_bits = cpr_read_efuse_row(cpr_vreg, sel_array[0], sel_array[4]);
+ ret = (fuse_bits >> sel_array[1]) & ((1 << sel_array[2]) - 1);
+ if (ret == sel_array[3])
+ ret = 1;
else
- redundant = 0;
+ ret = 0;
- pr_info("[row:%d] = 0x%llx @%d:%d = %d?: redundant=%d\n",
- redun_sel[0], fuse_bits,
- redun_sel[1], redun_sel[2], redun_sel[3], redundant);
- return redundant;
+ pr_info("[row:%d] = 0x%llx @%d:%d == %d ?: %s\n",
+ sel_array[0], fuse_bits,
+ sel_array[1], sel_array[2],
+ sel_array[3],
+ (ret == 1) ? "yes" : "no");
+ return ret;
+}
+
+static int cpr_voltage_uplift_wa_inc_volt(struct cpr_regulator *cpr_vreg,
+ struct device_node *of_node)
+{
+ u32 uplift_voltage;
+ u32 uplift_max_volt = 0;
+ int rc, i;
+
+ rc = of_property_read_u32(of_node,
+ "qti,cpr-uplift-voltage", &uplift_voltage);
+ if (rc < 0) {
+ pr_err("cpr-uplift-voltage is missing, rc = %d", rc);
+ return rc;
+ }
+ rc = of_property_read_u32(of_node,
+ "qti,cpr-uplift-max-volt", &uplift_max_volt);
+ if (rc < 0) {
+ pr_err("cpr-uplift-max-volt is missing, rc = %d", rc);
+ return rc;
+ }
+
+ for (i = 0; i < CPR_PVS_EFUSE_BINS_MAX; i++) {
+ cpr_vreg->pvs_init_v[i] += uplift_voltage;
+ if (cpr_vreg->pvs_init_v[i] > uplift_max_volt)
+ cpr_vreg->pvs_init_v[i] = uplift_max_volt;
+ }
+
+ return rc;
}
static int __devinit cpr_pvs_init(struct platform_device *pdev,
@@ -998,30 +1080,30 @@
struct device_node *of_node = pdev->dev.of_node;
u64 efuse_bits;
int rc, process;
- u32 pvs_fuse[3], pvs_fuse_redun_sel[4];
+ u32 pvs_fuse[4], pvs_fuse_redun_sel[5];
u32 init_v;
bool redundant;
size_t pvs_bins;
- rc = of_property_read_u32_array(of_node, "qcom,pvs-fuse-redun-sel",
- pvs_fuse_redun_sel, 4);
+ rc = of_property_read_u32_array(of_node, "qti,pvs-fuse-redun-sel",
+ pvs_fuse_redun_sel, 5);
if (rc < 0) {
pr_err("pvs-fuse-redun-sel missing: rc=%d\n", rc);
return rc;
}
- redundant = cpr_is_fuse_redundant(cpr_vreg, pvs_fuse_redun_sel);
+ redundant = cpr_fuse_is_setting_expected(cpr_vreg, pvs_fuse_redun_sel);
if (redundant) {
- rc = of_property_read_u32_array(of_node, "qcom,pvs-fuse-redun",
- pvs_fuse, 3);
+ rc = of_property_read_u32_array(of_node, "qti,pvs-fuse-redun",
+ pvs_fuse, 4);
if (rc < 0) {
pr_err("pvs-fuse-redun missing: rc=%d\n", rc);
return rc;
}
} else {
- rc = of_property_read_u32_array(of_node, "qcom,pvs-fuse",
- pvs_fuse, 3);
+ rc = of_property_read_u32_array(of_node, "qti,pvs-fuse",
+ pvs_fuse, 4);
if (rc < 0) {
pr_err("pvs-fuse missing: rc=%d\n", rc);
return rc;
@@ -1030,19 +1112,27 @@
/* Construct PVS process # from the efuse bits */
- efuse_bits = cpr_read_efuse_row(cpr_vreg, pvs_fuse[0]);
+ efuse_bits = cpr_read_efuse_row(cpr_vreg, pvs_fuse[0], pvs_fuse[3]);
cpr_vreg->pvs_bin = (efuse_bits >> pvs_fuse[1]) &
((1 << pvs_fuse[2]) - 1);
pvs_bins = 1 << pvs_fuse[2];
- rc = of_property_read_u32_array(of_node, "qcom,pvs-init-voltage",
+ rc = of_property_read_u32_array(of_node, "qti,pvs-init-voltage",
cpr_vreg->pvs_init_v, pvs_bins);
if (rc < 0) {
pr_err("pvs-init-voltage missing: rc=%d\n", rc);
return rc;
}
+ if (cpr_vreg->flags & FLAGS_UPLIFT_QUOT_VOLT) {
+ rc = cpr_voltage_uplift_wa_inc_volt(cpr_vreg, of_node);
+ if (rc < 0) {
+ pr_err("pvs volt uplift wa apply failed: %d", rc);
+ return rc;
+ }
+ }
+
init_v = cpr_vreg->pvs_init_v[cpr_vreg->pvs_bin];
for (process = NUM_APC_PVS - 1; process > APC_PVS_NO; process--) {
if (init_v <= cpr_vreg->pvs_corner_v[process][CPR_CORNER_TURBO])
@@ -1073,7 +1163,7 @@
do { \
if (!rc) { \
rc = of_property_read_u32(of_node, \
- "qcom," cpr_property, \
+ "qti," cpr_property, \
cpr_config); \
if (rc) { \
pr_err("Missing " #cpr_property \
@@ -1110,14 +1200,14 @@
/* Parse dependency parameters */
if (cpr_vreg->vdd_mx) {
- rc = of_property_read_u32(of_node, "qcom,vdd-mx-vmax",
+ rc = of_property_read_u32(of_node, "qti,vdd-mx-vmax",
&cpr_vreg->vdd_mx_vmax);
if (rc < 0) {
pr_err("vdd-mx-vmax missing: rc=%d\n", rc);
return rc;
}
- rc = of_property_read_u32(of_node, "qcom,vdd-mx-vmin-method",
+ rc = of_property_read_u32(of_node, "qti,vdd-mx-vmin-method",
&cpr_vreg->vdd_mx_vmin_method);
if (rc < 0) {
pr_err("vdd-mx-vmin-method missing: rc=%d\n", rc);
@@ -1143,40 +1233,131 @@
}
}
+static int cpr_voltage_uplift_wa_inc_quot(struct cpr_regulator *cpr_vreg,
+ struct device_node *of_node)
+{
+ u32 delta_quot[3];
+ int rc, i;
+
+ rc = of_property_read_u32_array(of_node,
+ "qti,cpr-uplift-quotient", delta_quot, 3);
+ if (rc < 0) {
+ pr_err("cpr-uplift-quotient is missing: %d", rc);
+ return rc;
+ }
+ for (i = CPR_CORNER_SVS; i < CPR_CORNER_MAX; i++)
+ cpr_vreg->cpr_fuse_target_quot[i] += delta_quot[i-1];
+ return rc;
+}
+
+static int cpr_get_of_cprfreq_mappings(struct cpr_regulator *cpr_vreg,
+ struct device *dev)
+{
+ int rc = 0;
+ int i, j, size, stripe_size, length;
+ struct property *prop;
+ u32 *tmp;
+
+ prop = of_find_property(dev->of_node, "qti,cpr-quot-adjust-table",
+ NULL);
+ if (prop) {
+ size = prop->length / sizeof(u32);
+ tmp = kzalloc(sizeof(u32) * size, GFP_KERNEL);
+ if (!tmp)
+ return -ENOMEM;
+
+ rc = of_property_read_u32_array(dev->of_node,
+ "qti,cpr-quot-adjust-table", tmp, size);
+ if (rc) {
+ pr_err("qti,cpr-quot-adjust-table missing, rc = %d",
+ rc);
+ kfree(tmp);
+ return rc;
+ }
+
+ length = 0;
+ stripe_size = 1 + sizeof(struct cpufreq_mapping_info) /
+ sizeof(int);
+ for (i = 0; i < size; i += stripe_size) {
+ if (tmp[i] == cpr_vreg->speed_bin)
+ length++;
+ }
+ if (i != size) {
+ pr_err("qti,cpr-quot-adjust-table data is not correct\n");
+ kfree(tmp);
+ return -EINVAL;
+ }
+
+ cpr_vreg->cpufreq_mapping_size = length;
+ if (length) {
+ cpr_vreg->cpufreq_mapping = devm_kzalloc(dev,
+ sizeof(struct cpufreq_mapping_info) * length,
+ GFP_KERNEL);
+
+ if (!cpr_vreg->cpufreq_mapping) {
+ kfree(tmp);
+ return -ENOMEM;
+ }
+
+ cpr_vreg->flags |= FLAGS_QUOT_ADJUST_WITH_FREQ;
+
+ for (i = 0, j = 0; i < size; i += stripe_size) {
+ if (tmp[i] == cpr_vreg->speed_bin) {
+ cpr_vreg->cpufreq_mapping[j].freq =
+ tmp[i+1];
+ cpr_vreg->cpufreq_mapping[j].quot_adjust
+ = tmp[i+2];
+ cpr_vreg->cpufreq_mapping[j].corner =
+ tmp[i+3];
+ ++j;
+ }
+
+ }
+
+ }
+
+ kfree(tmp);
+ }
+
+ return rc;
+}
+
static int __devinit cpr_init_cpr_efuse(struct platform_device *pdev,
struct cpr_regulator *cpr_vreg)
{
struct device_node *of_node = pdev->dev.of_node;
int i, rc = 0;
bool redundant;
- u32 cpr_fuse_redun_sel[4];
+ u32 cpr_fuse_redun_sel[5];
char *targ_quot_str, *ro_sel_str;
- u32 cpr_fuse_row;
+ u32 cpr_fuse_row[2];
u32 bp_cpr_disable, bp_scheme;
int bp_target_quot[CPR_CORNER_MAX];
int bp_ro_sel[CPR_CORNER_MAX];
u32 ro_sel, val;
u64 fuse_bits, fuse_bits_2;
- rc = of_property_read_u32_array(of_node, "qcom,cpr-fuse-redun-sel",
- cpr_fuse_redun_sel, 4);
+ rc = of_property_read_u32_array(of_node, "qti,cpr-fuse-redun-sel",
+ cpr_fuse_redun_sel, 5);
if (rc < 0) {
pr_err("cpr-fuse-redun-sel missing: rc=%d\n", rc);
return rc;
}
- redundant = cpr_is_fuse_redundant(cpr_vreg, cpr_fuse_redun_sel);
+ redundant = cpr_fuse_is_setting_expected(cpr_vreg, cpr_fuse_redun_sel);
if (redundant) {
- CPR_PROP_READ_U32(of_node, "cpr-fuse-redun-row",
- &cpr_fuse_row, rc);
- targ_quot_str = "qcom,cpr-fuse-redun-target-quot";
- ro_sel_str = "qcom,cpr-fuse-redun-ro-sel";
+ rc = of_property_read_u32_array(of_node,
+ "qti,cpr-fuse-redun-row",
+ cpr_fuse_row, 2);
+ targ_quot_str = "qti,cpr-fuse-redun-target-quot";
+ ro_sel_str = "qti,cpr-fuse-redun-ro-sel";
} else {
- CPR_PROP_READ_U32(of_node, "cpr-fuse-row",
- &cpr_fuse_row, rc);
- targ_quot_str = "qcom,cpr-fuse-target-quot";
- ro_sel_str = "qcom,cpr-fuse-ro-sel";
+ rc = of_property_read_u32_array(of_node,
+ "qti,cpr-fuse-row",
+ cpr_fuse_row, 2);
+ targ_quot_str = "qti,cpr-fuse-target-quot";
+ ro_sel_str = "qti,cpr-fuse-ro-sel";
}
if (rc)
return rc;
@@ -1200,12 +1381,13 @@
}
/* Read the control bits of eFuse */
- fuse_bits = cpr_read_efuse_row(cpr_vreg, cpr_fuse_row);
- pr_info("[row:%d] = 0x%llx\n", cpr_fuse_row, fuse_bits);
+ fuse_bits = cpr_read_efuse_row(cpr_vreg, cpr_fuse_row[0],
+ cpr_fuse_row[1]);
+ pr_info("[row:%d] = 0x%llx\n", cpr_fuse_row[0], fuse_bits);
if (redundant) {
if (of_property_read_bool(of_node,
- "qcom,cpr-fuse-redun-bp-cpr-disable")) {
+ "qti,cpr-fuse-redun-bp-cpr-disable")) {
CPR_PROP_READ_U32(of_node,
"cpr-fuse-redun-bp-cpr-disable",
&bp_cpr_disable, rc);
@@ -1216,21 +1398,23 @@
return rc;
fuse_bits_2 = fuse_bits;
} else {
- u32 temp_row;
+ u32 temp_row[2];
/* Use original fuse if no optional property */
CPR_PROP_READ_U32(of_node, "cpr-fuse-bp-cpr-disable",
&bp_cpr_disable, rc);
CPR_PROP_READ_U32(of_node, "cpr-fuse-bp-scheme",
&bp_scheme, rc);
- CPR_PROP_READ_U32(of_node, "cpr-fuse-row",
- &temp_row, rc);
+ rc = of_property_read_u32_array(of_node,
+ "qti,cpr-fuse-row",
+ temp_row, 2);
if (rc)
return rc;
- fuse_bits_2 = cpr_read_efuse_row(cpr_vreg, temp_row);
+ fuse_bits_2 = cpr_read_efuse_row(cpr_vreg, temp_row[0],
+ temp_row[1]);
pr_info("[original row:%d] = 0x%llx\n",
- temp_row, fuse_bits_2);
+ temp_row[0], fuse_bits_2);
}
} else {
CPR_PROP_READ_U32(of_node, "cpr-fuse-bp-cpr-disable",
@@ -1259,6 +1443,23 @@
i, ro_sel, val);
}
+ if (cpr_vreg->flags & FLAGS_UPLIFT_QUOT_VOLT) {
+ cpr_voltage_uplift_wa_inc_quot(cpr_vreg, of_node);
+ for (i = CPR_CORNER_SVS; i < CPR_CORNER_MAX; i++) {
+ pr_info("Corner[%d]: uplifted target quot = %d\n",
+ i, cpr_vreg->cpr_fuse_target_quot[i]);
+ }
+ }
+
+ for (i = CPR_CORNER_SVS; i < CPR_CORNER_MAX; i++) {
+ cpr_vreg->cpr_fuse_original_quot[i] =
+ cpr_vreg->cpr_fuse_target_quot[i];
+ }
+
+ rc = cpr_get_of_cprfreq_mappings(cpr_vreg, &pdev->dev);
+ if (rc)
+ return rc;
+
cpr_vreg->cpr_fuse_bits = fuse_bits;
if (!cpr_vreg->cpr_fuse_bits) {
cpr_vreg->cpr_fuse_disable = 1;
@@ -1364,7 +1565,7 @@
return rc;
/* Init module parameter with the DT value */
- cpr_vreg->enable = of_property_read_bool(of_node, "qcom,cpr-enable");
+ cpr_vreg->enable = of_property_read_bool(of_node, "qti,cpr-enable");
cpr_enable = (int) cpr_vreg->enable;
pr_info("CPR is %s by default.\n",
cpr_vreg->enable ? "enabled" : "disabled");
@@ -1452,11 +1653,6 @@
return -EINVAL;
}
- if (of_property_read_bool(pdev->dev.of_node, "qcom,use-tz-api"))
- cpr_vreg->use_tz_api = true;
- else
- cpr_vreg->use_tz_api = false;
-
return 0;
}
@@ -1465,14 +1661,84 @@
iounmap(cpr_vreg->efuse_base);
}
+static void cpr_parse_cond_min_volt_fuse(struct cpr_regulator *cpr_vreg,
+ struct device_node *of_node)
+{
+ int rc;
+ u32 fuse_sel[5];
+ /*
+ * Restrict all pvs corner voltages to a minimum value of
+ * qti,cpr-cond-min-voltage if the fuse defined in
+ * qti,cpr-fuse-cond-min-volt-sel does not read back with
+ * the expected value.
+ */
+ rc = of_property_read_u32_array(of_node,
+ "qti,cpr-fuse-cond-min-volt-sel", fuse_sel, 5);
+ if (!rc) {
+ if (!cpr_fuse_is_setting_expected(cpr_vreg, fuse_sel))
+ cpr_vreg->flags |= FLAGS_SET_MIN_VOLTAGE;
+ }
+}
+
+static void cpr_parse_speed_bin_fuse(struct cpr_regulator *cpr_vreg,
+ struct device_node *of_node)
+{
+ int rc;
+ u64 fuse_bits;
+ u32 fuse_sel[4];
+ u32 speed_bits;
+
+ rc = of_property_read_u32_array(of_node,
+ "qti,speed-bin-fuse-sel", fuse_sel, 4);
+
+ if (!rc) {
+ fuse_bits = cpr_read_efuse_row(cpr_vreg,
+ fuse_sel[0], fuse_sel[3]);
+ speed_bits = (fuse_bits >> fuse_sel[1]) &
+ ((1 << fuse_sel[2]) - 1);
+ pr_info("[row: %d]: 0x%llx, speed_bits = %d\n",
+ fuse_sel[0], fuse_bits, speed_bits);
+ cpr_vreg->speed_bin = speed_bits;
+ } else {
+ cpr_vreg->speed_bin = UINT_MAX;
+ }
+}
+
+static int cpr_voltage_uplift_enable_check(struct cpr_regulator *cpr_vreg,
+ struct device_node *of_node)
+{
+ int rc;
+ u32 fuse_sel[5];
+ u32 uplift_speed_bin;
+
+ rc = of_property_read_u32_array(of_node,
+ "qti,cpr-fuse-uplift-sel", fuse_sel, 5);
+ if (!rc) {
+ rc = of_property_read_u32(of_node,
+ "qti,cpr-uplift-speed-bin",
+ &uplift_speed_bin);
+ if (rc < 0) {
+ pr_err("qti,cpr-uplift-speed-bin missing\n");
+ return rc;
+ }
+ if (cpr_fuse_is_setting_expected(cpr_vreg, fuse_sel)
+ && (uplift_speed_bin == cpr_vreg->speed_bin)
+ && !(cpr_vreg->flags & FLAGS_SET_MIN_VOLTAGE)) {
+ cpr_vreg->flags |= FLAGS_UPLIFT_QUOT_VOLT;
+ }
+ }
+ return 0;
+}
+
static int __devinit cpr_voltage_plan_init(struct platform_device *pdev,
struct cpr_regulator *cpr_vreg)
{
struct device_node *of_node = pdev->dev.of_node;
- int rc, i;
+ int rc, i, j;
+ u32 min_uv = 0;
rc = of_property_read_u32_array(of_node,
- "qcom,pvs-corner-ceiling-slow",
+ "qti,pvs-corner-ceiling-slow",
&cpr_vreg->pvs_corner_v[APC_PVS_SLOW][CPR_CORNER_SVS],
CPR_CORNER_MAX - CPR_CORNER_SVS);
if (rc < 0) {
@@ -1481,7 +1747,7 @@
}
rc = of_property_read_u32_array(of_node,
- "qcom,pvs-corner-ceiling-nom",
+ "qti,pvs-corner-ceiling-nom",
&cpr_vreg->pvs_corner_v[APC_PVS_NOM][CPR_CORNER_SVS],
CPR_CORNER_MAX - CPR_CORNER_SVS);
if (rc < 0) {
@@ -1490,7 +1756,7 @@
}
rc = of_property_read_u32_array(of_node,
- "qcom,pvs-corner-ceiling-fast",
+ "qti,pvs-corner-ceiling-fast",
&cpr_vreg->pvs_corner_v[APC_PVS_FAST][CPR_CORNER_SVS],
CPR_CORNER_MAX - CPR_CORNER_SVS);
if (rc < 0) {
@@ -1498,6 +1764,22 @@
return rc;
}
+ cpr_parse_cond_min_volt_fuse(cpr_vreg, of_node);
+ cpr_parse_speed_bin_fuse(cpr_vreg, of_node);
+ rc = cpr_voltage_uplift_enable_check(cpr_vreg, of_node);
+ if (rc < 0) {
+ pr_err("voltage uplift enable check failed, %d\n", rc);
+ return rc;
+ }
+ if (cpr_vreg->flags & FLAGS_SET_MIN_VOLTAGE) {
+ of_property_read_u32(of_node, "qti,cpr-cond-min-voltage",
+ &min_uv);
+ for (i = APC_PVS_SLOW; i < NUM_APC_PVS; i++)
+ for (j = CPR_CORNER_SVS; j < CPR_CORNER_MAX; j++)
+ if (cpr_vreg->pvs_corner_v[i][j] < min_uv)
+ cpr_vreg->pvs_corner_v[i][j] = min_uv;
+ }
+
/* Set ceiling max and use it for APC_PVS_NO */
cpr_vreg->ceiling_max =
cpr_vreg->pvs_corner_v[APC_PVS_SLOW][CPR_CORNER_TURBO];
@@ -1512,6 +1794,51 @@
return 0;
}
+static int cpr_freq_transition(struct notifier_block *nb, unsigned long val,
+ void *data)
+{
+ int old_corner, new_corner;
+ struct cpr_regulator *cpr_vreg = container_of(nb, struct cpr_regulator,
+ freq_transition);
+ struct cpufreq_freqs *freqs = data;
+
+ mutex_lock(&cpr_vreg->cpr_mutex);
+ switch (val) {
+ case CPUFREQ_PRECHANGE:
+ cpr_vreg->freq = freqs->new;
+ if (freqs->new > freqs->old) {
+ old_corner = cpr_get_freq_corner(cpr_vreg, freqs->old);
+ new_corner = cpr_get_freq_corner(cpr_vreg, freqs->new);
+ if (new_corner > 0 && old_corner == new_corner &&
+ cpr_ctl_is_enabled(cpr_vreg)) {
+ cpr_ctl_disable(cpr_vreg);
+ cpr_irq_clr(cpr_vreg);
+ cpr_corner_restore(cpr_vreg, new_corner);
+ cpr_ctl_enable(cpr_vreg, new_corner);
+ }
+ }
+ break;
+ case CPUFREQ_POSTCHANGE:
+ if (freqs->new < freqs->old) {
+ old_corner = cpr_get_freq_corner(cpr_vreg, freqs->old);
+ new_corner = cpr_get_freq_corner(cpr_vreg, freqs->new);
+ if (new_corner > 0 && old_corner == new_corner &&
+ cpr_ctl_is_enabled(cpr_vreg)) {
+ cpr_ctl_disable(cpr_vreg);
+ cpr_irq_clr(cpr_vreg);
+ cpr_corner_restore(cpr_vreg, new_corner);
+ cpr_ctl_enable(cpr_vreg, new_corner);
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ mutex_unlock(&cpr_vreg->cpr_mutex);
+
+ return NOTIFY_OK;
+}
+
static int __devinit cpr_regulator_probe(struct platform_device *pdev)
{
struct cpr_regulator *cpr_vreg;
@@ -1595,6 +1922,10 @@
platform_set_drvdata(pdev, cpr_vreg);
the_cpr = cpr_vreg;
+ cpr_vreg->freq_transition.notifier_call = cpr_freq_transition;
+ if (cpr_vreg->flags & FLAGS_QUOT_ADJUST_WITH_FREQ)
+ cpufreq_register_notifier(&cpr_vreg->freq_transition,
+ CPUFREQ_TRANSITION_NOTIFIER);
return 0;
@@ -1615,6 +1946,9 @@
cpr_irq_set(cpr_vreg, 0);
}
+ if (cpr_vreg->flags & FLAGS_QUOT_ADJUST_WITH_FREQ)
+ cpufreq_unregister_notifier(&cpr_vreg->freq_transition,
+ CPUFREQ_TRANSITION_NOTIFIER);
cpr_apc_exit(cpr_vreg);
regulator_unregister(cpr_vreg->rdev);
}
diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
index 85a1468..60856c2 100644
--- a/arch/arm/mach-msm/cpufreq.c
+++ b/arch/arm/mach-msm/cpufreq.c
@@ -324,11 +324,15 @@
case CPU_UP_CANCELED:
if (is_clk) {
clk_disable_unprepare(cpu_clk[cpu]);
+ clk_disable_unprepare(l2_clk);
update_l2_bw(NULL);
}
break;
case CPU_UP_PREPARE:
if (is_clk) {
+ rc = clk_prepare_enable(l2_clk);
+ if (rc < 0)
+ return NOTIFY_BAD;
rc = clk_prepare_enable(cpu_clk[cpu]);
if (rc < 0)
return NOTIFY_BAD;
diff --git a/arch/arm/mach-msm/devices-8930.c b/arch/arm/mach-msm/devices-8930.c
index c4fe0df..94040b6 100644
--- a/arch/arm/mach-msm/devices-8930.c
+++ b/arch/arm/mach-msm/devices-8930.c
@@ -31,7 +31,6 @@
#include "rpm_stats.h"
#include "rpm_rbcpr_stats.h"
#include "footswitch.h"
-#include "acpuclock-krait.h"
#include "pm.h"
#ifdef CONFIG_MSM_MPM
@@ -675,16 +674,9 @@
.id = -1,
};
-static struct acpuclk_platform_data acpuclk_8930_pdata = {
- .uses_pm8917 = false,
-};
-
struct platform_device msm8930_device_acpuclk = {
.name = "acpuclk-8930",
.id = -1,
- .dev = {
- .platform_data = &acpuclk_8930_pdata,
- },
};
struct platform_device msm8930aa_device_acpuclk = {
@@ -692,16 +684,9 @@
.id = -1,
};
-static struct acpuclk_platform_data acpuclk_8930ab_pdata = {
- .uses_pm8917 = false,
-};
-
struct platform_device msm8930ab_device_acpuclk = {
.name = "acpuclk-8930ab",
.id = -1,
- .dev = {
- .platform_data = &acpuclk_8930ab_pdata,
- },
};
static struct fs_driver_data gfx3d_fs_data = {
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 20e3c3b..174a50a 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -11,6 +11,7 @@
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/cpu.h>
+#include <linux/ratelimit.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
@@ -150,6 +151,29 @@
.notifier_call = hotplug_rtb_callback,
};
+static int hotplug_cpu_check_callback(struct notifier_block *nfb,
+ unsigned long action, void *hcpu)
+{
+ int cpu = (int)hcpu;
+
+ switch (action & (~CPU_TASKS_FROZEN)) {
+ case CPU_DOWN_PREPARE:
+ if (cpu == 0) {
+ pr_err_ratelimited("CPU0 hotplug is not supported\n");
+ return NOTIFY_BAD;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+static struct notifier_block hotplug_cpu_check_notifier = {
+ .notifier_call = hotplug_cpu_check_callback,
+ .priority = INT_MAX,
+};
+
int msm_platform_secondary_init(unsigned int cpu)
{
int ret;
@@ -170,6 +194,12 @@
static int __init init_hotplug(void)
{
- return register_hotcpu_notifier(&hotplug_rtb_notifier);
+ int rc;
+
+ rc = register_hotcpu_notifier(&hotplug_rtb_notifier);
+ if (rc)
+ return rc;
+
+ return register_hotcpu_notifier(&hotplug_cpu_check_notifier);
}
early_initcall(init_hotplug);
diff --git a/arch/arm/mach-msm/idle-macros.S b/arch/arm/mach-msm/idle-macros.S
deleted file mode 100644
index 3d0c937..0000000
--- a/arch/arm/mach-msm/idle-macros.S
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <asm/hardware/cache-l2x0.h>
-
-/* Add 300 NOPs after 'wfi' for 8x25 target */
-.macro DELAY_8x25, rept
-#ifdef CONFIG_ARCH_MSM8625
- .rept \rept
- nop
- .endr
-#endif
-.endm
-
-/* Switch between smp_to_amp/amp_to_smp configuration */
-.macro SET_SMP_COHERENCY, on = 0
- ldr r0, =target_type
- ldr r0, [r0]
- mov r1, #TARGET_IS_8625
- cmp r0, r1
- bne skip\@
- mrc p15, 0, r0, c1, c0, 1 /* read ACTLR register */
- .if \on
- orr r0, r0, #(1 << 6) /* Set the SMP bit in ACTLR */
- .else
- bic r0, r0, #(1 << 6) /* Clear the SMP bit */
- .endif
- mcr p15, 0, r0, c1, c0, 1 /* write ACTLR register */
- isb
-skip\@:
-.endm
-
-/*
- * Enable the "L2" cache, not require to restore the controller registers
- */
-.macro ENABLE_8x25_L2
- ldr r0, =target_type
- ldr r0, [r0]
- mov r1, #TARGET_IS_8625
- cmp r0, r1
- bne skip_enable\@
- ldr r0, =apps_power_collapse
- ldr r0, [r0]
- cmp r0, #POWER_COLLAPSED
- bne skip_enable\@
- ldr r0, =l2x0_base_addr
- ldr r0, [r0]
- mov r1, #0x1
- str r1, [r0, #L2X0_CTRL]
- dmb
-skip_enable\@:
-.endm
-
-/*
- * Perform the required operation
- * operation: type of operation on l2 cache (e.g: clean&inv or inv)
- * l2_enable: enable or disable
- */
-.macro DO_CACHE_OPERATION, operation, l2_enable
- ldr r2, =l2x0_base_addr
- ldr r2, [r2]
- ldr r0, =0xffff
- str r0, [r2, #\operation]
-wait\@:
- ldr r0, [r2, #\operation]
- ldr r1, =0xffff
- ands r0, r0, r1
- bne wait\@
-l2x_sync\@:
- mov r0, #0x0
- str r0, [r2, #L2X0_CACHE_SYNC]
-sync\@:
- ldr r0, [r2, #L2X0_CACHE_SYNC]
- ands r0, r0, #0x1
- bne sync\@
- mov r1, #\l2_enable
- str r1, [r2, #L2X0_CTRL]
-.endm
-
-/*
- * Clean and invalidate the L2 cache.
- * 1. Check the target type
- * 2. Check whether we are coming from PC are not
- * 3. Save 'aux', 'data latency', & 'prefetch ctlr' registers
- * 4. Start L2 clean & invalidation operation
- * 5. Disable the L2 cache
- */
-.macro SUSPEND_8x25_L2
- ldr r0, =target_type
- ldr r0, [r0]
- mov r1, #TARGET_IS_8625
- cmp r0, r1
- bne skip_suspend\@
- ldr r0, =apps_power_collapse
- ldr r0, [r0]
- cmp r0, #POWER_COLLAPSED
- bne skip_suspend\@
- ldr r0, =l2x0_saved_ctrl_reg_val
- ldr r1, =l2x0_base_addr
- ldr r1, [r1]
- ldr r2, [r1, #L2X0_AUX_CTRL]
- str r2, [r0, #0x0] /* store aux_ctlr reg value */
- ldr r2, [r1, #L2X0_DATA_LATENCY_CTRL]
- str r2, [r0, #0x4] /* store data latency reg value */
- ldr r2, [r1, #L2X0_PREFETCH_CTRL]
- str r2, [r0, #0x8] /* store prefetch_ctlr reg value */
- DO_CACHE_OPERATION L2X0_CLEAN_INV_WAY OFF
- dmb
-skip_suspend\@:
-.endm
-
-/*
- * Coming back from a successful PC
- * 1. Check the target type
- * 2. Check whether we are going to PC are not
- * 3. Disable the L2 cache
- * 4. Restore 'aux', 'data latency', & 'prefetch ctlr' reg
- * 5. Invalidate the cache
- * 6. Enable the L2 cache
- */
-.macro RESUME_8x25_L2
- ldr r0, =target_type
- ldr r0, [r0]
- mov r1, #TARGET_IS_8625
- cmp r0, r1
- bne skip_resume\@
- ldr r0, =apps_power_collapse
- ldr r0, [r0]
- cmp r0, #POWER_COLLAPSED
- bne skip_resume\@
- ldr r1, =l2x0_base_addr
- ldr r1, [r1]
- mov r0, #0x0
- str r0, [r1, #L2X0_CTRL]
- ldr r0, =l2x0_saved_ctrl_reg_val
- ldr r2, [r0, #0x0]
- str r2, [r1, #L2X0_AUX_CTRL] /* restore aux_ctlr reg value */
- ldr r2, [r0, #0x4]
- str r2, [r1, #L2X0_DATA_LATENCY_CTRL]
- ldr r2, [r0, #0x8]
- str r2, [r1, #L2X0_PREFETCH_CTRL]
- DO_CACHE_OPERATION L2X0_INV_WAY ON
-skip_resume\@:
-.endm
diff --git a/arch/arm/mach-msm/idle-v7.S b/arch/arm/mach-msm/idle-v7.S
index 2956bd6..a133470 100644
--- a/arch/arm/mach-msm/idle-v7.S
+++ b/arch/arm/mach-msm/idle-v7.S
@@ -19,357 +19,7 @@
#include <linux/threads.h>
#include <asm/assembler.h>
-#include "idle.h"
-#include "idle-macros.S"
-
-#ifdef CONFIG_MSM_SCM
-#define SCM_SVC_BOOT 0x1
-#define SCM_CMD_TERMINATE_PC 0x2
-#define SCM_CMD_CORE_HOTPLUGGED 0x10
-#endif
-
-ENTRY(msm_arch_idle)
-#ifdef CONFIG_ARCH_MSM_KRAIT
- mrc p15, 0, r0, c0, c0, 0
- bic r1, r0, #0xff
- movw r2, #0x0400
- movt r2, #0x511F
- movw r3, #0x0600
- movt r3, #0x510F
- cmp r2, r1
- cmpne r3, r1
- bne go_wfi
-
- mrs r0, cpsr
- cpsid if
-
- mrc p15, 7, r1, c15, c0, 5
- bic r2, r1, #0x20000
- mcr p15, 7, r2, c15, c0, 5
- isb
-
-go_wfi:
- wfi
- bne wfi_done
- mcr p15, 7, r1, c15, c0, 5
- isb
- msr cpsr_c, r0
-
-wfi_done:
- bx lr
-#else
- wfi
-#ifdef CONFIG_ARCH_MSM8X60
- mrc p14, 1, r1, c1, c5, 4 /* read ETM PDSR to clear sticky bit */
- mrc p14, 0, r1, c1, c5, 4 /* read DBG PRSR to clear sticky bit */
- isb
-#endif
- bx lr
-#endif
-ENTRY(msm_pm_pc_hotplug)
- stmfd sp!, {lr}
-#if defined(CONFIG_MSM_FIQ_SUPPORT)
- cpsid f
-#endif
-
-#if defined(CONFIG_MSM_JTAG) || defined(CONFIG_MSM_JTAG_MM)
- bl msm_jtag_save_state
-#endif
- mov r1, #0
- mcr p15, 2, r1, c0, c0, 0 /*CCSELR*/
- isb
- mrc p15, 1, r1, c0, c0, 0 /*CCSIDR*/
- mov r2, #1
- and r1, r2, r1, ASR #30 /* Check if the cache is write back */
- cmp r1, #1
- bleq v7_flush_kern_cache_all
-
- mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
- and r0, r0, #15 /* what CPU am I */
-
- ldr r1, =msm_pc_debug_counters /*load the IMEM debug location */
- ldr r1, [r1]
- cmp r1, #0
- beq skip_hp_debug1
- add r1, r1, r0, LSL #4 /* debug location for this CPU */
- ldr r2, [r1]
- add r2, #1
- str r2, [r1]
-skip_hp_debug1:
-
-#ifdef CONFIG_MSM_SCM
- ldr r0, =SCM_SVC_BOOT
- ldr r1, =SCM_CMD_TERMINATE_PC
- ldr r2, =SCM_CMD_CORE_HOTPLUGGED
- bl scm_call_atomic1
-#else
- mrc p15, 0, r3, c1, c0, 0 /* read current CR */
- bic r0, r3, #(1 << 2) /* clear dcache bit */
- bic r0, r0, #(1 << 12) /* clear icache bit */
- mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
- isb
- wfi
- mcr p15, 0, r3, c1, c0, 0 /* restore d/i cache */
- isb
-#endif
-
-#if defined(CONFIG_MSM_FIQ_SUPPORT)
- cpsie f
-#endif
- mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
- and r0, r0, #15 /* what CPU am I */
-
- ldr r1, =msm_pc_debug_counters /*load the IMEM debug location */
- ldr r1, [r1]
- cmp r1, #0
- beq skip_hp_debug2
- add r1, r1, r0, LSL #4 /* debug location for this CPU */
- add r1, #8
- ldr r2, [r1]
- add r2, #1
- str r2, [r1]
-skip_hp_debug2:
-#if defined(CONFIG_MSM_JTAG) || defined(CONFIG_MSM_JTAG_MM)
- bl msm_jtag_restore_state
-#endif
- mov r0, #0 /* return power collapse failed */
- ldmfd sp!, {lr}
- bx lr
-
-ENTRY(msm_pm_collapse)
-#if defined(CONFIG_MSM_FIQ_SUPPORT)
- cpsid f
-#endif
-
- ldr r0, =msm_saved_state /* address of msm_saved_state ptr */
- ldr r0, [r0] /* load ptr */
-#if (NR_CPUS >= 2)
- mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
- ands r1, r1, #15 /* What CPU am I */
- mov r2, #CPU_SAVED_STATE_SIZE
- mul r1, r1, r2
- add r0, r0, r1
-#endif
-
- stmia r0!, {r4-r14}
- mrc p15, 0, r1, c1, c0, 0 /* MMU control */
- mrc p15, 0, r2, c2, c0, 0 /* TTBR0 */
- mrc p15, 0, r3, c3, c0, 0 /* dacr */
-#ifdef CONFIG_ARCH_MSM_SCORPION
- /* This instruction is not valid for non scorpion processors */
- mrc p15, 3, r4, c15, c0, 3 /* L2CR1 is the L2 cache control reg 1 */
-#endif
- mrc p15, 0, r5, c10, c2, 0 /* PRRR */
- mrc p15, 0, r6, c10, c2, 1 /* NMRR */
- mrc p15, 0, r7, c1, c0, 1 /* ACTLR */
- mrc p15, 0, r8, c2, c0, 1 /* TTBR1 */
- mrc p15, 0, r9, c13, c0, 3 /* TPIDRURO */
- mrc p15, 0, ip, c13, c0, 1 /* context ID */
- stmia r0!, {r1-r9, ip}
-
-#if defined(CONFIG_MSM_JTAG) || defined(CONFIG_MSM_JTAG_MM)
- bl msm_jtag_save_state
-#endif
-
- ldr r0, =msm_pm_flush_l2_flag
- ldr r0, [r0]
- mov r1, #0
- mcr p15, 2, r1, c0, c0, 0 /*CCSELR*/
- isb
- mrc p15, 1, r1, c0, c0, 0 /*CCSIDR*/
- mov r2, #1
- and r1, r2, r1, ASR #30 /* Check if the cache is write back */
- orr r1, r0, r1
- and r1, r1, #1
- cmp r1, #1
- bne skip
- bl v7_flush_dcache_all
- ldr r1, =msm_pm_flush_l2_fn
- ldr r1, [r1]
- cmp r1, #0
- blxne r1
-
-skip:
- ldr r1, =msm_pm_disable_l2_fn
- ldr r1, [r1]
- cmp r1, #0
- blxne r1
- dmb
-
- mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
- and r0, r0, #15 /* what CPU am I */
-
- ldr r1, =msm_pc_debug_counters /*load the IMEM debug location */
- ldr r1, [r1]
- cmp r1, #0
- beq skip_pc_debug1
- add r1, r1, r0, LSL #4 /* debug location for this CPU */
- ldr r2, [r1]
- add r2, #1
- str r2, [r1]
-skip_pc_debug1:
-
-#ifdef CONFIG_MSM_SCM
- ldr r0, =SCM_SVC_BOOT
- ldr r1, =SCM_CMD_TERMINATE_PC
- ldr r2, =msm_pm_flush_l2_flag
- ldr r2, [r2]
- bl scm_call_atomic1
-#else
- mrc p15, 0, r4, c1, c0, 0 /* read current CR */
- bic r0, r4, #(1 << 2) /* clear dcache bit */
- bic r0, r0, #(1 << 12) /* clear icache bit */
- mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
- isb
-
- SUSPEND_8x25_L2
- SET_SMP_COHERENCY OFF
- wfi
- DELAY_8x25 300
-
- mcr p15, 0, r4, c1, c0, 0 /* restore d/i cache */
- isb
- ENABLE_8x25_L2 /* enable only l2, no need to restore the reg back */
- SET_SMP_COHERENCY ON
-#endif
-
-#if defined(CONFIG_MSM_FIQ_SUPPORT)
- cpsie f
-#endif
- mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
- and r0, r0, #15 /* what CPU am I */
-
- ldr r1, =msm_pc_debug_counters /*load the IMEM debug location */
- ldr r1, [r1]
- cmp r1, #0
- beq skip_pc_debug2
- add r1, r1, r0, LSL #4 /* debug location for this CPU */
- add r1, #8
- ldr r2, [r1]
- add r2, #1
- str r2, [r1]
-
-skip_pc_debug2:
- ldr r1, =msm_pm_enable_l2_fn
- ldr r1, [r1]
- cmp r1, #0
- blxne r1
- dmb
-
-#if defined(CONFIG_MSM_JTAG) || defined(CONFIG_MSM_JTAG_MM)
- bl msm_jtag_restore_state
-#endif
- ldr r0, =msm_saved_state /* address of msm_saved_state ptr */
- ldr r0, [r0] /* load ptr */
-#if (NR_CPUS >= 2)
- mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
- ands r1, r1, #15 /* What CPU am I */
- mov r2, #CPU_SAVED_STATE_SIZE
- mul r2, r2, r1
- add r0, r0, r2
-#endif
- ldmfd r0, {r4-r14} /* restore registers */
- mov r0, #0 /* return power collapse failed */
- bx lr
-
-ENTRY(msm_pm_collapse_exit)
-#if 0 /* serial debug */
- mov r0, #0x80000016
- mcr p15, 0, r0, c15, c2, 4
- mov r0, #0xA9000000
- add r0, r0, #0x00A00000 /* UART1 */
- /*add r0, r0, #0x00C00000*/ /* UART3 */
- mov r1, #'A'
- str r1, [r0, #0x00C]
-#endif
- ldr r1, =msm_saved_state_phys
- ldr r2, =msm_pm_collapse_exit
- adr r3, msm_pm_collapse_exit
- add r1, r1, r3
- sub r1, r1, r2
- ldr r1, [r1]
- add r1, r1, #CPU_SAVED_STATE_SIZE
-#if (NR_CPUS >= 2)
- mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
- ands r2, r2, #15 /* What CPU am I */
- mov r3, #CPU_SAVED_STATE_SIZE
- mul r2, r2, r3
- add r1, r1, r2
-#endif
-
- ldmdb r1!, {r2-r11}
- mcr p15, 0, r4, c3, c0, 0 /* dacr */
- mcr p15, 0, r3, c2, c0, 0 /* TTBR0 */
-#ifdef CONFIG_ARCH_MSM_SCORPION
- /* This instruction is not valid for non scorpion processors */
- mcr p15, 3, r5, c15, c0, 3 /* L2CR1 */
-#endif
- mcr p15, 0, r6, c10, c2, 0 /* PRRR */
- mcr p15, 0, r7, c10, c2, 1 /* NMRR */
- mcr p15, 0, r8, c1, c0, 1 /* ACTLR */
- mcr p15, 0, r9, c2, c0, 1 /* TTBR1 */
- mcr p15, 0, r10, c13, c0, 3 /* TPIDRURO */
- mcr p15, 0, r11, c13, c0, 1 /* context ID */
- isb
- ldmdb r1!, {r4-r14}
- ldr r0, =msm_pm_pc_pgd
- ldr r1, =msm_pm_collapse_exit
- adr r3, msm_pm_collapse_exit
- add r0, r0, r3
- sub r0, r0, r1
- ldr r0, [r0]
- mrc p15, 0, r1, c2, c0, 0 /* save current TTBR0 */
- and r3, r1, #0x7f /* mask to get TTB flags */
- orr r0, r0, r3 /* add TTB flags to switch TTBR value */
- mcr p15, 0, r0, c2, c0, 0 /* temporary switch TTBR0 */
- isb
- mcr p15, 0, r2, c1, c0, 0 /* MMU control */
- isb
-msm_pm_mapped_pa:
- /* Switch to virtual */
- ldr r0, =msm_pm_pa_to_va
- mov pc, r0
-msm_pm_pa_to_va:
- mcr p15, 0, r1, c2, c0, 0 /* restore TTBR0 */
- isb
- mcr p15, 0, r3, c8, c7, 0 /* UTLBIALL */
- mcr p15, 0, r3, c7, c5, 6 /* BPIALL */
- dsb
- isb
-
-#ifdef CONFIG_ARCH_MSM_KRAIT
- mrc p15, 0, r1, c0, c0, 0
- ldr r3, =0xff00fc00
- and r3, r1, r3
- ldr r1, =0x51000400
- cmp r3, r1
- mrceq p15, 7, r3, c15, c0, 2
- biceq r3, r3, #0x400
- mcreq p15, 7, r3, c15, c0, 2
-#else
- RESUME_8x25_L2
- SET_SMP_COHERENCY ON
-#endif
-
- ldr r1, =msm_pm_enable_l2_fn
- ldr r1, [r1]
- cmp r1, #0
- stmfd sp!, {lr}
- blxne r1
- dmb
-#if defined(CONFIG_MSM_JTAG) || defined(CONFIG_MSM_JTAG_MM)
- bl msm_jtag_restore_state
-#endif
- ldmfd sp!, {lr}
- mov r0, #1
- bx lr
- nop
- nop
- nop
- nop
- nop
-1: b 1b
-
+ .arm
ENTRY(msm_pm_boot_entry)
mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
and r0, r0, #15 /* what CPU am I */
@@ -399,80 +49,14 @@
add r1, r1, r0, LSL #2 /* locate boot vector for our cpu */
ldr pc, [r1] /* jump */
-ENTRY(msm_pm_set_l2_flush_flag)
- ldr r1, =msm_pm_flush_l2_flag
- str r0, [r1]
- bx lr
-
-ENTRY(msm_pm_get_l2_flush_flag)
- ldr r1, =msm_pm_flush_l2_flag
- ldr r0, [r1]
- bx lr
+3: .long .
.data
- .globl msm_pm_pc_pgd
-msm_pm_pc_pgd:
- .long 0x0
-
- .globl msm_saved_state
-msm_saved_state:
- .long 0x0
-
- .globl msm_saved_state_phys
-msm_saved_state_phys:
- .long 0x0
-
.globl msm_pm_boot_vector
msm_pm_boot_vector:
.space 4 * NR_CPUS
- .globl target_type
-target_type:
- .long 0x0
-
- .globl apps_power_collapse
-apps_power_collapse:
- .long 0x0
-
- .globl l2x0_base_addr
-l2x0_base_addr:
- .long 0x0
-
.globl msm_pc_debug_counters_phys
msm_pc_debug_counters_phys:
.long 0x0
-
- .globl msm_pc_debug_counters
-msm_pc_debug_counters:
- .long 0x0
-
- .globl msm_pm_enable_l2_fn
-msm_pm_enable_l2_fn:
- .long 0x0
-
- .globl msm_pm_disable_l2_fn
-msm_pm_disable_l2_fn:
- .long 0x0
-
- .globl msm_pm_flush_l2_fn
-msm_pm_flush_l2_fn:
- .long 0x0
-
-/*
- * Default the l2 flush flag to 1 so that caches are flushed during power
- * collapse unless the L2 driver decides to flush them only during L2
- * Power collapse.
- */
-msm_pm_flush_l2_flag:
- .long 0x1
-
-/*
- * Save & restore l2x0 registers while system is entering and resuming
- * from Power Collapse.
- * 1. aux_ctrl_save (0x0)
- * 2. data_latency_ctrl (0x4)
- * 3. prefetch control (0x8)
- */
-l2x0_saved_ctrl_reg_val:
- .space 4 * 3
diff --git a/arch/arm/mach-msm/idle.h b/arch/arm/mach-msm/idle.h
index 72f1a03..0fb96c3 100644
--- a/arch/arm/mach-msm/idle.h
+++ b/arch/arm/mach-msm/idle.h
@@ -14,49 +14,13 @@
#ifndef _ARCH_ARM_MACH_MSM_IDLE_H_
#define _ARCH_ARM_MACH_MSM_IDLE_H_
-/* 11 general purpose registers (r4-r14), 10 cp15 registers */
-#define CPU_SAVED_STATE_SIZE (4 * 11 + 4 * 10)
-
-#define ON 1
-#define OFF 0
-#define TARGET_IS_8625 1
-#define POWER_COLLAPSED 1
-
-#ifndef __ASSEMBLY__
-
-int msm_arch_idle(void);
-int msm_pm_collapse(void);
-int msm_pm_pc_hotplug(void);
-void msm_pm_collapse_exit(void);
-extern void *msm_saved_state;
-extern void (*msm_pm_disable_l2_fn)(void);
-extern void (*msm_pm_enable_l2_fn)(void);
-extern void (*msm_pm_flush_l2_fn)(void);
-extern unsigned long msm_saved_state_phys;
-
#ifdef CONFIG_CPU_V7
-void msm_pm_boot_entry(void);
-void msm_pm_set_l2_flush_flag(unsigned int flag);
-int msm_pm_get_l2_flush_flag(void);
-extern unsigned long msm_pm_pc_pgd;
extern unsigned long msm_pm_boot_vector[NR_CPUS];
-extern uint32_t target_type;
-extern uint32_t apps_power_collapse;
-extern uint32_t *l2x0_base_addr;
+void msm_pm_boot_entry(void);
#else
-static inline void msm_pm_set_l2_flush_flag(unsigned int flag)
-{
- /* empty */
-}
static inline void msm_pm_boot_entry(void)
{
/* empty */
}
-static inline void msm_pm_write_boot_vector(unsigned int cpu,
- unsigned long address)
-{
- /* empty */
-}
-#endif
#endif
#endif
diff --git a/arch/arm/mach-msm/include/mach/clk-provider.h b/arch/arm/mach-msm/include/mach/clk-provider.h
index 027606e..4529a81 100644
--- a/arch/arm/mach-msm/include/mach/clk-provider.h
+++ b/arch/arm/mach-msm/include/mach/clk-provider.h
@@ -23,6 +23,7 @@
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/regulator/consumer.h>
+#include <linux/seq_file.h>
#include <mach/clk.h>
/*
@@ -41,6 +42,21 @@
#define ENABLE_VOTED 4 /* Bit pol: 1 = running; delay on disable */
#define DELAY 5 /* No bit to check, just delay */
+struct clk_register_data {
+ char *name;
+ u32 offset;
+};
+#ifdef CONFIG_DEBUG_FS
+void clk_debug_print_hw(struct clk *clk, struct seq_file *f);
+#else
+static inline void clk_debug_print_hw(struct clk *clk, struct seq_file *f) {}
+#endif
+
+#define CLK_WARN(clk, cond, fmt, ...) do { \
+ clk_debug_print_hw(clk, NULL); \
+ WARN(cond, "%s: " fmt, (clk)->dbg_name, ##__VA_ARGS__); \
+} while (0)
+
/**
* struct clk_vdd_class - Voltage scaling class
* @class_name: name of the class
@@ -129,6 +145,8 @@
int (*set_parent)(struct clk *clk, struct clk *parent);
struct clk *(*get_parent)(struct clk *clk);
bool (*is_local)(struct clk *clk);
+ void __iomem *(*list_registers)(struct clk *clk, int n,
+ struct clk_register_data **regs, u32 *size);
};
/**
diff --git a/arch/arm/mach-msm/include/mach/kgsl.h b/arch/arm/mach-msm/include/mach/kgsl.h
index 2d7e8df..f398652 100644
--- a/arch/arm/mach-msm/include/mach/kgsl.h
+++ b/arch/arm/mach-msm/include/mach/kgsl.h
@@ -81,9 +81,9 @@
int (*set_grp_async)(void);
unsigned int idle_timeout;
bool strtstp_sleepwake;
+ bool bus_control;
unsigned int clk_map;
unsigned int idle_needed;
- unsigned int step_mul;
struct msm_bus_scale_pdata *bus_scale_table;
struct kgsl_device_iommu_data *iommu_data;
int iommu_count;
diff --git a/arch/arm/mach-msm/include/mach/mpm.h b/arch/arm/mach-msm/include/mach/mpm.h
index e76a6a9..abfac48 100644
--- a/arch/arm/mach-msm/include/mach/mpm.h
+++ b/arch/arm/mach-msm/include/mach/mpm.h
@@ -112,11 +112,13 @@
* @sclk_count: wakeup time in sclk counts for programmed RPM wakeup
* @from_idle: indicates if the sytem is entering low power mode as a part of
* suspend/idle task.
+ * @cpumask: the next cpu to wakeup.
*
* Low power management code calls into this API to configure the MPM to
* monitor the active irqs before going to sleep.
*/
-void msm_mpm_enter_sleep(uint32_t sclk_count, bool from_idle);
+void msm_mpm_enter_sleep(uint32_t sclk_count, bool from_idle,
+ const struct cpumask *cpumask);
/**
* msm_mpm_exit_sleep() -Called from PM code after resuming from low power mode
*
@@ -159,7 +161,8 @@
{ return false; }
static inline bool msm_mpm_gpio_irqs_detectable(bool from_idle)
{ return false; }
-static inline void msm_mpm_enter_sleep(uint32_t sclk_count, bool from_idle) {}
+static inline void msm_mpm_enter_sleep(uint32_t sclk_count, bool from_idle
+ const struct cpumask *cpumask) {}
static inline void msm_mpm_exit_sleep(bool from_idle) {}
static inline void __init of_mpm_init(struct device_node *node) {}
#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_smd.h b/arch/arm/mach-msm/include/mach/msm_smd.h
index cd07662..e3bd488 100644
--- a/arch/arm/mach-msm/include/mach/msm_smd.h
+++ b/arch/arm/mach-msm/include/mach/msm_smd.h
@@ -24,6 +24,7 @@
#include <mach/msm_smem.h>
typedef struct smd_channel smd_channel_t;
+struct cpumask;
#define SMD_MAX_CH_NAME_LEN 20 /* includes null char at end */
@@ -217,13 +218,15 @@
* particular channel.
* @ch: open channel handle to use for the edge
* @mask: 1 = mask interrupts; 0 = unmask interrupts
+ * @cpumask cpumask for the next cpu scheduled to be woken up
* @returns: 0 for success; < 0 for failure
*
* Note that this enables/disables all interrupts from the remote subsystem for
* all channels. As such, it should be used with care and only for specific
* use cases such as power-collapse sequencing.
*/
-int smd_mask_receive_interrupt(smd_channel_t *ch, bool mask);
+int smd_mask_receive_interrupt(smd_channel_t *ch, bool mask,
+ const struct cpumask *cpumask);
/* Starts a packet transaction. The size of the packet may exceed the total
* size of the smd ring buffer.
@@ -411,7 +414,8 @@
{
}
-static inline int smd_mask_receive_interrupt(smd_channel_t *ch, bool mask)
+static inline int smd_mask_receive_interrupt(smd_channel_t *ch, bool mask,
+ struct cpumask *cpumask)
{
return -ENODEV;
}
diff --git a/arch/arm/mach-msm/include/mach/qdsp6v2/usf.h b/arch/arm/mach-msm/include/mach/qdsp6v2/usf.h
index 2e15cae..9a27fd2 100644
--- a/arch/arm/mach-msm/include/mach/qdsp6v2/usf.h
+++ b/arch/arm/mach-msm/include/mach/qdsp6v2/usf.h
@@ -73,7 +73,8 @@
#define USF_TSC_PTR_EVENT_IND 1
#define USF_MOUSE_EVENT_IND 2
#define USF_KEYBOARD_EVENT_IND 3
-#define USF_MAX_EVENT_IND 4
+#define USF_TSC_EXT_EVENT_IND 4
+#define USF_MAX_EVENT_IND 5
/* Types of events, produced by the calculators */
#define USF_NO_EVENT 0
@@ -81,10 +82,12 @@
#define USF_TSC_PTR_EVENT (1 << USF_TSC_PTR_EVENT_IND)
#define USF_MOUSE_EVENT (1 << USF_MOUSE_EVENT_IND)
#define USF_KEYBOARD_EVENT (1 << USF_KEYBOARD_EVENT_IND)
+#define USF_TSC_EXT_EVENT (1 << USF_TSC_EXT_EVENT_IND)
#define USF_ALL_EVENTS (USF_TSC_EVENT |\
USF_TSC_PTR_EVENT |\
USF_MOUSE_EVENT |\
- USF_KEYBOARD_EVENT)
+ USF_KEYBOARD_EVENT |\
+ USF_TSC_EXT_EVENT)
/* min, max array dimension */
#define MIN_MAX_DIM 2
@@ -146,6 +149,8 @@
int tsc_y_tilt[MIN_MAX_DIM];
/* Touch screen pressure limits: min & max; for input module */
int tsc_pressure[MIN_MAX_DIM];
+ /* The requested side buttons bitmap */
+ uint16_t req_side_buttons_bitmap;
/* Bitmap of types of events (USF_X_EVENT), produced by calculator */
uint16_t event_types;
/* Input event source */
@@ -174,6 +179,8 @@
int inclinations[TILTS_DIM];
/* [0-1023] (10bits); 0 - pen up */
uint32_t pressure;
+/* Bitmap for side button state. 1 - down, 0 - up */
+ uint16_t side_buttons_state_bitmap;
};
/* Mouse buttons, supported by USF */
diff --git a/arch/arm/mach-msm/ipc_socket.c b/arch/arm/mach-msm/ipc_socket.c
index bdda546..5aa6c93 100644
--- a/arch/arm/mach-msm/ipc_socket.c
+++ b/arch/arm/mach-msm/ipc_socket.c
@@ -589,17 +589,24 @@
};
static const struct proto_ops msm_ipc_proto_ops = {
- .owner = THIS_MODULE,
.family = AF_MSM_IPC,
+ .owner = THIS_MODULE,
+ .release = msm_ipc_router_close,
.bind = msm_ipc_router_bind,
.connect = sock_no_connect,
+ .socketpair = sock_no_socketpair,
+ .accept = sock_no_accept,
+ .getname = sock_no_getname,
+ .poll = msm_ipc_router_poll,
+ .ioctl = msm_ipc_router_ioctl,
+ .listen = sock_no_listen,
+ .shutdown = sock_no_shutdown,
+ .setsockopt = sock_no_setsockopt,
+ .getsockopt = sock_no_getsockopt,
.sendmsg = msm_ipc_router_sendmsg,
.recvmsg = msm_ipc_router_recvmsg,
- .ioctl = msm_ipc_router_ioctl,
- .poll = msm_ipc_router_poll,
- .setsockopt = sock_no_setsockopt,
- .getsockopt = sock_no_getsockopt,
- .release = msm_ipc_router_close,
+ .mmap = sock_no_mmap,
+ .sendpage = sock_no_sendpage,
};
static struct proto msm_ipc_proto = {
diff --git a/arch/arm/mach-msm/lpm_levels.c b/arch/arm/mach-msm/lpm_levels.c
index 249a334..b9dcf88 100644
--- a/arch/arm/mach-msm/lpm_levels.c
+++ b/arch/arm/mach-msm/lpm_levels.c
@@ -19,73 +19,115 @@
#include <linux/mutex.h>
#include <linux/cpu.h>
#include <linux/of.h>
+#include <linux/hrtimer.h>
+#include <linux/ktime.h>
+#include <linux/tick.h>
+#include <linux/suspend.h>
+#include <linux/pm_qos.h>
+#include <linux/of_platform.h>
#include <mach/mpm.h>
+#include <mach/cpuidle.h>
+#include <mach/event_timer.h>
#include "pm.h"
#include "rpm-notifier.h"
#include "spm.h"
#include "idle.h"
+#define SCLK_HZ (32768)
+
enum {
MSM_LPM_LVL_DBG_SUSPEND_LIMITS = BIT(0),
MSM_LPM_LVL_DBG_IDLE_LIMITS = BIT(1),
};
-enum {
- MSM_SCM_L2_ON = 0,
- MSM_SCM_L2_OFF = 1,
- MSM_SCM_L2_GDHS = 3,
-};
-
-struct msm_rpmrs_level {
- enum msm_pm_sleep_mode sleep_mode;
- uint32_t l2_cache;
- bool available;
+struct power_params {
uint32_t latency_us;
- uint32_t steady_state_power;
+ uint32_t ss_power;
uint32_t energy_overhead;
uint32_t time_overhead_us;
+ uint32_t target_residency_us;
};
+struct lpm_cpu_level {
+ const char *name;
+ enum msm_pm_sleep_mode mode;
+ struct power_params pwr;
+ bool use_bc_timer;
+ bool sync;
+};
+
+struct lpm_system_level {
+ const char *name;
+ uint32_t l2_mode;
+ struct power_params pwr;
+ enum msm_pm_sleep_mode min_cpu_mode;
+ int num_cpu_votes;
+ bool notify_rpm;
+ bool available;
+ bool sync;
+};
+
+struct lpm_system_state {
+ struct lpm_cpu_level *cpu_level;
+ int num_cpu_levels;
+ struct lpm_system_level *system_level;
+ int num_system_levels;
+ enum msm_pm_sleep_mode sync_cpu_mode;
+ int last_entered_cluster_index;
+ bool allow_synched_levels;
+ bool no_l2_saw;
+ struct spinlock sync_lock;
+ int num_cores_in_sync;
+};
+
+static struct lpm_system_state sys_state;
+static bool suspend_in_progress;
+
struct lpm_lookup_table {
uint32_t modes;
const char *mode_name;
};
-static void msm_lpm_level_update(void);
-
-static int msm_lpm_cpu_callback(struct notifier_block *cpu_nb,
+static void lpm_system_level_update(void);
+static void setup_broadcast_timer(void *arg);
+static int lpm_cpu_callback(struct notifier_block *cpu_nb,
unsigned long action, void *hcpu);
-static struct notifier_block __refdata msm_lpm_cpu_nblk = {
- .notifier_call = msm_lpm_cpu_callback,
+static struct notifier_block __refdata lpm_cpu_nblk = {
+ .notifier_call = lpm_cpu_callback,
};
static uint32_t allowed_l2_mode;
static uint32_t sysfs_dbg_l2_mode = MSM_SPM_L2_MODE_POWER_COLLAPSE;
static uint32_t default_l2_mode;
-static bool no_l2_saw;
-static ssize_t msm_lpm_levels_attr_show(
+static ssize_t lpm_levels_attr_show(
struct kobject *kobj, struct kobj_attribute *attr, char *buf);
-static ssize_t msm_lpm_levels_attr_store(struct kobject *kobj,
+static ssize_t lpm_levels_attr_store(struct kobject *kobj,
struct kobj_attribute *attr, const char *buf, size_t count);
-#define ADJUST_LATENCY(x) \
- ((x == MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE) ?\
- (num_online_cpus()) / 2 : 0)
-static int msm_lpm_lvl_dbg_msk;
+static int lpm_lvl_dbg_msk;
module_param_named(
- debug_mask, msm_lpm_lvl_dbg_msk, int, S_IRUGO | S_IWUSR | S_IWGRP
+ debug_mask, lpm_lvl_dbg_msk, int, S_IRUGO | S_IWUSR | S_IWGRP
);
-static struct msm_rpmrs_level *msm_lpm_levels;
-static int msm_lpm_level_count;
+static bool menu_select;
+module_param_named(
+ menu_select, menu_select, bool, S_IRUGO | S_IWUSR | S_IWGRP
+);
+
+static int msm_pm_sleep_time_override;
+module_param_named(sleep_time_override,
+ msm_pm_sleep_time_override, int, S_IRUGO | S_IWUSR | S_IWGRP);
+
+static int num_powered_cores;
+static struct hrtimer lpm_hrtimer;
static struct kobj_attribute lpm_l2_kattr = __ATTR(l2, S_IRUGO|S_IWUSR,\
- msm_lpm_levels_attr_show, msm_lpm_levels_attr_store);
+ lpm_levels_attr_show, lpm_levels_attr_store);
static struct attribute *lpm_levels_attr[] = {
&lpm_l2_kattr.attr,
@@ -97,7 +139,7 @@
};
/* SYSFS */
-static ssize_t msm_lpm_levels_attr_show(
+static ssize_t lpm_levels_attr_show(
struct kobject *kobj, struct kobj_attribute *attr, char *buf)
{
struct kernel_param kp;
@@ -115,7 +157,7 @@
return rc;
}
-static ssize_t msm_lpm_levels_attr_store(struct kobject *kobj,
+static ssize_t lpm_levels_attr_store(struct kobject *kobj,
struct kobj_attribute *attr, const char *buf, size_t count)
{
struct kernel_param kp;
@@ -128,64 +170,49 @@
return rc;
sysfs_dbg_l2_mode = temp;
- msm_lpm_level_update();
+ lpm_system_level_update();
return count;
}
-static int msm_pm_get_sleep_mode_value(struct device_node *node,
- const char *key, uint32_t *sleep_mode_val)
+static int msm_pm_get_sleep_mode_value(const char *mode_name)
{
- int i;
- struct lpm_lookup_table {
- uint32_t modes;
- const char *mode_name;
- };
struct lpm_lookup_table pm_sm_lookup[] = {
{MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
"wfi"},
- {MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT,
- "ramp_down_and_wfi"},
{MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
"standalone_pc"},
{MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
"pc"},
{MSM_PM_SLEEP_MODE_RETENTION,
"retention"},
- {MSM_PM_SLEEP_MODE_POWER_COLLAPSE_SUSPEND,
- "pc_suspend"},
- {MSM_PM_SLEEP_MODE_POWER_COLLAPSE_NO_XO_SHUTDOWN,
- "pc_no_xo_shutdown"}
};
- int ret;
- const char *mode_name;
+ int i;
+ int ret = -EINVAL;
- ret = of_property_read_string(node, key, &mode_name);
- if (!ret) {
- ret = -EINVAL;
- for (i = 0; i < ARRAY_SIZE(pm_sm_lookup); i++) {
- if (!strcmp(mode_name, pm_sm_lookup[i].mode_name)) {
- *sleep_mode_val = pm_sm_lookup[i].modes;
- ret = 0;
- break;
- }
+ for (i = 0; i < ARRAY_SIZE(pm_sm_lookup); i++) {
+ if (!strcmp(mode_name, pm_sm_lookup[i].mode_name)) {
+ ret = pm_sm_lookup[i].modes;
+ break;
}
}
return ret;
}
-static int msm_lpm_set_l2_mode(int sleep_mode)
+static int lpm_set_l2_mode(struct lpm_system_state *system_state,
+ int sleep_mode)
{
int lpm = sleep_mode;
int rc = 0;
- if (no_l2_saw)
+ if (system_state->no_l2_saw)
goto bail_set_l2_mode;
msm_pm_set_l2_flush_flag(MSM_SCM_L2_ON);
switch (sleep_mode) {
case MSM_SPM_L2_MODE_POWER_COLLAPSE:
+ pr_info("Configuring for L2 power collapse\n");
msm_pm_set_l2_flush_flag(MSM_SCM_L2_OFF);
break;
case MSM_SPM_L2_MODE_GDHS:
@@ -209,244 +236,341 @@
WARN_ON_ONCE(1);
else
pr_err("%s: Failed to set L2 low power mode %d, ERR %d",
- __func__, lpm, rc);
+ __func__, lpm, rc);
}
-
bail_set_l2_mode:
return rc;
}
-static void msm_lpm_level_update(void)
+static void lpm_system_level_update(void)
{
- int lpm_level;
- struct msm_rpmrs_level *level = NULL;
+ int i;
+ struct lpm_system_level *l = NULL;
uint32_t max_l2_mode;
static DEFINE_MUTEX(lpm_lock);
mutex_lock(&lpm_lock);
+ if (num_powered_cores == 1)
+ allowed_l2_mode = MSM_SPM_L2_MODE_POWER_COLLAPSE;
+ else if (sys_state.allow_synched_levels)
+ allowed_l2_mode = MSM_SPM_L2_MODE_POWER_COLLAPSE;
+ else
+ allowed_l2_mode = default_l2_mode;
max_l2_mode = min(allowed_l2_mode, sysfs_dbg_l2_mode);
- for (lpm_level = 0; lpm_level < msm_lpm_level_count; lpm_level++) {
- level = &msm_lpm_levels[lpm_level];
- level->available = !(level->l2_cache > max_l2_mode);
+ for (i = 0; i < sys_state.num_system_levels; i++) {
+ l = &sys_state.system_level[i];
+ l->available = !(l->l2_mode > max_l2_mode);
}
mutex_unlock(&lpm_lock);
}
-int msm_lpm_enter_sleep(uint32_t sclk_count, void *limits,
- bool from_idle, bool notify_rpm)
+static int lpm_system_mode_select(
+ struct lpm_system_state *system_state,
+ uint32_t sleep_us, bool from_idle)
{
- int ret = 0;
- int debug_mask;
- uint32_t l2 = *(uint32_t *)limits;
+ int best_level = -1;
+ int i;
+ uint32_t best_level_pwr = ~0UL;
+ uint32_t pwr;
+ uint32_t latency_us = pm_qos_request(PM_QOS_CPU_DMA_LATENCY);
- if (from_idle)
- debug_mask = msm_lpm_lvl_dbg_msk &
- MSM_LPM_LVL_DBG_IDLE_LIMITS;
- else
- debug_mask = msm_lpm_lvl_dbg_msk &
- MSM_LPM_LVL_DBG_SUSPEND_LIMITS;
+ if (!system_state->system_level)
+ return -EINVAL;
- if (debug_mask)
- pr_info("%s(): l2:%d", __func__, l2);
+ for (i = 0; i < system_state->num_system_levels; i++) {
+ struct lpm_system_level *system_level =
+ &system_state->system_level[i];
+ struct power_params *pwr_param = &system_level->pwr;
- ret = msm_lpm_set_l2_mode(l2);
+ if (!system_level->available)
+ continue;
- if (ret) {
- if (ret == -ENXIO)
- ret = 0;
- else {
- pr_warn("%s(): Failed to set L2 SPM Mode %d",
- __func__, l2);
- goto bail;
+ if (system_level->sync &&
+ system_level->num_cpu_votes != num_powered_cores)
+ continue;
+
+ if (latency_us < pwr_param->latency_us && from_idle)
+ continue;
+
+ if (sleep_us < pwr_param->time_overhead_us)
+ continue;
+
+ /*
+ * After the suspend prepare notifications its possible
+ * for the CPU to enter a system sleep mode. But MPM would have
+ * already requested a XO clock based on the wakeup irqs. To
+ * prevent suspend votes from being overriden by idle irqs, MPM
+ * doesn't send an updated MPM vote after suspend_prepare
+ * callback.
+ * To ensure that XO sleep vote isn't used if and when the
+ * device enters idle PC after suspend prepare callback,
+ * disallow any low power modes that notifies RPM after suspend
+ * prepare function is called
+ */
+ if (suspend_in_progress && system_level->notify_rpm &&
+ from_idle)
+ continue;
+
+ if ((sleep_us >> 10) > pwr_param->time_overhead_us) {
+ pwr = pwr_param->ss_power;
+ } else {
+ pwr = pwr_param->ss_power;
+ pwr -= (pwr_param->time_overhead_us
+ * pwr_param->ss_power) / sleep_us;
+ pwr += pwr_param->energy_overhead / sleep_us;
+ }
+
+ if (best_level_pwr >= pwr) {
+ best_level = i;
+ best_level_pwr = pwr;
}
}
+ return best_level;
+}
- if (notify_rpm) {
- ret = msm_rpm_enter_sleep(debug_mask);
+static void lpm_system_prepare(struct lpm_system_state *system_state,
+ int index, bool from_idle)
+{
+ struct lpm_system_level *lvl;
+ struct clock_event_device *bc = tick_get_broadcast_device()->evtdev;
+ uint32_t sclk;
+ int64_t us = (~0ULL);
+ int dbg_mask;
+ int ret;
+ const struct cpumask *nextcpu;
+
+ spin_lock(&system_state->sync_lock);
+ if (num_powered_cores != system_state->num_cores_in_sync) {
+ spin_unlock(&system_state->sync_lock);
+ return;
+ }
+
+ if (from_idle) {
+ dbg_mask = lpm_lvl_dbg_msk & MSM_LPM_LVL_DBG_IDLE_LIMITS;
+ us = ktime_to_us(ktime_sub(bc->next_event, ktime_get()));
+ nextcpu = bc->cpumask;
+ } else {
+ dbg_mask = lpm_lvl_dbg_msk & MSM_LPM_LVL_DBG_SUSPEND_LIMITS;
+ nextcpu = cpumask_of(smp_processor_id());
+ }
+
+ lvl = &system_state->system_level[index];
+
+ ret = lpm_set_l2_mode(system_state, lvl->l2_mode);
+
+ if (ret && ret != -ENXIO) {
+ pr_warn("%s(): Cannot set L2 Mode %d, ret:%d\n",
+ __func__, lvl->l2_mode, ret);
+ goto bail_system_sleep;
+ }
+
+ if (lvl->notify_rpm) {
+ ret = msm_rpm_enter_sleep(dbg_mask, nextcpu);
if (ret) {
- pr_warn("%s(): RPM failed to enter sleep err:%d\n",
- __func__, ret);
- goto bail;
+ pr_err("rpm_enter_sleep() failed with rc = %d\n", ret);
+ goto bail_system_sleep;
}
- msm_mpm_enter_sleep(sclk_count, from_idle);
+
+ if (!from_idle)
+ us = USEC_PER_SEC * msm_pm_sleep_time_override;
+
+ do_div(us, USEC_PER_SEC/SCLK_HZ);
+ sclk = (uint32_t)us;
+ msm_mpm_enter_sleep(sclk, from_idle, nextcpu);
}
-bail:
- return ret;
-}
-
-static void msm_lpm_exit_sleep(void *limits, bool from_idle,
- bool notify_rpm, bool collapsed)
-{
-
- msm_lpm_set_l2_mode(default_l2_mode);
-
- if (notify_rpm) {
- msm_mpm_exit_sleep(from_idle);
- msm_rpm_exit_sleep();
- }
-}
-
-void msm_lpm_show_resources(void)
-{
- /* TODO */
+ system_state->last_entered_cluster_index = index;
+ spin_unlock(&system_state->sync_lock);
return;
+
+bail_system_sleep:
+ if (default_l2_mode != system_state->system_level[index].l2_mode)
+ lpm_set_l2_mode(system_state, default_l2_mode);
+ spin_unlock(&system_state->sync_lock);
+}
+
+static void lpm_system_unprepare(struct lpm_system_state *system_state,
+ int cpu_index, bool from_idle)
+{
+ int index, i;
+ struct lpm_cpu_level *cpu_level = &system_state->cpu_level[cpu_index];
+ bool first_core_up;
+
+ if (cpu_level->mode < system_state->sync_cpu_mode)
+ return;
+
+ spin_lock(&system_state->sync_lock);
+
+ first_core_up = (system_state->num_cores_in_sync == num_powered_cores);
+
+ system_state->num_cores_in_sync--;
+
+ if (!system_state->system_level)
+ goto unlock_and_return;
+
+ index = system_state->last_entered_cluster_index;
+
+ for (i = 0; i < system_state->num_system_levels; i++) {
+ struct lpm_system_level *system_lvl
+ = &system_state->system_level[i];
+ if (cpu_level->mode >= system_lvl->min_cpu_mode)
+ system_lvl->num_cpu_votes--;
+ }
+
+ if (!first_core_up)
+ goto unlock_and_return;
+
+ if (default_l2_mode != system_state->system_level[index].l2_mode)
+ lpm_set_l2_mode(system_state, default_l2_mode);
+
+ if (system_state->system_level[index].notify_rpm) {
+ msm_rpm_exit_sleep();
+ msm_mpm_exit_sleep(from_idle);
+ }
+unlock_and_return:
+ spin_unlock(&system_state->sync_lock);
}
s32 msm_cpuidle_get_deep_idle_latency(void)
{
int i;
- struct msm_rpmrs_level *level = msm_lpm_levels, *best = level;
+ struct lpm_cpu_level *level = sys_state.cpu_level;
if (!level)
return 0;
- for (i = 0; i < msm_lpm_level_count; i++, level++) {
- if (!level->available)
- continue;
- if (level->sleep_mode != MSM_PM_SLEEP_MODE_POWER_COLLAPSE)
- continue;
- /* Pick the first power collapse mode by default */
- if (best->sleep_mode != MSM_PM_SLEEP_MODE_POWER_COLLAPSE)
- best = level;
- /* Find the lowest latency for power collapse */
- if (level->latency_us < best->latency_us)
- best = level;
+ for (i = 0; i < sys_state.num_cpu_levels; i++, level++) {
+ if (level->mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE)
+ break;
}
- return best->latency_us - 1;
+
+ if (i == sys_state.num_cpu_levels)
+ return 0;
+ else
+ return level->pwr.latency_us;
}
-static int msm_lpm_cpu_callback(struct notifier_block *cpu_nb,
+static int lpm_cpu_callback(struct notifier_block *cpu_nb,
unsigned long action, void *hcpu)
{
- switch (action) {
+ switch (action & ~CPU_TASKS_FROZEN) {
case CPU_UP_PREPARE:
- case CPU_UP_PREPARE_FROZEN:
- allowed_l2_mode = default_l2_mode;
- msm_lpm_level_update();
+ ++num_powered_cores;
+ lpm_system_level_update();
break;
- case CPU_DEAD_FROZEN:
case CPU_DEAD:
case CPU_UP_CANCELED:
- case CPU_UP_CANCELED_FROZEN:
- if (num_online_cpus() == 1)
- allowed_l2_mode = MSM_SPM_L2_MODE_POWER_COLLAPSE;
- msm_lpm_level_update();
+ num_powered_cores = num_online_cpus();
+ lpm_system_level_update();
+ break;
+ case CPU_ONLINE:
+ smp_call_function_single((unsigned long)hcpu,
+ setup_broadcast_timer, (void *)true, 1);
+ break;
+ default:
break;
}
return NOTIFY_OK;
}
-static void *msm_lpm_lowest_limits(bool from_idle,
- enum msm_pm_sleep_mode sleep_mode,
- struct msm_pm_time_params *time_param, uint32_t *power)
+static enum hrtimer_restart lpm_hrtimer_cb(struct hrtimer *h)
{
- unsigned int cpu = smp_processor_id();
- struct msm_rpmrs_level *best_level = NULL;
- uint32_t best_level_pwr = 0;
- uint32_t pwr;
+ return HRTIMER_NORESTART;
+}
+
+static void msm_pm_set_timer(uint32_t modified_time_us)
+{
+ u64 modified_time_ns = modified_time_us * NSEC_PER_USEC;
+ ktime_t modified_ktime = ns_to_ktime(modified_time_ns);
+ lpm_hrtimer.function = lpm_hrtimer_cb;
+ hrtimer_start(&lpm_hrtimer, modified_ktime, HRTIMER_MODE_REL_PINNED);
+}
+
+static noinline int lpm_cpu_power_select(struct cpuidle_device *dev, int *index)
+{
+ int best_level = -1;
+ uint32_t best_level_pwr = ~0UL;
+ uint32_t latency_us = pm_qos_request(PM_QOS_CPU_DMA_LATENCY);
+ uint32_t sleep_us =
+ (uint32_t)(ktime_to_us(tick_nohz_get_sleep_length()));
+ uint32_t modified_time_us = 0;
+ uint32_t next_event_us = 0;
+ uint32_t power;
int i;
- bool modify_event_timer;
- uint32_t next_wakeup_us = time_param->sleep_us;
- uint32_t lvl_latency_us = 0;
- uint32_t lvl_overhead_us = 0;
- uint32_t lvl_overhead_energy = 0;
- if (!msm_lpm_levels)
- return NULL;
+ if (!sys_state.cpu_level)
+ return -EINVAL;
- for (i = 0; i < msm_lpm_level_count; i++) {
- struct msm_rpmrs_level *level = &msm_lpm_levels[i];
+ if (!dev->cpu)
+ next_event_us = (uint32_t)(ktime_to_us(get_next_event_time()));
- modify_event_timer = false;
+ for (i = 0; i < sys_state.num_cpu_levels; i++) {
+ struct lpm_cpu_level *level = &sys_state.cpu_level[i];
+ struct power_params *pwr = &level->pwr;
+ uint32_t next_wakeup_us = sleep_us;
+ enum msm_pm_sleep_mode mode = level->mode;
+ bool allow;
- if (!level->available)
+ if (level->sync && num_online_cpus() > 1
+ && !sys_state.allow_synched_levels)
continue;
- if (sleep_mode != level->sleep_mode)
+ allow = msm_cpu_pm_check_mode(dev->cpu, mode, true);
+
+ if (!allow)
continue;
- lvl_latency_us =
- level->latency_us + (level->latency_us *
- ADJUST_LATENCY(sleep_mode));
-
- lvl_overhead_us =
- level->time_overhead_us + (level->time_overhead_us *
- ADJUST_LATENCY(sleep_mode));
-
- lvl_overhead_energy =
- level->energy_overhead + level->energy_overhead *
- ADJUST_LATENCY(sleep_mode);
-
- if (time_param->latency_us < lvl_latency_us)
+ if (latency_us < pwr->latency_us)
continue;
- if (time_param->next_event_us &&
- time_param->next_event_us < lvl_latency_us)
- continue;
+ if (next_event_us)
+ if (next_event_us < pwr->latency_us)
+ continue;
- if (time_param->next_event_us) {
- if ((time_param->next_event_us < time_param->sleep_us)
- || ((time_param->next_event_us - lvl_latency_us) <
- time_param->sleep_us)) {
- modify_event_timer = true;
- next_wakeup_us = time_param->next_event_us -
- lvl_latency_us;
+ if (((next_event_us - pwr->latency_us) < sleep_us)
+ || (next_event_us < sleep_us)) {
+ next_wakeup_us = next_event_us
+ - pwr->latency_us;
}
- }
- if (next_wakeup_us <= lvl_overhead_us)
+ if (next_wakeup_us <= pwr->time_overhead_us)
continue;
- if ((MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE == sleep_mode)
- || (MSM_PM_SLEEP_MODE_POWER_COLLAPSE == sleep_mode))
- if (!cpu && msm_rpm_waiting_for_ack())
+ if ((MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE == mode)
+ || (MSM_PM_SLEEP_MODE_POWER_COLLAPSE == mode))
+ if (!dev->cpu && msm_rpm_waiting_for_ack())
break;
- if (next_wakeup_us <= 1) {
- pwr = lvl_overhead_energy;
- } else if (next_wakeup_us <= lvl_overhead_us) {
- pwr = lvl_overhead_energy / next_wakeup_us;
- } else if ((next_wakeup_us >> 10)
- > lvl_overhead_us) {
- pwr = level->steady_state_power;
+ if ((next_wakeup_us >> 10) > pwr->latency_us) {
+ power = pwr->ss_power;
} else {
- pwr = level->steady_state_power;
- pwr -= (lvl_overhead_us *
- level->steady_state_power) /
- next_wakeup_us;
- pwr += lvl_overhead_energy / next_wakeup_us;
+ power = pwr->ss_power;
+ power -= (pwr->latency_us * pwr->ss_power)
+ / next_wakeup_us;
+ power += pwr->energy_overhead / next_wakeup_us;
}
- if (!best_level || (best_level_pwr >= pwr)) {
- best_level = level;
- best_level_pwr = pwr;
- if (power)
- *power = pwr;
- if (modify_event_timer &&
- (sleep_mode !=
- MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT))
- time_param->modified_time_us =
- time_param->next_event_us -
- lvl_latency_us;
+ if (best_level_pwr >= power) {
+ best_level = i;
+ best_level_pwr = power;
+ if (next_event_us < sleep_us &&
+ (mode != MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT))
+ modified_time_us = next_event_us
+ - pwr->latency_us;
else
- time_param->modified_time_us = 0;
+ modified_time_us = 0;
}
}
- return best_level ? &best_level->l2_cache : NULL;
+ if (modified_time_us && !dev->cpu)
+ msm_pm_set_timer(modified_time_us);
+
+ return best_level;
}
-static struct msm_pm_sleep_ops msm_lpm_ops = {
- .lowest_limits = msm_lpm_lowest_limits,
- .enter_sleep = msm_lpm_enter_sleep,
- .exit_sleep = msm_lpm_exit_sleep,
-};
-
-static int msm_lpm_get_l2_cache_value(struct device_node *node,
- char *key, uint32_t *l2_val)
+static int lpm_get_l2_cache_value(const char *l2_str)
{
int i;
struct lpm_lookup_table l2_mode_lookup[] = {
@@ -456,24 +580,14 @@
{MSM_SPM_L2_MODE_RETENTION, "l2_cache_retention"},
{MSM_SPM_L2_MODE_DISABLED, "l2_cache_active"}
};
- const char *l2_str;
- int ret;
- ret = of_property_read_string(node, key, &l2_str);
- if (!ret) {
- ret = -EINVAL;
- for (i = 0; i < ARRAY_SIZE(l2_mode_lookup); i++) {
- if (!strcmp(l2_str, l2_mode_lookup[i].mode_name)) {
- *l2_val = l2_mode_lookup[i].modes;
- ret = 0;
- break;
- }
- }
- }
- return ret;
+ for (i = 0; i < ARRAY_SIZE(l2_mode_lookup); i++)
+ if (!strcmp(l2_str, l2_mode_lookup[i].mode_name))
+ return l2_mode_lookup[i].modes;
+ return -EINVAL;
}
-static int __devinit msm_lpm_levels_sysfs_add(void)
+static int lpm_levels_sysfs_add(void)
{
struct kobject *module_kobj = NULL;
struct kobject *low_power_kobj = NULL;
@@ -500,126 +614,548 @@
if (rc) {
if (low_power_kobj) {
sysfs_remove_group(low_power_kobj,
- &lpm_levels_attr_grp);
+ &lpm_levels_attr_grp);
kobject_del(low_power_kobj);
}
}
return rc;
}
-
-static int __devinit msm_lpm_levels_probe(struct platform_device *pdev)
+static int lpm_cpu_menu_select(struct cpuidle_device *dev, int *index)
{
- struct msm_rpmrs_level *levels = NULL;
- struct msm_rpmrs_level *level = NULL;
+ int j;
+
+ for (; *index >= 0; (*index)--) {
+ int mode = 0;
+ bool allow = false;
+
+ allow = msm_cpu_pm_check_mode(dev->cpu, mode, true);
+
+ if (!allow)
+ continue;
+
+ for (j = sys_state.num_cpu_levels; j >= 0; j--) {
+ struct lpm_cpu_level *l = &sys_state.cpu_level[j];
+ if (mode == l->mode)
+ return j;
+ }
+ }
+ return -EPERM;
+}
+
+static inline void lpm_cpu_prepare(struct lpm_system_state *system_state,
+ int cpu_index, bool from_idle)
+{
+ struct lpm_cpu_level *cpu_level = &system_state->cpu_level[cpu_index];
+ unsigned int cpu = smp_processor_id();
+
+ /* Use broadcast timer for aggregating sleep mode within a cluster.
+ * A broadcast timer could be used because of harware restriction or
+ * to ensure that we BC timer is used incase a cpu mode could trigger
+ * a cluster level sleep
+ */
+ if (from_idle && (cpu_level->use_bc_timer ||
+ (cpu_level->mode >= system_state->sync_cpu_mode)))
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
+}
+
+static inline void lpm_cpu_unprepare(struct lpm_system_state *system_state,
+ int cpu_index, bool from_idle)
+{
+ struct lpm_cpu_level *cpu_level = &system_state->cpu_level[cpu_index];
+ unsigned int cpu = smp_processor_id();
+
+ if (from_idle && (cpu_level->use_bc_timer ||
+ (cpu_level->mode >= system_state->sync_cpu_mode)))
+ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
+}
+
+static int lpm_system_select(struct lpm_system_state *system_state,
+ int cpu_index, bool from_idle)
+{
+ uint64_t us = (~0ULL);
+ struct clock_event_device *ed;
+ struct lpm_cpu_level *cpu_level = &system_state->cpu_level[cpu_index];
+ int i;
+ bool last_core_down;
+
+ if (cpu_level->mode < system_state->sync_cpu_mode)
+ return -EINVAL;
+
+ spin_lock(&system_state->sync_lock);
+
+ last_core_down =
+ (++system_state->num_cores_in_sync == num_powered_cores);
+
+ if (!system_state->system_level) {
+ spin_unlock(&system_state->sync_lock);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < system_state->num_system_levels; i++) {
+ struct lpm_system_level *system_lvl =
+ &system_state->system_level[i];
+ if (cpu_level->mode >= system_lvl->min_cpu_mode)
+ system_lvl->num_cpu_votes++;
+ }
+ spin_unlock(&system_state->sync_lock);
+
+ if (!last_core_down)
+ return -EBUSY;
+
+ ed = tick_get_broadcast_device()->evtdev;
+ if (!ed)
+ return -EINVAL;
+
+ if (from_idle)
+ us = ktime_to_us(ktime_sub(ed->next_event, ktime_get()));
+ else
+ us = (~0ULL);
+
+ return lpm_system_mode_select(system_state, (uint32_t)(us), from_idle);
+}
+
+static void lpm_enter_low_power(struct lpm_system_state *system_state,
+ int cpu_index, bool from_idle)
+{
+ int idx;
+ struct lpm_cpu_level *cpu_level = &system_state->cpu_level[cpu_index];
+
+ cpu_level = &system_state->cpu_level[cpu_index];
+
+ lpm_cpu_prepare(system_state, cpu_index, from_idle);
+
+ idx = lpm_system_select(system_state, cpu_index, from_idle);
+
+ if (idx >= 0)
+ lpm_system_prepare(system_state, idx, from_idle);
+
+ msm_cpu_pm_enter_sleep(cpu_level->mode, from_idle);
+
+ lpm_system_unprepare(system_state, cpu_index, from_idle);
+
+ lpm_cpu_unprepare(system_state, cpu_index, from_idle);
+}
+
+static int lpm_cpuidle_enter(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ int64_t time = ktime_to_ns(ktime_get());
+ int idx;
+
+ idx = menu_select ? lpm_cpu_menu_select(dev, &index) :
+ lpm_cpu_power_select(dev, &index);
+ if (idx < 0) {
+ local_irq_enable();
+ return -EPERM;
+ }
+
+ lpm_enter_low_power(&sys_state, idx, true);
+
+ time = ktime_to_ns(ktime_get()) - time;
+ do_div(time, 1000);
+ dev->last_residency = (int)time;
+ local_irq_enable();
+ return index;
+}
+
+static int lpm_suspend_enter(suspend_state_t state)
+{
+ int i;
+
+ for (i = sys_state.num_cpu_levels - 1; i >= 0; i--) {
+ bool allow = msm_cpu_pm_check_mode(smp_processor_id(),
+ sys_state.cpu_level[i].mode, false);
+ if (allow)
+ break;
+ }
+
+ if (i < 0)
+ return -EINVAL;
+
+ lpm_enter_low_power(&sys_state, i, false);
+
+ return 0;
+}
+
+static int lpm_suspend_prepare(void)
+{
+ suspend_in_progress = true;
+ msm_mpm_suspend_prepare();
+ return 0;
+}
+
+static void lpm_suspend_wake(void)
+{
+ msm_mpm_suspend_wake();
+ suspend_in_progress = false;
+}
+
+static struct platform_device lpm_dev = {
+ .name = "msm_pm",
+ .id = -1,
+};
+
+static const struct platform_suspend_ops lpm_suspend_ops = {
+ .enter = lpm_suspend_enter,
+ .valid = suspend_valid_only_mem,
+ .prepare_late = lpm_suspend_prepare,
+ .wake = lpm_suspend_wake,
+};
+
+static void setup_broadcast_timer(void *arg)
+{
+ unsigned long reason = (unsigned long)arg;
+ int cpu = smp_processor_id();
+
+ reason = reason ?
+ CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
+
+ clockevents_notify(reason, &cpu);
+}
+
+static struct cpuidle_driver msm_cpuidle_driver = {
+ .name = "msm_idle",
+ .owner = THIS_MODULE,
+};
+
+static void lpm_cpuidle_init(void)
+{
+ int i = 0;
+ int state_count = 0;
+
+ if (!sys_state.cpu_level)
+ return;
+ BUG_ON(sys_state.num_cpu_levels > CPUIDLE_STATE_MAX);
+
+ for (i = 0; i < sys_state.num_cpu_levels; i++) {
+ struct cpuidle_state *st = &msm_cpuidle_driver.states[i];
+ struct lpm_cpu_level *cpu_level = &sys_state.cpu_level[i];
+ snprintf(st->name, CPUIDLE_NAME_LEN, "C%u\n", i);
+ snprintf(st->desc, CPUIDLE_DESC_LEN, cpu_level->name);
+ st->flags = 0;
+ st->exit_latency = cpu_level->pwr.latency_us;
+ st->power_usage = cpu_level->pwr.ss_power;
+ st->target_residency = 0;
+ st->enter = lpm_cpuidle_enter;
+ state_count++;
+ }
+ msm_cpuidle_driver.state_count = state_count;
+ msm_cpuidle_driver.safe_state_index = 0;
+
+ if (cpuidle_register(&msm_cpuidle_driver, NULL))
+ pr_err("%s(): Failed to register CPUIDLE device\n", __func__);
+}
+
+static int lpm_parse_power_params(struct device_node *node,
+ struct power_params *pwr)
+{
+ char *key;
+ int ret;
+
+ key = "qcom,latency-us";
+ ret = of_property_read_u32(node, key, &pwr->latency_us);
+ if (ret)
+ goto fail;
+
+ key = "qcom,ss-power";
+ ret = of_property_read_u32(node, key, &pwr->ss_power);
+ if (ret)
+ goto fail;
+
+ key = "qcom,energy-overhead";
+ ret = of_property_read_u32(node, key, &pwr->energy_overhead);
+ if (ret)
+ goto fail;
+
+ key = "qcom,time-overhead";
+ ret = of_property_read_u32(node, key, &pwr->time_overhead_us);
+ if (ret)
+ goto fail;
+fail:
+ if (ret)
+ pr_err("%s(): Error reading %s\n", __func__, key);
+ return ret;
+}
+
+static int lpm_cpu_probe(struct platform_device *pdev)
+{
+ struct lpm_cpu_level *level = NULL, *l;
struct device_node *node = NULL;
- char *key = NULL;
- uint32_t val = 0;
- int ret = 0;
- uint32_t num_levels = 0;
- int idx = 0;
+ int num_levels = 0;
+ char *key;
+ int ret;
for_each_child_of_node(pdev->dev.of_node, node)
num_levels++;
- levels = kzalloc(num_levels * sizeof(struct msm_rpmrs_level),
+ level = kzalloc(num_levels * sizeof(struct lpm_cpu_level),
GFP_KERNEL);
- if (!levels)
+
+ if (!level)
return -ENOMEM;
+ l = &level[0];
for_each_child_of_node(pdev->dev.of_node, node) {
- level = &levels[idx++];
- level->available = false;
key = "qcom,mode";
- ret = msm_pm_get_sleep_mode_value(node, key, &val);
- if (ret)
+ ret = of_property_read_string(node, key, &l->name);
+
+ if (ret) {
+ pr_err("%s(): Cannot read cpu mode%s\n", __func__, key);
goto fail;
- level->sleep_mode = val;
+ }
+
+ l->mode = msm_pm_get_sleep_mode_value(l->name);
+
+ if (l->mode < 0) {
+ pr_err("%s():Cannot parse cpu mode:%s\n", __func__,
+ l->name);
+ goto fail;
+ }
+
+ if (l->mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE)
+ l->sync = true;
+
+ key = "qcom,use-broadcast-timer";
+ l->use_bc_timer = of_property_read_bool(node, key);
+
+ ret = lpm_parse_power_params(node, &l->pwr);
+ if (ret) {
+ pr_err("%s(): cannot Parse power params\n", __func__);
+ goto fail;
+ }
+ l++;
+ }
+ sys_state.cpu_level = level;
+ sys_state.num_cpu_levels = num_levels;
+ return ret;
+fail:
+ kfree(level);
+ return ret;
+}
+
+static int lpm_system_probe(struct platform_device *pdev)
+{
+ struct lpm_system_level *level = NULL, *l;
+ int num_levels = 0;
+ struct device_node *node;
+ char *key;
+ int ret;
+
+ for_each_child_of_node(pdev->dev.of_node, node)
+ num_levels++;
+
+ level = kzalloc(num_levels * sizeof(struct lpm_system_level),
+ GFP_KERNEL);
+
+ if (!level)
+ return -ENOMEM;
+
+ l = &level[0];
+ for_each_child_of_node(pdev->dev.of_node, node) {
key = "qcom,l2";
- ret = msm_lpm_get_l2_cache_value(node, key, &val);
- if (ret)
+ ret = of_property_read_string(node, key, &l->name);
+ if (ret) {
+ pr_err("%s(): Failed to read L2 mode\n", __func__);
goto fail;
- level->l2_cache = val;
+ }
- key = "qcom,latency-us";
- ret = of_property_read_u32(node, key, &val);
- if (ret)
+ l->l2_mode = lpm_get_l2_cache_value(l->name);
+
+ if (l->l2_mode < 0) {
+ pr_err("%s(): Failed to read l2 cache mode\n",
+ __func__);
goto fail;
- level->latency_us = val;
+ }
- key = "qcom,ss-power";
- ret = of_property_read_u32(node, key, &val);
- if (ret)
+ if (l->l2_mode == MSM_SPM_L2_MODE_GDHS ||
+ l->l2_mode == MSM_SPM_L2_MODE_POWER_COLLAPSE)
+ l->notify_rpm = true;
+
+ if (l->l2_mode >= MSM_SPM_L2_MODE_GDHS)
+ l->sync = true;
+
+ ret = lpm_parse_power_params(node, &l->pwr);
+ if (ret) {
+ pr_err("%s(): Failed to parse power params\n",
+ __func__);
goto fail;
- level->steady_state_power = val;
+ }
- key = "qcom,energy-overhead";
- ret = of_property_read_u32(node, key, &val);
- if (ret)
- goto fail;
- level->energy_overhead = val;
+ key = "qcom,sync-cpus";
+ l->sync = of_property_read_bool(node, key);
- key = "qcom,time-overhead";
- ret = of_property_read_u32(node, key, &val);
- if (ret)
- goto fail;
- level->time_overhead_us = val;
+ if (l->sync) {
+ const char *name;
- level->available = true;
+ key = "qcom,min-cpu-mode";
+ ret = of_property_read_string(node, key, &name);
+ if (ret) {
+ pr_err("%s(): Required key %snot found\n",
+ __func__, name);
+ goto fail;
+ }
+
+ l->min_cpu_mode = msm_pm_get_sleep_mode_value(name);
+
+ if (l->min_cpu_mode < 0) {
+ pr_err("%s(): Cannot parse cpu mode:%s\n",
+ __func__, name);
+ goto fail;
+ }
+
+ if (l->min_cpu_mode < sys_state.sync_cpu_mode)
+ sys_state.sync_cpu_mode = l->min_cpu_mode;
+ }
+
+ l++;
}
+ sys_state.system_level = level;
+ sys_state.num_system_levels = num_levels;
+ return ret;
+fail:
+ kfree(level);
+ return ret;
+}
+
+static int lpm_probe(struct platform_device *pdev)
+{
+ struct device_node *node = NULL;
+ char *key = NULL;
+ int ret;
node = pdev->dev.of_node;
+
+ key = "qcom,allow-synced-levels";
+ sys_state.allow_synched_levels = of_property_read_bool(node, key);
+
key = "qcom,no-l2-saw";
- no_l2_saw = of_property_read_bool(node, key);
+ sys_state.no_l2_saw = of_property_read_bool(node, key);
- msm_lpm_levels = levels;
- msm_lpm_level_count = idx;
+ sys_state.sync_cpu_mode = MSM_PM_SLEEP_MODE_NR;
+ spin_lock_init(&sys_state.sync_lock);
+ sys_state.num_cores_in_sync = 0;
- if (num_online_cpus() == 1)
- allowed_l2_mode = MSM_SPM_L2_MODE_POWER_COLLAPSE;
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+
+ if (ret)
+ goto fail;
/* Do the following two steps only if L2 SAW is present */
- if (!no_l2_saw) {
- key = "qcom,default-l2-state";
- if (msm_lpm_get_l2_cache_value(node, key, &default_l2_mode))
- goto fail;
+ num_powered_cores = num_online_cpus();
- if (msm_lpm_levels_sysfs_add())
+ if (!sys_state.no_l2_saw) {
+ int ret;
+ const char *l2;
+ key = "qcom,default-l2-state";
+ ret = of_property_read_string(node, key, &l2);
+ if (ret) {
+ pr_err("%s(): Failed to read default L2 mode\n",
+ __func__);
goto fail;
- register_hotcpu_notifier(&msm_lpm_cpu_nblk);
- msm_pm_set_l2_flush_flag(0);
+ }
+
+ default_l2_mode = lpm_get_l2_cache_value(l2);
+ if (default_l2_mode < 0) {
+ pr_err("%s(): Unable to parse default L2 mode\n",
+ __func__);
+ goto fail;
+ }
+
+ if (lpm_levels_sysfs_add())
+ goto fail;
+ msm_pm_set_l2_flush_flag(MSM_SCM_L2_ON);
} else {
- msm_pm_set_l2_flush_flag(1);
+ msm_pm_set_l2_flush_flag(MSM_SCM_L2_OFF);
default_l2_mode = MSM_SPM_L2_MODE_POWER_COLLAPSE;
}
- msm_lpm_level_update();
- msm_pm_set_sleep_ops(&msm_lpm_ops);
+ get_cpu();
+ on_each_cpu(setup_broadcast_timer, (void *)true, 1);
+ put_cpu();
+
+ register_hotcpu_notifier(&lpm_cpu_nblk);
+
+ lpm_system_level_update();
+ platform_device_register(&lpm_dev);
+ suspend_set_ops(&lpm_suspend_ops);
+ hrtimer_init(&lpm_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ lpm_cpuidle_init();
return 0;
fail:
pr_err("%s: Error in name %s key %s\n", __func__, node->full_name, key);
- kfree(levels);
return -EFAULT;
}
-static struct of_device_id msm_lpm_levels_match_table[] = {
+static struct of_device_id cpu_modes_mtch_tbl[] = {
+ {.compatible = "qcom,cpu-modes"},
+ {},
+};
+
+static struct platform_driver cpu_modes_driver = {
+ .probe = lpm_cpu_probe,
+ .driver = {
+ .name = "cpu-modes",
+ .owner = THIS_MODULE,
+ .of_match_table = cpu_modes_mtch_tbl,
+ },
+};
+
+static struct of_device_id system_modes_mtch_tbl[] = {
+ {.compatible = "qcom,system-modes"},
+ {},
+};
+
+static struct platform_driver system_modes_driver = {
+ .probe = lpm_system_probe,
+ .driver = {
+ .name = "system-modes",
+ .owner = THIS_MODULE,
+ .of_match_table = system_modes_mtch_tbl,
+ },
+};
+
+static struct of_device_id lpm_levels_match_table[] = {
{.compatible = "qcom,lpm-levels"},
{},
};
-static struct platform_driver msm_lpm_levels_driver = {
- .probe = msm_lpm_levels_probe,
+static struct platform_driver lpm_levels_driver = {
+ .probe = lpm_probe,
.driver = {
.name = "lpm-levels",
.owner = THIS_MODULE,
- .of_match_table = msm_lpm_levels_match_table,
+ .of_match_table = lpm_levels_match_table,
},
};
-static int __init msm_lpm_levels_module_init(void)
+static int __init lpm_levels_module_init(void)
{
- return platform_driver_register(&msm_lpm_levels_driver);
+ int rc;
+ rc = platform_driver_register(&cpu_modes_driver);
+ if (rc) {
+ pr_err("Error registering %s\n", cpu_modes_driver.driver.name);
+ goto fail;
+ }
+
+ rc = platform_driver_register(&system_modes_driver);
+ if (rc) {
+ platform_driver_unregister(&cpu_modes_driver);
+ pr_err("Error registering %s\n",
+ system_modes_driver.driver.name);
+ goto fail;
+ }
+
+ rc = platform_driver_register(&lpm_levels_driver);
+ if (rc) {
+ platform_driver_unregister(&cpu_modes_driver);
+ platform_driver_unregister(&system_modes_driver);
+ pr_err("Error registering %s\n",
+ lpm_levels_driver.driver.name);
+ }
+fail:
+ return rc;
}
-late_initcall(msm_lpm_levels_module_init);
+late_initcall(lpm_levels_module_init);
diff --git a/arch/arm/mach-msm/mpm-of.c b/arch/arm/mach-msm/mpm-of.c
index e364393..5b351b4 100644
--- a/arch/arm/mach-msm/mpm-of.c
+++ b/arch/arm/mach-msm/mpm-of.c
@@ -505,7 +505,9 @@
return msm_mpm_interrupts_detectable(MSM_MPM_GIC_IRQ_DOMAIN,
from_idle);
}
-void msm_mpm_enter_sleep(uint32_t sclk_count, bool from_idle)
+
+void msm_mpm_enter_sleep(uint32_t sclk_count, bool from_idle,
+ const struct cpumask *cpumask)
{
cycle_t wakeup = (u64)sclk_count * ARCH_TIMER_HZ;
@@ -522,6 +524,7 @@
}
msm_mpm_set(wakeup, !from_idle);
+ irq_set_affinity(msm_mpm_dev_data.mpm_ipc_irq, cpumask);
}
void msm_mpm_exit_sleep(bool from_idle)
diff --git a/arch/arm/mach-msm/msm-pm.c b/arch/arm/mach-msm/msm-pm.c
new file mode 100644
index 0000000..fab86d3
--- /dev/null
+++ b/arch/arm/mach-msm/msm-pm.c
@@ -0,0 +1,1247 @@
+/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/ktime.h>
+#include <linux/smp.h>
+#include <linux/tick.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+#include <linux/cpu_pm.h>
+#include <asm/uaccess.h>
+#include <asm/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/outercache.h>
+#include <mach/scm.h>
+#include <mach/msm_bus.h>
+#include <mach/jtag.h>
+#include "acpuclock.h"
+#include "avs.h"
+#include "idle.h"
+#include "pm.h"
+#include "scm-boot.h"
+#include "spm.h"
+#include "pm-boot.h"
+
+#define CREATE_TRACE_POINTS
+#include <mach/trace_msm_low_power.h>
+
+#define SCM_CMD_TERMINATE_PC (0x2)
+#define SCM_CMD_CORE_HOTPLUGGED (0x10)
+
+#define GET_CPU_OF_ATTR(attr) \
+ (container_of(attr, struct msm_pm_kobj_attribute, ka)->cpu)
+
+#define SCLK_HZ (32768)
+
+#define MAX_BUF_SIZE 512
+
+static int msm_pm_debug_mask = 1;
+module_param_named(
+ debug_mask, msm_pm_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP
+);
+
+static bool use_acpuclk_apis;
+
+enum {
+ MSM_PM_DEBUG_SUSPEND = BIT(0),
+ MSM_PM_DEBUG_POWER_COLLAPSE = BIT(1),
+ MSM_PM_DEBUG_SUSPEND_LIMITS = BIT(2),
+ MSM_PM_DEBUG_CLOCK = BIT(3),
+ MSM_PM_DEBUG_RESET_VECTOR = BIT(4),
+ MSM_PM_DEBUG_IDLE_CLK = BIT(5),
+ MSM_PM_DEBUG_IDLE = BIT(6),
+ MSM_PM_DEBUG_IDLE_LIMITS = BIT(7),
+ MSM_PM_DEBUG_HOTPLUG = BIT(8),
+};
+
+enum msm_pc_count_offsets {
+ MSM_PC_ENTRY_COUNTER,
+ MSM_PC_EXIT_COUNTER,
+ MSM_PC_FALLTHRU_COUNTER,
+ MSM_PC_NUM_COUNTERS,
+};
+
+enum {
+ MSM_PM_MODE_ATTR_SUSPEND,
+ MSM_PM_MODE_ATTR_IDLE,
+ MSM_PM_MODE_ATTR_NR,
+};
+
+static char *msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_NR] = {
+ [MSM_PM_MODE_ATTR_SUSPEND] = "suspend_enabled",
+ [MSM_PM_MODE_ATTR_IDLE] = "idle_enabled",
+};
+
+struct msm_pm_kobj_attribute {
+ unsigned int cpu;
+ struct kobj_attribute ka;
+};
+
+struct msm_pm_sysfs_sleep_mode {
+ struct kobject *kobj;
+ struct attribute_group attr_group;
+ struct attribute *attrs[MSM_PM_MODE_ATTR_NR + 1];
+ struct msm_pm_kobj_attribute kas[MSM_PM_MODE_ATTR_NR];
+};
+
+static char *msm_pm_sleep_mode_labels[MSM_PM_SLEEP_MODE_NR] = {
+ [MSM_PM_SLEEP_MODE_POWER_COLLAPSE] = "power_collapse",
+ [MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT] = "wfi",
+ [MSM_PM_SLEEP_MODE_RETENTION] = "retention",
+ [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE] =
+ "standalone_power_collapse",
+};
+
+static bool msm_pm_ldo_retention_enabled = true;
+static bool msm_no_ramp_down_pc;
+static struct msm_pm_sleep_status_data *msm_pm_slp_sts;
+DEFINE_PER_CPU(struct clk *, cpu_clks);
+static struct clk *l2_clk;
+
+static void (*msm_pm_disable_l2_fn)(void);
+static void (*msm_pm_enable_l2_fn)(void);
+static void (*msm_pm_flush_l2_fn)(void);
+static void __iomem *msm_pc_debug_counters;
+
+/*
+ * Default the l2 flush flag to OFF so the caches are flushed during power
+ * collapse unless the explicitly voted by lpm driver.
+ */
+static enum msm_pm_l2_scm_flag msm_pm_flush_l2_flag = MSM_SCM_L2_OFF;
+
+void msm_pm_set_l2_flush_flag(enum msm_pm_l2_scm_flag flag)
+{
+ msm_pm_flush_l2_flag = flag;
+}
+EXPORT_SYMBOL(msm_pm_set_l2_flush_flag);
+
+static enum msm_pm_l2_scm_flag msm_pm_get_l2_flush_flag(void)
+{
+ return msm_pm_flush_l2_flag;
+}
+
+static cpumask_t retention_cpus;
+static DEFINE_SPINLOCK(retention_lock);
+
+static int msm_pm_get_pc_mode(struct device_node *node,
+ const char *key, uint32_t *pc_mode_val)
+{
+ struct pc_mode_of {
+ uint32_t mode;
+ char *mode_name;
+ };
+ int i;
+ struct pc_mode_of pc_modes[] = {
+ {MSM_PM_PC_TZ_L2_INT, "tz_l2_int"},
+ {MSM_PM_PC_NOTZ_L2_EXT, "no_tz_l2_ext"},
+ {MSM_PM_PC_TZ_L2_EXT , "tz_l2_ext"} };
+ int ret;
+ const char *pc_mode_str;
+ *pc_mode_val = MSM_PM_PC_TZ_L2_INT;
+
+ ret = of_property_read_string(node, key, &pc_mode_str);
+ if (!ret) {
+ ret = -EINVAL;
+ for (i = 0; i < ARRAY_SIZE(pc_modes); i++) {
+ if (!strncmp(pc_mode_str, pc_modes[i].mode_name,
+ strlen(pc_modes[i].mode_name))) {
+ *pc_mode_val = pc_modes[i].mode;
+ ret = 0;
+ break;
+ }
+ }
+ } else {
+ pr_debug("%s: Cannot read %s,defaulting to 0", __func__, key);
+ ret = 0;
+ }
+ return ret;
+}
+
+/*
+ * Write out the attribute.
+ */
+static ssize_t msm_pm_mode_attr_show(
+ struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+ int ret = -EINVAL;
+ int i;
+
+ for (i = 0; i < MSM_PM_SLEEP_MODE_NR; i++) {
+ struct kernel_param kp;
+ unsigned int cpu;
+ struct msm_pm_platform_data *mode;
+
+ if (msm_pm_sleep_mode_labels[i] == NULL)
+ continue;
+
+ if (strcmp(kobj->name, msm_pm_sleep_mode_labels[i]))
+ continue;
+
+ cpu = GET_CPU_OF_ATTR(attr);
+ mode = &msm_pm_sleep_modes[MSM_PM_MODE(cpu, i)];
+
+ if (!strcmp(attr->attr.name,
+ msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_SUSPEND])) {
+ u32 arg = mode->suspend_enabled;
+ kp.arg = &arg;
+ ret = param_get_ulong(buf, &kp);
+ } else if (!strcmp(attr->attr.name,
+ msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_IDLE])) {
+ u32 arg = mode->idle_enabled;
+ kp.arg = &arg;
+ ret = param_get_ulong(buf, &kp);
+ }
+
+ break;
+ }
+
+ if (ret > 0) {
+ strlcat(buf, "\n", PAGE_SIZE);
+ ret++;
+ }
+
+ return ret;
+}
+
+static ssize_t msm_pm_mode_attr_store(struct kobject *kobj,
+ struct kobj_attribute *attr, const char *buf, size_t count)
+{
+ int ret = -EINVAL;
+ int i;
+
+ for (i = 0; i < MSM_PM_SLEEP_MODE_NR; i++) {
+ struct kernel_param kp;
+ unsigned int cpu;
+ struct msm_pm_platform_data *mode;
+
+ if (msm_pm_sleep_mode_labels[i] == NULL)
+ continue;
+
+ if (strcmp(kobj->name, msm_pm_sleep_mode_labels[i]))
+ continue;
+
+ cpu = GET_CPU_OF_ATTR(attr);
+ mode = &msm_pm_sleep_modes[MSM_PM_MODE(cpu, i)];
+
+ if (!strcmp(attr->attr.name,
+ msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_SUSPEND])) {
+ kp.arg = &mode->suspend_enabled;
+ ret = param_set_byte(buf, &kp);
+ } else if (!strcmp(attr->attr.name,
+ msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_IDLE])) {
+ kp.arg = &mode->idle_enabled;
+ ret = param_set_byte(buf, &kp);
+ }
+
+ break;
+ }
+
+ return ret ? ret : count;
+}
+
+static int msm_pm_mode_sysfs_add_cpu(
+ unsigned int cpu, struct kobject *modes_kobj)
+{
+ char cpu_name[8];
+ struct kobject *cpu_kobj;
+ struct msm_pm_sysfs_sleep_mode *mode = NULL;
+ int i, j, k;
+ int ret;
+
+ snprintf(cpu_name, sizeof(cpu_name), "cpu%u", cpu);
+ cpu_kobj = kobject_create_and_add(cpu_name, modes_kobj);
+ if (!cpu_kobj) {
+ pr_err("%s: cannot create %s kobject\n", __func__, cpu_name);
+ ret = -ENOMEM;
+ goto mode_sysfs_add_cpu_exit;
+ }
+
+ for (i = 0; i < MSM_PM_SLEEP_MODE_NR; i++) {
+ int idx = MSM_PM_MODE(cpu, i);
+
+ if ((!msm_pm_sleep_modes[idx].suspend_supported)
+ && (!msm_pm_sleep_modes[idx].idle_supported))
+ continue;
+
+ if (!msm_pm_sleep_mode_labels[i] ||
+ !msm_pm_sleep_mode_labels[i][0])
+ continue;
+
+ mode = kzalloc(sizeof(*mode), GFP_KERNEL);
+ if (!mode) {
+ pr_err("%s: cannot allocate memory for attributes\n",
+ __func__);
+ ret = -ENOMEM;
+ goto mode_sysfs_add_cpu_exit;
+ }
+
+ mode->kobj = kobject_create_and_add(
+ msm_pm_sleep_mode_labels[i], cpu_kobj);
+ if (!mode->kobj) {
+ pr_err("%s: cannot create kobject\n", __func__);
+ ret = -ENOMEM;
+ goto mode_sysfs_add_cpu_exit;
+ }
+
+ for (k = 0, j = 0; k < MSM_PM_MODE_ATTR_NR; k++) {
+ if ((k == MSM_PM_MODE_ATTR_IDLE) &&
+ !msm_pm_sleep_modes[idx].idle_supported)
+ continue;
+ if ((k == MSM_PM_MODE_ATTR_SUSPEND) &&
+ !msm_pm_sleep_modes[idx].suspend_supported)
+ continue;
+ sysfs_attr_init(&mode->kas[j].ka.attr);
+ mode->kas[j].cpu = cpu;
+ mode->kas[j].ka.attr.mode = 0644;
+ mode->kas[j].ka.show = msm_pm_mode_attr_show;
+ mode->kas[j].ka.store = msm_pm_mode_attr_store;
+ mode->kas[j].ka.attr.name = msm_pm_mode_attr_labels[k];
+ mode->attrs[j] = &mode->kas[j].ka.attr;
+ j++;
+ }
+ mode->attrs[j] = NULL;
+
+ mode->attr_group.attrs = mode->attrs;
+ ret = sysfs_create_group(mode->kobj, &mode->attr_group);
+ if (ret) {
+ pr_err("%s: cannot create kobject attribute group\n",
+ __func__);
+ goto mode_sysfs_add_cpu_exit;
+ }
+ }
+
+ ret = 0;
+
+mode_sysfs_add_cpu_exit:
+ if (ret) {
+ if (mode && mode->kobj)
+ kobject_del(mode->kobj);
+ kfree(mode);
+ }
+
+ return ret;
+}
+
+int msm_pm_mode_sysfs_add(void)
+{
+ struct kobject *module_kobj;
+ struct kobject *modes_kobj;
+ unsigned int cpu;
+ int ret;
+
+ module_kobj = kset_find_obj(module_kset, KBUILD_MODNAME);
+ if (!module_kobj) {
+ pr_err("%s: cannot find kobject for module %s\n",
+ __func__, KBUILD_MODNAME);
+ ret = -ENOENT;
+ goto mode_sysfs_add_exit;
+ }
+
+ modes_kobj = kobject_create_and_add("modes", module_kobj);
+ if (!modes_kobj) {
+ pr_err("%s: cannot create modes kobject\n", __func__);
+ ret = -ENOMEM;
+ goto mode_sysfs_add_exit;
+ }
+
+ for_each_possible_cpu(cpu) {
+ ret = msm_pm_mode_sysfs_add_cpu(cpu, modes_kobj);
+ if (ret)
+ goto mode_sysfs_add_exit;
+ }
+
+ ret = 0;
+
+mode_sysfs_add_exit:
+ return ret;
+}
+
+static inline void msm_arch_idle(void)
+{
+ mb();
+ wfi();
+}
+
+static bool msm_pm_is_L1_writeback(void)
+{
+ u32 sel = 0, cache_id;
+
+ asm volatile ("mcr p15, 2, %[ccselr], c0, c0, 0\n\t"
+ "isb\n\t"
+ "mrc p15, 1, %[ccsidr], c0, c0, 0\n\t"
+ :[ccsidr]"=r" (cache_id)
+ :[ccselr]"r" (sel)
+ );
+ return cache_id & BIT(31);
+}
+
+static enum msm_pm_time_stats_id msm_pm_swfi(bool from_idle)
+{
+ msm_arch_idle();
+ return MSM_PM_STAT_IDLE_WFI;
+}
+
+static enum msm_pm_time_stats_id msm_pm_retention(bool from_idle)
+{
+ int ret = 0;
+ int cpu = smp_processor_id();
+ int saved_rate = 0;
+ struct clk *cpu_clk = per_cpu(cpu_clks, cpu);
+
+ spin_lock(&retention_lock);
+
+ if (!msm_pm_ldo_retention_enabled)
+ goto bailout;
+
+ cpumask_set_cpu(cpu, &retention_cpus);
+ spin_unlock(&retention_lock);
+
+ if (use_acpuclk_apis)
+ saved_rate = acpuclk_power_collapse();
+ else
+ clk_disable(cpu_clk);
+
+ ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_POWER_RETENTION, false);
+ WARN_ON(ret);
+
+ msm_arch_idle();
+
+ if (use_acpuclk_apis) {
+ if (acpuclk_set_rate(cpu, saved_rate, SETRATE_PC))
+ pr_err("%s(): Error setting acpuclk_set_rate\n",
+ __func__);
+ } else {
+ if (clk_enable(cpu_clk))
+ pr_err("%s(): Error restoring cpu clk\n", __func__);
+ }
+
+ spin_lock(&retention_lock);
+ cpumask_clear_cpu(cpu, &retention_cpus);
+bailout:
+ spin_unlock(&retention_lock);
+
+ ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_CLOCK_GATING, false);
+ WARN_ON(ret);
+
+ return MSM_PM_STAT_RETENTION;
+}
+
+static inline void msm_pc_inc_debug_count(uint32_t cpu,
+ enum msm_pc_count_offsets offset)
+{
+ uint32_t cnt;
+
+ if (!msm_pc_debug_counters)
+ return;
+
+ cnt = readl_relaxed(msm_pc_debug_counters + cpu * 4 + offset * 4);
+ writel_relaxed(++cnt, msm_pc_debug_counters + cpu * 4 + offset * 4);
+ mb();
+}
+
+static bool msm_pm_pc_hotplug(void)
+{
+ uint32_t cpu = smp_processor_id();
+
+ if (msm_pm_is_L1_writeback())
+ flush_cache_louis();
+
+ msm_pc_inc_debug_count(cpu, MSM_PC_ENTRY_COUNTER);
+
+ scm_call_atomic1(SCM_SVC_BOOT, SCM_CMD_TERMINATE_PC,
+ SCM_CMD_CORE_HOTPLUGGED);
+
+ /* Should not return here */
+ msm_pc_inc_debug_count(cpu, MSM_PC_FALLTHRU_COUNTER);
+ return 0;
+}
+
+static int msm_pm_collapse(unsigned long unused)
+{
+ uint32_t cpu = smp_processor_id();
+
+ if (msm_pm_get_l2_flush_flag() == MSM_SCM_L2_OFF) {
+ flush_cache_all();
+ if (msm_pm_flush_l2_fn)
+ msm_pm_flush_l2_fn();
+ } else if (msm_pm_is_L1_writeback())
+ flush_cache_louis();
+
+ if (msm_pm_disable_l2_fn)
+ msm_pm_disable_l2_fn();
+
+ msm_pc_inc_debug_count(cpu, MSM_PC_ENTRY_COUNTER);
+
+ scm_call_atomic1(SCM_SVC_BOOT, SCM_CMD_TERMINATE_PC,
+ msm_pm_get_l2_flush_flag());
+
+ msm_pc_inc_debug_count(cpu, MSM_PC_FALLTHRU_COUNTER);
+
+ if (msm_pm_enable_l2_fn)
+ msm_pm_enable_l2_fn();
+
+ return 0;
+}
+
+static bool __ref msm_pm_spm_power_collapse(
+ unsigned int cpu, bool from_idle, bool notify_rpm)
+{
+ void *entry;
+ bool collapsed = 0;
+ int ret;
+ bool save_cpu_regs = !cpu || from_idle;
+
+ if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: notify_rpm %d\n",
+ cpu, __func__, (int) notify_rpm);
+
+ if (from_idle)
+ cpu_pm_enter();
+
+ ret = msm_spm_set_low_power_mode(
+ MSM_SPM_MODE_POWER_COLLAPSE, notify_rpm);
+ WARN_ON(ret);
+
+ entry = save_cpu_regs ? cpu_resume : msm_secondary_startup;
+
+ msm_pm_boot_config_before_pc(cpu, virt_to_phys(entry));
+
+ if (MSM_PM_DEBUG_RESET_VECTOR & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: program vector to %p\n",
+ cpu, __func__, entry);
+
+ msm_jtag_save_state();
+
+ collapsed = save_cpu_regs ?
+ !cpu_suspend(0, msm_pm_collapse) : msm_pm_pc_hotplug();
+
+ msm_jtag_restore_state();
+
+ if (collapsed) {
+ cpu_init();
+ local_fiq_enable();
+ }
+
+ msm_pm_boot_config_after_pc(cpu);
+
+ if (from_idle)
+ cpu_pm_exit();
+
+ if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: msm_pm_collapse returned, collapsed %d\n",
+ cpu, __func__, collapsed);
+
+ ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_CLOCK_GATING, false);
+ WARN_ON(ret);
+ return collapsed;
+}
+
+static enum msm_pm_time_stats_id msm_pm_power_collapse_standalone(
+ bool from_idle)
+{
+ unsigned int cpu = smp_processor_id();
+ unsigned int avsdscr;
+ unsigned int avscsr;
+ bool collapsed;
+
+ avsdscr = avs_get_avsdscr();
+ avscsr = avs_get_avscsr();
+ avs_set_avscsr(0); /* Disable AVS */
+
+ collapsed = msm_pm_spm_power_collapse(cpu, from_idle, false);
+
+ avs_set_avsdscr(avsdscr);
+ avs_set_avscsr(avscsr);
+ return collapsed ? MSM_PM_STAT_IDLE_STANDALONE_POWER_COLLAPSE :
+ MSM_PM_STAT_IDLE_FAILED_STANDALONE_POWER_COLLAPSE;
+}
+
+static int ramp_down_last_cpu(int cpu)
+{
+ struct clk *cpu_clk = per_cpu(cpu_clks, cpu);
+ int ret = 0;
+
+ if (use_acpuclk_apis) {
+ ret = acpuclk_power_collapse();
+ if (MSM_PM_DEBUG_CLOCK & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: change clk rate(old rate = %d)\n",
+ cpu, __func__, ret);
+ } else {
+ clk_disable(cpu_clk);
+ clk_disable(l2_clk);
+ }
+ return ret;
+}
+
+static int ramp_up_first_cpu(int cpu, int saved_rate)
+{
+ struct clk *cpu_clk = per_cpu(cpu_clks, cpu);
+ int rc = 0;
+
+ if (MSM_PM_DEBUG_CLOCK & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: restore clock rate\n",
+ cpu, __func__);
+
+ if (use_acpuclk_apis) {
+ rc = acpuclk_set_rate(cpu, saved_rate, SETRATE_PC);
+ if (rc)
+ pr_err("CPU:%u: Error restoring cpu clk\n", cpu);
+ } else {
+ if (l2_clk) {
+ rc = clk_enable(l2_clk);
+ if (rc)
+ pr_err("%s(): Error restoring l2 clk\n",
+ __func__);
+ }
+
+ if (cpu_clk) {
+ int ret = clk_enable(cpu_clk);
+
+ if (ret) {
+ pr_err("%s(): Error restoring cpu clk\n",
+ __func__);
+ return ret;
+ }
+ }
+ }
+
+ return rc;
+}
+
+static enum msm_pm_time_stats_id msm_pm_power_collapse(bool from_idle)
+{
+ unsigned int cpu = smp_processor_id();
+ unsigned long saved_acpuclk_rate = 0;
+ unsigned int avsdscr;
+ unsigned int avscsr;
+ bool collapsed;
+
+ if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: idle %d\n",
+ cpu, __func__, (int)from_idle);
+
+ if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: pre power down\n", cpu, __func__);
+
+ avsdscr = avs_get_avsdscr();
+ avscsr = avs_get_avscsr();
+ avs_set_avscsr(0); /* Disable AVS */
+
+ if (cpu_online(cpu) && !msm_no_ramp_down_pc)
+ saved_acpuclk_rate = ramp_down_last_cpu(cpu);
+
+ collapsed = msm_pm_spm_power_collapse(cpu, from_idle, true);
+
+ if (cpu_online(cpu) && !msm_no_ramp_down_pc)
+ ramp_up_first_cpu(cpu, saved_acpuclk_rate);
+
+ avs_set_avsdscr(avsdscr);
+ avs_set_avscsr(avscsr);
+
+ if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: post power up\n", cpu, __func__);
+
+ if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: return\n", cpu, __func__);
+ return collapsed ? MSM_PM_STAT_IDLE_POWER_COLLAPSE :
+ MSM_PM_STAT_IDLE_FAILED_POWER_COLLAPSE;
+}
+/******************************************************************************
+ * External Idle/Suspend Functions
+ *****************************************************************************/
+
+void arch_idle(void)
+{
+ return;
+}
+
+static inline void msm_pm_ftrace_lpm_enter(unsigned int cpu,
+ uint32_t latency, uint32_t sleep_us,
+ uint32_t wake_up,
+ enum msm_pm_sleep_mode mode)
+{
+ switch (mode) {
+ case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
+ trace_msm_pm_enter_wfi(cpu, latency, sleep_us, wake_up);
+ break;
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
+ trace_msm_pm_enter_spc(cpu, latency, sleep_us, wake_up);
+ break;
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
+ trace_msm_pm_enter_pc(cpu, latency, sleep_us, wake_up);
+ break;
+ case MSM_PM_SLEEP_MODE_RETENTION:
+ trace_msm_pm_enter_ret(cpu, latency, sleep_us, wake_up);
+ break;
+ default:
+ break;
+ }
+}
+
+static inline void msm_pm_ftrace_lpm_exit(unsigned int cpu,
+ enum msm_pm_sleep_mode mode,
+ bool success)
+{
+ switch (mode) {
+ case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
+ trace_msm_pm_exit_wfi(cpu, success);
+ break;
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
+ trace_msm_pm_exit_spc(cpu, success);
+ break;
+ case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
+ trace_msm_pm_exit_pc(cpu, success);
+ break;
+ case MSM_PM_SLEEP_MODE_RETENTION:
+ trace_msm_pm_exit_ret(cpu, success);
+ break;
+ default:
+ break;
+ }
+}
+
+static enum msm_pm_time_stats_id (*execute[MSM_PM_SLEEP_MODE_NR])(bool idle) = {
+ [MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT] = msm_pm_swfi,
+ [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE] =
+ msm_pm_power_collapse_standalone,
+ [MSM_PM_SLEEP_MODE_RETENTION] = msm_pm_retention,
+ [MSM_PM_SLEEP_MODE_POWER_COLLAPSE] = msm_pm_power_collapse,
+};
+
+bool msm_cpu_pm_check_mode(unsigned int cpu, enum msm_pm_sleep_mode mode,
+ bool from_idle)
+{
+ int idx = MSM_PM_MODE(cpu, mode);
+ struct msm_pm_platform_data *d = &msm_pm_sleep_modes[idx];
+
+ if ((mode == MSM_PM_SLEEP_MODE_RETENTION)
+ && !msm_pm_ldo_retention_enabled)
+ return false;
+
+ if (from_idle)
+ return d->idle_enabled && d->idle_supported;
+ else
+ return d->suspend_enabled && d->suspend_supported;
+}
+
+int msm_cpu_pm_enter_sleep(enum msm_pm_sleep_mode mode, bool from_idle)
+{
+ int64_t time;
+ bool collapsed = 1;
+ int exit_stat = -1;
+
+ if (MSM_PM_DEBUG_IDLE & msm_pm_debug_mask)
+ pr_info("CPU%u: %s: mode %d\n",
+ smp_processor_id(), __func__, mode);
+ if (!from_idle)
+ pr_info("CPU%u: %s mode:%d\n",
+ smp_processor_id(), __func__, mode);
+
+ time = sched_clock();
+ if (execute[mode])
+ exit_stat = execute[mode](from_idle);
+ time = sched_clock() - time;
+ if (from_idle)
+ msm_pm_ftrace_lpm_exit(smp_processor_id(), mode, collapsed);
+ else
+ exit_stat = MSM_PM_STAT_SUSPEND;
+ if (exit_stat >= 0)
+ msm_pm_add_stat(exit_stat, time);
+ do_div(time, 1000);
+ return collapsed;
+}
+
+int msm_pm_wait_cpu_shutdown(unsigned int cpu)
+{
+ int timeout = 10;
+
+ if (!msm_pm_slp_sts)
+ return 0;
+ if (!msm_pm_slp_sts[cpu].base_addr)
+ return 0;
+ while (timeout--) {
+ /*
+ * Check for the SPM of the core being hotplugged to set
+ * its sleep state.The SPM sleep state indicates that the
+ * core has been power collapsed.
+ */
+ int acc_sts = __raw_readl(msm_pm_slp_sts[cpu].base_addr);
+
+ if (acc_sts & msm_pm_slp_sts[cpu].mask)
+ return 0;
+ udelay(100);
+ }
+
+ pr_info("%s(): Timed out waiting for CPU %u SPM to enter sleep state",
+ __func__, cpu);
+ return -EBUSY;
+}
+
+void msm_pm_cpu_enter_lowpower(unsigned int cpu)
+{
+ int i;
+ bool allow[MSM_PM_SLEEP_MODE_NR];
+
+ for (i = 0; i < MSM_PM_SLEEP_MODE_NR; i++) {
+ struct msm_pm_platform_data *mode;
+
+ mode = &msm_pm_sleep_modes[MSM_PM_MODE(cpu, i)];
+ allow[i] = mode->suspend_supported && mode->suspend_enabled;
+ }
+
+ if (MSM_PM_DEBUG_HOTPLUG & msm_pm_debug_mask)
+ pr_notice("CPU%u: %s: shutting down cpu\n", cpu, __func__);
+
+ if (allow[MSM_PM_SLEEP_MODE_POWER_COLLAPSE])
+ msm_pm_power_collapse(false);
+ else if (allow[MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE])
+ msm_pm_power_collapse_standalone(false);
+ else if (allow[MSM_PM_SLEEP_MODE_RETENTION])
+ msm_pm_retention(false);
+ else
+ msm_pm_swfi(false);
+}
+
+static void msm_pm_ack_retention_disable(void *data)
+{
+ /*
+ * This is a NULL function to ensure that the core has woken up
+ * and is safe to disable retention.
+ */
+}
+/**
+ * msm_pm_enable_retention() - Disable/Enable retention on all cores
+ * @enable: Enable/Disable retention
+ *
+ */
+void msm_pm_enable_retention(bool enable)
+{
+ if (enable == msm_pm_ldo_retention_enabled)
+ return;
+
+ msm_pm_ldo_retention_enabled = enable;
+
+ /*
+ * If retention is being disabled, wakeup all online core to ensure
+ * that it isn't executing retention. Offlined cores need not be woken
+ * up as they enter the deepest sleep mode, namely RPM assited power
+ * collapse
+ */
+ if (!enable) {
+ preempt_disable();
+ smp_call_function_many(&retention_cpus,
+ msm_pm_ack_retention_disable,
+ NULL, true);
+ preempt_enable();
+ }
+}
+EXPORT_SYMBOL(msm_pm_enable_retention);
+
+static int msm_pm_snoc_client_probe(struct platform_device *pdev)
+{
+ int rc = 0;
+ static struct msm_bus_scale_pdata *msm_pm_bus_pdata;
+ static uint32_t msm_pm_bus_client;
+
+ msm_pm_bus_pdata = msm_bus_cl_get_pdata(pdev);
+
+ if (msm_pm_bus_pdata) {
+ msm_pm_bus_client =
+ msm_bus_scale_register_client(msm_pm_bus_pdata);
+
+ if (!msm_pm_bus_client) {
+ pr_err("%s: Failed to register SNOC client", __func__);
+ rc = -ENXIO;
+ goto snoc_cl_probe_done;
+ }
+
+ rc = msm_bus_scale_client_update_request(msm_pm_bus_client, 1);
+
+ if (rc)
+ pr_err("%s: Error setting bus rate", __func__);
+ }
+
+snoc_cl_probe_done:
+ return rc;
+}
+
+static int msm_cpu_status_probe(struct platform_device *pdev)
+{
+ struct msm_pm_sleep_status_data *pdata;
+ char *key;
+ u32 cpu;
+
+ if (!pdev)
+ return -EFAULT;
+
+ msm_pm_slp_sts = devm_kzalloc(&pdev->dev,
+ sizeof(*msm_pm_slp_sts) * num_possible_cpus(),
+ GFP_KERNEL);
+
+ if (!msm_pm_slp_sts)
+ return -ENOMEM;
+
+ if (pdev->dev.of_node) {
+ struct resource *res;
+ u32 offset;
+ int rc;
+ u32 mask;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ key = "qcom,cpu-alias-addr";
+ rc = of_property_read_u32(pdev->dev.of_node, key, &offset);
+
+ if (rc)
+ return -ENODEV;
+
+ key = "qcom,sleep-status-mask";
+ rc = of_property_read_u32(pdev->dev.of_node, key, &mask);
+
+ if (rc)
+ return -ENODEV;
+
+ for_each_possible_cpu(cpu) {
+ phys_addr_t base_c = res->start + cpu * offset;
+ msm_pm_slp_sts[cpu].base_addr =
+ devm_ioremap(&pdev->dev, base_c,
+ resource_size(res));
+ msm_pm_slp_sts[cpu].mask = mask;
+
+ if (!msm_pm_slp_sts[cpu].base_addr)
+ return -ENOMEM;
+ }
+ } else {
+ pdata = pdev->dev.platform_data;
+ if (!pdev->dev.platform_data)
+ return -EINVAL;
+
+ for_each_possible_cpu(cpu) {
+ msm_pm_slp_sts[cpu].base_addr =
+ pdata->base_addr + cpu * pdata->cpu_offset;
+ msm_pm_slp_sts[cpu].mask = pdata->mask;
+ }
+ }
+
+ return 0;
+};
+
+static struct of_device_id msm_slp_sts_match_tbl[] = {
+ {.compatible = "qcom,cpu-sleep-status"},
+ {},
+};
+
+static struct platform_driver msm_cpu_status_driver = {
+ .probe = msm_cpu_status_probe,
+ .driver = {
+ .name = "cpu_slp_status",
+ .owner = THIS_MODULE,
+ .of_match_table = msm_slp_sts_match_tbl,
+ },
+};
+
+static struct of_device_id msm_snoc_clnt_match_tbl[] = {
+ {.compatible = "qcom,pm-snoc-client"},
+ {},
+};
+
+static struct platform_driver msm_cpu_pm_snoc_client_driver = {
+ .probe = msm_pm_snoc_client_probe,
+ .driver = {
+ .name = "pm_snoc_client",
+ .owner = THIS_MODULE,
+ .of_match_table = msm_snoc_clnt_match_tbl,
+ },
+};
+
+static int msm_pm_init(void)
+{
+ enum msm_pm_time_stats_id enable_stats[] = {
+ MSM_PM_STAT_IDLE_WFI,
+ MSM_PM_STAT_RETENTION,
+ MSM_PM_STAT_IDLE_STANDALONE_POWER_COLLAPSE,
+ MSM_PM_STAT_IDLE_FAILED_STANDALONE_POWER_COLLAPSE,
+ MSM_PM_STAT_IDLE_POWER_COLLAPSE,
+ MSM_PM_STAT_IDLE_FAILED_POWER_COLLAPSE,
+ MSM_PM_STAT_SUSPEND,
+ };
+ msm_pm_mode_sysfs_add();
+ msm_pm_add_stats(enable_stats, ARRAY_SIZE(enable_stats));
+
+ return 0;
+}
+
+static void msm_pm_set_flush_fn(uint32_t pc_mode)
+{
+ msm_pm_disable_l2_fn = NULL;
+ msm_pm_enable_l2_fn = NULL;
+ msm_pm_flush_l2_fn = outer_flush_all;
+
+ if (pc_mode == MSM_PM_PC_NOTZ_L2_EXT) {
+ msm_pm_disable_l2_fn = outer_disable;
+ msm_pm_enable_l2_fn = outer_resume;
+ }
+}
+
+struct msm_pc_debug_counters_buffer {
+ void __iomem *reg;
+ u32 len;
+ char buf[MAX_BUF_SIZE];
+};
+
+static inline u32 msm_pc_debug_counters_read_register(
+ void __iomem *reg, int index , int offset)
+{
+ return readl_relaxed(reg + (index * 4 + offset) * 4);
+}
+
+static char *counter_name[] = {
+ "PC Entry Counter",
+ "Warmboot Entry Counter",
+ "PC Bailout Counter"
+};
+
+static int msm_pc_debug_counters_copy(
+ struct msm_pc_debug_counters_buffer *data)
+{
+ int j;
+ u32 stat;
+ unsigned int cpu;
+
+ for_each_possible_cpu(cpu) {
+ data->len += scnprintf(data->buf + data->len,
+ sizeof(data->buf)-data->len,
+ "CPU%d\n", cpu);
+
+ for (j = 0; j < MSM_PC_NUM_COUNTERS; j++) {
+ stat = msm_pc_debug_counters_read_register(
+ data->reg, cpu, j);
+ data->len += scnprintf(data->buf + data->len,
+ sizeof(data->buf)-data->len,
+ "\t%s : %d\n", counter_name[j],
+ stat);
+ }
+
+ }
+
+ return data->len;
+}
+
+static int msm_pc_debug_counters_file_read(struct file *file,
+ char __user *bufu, size_t count, loff_t *ppos)
+{
+ struct msm_pc_debug_counters_buffer *data;
+
+ data = file->private_data;
+
+ if (!data)
+ return -EINVAL;
+
+ if (!bufu || count < 0)
+ return -EINVAL;
+
+ if (!access_ok(VERIFY_WRITE, bufu, count))
+ return -EFAULT;
+
+ if (*ppos >= data->len && data->len == 0)
+ data->len = msm_pc_debug_counters_copy(data);
+
+ return simple_read_from_buffer(bufu, count, ppos,
+ data->buf, data->len);
+}
+
+static int msm_pc_debug_counters_file_open(struct inode *inode,
+ struct file *file)
+{
+ struct msm_pc_debug_counters_buffer *buf;
+ void __iomem *msm_pc_debug_counters_reg;
+
+ msm_pc_debug_counters_reg = inode->i_private;
+
+ if (!msm_pc_debug_counters_reg)
+ return -EINVAL;
+
+ file->private_data = kzalloc(
+ sizeof(struct msm_pc_debug_counters_buffer), GFP_KERNEL);
+
+ if (!file->private_data) {
+ pr_err("%s: ERROR kmalloc failed to allocate %d bytes\n",
+ __func__, sizeof(struct msm_pc_debug_counters_buffer));
+
+ return -ENOMEM;
+ }
+
+ buf = file->private_data;
+ buf->reg = msm_pc_debug_counters_reg;
+
+ return 0;
+}
+
+static int msm_pc_debug_counters_file_close(struct inode *inode,
+ struct file *file)
+{
+ kfree(file->private_data);
+ return 0;
+}
+
+static const struct file_operations msm_pc_debug_counters_fops = {
+ .open = msm_pc_debug_counters_file_open,
+ .read = msm_pc_debug_counters_file_read,
+ .release = msm_pc_debug_counters_file_close,
+ .llseek = no_llseek,
+};
+
+static int msm_pm_clk_init(struct platform_device *pdev)
+{
+ bool synced_clocks;
+ u32 cpu;
+ char clk_name[] = "cpu??_clk";
+ bool cpu_as_clocks;
+ char *key;
+
+ key = "qcom,cpus-as-clocks";
+ cpu_as_clocks = of_property_read_bool(pdev->dev.of_node, key);
+
+ if (!cpu_as_clocks) {
+ use_acpuclk_apis = true;
+ return 0;
+ }
+
+ key = "qcom,synced-clocks";
+ synced_clocks = of_property_read_bool(pdev->dev.of_node, key);
+
+ for_each_possible_cpu(cpu) {
+ struct clk *clk;
+ snprintf(clk_name, sizeof(clk_name), "cpu%d_clk", cpu);
+ clk = devm_clk_get(&pdev->dev, clk_name);
+ if (IS_ERR(clk)) {
+ if (cpu && synced_clocks)
+ return 0;
+ else
+ return PTR_ERR(clk);
+ }
+ per_cpu(cpu_clks, cpu) = clk;
+ }
+
+ if (synced_clocks)
+ return 0;
+
+ l2_clk = devm_clk_get(&pdev->dev, "l2_clk");
+
+ return PTR_RET(l2_clk);
+}
+
+static int msm_cpu_pm_probe(struct platform_device *pdev)
+{
+ char *key = NULL;
+ struct dentry *dent = NULL;
+ struct resource *res = NULL;
+ int i;
+ struct msm_pm_init_data_type pdata_local;
+ int ret = 0;
+
+ memset(&pdata_local, 0, sizeof(struct msm_pm_init_data_type));
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return 0;
+ msm_pc_debug_counters_phys = res->start;
+ WARN_ON(resource_size(res) < SZ_64);
+ msm_pc_debug_counters = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+ if (msm_pc_debug_counters) {
+ for (i = 0; i < resource_size(res)/4; i++)
+ __raw_writel(0, msm_pc_debug_counters + i * 4);
+
+ dent = debugfs_create_file("pc_debug_counter", S_IRUGO, NULL,
+ msm_pc_debug_counters,
+ &msm_pc_debug_counters_fops);
+ if (!dent)
+ pr_err("%s: ERROR debugfs_create_file failed\n",
+ __func__);
+ } else {
+ msm_pc_debug_counters = 0;
+ msm_pc_debug_counters_phys = 0;
+ }
+
+ if (pdev->dev.of_node) {
+ enum msm_pm_pc_mode_type pc_mode;
+
+ ret = msm_pm_clk_init(pdev);
+ if (ret) {
+ pr_info("msm_pm_clk_init returned error\n");
+ return ret;
+ }
+
+ key = "qcom,pc-mode";
+ ret = msm_pm_get_pc_mode(pdev->dev.of_node, key, &pc_mode);
+ if (ret) {
+ pr_debug("%s: Error reading key %s", __func__, key);
+ return -EINVAL;
+ }
+ msm_pm_set_flush_fn(pc_mode);
+ }
+
+ msm_pm_init();
+ if (pdev->dev.of_node)
+ of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+
+ return ret;
+}
+
+static struct of_device_id msm_cpu_pm_table[] = {
+ {.compatible = "qcom,pm-8x60"},
+ {},
+};
+
+static struct platform_driver msm_cpu_pm_driver = {
+ .probe = msm_cpu_pm_probe,
+ .driver = {
+ .name = "pm-8x60",
+ .owner = THIS_MODULE,
+ .of_match_table = msm_cpu_pm_table,
+ },
+};
+
+static int __init msm_cpu_pm_init(void)
+{
+ int rc;
+
+ cpumask_clear(&retention_cpus);
+
+ rc = platform_driver_register(&msm_cpu_pm_snoc_client_driver);
+
+ if (rc) {
+ pr_err("%s(): failed to register driver %s\n", __func__,
+ msm_cpu_pm_snoc_client_driver.driver.name);
+ return rc;
+ }
+
+ return platform_driver_register(&msm_cpu_pm_driver);
+}
+device_initcall(msm_cpu_pm_init);
+
+void __init msm_pm_sleep_status_init(void)
+{
+ platform_driver_register(&msm_cpu_status_driver);
+}
diff --git a/arch/arm/mach-msm/pil-msa.c b/arch/arm/mach-msm/pil-msa.c
index 3a26af9..76afe6c 100644
--- a/arch/arm/mach-msm/pil-msa.c
+++ b/arch/arm/mach-msm/pil-msa.c
@@ -233,18 +233,17 @@
if (drv->self_auth) {
ret = pil_msa_wait_for_mba_ready(drv);
if (ret)
- goto err_auth;
+ goto err_q6v5_reset;
}
drv->is_booted = true;
return 0;
-err_auth:
- pil_q6v5_shutdown(pil);
err_q6v5_reset:
pil_msa_pbl_disable_clks(drv);
err_clks:
+ writel_relaxed(1, drv->restart_reg);
pil_msa_pbl_power_down(drv);
err_power:
return ret;
diff --git a/arch/arm/mach-msm/pm-8x60.c b/arch/arm/mach-msm/pm-8x60.c
deleted file mode 100644
index c8a6496..0000000
--- a/arch/arm/mach-msm/pm-8x60.c
+++ /dev/null
@@ -1,1845 +0,0 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/debugfs.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/completion.h>
-#include <linux/cpuidle.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/ktime.h>
-#include <linux/pm.h>
-#include <linux/pm_qos.h>
-#include <linux/smp.h>
-#include <linux/suspend.h>
-#include <linux/tick.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/of_platform.h>
-#include <linux/regulator/krait-regulator.h>
-#include <linux/cpu.h>
-#include <mach/msm_iomap.h>
-#include <mach/socinfo.h>
-#include <mach/system.h>
-#include <mach/scm.h>
-#include <mach/socinfo.h>
-#define CREATE_TRACE_POINTS
-#include <mach/trace_msm_low_power.h>
-#include <mach/msm-krait-l2-accessors.h>
-#include <mach/msm_bus.h>
-#include <mach/mpm.h>
-#include <asm/cacheflush.h>
-#include <asm/hardware/gic.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/outercache.h>
-#ifdef CONFIG_VFP
-#include <asm/vfp.h>
-#endif
-#include "acpuclock.h"
-#include "clock.h"
-#include "avs.h"
-#include <mach/cpuidle.h>
-#include "idle.h"
-#include "pm.h"
-#include "scm-boot.h"
-#include "spm.h"
-#include "timer.h"
-#include "pm-boot.h"
-#include <mach/event_timer.h>
-#include <linux/cpu_pm.h>
-
-#define SCM_L2_RETENTION (0x2)
-#define SCM_CMD_TERMINATE_PC (0x2)
-
-#define GET_CPU_OF_ATTR(attr) \
- (container_of(attr, struct msm_pm_kobj_attribute, ka)->cpu)
-
-#define SCLK_HZ (32768)
-
-#define NUM_OF_COUNTERS 3
-#define MAX_BUF_SIZE 512
-
-static int msm_pm_debug_mask = 1;
-module_param_named(
- debug_mask, msm_pm_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP
-);
-
-static int msm_pm_sleep_time_override;
-module_param_named(sleep_time_override,
- msm_pm_sleep_time_override, int, S_IRUGO | S_IWUSR | S_IWGRP);
-
-static bool use_acpuclk_apis;
-
-enum {
- MSM_PM_DEBUG_SUSPEND = BIT(0),
- MSM_PM_DEBUG_POWER_COLLAPSE = BIT(1),
- MSM_PM_DEBUG_SUSPEND_LIMITS = BIT(2),
- MSM_PM_DEBUG_CLOCK = BIT(3),
- MSM_PM_DEBUG_RESET_VECTOR = BIT(4),
- MSM_PM_DEBUG_IDLE_CLK = BIT(5),
- MSM_PM_DEBUG_IDLE = BIT(6),
- MSM_PM_DEBUG_IDLE_LIMITS = BIT(7),
- MSM_PM_DEBUG_HOTPLUG = BIT(8),
-};
-
-enum {
- MSM_PM_MODE_ATTR_SUSPEND,
- MSM_PM_MODE_ATTR_IDLE,
- MSM_PM_MODE_ATTR_NR,
-};
-
-static char *msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_NR] = {
- [MSM_PM_MODE_ATTR_SUSPEND] = "suspend_enabled",
- [MSM_PM_MODE_ATTR_IDLE] = "idle_enabled",
-};
-
-struct msm_pm_kobj_attribute {
- unsigned int cpu;
- struct kobj_attribute ka;
-};
-
-struct msm_pm_sysfs_sleep_mode {
- struct kobject *kobj;
- struct attribute_group attr_group;
- struct attribute *attrs[MSM_PM_MODE_ATTR_NR + 1];
- struct msm_pm_kobj_attribute kas[MSM_PM_MODE_ATTR_NR];
-};
-
-static char *msm_pm_sleep_mode_labels[MSM_PM_SLEEP_MODE_NR] = {
- [MSM_PM_SLEEP_MODE_POWER_COLLAPSE] = "power_collapse",
- [MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT] = "wfi",
- [MSM_PM_SLEEP_MODE_RETENTION] = "retention",
- [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE] =
- "standalone_power_collapse",
-};
-
-static struct hrtimer pm_hrtimer;
-static struct msm_pm_sleep_ops pm_sleep_ops;
-static bool msm_pm_ldo_retention_enabled = true;
-static bool msm_pm_use_sync_timer;
-static struct msm_pm_cp15_save_data cp15_data;
-static bool msm_pm_retention_calls_tz;
-static bool msm_no_ramp_down_pc;
-static struct msm_pm_sleep_status_data *msm_pm_slp_sts;
-static bool msm_pm_pc_reset_timer;
-
-DEFINE_PER_CPU(struct clk *, cpu_clks);
-static struct clk *l2_clk;
-
-static int msm_pm_get_pc_mode(struct device_node *node,
- const char *key, uint32_t *pc_mode_val)
-{
- struct pc_mode_of {
- uint32_t mode;
- char *mode_name;
- };
- int i;
- struct pc_mode_of pc_modes[] = {
- {MSM_PM_PC_TZ_L2_INT, "tz_l2_int"},
- {MSM_PM_PC_NOTZ_L2_EXT, "no_tz_l2_ext"},
- {MSM_PM_PC_TZ_L2_EXT , "tz_l2_ext"} };
- int ret;
- const char *pc_mode_str;
-
- ret = of_property_read_string(node, key, &pc_mode_str);
- if (ret) {
- pr_debug("%s: Cannot read %s,defaulting to 0", __func__, key);
- pc_mode_val = MSM_PM_PC_TZ_L2_INT;
- ret = 0;
- } else {
- ret = -EINVAL;
- for (i = 0; i < ARRAY_SIZE(pc_modes); i++) {
- if (!strncmp(pc_mode_str, pc_modes[i].mode_name,
- strlen(pc_modes[i].mode_name))) {
- *pc_mode_val = pc_modes[i].mode;
- ret = 0;
- break;
- }
- }
- }
- return ret;
-}
-
-/*
- * Write out the attribute.
- */
-static ssize_t msm_pm_mode_attr_show(
- struct kobject *kobj, struct kobj_attribute *attr, char *buf)
-{
- int ret = -EINVAL;
- int i;
-
- for (i = 0; i < MSM_PM_SLEEP_MODE_NR; i++) {
- struct kernel_param kp;
- unsigned int cpu;
- struct msm_pm_platform_data *mode;
-
- if (msm_pm_sleep_mode_labels[i] == NULL)
- continue;
-
- if (strcmp(kobj->name, msm_pm_sleep_mode_labels[i]))
- continue;
-
- cpu = GET_CPU_OF_ATTR(attr);
- mode = &msm_pm_sleep_modes[MSM_PM_MODE(cpu, i)];
-
- if (!strcmp(attr->attr.name,
- msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_SUSPEND])) {
- u32 arg = mode->suspend_enabled;
- kp.arg = &arg;
- ret = param_get_ulong(buf, &kp);
- } else if (!strcmp(attr->attr.name,
- msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_IDLE])) {
- u32 arg = mode->idle_enabled;
- kp.arg = &arg;
- ret = param_get_ulong(buf, &kp);
- }
-
- break;
- }
-
- if (ret > 0) {
- strlcat(buf, "\n", PAGE_SIZE);
- ret++;
- }
-
- return ret;
-}
-
-static ssize_t msm_pm_mode_attr_store(struct kobject *kobj,
- struct kobj_attribute *attr, const char *buf, size_t count)
-{
- int ret = -EINVAL;
- int i;
-
- for (i = 0; i < MSM_PM_SLEEP_MODE_NR; i++) {
- struct kernel_param kp;
- unsigned int cpu;
- struct msm_pm_platform_data *mode;
-
- if (msm_pm_sleep_mode_labels[i] == NULL)
- continue;
-
- if (strcmp(kobj->name, msm_pm_sleep_mode_labels[i]))
- continue;
-
- cpu = GET_CPU_OF_ATTR(attr);
- mode = &msm_pm_sleep_modes[MSM_PM_MODE(cpu, i)];
-
- if (!strcmp(attr->attr.name,
- msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_SUSPEND])) {
- kp.arg = &mode->suspend_enabled;
- ret = param_set_byte(buf, &kp);
- } else if (!strcmp(attr->attr.name,
- msm_pm_mode_attr_labels[MSM_PM_MODE_ATTR_IDLE])) {
- kp.arg = &mode->idle_enabled;
- ret = param_set_byte(buf, &kp);
- }
-
- break;
- }
-
- return ret ? ret : count;
-}
-
-static int __devinit msm_pm_mode_sysfs_add_cpu(
- unsigned int cpu, struct kobject *modes_kobj)
-{
- char cpu_name[8];
- struct kobject *cpu_kobj;
- struct msm_pm_sysfs_sleep_mode *mode = NULL;
- int i, j, k;
- int ret;
-
- snprintf(cpu_name, sizeof(cpu_name), "cpu%u", cpu);
- cpu_kobj = kobject_create_and_add(cpu_name, modes_kobj);
- if (!cpu_kobj) {
- pr_err("%s: cannot create %s kobject\n", __func__, cpu_name);
- ret = -ENOMEM;
- goto mode_sysfs_add_cpu_exit;
- }
-
- for (i = 0; i < MSM_PM_SLEEP_MODE_NR; i++) {
- int idx = MSM_PM_MODE(cpu, i);
-
- if ((!msm_pm_sleep_modes[idx].suspend_supported)
- && (!msm_pm_sleep_modes[idx].idle_supported))
- continue;
-
- if (!msm_pm_sleep_mode_labels[i] ||
- !msm_pm_sleep_mode_labels[i][0])
- continue;
-
- mode = kzalloc(sizeof(*mode), GFP_KERNEL);
- if (!mode) {
- pr_err("%s: cannot allocate memory for attributes\n",
- __func__);
- ret = -ENOMEM;
- goto mode_sysfs_add_cpu_exit;
- }
-
- mode->kobj = kobject_create_and_add(
- msm_pm_sleep_mode_labels[i], cpu_kobj);
- if (!mode->kobj) {
- pr_err("%s: cannot create kobject\n", __func__);
- ret = -ENOMEM;
- goto mode_sysfs_add_cpu_exit;
- }
-
- for (k = 0, j = 0; k < MSM_PM_MODE_ATTR_NR; k++) {
- if ((k == MSM_PM_MODE_ATTR_IDLE) &&
- !msm_pm_sleep_modes[idx].idle_supported)
- continue;
- if ((k == MSM_PM_MODE_ATTR_SUSPEND) &&
- !msm_pm_sleep_modes[idx].suspend_supported)
- continue;
- sysfs_attr_init(&mode->kas[j].ka.attr);
- mode->kas[j].cpu = cpu;
- mode->kas[j].ka.attr.mode = 0644;
- mode->kas[j].ka.show = msm_pm_mode_attr_show;
- mode->kas[j].ka.store = msm_pm_mode_attr_store;
- mode->kas[j].ka.attr.name = msm_pm_mode_attr_labels[k];
- mode->attrs[j] = &mode->kas[j].ka.attr;
- j++;
- }
- mode->attrs[j] = NULL;
-
- mode->attr_group.attrs = mode->attrs;
- ret = sysfs_create_group(mode->kobj, &mode->attr_group);
- if (ret) {
- pr_err("%s: cannot create kobject attribute group\n",
- __func__);
- goto mode_sysfs_add_cpu_exit;
- }
- }
-
- ret = 0;
-
-mode_sysfs_add_cpu_exit:
- if (ret) {
- if (mode && mode->kobj)
- kobject_del(mode->kobj);
- kfree(mode);
- }
-
- return ret;
-}
-
-int __devinit msm_pm_mode_sysfs_add(void)
-{
- struct kobject *module_kobj;
- struct kobject *modes_kobj;
- unsigned int cpu;
- int ret;
-
- module_kobj = kset_find_obj(module_kset, KBUILD_MODNAME);
- if (!module_kobj) {
- pr_err("%s: cannot find kobject for module %s\n",
- __func__, KBUILD_MODNAME);
- ret = -ENOENT;
- goto mode_sysfs_add_exit;
- }
-
- modes_kobj = kobject_create_and_add("modes", module_kobj);
- if (!modes_kobj) {
- pr_err("%s: cannot create modes kobject\n", __func__);
- ret = -ENOMEM;
- goto mode_sysfs_add_exit;
- }
-
- for_each_possible_cpu(cpu) {
- ret = msm_pm_mode_sysfs_add_cpu(cpu, modes_kobj);
- if (ret)
- goto mode_sysfs_add_exit;
- }
-
- ret = 0;
-
-mode_sysfs_add_exit:
- return ret;
-}
-
-/*
- * Configure hardware registers in preparation for Apps power down.
- */
-static void msm_pm_config_hw_before_power_down(void)
-{
- return;
-}
-
-/*
- * Clear hardware registers after Apps powers up.
- */
-static void msm_pm_config_hw_after_power_up(void)
-{
-}
-
-/*
- * Configure hardware registers in preparation for SWFI.
- */
-static void msm_pm_config_hw_before_swfi(void)
-{
- return;
-}
-
-/*
- * Configure/Restore hardware registers in preparation for Retention.
- */
-
-static void msm_pm_config_hw_after_retention(void)
-{
- int ret;
-
- ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_CLOCK_GATING, false);
- WARN_ON(ret);
-}
-
-static void msm_pm_config_hw_before_retention(void)
-{
- return;
-}
-
-static void msm_pm_save_cpu_reg(void)
-{
- int i;
-
- /* Only on core0 */
- if (smp_processor_id())
- return;
-
- /**
- * On some targets, L2 PC will turn off may reset the core
- * configuration for the mux and the default may not make the core
- * happy when it resumes.
- * Save the active vdd, and set the core vdd to QSB max vdd, so that
- * when the core resumes, it is capable of supporting the current QSB
- * rate. Then restore the active vdd before switching the acpuclk rate.
- */
- if (msm_pm_get_l2_flush_flag() == 1) {
- cp15_data.active_vdd = msm_spm_get_vdd(0);
- for (i = 0; i < cp15_data.reg_saved_state_size; i++)
- cp15_data.reg_val[i] =
- get_l2_indirect_reg(
- cp15_data.reg_data[i]);
- msm_spm_set_vdd(0, cp15_data.qsb_pc_vdd);
- }
-}
-
-static void msm_pm_restore_cpu_reg(void)
-{
- int i;
-
- /* Only on core0 */
- if (smp_processor_id())
- return;
-
- if (msm_pm_get_l2_flush_flag() == 1) {
- for (i = 0; i < cp15_data.reg_saved_state_size; i++)
- set_l2_indirect_reg(
- cp15_data.reg_data[i],
- cp15_data.reg_val[i]);
- msm_spm_set_vdd(0, cp15_data.active_vdd);
- }
-}
-
-static void msm_pm_swfi(void)
-{
- msm_pm_config_hw_before_swfi();
- msm_arch_idle();
-}
-
-static void msm_pm_retention(void)
-{
- int ret = 0;
-
- msm_pm_config_hw_before_retention();
- ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_POWER_RETENTION, false);
- WARN_ON(ret);
-
- if (msm_pm_retention_calls_tz)
- scm_call_atomic1(SCM_SVC_BOOT, SCM_CMD_TERMINATE_PC,
- SCM_L2_RETENTION);
- else
- msm_arch_idle();
-
- msm_pm_config_hw_after_retention();
-}
-
-static bool __ref msm_pm_spm_power_collapse(
- unsigned int cpu, bool from_idle, bool notify_rpm)
-{
- void *entry;
- bool collapsed = 0;
- int ret;
- bool save_cpu_regs = !cpu || from_idle;
- unsigned int saved_gic_cpu_ctrl;
-
- saved_gic_cpu_ctrl = readl_relaxed(MSM_QGIC_CPU_BASE + GIC_CPU_CTRL);
- mb();
-
- if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
- pr_info("CPU%u: %s: notify_rpm %d\n",
- cpu, __func__, (int) notify_rpm);
-
- if (from_idle == true)
- cpu_pm_enter();
-
- ret = msm_spm_set_low_power_mode(
- MSM_SPM_MODE_POWER_COLLAPSE, notify_rpm);
- WARN_ON(ret);
-
- entry = save_cpu_regs ? msm_pm_collapse_exit : msm_secondary_startup;
-
- msm_pm_boot_config_before_pc(cpu, virt_to_phys(entry));
-
- if (MSM_PM_DEBUG_RESET_VECTOR & msm_pm_debug_mask)
- pr_info("CPU%u: %s: program vector to %p\n",
- cpu, __func__, entry);
- if (from_idle && msm_pm_pc_reset_timer)
- clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
-
-#ifdef CONFIG_VFP
- vfp_pm_suspend();
-#endif
- collapsed = save_cpu_regs ? msm_pm_collapse() : msm_pm_pc_hotplug();
-
- if (from_idle && msm_pm_pc_reset_timer)
- clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
-
- msm_pm_boot_config_after_pc(cpu);
-
- if (collapsed) {
-#ifdef CONFIG_VFP
- vfp_pm_resume();
-#endif
- cpu_init();
- writel(0xF0, MSM_QGIC_CPU_BASE + GIC_CPU_PRIMASK);
- writel_relaxed(saved_gic_cpu_ctrl,
- MSM_QGIC_CPU_BASE + GIC_CPU_CTRL);
- mb();
- local_fiq_enable();
- }
-
- if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
- pr_info("CPU%u: %s: msm_pm_collapse returned, collapsed %d\n",
- cpu, __func__, collapsed);
-
- ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_CLOCK_GATING, false);
- WARN_ON(ret);
-
- if (from_idle == true)
- cpu_pm_exit();
-
- return collapsed;
-}
-
-static bool msm_pm_power_collapse_standalone(bool from_idle)
-{
- unsigned int cpu = smp_processor_id();
- unsigned int avsdscr;
- unsigned int avscsr;
- bool collapsed;
-
- avsdscr = avs_get_avsdscr();
- avscsr = avs_get_avscsr();
- avs_set_avscsr(0); /* Disable AVS */
-
- collapsed = msm_pm_spm_power_collapse(cpu, from_idle, false);
-
- avs_set_avsdscr(avsdscr);
- avs_set_avscsr(avscsr);
- return collapsed;
-}
-
-static int ramp_down_last_cpu(int cpu)
-{
- struct clk *cpu_clk = per_cpu(cpu_clks, cpu);
- int ret = 0;
-
- if (use_acpuclk_apis) {
- ret = acpuclk_power_collapse();
- if (MSM_PM_DEBUG_CLOCK & msm_pm_debug_mask)
- pr_info("CPU%u: %s: change clk rate(old rate = %d)\n",
- cpu, __func__, ret);
- } else {
- clk_disable(cpu_clk);
- clk_disable(l2_clk);
- }
- return ret;
-}
-
-static int ramp_up_first_cpu(int cpu, int saved_rate)
-{
- struct clk *cpu_clk = per_cpu(cpu_clks, cpu);
- int rc = 0;
-
- if (MSM_PM_DEBUG_CLOCK & msm_pm_debug_mask)
- pr_info("CPU%u: %s: restore clock rate\n",
- cpu, __func__);
-
- if (use_acpuclk_apis) {
- rc = acpuclk_set_rate(cpu, saved_rate, SETRATE_PC);
- if (rc)
- pr_err("CPU:%u: Error restoring cpu clk\n", cpu);
- } else {
- if (l2_clk) {
- rc = clk_enable(l2_clk);
- if (rc)
- pr_err("%s(): Error restoring l2 clk\n",
- __func__);
- }
-
- if (cpu_clk) {
- int ret = clk_enable(cpu_clk);
-
- if (ret) {
- pr_err("%s(): Error restoring cpu clk\n",
- __func__);
- return ret;
- }
- }
- }
-
- return rc;
-}
-
-static bool msm_pm_power_collapse(bool from_idle)
-{
- unsigned int cpu = smp_processor_id();
- unsigned long saved_acpuclk_rate = 0;
- unsigned int avsdscr;
- unsigned int avscsr;
- bool collapsed;
-
- if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
- pr_info("CPU%u: %s: idle %d\n",
- cpu, __func__, (int)from_idle);
-
- msm_pm_config_hw_before_power_down();
- if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
- pr_info("CPU%u: %s: pre power down\n", cpu, __func__);
-
- avsdscr = avs_get_avsdscr();
- avscsr = avs_get_avscsr();
- avs_set_avscsr(0); /* Disable AVS */
-
- if (cpu_online(cpu) && !msm_no_ramp_down_pc)
- saved_acpuclk_rate = ramp_down_last_cpu(cpu);
-
- if (cp15_data.save_cp15)
- msm_pm_save_cpu_reg();
-
- collapsed = msm_pm_spm_power_collapse(cpu, from_idle, true);
-
- if (cp15_data.save_cp15)
- msm_pm_restore_cpu_reg();
-
- if (cpu_online(cpu) && !msm_no_ramp_down_pc) {
- ramp_up_first_cpu(cpu, saved_acpuclk_rate);
- } else {
- unsigned int gic_dist_enabled;
- unsigned int gic_dist_pending;
- gic_dist_enabled = readl_relaxed(
- MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_CLEAR);
- gic_dist_pending = readl_relaxed(
- MSM_QGIC_DIST_BASE + GIC_DIST_PENDING_SET);
- mb();
- gic_dist_pending &= gic_dist_enabled;
-
- if (gic_dist_pending)
- pr_err("CPU %d interrupted during hotplug.Pending int 0x%x\n",
- cpu, gic_dist_pending);
- }
-
-
- avs_set_avsdscr(avsdscr);
- avs_set_avscsr(avscsr);
- msm_pm_config_hw_after_power_up();
- if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
- pr_info("CPU%u: %s: post power up\n", cpu, __func__);
-
- if (MSM_PM_DEBUG_POWER_COLLAPSE & msm_pm_debug_mask)
- pr_info("CPU%u: %s: return\n", cpu, __func__);
- return collapsed;
-}
-
-static int64_t msm_pm_timer_enter_idle(void)
-{
- if (msm_pm_use_sync_timer)
- return ktime_to_ns(tick_nohz_get_sleep_length());
-
- return msm_timer_enter_idle();
-}
-
-static void msm_pm_timer_exit_idle(bool timer_halted)
-{
- if (msm_pm_use_sync_timer)
- return;
-
- msm_timer_exit_idle((int) timer_halted);
-}
-
-static int64_t msm_pm_timer_enter_suspend(int64_t *period)
-{
- int64_t time = 0;
-
- if (msm_pm_use_sync_timer) {
- struct timespec ts;
- getnstimeofday(&ts);
- return timespec_to_ns(&ts);
- }
-
- time = msm_timer_get_sclk_time(period);
- if (!time)
- pr_err("%s: Unable to read sclk.\n", __func__);
-
- return time;
-}
-
-static int64_t msm_pm_timer_exit_suspend(int64_t time, int64_t period)
-{
- if (msm_pm_use_sync_timer) {
- struct timespec ts;
- getnstimeofday(&ts);
-
- return timespec_to_ns(&ts) - time;
- }
-
- if (time != 0) {
- int64_t end_time = msm_timer_get_sclk_time(NULL);
- if (end_time != 0) {
- time = end_time - time;
- if (time < 0)
- time += period;
- } else
- time = 0;
- }
-
- return time;
-}
-
-/**
- * pm_hrtimer_cb() : Callback function for hrtimer created if the
- * core needs to be awake to handle an event.
- * @hrtimer : Pointer to hrtimer
- */
-static enum hrtimer_restart pm_hrtimer_cb(struct hrtimer *hrtimer)
-{
- return HRTIMER_NORESTART;
-}
-
-/**
- * msm_pm_set_timer() : Set an hrtimer to wakeup the core in time
- * to handle an event.
- */
-static void msm_pm_set_timer(uint32_t modified_time_us)
-{
- u64 modified_time_ns = modified_time_us * NSEC_PER_USEC;
- ktime_t modified_ktime = ns_to_ktime(modified_time_ns);
- pm_hrtimer.function = pm_hrtimer_cb;
- hrtimer_start(&pm_hrtimer, modified_ktime, HRTIMER_MODE_REL);
-}
-
-/******************************************************************************
- * External Idle/Suspend Functions
- *****************************************************************************/
-
-void arch_idle(void)
-{
- return;
-}
-
-static inline void msm_pm_ftrace_lpm_enter(unsigned int cpu,
- uint32_t latency, uint32_t sleep_us,
- uint32_t wake_up,
- enum msm_pm_sleep_mode mode)
-{
- switch (mode) {
- case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
- trace_msm_pm_enter_wfi(cpu, latency, sleep_us, wake_up);
- break;
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
- trace_msm_pm_enter_spc(cpu, latency, sleep_us, wake_up);
- break;
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
- trace_msm_pm_enter_pc(cpu, latency, sleep_us, wake_up);
- break;
- case MSM_PM_SLEEP_MODE_RETENTION:
- trace_msm_pm_enter_ret(cpu, latency, sleep_us, wake_up);
- break;
- default:
- break;
- }
-}
-
-static inline void msm_pm_ftrace_lpm_exit(unsigned int cpu,
- enum msm_pm_sleep_mode mode,
- bool success)
-{
- switch (mode) {
- case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
- trace_msm_pm_exit_wfi(cpu, success);
- break;
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
- trace_msm_pm_exit_spc(cpu, success);
- break;
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
- trace_msm_pm_exit_pc(cpu, success);
- break;
- case MSM_PM_SLEEP_MODE_RETENTION:
- trace_msm_pm_exit_ret(cpu, success);
- break;
- default:
- break;
- }
-}
-
-static int msm_pm_idle_prepare(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index,
- void **msm_pm_idle_rs_limits)
-{
- int i;
- unsigned int power_usage = -1;
- int ret = MSM_PM_SLEEP_MODE_NOT_SELECTED;
- uint32_t modified_time_us = 0;
- struct msm_pm_time_params time_param;
-
- time_param.latency_us =
- (uint32_t) pm_qos_request(PM_QOS_CPU_DMA_LATENCY);
- time_param.sleep_us =
- (uint32_t) (ktime_to_us(tick_nohz_get_sleep_length())
- & UINT_MAX);
- time_param.modified_time_us = 0;
-
- if (!dev->cpu)
- time_param.next_event_us =
- (uint32_t) (ktime_to_us(get_next_event_time())
- & UINT_MAX);
- else
- time_param.next_event_us = 0;
-
- for (i = 0; i < dev->state_count; i++) {
- struct cpuidle_state *state = &drv->states[i];
- struct cpuidle_state_usage *st_usage = &dev->states_usage[i];
- enum msm_pm_sleep_mode mode;
- bool allow;
- uint32_t power;
- int idx;
- void *rs_limits = NULL;
-
- mode = (enum msm_pm_sleep_mode) cpuidle_get_statedata(st_usage);
- idx = MSM_PM_MODE(dev->cpu, mode);
-
- allow = msm_pm_sleep_modes[idx].idle_enabled &&
- msm_pm_sleep_modes[idx].idle_supported;
-
- switch (mode) {
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
- if (num_online_cpus() > 1)
- allow = false;
- break;
- case MSM_PM_SLEEP_MODE_RETENTION:
- /*
- * The Krait BHS regulator doesn't have enough head
- * room to drive the retention voltage on LDO and so
- * has disabled retention
- */
- if (!msm_pm_ldo_retention_enabled)
- allow = false;
-
- if (msm_pm_retention_calls_tz && num_online_cpus() > 1)
- allow = false;
- break;
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
- case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
- break;
- default:
- allow = false;
- break;
- }
-
- if (!allow)
- continue;
-
- if (pm_sleep_ops.lowest_limits)
- rs_limits = pm_sleep_ops.lowest_limits(true,
- mode, &time_param, &power);
-
- if (MSM_PM_DEBUG_IDLE & msm_pm_debug_mask)
- pr_info("CPU%u:%s:%s, latency %uus, slp %uus, lim %p\n",
- dev->cpu, __func__, state->desc,
- time_param.latency_us,
- time_param.sleep_us, rs_limits);
- if (!rs_limits)
- continue;
-
- if (power < power_usage) {
- power_usage = power;
- modified_time_us = time_param.modified_time_us;
- ret = mode;
- *msm_pm_idle_rs_limits = rs_limits;
- }
-
- }
-
- if (modified_time_us && !dev->cpu)
- msm_pm_set_timer(modified_time_us);
-
- msm_pm_ftrace_lpm_enter(dev->cpu, time_param.latency_us,
- time_param.sleep_us, time_param.next_event_us,
- ret);
-
- return ret;
-}
-
-enum msm_pm_sleep_mode msm_pm_idle_enter(struct cpuidle_device *dev,
- struct cpuidle_driver *drv, int index)
-{
- int64_t time;
- bool collapsed = 1;
- int exit_stat = -1;
- enum msm_pm_sleep_mode sleep_mode;
- void *msm_pm_idle_rs_limits = NULL;
- uint32_t sleep_delay = 1;
- int ret = -ENODEV;
- int notify_rpm = false;
- bool timer_halted = false;
-
- sleep_mode = msm_pm_idle_prepare(dev, drv, index,
- &msm_pm_idle_rs_limits);
-
- if (!msm_pm_idle_rs_limits) {
- sleep_mode = MSM_PM_SLEEP_MODE_NOT_SELECTED;
- goto cpuidle_enter_bail;
- }
-
- if (MSM_PM_DEBUG_IDLE & msm_pm_debug_mask)
- pr_info("CPU%u: %s: mode %d\n",
- smp_processor_id(), __func__, sleep_mode);
-
- time = ktime_to_ns(ktime_get());
-
- if (sleep_mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE) {
- int64_t ns = msm_pm_timer_enter_idle();
- notify_rpm = true;
- do_div(ns, NSEC_PER_SEC / SCLK_HZ);
- sleep_delay = (uint32_t)ns;
-
- if (sleep_delay == 0) /* 0 would mean infinite time */
- sleep_delay = 1;
- }
-
- if (pm_sleep_ops.enter_sleep)
- ret = pm_sleep_ops.enter_sleep(sleep_delay,
- msm_pm_idle_rs_limits, true, notify_rpm);
- if (ret)
- goto cpuidle_enter_bail;
-
- switch (sleep_mode) {
- case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
- msm_pm_swfi();
- exit_stat = MSM_PM_STAT_IDLE_WFI;
- break;
-
- case MSM_PM_SLEEP_MODE_RETENTION:
- msm_pm_retention();
- exit_stat = MSM_PM_STAT_RETENTION;
- break;
-
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE:
- collapsed = msm_pm_power_collapse_standalone(true);
- if (collapsed)
- exit_stat = MSM_PM_STAT_IDLE_STANDALONE_POWER_COLLAPSE;
- else
- exit_stat
- = MSM_PM_STAT_IDLE_FAILED_STANDALONE_POWER_COLLAPSE;
- break;
-
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
- if (MSM_PM_DEBUG_IDLE_CLK & msm_pm_debug_mask)
- clock_debug_print_enabled();
-
- collapsed = msm_pm_power_collapse(true);
- timer_halted = true;
-
- if (collapsed)
- exit_stat = MSM_PM_STAT_IDLE_POWER_COLLAPSE;
- else
- exit_stat = MSM_PM_STAT_IDLE_FAILED_POWER_COLLAPSE;
-
- msm_pm_timer_exit_idle(timer_halted);
- break;
-
- case MSM_PM_SLEEP_MODE_NOT_SELECTED:
- goto cpuidle_enter_bail;
- break;
-
- default:
- __WARN();
- goto cpuidle_enter_bail;
- break;
- }
-
- if (pm_sleep_ops.exit_sleep)
- pm_sleep_ops.exit_sleep(msm_pm_idle_rs_limits, true,
- notify_rpm, collapsed);
-
- time = ktime_to_ns(ktime_get()) - time;
- msm_pm_ftrace_lpm_exit(smp_processor_id(), sleep_mode, collapsed);
- if (exit_stat >= 0)
- msm_pm_add_stat(exit_stat, time);
- do_div(time, 1000);
- dev->last_residency = (int) time;
- return sleep_mode;
-
-cpuidle_enter_bail:
- dev->last_residency = 0;
- if (sleep_mode == MSM_PM_SLEEP_MODE_POWER_COLLAPSE)
- msm_pm_timer_exit_idle(timer_halted);
- sleep_mode = MSM_PM_SLEEP_MODE_NOT_SELECTED;
- return sleep_mode;
-}
-
-int msm_pm_wait_cpu_shutdown(unsigned int cpu)
-{
- int timeout = 0;
-
- if (!msm_pm_slp_sts)
- return 0;
- if (!msm_pm_slp_sts[cpu].base_addr)
- return 0;
- while (1) {
- /*
- * Check for the SPM of the core being hotplugged to set
- * its sleep state.The SPM sleep state indicates that the
- * core has been power collapsed.
- */
- int acc_sts = __raw_readl(msm_pm_slp_sts[cpu].base_addr);
-
- if (acc_sts & msm_pm_slp_sts[cpu].mask)
- return 0;
- udelay(100);
- WARN(++timeout == 20, "CPU%u didn't collape within 2ms\n",
- cpu);
- }
-
- return -EBUSY;
-}
-
-void msm_pm_cpu_enter_lowpower(unsigned int cpu)
-{
- int i;
- bool allow[MSM_PM_SLEEP_MODE_NR];
-
- for (i = 0; i < MSM_PM_SLEEP_MODE_NR; i++) {
- struct msm_pm_platform_data *mode;
-
- mode = &msm_pm_sleep_modes[MSM_PM_MODE(cpu, i)];
- allow[i] = mode->suspend_supported && mode->suspend_enabled;
- }
-
- if (MSM_PM_DEBUG_HOTPLUG & msm_pm_debug_mask)
- pr_notice("CPU%u: %s: shutting down cpu\n", cpu, __func__);
-
- if (allow[MSM_PM_SLEEP_MODE_POWER_COLLAPSE])
- msm_pm_power_collapse(false);
- else if (allow[MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE])
- msm_pm_power_collapse_standalone(false);
- else if (allow[MSM_PM_SLEEP_MODE_RETENTION])
- msm_pm_retention();
- else
- msm_pm_swfi();
-}
-
-static void msm_pm_ack_retention_disable(void *data)
-{
- /*
- * This is a NULL function to ensure that the core has woken up
- * and is safe to disable retention.
- */
-}
-/**
- * msm_pm_enable_retention() - Disable/Enable retention on all cores
- * @enable: Enable/Disable retention
- *
- */
-void msm_pm_enable_retention(bool enable)
-{
- if (enable == msm_pm_ldo_retention_enabled)
- return;
-
- msm_pm_ldo_retention_enabled = enable;
- /*
- * If retention is being disabled, wakeup all online core to ensure
- * that it isn't executing retention. Offlined cores need not be woken
- * up as they enter the deepest sleep mode, namely RPM assited power
- * collapse
- */
- if (!enable) {
- preempt_disable();
- smp_call_function_many(cpu_online_mask,
- msm_pm_ack_retention_disable,
- NULL, true);
- preempt_enable();
-
-
- }
-}
-EXPORT_SYMBOL(msm_pm_enable_retention);
-
-static int64_t suspend_time, suspend_period;
-static int collapsed;
-static int suspend_power_collapsed;
-
-static int msm_pm_enter(suspend_state_t state)
-{
- bool allow[MSM_PM_SLEEP_MODE_NR];
- int i;
- struct msm_pm_time_params time_param;
-
- time_param.latency_us = -1;
- time_param.sleep_us = -1;
- time_param.next_event_us = 0;
-
- if (MSM_PM_DEBUG_SUSPEND & msm_pm_debug_mask)
- pr_info("%s\n", __func__);
-
- if (smp_processor_id()) {
- __WARN();
- goto enter_exit;
- }
-
-
- for (i = 0; i < MSM_PM_SLEEP_MODE_NR; i++) {
- struct msm_pm_platform_data *mode;
-
- mode = &msm_pm_sleep_modes[MSM_PM_MODE(0, i)];
- allow[i] = mode->suspend_supported && mode->suspend_enabled;
- }
-
- if (allow[MSM_PM_SLEEP_MODE_POWER_COLLAPSE]) {
- void *rs_limits = NULL;
- int ret = -ENODEV;
- uint32_t power;
- uint32_t msm_pm_max_sleep_time = 0;
-
- if (MSM_PM_DEBUG_SUSPEND & msm_pm_debug_mask)
- pr_info("%s: power collapse\n", __func__);
-
- clock_debug_print_enabled();
-
- if (msm_pm_sleep_time_override > 0) {
- int64_t ns = NSEC_PER_SEC *
- (int64_t) msm_pm_sleep_time_override;
- do_div(ns, NSEC_PER_SEC / SCLK_HZ);
- msm_pm_max_sleep_time = (uint32_t) ns;
- }
-
- if (pm_sleep_ops.lowest_limits)
- rs_limits = pm_sleep_ops.lowest_limits(false,
- MSM_PM_SLEEP_MODE_POWER_COLLAPSE, &time_param, &power);
-
- if (rs_limits) {
- if (pm_sleep_ops.enter_sleep)
- ret = pm_sleep_ops.enter_sleep(
- msm_pm_max_sleep_time,
- rs_limits, false, true);
- if (!ret) {
- collapsed = msm_pm_power_collapse(false);
- if (pm_sleep_ops.exit_sleep) {
- pm_sleep_ops.exit_sleep(rs_limits,
- false, true, collapsed);
- }
- }
- } else {
- pr_err("%s: cannot find the lowest power limit\n",
- __func__);
- }
- suspend_power_collapsed = true;
- } else if (allow[MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE]) {
- if (MSM_PM_DEBUG_SUSPEND & msm_pm_debug_mask)
- pr_info("%s: standalone power collapse\n", __func__);
- msm_pm_power_collapse_standalone(false);
- } else if (allow[MSM_PM_SLEEP_MODE_RETENTION]) {
- if (MSM_PM_DEBUG_SUSPEND & msm_pm_debug_mask)
- pr_info("%s: retention\n", __func__);
- msm_pm_retention();
- } else if (allow[MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT]) {
- if (MSM_PM_DEBUG_SUSPEND & msm_pm_debug_mask)
- pr_info("%s: swfi\n", __func__);
- msm_pm_swfi();
- }
-
-enter_exit:
- if (MSM_PM_DEBUG_SUSPEND & msm_pm_debug_mask)
- pr_info("%s: return\n", __func__);
-
- return 0;
-}
-
-void msm_pm_set_sleep_ops(struct msm_pm_sleep_ops *ops)
-{
- if (ops)
- pm_sleep_ops = *ops;
-}
-
-static int msm_suspend_prepare(void)
-{
- suspend_time = msm_pm_timer_enter_suspend(&suspend_period);
- msm_mpm_suspend_prepare();
- return 0;
-}
-
-static void msm_suspend_wake(void)
-{
- msm_mpm_suspend_wake();
- if (suspend_power_collapsed) {
- suspend_time = msm_pm_timer_exit_suspend(suspend_time,
- suspend_period);
- if (collapsed)
- msm_pm_add_stat(MSM_PM_STAT_SUSPEND, suspend_time);
- else
- msm_pm_add_stat(MSM_PM_STAT_FAILED_SUSPEND,
- suspend_time);
- suspend_power_collapsed = false;
- }
-}
-
-static const struct platform_suspend_ops msm_pm_ops = {
- .enter = msm_pm_enter,
- .valid = suspend_valid_only_mem,
- .prepare_late = msm_suspend_prepare,
- .wake = msm_suspend_wake,
-};
-
-static int __devinit msm_pm_snoc_client_probe(struct platform_device *pdev)
-{
- int rc = 0;
- static struct msm_bus_scale_pdata *msm_pm_bus_pdata;
- static uint32_t msm_pm_bus_client;
-
- msm_pm_bus_pdata = msm_bus_cl_get_pdata(pdev);
-
- if (msm_pm_bus_pdata) {
- msm_pm_bus_client =
- msm_bus_scale_register_client(msm_pm_bus_pdata);
-
- if (!msm_pm_bus_client) {
- pr_err("%s: Failed to register SNOC client",
- __func__);
- rc = -ENXIO;
- goto snoc_cl_probe_done;
- }
-
- rc = msm_bus_scale_client_update_request(msm_pm_bus_client, 1);
-
- if (rc)
- pr_err("%s: Error setting bus rate", __func__);
- }
-
-snoc_cl_probe_done:
- return rc;
-}
-
-static int __devinit msm_cpu_status_probe(struct platform_device *pdev)
-{
- struct msm_pm_sleep_status_data *pdata;
- char *key;
- u32 cpu;
-
- if (!pdev)
- return -EFAULT;
-
- msm_pm_slp_sts =
- kzalloc(sizeof(*msm_pm_slp_sts) * num_possible_cpus(),
- GFP_KERNEL);
-
- if (!msm_pm_slp_sts)
- return -ENOMEM;
-
- if (pdev->dev.of_node) {
- struct resource *res;
- u32 offset;
- int rc;
- u32 mask;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res)
- goto fail_free_mem;
-
- key = "qcom,cpu-alias-addr";
- rc = of_property_read_u32(pdev->dev.of_node, key, &offset);
-
- if (rc)
- goto fail_free_mem;
-
- key = "qcom,sleep-status-mask";
- rc = of_property_read_u32(pdev->dev.of_node, key,
- &mask);
- if (rc)
- goto fail_free_mem;
-
- for_each_possible_cpu(cpu) {
- msm_pm_slp_sts[cpu].base_addr =
- ioremap(res->start + cpu * offset,
- resource_size(res));
- msm_pm_slp_sts[cpu].mask = mask;
-
- if (!msm_pm_slp_sts[cpu].base_addr)
- goto failed_of_node;
- }
-
- } else {
- pdata = pdev->dev.platform_data;
- if (!pdev->dev.platform_data)
- goto fail_free_mem;
-
- for_each_possible_cpu(cpu) {
- msm_pm_slp_sts[cpu].base_addr =
- pdata->base_addr + cpu * pdata->cpu_offset;
- msm_pm_slp_sts[cpu].mask = pdata->mask;
- }
- }
-
- return 0;
-
-failed_of_node:
- pr_info("%s(): Failed to key=%s\n", __func__, key);
- for_each_possible_cpu(cpu) {
- if (msm_pm_slp_sts[cpu].base_addr)
- iounmap(msm_pm_slp_sts[cpu].base_addr);
- }
-fail_free_mem:
- kfree(msm_pm_slp_sts);
- return -EINVAL;
-
-};
-
-static struct of_device_id msm_slp_sts_match_tbl[] = {
- {.compatible = "qcom,cpu-sleep-status"},
- {},
-};
-
-static struct platform_driver msm_cpu_status_driver = {
- .probe = msm_cpu_status_probe,
- .driver = {
- .name = "cpu_slp_status",
- .owner = THIS_MODULE,
- .of_match_table = msm_slp_sts_match_tbl,
- },
-};
-
-static struct of_device_id msm_snoc_clnt_match_tbl[] = {
- {.compatible = "qcom,pm-snoc-client"},
- {},
-};
-
-static struct platform_driver msm_cpu_pm_snoc_client_driver = {
- .probe = msm_pm_snoc_client_probe,
- .driver = {
- .name = "pm_snoc_client",
- .owner = THIS_MODULE,
- .of_match_table = msm_snoc_clnt_match_tbl,
- },
-};
-
-#ifdef CONFIG_ARM_LPAE
-static int msm_pm_idmap_add_pmd(pud_t *pud, unsigned long addr,
- unsigned long end, unsigned long prot)
-{
- pmd_t *pmd;
- unsigned long next;
-
- if (pud_none_or_clear_bad(pud) || (pud_val(*pud) & L_PGD_SWAPPER)) {
- pmd = pmd_alloc_one(&init_mm, addr);
- if (!pmd)
- return -ENOMEM;
-
- pud_populate(&init_mm, pud, pmd);
- pmd += pmd_index(addr);
- } else {
- pmd = pmd_offset(pud, addr);
- }
-
- do {
- next = pmd_addr_end(addr, end);
- *pmd = __pmd((addr & PMD_MASK) | prot);
- flush_pmd_entry(pmd);
- } while (pmd++, addr = next, addr != end);
-
- return 0;
-}
-#else /* !CONFIG_ARM_LPAE */
-static int msm_pm_idmap_add_pmd(pud_t *pud, unsigned long addr,
- unsigned long end, unsigned long prot)
-{
- pmd_t *pmd = pmd_offset(pud, addr);
-
- addr = (addr & PMD_MASK) | prot;
- pmd[0] = __pmd(addr);
- addr += SECTION_SIZE;
- pmd[1] = __pmd(addr);
- flush_pmd_entry(pmd);
-
- return 0;
-}
-#endif /* CONFIG_ARM_LPAE */
-
-static int msm_pm_idmap_add_pud(pgd_t *pgd, unsigned long addr,
- unsigned long end,
- unsigned long prot)
-{
- pud_t *pud = pud_offset(pgd, addr);
- unsigned long next;
- int ret;
-
- do {
- next = pud_addr_end(addr, end);
- ret = msm_pm_idmap_add_pmd(pud, addr, next, prot);
- if (ret)
- return ret;
- } while (pud++, addr = next, addr != end);
-
- return 0;
-}
-
-static int msm_pm_add_idmap(pgd_t *pgd, unsigned long addr,
- unsigned long end,
- unsigned long prot)
-{
- unsigned long next;
- int ret;
-
- pgd += pgd_index(addr);
- do {
- next = pgd_addr_end(addr, end);
- ret = msm_pm_idmap_add_pud(pgd, addr, next, prot);
- if (ret)
- return ret;
- } while (pgd++, addr = next, addr != end);
-
- return 0;
-}
-
-static int msm_pm_setup_pagetable(void)
-{
- pgd_t *pc_pgd;
- unsigned long exit_phys;
- unsigned long end;
- int ret;
-
- /* Page table for cores to come back up safely. */
- pc_pgd = pgd_alloc(&init_mm);
- if (!pc_pgd)
- return -ENOMEM;
-
- exit_phys = virt_to_phys(msm_pm_collapse_exit);
-
- /*
- * Make the (hopefully) reasonable assumption that the code size of
- * msm_pm_collapse_exit won't be more than a section in size
- */
- end = exit_phys + SECTION_SIZE;
-
- ret = msm_pm_add_idmap(pc_pgd, exit_phys, end,
- PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AF);
-
- if (ret)
- return ret;
-
- msm_pm_pc_pgd = virt_to_phys(pc_pgd);
- clean_caches((unsigned long)&msm_pm_pc_pgd, sizeof(msm_pm_pc_pgd),
- virt_to_phys(&msm_pm_pc_pgd));
-
- return 0;
-}
-
-static int __init msm_pm_setup_saved_state(void)
-{
- int ret;
- dma_addr_t temp_phys;
-
- ret = msm_pm_setup_pagetable();
- if (ret)
- return ret;
-
- msm_saved_state = dma_zalloc_coherent(NULL, CPU_SAVED_STATE_SIZE *
- num_possible_cpus(),
- &temp_phys, 0);
-
- if (!msm_saved_state)
- return -ENOMEM;
-
- /*
- * Explicitly cast here since msm_saved_state_phys is defined
- * in assembly and we want to avoid any kind of truncation
- * or endian problems.
- */
- msm_saved_state_phys = (unsigned long)temp_phys;
-
- return 0;
-}
-arch_initcall(msm_pm_setup_saved_state);
-
-static void setup_broadcast_timer(void *arg)
-{
- int cpu = smp_processor_id();
-
- clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
-}
-
-static int setup_broadcast_cpuhp_notify(struct notifier_block *n,
- unsigned long action, void *hcpu)
-{
- int cpu = (unsigned long)hcpu;
-
- switch (action & ~CPU_TASKS_FROZEN) {
- case CPU_ONLINE:
- smp_call_function_single(cpu, setup_broadcast_timer, NULL, 1);
- break;
- }
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block setup_broadcast_notifier = {
- .notifier_call = setup_broadcast_cpuhp_notify,
-};
-
-static int __init msm_pm_init(void)
-{
- enum msm_pm_time_stats_id enable_stats[] = {
- MSM_PM_STAT_IDLE_WFI,
- MSM_PM_STAT_RETENTION,
- MSM_PM_STAT_IDLE_STANDALONE_POWER_COLLAPSE,
- MSM_PM_STAT_IDLE_POWER_COLLAPSE,
- MSM_PM_STAT_SUSPEND,
- };
- msm_pm_mode_sysfs_add();
- msm_pm_add_stats(enable_stats, ARRAY_SIZE(enable_stats));
- suspend_set_ops(&msm_pm_ops);
- hrtimer_init(&pm_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
- msm_cpuidle_init();
-
- if (msm_pm_pc_reset_timer) {
- on_each_cpu(setup_broadcast_timer, NULL, 1);
- register_cpu_notifier(&setup_broadcast_notifier);
- }
-
- return 0;
-}
-
-static void __devinit msm_pm_set_flush_fn(uint32_t pc_mode)
-{
- msm_pm_disable_l2_fn = NULL;
- msm_pm_enable_l2_fn = NULL;
- msm_pm_flush_l2_fn = outer_flush_all;
-
- if (pc_mode == MSM_PM_PC_NOTZ_L2_EXT) {
- msm_pm_disable_l2_fn = outer_disable;
- msm_pm_enable_l2_fn = outer_resume;
- }
-}
-
-struct msm_pc_debug_counters_buffer {
- void __iomem *reg;
- u32 len;
- char buf[MAX_BUF_SIZE];
-};
-
-static inline u32 msm_pc_debug_counters_read_register(
- void __iomem *reg, int index , int offset)
-{
- return readl_relaxed(reg + (index * 4 + offset) * 4);
-}
-
-static char *counter_name[] = {
- "PC Entry Counter",
- "Warmboot Entry Counter",
- "PC Bailout Counter"
-};
-
-static int msm_pc_debug_counters_copy(
- struct msm_pc_debug_counters_buffer *data)
-{
- int j;
- u32 stat;
- unsigned int cpu;
-
- for_each_possible_cpu(cpu) {
- data->len += scnprintf(data->buf + data->len,
- sizeof(data->buf)-data->len,
- "CPU%d\n", cpu);
-
- for (j = 0; j < NUM_OF_COUNTERS; j++) {
- stat = msm_pc_debug_counters_read_register(
- data->reg, cpu, j);
- data->len += scnprintf(data->buf + data->len,
- sizeof(data->buf)-data->len,
- "\t%s : %d\n", counter_name[j],
- stat);
- }
-
- }
-
- return data->len;
-}
-
-static int msm_pc_debug_counters_file_read(struct file *file,
- char __user *bufu, size_t count, loff_t *ppos)
-{
- struct msm_pc_debug_counters_buffer *data;
-
- data = file->private_data;
-
- if (!data)
- return -EINVAL;
-
- if (!bufu)
- return -EINVAL;
-
- if (!access_ok(VERIFY_WRITE, bufu, count))
- return -EFAULT;
-
- if (*ppos >= data->len && data->len == 0)
- data->len = msm_pc_debug_counters_copy(data);
-
- return simple_read_from_buffer(bufu, count, ppos,
- data->buf, data->len);
-}
-
-static int msm_pc_debug_counters_file_open(struct inode *inode,
- struct file *file)
-{
- struct msm_pc_debug_counters_buffer *buf;
- void __iomem *msm_pc_debug_counters_reg;
-
- msm_pc_debug_counters_reg = inode->i_private;
-
- if (!msm_pc_debug_counters_reg)
- return -EINVAL;
-
- file->private_data = kzalloc(
- sizeof(struct msm_pc_debug_counters_buffer), GFP_KERNEL);
-
- if (!file->private_data) {
- pr_err("%s: ERROR kmalloc failed to allocate %d bytes\n",
- __func__, sizeof(struct msm_pc_debug_counters_buffer));
-
- return -ENOMEM;
- }
-
- buf = file->private_data;
- buf->reg = msm_pc_debug_counters_reg;
-
- return 0;
-}
-
-static int msm_pc_debug_counters_file_close(struct inode *inode,
- struct file *file)
-{
- kfree(file->private_data);
- return 0;
-}
-
-static const struct file_operations msm_pc_debug_counters_fops = {
- .open = msm_pc_debug_counters_file_open,
- .read = msm_pc_debug_counters_file_read,
- .release = msm_pc_debug_counters_file_close,
- .llseek = no_llseek,
-};
-
-static int msm_pm_clk_init(struct platform_device *pdev)
-{
- bool synced_clocks;
- u32 cpu;
- char clk_name[] = "cpu??_clk";
- bool cpu_as_clocks;
- char *key;
-
- key = "qcom,cpus-as-clocks";
- cpu_as_clocks = of_property_read_bool(pdev->dev.of_node, key);
-
- if (!cpu_as_clocks) {
- use_acpuclk_apis = true;
- return 0;
- }
-
- key = "qcom,synced-clocks";
- synced_clocks = of_property_read_bool(pdev->dev.of_node, key);
-
- for_each_possible_cpu(cpu) {
- struct clk *clk;
- snprintf(clk_name, sizeof(clk_name), "cpu%d_clk", cpu);
- clk = devm_clk_get(&pdev->dev, clk_name);
- if (IS_ERR(clk)) {
- if (cpu && synced_clocks)
- return 0;
- else
- return PTR_ERR(clk);
- }
- per_cpu(cpu_clks, cpu) = clk;
- }
-
- if (synced_clocks)
- return 0;
-
- l2_clk = devm_clk_get(&pdev->dev, "l2_clk");
-
- return PTR_RET(l2_clk);
-}
-
-static int __devinit msm_pm_8x60_probe(struct platform_device *pdev)
-{
- char *key = NULL;
- struct dentry *dent = NULL;
- struct resource *res = NULL;
- int i ;
- struct msm_pm_init_data_type pdata_local;
- int ret = 0;
-
- memset(&pdata_local, 0, sizeof(struct msm_pm_init_data_type));
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res) {
- msm_pc_debug_counters_phys = res->start;
- WARN_ON(resource_size(res) < SZ_64);
- msm_pc_debug_counters = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (msm_pc_debug_counters)
- for (i = 0; i < resource_size(res)/4; i++)
- __raw_writel(0, msm_pc_debug_counters + i * 4);
-
- }
-
- if (!msm_pc_debug_counters) {
- msm_pc_debug_counters = 0;
- msm_pc_debug_counters_phys = 0;
- } else {
- dent = debugfs_create_file("pc_debug_counter", S_IRUGO, NULL,
- msm_pc_debug_counters,
- &msm_pc_debug_counters_fops);
- if (!dent)
- pr_err("%s: ERROR debugfs_create_file failed\n",
- __func__);
- }
-
- if (!pdev->dev.of_node) {
- struct msm_pm_init_data_type *d = pdev->dev.platform_data;
-
- if (!d)
- goto pm_8x60_probe_done;
-
- memcpy(&pdata_local, d, sizeof(struct msm_pm_init_data_type));
-
- } else {
- ret = msm_pm_clk_init(pdev);
- if (ret) {
- pr_info("msm_pm_clk_init returned error\n");
- return ret;
- }
-
- key = "qcom,pc-mode";
- ret = msm_pm_get_pc_mode(pdev->dev.of_node,
- key,
- &pdata_local.pc_mode);
- if (ret) {
- pr_debug("%s: Error reading key %s",
- __func__, key);
- return -EINVAL;
- }
-
- key = "qcom,use-sync-timer";
- pdata_local.use_sync_timer =
- of_property_read_bool(pdev->dev.of_node, key);
-
- key = "qcom,saw-turns-off-pll";
- msm_no_ramp_down_pc = of_property_read_bool(pdev->dev.of_node,
- key);
-
- key = "qcom,pc-resets-timer";
- msm_pm_pc_reset_timer = of_property_read_bool(
- pdev->dev.of_node, key);
- }
-
- if (pdata_local.cp15_data.reg_data &&
- pdata_local.cp15_data.reg_saved_state_size > 0) {
- cp15_data.reg_data = kzalloc(sizeof(uint32_t) *
- pdata_local.cp15_data.reg_saved_state_size,
- GFP_KERNEL);
- if (!cp15_data.reg_data)
- return -ENOMEM;
-
- cp15_data.reg_val = kzalloc(sizeof(uint32_t) *
- pdata_local.cp15_data.reg_saved_state_size,
- GFP_KERNEL);
- if (cp15_data.reg_val)
- return -ENOMEM;
-
- memcpy(cp15_data.reg_data, pdata_local.cp15_data.reg_data,
- pdata_local.cp15_data.reg_saved_state_size *
- sizeof(uint32_t));
- }
-
- msm_pm_set_flush_fn(pdata_local.pc_mode);
- msm_pm_use_sync_timer = pdata_local.use_sync_timer;
- msm_pm_retention_calls_tz = pdata_local.retention_calls_tz;
-
-pm_8x60_probe_done:
- msm_pm_init();
- if (pdev->dev.of_node)
- of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
-
- return ret;
-}
-
-static struct of_device_id msm_pm_8x60_table[] = {
- {.compatible = "qcom,pm-8x60"},
- {},
-};
-
-static struct platform_driver msm_pm_8x60_driver = {
- .probe = msm_pm_8x60_probe,
- .driver = {
- .name = "pm-8x60",
- .owner = THIS_MODULE,
- .of_match_table = msm_pm_8x60_table,
- },
-};
-
-static int __init msm_pm_8x60_init(void)
-{
- int rc;
-
- rc = platform_driver_register(&msm_cpu_pm_snoc_client_driver);
-
- if (rc) {
- pr_err("%s(): failed to register driver %s\n", __func__,
- msm_cpu_pm_snoc_client_driver.driver.name);
- return rc;
- }
-
- return platform_driver_register(&msm_pm_8x60_driver);
-}
-device_initcall(msm_pm_8x60_init);
-
-void __init msm_pm_sleep_status_init(void)
-{
- platform_driver_register(&msm_cpu_status_driver);
-}
diff --git a/arch/arm/mach-msm/pm-data.c b/arch/arm/mach-msm/pm-data.c
index f41c569..04f4237 100644
--- a/arch/arm/mach-msm/pm-data.c
+++ b/arch/arm/mach-msm/pm-data.c
@@ -43,7 +43,7 @@
},
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
- .idle_supported = 0,
+ .idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 1,
@@ -71,7 +71,7 @@
},
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
- .idle_supported = 0,
+ .idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 1,
@@ -99,7 +99,7 @@
},
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
- .idle_supported = 0,
+ .idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 1,
diff --git a/arch/arm/mach-msm/pm.h b/arch/arm/mach-msm/pm.h
index f2fc80b..a20b36e 100644
--- a/arch/arm/mach-msm/pm.h
+++ b/arch/arm/mach-msm/pm.h
@@ -27,33 +27,20 @@
#define msm_secondary_startup NULL
#endif
-DECLARE_PER_CPU(int, power_collapsed);
-
-struct msm_pm_irq_calls {
- unsigned int (*irq_pending)(void);
- int (*idle_sleep_allowed)(void);
- void (*enter_sleep1)(bool modem_wake, int from_idle, uint32_t
- *irq_mask);
- int (*enter_sleep2)(bool modem_wake, int from_idle);
- void (*exit_sleep1)(uint32_t irq_mask, uint32_t wakeup_reason,
- uint32_t pending_irqs);
- void (*exit_sleep2)(uint32_t irq_mask, uint32_t wakeup_reason,
- uint32_t pending_irqs);
- void (*exit_sleep3)(uint32_t irq_mask, uint32_t wakeup_reason,
- uint32_t pending_irqs);
+enum msm_pm_sleep_mode {
+ MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
+ MSM_PM_SLEEP_MODE_RETENTION,
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
+ MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
+ MSM_PM_SLEEP_MODE_NR,
+ MSM_PM_SLEEP_MODE_NOT_SELECTED,
};
-enum msm_pm_sleep_mode {
- MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT = 0,
- MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT = 1,
- MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE = 2,
- MSM_PM_SLEEP_MODE_POWER_COLLAPSE = 3,
- MSM_PM_SLEEP_MODE_APPS_SLEEP = 4,
- MSM_PM_SLEEP_MODE_RETENTION = MSM_PM_SLEEP_MODE_APPS_SLEEP,
- MSM_PM_SLEEP_MODE_POWER_COLLAPSE_SUSPEND = 5,
- MSM_PM_SLEEP_MODE_POWER_COLLAPSE_NO_XO_SHUTDOWN = 6,
- MSM_PM_SLEEP_MODE_NR = 7,
- MSM_PM_SLEEP_MODE_NOT_SELECTED,
+enum msm_pm_l2_scm_flag {
+ MSM_SCM_L2_ON = 0,
+ MSM_SCM_L2_OFF = 1,
+ MSM_SCM_L2_RET = 2,
+ MSM_SCM_L2_GDHS = 3,
};
#define MSM_PM_MODE(cpu, mode_nr) ((cpu) * MSM_PM_SLEEP_MODE_NR + (mode_nr))
@@ -84,16 +71,6 @@
extern struct msm_pm_platform_data msm_pm_sleep_modes[];
-struct msm_pm_sleep_ops {
- void *(*lowest_limits)(bool from_idle,
- enum msm_pm_sleep_mode sleep_mode,
- struct msm_pm_time_params *time_param, uint32_t *power);
- int (*enter_sleep)(uint32_t sclk_count, void *limits,
- bool from_idle, bool notify_rpm);
- void (*exit_sleep)(void *limits, bool from_idle,
- bool notify_rpm, bool collapsed);
-};
-
enum msm_pm_pc_mode_type {
MSM_PM_PC_TZ_L2_INT, /*Power collapse terminates in TZ;
integrated L2 cache controller */
@@ -103,20 +80,8 @@
external L2 cache controller */
};
-struct msm_pm_cp15_save_data {
- bool save_cp15;
- uint32_t active_vdd;
- uint32_t qsb_pc_vdd;
- uint32_t reg_saved_state_size;
- uint32_t *reg_data;
- uint32_t *reg_val;
-};
-
struct msm_pm_init_data_type {
enum msm_pm_pc_mode_type pc_mode;
- bool retention_calls_tz;
- struct msm_pm_cp15_save_data cp15_data;
- bool use_sync_timer;
};
struct msm_pm_cpr_ops {
@@ -127,21 +92,37 @@
void msm_pm_set_platform_data(struct msm_pm_platform_data *data, int count);
enum msm_pm_sleep_mode msm_pm_idle_enter(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
-void msm_pm_set_irq_extns(struct msm_pm_irq_calls *irq_calls);
void msm_pm_cpu_enter_lowpower(unsigned int cpu);
void __init msm_pm_set_tz_retention_flag(unsigned int flag);
void msm_pm_enable_retention(bool enable);
-#ifdef CONFIG_MSM_PM8X60
+#if defined(CONFIG_MSM_PM)
void msm_pm_set_rpm_wakeup_irq(unsigned int irq);
-void msm_pm_set_sleep_ops(struct msm_pm_sleep_ops *ops);
int msm_pm_wait_cpu_shutdown(unsigned int cpu);
+int msm_cpu_pm_enter_sleep(enum msm_pm_sleep_mode mode, bool from_idle);
void __init msm_pm_sleep_status_init(void);
+void msm_pm_set_l2_flush_flag(enum msm_pm_l2_scm_flag flag);
+bool msm_cpu_pm_check_mode(unsigned int cpu, enum msm_pm_sleep_mode mode,
+ bool from_idle);
+int msm_cpu_pm_enter_sleep(enum msm_pm_sleep_mode mode, bool from_idle);
#else
static inline void msm_pm_set_rpm_wakeup_irq(unsigned int irq) {}
-static inline void msm_pm_set_sleep_ops(struct msm_pm_sleep_ops *ops) {}
static inline int msm_pm_wait_cpu_shutdown(unsigned int cpu) { return 0; }
+static inline int msm_cpu_pm_enter_sleep(enum msm_pm_sleep_mode mode,
+ bool from_idle)
+{
+ return -ENODEV;
+}
static inline void msm_pm_sleep_status_init(void) {};
+static inline void msm_pm_set_l2_flush_flag(unsigned int flag)
+{
+ /* empty */
+}
+bool msm_cpu_pm_check_mode(unsigned int cpu, enum msm_pm_sleep_mode mode,
+ bool from_idle)
+{
+ return false;
+}
#endif
#ifdef CONFIG_HOTPLUG_CPU
int msm_platform_secondary_init(unsigned int cpu);
@@ -174,6 +155,5 @@
#endif
void msm_pm_set_cpr_ops(struct msm_pm_cpr_ops *ops);
-extern void *msm_pc_debug_counters;
extern unsigned long msm_pc_debug_counters_phys;
#endif /* __ARCH_ARM_MACH_MSM_PM_H */
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_dev_ctl.c b/arch/arm/mach-msm/qdsp6v2/audio_dev_ctl.c
deleted file mode 100644
index 8aacb56..0000000
--- a/arch/arm/mach-msm/qdsp6v2/audio_dev_ctl.c
+++ /dev/null
@@ -1,1731 +0,0 @@
-/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/miscdevice.h>
-#include <linux/msm_audio.h>
-#include <linux/slab.h>
-#include <linux/wait.h>
-#include <linux/sched.h>
-#include <linux/workqueue.h>
-#include <asm/uaccess.h>
-#include <asm/atomic.h>
-#include <mach/qdsp6v2/audio_dev_ctl.h>
-#include <mach/debug_mm.h>
-#include <mach/qdsp6v2/q6voice.h>
-#include <sound/apr_audio.h>
-#include <sound/q6adm.h>
-
-#ifndef MAX
-#define MAX(x, y) (((x) > (y)) ? (x) : (y))
-#endif
-
-
-static DEFINE_MUTEX(session_lock);
-static struct workqueue_struct *msm_reset_device_work_queue;
-static void reset_device_work(struct work_struct *work);
-static DECLARE_WORK(msm_reset_device_work, reset_device_work);
-
-struct audio_dev_ctrl_state {
- struct msm_snddev_info *devs[AUDIO_DEV_CTL_MAX_DEV];
- u32 num_dev;
- atomic_t opened;
- struct msm_snddev_info *voice_rx_dev;
- struct msm_snddev_info *voice_tx_dev;
- wait_queue_head_t wait;
-};
-
-static struct audio_dev_ctrl_state audio_dev_ctrl;
-struct event_listner event;
-
-struct session_freq {
- int freq;
- int evt;
-};
-
-struct audio_routing_info {
- unsigned short mixer_mask[MAX_SESSIONS];
- unsigned short audrec_mixer_mask[MAX_SESSIONS];
- struct session_freq dec_freq[MAX_SESSIONS];
- struct session_freq enc_freq[MAX_SESSIONS];
- unsigned int copp_list[MAX_SESSIONS][AFE_MAX_PORTS];
- int voice_tx_dev_id;
- int voice_rx_dev_id;
- int voice_tx_sample_rate;
- int voice_rx_sample_rate;
- signed int voice_tx_vol;
- signed int voice_rx_vol;
- int tx_mute;
- int rx_mute;
- int voice_state;
- struct mutex copp_list_mutex;
- struct mutex adm_mutex;
-};
-
-static struct audio_routing_info routing_info;
-
-struct audio_copp_topology {
- struct mutex lock;
- int session_cnt;
- int session_id[MAX_SESSIONS];
- int topolog_id[MAX_SESSIONS];
-};
-static struct audio_copp_topology adm_tx_topology_tbl;
-
-int msm_reset_all_device(void)
-{
- int rc = 0;
- int dev_id = 0;
- struct msm_snddev_info *dev_info = NULL;
-
- for (dev_id = 0; dev_id < audio_dev_ctrl.num_dev; dev_id++) {
- dev_info = audio_dev_ctrl_find_dev(dev_id);
- if (IS_ERR(dev_info)) {
- pr_err("%s:pass invalid dev_id\n", __func__);
- rc = PTR_ERR(dev_info);
- return rc;
- }
- if (!dev_info->opened)
- continue;
- pr_debug("%s:Resetting device %d active on COPP %d"
- "with %lld as routing\n", __func__,
- dev_id, dev_info->copp_id, dev_info->sessions);
- broadcast_event(AUDDEV_EVT_REL_PENDING,
- dev_id,
- SESSION_IGNORE);
- rc = dev_info->dev_ops.close(dev_info);
- if (rc < 0) {
- pr_err("%s:Snd device failed close!\n", __func__);
- return rc;
- } else {
- dev_info->opened = 0;
- broadcast_event(AUDDEV_EVT_DEV_RLS,
- dev_id,
- SESSION_IGNORE);
-
- if (dev_info->copp_id == VOICE_PLAYBACK_TX)
- voice_start_playback(0);
- }
- dev_info->sessions = 0;
- }
- msm_clear_all_session();
- return 0;
-}
-EXPORT_SYMBOL(msm_reset_all_device);
-
-static void reset_device_work(struct work_struct *work)
-{
- msm_reset_all_device();
-}
-
-int reset_device(void)
-{
- queue_work(msm_reset_device_work_queue, &msm_reset_device_work);
- return 0;
-}
-EXPORT_SYMBOL(reset_device);
-
-int msm_set_copp_id(int session_id, int copp_id)
-{
- int rc = 0;
- int index;
-
- if (session_id < 1 || session_id > 8)
- return -EINVAL;
- if (afe_validate_port(copp_id) < 0)
- return -EINVAL;
-
- index = afe_get_port_index(copp_id);
- if (index < 0 || index > AFE_MAX_PORTS)
- return -EINVAL;
- pr_debug("%s: session[%d] copp_id[%d] index[%d]\n", __func__,
- session_id, copp_id, index);
- mutex_lock(&routing_info.copp_list_mutex);
- if (routing_info.copp_list[session_id][index] == COPP_IGNORE)
- routing_info.copp_list[session_id][index] = copp_id;
- mutex_unlock(&routing_info.copp_list_mutex);
-
- return rc;
-}
-EXPORT_SYMBOL(msm_set_copp_id);
-
-int msm_clear_copp_id(int session_id, int copp_id)
-{
- int rc = 0;
- int index = afe_get_port_index(copp_id);
-
- if (session_id < 1 || session_id > 8)
- return -EINVAL;
- pr_debug("%s: session[%d] copp_id[%d] index[%d]\n", __func__,
- session_id, copp_id, index);
- mutex_lock(&routing_info.copp_list_mutex);
- if (routing_info.copp_list[session_id][index] == copp_id)
- routing_info.copp_list[session_id][index] = COPP_IGNORE;
-#ifdef CONFIG_MSM8X60_RTAC
- rtac_remove_adm_device(copp_id, session_id);
-#endif
- mutex_unlock(&routing_info.copp_list_mutex);
-
- return rc;
-}
-EXPORT_SYMBOL(msm_clear_copp_id);
-
-int msm_clear_session_id(int session_id)
-{
- int rc = 0;
- int i = 0;
- if (session_id < 1 || session_id > 8)
- return -EINVAL;
- pr_debug("%s: session[%d]\n", __func__, session_id);
- mutex_lock(&routing_info.adm_mutex);
- mutex_lock(&routing_info.copp_list_mutex);
- for (i = 0; i < AFE_MAX_PORTS; i++) {
- if (routing_info.copp_list[session_id][i] != COPP_IGNORE) {
- rc = adm_close(routing_info.copp_list[session_id][i]);
- if (rc < 0) {
- pr_err("%s: adm close fail port[%d] rc[%d]\n",
- __func__,
- routing_info.copp_list[session_id][i],
- rc);
- continue;
- }
-#ifdef CONFIG_MSM8X60_RTAC
- rtac_remove_adm_device(
- routing_info.copp_list[session_id][i], session_id);
-#endif
- routing_info.copp_list[session_id][i] = COPP_IGNORE;
- rc = 0;
- }
- }
- mutex_unlock(&routing_info.copp_list_mutex);
- mutex_unlock(&routing_info.adm_mutex);
-
- return rc;
-}
-EXPORT_SYMBOL(msm_clear_session_id);
-
-int msm_clear_all_session()
-{
- int rc = 0;
- int i = 0, j = 0;
- pr_info("%s:\n", __func__);
- mutex_lock(&routing_info.adm_mutex);
- mutex_lock(&routing_info.copp_list_mutex);
- for (j = 1; j < MAX_SESSIONS; j++) {
- for (i = 0; i < AFE_MAX_PORTS; i++) {
- if (routing_info.copp_list[j][i] != COPP_IGNORE) {
- rc = adm_close(
- routing_info.copp_list[j][i]);
- if (rc < 0) {
- pr_err("%s: adm close fail copp[%d]"
- "session[%d] rc[%d]\n",
- __func__,
- routing_info.copp_list[j][i],
- j, rc);
- continue;
- }
- routing_info.copp_list[j][i] = COPP_IGNORE;
- rc = 0;
- }
- }
- }
- mutex_unlock(&routing_info.copp_list_mutex);
- mutex_unlock(&routing_info.adm_mutex);
- return rc;
-}
-EXPORT_SYMBOL(msm_clear_all_session);
-
-int msm_get_voice_state(void)
-{
- pr_debug("voice state %d\n", routing_info.voice_state);
- return routing_info.voice_state;
-}
-EXPORT_SYMBOL(msm_get_voice_state);
-
-int msm_set_voice_mute(int dir, int mute, u32 session_id)
-{
- pr_debug("dir %x mute %x\n", dir, mute);
- if (dir == DIR_TX) {
- routing_info.tx_mute = mute;
- broadcast_event(AUDDEV_EVT_DEVICE_VOL_MUTE_CHG,
- routing_info.voice_tx_dev_id, session_id);
- } else
- return -EPERM;
- return 0;
-}
-EXPORT_SYMBOL(msm_set_voice_mute);
-
-int msm_set_voice_vol(int dir, s32 volume, u32 session_id)
-{
- if (dir == DIR_TX) {
- routing_info.voice_tx_vol = volume;
- broadcast_event(AUDDEV_EVT_DEVICE_VOL_MUTE_CHG,
- routing_info.voice_tx_dev_id,
- session_id);
- } else if (dir == DIR_RX) {
- routing_info.voice_rx_vol = volume;
- broadcast_event(AUDDEV_EVT_DEVICE_VOL_MUTE_CHG,
- routing_info.voice_rx_dev_id,
- session_id);
- } else
- return -EINVAL;
- return 0;
-}
-EXPORT_SYMBOL(msm_set_voice_vol);
-
-void msm_snddev_register(struct msm_snddev_info *dev_info)
-{
- mutex_lock(&session_lock);
- if (audio_dev_ctrl.num_dev < AUDIO_DEV_CTL_MAX_DEV) {
- audio_dev_ctrl.devs[audio_dev_ctrl.num_dev] = dev_info;
- /* roughly 0 DB for digital gain
- * If default gain is not desirable, it is expected that
- * application sets desired gain before activating sound
- * device
- */
- dev_info->dev_volume = 75;
- dev_info->sessions = 0x0;
- dev_info->usage_count = 0;
- audio_dev_ctrl.num_dev++;
- } else
- pr_err("%s: device registry max out\n", __func__);
- mutex_unlock(&session_lock);
-}
-EXPORT_SYMBOL(msm_snddev_register);
-
-int msm_snddev_devcount(void)
-{
- return audio_dev_ctrl.num_dev;
-}
-EXPORT_SYMBOL(msm_snddev_devcount);
-
-int msm_snddev_query(int dev_id)
-{
- if (dev_id <= audio_dev_ctrl.num_dev)
- return 0;
- return -ENODEV;
-}
-EXPORT_SYMBOL(msm_snddev_query);
-
-int msm_snddev_is_set(int popp_id, int copp_id)
-{
- return routing_info.mixer_mask[popp_id] & (0x1 << copp_id);
-}
-EXPORT_SYMBOL(msm_snddev_is_set);
-
-unsigned short msm_snddev_route_enc(int enc_id)
-{
- if (enc_id >= MAX_SESSIONS)
- return -EINVAL;
- return routing_info.audrec_mixer_mask[enc_id];
-}
-EXPORT_SYMBOL(msm_snddev_route_enc);
-
-unsigned short msm_snddev_route_dec(int popp_id)
-{
- if (popp_id >= MAX_SESSIONS)
- return -EINVAL;
- return routing_info.mixer_mask[popp_id];
-}
-EXPORT_SYMBOL(msm_snddev_route_dec);
-
-/*To check one->many case*/
-int msm_check_multicopp_per_stream(int session_id,
- struct route_payload *payload)
-{
- int i = 0;
- int flag = 0;
- pr_debug("%s: session_id=%d\n", __func__, session_id);
- mutex_lock(&routing_info.copp_list_mutex);
- for (i = 0; i < AFE_MAX_PORTS; i++) {
- if (routing_info.copp_list[session_id][i] == COPP_IGNORE)
- continue;
- else {
- pr_debug("Device enabled\n");
- payload->copp_ids[flag++] =
- routing_info.copp_list[session_id][i];
- }
- }
- mutex_unlock(&routing_info.copp_list_mutex);
- if (flag > 1) {
- pr_debug("Multiple copp per stream case num_copps=%d\n", flag);
- } else {
- pr_debug("Stream routed to single copp\n");
- }
- payload->num_copps = flag;
- return flag;
-}
-
-int msm_snddev_set_dec(int popp_id, int copp_id, int set,
- int rate, int mode)
-{
- int rc = 0, i = 0, num_copps;
- struct route_payload payload;
-
- if ((popp_id >= MAX_SESSIONS) || (popp_id <= 0)) {
- pr_err("%s: Invalid session id %d\n", __func__, popp_id);
- return 0;
- }
-
- mutex_lock(&routing_info.adm_mutex);
- if (set) {
- rc = adm_open(copp_id, ADM_PATH_PLAYBACK, rate, mode,
- DEFAULT_COPP_TOPOLOGY);
- if (rc < 0) {
- pr_err("%s: adm open fail rc[%d]\n", __func__, rc);
- rc = -EINVAL;
- mutex_unlock(&routing_info.adm_mutex);
- return rc;
- }
- msm_set_copp_id(popp_id, copp_id);
- pr_debug("%s:Session id=%d copp_id=%d\n",
- __func__, popp_id, copp_id);
- memset(payload.copp_ids, COPP_IGNORE,
- (sizeof(unsigned int) * AFE_MAX_PORTS));
- num_copps = msm_check_multicopp_per_stream(popp_id, &payload);
- /* Multiple streams per copp is handled, one stream at a time */
- rc = adm_matrix_map(popp_id, ADM_PATH_PLAYBACK, num_copps,
- payload.copp_ids, copp_id);
- if (rc < 0) {
- pr_err("%s: matrix map failed rc[%d]\n",
- __func__, rc);
- adm_close(copp_id);
- rc = -EINVAL;
- mutex_unlock(&routing_info.adm_mutex);
- return rc;
- }
-#ifdef CONFIG_MSM8X60_RTAC
- for (i = 0; i < num_copps; i++)
- rtac_add_adm_device(payload.copp_ids[i], popp_id);
-#endif
- } else {
- for (i = 0; i < AFE_MAX_PORTS; i++) {
- if (routing_info.copp_list[popp_id][i] == copp_id) {
- rc = adm_close(copp_id);
- if (rc < 0) {
- pr_err("%s: adm close fail copp[%d]"
- "rc[%d]\n",
- __func__, copp_id, rc);
- rc = -EINVAL;
- mutex_unlock(&routing_info.adm_mutex);
- return rc;
- }
- msm_clear_copp_id(popp_id, copp_id);
- break;
- }
- }
- }
-
- if (copp_id == VOICE_PLAYBACK_TX) {
- /* Signal uplink playback. */
- rc = voice_start_playback(set);
- }
- mutex_unlock(&routing_info.adm_mutex);
- return rc;
-}
-EXPORT_SYMBOL(msm_snddev_set_dec);
-
-
-static int check_tx_copp_topology(int session_id)
-{
- int cnt;
- int ret_val = -ENOENT;
-
- cnt = adm_tx_topology_tbl.session_cnt;
- if (cnt) {
- do {
- if (adm_tx_topology_tbl.session_id[cnt-1]
- == session_id)
- ret_val = cnt-1;
- } while (--cnt);
- }
-
- return ret_val;
-}
-
-static int add_to_tx_topology_lists(int session_id, int topology)
-{
- int idx = 0, tbl_idx;
- int ret_val = -ENOSPC;
-
- mutex_lock(&adm_tx_topology_tbl.lock);
-
- tbl_idx = check_tx_copp_topology(session_id);
- if (tbl_idx == -ENOENT) {
- while (adm_tx_topology_tbl.session_id[idx++])
- ;
- tbl_idx = idx-1;
- }
-
- if (tbl_idx < MAX_SESSIONS) {
- adm_tx_topology_tbl.session_id[tbl_idx] = session_id;
- adm_tx_topology_tbl.topolog_id[tbl_idx] = topology;
- adm_tx_topology_tbl.session_cnt++;
-
- ret_val = 0;
- }
- mutex_unlock(&adm_tx_topology_tbl.lock);
- return ret_val;
-}
-
-static void remove_from_tx_topology_lists(int session_id)
-{
- int tbl_idx;
-
- mutex_lock(&adm_tx_topology_tbl.lock);
- tbl_idx = check_tx_copp_topology(session_id);
- if (tbl_idx != -ENOENT) {
-
- adm_tx_topology_tbl.session_cnt--;
- adm_tx_topology_tbl.session_id[tbl_idx] = 0;
- adm_tx_topology_tbl.topolog_id[tbl_idx] = 0;
- }
- mutex_unlock(&adm_tx_topology_tbl.lock);
-}
-
-int auddev_cfg_tx_copp_topology(int session_id, int cfg)
-{
- int ret = 0;
-
- if (cfg == DEFAULT_COPP_TOPOLOGY)
- remove_from_tx_topology_lists(session_id);
- else {
- switch (cfg) {
- case VPM_TX_SM_ECNS_COPP_TOPOLOGY:
- case VPM_TX_DM_FLUENCE_COPP_TOPOLOGY:
- ret = add_to_tx_topology_lists(session_id, cfg);
- break;
-
- default:
- ret = -ENODEV;
- break;
- }
- }
- return ret;
-}
-
-int msm_snddev_set_enc(int popp_id, int copp_id, int set,
- int rate, int mode)
-{
- int topology;
- int tbl_idx;
- int rc = 0, i = 0;
- mutex_lock(&routing_info.adm_mutex);
- if (set) {
- mutex_lock(&adm_tx_topology_tbl.lock);
- tbl_idx = check_tx_copp_topology(popp_id);
- if (tbl_idx == -ENOENT)
- topology = DEFAULT_COPP_TOPOLOGY;
- else {
- topology = adm_tx_topology_tbl.topolog_id[tbl_idx];
- rate = 16000;
- }
- mutex_unlock(&adm_tx_topology_tbl.lock);
- rc = adm_open(copp_id, ADM_PATH_LIVE_REC, rate, mode, topology);
- if (rc < 0) {
- pr_err("%s: adm open fail rc[%d]\n", __func__, rc);
- rc = -EINVAL;
- goto fail_cmd;
- }
-
- rc = adm_matrix_map(popp_id, ADM_PATH_LIVE_REC, 1,
- (unsigned int *)&copp_id, copp_id);
- if (rc < 0) {
- pr_err("%s: matrix map failed rc[%d]\n", __func__, rc);
- adm_close(copp_id);
- rc = -EINVAL;
- goto fail_cmd;
- }
- msm_set_copp_id(popp_id, copp_id);
-#ifdef CONFIG_MSM8X60_RTAC
- rtac_add_adm_device(copp_id, popp_id);
-#endif
-
- } else {
- for (i = 0; i < AFE_MAX_PORTS; i++) {
- if (routing_info.copp_list[popp_id][i] == copp_id) {
- rc = adm_close(copp_id);
- if (rc < 0) {
- pr_err("%s: adm close fail copp[%d]"
- "rc[%d]\n",
- __func__, copp_id, rc);
- rc = -EINVAL;
- goto fail_cmd;
- }
- msm_clear_copp_id(popp_id, copp_id);
- break;
- }
- }
- }
-fail_cmd:
- mutex_unlock(&routing_info.adm_mutex);
- return rc;
-}
-EXPORT_SYMBOL(msm_snddev_set_enc);
-
-int msm_device_is_voice(int dev_id)
-{
- if ((dev_id == routing_info.voice_rx_dev_id)
- || (dev_id == routing_info.voice_tx_dev_id))
- return 0;
- else
- return -EINVAL;
-}
-EXPORT_SYMBOL(msm_device_is_voice);
-
-int msm_set_voc_route(struct msm_snddev_info *dev_info,
- int stream_type, int dev_id)
-{
- int rc = 0;
- u64 session_mask = 0;
-
- mutex_lock(&session_lock);
- switch (stream_type) {
- case AUDIO_ROUTE_STREAM_VOICE_RX:
- if (audio_dev_ctrl.voice_rx_dev)
- audio_dev_ctrl.voice_rx_dev->sessions &= ~0xFFFF;
-
- if (!(dev_info->capability & SNDDEV_CAP_RX) |
- !(dev_info->capability & SNDDEV_CAP_VOICE)) {
- rc = -EINVAL;
- break;
- }
- audio_dev_ctrl.voice_rx_dev = dev_info;
- if (audio_dev_ctrl.voice_rx_dev) {
- session_mask =
- ((u64)0x1) << (MAX_BIT_PER_CLIENT * \
- ((int)AUDDEV_CLNT_VOC-1));
- audio_dev_ctrl.voice_rx_dev->sessions |=
- session_mask;
- }
- routing_info.voice_rx_dev_id = dev_id;
- break;
- case AUDIO_ROUTE_STREAM_VOICE_TX:
- if (audio_dev_ctrl.voice_tx_dev)
- audio_dev_ctrl.voice_tx_dev->sessions &= ~0xFFFF;
-
- if (!(dev_info->capability & SNDDEV_CAP_TX) |
- !(dev_info->capability & SNDDEV_CAP_VOICE)) {
- rc = -EINVAL;
- break;
- }
-
- audio_dev_ctrl.voice_tx_dev = dev_info;
- if (audio_dev_ctrl.voice_rx_dev) {
- session_mask =
- ((u64)0x1) << (MAX_BIT_PER_CLIENT * \
- ((int)AUDDEV_CLNT_VOC-1));
- audio_dev_ctrl.voice_tx_dev->sessions |=
- session_mask;
- }
- routing_info.voice_tx_dev_id = dev_id;
- break;
- default:
- rc = -EINVAL;
- }
- mutex_unlock(&session_lock);
- return rc;
-}
-EXPORT_SYMBOL(msm_set_voc_route);
-
-void msm_release_voc_thread(void)
-{
- wake_up(&audio_dev_ctrl.wait);
-}
-EXPORT_SYMBOL(msm_release_voc_thread);
-
-int msm_snddev_get_enc_freq(session_id)
-{
- return routing_info.enc_freq[session_id].freq;
-}
-EXPORT_SYMBOL(msm_snddev_get_enc_freq);
-
-int msm_get_voc_freq(int *tx_freq, int *rx_freq)
-{
- *tx_freq = routing_info.voice_tx_sample_rate;
- *rx_freq = routing_info.voice_rx_sample_rate;
- return 0;
-}
-EXPORT_SYMBOL(msm_get_voc_freq);
-
-int msm_get_voc_route(u32 *rx_id, u32 *tx_id)
-{
- int rc = 0;
-
- if (!rx_id || !tx_id)
- return -EINVAL;
-
- mutex_lock(&session_lock);
- if (!audio_dev_ctrl.voice_rx_dev || !audio_dev_ctrl.voice_tx_dev) {
- rc = -ENODEV;
- mutex_unlock(&session_lock);
- return rc;
- }
-
- *rx_id = audio_dev_ctrl.voice_rx_dev->acdb_id;
- *tx_id = audio_dev_ctrl.voice_tx_dev->acdb_id;
-
- mutex_unlock(&session_lock);
-
- return rc;
-}
-EXPORT_SYMBOL(msm_get_voc_route);
-
-struct msm_snddev_info *audio_dev_ctrl_find_dev(u32 dev_id)
-{
- struct msm_snddev_info *info;
-
- if ((audio_dev_ctrl.num_dev - 1) < dev_id) {
- info = ERR_PTR(-ENODEV);
- goto error;
- }
-
- info = audio_dev_ctrl.devs[dev_id];
-error:
- return info;
-
-}
-EXPORT_SYMBOL(audio_dev_ctrl_find_dev);
-
-int snddev_voice_set_volume(int vol, int path)
-{
- if (audio_dev_ctrl.voice_rx_dev
- && audio_dev_ctrl.voice_tx_dev) {
- if (path)
- audio_dev_ctrl.voice_tx_dev->dev_volume = vol;
- else
- audio_dev_ctrl.voice_rx_dev->dev_volume = vol;
- } else
- return -ENODEV;
- return 0;
-}
-EXPORT_SYMBOL(snddev_voice_set_volume);
-
-static int audio_dev_ctrl_get_devices(struct audio_dev_ctrl_state *dev_ctrl,
- void __user *arg)
-{
- int rc = 0;
- u32 index;
- struct msm_snd_device_list work_list;
- struct msm_snd_device_info *work_tbl;
-
- if (copy_from_user(&work_list, arg, sizeof(work_list))) {
- rc = -EFAULT;
- goto error;
- }
-
- if (work_list.num_dev > dev_ctrl->num_dev) {
- rc = -EINVAL;
- goto error;
- }
-
- work_tbl = kmalloc(work_list.num_dev *
- sizeof(struct msm_snd_device_info), GFP_KERNEL);
- if (!work_tbl) {
- rc = -ENOMEM;
- goto error;
- }
-
- for (index = 0; index < dev_ctrl->num_dev; index++) {
- work_tbl[index].dev_id = index;
- work_tbl[index].dev_cap = dev_ctrl->devs[index]->capability;
- strlcpy(work_tbl[index].dev_name, dev_ctrl->devs[index]->name,
- 64);
- }
-
- if (copy_to_user((void *) (work_list.list), work_tbl,
- work_list.num_dev * sizeof(struct msm_snd_device_info)))
- rc = -EFAULT;
- kfree(work_tbl);
-error:
- return rc;
-}
-
-
-int auddev_register_evt_listner(u32 evt_id, u32 clnt_type, u32 clnt_id,
- void (*listner)(u32 evt_id,
- union auddev_evt_data *evt_payload,
- void *private_data),
- void *private_data)
-{
- int rc;
- struct msm_snd_evt_listner *callback = NULL;
- struct msm_snd_evt_listner *new_cb;
-
- new_cb = kzalloc(sizeof(struct msm_snd_evt_listner), GFP_KERNEL);
- if (!new_cb) {
- pr_err("No memory to add new listener node\n");
- return -ENOMEM;
- }
-
- mutex_lock(&session_lock);
- new_cb->cb_next = NULL;
- new_cb->auddev_evt_listener = listner;
- new_cb->evt_id = evt_id;
- new_cb->clnt_type = clnt_type;
- new_cb->clnt_id = clnt_id;
- new_cb->private_data = private_data;
- if (event.cb == NULL) {
- event.cb = new_cb;
- new_cb->cb_prev = NULL;
- } else {
- callback = event.cb;
- for (; ;) {
- if (callback->cb_next == NULL)
- break;
- else {
- callback = callback->cb_next;
- continue;
- }
- }
- callback->cb_next = new_cb;
- new_cb->cb_prev = callback;
- }
- event.num_listner++;
- mutex_unlock(&session_lock);
- rc = 0;
- return rc;
-}
-EXPORT_SYMBOL(auddev_register_evt_listner);
-
-int auddev_unregister_evt_listner(u32 clnt_type, u32 clnt_id)
-{
- struct msm_snd_evt_listner *callback = event.cb;
- struct msm_snddev_info *info;
- u64 session_mask = 0;
- int i = 0;
-
- mutex_lock(&session_lock);
- while (callback != NULL) {
- if ((callback->clnt_type == clnt_type)
- && (callback->clnt_id == clnt_id))
- break;
- callback = callback->cb_next;
- }
- if (callback == NULL) {
- mutex_unlock(&session_lock);
- return -EINVAL;
- }
-
- if ((callback->cb_next == NULL) && (callback->cb_prev == NULL))
- event.cb = NULL;
- else if (callback->cb_next == NULL)
- callback->cb_prev->cb_next = NULL;
- else if (callback->cb_prev == NULL) {
- callback->cb_next->cb_prev = NULL;
- event.cb = callback->cb_next;
- } else {
- callback->cb_prev->cb_next = callback->cb_next;
- callback->cb_next->cb_prev = callback->cb_prev;
- }
- kfree(callback);
-
- session_mask = (((u64)0x1) << clnt_id) << (MAX_BIT_PER_CLIENT * \
- ((int)clnt_type-1));
- for (i = 0; i < audio_dev_ctrl.num_dev; i++) {
- info = audio_dev_ctrl.devs[i];
- info->sessions &= ~session_mask;
- }
- mutex_unlock(&session_lock);
- return 0;
-}
-EXPORT_SYMBOL(auddev_unregister_evt_listner);
-
-int msm_snddev_withdraw_freq(u32 session_id, u32 capability, u32 clnt_type)
-{
- int i = 0;
- struct msm_snddev_info *info;
- u64 session_mask = 0;
-
- if ((clnt_type == AUDDEV_CLNT_VOC) && (session_id != 0))
- return -EINVAL;
- if ((clnt_type == AUDDEV_CLNT_DEC)
- && (session_id >= MAX_SESSIONS))
- return -EINVAL;
- if ((clnt_type == AUDDEV_CLNT_ENC)
- && (session_id >= MAX_SESSIONS))
- return -EINVAL;
-
- session_mask = (((u64)0x1) << session_id) << (MAX_BIT_PER_CLIENT * \
- ((int)clnt_type-1));
-
- for (i = 0; i < audio_dev_ctrl.num_dev; i++) {
- info = audio_dev_ctrl.devs[i];
- if ((info->sessions & session_mask)
- && (info->capability & capability)) {
- if (!(info->sessions & ~(session_mask)))
- info->set_sample_rate = 0;
- }
- }
- if (clnt_type == AUDDEV_CLNT_DEC)
- routing_info.dec_freq[session_id].freq
- = 0;
- else if (clnt_type == AUDDEV_CLNT_ENC)
- routing_info.enc_freq[session_id].freq
- = 0;
- else if (capability == SNDDEV_CAP_TX)
- routing_info.voice_tx_sample_rate = 0;
- else
- routing_info.voice_rx_sample_rate = 48000;
- return 0;
-}
-
-int msm_snddev_request_freq(int *freq, u32 session_id,
- u32 capability, u32 clnt_type)
-{
- int i = 0;
- int rc = 0;
- struct msm_snddev_info *info;
- u32 set_freq;
- u64 session_mask = 0;
- u64 clnt_type_mask = 0;
-
- pr_debug(": clnt_type 0x%08x\n", clnt_type);
-
- if ((clnt_type == AUDDEV_CLNT_VOC) && (session_id != 0))
- return -EINVAL;
- if ((clnt_type == AUDDEV_CLNT_DEC)
- && (session_id >= MAX_SESSIONS))
- return -EINVAL;
- if ((clnt_type == AUDDEV_CLNT_ENC)
- && (session_id >= MAX_SESSIONS))
- return -EINVAL;
- session_mask = (((u64)0x1) << session_id) << (MAX_BIT_PER_CLIENT * \
- ((int)clnt_type-1));
- clnt_type_mask = (0xFFFF << (MAX_BIT_PER_CLIENT * (clnt_type-1)));
- if (!(*freq == 8000) && !(*freq == 11025) &&
- !(*freq == 12000) && !(*freq == 16000) &&
- !(*freq == 22050) && !(*freq == 24000) &&
- !(*freq == 32000) && !(*freq == 44100) &&
- !(*freq == 48000))
- return -EINVAL;
-
- for (i = 0; i < audio_dev_ctrl.num_dev; i++) {
- info = audio_dev_ctrl.devs[i];
- if ((info->sessions & session_mask)
- && (info->capability & capability)) {
- rc = 0;
- if ((info->sessions & ~clnt_type_mask)
- && ((*freq != 8000) && (*freq != 16000)
- && (*freq != 48000))) {
- if (clnt_type == AUDDEV_CLNT_ENC) {
- routing_info.enc_freq[session_id].freq
- = 0;
- return -EPERM;
- } else if (clnt_type == AUDDEV_CLNT_DEC) {
- routing_info.dec_freq[session_id].freq
- = 0;
- return -EPERM;
- }
- }
- if (*freq == info->set_sample_rate) {
- rc = info->set_sample_rate;
- continue;
- }
- set_freq = MAX(*freq, info->set_sample_rate);
-
-
- if (clnt_type == AUDDEV_CLNT_DEC) {
- routing_info.dec_freq[session_id].evt = 1;
- routing_info.dec_freq[session_id].freq
- = set_freq;
- } else if (clnt_type == AUDDEV_CLNT_ENC) {
- routing_info.enc_freq[session_id].evt = 1;
- routing_info.enc_freq[session_id].freq
- = set_freq;
- } else if (capability == SNDDEV_CAP_TX)
- routing_info.voice_tx_sample_rate = set_freq;
-
- rc = set_freq;
- info->set_sample_rate = set_freq;
- *freq = info->set_sample_rate;
-
- if (info->opened) {
- broadcast_event(AUDDEV_EVT_FREQ_CHG, i,
- SESSION_IGNORE);
- set_freq = info->dev_ops.set_freq(info,
- set_freq);
- broadcast_event(AUDDEV_EVT_DEV_RDY, i,
- SESSION_IGNORE);
- }
- }
- pr_debug("info->set_sample_rate = %d\n", info->set_sample_rate);
- pr_debug("routing_info.enc_freq.freq = %d\n",
- routing_info.enc_freq[session_id].freq);
- }
- return rc;
-}
-EXPORT_SYMBOL(msm_snddev_request_freq);
-
-int msm_snddev_enable_sidetone(u32 dev_id, u32 enable, uint16_t gain)
-{
- int rc;
- struct msm_snddev_info *dev_info;
-
- pr_debug("dev_id %d enable %d\n", dev_id, enable);
-
- dev_info = audio_dev_ctrl_find_dev(dev_id);
-
- if (IS_ERR(dev_info)) {
- pr_err("bad dev_id %d\n", dev_id);
- rc = -EINVAL;
- } else if (!dev_info->dev_ops.enable_sidetone) {
- pr_debug("dev %d no sidetone support\n", dev_id);
- rc = -EPERM;
- } else
- rc = dev_info->dev_ops.enable_sidetone(dev_info, enable, gain);
-
- return rc;
-}
-EXPORT_SYMBOL(msm_snddev_enable_sidetone);
-
-int msm_enable_incall_recording(int popp_id, int rec_mode, int rate,
- int channel_mode)
-{
- int rc = 0;
- unsigned int port_id[2];
- port_id[0] = VOICE_RECORD_TX;
- port_id[1] = VOICE_RECORD_RX;
-
- pr_debug("%s: popp_id %d, rec_mode %d, rate %d, channel_mode %d\n",
- __func__, popp_id, rec_mode, rate, channel_mode);
-
- mutex_lock(&routing_info.adm_mutex);
-
- if (rec_mode == VOC_REC_UPLINK) {
- rc = afe_start_pseudo_port(port_id[0]);
- if (rc < 0) {
- pr_err("%s: Error %d in Tx pseudo port start\n",
- __func__, rc);
-
- goto fail_cmd;
- }
-
- rc = adm_open(port_id[0], ADM_PATH_LIVE_REC, rate, channel_mode,
- DEFAULT_COPP_TOPOLOGY);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM open %d\n",
- __func__, rc, port_id[0]);
-
- goto fail_cmd;
- }
-
- rc = adm_matrix_map(popp_id, ADM_PATH_LIVE_REC, 1,
- &port_id[0], port_id[0]);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM matrix map %d\n",
- __func__, rc, port_id[0]);
-
- goto fail_cmd;
- }
-
- msm_set_copp_id(popp_id, port_id[0]);
-
- } else if (rec_mode == VOC_REC_DOWNLINK) {
- rc = afe_start_pseudo_port(port_id[1]);
- if (rc < 0) {
- pr_err("%s: Error %d in Rx pseudo port start\n",
- __func__, rc);
-
- goto fail_cmd;
- }
-
- rc = adm_open(port_id[1], ADM_PATH_LIVE_REC, rate, channel_mode,
- DEFAULT_COPP_TOPOLOGY);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM open %d\n",
- __func__, rc, port_id[1]);
-
- goto fail_cmd;
- }
-
- rc = adm_matrix_map(popp_id, ADM_PATH_LIVE_REC, 1,
- &port_id[1], port_id[1]);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM matrix map %d\n",
- __func__, rc, port_id[1]);
-
- goto fail_cmd;
- }
-
- msm_set_copp_id(popp_id, port_id[1]);
-
- } else if (rec_mode == VOC_REC_BOTH) {
- rc = afe_start_pseudo_port(port_id[0]);
- if (rc < 0) {
- pr_err("%s: Error %d in Tx pseudo port start\n",
- __func__, rc);
-
- goto fail_cmd;
- }
-
- rc = adm_open(port_id[0], ADM_PATH_LIVE_REC, rate, channel_mode,
- DEFAULT_COPP_TOPOLOGY);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM open %d\n",
- __func__, rc, port_id[0]);
-
- goto fail_cmd;
- }
-
- msm_set_copp_id(popp_id, port_id[0]);
-
- rc = afe_start_pseudo_port(port_id[1]);
- if (rc < 0) {
- pr_err("%s: Error %d in Rx pseudo port start\n",
- __func__, rc);
-
- goto fail_cmd;
- }
-
- rc = adm_open(port_id[1], ADM_PATH_LIVE_REC, rate, channel_mode,
- DEFAULT_COPP_TOPOLOGY);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM open %d\n",
- __func__, rc, port_id[0]);
-
- goto fail_cmd;
- }
-
- rc = adm_matrix_map(popp_id, ADM_PATH_LIVE_REC, 2,
- &port_id[0], port_id[1]);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM matrix map\n",
- __func__, rc);
-
- goto fail_cmd;
- }
-
- msm_set_copp_id(popp_id, port_id[1]);
- } else {
- pr_err("%s Unknown rec_mode %d\n", __func__, rec_mode);
-
- goto fail_cmd;
- }
-
- rc = voice_start_record(rec_mode, 1);
-
-fail_cmd:
- mutex_unlock(&routing_info.adm_mutex);
- return rc;
-}
-
-int msm_disable_incall_recording(uint32_t popp_id, uint32_t rec_mode)
-{
- int rc = 0;
- uint32_t port_id[2];
- port_id[0] = VOICE_RECORD_TX;
- port_id[1] = VOICE_RECORD_RX;
-
- pr_debug("%s: popp_id %d, rec_mode %d\n", __func__, popp_id, rec_mode);
-
- mutex_lock(&routing_info.adm_mutex);
-
- rc = voice_start_record(rec_mode, 0);
- if (rc < 0) {
- pr_err("%s: Error %d stopping record\n", __func__, rc);
-
- goto fail_cmd;
- }
-
- if (rec_mode == VOC_REC_UPLINK) {
- rc = adm_close(port_id[0]);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM close %d\n",
- __func__, rc, port_id[0]);
-
- goto fail_cmd;
- }
-
- msm_clear_copp_id(popp_id, port_id[0]);
-
- rc = afe_stop_pseudo_port(port_id[0]);
- if (rc < 0) {
- pr_err("%s: Error %d in Tx pseudo port stop\n",
- __func__, rc);
- goto fail_cmd;
- }
-
- } else if (rec_mode == VOC_REC_DOWNLINK) {
- rc = adm_close(port_id[1]);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM close %d\n",
- __func__, rc, port_id[1]);
-
- goto fail_cmd;
- }
-
- msm_clear_copp_id(popp_id, port_id[1]);
-
- rc = afe_stop_pseudo_port(port_id[1]);
- if (rc < 0) {
- pr_err("%s: Error %d in Rx pseudo port stop\n",
- __func__, rc);
- goto fail_cmd;
- }
- } else if (rec_mode == VOC_REC_BOTH) {
- rc = adm_close(port_id[0]);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM close %d\n",
- __func__, rc, port_id[0]);
-
- goto fail_cmd;
- }
-
- msm_clear_copp_id(popp_id, port_id[0]);
-
- rc = afe_stop_pseudo_port(port_id[0]);
- if (rc < 0) {
- pr_err("%s: Error %d in Tx pseudo port stop\n",
- __func__, rc);
- goto fail_cmd;
- }
-
- rc = adm_close(port_id[1]);
- if (rc < 0) {
- pr_err("%s: Error %d in ADM close %d\n",
- __func__, rc, port_id[1]);
-
- goto fail_cmd;
- }
-
- msm_clear_copp_id(popp_id, port_id[1]);
-
- rc = afe_stop_pseudo_port(port_id[1]);
- if (rc < 0) {
- pr_err("%s: Error %d in Rx pseudo port stop\n",
- __func__, rc);
- goto fail_cmd;
- }
- } else {
- pr_err("%s Unknown rec_mode %d\n", __func__, rec_mode);
-
- goto fail_cmd;
- }
-
-fail_cmd:
- mutex_unlock(&routing_info.adm_mutex);
- return rc;
-}
-
-static long audio_dev_ctrl_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int rc = 0;
- struct audio_dev_ctrl_state *dev_ctrl = file->private_data;
-
- mutex_lock(&session_lock);
- switch (cmd) {
- case AUDIO_GET_NUM_SND_DEVICE:
- rc = put_user(dev_ctrl->num_dev, (uint32_t __user *) arg);
- break;
- case AUDIO_GET_SND_DEVICES:
- rc = audio_dev_ctrl_get_devices(dev_ctrl, (void __user *) arg);
- break;
- case AUDIO_ENABLE_SND_DEVICE: {
- struct msm_snddev_info *dev_info;
- u32 dev_id;
-
- if (get_user(dev_id, (u32 __user *) arg)) {
- rc = -EFAULT;
- break;
- }
- dev_info = audio_dev_ctrl_find_dev(dev_id);
- if (IS_ERR(dev_info))
- rc = PTR_ERR(dev_info);
- else {
- rc = dev_info->dev_ops.open(dev_info);
- if (!rc)
- dev_info->opened = 1;
- wake_up(&audio_dev_ctrl.wait);
- }
- break;
-
- }
-
- case AUDIO_DISABLE_SND_DEVICE: {
- struct msm_snddev_info *dev_info;
- u32 dev_id;
-
- if (get_user(dev_id, (u32 __user *) arg)) {
- rc = -EFAULT;
- break;
- }
- dev_info = audio_dev_ctrl_find_dev(dev_id);
- if (IS_ERR(dev_info))
- rc = PTR_ERR(dev_info);
- else {
- rc = dev_info->dev_ops.close(dev_info);
- dev_info->opened = 0;
- }
- break;
- }
-
- case AUDIO_ROUTE_STREAM: {
- struct msm_audio_route_config route_cfg;
- struct msm_snddev_info *dev_info;
-
- if (copy_from_user(&route_cfg, (void __user *) arg,
- sizeof(struct msm_audio_route_config))) {
- rc = -EFAULT;
- break;
- }
- pr_debug("%s: route cfg %d %d type\n", __func__,
- route_cfg.dev_id, route_cfg.stream_type);
- dev_info = audio_dev_ctrl_find_dev(route_cfg.dev_id);
- if (IS_ERR(dev_info)) {
- pr_err("%s: pass invalid dev_id\n", __func__);
- rc = PTR_ERR(dev_info);
- break;
- }
-
- switch (route_cfg.stream_type) {
-
- case AUDIO_ROUTE_STREAM_VOICE_RX:
- if (!(dev_info->capability & SNDDEV_CAP_RX) |
- !(dev_info->capability & SNDDEV_CAP_VOICE)) {
- rc = -EINVAL;
- break;
- }
- dev_ctrl->voice_rx_dev = dev_info;
- break;
- case AUDIO_ROUTE_STREAM_VOICE_TX:
- if (!(dev_info->capability & SNDDEV_CAP_TX) |
- !(dev_info->capability & SNDDEV_CAP_VOICE)) {
- rc = -EINVAL;
- break;
- }
- dev_ctrl->voice_tx_dev = dev_info;
- break;
- }
- break;
- }
-
- default:
- rc = -EINVAL;
- }
- mutex_unlock(&session_lock);
- return rc;
-}
-
-static int audio_dev_ctrl_open(struct inode *inode, struct file *file)
-{
- pr_debug("open audio_dev_ctrl\n");
- atomic_inc(&audio_dev_ctrl.opened);
- file->private_data = &audio_dev_ctrl;
- return 0;
-}
-
-static int audio_dev_ctrl_release(struct inode *inode, struct file *file)
-{
- pr_debug("release audio_dev_ctrl\n");
- atomic_dec(&audio_dev_ctrl.opened);
- return 0;
-}
-
-static const struct file_operations audio_dev_ctrl_fops = {
- .owner = THIS_MODULE,
- .open = audio_dev_ctrl_open,
- .release = audio_dev_ctrl_release,
- .unlocked_ioctl = audio_dev_ctrl_ioctl,
-};
-
-
-struct miscdevice audio_dev_ctrl_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_audio_dev_ctrl",
- .fops = &audio_dev_ctrl_fops,
-};
-
-/* session id is 64 bit routing mask per device
- * 0-15 for voice clients
- * 16-31 for Decoder clients
- * 32-47 for Encoder clients
- * 48-63 Do not care
- */
-void broadcast_event(u32 evt_id, u32 dev_id, u64 session_id)
-{
- int clnt_id = 0, i;
- union auddev_evt_data *evt_payload;
- struct msm_snd_evt_listner *callback;
- struct msm_snddev_info *dev_info = NULL;
- u64 session_mask = 0;
- static int pending_sent;
-
- pr_debug(": evt_id = %d\n", evt_id);
-
- if ((evt_id != AUDDEV_EVT_START_VOICE)
- && (evt_id != AUDDEV_EVT_END_VOICE)
- && (evt_id != AUDDEV_EVT_STREAM_VOL_CHG)
- && (evt_id != AUDDEV_EVT_VOICE_STATE_CHG)) {
- dev_info = audio_dev_ctrl_find_dev(dev_id);
- if (IS_ERR(dev_info)) {
- pr_err("%s: pass invalid dev_id(%d)\n",
- __func__, dev_id);
- return;
- }
- }
-
- if (event.cb != NULL)
- callback = event.cb;
- else
- return;
- mutex_lock(&session_lock);
-
- if (evt_id == AUDDEV_EVT_VOICE_STATE_CHG)
- routing_info.voice_state = dev_id;
-
- evt_payload = kzalloc(sizeof(union auddev_evt_data),
- GFP_KERNEL);
-
- if (evt_payload == NULL) {
- pr_err("broadcast_event: cannot allocate memory\n");
- mutex_unlock(&session_lock);
- return;
- }
- for (; ;) {
- if (!(evt_id & callback->evt_id)) {
- if (callback->cb_next == NULL)
- break;
- else {
- callback = callback->cb_next;
- continue;
- }
- }
- clnt_id = callback->clnt_id;
- memset(evt_payload, 0, sizeof(union auddev_evt_data));
-
- if ((evt_id == AUDDEV_EVT_START_VOICE)
- || (evt_id == AUDDEV_EVT_END_VOICE)
- || evt_id == AUDDEV_EVT_DEVICE_VOL_MUTE_CHG)
- goto skip_check;
- if (callback->clnt_type == AUDDEV_CLNT_AUDIOCAL)
- goto aud_cal;
-
- session_mask = (((u64)0x1) << clnt_id)
- << (MAX_BIT_PER_CLIENT * \
- ((int)callback->clnt_type-1));
-
- if ((evt_id == AUDDEV_EVT_STREAM_VOL_CHG) || \
- (evt_id == AUDDEV_EVT_VOICE_STATE_CHG)) {
- pr_debug("AUDDEV_EVT_STREAM_VOL_CHG or\
- AUDDEV_EVT_VOICE_STATE_CHG\n");
- goto volume_strm;
- }
-
- pr_debug("dev_info->sessions = %llu\n", dev_info->sessions);
-
- if ((!session_id && !(dev_info->sessions & session_mask)) ||
- (session_id && ((dev_info->sessions & session_mask) !=
- session_id))) {
- if (callback->cb_next == NULL)
- break;
- else {
- callback = callback->cb_next;
- continue;
- }
- }
- if (evt_id == AUDDEV_EVT_DEV_CHG_VOICE)
- goto voc_events;
-
-volume_strm:
- if (callback->clnt_type == AUDDEV_CLNT_DEC) {
- pr_debug("AUDDEV_CLNT_DEC\n");
- if (evt_id == AUDDEV_EVT_STREAM_VOL_CHG) {
- pr_debug("clnt_id = %d, session_id = %llu\n",
- clnt_id, session_id);
- if (session_mask != session_id)
- goto sent_dec;
- else
- evt_payload->session_vol =
- msm_vol_ctl.volume;
- } else if (evt_id == AUDDEV_EVT_FREQ_CHG) {
- if (routing_info.dec_freq[clnt_id].evt) {
- routing_info.dec_freq[clnt_id].evt
- = 0;
- goto sent_dec;
- } else if (routing_info.dec_freq[clnt_id].freq
- == dev_info->set_sample_rate)
- goto sent_dec;
- else {
- evt_payload->freq_info.sample_rate
- = dev_info->set_sample_rate;
- evt_payload->freq_info.dev_type
- = dev_info->capability;
- evt_payload->freq_info.acdb_dev_id
- = dev_info->acdb_id;
- }
- } else if (evt_id == AUDDEV_EVT_VOICE_STATE_CHG)
- evt_payload->voice_state =
- routing_info.voice_state;
- else
- evt_payload->routing_id = dev_info->copp_id;
- callback->auddev_evt_listener(
- evt_id,
- evt_payload,
- callback->private_data);
-sent_dec:
- if ((evt_id != AUDDEV_EVT_STREAM_VOL_CHG) &&
- (evt_id != AUDDEV_EVT_VOICE_STATE_CHG))
- routing_info.dec_freq[clnt_id].freq
- = dev_info->set_sample_rate;
-
- if (callback->cb_next == NULL)
- break;
- else {
- callback = callback->cb_next;
- continue;
- }
- }
- if (callback->clnt_type == AUDDEV_CLNT_ENC) {
- pr_debug("AUDDEV_CLNT_ENC\n");
- if (evt_id == AUDDEV_EVT_FREQ_CHG) {
- if (routing_info.enc_freq[clnt_id].evt) {
- routing_info.enc_freq[clnt_id].evt
- = 0;
- goto sent_enc;
- } else {
- evt_payload->freq_info.sample_rate
- = dev_info->set_sample_rate;
- evt_payload->freq_info.dev_type
- = dev_info->capability;
- evt_payload->freq_info.acdb_dev_id
- = dev_info->acdb_id;
- }
- } else if (evt_id == AUDDEV_EVT_VOICE_STATE_CHG)
- evt_payload->voice_state =
- routing_info.voice_state;
- else
- evt_payload->routing_id = dev_info->copp_id;
- callback->auddev_evt_listener(
- evt_id,
- evt_payload,
- callback->private_data);
-sent_enc:
- if (callback->cb_next == NULL)
- break;
- else {
- callback = callback->cb_next;
- continue;
- }
- }
-aud_cal:
- if (callback->clnt_type == AUDDEV_CLNT_AUDIOCAL) {
- pr_debug("AUDDEV_CLNT_AUDIOCAL\n");
- if (evt_id == AUDDEV_EVT_VOICE_STATE_CHG)
- evt_payload->voice_state =
- routing_info.voice_state;
- else if (!dev_info->sessions)
- goto sent_aud_cal;
- else {
- evt_payload->audcal_info.dev_id =
- dev_info->copp_id;
- evt_payload->audcal_info.acdb_id =
- dev_info->acdb_id;
- evt_payload->audcal_info.dev_type =
- (dev_info->capability & SNDDEV_CAP_TX) ?
- SNDDEV_CAP_TX : SNDDEV_CAP_RX;
- evt_payload->audcal_info.sample_rate =
- dev_info->set_sample_rate ?
- dev_info->set_sample_rate :
- dev_info->sample_rate;
- }
- callback->auddev_evt_listener(
- evt_id,
- evt_payload,
- callback->private_data);
-
-sent_aud_cal:
- if (callback->cb_next == NULL)
- break;
- else {
- callback = callback->cb_next;
- continue;
- }
- }
-skip_check:
-voc_events:
- if (callback->clnt_type == AUDDEV_CLNT_VOC) {
- pr_debug("AUDDEV_CLNT_VOC\n");
- if (evt_id == AUDDEV_EVT_DEV_RLS) {
- if (!pending_sent)
- goto sent_voc;
- else
- pending_sent = 0;
- }
- if (evt_id == AUDDEV_EVT_REL_PENDING)
- pending_sent = 1;
-
- if (evt_id == AUDDEV_EVT_DEVICE_VOL_MUTE_CHG) {
- evt_payload->voc_vm_info.voice_session_id =
- session_id;
-
- if (dev_info->capability & SNDDEV_CAP_TX) {
- evt_payload->voc_vm_info.dev_type =
- SNDDEV_CAP_TX;
- evt_payload->voc_vm_info.acdb_dev_id =
- dev_info->acdb_id;
- evt_payload->
- voc_vm_info.dev_vm_val.mute =
- routing_info.tx_mute;
- } else {
- evt_payload->voc_vm_info.dev_type =
- SNDDEV_CAP_RX;
- evt_payload->voc_vm_info.acdb_dev_id =
- dev_info->acdb_id;
- evt_payload->
- voc_vm_info.dev_vm_val.vol =
- routing_info.voice_rx_vol;
- }
- } else if ((evt_id == AUDDEV_EVT_START_VOICE)
- || (evt_id == AUDDEV_EVT_END_VOICE)) {
- memset(evt_payload, 0,
- sizeof(union auddev_evt_data));
-
- evt_payload->voice_session_id = session_id;
- } else if (evt_id == AUDDEV_EVT_FREQ_CHG) {
- if (routing_info.voice_tx_sample_rate
- != dev_info->set_sample_rate) {
- routing_info.voice_tx_sample_rate
- = dev_info->set_sample_rate;
- evt_payload->freq_info.sample_rate
- = dev_info->set_sample_rate;
- evt_payload->freq_info.dev_type
- = dev_info->capability;
- evt_payload->freq_info.acdb_dev_id
- = dev_info->acdb_id;
- } else
- goto sent_voc;
- } else if (evt_id == AUDDEV_EVT_VOICE_STATE_CHG)
- evt_payload->voice_state =
- routing_info.voice_state;
- else {
- evt_payload->voc_devinfo.dev_type =
- (dev_info->capability & SNDDEV_CAP_TX) ?
- SNDDEV_CAP_TX : SNDDEV_CAP_RX;
- evt_payload->voc_devinfo.acdb_dev_id =
- dev_info->acdb_id;
- evt_payload->voc_devinfo.dev_port_id =
- dev_info->copp_id;
- evt_payload->voc_devinfo.dev_sample =
- dev_info->set_sample_rate ?
- dev_info->set_sample_rate :
- dev_info->sample_rate;
- evt_payload->voc_devinfo.dev_id = dev_id;
- if (dev_info->capability & SNDDEV_CAP_RX) {
- for (i = 0; i < VOC_RX_VOL_ARRAY_NUM;
- i++) {
- evt_payload->
- voc_devinfo.max_rx_vol[i] =
- dev_info->max_voc_rx_vol[i];
- evt_payload
- ->voc_devinfo.min_rx_vol[i] =
- dev_info->min_voc_rx_vol[i];
- }
- }
- }
- callback->auddev_evt_listener(
- evt_id,
- evt_payload,
- callback->private_data);
- if (evt_id == AUDDEV_EVT_DEV_RLS)
- dev_info->sessions &= ~(0xFFFF);
-sent_voc:
- if (callback->cb_next == NULL)
- break;
- else {
- callback = callback->cb_next;
- continue;
- }
- }
- }
- kfree(evt_payload);
- mutex_unlock(&session_lock);
-}
-EXPORT_SYMBOL(broadcast_event);
-
-
-void mixer_post_event(u32 evt_id, u32 id)
-{
-
- pr_debug("evt_id = %d\n", evt_id);
- switch (evt_id) {
- case AUDDEV_EVT_DEV_CHG_VOICE: /* Called from Voice_route */
- broadcast_event(AUDDEV_EVT_DEV_CHG_VOICE, id, SESSION_IGNORE);
- break;
- case AUDDEV_EVT_DEV_RDY:
- broadcast_event(AUDDEV_EVT_DEV_RDY, id, SESSION_IGNORE);
- break;
- case AUDDEV_EVT_DEV_RLS:
- broadcast_event(AUDDEV_EVT_DEV_RLS, id, SESSION_IGNORE);
- break;
- case AUDDEV_EVT_REL_PENDING:
- broadcast_event(AUDDEV_EVT_REL_PENDING, id, SESSION_IGNORE);
- break;
- case AUDDEV_EVT_DEVICE_VOL_MUTE_CHG:
- broadcast_event(AUDDEV_EVT_DEVICE_VOL_MUTE_CHG, id,
- SESSION_IGNORE);
- break;
- case AUDDEV_EVT_STREAM_VOL_CHG:
- broadcast_event(AUDDEV_EVT_STREAM_VOL_CHG, id,
- SESSION_IGNORE);
- break;
- case AUDDEV_EVT_START_VOICE:
- broadcast_event(AUDDEV_EVT_START_VOICE,
- id, SESSION_IGNORE);
- break;
- case AUDDEV_EVT_END_VOICE:
- broadcast_event(AUDDEV_EVT_END_VOICE,
- id, SESSION_IGNORE);
- break;
- case AUDDEV_EVT_FREQ_CHG:
- broadcast_event(AUDDEV_EVT_FREQ_CHG, id, SESSION_IGNORE);
- break;
- default:
- break;
- }
-}
-EXPORT_SYMBOL(mixer_post_event);
-
-static int __init audio_dev_ctrl_init(void)
-{
- init_waitqueue_head(&audio_dev_ctrl.wait);
-
- event.cb = NULL;
- msm_reset_device_work_queue = create_workqueue("reset_device");
- if (msm_reset_device_work_queue == NULL)
- return -ENOMEM;
- atomic_set(&audio_dev_ctrl.opened, 0);
- audio_dev_ctrl.num_dev = 0;
- audio_dev_ctrl.voice_tx_dev = NULL;
- audio_dev_ctrl.voice_rx_dev = NULL;
- routing_info.voice_state = VOICE_STATE_INVALID;
-
- mutex_init(&adm_tx_topology_tbl.lock);
- mutex_init(&routing_info.copp_list_mutex);
- mutex_init(&routing_info.adm_mutex);
-
- memset(routing_info.copp_list, COPP_IGNORE,
- (sizeof(unsigned int) * MAX_SESSIONS * AFE_MAX_PORTS));
- return misc_register(&audio_dev_ctrl_misc);
-}
-
-static void __exit audio_dev_ctrl_exit(void)
-{
- destroy_workqueue(msm_reset_device_work_queue);
-}
-module_init(audio_dev_ctrl_init);
-module_exit(audio_dev_ctrl_exit);
-
-MODULE_DESCRIPTION("MSM 8K Audio Device Control driver");
-MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_utils.c b/arch/arm/mach-msm/qdsp6v2/audio_utils.c
index ccacd3e..2f1ff3e 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_utils.c
+++ b/arch/arm/mach-msm/qdsp6v2/audio_utils.c
@@ -393,7 +393,7 @@
uint32_t mfield_size = (audio->buf_cfg.meta_info_enable == 0) ? 0 :
(sizeof(unsigned char) +
(sizeof(struct meta_out_dsp)*(audio->buf_cfg.frames_per_buf)));
-
+ memset(&meta, 0, sizeof(meta));
pr_debug("%s:session id %d: read - %d\n", __func__, audio->ac->session,
count);
if (!audio->enabled)
diff --git a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
index 5fa7b1b..5bdd10a 100644
--- a/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
+++ b/arch/arm/mach-msm/qdsp6v2/audio_utils_aio.c
@@ -1199,6 +1199,7 @@
case AUDIO_GET_STATS: {
struct msm_audio_stats stats;
uint64_t timestamp;
+ memset(&stats, 0, sizeof(struct msm_audio_stats));
stats.byte_count = atomic_read(&audio->in_bytes);
stats.sample_count = atomic_read(&audio->in_samples);
rc = q6asm_get_session_time(audio->ac, ×tamp);
diff --git a/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c b/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c
deleted file mode 100644
index c6def46..0000000
--- a/arch/arm/mach-msm/qdsp6v2/lpa_if_hdmi.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define pr_fmt(fmt) "%s: " fmt, __func__
-
-#include <linux/fs.h>
-#include <linux/module.h>
-#include <linux/miscdevice.h>
-#include <linux/mutex.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/uaccess.h>
-#include <linux/dma-mapping.h>
-#include <linux/msm_audio.h>
-#include <mach/msm_hdmi_audio.h>
-#include <mach/audio_dma_msm8k.h>
-#include <sound/dai.h>
-#include <mach/qdsp6v2/q6core.h>
-
-#define DMA_ALLOC_BUF_SZ (SZ_4K * 16)
-
-#define HDMI_AUDIO_FIFO_WATER_MARK 4
-
-struct audio_buffer {
- dma_addr_t phys;
- void *data;
- uint32_t size;
- uint32_t used; /* 1 = CPU is waiting for DMA to consume this buf */
- uint32_t actual_size; /* actual number of bytes read by DMA */
-};
-
-struct lpa_if {
- struct mutex lock;
- struct msm_audio_config cfg;
- struct audio_buffer audio_buf[6];
- int cpu_buf; /* next buffer the CPU will touch */
- int dma_buf; /* next buffer the DMA will touch */
- u8 *buffer;
- dma_addr_t buffer_phys;
- u32 dma_ch;
- wait_queue_head_t wait;
- u32 config;
- u32 dma_period_sz;
- unsigned int num_periods;
-};
-
-static struct lpa_if *lpa_if_ptr;
-
-static unsigned int dma_buf_index;
-
-static irqreturn_t lpa_if_irq(int intrsrc, void *data)
-{
- struct lpa_if *lpa_if = data;
- int dma_ch = 0;
- unsigned int pending;
-
- if (lpa_if)
- dma_ch = lpa_if->dma_ch;
- else {
- pr_err("invalid lpa_if\n");
- return IRQ_NONE;
- }
-
- pending = (intrsrc
- & (UNDER_CH(dma_ch) | PER_CH(dma_ch) | ERR_CH(dma_ch)));
-
- if (pending & UNDER_CH(dma_ch))
- pr_err("under run\n");
- if (pending & ERR_CH(dma_ch))
- pr_err("DMA %x Master Error\n", dma_ch);
-
- if (pending & PER_CH(dma_ch)) {
-
- lpa_if->audio_buf[lpa_if->dma_buf].used = 0;
-
- pr_debug("dma_buf %d used %d\n", lpa_if->dma_buf,
- lpa_if->audio_buf[lpa_if->dma_buf].used);
- lpa_if->dma_buf++;
- lpa_if->dma_buf = lpa_if->dma_buf % lpa_if->cfg.buffer_count;
-
- if (lpa_if->dma_buf == lpa_if->cpu_buf)
- pr_err("Err:both dma_buf and cpu_buf are on same index\n");
- wake_up(&lpa_if->wait);
- }
- return IRQ_HANDLED;
-}
-
-
-int lpa_if_start(struct lpa_if *lpa_if)
-{
- pr_debug("buf1 0x%x, buf2 0x%x dma_ch %d\n",
- (unsigned int)lpa_if->audio_buf[0].data,
- (unsigned int)lpa_if->audio_buf[1].data, lpa_if->dma_ch);
-
- dai_start_hdmi(lpa_if->dma_ch);
-
- hdmi_audio_enable(1, HDMI_AUDIO_FIFO_WATER_MARK);
-
- hdmi_audio_packet_enable(1);
- return 0;
-}
-
-int lpa_if_config(struct lpa_if *lpa_if)
-{
- struct dai_dma_params dma_params;
-
- dma_params.src_start = lpa_if->buffer_phys;
- dma_params.buffer = lpa_if->buffer;
- dma_params.buffer_size = lpa_if->dma_period_sz * lpa_if->num_periods;
- dma_params.period_size = lpa_if->dma_period_sz;
- dma_params.channels = 2;
-
- lpa_if->dma_ch = 4;
- dai_set_params(lpa_if->dma_ch, &dma_params);
-
- register_dma_irq_handler(lpa_if->dma_ch, lpa_if_irq, (void *)lpa_if);
-
- mb();
- pr_debug("lpa_if 0x%08x buf_vir 0x%08x buf_phys 0x%08x "
- "config %u\n", (u32)lpa_if, (u32) (lpa_if->buffer),
- lpa_if->buffer_phys, lpa_if->config);
-
- pr_debug("user_buf_cnt %u user_buf_size %u\n",
- lpa_if->cfg.buffer_count, lpa_if->cfg.buffer_size);
-
- lpa_if->config = 1;
-
- lpa_if_start(lpa_if);
-
- return 0;
-}
-
-
-static long lpa_if_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- struct lpa_if *lpa_if = file->private_data;
- int rc = 0;
- unsigned int i;
- pr_debug("cmd %u\n", cmd);
-
- mutex_lock(&lpa_if->lock);
-
- switch (cmd) {
- case AUDIO_START:
- pr_debug("AUDIO_START\n");
-
- if (dma_buf_index == 2) {
- if (!lpa_if->config) {
- rc = lpa_if_config(lpa_if);
- if (rc)
- pr_err("lpa_if_config failed\n");
- }
- } else {
- pr_err("did not receved two buffer for "
- "AUDIO_STAR\n");
- rc = -EPERM;
- }
- break;
-
- case AUDIO_STOP:
- pr_debug("AUDIO_STOP\n");
- break;
-
- case AUDIO_FLUSH:
- pr_debug("AUDIO_FLUSH\n");
- break;
-
-
- case AUDIO_GET_CONFIG:
- pr_debug("AUDIO_GET_CONFIG\n");
- if (copy_to_user((void *)arg, &lpa_if->cfg,
- sizeof(struct msm_audio_config))) {
- rc = -EFAULT;
- }
- break;
- case AUDIO_SET_CONFIG: {
- /* Setting default rate as 48khz */
- unsigned int cur_sample_rate =
- HDMI_SAMPLE_RATE_48KHZ;
- struct msm_audio_config config;
-
- pr_debug("AUDIO_SET_CONFIG\n");
- if (copy_from_user(&config, (void *)arg, sizeof(config))) {
- rc = -EFAULT;
- break;
- }
- lpa_if->dma_period_sz = config.buffer_size;
- if ((lpa_if->dma_period_sz * lpa_if->num_periods) >
- DMA_ALLOC_BUF_SZ) {
- pr_err("Dma buffer size greater than allocated size\n");
- return -EINVAL;
- }
- pr_debug("Dma_period_sz %d\n", lpa_if->dma_period_sz);
- if (lpa_if->dma_period_sz < (2 * SZ_4K))
- lpa_if->num_periods = 6;
- pr_debug("No. of Periods %d\n", lpa_if->num_periods);
-
- lpa_if->cfg.buffer_count = lpa_if->num_periods;
- lpa_if->cfg.buffer_size = lpa_if->dma_period_sz *
- lpa_if->num_periods;
-
- for (i = 0; i < lpa_if->cfg.buffer_count; i++) {
- lpa_if->audio_buf[i].phys =
- lpa_if->buffer_phys + i * lpa_if->dma_period_sz;
- lpa_if->audio_buf[i].data =
- lpa_if->buffer + i * lpa_if->dma_period_sz;
- lpa_if->audio_buf[i].size = lpa_if->dma_period_sz;
- lpa_if->audio_buf[i].used = 0;
- }
-
- pr_debug("Sample rate %d\n", config.sample_rate);
- switch (config.sample_rate) {
- case 48000:
- cur_sample_rate = HDMI_SAMPLE_RATE_48KHZ;
- break;
- case 44100:
- cur_sample_rate = HDMI_SAMPLE_RATE_44_1KHZ;
- break;
- case 32000:
- cur_sample_rate = HDMI_SAMPLE_RATE_32KHZ;
- break;
- case 88200:
- cur_sample_rate = HDMI_SAMPLE_RATE_88_2KHZ;
- break;
- case 96000:
- cur_sample_rate = HDMI_SAMPLE_RATE_96KHZ;
- break;
- case 176400:
- cur_sample_rate = HDMI_SAMPLE_RATE_176_4KHZ;
- break;
- case 192000:
- cur_sample_rate = HDMI_SAMPLE_RATE_192KHZ;
- break;
- default:
- cur_sample_rate = HDMI_SAMPLE_RATE_48KHZ;
- }
- if (cur_sample_rate != hdmi_msm_audio_get_sample_rate())
- hdmi_msm_audio_sample_rate_reset(cur_sample_rate);
- else
- pr_debug("Previous sample rate and current"
- "sample rate are same\n");
- break;
- }
- default:
- pr_err("UnKnown Ioctl\n");
- rc = -EINVAL;
- }
-
- mutex_unlock(&lpa_if->lock);
-
- return rc;
-}
-
-
-static int lpa_if_open(struct inode *inode, struct file *file)
-{
- pr_debug("\n");
-
- file->private_data = lpa_if_ptr;
- dma_buf_index = 0;
- lpa_if_ptr->cpu_buf = 2;
- lpa_if_ptr->dma_buf = 0;
- lpa_if_ptr->num_periods = 4;
-
- core_req_bus_bandwith(AUDIO_IF_BUS_ID, 100000, 0);
- mb();
-
- return 0;
-}
-
-static inline int rt_policy(int policy)
-{
- if (unlikely(policy == SCHED_FIFO) || unlikely(policy == SCHED_RR))
- return 1;
- return 0;
-}
-
-static inline int task_has_rt_policy(struct task_struct *p)
-{
- return rt_policy(p->policy);
-}
-static ssize_t lpa_if_write(struct file *file, const char __user *buf,
- size_t count, loff_t *pos)
-{
- struct lpa_if *lpa_if = file->private_data;
- struct audio_buffer *ab;
- const char __user *start = buf;
- int xfer, rc;
- struct sched_param s = { .sched_priority = 1 };
- int old_prio = current->rt_priority;
- int old_policy = current->policy;
- int cap_nice = cap_raised(current_cap(), CAP_SYS_NICE);
-
- /* just for this write, set us real-time */
- if (!task_has_rt_policy(current)) {
- struct cred *new = prepare_creds();
- cap_raise(new->cap_effective, CAP_SYS_NICE);
- commit_creds(new);
- if ((sched_setscheduler(current, SCHED_RR, &s)) < 0)
- pr_err("sched_setscheduler failed\n");
- }
- mutex_lock(&lpa_if->lock);
-
- if (dma_buf_index < 2) {
-
- ab = lpa_if->audio_buf + dma_buf_index;
-
- if (copy_from_user(ab->data, buf, count)) {
- pr_err("copy from user failed\n");
- rc = 0;
- goto end;
-
- }
- mb();
- pr_debug("prefill: count %u audio_buf[%u].size %u\n",
- count, dma_buf_index, ab->size);
-
- ab->used = 1;
- dma_buf_index++;
- rc = count;
- goto end;
- }
-
- if (lpa_if->config != 1) {
- pr_err("AUDIO_START did not happen\n");
- rc = 0;
- goto end;
- }
-
- while (count > 0) {
-
- ab = lpa_if->audio_buf + lpa_if->cpu_buf;
-
- rc = wait_event_timeout(lpa_if->wait, (ab->used == 0), 10 * HZ);
- if (!rc) {
- pr_err("wait_event_timeout failed\n");
- rc = buf - start;
- goto end;
- }
-
- xfer = count;
-
- if (xfer > lpa_if->dma_period_sz)
- xfer = lpa_if->dma_period_sz;
-
- if (copy_from_user(ab->data, buf, xfer)) {
- pr_err("copy from user failed\n");
- rc = buf - start;
- goto end;
- }
-
- mb();
- buf += xfer;
- count -= xfer;
- ab->used = 1;
-
- pr_debug("xfer %d, size %d, used %d cpu_buf %d\n",
- xfer, ab->size, ab->used, lpa_if->cpu_buf);
- lpa_if->cpu_buf++;
- lpa_if->cpu_buf = lpa_if->cpu_buf % lpa_if->cfg.buffer_count;
- }
- rc = buf - start;
-end:
- mutex_unlock(&lpa_if->lock);
- /* restore old scheduling policy */
- if (!rt_policy(old_policy)) {
- struct sched_param v = { .sched_priority = old_prio };
- if ((sched_setscheduler(current, old_policy, &v)) < 0)
- pr_err("sched_setscheduler failed\n");
- if (likely(!cap_nice)) {
- struct cred *new = prepare_creds();
- cap_lower(new->cap_effective, CAP_SYS_NICE);
- commit_creds(new);
- }
- }
- return rc;
-}
-
-static int lpa_if_release(struct inode *inode, struct file *file)
-{
- struct lpa_if *lpa_if = file->private_data;
-
- hdmi_audio_packet_enable(0);
-
- wait_for_dma_cnt_stop(lpa_if->dma_ch);
-
- hdmi_audio_enable(0, HDMI_AUDIO_FIFO_WATER_MARK);
-
- if (lpa_if->config) {
- unregister_dma_irq_handler(lpa_if->dma_ch);
- dai_stop_hdmi(lpa_if->dma_ch);
- lpa_if->config = 0;
- }
- core_req_bus_bandwith(AUDIO_IF_BUS_ID, 0, 0);
-
- if (hdmi_msm_audio_get_sample_rate() != HDMI_SAMPLE_RATE_48KHZ)
- hdmi_msm_audio_sample_rate_reset(HDMI_SAMPLE_RATE_48KHZ);
-
- return 0;
-}
-
-static const struct file_operations lpa_if_fops = {
- .owner = THIS_MODULE,
- .open = lpa_if_open,
- .write = lpa_if_write,
- .release = lpa_if_release,
- .unlocked_ioctl = lpa_if_ioctl,
-};
-
-struct miscdevice lpa_if_misc = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "msm_lpa_if_out",
- .fops = &lpa_if_fops,
-};
-
-static int __init lpa_if_init(void)
-{
- int rc;
-
- lpa_if_ptr = kzalloc(sizeof(struct lpa_if), GFP_KERNEL);
- if (!lpa_if_ptr) {
- pr_info("No mem for lpa-if\n");
- return -ENOMEM;
- }
-
- mutex_init(&lpa_if_ptr->lock);
- init_waitqueue_head(&lpa_if_ptr->wait);
-
- lpa_if_ptr->buffer = dma_alloc_coherent(NULL, DMA_ALLOC_BUF_SZ,
- &(lpa_if_ptr->buffer_phys), GFP_KERNEL);
- if (!lpa_if_ptr->buffer) {
- pr_err("dma_alloc_coherent failed\n");
- kfree(lpa_if_ptr);
- return -ENOMEM;
- }
-
- pr_info("lpa_if_ptr 0x%08x buf_vir 0x%08x buf_phy 0x%08x "
- " buf_zise %u\n", (u32)lpa_if_ptr,
- (u32)(lpa_if_ptr->buffer), lpa_if_ptr->buffer_phys,
- DMA_ALLOC_BUF_SZ);
-
- rc = misc_register(&lpa_if_misc);
- if (rc < 0) {
- pr_err("misc_register failed\n");
-
- dma_free_coherent(NULL, DMA_ALLOC_BUF_SZ, lpa_if_ptr->buffer,
- lpa_if_ptr->buffer_phys);
- kfree(lpa_if_ptr);
- }
- return rc;
-}
-
-device_initcall(lpa_if_init);
diff --git a/arch/arm/mach-msm/qdsp6v2/msm_audio_ion.c b/arch/arm/mach-msm/qdsp6v2/msm_audio_ion.c
index 0a50bcc..fc6de64 100644
--- a/arch/arm/mach-msm/qdsp6v2/msm_audio_ion.c
+++ b/arch/arm/mach-msm/qdsp6v2/msm_audio_ion.c
@@ -269,6 +269,7 @@
} else {
ion_phys_addr_t phys_addr;
size_t phys_len;
+ size_t va_len = 0;
pr_debug("%s: page is NULL\n", __func__);
ret = ion_phys(ab->client, ab->handle, &phys_addr, &phys_len);
@@ -282,6 +283,12 @@
vma, (unsigned int)vma->vm_start,
(unsigned int)vma->vm_end, vma->vm_pgoff,
(unsigned long int)vma->vm_page_prot);
+ va_len = vma->vm_end - vma->vm_start;
+ if ((offset > phys_len) || (va_len > phys_len-offset)) {
+ pr_err("wrong offset size %ld, lens= %d, va_len=%d\n",
+ offset, phys_len, va_len);
+ return -EINVAL;
+ }
ret = remap_pfn_range(vma, vma->vm_start,
__phys_to_pfn(phys_addr) + vma->vm_pgoff,
vma->vm_end - vma->vm_start,
@@ -321,6 +328,11 @@
ion_phys_addr_t *paddr, size_t *pa_len, void **vaddr)
{
int rc = 0;
+ if (!name || !client || !handle || !paddr || !vaddr || !pa_len) {
+ pr_err("%s: Invalid params\n", __func__);
+ rc = -EINVAL;
+ goto err;
+ }
/* client is already created for legacy and given*/
/* name should be audio_acdb_client or Audio_Dec_Client,
bufsz should be 0 and fd shouldn't be 0 as of now
@@ -331,14 +343,16 @@
if (IS_ERR_OR_NULL((void *)(*handle))) {
pr_err("%s: ion import dma buffer failed\n",
__func__);
- goto err_ion_handle;
- }
+ rc = -EINVAL;
+ goto err_destroy_client;
+ }
if (ionflag != NULL) {
rc = ion_handle_get_flags(client, *handle, ionflag);
if (rc) {
pr_err("%s: could not get flags for the handle\n",
__func__);
+ rc = -EINVAL;
goto err_ion_handle;
}
}
@@ -347,6 +361,7 @@
if (rc) {
pr_err("%s: ION Get Physical for AUDIO failed, rc = %d\n",
__func__, rc);
+ rc = -EINVAL;
goto err_ion_handle;
}
@@ -354,6 +369,7 @@
*vaddr = ion_map_kernel(client, *handle);
if (IS_ERR_OR_NULL((void *)*vaddr)) {
pr_err("%s: ION memory mapping for AUDIO failed\n", __func__);
+ rc = -EINVAL;
goto err_ion_handle;
}
@@ -364,8 +380,12 @@
err_ion_handle:
ion_free(client, *handle);
- return -EINVAL;
-
+err_destroy_client:
+ msm_audio_ion_client_destroy(client);
+ client = NULL;
+ *handle = NULL;
+err:
+ return rc;
}
int msm_audio_ion_free_legacy(struct ion_client *client,
diff --git a/arch/arm/mach-msm/qdsp6v2/pcm_in.c b/arch/arm/mach-msm/qdsp6v2/pcm_in.c
index 0db4894..cf7548d 100644
--- a/arch/arm/mach-msm/qdsp6v2/pcm_in.c
+++ b/arch/arm/mach-msm/qdsp6v2/pcm_in.c
@@ -1,7 +1,7 @@
/*
* Copyright (C) 2009 Google, Inc.
* Copyright (C) 2009 HTC Corporation
- * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -256,6 +256,7 @@
}
case AUDIO_GET_CONFIG: {
struct msm_audio_config config;
+ memset(&config, 0, sizeof(config));
config.buffer_size = pcm->buffer_size;
config.buffer_count = pcm->buffer_count;
config.sample_rate = pcm->sample_rate;
diff --git a/arch/arm/mach-msm/qdsp6v2/pcm_in_proxy.c b/arch/arm/mach-msm/qdsp6v2/pcm_in_proxy.c
index 5faee21..f7bf1ae 100644
--- a/arch/arm/mach-msm/qdsp6v2/pcm_in_proxy.c
+++ b/arch/arm/mach-msm/qdsp6v2/pcm_in_proxy.c
@@ -1,5 +1,5 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -475,6 +475,7 @@
}
case AUDIO_GET_CONFIG: {
struct msm_audio_config config;
+ memset(&config, 0, sizeof(config));
config.buffer_size = pcm->buffer_size;
config.buffer_count = pcm->buffer_count;
config.sample_rate = pcm->sample_rate;
diff --git a/arch/arm/mach-msm/qdsp6v2/ultrasound/q6usm.h b/arch/arm/mach-msm/qdsp6v2/ultrasound/q6usm.h
index bf47366..7ab4ec3 100644
--- a/arch/arm/mach-msm/qdsp6v2/ultrasound/q6usm.h
+++ b/arch/arm/mach-msm/qdsp6v2/ultrasound/q6usm.h
@@ -26,6 +26,8 @@
#define FORMAT_USPS_EPOS 0x00000000
#define FORMAT_USRAW 0x00000001
#define FORMAT_USPROX 0x00000002
+#define FORMAT_USGES_SYNC 0x00000003
+#define FORMAT_USRAW_SYNC 0x00000004
#define INVALID_FORMAT 0xffffffff
#define IN 0x000
diff --git a/arch/arm/mach-msm/qdsp6v2/ultrasound/usf.c b/arch/arm/mach-msm/qdsp6v2/ultrasound/usf.c
index 1ea213a..e6b1324 100644
--- a/arch/arm/mach-msm/qdsp6v2/ultrasound/usf.c
+++ b/arch/arm/mach-msm/qdsp6v2/ultrasound/usf.c
@@ -27,8 +27,8 @@
#include "usfcdev.h"
/* The driver version*/
-#define DRV_VERSION "1.4.2"
-#define USF_VERSION_ID 0x0142
+#define DRV_VERSION "1.5.1"
+#define USF_VERSION_ID 0x0151
/* Standard timeout in the asynchronous ops */
#define USF_TIMEOUT_JIFFIES (1*HZ) /* 1 sec */
@@ -57,6 +57,8 @@
/* Place for US detection result, received from QDSP6 */
#define APR_US_DETECT_RESULT_IND 0
+#define BITS_IN_BYTE 8
+
/* The driver states */
enum usf_state_type {
USF_IDLE_STATE,
@@ -117,6 +119,8 @@
uint16_t conflicting_event_types;
/* Bitmap of types of events from devs, conflicting with USF */
uint16_t conflicting_event_filters;
+ /* The requested side buttons bitmap */
+ uint16_t req_side_buttons_bitmap;
};
struct usf_input_dev_type {
@@ -146,6 +150,12 @@
0, /* US_INPUT_SRC_UNDEF */
};
+/* Supported buttons container */
+static const int s_button_map[] = {
+ BTN_STYLUS,
+ BTN_STYLUS2
+};
+
/* The opened devices container */
static int s_opened_devs[MAX_DEVS_NUMBER];
@@ -176,14 +186,35 @@
struct us_input_info_type *input_info,
const char *name)
{
+ int i = 0;
+ int num_side_buttons = min(ARRAY_SIZE(s_button_map),
+ sizeof(input_info->req_side_buttons_bitmap) *
+ BITS_IN_BYTE);
+ uint16_t max_side_button_bitmap = ((1 << ARRAY_SIZE(s_button_map)) - 1);
struct input_dev *in_dev = allocate_dev(ind, name);
-
if (in_dev == NULL)
return -ENOMEM;
+ if (input_info->req_side_buttons_bitmap > max_side_button_bitmap) {
+ pr_err("%s: Requested side buttons[%d] exceeds max side buttons available[%d]\n",
+ __func__,
+ input_info->req_side_buttons_bitmap,
+ max_side_button_bitmap);
+ return -EINVAL;
+ }
+
usf_info->input_ifs[ind] = in_dev;
+ usf_info->req_side_buttons_bitmap =
+ input_info->req_side_buttons_bitmap;
in_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
in_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
+
+
+ for (i = 0; i < num_side_buttons; i++)
+ if (input_info->req_side_buttons_bitmap & (1 << i))
+ in_dev->keybit[BIT_WORD(s_button_map[i])] |=
+ BIT_MASK(s_button_map[i]);
+
input_set_abs_params(in_dev, ABS_X,
input_info->tsc_x_dim[MIN_IND],
input_info->tsc_x_dim[MAX_IND],
@@ -260,6 +291,11 @@
struct usf_event_type *event)
{
+ int i = 0;
+ int num_side_buttons = min(ARRAY_SIZE(s_button_map),
+ sizeof(usf_info->req_side_buttons_bitmap) *
+ BITS_IN_BYTE);
+
struct input_dev *input_if = usf_info->input_ifs[if_ind];
struct point_event_type *pe = &(event->event_data.point_event);
@@ -273,19 +309,27 @@
input_report_abs(input_if, ABS_PRESSURE, pe->pressure);
input_report_key(input_if, BTN_TOUCH, !!(pe->pressure));
+ for (i = 0; i < num_side_buttons; i++) {
+ uint16_t mask = (1 << i),
+ btn_state = !!(pe->side_buttons_state_bitmap & mask);
+ if (usf_info->req_side_buttons_bitmap & mask)
+ input_report_key(input_if, s_button_map[i], btn_state);
+ }
+
if (usf_info->event_src)
input_report_key(input_if, usf_info->event_src, 1);
input_sync(input_if);
- pr_debug("%s: TSC event: xyz[%d;%d;%d], incl[%d;%d], pressure[%d]\n",
+ pr_debug("%s: TSC event: xyz[%d;%d;%d], incl[%d;%d], pressure[%d], side_buttons[%d]\n",
__func__,
pe->coordinates[X_IND],
pe->coordinates[Y_IND],
pe->coordinates[Z_IND],
pe->inclinations[X_IND],
pe->inclinations[Y_IND],
- pe->pressure);
+ pe->pressure,
+ pe->side_buttons_state_bitmap);
}
static void notify_mouse_event(struct usf_type *usf_info,
@@ -338,6 +382,8 @@
prepare_mouse_input_device, notify_mouse_event},
{USF_KEYBOARD_EVENT, "usf_kb",
prepare_keyboard_input_device, notify_key_event},
+ {USF_TSC_EXT_EVENT, "usf_tsc_ext",
+ prepare_tsc_input_device, notify_tsc_event},
};
static void usf_rx_cb(uint32_t opcode, uint32_t token,
diff --git a/arch/arm/mach-msm/qdsp6v2/ultrasound/usfcdev.c b/arch/arm/mach-msm/qdsp6v2/ultrasound/usfcdev.c
index 1299b96..578a6e5 100644
--- a/arch/arm/mach-msm/qdsp6v2/ultrasound/usfcdev.c
+++ b/arch/arm/mach-msm/qdsp6v2/ultrasound/usfcdev.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -24,8 +24,6 @@
#define SLOT_CMD_ID 0
#define MAX_RETRIES 10
-
-
enum usdev_event_status {
USFCDEV_EVENT_ENABLED,
USFCDEV_EVENT_DISABLING,
@@ -98,8 +96,14 @@
},
};
-/* For each event type, one conflicting device (and handle) is supported */
-static struct input_handle s_usfc_handles[MAX_EVENT_TYPE_NUM] = {
+/*
+ * For each event type, there are a number conflicting devices (handles)
+ * The first registered device (primary) is real TSC device; it's mandatory
+ * Optionally, later registered devices are simulated ones.
+ * They are dynamically managed
+ * The primary device's handles are stored in the below static array
+ */
+static struct input_handle s_usfc_primary_handles[MAX_EVENT_TYPE_NUM] = {
{ /* TSC handle */
.handler = &s_usfc_handlers[TSC_EVENT_TYPE_IND],
.name = "usfc_tsc_handle",
@@ -142,22 +146,48 @@
{
int ret = 0;
uint16_t ind = handler->minor;
+ struct input_handle *usfc_handle = NULL;
- s_usfc_handles[ind].dev = dev;
- ret = input_register_handle(&s_usfc_handles[ind]);
- if (ret) {
+ if (s_usfc_primary_handles[ind].dev == NULL) {
+ pr_debug("%s: primary device; ind=%d\n",
+ __func__,
+ ind);
+ usfc_handle = &s_usfc_primary_handles[ind];
+ } else {
+ pr_debug("%s: secondary device; ind=%d\n",
+ __func__,
+ ind);
+ usfc_handle = kzalloc(sizeof(struct input_handle),
+ GFP_KERNEL);
+ if (!usfc_handle) {
+ pr_err("%s: memory allocation failed; ind=%d\n",
+ __func__,
+ ind);
+ return -ENOMEM;
+ }
+ usfc_handle->handler = &s_usfc_handlers[ind];
+ usfc_handle->name = s_usfc_primary_handles[ind].name;
+ }
+ usfc_handle->dev = dev;
+ ret = input_register_handle(usfc_handle);
+ pr_debug("%s: name=[%s]; ind=%d; dev=0x%p\n",
+ __func__,
+ dev->name,
+ ind,
+ usfc_handle->dev);
+ if (ret)
pr_err("%s: input_register_handle[%d] failed: ret=%d\n",
__func__,
ind,
ret);
- } else {
- ret = input_open_device(&s_usfc_handles[ind]);
+ else {
+ ret = input_open_device(usfc_handle);
if (ret) {
pr_err("%s: input_open_device[%d] failed: ret=%d\n",
__func__,
ind,
ret);
- input_unregister_handle(&s_usfc_handles[ind]);
+ input_unregister_handle(usfc_handle);
} else
pr_debug("%s: device[%d] is opened\n",
__func__,
@@ -169,10 +199,18 @@
static void usfcdev_disconnect(struct input_handle *handle)
{
+ int ind = handle->handler->minor;
+
+ input_close_device(handle);
input_unregister_handle(handle);
- pr_debug("%s: handle[%d] is disconnect\n",
+ pr_debug("%s: handle[%d], name=[%s] is disconnected\n",
__func__,
- handle->handler->minor);
+ ind,
+ handle->dev->name);
+ if (s_usfc_primary_handles[ind].dev == handle->dev)
+ s_usfc_primary_handles[ind].dev = NULL;
+ else
+ kfree(handle);
}
static bool usfcdev_filter(struct input_handle *handle,
@@ -297,8 +335,13 @@
event_type_ind);
return;
}
-
- dev = s_usfc_handles[event_type_ind].dev;
+ /* Only primary device must exist */
+ dev = s_usfc_primary_handles[event_type_ind].dev;
+ if (dev == NULL) {
+ pr_err("%s: NULL primary device\n",
+ __func__);
+ return;
+ }
for (i = 0; i < ARRAY_SIZE(initial_clear_cmds); i++)
usfcdev_send_cmd(dev, initial_clear_cmds[i]);
@@ -307,7 +350,7 @@
/* Send commands to free all slots */
for (i = 0; i < dev->mtsize; i++) {
s_usfcdev_events[event_type_ind].interleaved = false;
- if (input_mt_get_value(&(dev->mt[i]), ABS_MT_TRACKING_ID) < 0) {
+ if (input_mt_get_value(&dev->mt[i], ABS_MT_TRACKING_ID) < 0) {
pr_debug("%s: skipping slot %d",
__func__, i);
continue;
@@ -323,7 +366,7 @@
--i;
continue;
}
- pr_warning("%s: index(%d) reached max retires",
+ pr_warn("%s: index(%d) reached max retires",
__func__, i);
}
diff --git a/arch/arm/mach-msm/qdsp6v2/ultrasound/version_b/q6usm_b.c b/arch/arm/mach-msm/qdsp6v2/ultrasound/version_b/q6usm_b.c
index fe7c8c2..51a51c5 100644
--- a/arch/arm/mach-msm/qdsp6v2/ultrasound/version_b/q6usm_b.c
+++ b/arch/arm/mach-msm/qdsp6v2/ultrasound/version_b/q6usm_b.c
@@ -628,6 +628,12 @@
case FORMAT_USPROX:
int_format = US_PROX_FORMAT_V2;
break;
+ case FORMAT_USGES_SYNC:
+ int_format = US_GES_SYNC_FORMAT;
+ break;
+ case FORMAT_USRAW_SYNC:
+ int_format = US_RAW_SYNC_FORMAT;
+ break;
default:
pr_err("%s: Invalid format[%d]\n", __func__, ext_format);
break;
diff --git a/arch/arm/mach-msm/rpm-notifier.h b/arch/arm/mach-msm/rpm-notifier.h
index 16de77e..1f4fdab 100644
--- a/arch/arm/mach-msm/rpm-notifier.h
+++ b/arch/arm/mach-msm/rpm-notifier.h
@@ -42,10 +42,11 @@
* msm_rpm_enter_sleep - Notify RPM driver to prepare for entering sleep
*
* @bool - flag to enable print contents of sleep buffer.
+ * @cpumask - cpumask of next wakeup cpu
*
* return 0 on success errno on failure.
*/
-int msm_rpm_enter_sleep(bool print);
+int msm_rpm_enter_sleep(bool print, const struct cpumask *cpumask);
/**
* msm_rpm_exit_sleep - Notify RPM driver about resuming from power collapse
diff --git a/arch/arm/mach-msm/rpm-regulator-smd.c b/arch/arm/mach-msm/rpm-regulator-smd.c
index faf774f..7995e9a 100644
--- a/arch/arm/mach-msm/rpm-regulator-smd.c
+++ b/arch/arm/mach-msm/rpm-regulator-smd.c
@@ -864,7 +864,7 @@
load_mA = params[RPM_REGULATOR_PARAM_CURRENT].max;
rpm_vreg_lock(reg->rpm_vreg);
- RPM_VREG_SET_PARAM(reg, CURRENT, MICRO_TO_MILLI(load_uA));
+ RPM_VREG_SET_PARAM(reg, CURRENT, load_mA);
rpm_vreg_unlock(reg->rpm_vreg);
return (load_uA >= reg->rpm_vreg->hpm_min_load)
@@ -917,7 +917,6 @@
if (priv_reg == NULL) {
vreg_err(framework_reg, "could not allocate memory for "
"regulator\n");
- rpm_vreg_unlock(rpm_vreg);
return ERR_PTR(-ENOMEM);
}
@@ -930,7 +929,6 @@
vreg_err(framework_reg, "could not allocate memory for "
"regulator_dev\n");
kfree(priv_reg);
- rpm_vreg_unlock(rpm_vreg);
return ERR_PTR(-ENOMEM);
}
priv_reg->rdev->reg_data = priv_reg;
diff --git a/arch/arm/mach-msm/rpm-smd.c b/arch/arm/mach-msm/rpm-smd.c
index ccab6e2..54576a9 100644
--- a/arch/arm/mach-msm/rpm-smd.c
+++ b/arch/arm/mach-msm/rpm-smd.c
@@ -1287,14 +1287,14 @@
* During power collapse, the rpm driver disables the SMD interrupts to make
* sure that the interrupt doesn't wakes us from sleep.
*/
-int msm_rpm_enter_sleep(bool print)
+int msm_rpm_enter_sleep(bool print, const struct cpumask *cpumask)
{
if (standalone)
return 0;
msm_rpm_flush_requests(print);
- return smd_mask_receive_interrupt(msm_rpm_data.ch_info, true);
+ return smd_mask_receive_interrupt(msm_rpm_data.ch_info, true, cpumask);
}
EXPORT_SYMBOL(msm_rpm_enter_sleep);
@@ -1307,7 +1307,7 @@
if (standalone)
return;
- smd_mask_receive_interrupt(msm_rpm_data.ch_info, false);
+ smd_mask_receive_interrupt(msm_rpm_data.ch_info, false, NULL);
}
EXPORT_SYMBOL(msm_rpm_exit_sleep);
diff --git a/arch/arm/mach-msm/sensors_adsp.c b/arch/arm/mach-msm/sensors_adsp.c
index fab10b8..ad19e16 100644
--- a/arch/arm/mach-msm/sensors_adsp.c
+++ b/arch/arm/mach-msm/sensors_adsp.c
@@ -38,6 +38,7 @@
#include <mach/msm_bus.h>
#include <mach/msm_bus_board.h>
+#define CLASS_NAME "ssc"
#define DRV_NAME "sensors"
#define DRV_VERSION "1.00"
@@ -1079,7 +1080,7 @@
static int sensors_adsp_probe(struct platform_device *pdev)
{
int ret = 0;
- sns_ctl.dev_class = class_create(THIS_MODULE, DRV_NAME);
+ sns_ctl.dev_class = class_create(THIS_MODULE, CLASS_NAME);
if (sns_ctl.dev_class == NULL) {
pr_err("%s: class_create fail.\n", __func__);
goto res_err;
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index cb9697d..09b3113 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -2247,13 +2247,15 @@
* particular channel.
* @ch: open channel handle to use for the edge
* @mask: 1 = mask interrupts; 0 = unmask interrupts
+ * @cpumask cpumask for the next cpu scheduled to be woken up
* @returns: 0 for success; < 0 for failure
*
* Note that this enables/disables all interrupts from the remote subsystem for
* all channels. As such, it should be used with care and only for specific
* use cases such as power-collapse sequencing.
*/
-int smd_mask_receive_interrupt(smd_channel_t *ch, bool mask)
+int smd_mask_receive_interrupt(smd_channel_t *ch, bool mask,
+ const struct cpumask *cpumask)
{
struct irq_chip *irq_chip;
struct irq_data *irq_data;
@@ -2282,6 +2284,8 @@
SMD_POWER_INFO("SMD Masking interrupts from %s\n",
edge_to_pids[ch->type].subsys_name);
irq_chip->irq_mask(irq_data);
+ if (cpumask)
+ irq_chip->irq_set_affinity(irq_data, cpumask, true);
} else {
SMD_POWER_INFO("SMD Unmasking interrupts from %s\n",
edge_to_pids[ch->type].subsys_name);
diff --git a/arch/arm/mach-msm/socinfo.c b/arch/arm/mach-msm/socinfo.c
index 4b68e66..e7cec58 100644
--- a/arch/arm/mach-msm/socinfo.c
+++ b/arch/arm/mach-msm/socinfo.c
@@ -36,7 +36,6 @@
#define SMEM_IMAGE_VERSION_SINGLE_BLOCK_SIZE 128
#define SMEM_IMAGE_VERSION_SIZE 4096
#define SMEM_IMAGE_VERSION_NAME_SIZE 75
-#define SMEM_IMAGE_VERSION_NAME_OFFSET 3
#define SMEM_IMAGE_VERSION_VARIANT_SIZE 20
#define SMEM_IMAGE_VERSION_VARIANT_OFFSET 75
#define SMEM_IMAGE_VERSION_OEM_SIZE 32
@@ -859,8 +858,7 @@
return snprintf(buf, SMEM_IMAGE_VERSION_NAME_SIZE, "Unknown");
}
string_address += current_image * SMEM_IMAGE_VERSION_SINGLE_BLOCK_SIZE;
- string_address += SMEM_IMAGE_VERSION_NAME_OFFSET;
- return snprintf(buf, SMEM_IMAGE_VERSION_NAME_SIZE, "%-.72s\n",
+ return snprintf(buf, SMEM_IMAGE_VERSION_NAME_SIZE, "%-.75s\n",
string_address);
}
diff --git a/arch/arm/mach-msm/spm.h b/arch/arm/mach-msm/spm.h
index 1769402..2946689 100644
--- a/arch/arm/mach-msm/spm.h
+++ b/arch/arm/mach-msm/spm.h
@@ -28,43 +28,6 @@
MSM_SPM_L2_MODE_POWER_COLLAPSE,
};
-#if defined(CONFIG_MSM_SPM_V1)
-
-enum {
- MSM_SPM_REG_SAW_AVS_CTL,
- MSM_SPM_REG_SAW_CFG,
- MSM_SPM_REG_SAW_SPM_CTL,
- MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY,
- MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY,
- MSM_SPM_REG_SAW_SLP_CLK_EN,
- MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN,
- MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN,
- MSM_SPM_REG_SAW_SLP_CLMP_EN,
- MSM_SPM_REG_SAW_SLP_RST_EN,
- MSM_SPM_REG_SAW_SPM_MPM_CFG,
- MSM_SPM_REG_NR_INITIALIZE,
-
- MSM_SPM_REG_SAW_VCTL = MSM_SPM_REG_NR_INITIALIZE,
- MSM_SPM_REG_SAW_STS,
- MSM_SPM_REG_SAW_SPM_PMIC_CTL,
- MSM_SPM_REG_NR
-};
-
-struct msm_spm_platform_data {
- void __iomem *reg_base_addr;
- uint32_t reg_init_values[MSM_SPM_REG_NR_INITIALIZE];
-
- uint8_t awake_vlevel;
- uint8_t retention_vlevel;
- uint8_t collapse_vlevel;
- uint8_t retention_mid_vlevel;
- uint8_t collapse_mid_vlevel;
-
- uint32_t vctl_timeout_us;
-};
-
-#elif defined(CONFIG_MSM_SPM_V2)
-
enum {
MSM_SPM_REG_SAW2_CFG,
MSM_SPM_REG_SAW2_AVS_CTL,
@@ -122,9 +85,8 @@
uint32_t num_modes;
struct msm_spm_seq_entry *modes;
};
-#endif
-#if defined(CONFIG_MSM_SPM_V1) || defined(CONFIG_MSM_SPM_V2)
+#if defined(CONFIG_MSM_SPM_V2)
/* Public functions */
@@ -187,7 +149,7 @@
return -ENOSYS;
}
#endif /* defined(CONFIG_MSM_L2_SPM) */
-#else /* defined(CONFIG_MSM_SPM_V1) || defined(CONFIG_MSM_SPM_V2) */
+#else /* defined(CONFIG_MSM_SPM_V2) */
static inline int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm)
{
return -ENOSYS;
@@ -218,5 +180,5 @@
return -ENOSYS;
}
-#endif /*defined(CONFIG_MSM_SPM_V1) || defined (CONFIG_MSM_SPM_V2) */
+#endif /* defined (CONFIG_MSM_SPM_V2) */
#endif /* __ARCH_ARM_MACH_MSM_SPM_H */
diff --git a/arch/arm/mach-msm/test-lpm.c b/arch/arm/mach-msm/test-lpm.c
index 031b2dc..790c909 100644
--- a/arch/arm/mach-msm/test-lpm.c
+++ b/arch/arm/mach-msm/test-lpm.c
@@ -121,9 +121,6 @@
case MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT:
strlcat(nm, "WFI ", BUF_SIZE);
break;
- case MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT:
- strlcat(nm, "WFI voltage Rampdown ", BUF_SIZE);
- break;
case MSM_PM_SLEEP_MODE_RETENTION:
strlcat(nm, "Retention ", BUF_SIZE);
break;
@@ -133,9 +130,6 @@
case MSM_PM_SLEEP_MODE_POWER_COLLAPSE:
strlcat(nm, "Idle Power collapse ", BUF_SIZE);
break;
- case MSM_PM_SLEEP_MODE_POWER_COLLAPSE_SUSPEND:
- strlcat(nm, "Suspend Power collapse ", BUF_SIZE);
- break;
default:
strlcat(nm, "Invalid Mode ", BUF_SIZE);
break;
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index 0720163..e505bef 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -240,6 +240,9 @@
mov pc, lr
ENDPROC(fa_dma_unmap_area)
+ .globl fa_flush_kern_cache_louis
+ .equ fa_flush_kern_cache_louis, fa_flush_kern_cache_all
+
__INITDATA
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index c2301f2..d99c00c 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -127,6 +127,9 @@
ENDPROC(v3_dma_unmap_area)
ENDPROC(v3_dma_map_area)
+ .globl v3_flush_kern_cache_louis
+ .equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all
+
__INITDATA
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index fd9bb7a..548b892a 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -139,6 +139,9 @@
ENDPROC(v4_dma_unmap_area)
ENDPROC(v4_dma_map_area)
+ .globl v4_flush_kern_cache_louis
+ .equ v4_flush_kern_cache_louis, v4_flush_kern_cache_all
+
__INITDATA
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 4f2c141..63b7e49 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -251,6 +251,9 @@
mov pc, lr
ENDPROC(v4wb_dma_unmap_area)
+ .globl v4wb_flush_kern_cache_louis
+ .equ v4wb_flush_kern_cache_louis, v4wb_flush_kern_cache_all
+
__INITDATA
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 4d7b467..198d424 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -195,6 +195,9 @@
ENDPROC(v4wt_dma_unmap_area)
ENDPROC(v4wt_dma_map_area)
+ .globl v4wt_flush_kern_cache_louis
+ .equ v4wt_flush_kern_cache_louis, v4wt_flush_kern_cache_all
+
__INITDATA
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 2edb6f6..6a5674d 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -345,6 +345,9 @@
mov pc, lr
ENDPROC(v6_dma_unmap_area)
+ .globl v6_flush_kern_cache_louis
+ .equ v6_flush_kern_cache_louis, v6_flush_kern_cache_all
+
__INITDATA
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index a655d3d..df79627 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -32,6 +32,24 @@
mov pc, lr
ENDPROC(v7_flush_icache_all)
+ /*
+ * v7_flush_dcache_louis()
+ *
+ * Flush the D-cache up to the Level of Unification Inner Shareable
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ */
+
+ENTRY(v7_flush_dcache_louis)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
+ ands r3, r0, #0xe00000 @ extract LoUIS from clidr
+ mov r3, r3, lsr #20 @ r3 = LoUIS * 2
+ moveq pc, lr @ return if level == 0
+ mov r10, #0 @ r10 (starting level) = 0
+ b loop1 @ start flushing cache levels
+ENDPROC(v7_flush_dcache_louis)
+
/*
* v7_flush_dcache_all()
*
@@ -119,6 +137,24 @@
mov pc, lr
ENDPROC(v7_flush_kern_cache_all)
+ /*
+ * v7_flush_kern_cache_louis(void)
+ *
+ * Flush the data cache up to Level of Unification Inner Shareable.
+ * Invalidate the I-cache to the point of unification.
+ */
+ENTRY(v7_flush_kern_cache_louis)
+ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
+ bl v7_flush_dcache_louis
+ mov r0, #0
+ ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
+ ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
+ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
+ mov pc, lr
+ENDPROC(v7_flush_kern_cache_louis)
+
/*
* v7_flush_cache_all()
*
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 2349513..c11e32e 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -367,6 +367,9 @@
mov pc, lr
ENDPROC(arm1020_dma_unmap_area)
+ .globl arm1020_flush_kern_cache_louis
+ .equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm1020
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index c244b06..9624a35 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -353,6 +353,9 @@
mov pc, lr
ENDPROC(arm1020e_dma_unmap_area)
+ .globl arm1020e_flush_kern_cache_louis
+ .equ arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm1020e
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 38fe22e..f2b45ee 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -342,6 +342,9 @@
mov pc, lr
ENDPROC(arm1022_dma_unmap_area)
+ .globl arm1022_flush_kern_cache_louis
+ .equ arm1022_flush_kern_cache_louis, arm1022_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm1022
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 3eb9c3c..95934d2 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -336,6 +336,9 @@
mov pc, lr
ENDPROC(arm1026_dma_unmap_area)
+ .globl arm1026_flush_kern_cache_louis
+ .equ arm1026_flush_kern_cache_louis, arm1026_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm1026
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index cb941ae..ed3acd4 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -318,6 +318,9 @@
mov pc, lr
ENDPROC(arm920_dma_unmap_area)
+ .globl arm920_flush_kern_cache_louis
+ .equ arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm920
#endif
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 4ec0e07..142bace 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -320,6 +320,9 @@
mov pc, lr
ENDPROC(arm922_dma_unmap_area)
+ .globl arm922_flush_kern_cache_louis
+ .equ arm922_flush_kern_cache_louis, arm922_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm922
#endif
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 9dccd9a..3028390 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -375,6 +375,9 @@
mov pc, lr
ENDPROC(arm925_dma_unmap_area)
+ .globl arm925_flush_kern_cache_louis
+ .equ arm925_flush_kern_cache_louis, arm925_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm925
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 820259b..1f99b46 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -338,6 +338,9 @@
mov pc, lr
ENDPROC(arm926_dma_unmap_area)
+ .globl arm926_flush_kern_cache_louis
+ .equ arm926_flush_kern_cache_louis, arm926_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm926
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 9fdc0a1..e5af959 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -267,6 +267,9 @@
mov pc, lr
ENDPROC(arm940_dma_unmap_area)
+ .globl arm940_flush_kern_cache_louis
+ .equ arm940_flush_kern_cache_louis, arm940_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm940
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index f684cfe..3599b37 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -309,6 +309,9 @@
mov pc, lr
ENDPROC(arm946_dma_unmap_area)
+ .globl arm946_flush_kern_cache_louis
+ .equ arm946_flush_kern_cache_louis, arm946_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm946
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index ba3c500..26a9984 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -414,6 +414,9 @@
mov pc, lr
ENDPROC(feroceon_dma_unmap_area)
+ .globl feroceon_flush_kern_cache_louis
+ .equ feroceon_flush_kern_cache_louis, feroceon_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions feroceon
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 5829bb3..2ea177a 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -299,6 +299,7 @@
ENTRY(\name\()_cache_fns)
.long \name\()_flush_icache_all
.long \name\()_flush_kern_cache_all
+ .long \name\()_flush_kern_cache_louis
.long \name\()_flush_user_cache_all
.long \name\()_flush_user_cache_range
.long \name\()_coherent_kern_range
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index cdfedc5..224d0f5 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -302,6 +302,9 @@
mov pc, lr
ENDPROC(mohawk_dma_unmap_area)
+ .globl mohawk_flush_kern_cache_louis
+ .equ mohawk_flush_kern_cache_louis, mohawk_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions mohawk
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index b0d5786..eb93d64 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -337,6 +337,9 @@
mov pc, lr
ENDPROC(xsc3_dma_unmap_area)
+ .globl xsc3_flush_kern_cache_louis
+ .equ xsc3_flush_kern_cache_louis, xsc3_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions xsc3
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 4ffebaa..b5ea31d 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -410,6 +410,9 @@
mov pc, lr
ENDPROC(xscale_dma_unmap_area)
+ .globl xscale_flush_kern_cache_louis
+ .equ xscale_flush_kern_cache_louis, xscale_flush_kern_cache_all
+
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions xscale
diff --git a/drivers/Kconfig b/drivers/Kconfig
index adead10..72440c9 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -152,4 +152,6 @@
source "drivers/bif/Kconfig"
+source "drivers/sensors/Kconfig"
+
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index d55b035..867be8a 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -144,3 +144,4 @@
obj-$(CONFIG_CORESIGHT) += coresight/
obj-$(CONFIG_BIF) += bif/
+obj-$(CONFIG_SENSORS) += sensors/
diff --git a/drivers/base/dma-contiguous.c b/drivers/base/dma-contiguous.c
index 45c9023..885721f 100644
--- a/drivers/base/dma-contiguous.c
+++ b/drivers/base/dma-contiguous.c
@@ -447,6 +447,13 @@
}
core_initcall(cma_init_reserved_areas);
+phys_addr_t cma_get_base(struct device *dev)
+{
+ struct cma *cma = dev_get_cma_area(dev);
+
+ return cma->base_pfn << PAGE_SHIFT;
+}
+
/**
* dma_alloc_from_contiguous() - allocate pages from contiguous area
* @dev: Pointer to device for which the allocation is performed.
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index e2864ec..97b1f39 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -650,14 +650,13 @@
different function.
config MSM_ADSPRPC
- tristate "Qualcomm ADSP RPC driver"
- depends on MSM_AUDIO_QDSP6 || MSM_AUDIO_QDSP6V2
- default m
- help
- Provides a communication mechanism that allows for clients to
- make remote method invocations across processor boundary to
- applications DSP processor. Say M if you want to enable this
- module.
+ tristate "Qualcomm ADSP RPC driver"
+ depends on MSM_AUDIO_QDSP6 || MSM_AUDIO_QDSP6V2
+ help
+ Provides a communication mechanism that allows for clients to
+ make remote method invocations across processor boundary to
+ applications DSP processor. Say M if you want to enable this
+ module.
config MMC_GENERIC_CSDIO
tristate "Generic sdio driver"
@@ -681,6 +680,13 @@
help
Enter device id for targeted sdio device, this may be overwritten by
module parameters.
-.
+
+config MSM_RDBG
+ tristate "Qualcomm Remote debug driver"
+ depends on MSM_AUDIO_QDSP6 || MSM_AUDIO_QDSP6V2
+ help
+ Implements a shared memory based transport mechanism that allows
+ for a debugger running on a host PC to communicate with a remote
+ stub running on peripheral subsystems such as the ADSP, MODEM etc.
endmenu
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 8032f0b..7589946 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -68,3 +68,4 @@
obj-$(CONFIG_MMC_GENERIC_CSDIO) += csdio.o
obj-$(CONFIG_DIAG_CHAR) += diag/
obj-$(CONFIG_MSM_ADSPRPC) += adsprpc.o
+obj-$(CONFIG_MSM_RDBG) += rdbg.o
diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c
index 3aa86463..cc8cf47 100644
--- a/drivers/char/adsprpc.c
+++ b/drivers/char/adsprpc.c
@@ -33,6 +33,7 @@
#include <linux/device.h>
#include <linux/of.h>
#include <linux/iommu.h>
+#include <linux/kref.h>
#ifndef ION_ADSPRPC_HEAP_ID
#define ION_ADSPRPC_HEAP_ID ION_AUDIO_HEAP_ID
@@ -124,16 +125,38 @@
return n;
}
+struct fastrpc_buf {
+ struct ion_handle *handle;
+ void *virt;
+ ion_phys_addr_t phys;
+ int size;
+ int used;
+};
+
+struct smq_context_list;
+
struct smq_invoke_ctx {
+ struct hlist_node hn;
struct completion work;
int retval;
- atomic_t free;
+ int pid;
+ remote_arg_t *pra;
+ remote_arg_t *rpra;
+ struct fastrpc_buf obuf;
+ struct fastrpc_buf *abufs;
+ struct fastrpc_device *dev;
+ struct fastrpc_apps *apps;
+ int *fds;
+ struct ion_handle **handles;
+ int nbufs;
+ bool smmu;
+ uint32_t sc;
};
struct smq_context_list {
- struct smq_invoke_ctx *ls;
- int size;
- int last;
+ struct hlist_head pending;
+ struct hlist_head interrupted;
+ spinlock_t hlock;
};
struct fastrpc_smmu {
@@ -152,9 +175,11 @@
struct class *class;
struct device *dev;
struct fastrpc_smmu smmu;
+ struct mutex smd_mutex;
dev_t dev_no;
spinlock_t wrlock;
spinlock_t hlock;
+ struct kref kref;
struct hlist_head htbl[RPC_HASH_SZ];
};
@@ -162,22 +187,16 @@
struct hlist_node hn;
struct ion_handle *handle;
void *virt;
+ ion_phys_addr_t phys;
uint32_t vaddrin;
uint32_t vaddrout;
int size;
};
-struct fastrpc_buf {
- struct ion_handle *handle;
- void *virt;
- ion_phys_addr_t phys;
- int size;
- int used;
-};
-
struct file_data {
spinlock_t hlock;
struct hlist_head hlst;
+ uint32_t mode;
};
struct fastrpc_device {
@@ -211,6 +230,11 @@
{
struct fastrpc_apps *me = &gfa;
if (!IS_ERR_OR_NULL(map->handle)) {
+ if (me->smmu.enabled && map->phys) {
+ ion_unmap_iommu(me->iclient, map->handle,
+ me->smmu.domain_id, 0);
+ map->phys = 0;
+ }
if (!IS_ERR_OR_NULL(map->virt)) {
ion_unmap_kernel(me->iclient, map->handle);
map->virt = 0;
@@ -252,9 +276,6 @@
VERIFY(err, 0 != (sg = ion_sg_table(clnt, buf->handle)));
if (err)
goto bail;
- VERIFY(err, 1 == sg->nents);
- if (err)
- goto bail;
buf->phys = sg_dma_address(sg->sgl);
}
bail:
@@ -263,65 +284,186 @@
return err;
}
-static int context_list_ctor(struct smq_context_list *me, int size)
+static int context_restore_interrupted(struct fastrpc_apps *me,
+ struct fastrpc_ioctl_invoke_fd *invokefd,
+ struct smq_invoke_ctx **po)
{
int err = 0;
- VERIFY(err, 0 != (me->ls = kzalloc(size, GFP_KERNEL)));
- if (err)
- goto bail;
- me->size = size / sizeof(*me->ls);
- me->last = 0;
- bail:
+ struct smq_invoke_ctx *ctx = 0, *ictx = 0;
+ struct hlist_node *pos, *n;
+ struct fastrpc_ioctl_invoke *invoke = &invokefd->inv;
+ spin_lock(&me->clst.hlock);
+ hlist_for_each_entry_safe(ictx, pos, n, &me->clst.interrupted, hn) {
+ if (ictx->pid == current->pid) {
+ if (invoke->sc != ictx->sc)
+ err = -1;
+ else {
+ ctx = ictx;
+ hlist_del(&ctx->hn);
+ hlist_add_head(&ctx->hn, &me->clst.pending);
+ }
+ break;
+ }
+ }
+ spin_unlock(&me->clst.hlock);
+ if (ctx)
+ *po = ctx;
return err;
}
-static void context_list_dtor(struct smq_context_list *me)
+static int context_alloc(struct fastrpc_apps *me, uint32_t kernel,
+ struct fastrpc_ioctl_invoke_fd *invokefd,
+ struct smq_invoke_ctx **po)
{
- kfree(me->ls);
-}
+ int err = 0, bufs, size = 0;
+ struct smq_invoke_ctx *ctx = 0;
+ struct smq_context_list *clst = &me->clst;
+ struct fastrpc_ioctl_invoke *invoke = &invokefd->inv;
-static void context_list_alloc_ctx(struct smq_context_list *me,
- struct smq_invoke_ctx **po)
-{
- int i = me->last;
- struct smq_invoke_ctx *ctx;
-
- for (;;) {
- i = i % me->size;
- ctx = &me->ls[i];
- if (atomic_read(&ctx->free) == 0)
- if (atomic_cmpxchg(&ctx->free, 0, 1) == 0)
- break;
- i++;
+ bufs = REMOTE_SCALARS_INBUFS(invoke->sc) +
+ REMOTE_SCALARS_OUTBUFS(invoke->sc);
+ if (bufs) {
+ size = bufs * sizeof(*ctx->pra);
+ if (invokefd->fds)
+ size = size + bufs * sizeof(*ctx->fds) +
+ bufs * sizeof(*ctx->handles);
}
- me->last = i;
+
+ VERIFY(err, 0 != (ctx = kzalloc(sizeof(*ctx) + size, GFP_KERNEL)));
+ if (err)
+ goto bail;
+
+ INIT_HLIST_NODE(&ctx->hn);
+ ctx->pra = (remote_arg_t *)(&ctx[1]);
+ ctx->fds = invokefd->fds == 0 ? 0 : (int *)(&ctx->pra[bufs]);
+ ctx->handles = invokefd->fds == 0 ? 0 :
+ (struct ion_handle **)(&ctx->fds[bufs]);
+ if (!kernel) {
+ VERIFY(err, 0 == copy_from_user(ctx->pra, invoke->pra,
+ bufs * sizeof(*ctx->pra)));
+ if (err)
+ goto bail;
+ } else {
+ memmove(ctx->pra, invoke->pra, bufs * sizeof(*ctx->pra));
+ }
+
+ if (invokefd->fds) {
+ if (!kernel) {
+ VERIFY(err, 0 == copy_from_user(ctx->fds, invokefd->fds,
+ bufs * sizeof(*ctx->fds)));
+ if (err)
+ goto bail;
+ } else {
+ memmove(ctx->fds, invokefd->fds,
+ bufs * sizeof(*ctx->fds));
+ }
+ }
+ ctx->sc = invoke->sc;
ctx->retval = -1;
+ ctx->pid = current->pid;
+ ctx->apps = me;
init_completion(&ctx->work);
+ spin_lock(&clst->hlock);
+ hlist_add_head(&ctx->hn, &clst->pending);
+ spin_unlock(&clst->hlock);
+
*po = ctx;
+bail:
+ if (ctx && err)
+ kfree(ctx);
+ return err;
}
-static void context_free(struct smq_invoke_ctx *me)
+static void context_save_interrupted(struct smq_invoke_ctx *ctx)
{
- if (me)
- atomic_set(&me->free, 0);
+ struct smq_context_list *clst = &ctx->apps->clst;
+ spin_lock(&clst->hlock);
+ hlist_del(&ctx->hn);
+ hlist_add_head(&ctx->hn, &clst->interrupted);
+ spin_unlock(&clst->hlock);
}
-static void context_notify_user(struct smq_invoke_ctx *me, int retval)
+static void add_dev(struct fastrpc_apps *me, struct fastrpc_device *dev);
+
+static void context_free(struct smq_invoke_ctx *ctx, bool lock)
{
- me->retval = retval;
- complete(&me->work);
+ struct smq_context_list *clst = &ctx->apps->clst;
+ struct fastrpc_apps *apps = ctx->apps;
+ struct ion_client *clnt = apps->iclient;
+ struct fastrpc_smmu *smmu = &apps->smmu;
+ struct fastrpc_buf *b;
+ int i, bufs;
+ if (ctx->smmu) {
+ bufs = REMOTE_SCALARS_INBUFS(ctx->sc) +
+ REMOTE_SCALARS_OUTBUFS(ctx->sc);
+ if (ctx->fds) {
+ for (i = 0; i < bufs; i++)
+ if (!IS_ERR_OR_NULL(ctx->handles[i])) {
+ ion_unmap_iommu(clnt, ctx->handles[i],
+ smmu->domain_id, 0);
+ ion_free(clnt, ctx->handles[i]);
+ }
+ }
+ iommu_detach_group(smmu->domain, smmu->group);
+ }
+ for (i = 0, b = ctx->abufs; i < ctx->nbufs; ++i, ++b)
+ free_mem(b);
+
+ kfree(ctx->abufs);
+ if (ctx->dev) {
+ add_dev(apps, ctx->dev);
+ if (ctx->obuf.handle != ctx->dev->buf.handle)
+ free_mem(&ctx->obuf);
+ }
+ if (lock)
+ spin_lock(&clst->hlock);
+ hlist_del(&ctx->hn);
+ if (lock)
+ spin_unlock(&clst->hlock);
+ kfree(ctx);
+}
+
+static void context_notify_user(struct smq_invoke_ctx *ctx, int retval)
+{
+ ctx->retval = retval;
+ complete(&ctx->work);
}
static void context_notify_all_users(struct smq_context_list *me)
{
- int i;
-
- if (!me->ls)
- return;
- for (i = 0; i < me->size; ++i) {
- if (atomic_read(&me->ls[i].free) != 0)
- complete(&me->ls[i].work);
+ struct smq_invoke_ctx *ictx = 0;
+ struct hlist_node *pos, *n;
+ spin_lock(&me->hlock);
+ hlist_for_each_entry_safe(ictx, pos, n, &me->pending, hn) {
+ complete(&ictx->work);
}
+ hlist_for_each_entry_safe(ictx, pos, n, &me->interrupted, hn) {
+ complete(&ictx->work);
+ }
+ spin_unlock(&me->hlock);
+
+}
+
+static void context_list_ctor(struct smq_context_list *me)
+{
+ INIT_HLIST_HEAD(&me->interrupted);
+ INIT_HLIST_HEAD(&me->pending);
+ spin_lock_init(&me->hlock);
+}
+
+static void context_list_dtor(struct fastrpc_apps *me,
+ struct smq_context_list *clst)
+{
+ struct smq_invoke_ctx *ictx = 0;
+ struct hlist_node *pos, *n;
+ spin_lock(&clst->hlock);
+ hlist_for_each_entry_safe(ictx, pos, n, &clst->interrupted, hn) {
+ context_free(ictx, 0);
+ }
+ hlist_for_each_entry_safe(ictx, pos, n, &clst->pending, hn) {
+ context_free(ictx, 0);
+ }
+ spin_unlock(&clst->hlock);
}
static int get_page_list(uint32_t kernel, uint32_t sc, remote_arg_t *pra,
@@ -400,13 +542,12 @@
static int get_args(uint32_t kernel, uint32_t sc, remote_arg_t *pra,
remote_arg_t *rpra, remote_arg_t *upra,
struct fastrpc_buf *ibuf, struct fastrpc_buf **abufs,
- int *nbufs, int *fds)
+ int *nbufs, int *fds, struct ion_handle **handles)
{
struct fastrpc_apps *me = &gfa;
struct smq_invoke_buf *list;
struct fastrpc_buf *pbuf = ibuf, *obufs = 0;
struct smq_phy_page *pages;
- struct ion_handle **handles = NULL;
void *args;
int i, rlen, size, used, inh, bufs = 0, err = 0;
int inbufs = REMOTE_SCALARS_INBUFS(sc);
@@ -418,8 +559,6 @@
used = ALIGN(pbuf->used, BALIGN);
args = (void *)((char *)pbuf->virt + used);
rlen = pbuf->size - used;
- if (fds)
- handles = (struct ion_handle **)(fds + inbufs + outbufs);
for (i = 0; i < inbufs + outbufs; ++i) {
rpra[i].buf.len = pra[i].buf.len;
@@ -614,7 +753,6 @@
struct fastrpc_apps *me = &gfa;
smd_close(me->chan);
- context_list_dtor(&me->clst);
ion_client_destroy(me->iclient);
me->iclient = 0;
me->chan = 0;
@@ -666,16 +804,15 @@
spin_lock_init(&me->hlock);
spin_lock_init(&me->wrlock);
init_completion(&me->work);
+ mutex_init(&me->smd_mutex);
+ context_list_ctor(&me->clst);
for (i = 0; i < RPC_HASH_SZ; ++i)
INIT_HLIST_HEAD(&me->htbl[i]);
- VERIFY(err, 0 == context_list_ctor(&me->clst, SZ_4K));
- if (err)
- goto context_list_bail;
me->iclient = msm_ion_client_create(ION_HEAP_CARVEOUT_MASK,
DEVICE_NAME);
VERIFY(err, 0 == IS_ERR_OR_NULL(me->iclient));
if (err)
- goto ion_bail;
+ goto bail;
node = of_find_compatible_node(NULL, NULL,
"qcom,msm-audio-ion");
if (node)
@@ -692,26 +829,11 @@
if (me->smmu.domain_id >= 0)
me->smmu.enabled = enabled;
}
- VERIFY(err, 0 == smd_named_open_on_edge(FASTRPC_SMD_GUID,
- SMD_APPS_QDSP, &me->chan,
- me, smd_event_handler));
- if (err)
- goto smd_bail;
- VERIFY(err, 0 != wait_for_completion_timeout(&me->work,
- RPC_TIMEOUT));
- if (err)
- goto completion_bail;
}
return 0;
-completion_bail:
- smd_close(me->chan);
-smd_bail:
- ion_client_destroy(me->iclient);
-ion_bail:
- context_list_dtor(&me->clst);
-context_list_bail:
+bail:
return err;
}
@@ -795,96 +917,88 @@
static int fastrpc_release_current_dsp_process(void);
-static int fastrpc_internal_invoke(struct fastrpc_apps *me, uint32_t kernel,
- struct fastrpc_ioctl_invoke *invoke, remote_arg_t *pra,
- int *fds)
+static int fastrpc_internal_invoke(struct fastrpc_apps *me, uint32_t mode,
+ uint32_t kernel,
+ struct fastrpc_ioctl_invoke_fd *invokefd)
{
- remote_arg_t *rpra = 0;
- struct fastrpc_device *dev = 0;
struct smq_invoke_ctx *ctx = 0;
- struct fastrpc_buf obuf, *abufs = 0, *b;
- struct ion_handle **handles = NULL;
+ struct fastrpc_ioctl_invoke *invoke = &invokefd->inv;
int interrupted = 0;
- uint32_t sc;
- int i, bufs, nbufs = 0, err = 0;
+ int err = 0;
- sc = invoke->sc;
- obuf.handle = 0;
+ if (!kernel) {
+ VERIFY(err, 0 == context_restore_interrupted(me, invokefd,
+ &ctx));
+ if (err)
+ goto bail;
+ if (ctx)
+ goto wait;
+ }
+
+ VERIFY(err, 0 == context_alloc(me, kernel, invokefd, &ctx));
+ if (err)
+ goto bail;
+
if (me->smmu.enabled) {
VERIFY(err, 0 == iommu_attach_group(me->smmu.domain,
me->smmu.group));
if (err)
- return err;
+ goto bail;
+ ctx->smmu = 1;
}
- if (REMOTE_SCALARS_LENGTH(sc)) {
- VERIFY(err, 0 == get_dev(me, &dev));
+ if (REMOTE_SCALARS_LENGTH(ctx->sc)) {
+ VERIFY(err, 0 == get_dev(me, &ctx->dev));
if (err)
goto bail;
- VERIFY(err, 0 == get_page_list(kernel, sc, pra, &dev->buf,
- &obuf));
+ VERIFY(err, 0 == get_page_list(kernel, ctx->sc, ctx->pra,
+ &ctx->dev->buf, &ctx->obuf));
if (err)
goto bail;
- rpra = (remote_arg_t *)obuf.virt;
- VERIFY(err, 0 == get_args(kernel, sc, pra, rpra, invoke->pra,
- &obuf, &abufs, &nbufs, fds));
+ ctx->rpra = (remote_arg_t *)ctx->obuf.virt;
+ VERIFY(err, 0 == get_args(kernel, ctx->sc, ctx->pra, ctx->rpra,
+ invoke->pra, &ctx->obuf, &ctx->abufs,
+ &ctx->nbufs, ctx->fds, ctx->handles));
if (err)
goto bail;
}
- context_list_alloc_ctx(&me->clst, &ctx);
- inv_args_pre(sc, rpra);
- VERIFY(err, 0 == fastrpc_invoke_send(me, kernel, invoke->handle, sc,
- ctx, &obuf));
+ inv_args_pre(ctx->sc, ctx->rpra);
+ if (FASTRPC_MODE_SERIAL == mode)
+ inv_args(ctx->sc, ctx->rpra, ctx->obuf.used);
+ VERIFY(err, 0 == fastrpc_invoke_send(me, kernel, invoke->handle,
+ ctx->sc, ctx, &ctx->obuf));
if (err)
goto bail;
- inv_args(sc, rpra, obuf.used);
- VERIFY(err, 0 == (interrupted =
- wait_for_completion_interruptible(&ctx->work)));
- if (err)
- goto bail;
+ if (FASTRPC_MODE_PARALLEL == mode)
+ inv_args(ctx->sc, ctx->rpra, ctx->obuf.used);
+ wait:
+ if (kernel)
+ wait_for_completion(&ctx->work);
+ else {
+ interrupted = wait_for_completion_interruptible(&ctx->work);
+ VERIFY(err, 0 == (err = interrupted));
+ if (err)
+ goto bail;
+ }
VERIFY(err, 0 == (err = ctx->retval));
if (err)
goto bail;
- VERIFY(err, 0 == put_args(kernel, sc, pra, rpra, invoke->pra));
+ VERIFY(err, 0 == put_args(kernel, ctx->sc, ctx->pra, ctx->rpra,
+ invoke->pra));
if (err)
goto bail;
bail:
- if (interrupted) {
- if (!kernel)
- (void)fastrpc_release_current_dsp_process();
- wait_for_completion(&ctx->work);
- }
- context_free(ctx);
-
- if (me->smmu.enabled) {
- bufs = REMOTE_SCALARS_INBUFS(sc) + REMOTE_SCALARS_OUTBUFS(sc);
- if (fds) {
- handles = (struct ion_handle **)(fds + bufs);
- for (i = 0; i < bufs; i++)
- if (!IS_ERR_OR_NULL(handles[i])) {
- ion_unmap_iommu(me->iclient, handles[i],
- me->smmu.domain_id, 0);
- ion_free(me->iclient, handles[i]);
- }
- }
- iommu_detach_group(me->smmu.domain, me->smmu.group);
- }
- for (i = 0, b = abufs; i < nbufs; ++i, ++b)
- free_mem(b);
-
- kfree(abufs);
- if (dev) {
- add_dev(me, dev);
- if (obuf.handle != dev->buf.handle)
- free_mem(&obuf);
- }
+ if (ctx && interrupted == -ERESTARTSYS)
+ context_save_interrupted(ctx);
+ else if (ctx)
+ context_free(ctx, 1);
return err;
}
static int fastrpc_create_current_dsp_process(void)
{
int err = 0;
- struct fastrpc_ioctl_invoke ioctl;
+ struct fastrpc_ioctl_invoke_fd ioctl;
struct fastrpc_apps *me = &gfa;
remote_arg_t ra[1];
int tgid = 0;
@@ -892,10 +1006,12 @@
tgid = current->tgid;
ra[0].buf.pv = &tgid;
ra[0].buf.len = sizeof(tgid);
- ioctl.handle = 1;
- ioctl.sc = REMOTE_SCALARS_MAKE(0, 1, 0);
- ioctl.pra = ra;
- VERIFY(err, 0 == (err = fastrpc_internal_invoke(me, 1, &ioctl, ra, 0)));
+ ioctl.inv.handle = 1;
+ ioctl.inv.sc = REMOTE_SCALARS_MAKE(0, 1, 0);
+ ioctl.inv.pra = ra;
+ ioctl.fds = 0;
+ VERIFY(err, 0 == (err = fastrpc_internal_invoke(me,
+ FASTRPC_MODE_PARALLEL, 1, &ioctl)));
return err;
}
@@ -903,17 +1019,19 @@
{
int err = 0;
struct fastrpc_apps *me = &gfa;
- struct fastrpc_ioctl_invoke ioctl;
+ struct fastrpc_ioctl_invoke_fd ioctl;
remote_arg_t ra[1];
int tgid = 0;
tgid = current->tgid;
ra[0].buf.pv = &tgid;
ra[0].buf.len = sizeof(tgid);
- ioctl.handle = 1;
- ioctl.sc = REMOTE_SCALARS_MAKE(1, 1, 0);
- ioctl.pra = ra;
- VERIFY(err, 0 == (err = fastrpc_internal_invoke(me, 1, &ioctl, ra, 0)));
+ ioctl.inv.handle = 1;
+ ioctl.inv.sc = REMOTE_SCALARS_MAKE(1, 1, 0);
+ ioctl.inv.pra = ra;
+ ioctl.fds = 0;
+ VERIFY(err, 0 == (err = fastrpc_internal_invoke(me,
+ FASTRPC_MODE_PARALLEL, 1, &ioctl)));
return err;
}
@@ -922,7 +1040,7 @@
struct smq_phy_page *pages,
int num)
{
- struct fastrpc_ioctl_invoke ioctl;
+ struct fastrpc_ioctl_invoke_fd ioctl;
remote_arg_t ra[3];
int err = 0;
struct {
@@ -948,10 +1066,12 @@
ra[2].buf.pv = &routargs;
ra[2].buf.len = sizeof(routargs);
- ioctl.handle = 1;
- ioctl.sc = REMOTE_SCALARS_MAKE(2, 2, 1);
- ioctl.pra = ra;
- VERIFY(err, 0 == (err = fastrpc_internal_invoke(me, 1, &ioctl, ra, 0)));
+ ioctl.inv.handle = 1;
+ ioctl.inv.sc = REMOTE_SCALARS_MAKE(2, 2, 1);
+ ioctl.inv.pra = ra;
+ ioctl.fds = 0;
+ VERIFY(err, 0 == (err = fastrpc_internal_invoke(me,
+ FASTRPC_MODE_PARALLEL, 1, &ioctl)));
mmap->vaddrout = routargs.vaddrout;
if (err)
goto bail;
@@ -962,7 +1082,7 @@
static int fastrpc_munmap_on_dsp(struct fastrpc_apps *me,
struct fastrpc_ioctl_munmap *munmap)
{
- struct fastrpc_ioctl_invoke ioctl;
+ struct fastrpc_ioctl_invoke_fd ioctl;
remote_arg_t ra[1];
int err = 0;
struct {
@@ -977,10 +1097,12 @@
ra[0].buf.pv = &inargs;
ra[0].buf.len = sizeof(inargs);
- ioctl.handle = 1;
- ioctl.sc = REMOTE_SCALARS_MAKE(3, 1, 0);
- ioctl.pra = ra;
- VERIFY(err, 0 == (err = fastrpc_internal_invoke(me, 1, &ioctl, ra, 0)));
+ ioctl.inv.handle = 1;
+ ioctl.inv.sc = REMOTE_SCALARS_MAKE(3, 1, 0);
+ ioctl.inv.pra = ra;
+ ioctl.fds = 0;
+ VERIFY(err, 0 == (err = fastrpc_internal_invoke(me,
+ FASTRPC_MODE_PARALLEL, 1, &ioctl)));
return err;
}
@@ -1022,7 +1144,7 @@
struct fastrpc_mmap *map = 0;
struct smq_phy_page *pages = 0;
void *buf;
- int len;
+ unsigned long len;
int num;
int err = 0;
@@ -1043,9 +1165,22 @@
VERIFY(err, 0 != (pages = kzalloc(num * sizeof(*pages), GFP_KERNEL)));
if (err)
goto bail;
- VERIFY(err, 0 < (num = buf_get_pages(buf, len, num, 1, pages, num)));
- if (err)
- goto bail;
+
+ if (me->smmu.enabled) {
+ VERIFY(err, 0 == ion_map_iommu(clnt, map->handle,
+ me->smmu.domain_id, 0,
+ SZ_4K, 0, &map->phys, &len, 0, 0));
+ if (err)
+ goto bail;
+ pages->addr = map->phys;
+ pages->size = len;
+ num = 1;
+ } else {
+ VERIFY(err, 0 < (num = buf_get_pages(buf, len, num, 1,
+ pages, num)));
+ if (err)
+ goto bail;
+ }
VERIFY(err, 0 == fastrpc_mmap_on_dsp(me, mmap, pages, num));
if (err)
@@ -1093,13 +1228,26 @@
return;
}
+static void fastrpc_channel_close(struct kref *kref)
+{
+ struct fastrpc_apps *me = &gfa;
+
+ smd_close(me->chan);
+ me->chan = 0;
+ mutex_unlock(&me->smd_mutex);
+ pr_info("'closed /dev/%s c %d 0'\n", DEVICE_NAME,
+ MAJOR(me->dev_no));
+}
+
static int fastrpc_device_release(struct inode *inode, struct file *file)
{
struct file_data *fdata = (struct file_data *)file->private_data;
+ struct fastrpc_apps *me = &gfa;
+
(void)fastrpc_release_current_dsp_process();
cleanup_current_dev();
if (fdata) {
- struct fastrpc_mmap *map;
+ struct fastrpc_mmap *map = 0;
struct hlist_node *n, *pos;
file->private_data = 0;
hlist_for_each_entry_safe(map, pos, n, &fdata->hlst, hn) {
@@ -1108,6 +1256,8 @@
kfree(map);
}
kfree(fdata);
+ kref_put_mutex(&me->kref, fastrpc_channel_close,
+ &me->smd_mutex);
}
return 0;
}
@@ -1115,6 +1265,25 @@
static int fastrpc_device_open(struct inode *inode, struct file *filp)
{
int err = 0;
+ struct fastrpc_apps *me = &gfa;
+
+ mutex_lock(&me->smd_mutex);
+ if (kref_get_unless_zero(&me->kref) == 0) {
+ VERIFY(err, 0 == smd_named_open_on_edge(FASTRPC_SMD_GUID,
+ SMD_APPS_QDSP, &me->chan,
+ me, smd_event_handler));
+ if (err)
+ goto smd_bail;
+ VERIFY(err, 0 != wait_for_completion_timeout(&me->work,
+ RPC_TIMEOUT));
+ if (err)
+ goto completion_bail;
+ kref_init(&me->kref);
+ pr_info("'opened /dev/%s c %d 0'\n", DEVICE_NAME,
+ MAJOR(me->dev_no));
+ }
+ mutex_unlock(&me->smd_mutex);
+
filp->private_data = 0;
if (0 != try_module_get(THIS_MODULE)) {
struct file_data *fdata = 0;
@@ -1136,10 +1305,19 @@
if (err) {
cleanup_current_dev();
kfree(fdata);
+ kref_put_mutex(&me->kref, fastrpc_channel_close,
+ &me->smd_mutex);
}
module_put(THIS_MODULE);
}
return err;
+
+completion_bail:
+ smd_close(me->chan);
+ me->chan = 0;
+smd_bail:
+ mutex_unlock(&me->smd_mutex);
+ return err;
}
@@ -1148,48 +1326,23 @@
{
struct fastrpc_apps *me = &gfa;
struct fastrpc_ioctl_invoke_fd invokefd;
- struct fastrpc_ioctl_invoke *invoke = &invokefd.inv;
struct fastrpc_ioctl_mmap mmap;
struct fastrpc_ioctl_munmap munmap;
- remote_arg_t *pra = 0;
void *param = (char *)ioctl_param;
struct file_data *fdata = (struct file_data *)file->private_data;
- int *fds = 0;
- int bufs, size = 0, err = 0;
+ int size = 0, err = 0;
switch (ioctl_num) {
case FASTRPC_IOCTL_INVOKE_FD:
case FASTRPC_IOCTL_INVOKE:
invokefd.fds = 0;
size = (ioctl_num == FASTRPC_IOCTL_INVOKE) ?
- sizeof(*invoke) : sizeof(invokefd);
+ sizeof(invokefd.inv) : sizeof(invokefd);
VERIFY(err, 0 == copy_from_user(&invokefd, param, size));
if (err)
goto bail;
- bufs = REMOTE_SCALARS_INBUFS(invoke->sc) +
- REMOTE_SCALARS_OUTBUFS(invoke->sc);
- if (bufs) {
- size = bufs * sizeof(*pra);
- if (invokefd.fds)
- size = size + bufs * sizeof(*fds) +
- bufs * sizeof(struct ion_handle *);
- VERIFY(err, 0 != (pra = kzalloc(size, GFP_KERNEL)));
- if (err)
- goto bail;
- }
- VERIFY(err, 0 == copy_from_user(pra, invoke->pra,
- bufs * sizeof(*pra)));
- if (err)
- goto bail;
- if (invokefd.fds) {
- fds = (int *)(pra + bufs);
- VERIFY(err, 0 == copy_from_user(fds, invokefd.fds,
- bufs * sizeof(*fds)));
- if (err)
- goto bail;
- }
- VERIFY(err, 0 == (err = fastrpc_internal_invoke(me, 0, invoke,
- pra, fds)));
+ VERIFY(err, 0 == (err = fastrpc_internal_invoke(me, fdata->mode,
+ 0, &invokefd)));
if (err)
goto bail;
break;
@@ -1216,12 +1369,22 @@
if (err)
goto bail;
break;
+ case FASTRPC_IOCTL_SETMODE:
+ switch ((uint32_t)ioctl_param) {
+ case FASTRPC_MODE_PARALLEL:
+ case FASTRPC_MODE_SERIAL:
+ fdata->mode = (uint32_t)ioctl_param;
+ break;
+ default:
+ err = -ENOTTY;
+ break;
+ }
+ break;
default:
err = -ENOTTY;
break;
}
bail:
- kfree(pra);
return err;
}
@@ -1248,7 +1411,7 @@
VERIFY(err, 0 == cdev_add(&me->cdev, MKDEV(MAJOR(me->dev_no), 0), 1));
if (err)
goto cdev_init_bail;
- me->class = class_create(THIS_MODULE, "chardrv");
+ me->class = class_create(THIS_MODULE, "fastrpc");
VERIFY(err, !IS_ERR(me->class));
if (err)
goto class_create_bail;
@@ -1257,7 +1420,6 @@
VERIFY(err, !IS_ERR(me->dev));
if (err)
goto device_create_bail;
- pr_info("'created /dev/%s c %d 0'\n", DEVICE_NAME, MAJOR(me->dev_no));
return 0;
@@ -1277,7 +1439,9 @@
{
struct fastrpc_apps *me = &gfa;
+ context_list_dtor(me, &me->clst);
fastrpc_deinit();
+ cleanup_current_dev();
device_destroy(me->class, MKDEV(MAJOR(me->dev_no), 0));
class_destroy(me->class);
cdev_del(&me->cdev);
diff --git a/drivers/char/adsprpc_shared.h b/drivers/char/adsprpc_shared.h
index da70eb5..f5d7450 100644
--- a/drivers/char/adsprpc_shared.h
+++ b/drivers/char/adsprpc_shared.h
@@ -20,9 +20,16 @@
#define FASTRPC_IOCTL_MMAP _IOWR('R', 2, struct fastrpc_ioctl_mmap)
#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 3, struct fastrpc_ioctl_munmap)
#define FASTRPC_IOCTL_INVOKE_FD _IOWR('R', 4, struct fastrpc_ioctl_invoke_fd)
+#define FASTRPC_IOCTL_SETMODE _IOWR('R', 5, uint32_t)
#define FASTRPC_SMD_GUID "fastrpcsmd-apps-dsp"
#define DEVICE_NAME "adsprpc-smd"
+/* Driver should operate in parallel with the co-processor */
+#define FASTRPC_MODE_PARALLEL 0
+
+/* Driver should operate in serial mode with the co-processor */
+#define FASTRPC_MODE_SERIAL 1
+
/* Retrives number of input buffers from the scalars parameter */
#define REMOTE_SCALARS_INBUFS(sc) (((sc) >> 16) & 0x0ff)
diff --git a/drivers/char/diag/diag_dci.c b/drivers/char/diag/diag_dci.c
index 91b90a8..2dbb2f5 100644
--- a/drivers/char/diag/diag_dci.c
+++ b/drivers/char/diag/diag_dci.c
@@ -124,45 +124,131 @@
return 0;
}
+static struct dci_pkt_req_entry_t *diag_register_dci_transaction(int uid)
+{
+ struct dci_pkt_req_entry_t *entry = NULL;
+ entry = kzalloc(sizeof(struct dci_pkt_req_entry_t), GFP_KERNEL);
+ if (!entry)
+ return NULL;
+
+ mutex_lock(&driver->dci_mutex);
+ driver->dci_tag++;
+ entry->pid = current->tgid;
+ entry->uid = uid;
+ entry->tag = driver->dci_tag;
+ list_add_tail(&entry->track, &driver->dci_req_list);
+ mutex_unlock(&driver->dci_mutex);
+
+ return entry;
+}
+
+static struct dci_pkt_req_entry_t *diag_dci_get_request_entry(int tag)
+{
+ struct list_head *start, *temp;
+ struct dci_pkt_req_entry_t *entry = NULL;
+ list_for_each_safe(start, temp, &driver->dci_req_list) {
+ entry = list_entry(start, struct dci_pkt_req_entry_t, track);
+ if (entry->tag == tag)
+ return entry;
+ }
+ return NULL;
+}
+
+static int diag_dci_remove_req_entry(unsigned char *buf, int len,
+ struct dci_pkt_req_entry_t *entry)
+{
+ uint16_t rsp_count = 0, delayed_rsp_id = 0;
+ if (!buf || len <= 0 || !entry) {
+ pr_err("diag: In %s, invalid input buf: %p, len: %d, entry: %p\n",
+ __func__, buf, len, entry);
+ return -EIO;
+ }
+
+ /* It is an immediate response, delete it from the table */
+ if (*buf != 0x80) {
+ list_del(&entry->track);
+ kfree(entry);
+ return 1;
+ }
+
+ /* It is a delayed response. Check if the length is valid */
+ if (len < MIN_DELAYED_RSP_LEN) {
+ pr_err("diag: Invalid delayed rsp packet length %d\n", len);
+ return -EINVAL;
+ }
+
+ /*
+ * If the delayed response id field (uint16_t at byte 8) is 0 then
+ * there is only one response and we can remove the request entry.
+ */
+ delayed_rsp_id = *(uint16_t *)(buf + 8);
+ if (delayed_rsp_id == 0) {
+ list_del(&entry->track);
+ kfree(entry);
+ return 1;
+ }
+
+ /*
+ * Check the response count field (uint16 at byte 10). The request
+ * entry can be deleted it it is the last response in the sequence.
+ * It is the last response in the sequence if the response count
+ * is 1 or if the signed bit gets dropped.
+ */
+ rsp_count = *(uint16_t *)(buf + 10);
+ if (rsp_count > 0 && rsp_count < 0x1000) {
+ list_del(&entry->track);
+ kfree(entry);
+ return 1;
+ }
+
+ return 0;
+}
+
void extract_dci_pkt_rsp(struct diag_smd_info *smd_info, unsigned char *buf)
{
- int i = 0, index = -1, cmd_code_len = 1;
- int curr_client_pid = 0, write_len;
+ int i = 0, cmd_code_len = 1;
+ int curr_client_pid = 0, write_len, *tag = NULL;
struct diag_dci_client_tbl *entry;
void *temp_buf = NULL;
- uint8_t recv_pkt_cmd_code;
-
+ uint8_t recv_pkt_cmd_code, delete_flag = 0;
+ struct dci_pkt_req_entry_t *req_entry = NULL;
recv_pkt_cmd_code = *(uint8_t *)(buf+4);
if (recv_pkt_cmd_code != DCI_PKT_RSP_CODE)
cmd_code_len = 4; /* delayed response */
write_len = (int)(*(uint16_t *)(buf+2)) - cmd_code_len;
pr_debug("diag: len = %d\n", write_len);
- /* look up DCI client with tag */
- for (i = 0; i < dci_max_reg; i++) {
- if (driver->req_tracking_tbl[i].tag ==
- *(int *)(buf+(4+cmd_code_len))) {
- *(int *)(buf+4+cmd_code_len) =
- driver->req_tracking_tbl[i].uid;
- curr_client_pid =
- driver->req_tracking_tbl[i].pid;
- index = i;
- break;
- }
- }
- if (index == -1) {
+ tag = (int *)(buf + (4 + cmd_code_len)); /* Retrieve the Tag field */
+ req_entry = diag_dci_get_request_entry(*tag);
+ if (!req_entry) {
pr_alert("diag: No matching PID for DCI data\n");
return;
}
+ *tag = req_entry->uid;
+ curr_client_pid = req_entry->pid;
+
+ /* Remove the headers and send only the response to this function */
+ delete_flag = diag_dci_remove_req_entry(buf + 8 + cmd_code_len,
+ write_len - 4,
+ req_entry);
+ if (delete_flag < 0)
+ return;
+
/* Using PID of client process, find client buffer */
i = diag_dci_find_client_index(curr_client_pid);
if (i != DCI_CLIENT_INDEX_INVALID) {
/* copy pkt rsp in client buf */
entry = &(driver->dci_client_tbl[i]);
mutex_lock(&entry->data_mutex);
- if (DCI_CHK_CAPACITY(entry, 8+write_len)) {
+ /*
+ * Check if we can fit the data in the rsp buffer. The total
+ * length of the rsp is the rsp length (write_len) +
+ * DCI_PKT_RSP_TYPE header (int) + field for length (int) +
+ * delete_flag (uint8_t)
+ */
+ if (DCI_CHK_CAPACITY(entry, 9+write_len)) {
pr_alert("diag: create capacity for pkt rsp\n");
- entry->total_capacity += 8+write_len;
+ entry->total_capacity += 9+write_len;
temp_buf = krealloc(entry->dci_data,
entry->total_capacity, GFP_KERNEL);
if (!temp_buf) {
@@ -179,13 +265,12 @@
*(int *)(entry->dci_data+entry->data_len)
= write_len;
entry->data_len += 4;
+ *(uint8_t *)(entry->dci_data + entry->data_len) = delete_flag;
+ entry->data_len += sizeof(uint8_t);
memcpy(entry->dci_data+entry->data_len,
buf+4+cmd_code_len, write_len);
entry->data_len += write_len;
mutex_unlock(&entry->data_mutex);
- /* delete immediate response entry */
- if (smd_info->buf_in_1[8+cmd_code_len] != 0x80)
- driver->req_tracking_tbl[index].pid = 0;
}
}
@@ -433,8 +518,8 @@
} /* end of loop for all DCI clients */
}
-int diag_send_dci_pkt(struct diag_master_table entry, unsigned char *buf,
- int len, int index)
+static int diag_send_dci_pkt(struct diag_master_table entry, unsigned char *buf,
+ int len, int tag)
{
int i, status = 0;
unsigned int read_len = 0;
@@ -459,8 +544,7 @@
driver->apps_dci_buf[1] = 1; /* version */
*(uint16_t *)(driver->apps_dci_buf + 2) = len + 4 + 1; /* length */
driver->apps_dci_buf[4] = DCI_PKT_RSP_CODE;
- *(int *)(driver->apps_dci_buf + 5) =
- driver->req_tracking_tbl[index].tag;
+ *(int *)(driver->apps_dci_buf + 5) = tag;
for (i = 0; i < len; i++)
driver->apps_dci_buf[i+9] = *(buf+i);
read_len += len;
@@ -494,42 +578,17 @@
return status;
}
-int diag_register_dci_transaction(int uid)
-{
- int i, new_dci_client = 1, ret = -1;
-
- for (i = 0; i < dci_max_reg; i++) {
- if (driver->req_tracking_tbl[i].pid == current->tgid) {
- new_dci_client = 0;
- break;
- }
- }
- mutex_lock(&driver->dci_mutex);
- /* Make an entry in kernel DCI table */
- driver->dci_tag++;
- for (i = 0; i < dci_max_reg; i++) {
- if (driver->req_tracking_tbl[i].pid == 0) {
- driver->req_tracking_tbl[i].pid = current->tgid;
- driver->req_tracking_tbl[i].uid = uid;
- driver->req_tracking_tbl[i].tag = driver->dci_tag;
- ret = i;
- break;
- }
- }
- mutex_unlock(&driver->dci_mutex);
- return ret;
-}
-
int diag_process_dci_transaction(unsigned char *buf, int len)
{
unsigned char *temp = buf;
uint16_t subsys_cmd_code, log_code, item_num;
- int subsys_id, cmd_code, ret = -1, index = -1, found = 0;
+ int subsys_id, cmd_code, ret = -1, found = 0;
struct diag_master_table entry;
int count, set_mask, num_codes, bit_index, event_id, offset = 0, i;
unsigned int byte_index, read_len = 0;
uint8_t equip_id, *log_mask_ptr, *head_log_mask_ptr, byte_mask;
uint8_t *event_mask_ptr;
+ struct dci_pkt_req_entry_t *req_entry = NULL;
if (!driver->smd_dci[MODEM_DATA].ch) {
pr_err("diag: DCI smd channel for peripheral %d not valid for dci updates\n",
@@ -550,8 +609,8 @@
return -EIO;
}
/* enter this UID into kernel table and return index */
- index = diag_register_dci_transaction(*(int *)temp);
- if (index < 0) {
+ req_entry = diag_register_dci_transaction(*(int *)temp);
+ if (!req_entry) {
pr_alert("diag: registering new DCI transaction failed\n");
return DIAG_DCI_NO_REG;
}
@@ -581,7 +640,8 @@
entry.cmd_code_lo <= subsys_cmd_code &&
entry.cmd_code_hi >= subsys_cmd_code) {
ret = diag_send_dci_pkt(entry, buf,
- len, index);
+ len,
+ req_entry->tag);
} else if (entry.cmd_code == 255
&& cmd_code == 75) {
if (entry.subsys_id == subsys_id &&
@@ -590,7 +650,8 @@
entry.cmd_code_hi >=
subsys_cmd_code) {
ret = diag_send_dci_pkt(entry,
- buf, len, index);
+ buf, len,
+ req_entry->tag);
}
} else if (entry.cmd_code == 255 &&
entry.subsys_id == 255) {
@@ -598,7 +659,8 @@
entry.cmd_code_hi >=
cmd_code) {
ret = diag_send_dci_pkt(entry,
- buf, len, index);
+ buf, len,
+ req_entry->tag);
}
}
}
@@ -883,7 +945,7 @@
void *buf = driver->buf_event_mask_update;
int header_size = sizeof(struct diag_ctrl_event_mask);
int wr_size = -ENOMEM, retry_count = 0, timer;
- int ret = DIAG_DCI_NO_ERROR;
+ int ret = DIAG_DCI_NO_ERROR, i;
mutex_lock(&driver->diag_cntl_mutex);
/* send event mask update */
@@ -891,8 +953,14 @@
driver->event_mask->data_len = 7 + DCI_EVENT_MASK_SIZE;
driver->event_mask->stream_id = DCI_MASK_STREAM;
driver->event_mask->status = 3; /* status for valid mask */
- driver->event_mask->event_config = 1; /* event config */
+ driver->event_mask->event_config = 0; /* event config */
driver->event_mask->event_mask_size = DCI_EVENT_MASK_SIZE;
+ for (i = 0; i < DCI_EVENT_MASK_SIZE; i++) {
+ if (dci_cumulative_event_mask[i] != 0) {
+ driver->event_mask->event_config = 1;
+ break;
+ }
+ }
memcpy(buf, driver->event_mask, header_size);
memcpy(buf+header_size, dci_cumulative_event_mask, DCI_EVENT_MASK_SIZE);
if (ch) {
@@ -1227,13 +1295,6 @@
goto err;
}
}
-
- if (driver->req_tracking_tbl == NULL) {
- driver->req_tracking_tbl = kzalloc(dci_max_reg *
- sizeof(struct dci_pkt_req_tracking_tbl), GFP_KERNEL);
- if (driver->req_tracking_tbl == NULL)
- goto err;
- }
if (driver->apps_dci_buf == NULL) {
driver->apps_dci_buf = kzalloc(APPS_BUF_SIZE, GFP_KERNEL);
if (driver->apps_dci_buf == NULL)
@@ -1246,6 +1307,7 @@
goto err;
}
driver->diag_dci_wq = create_singlethread_workqueue("diag_dci_wq");
+ INIT_LIST_HEAD(&driver->dci_req_list);
success = platform_driver_register(&msm_diag_dci_driver);
if (success) {
pr_err("diag: Could not register DCI driver\n");
@@ -1261,7 +1323,6 @@
return DIAG_DCI_NO_ERROR;
err:
pr_err("diag: Could not initialize diag DCI buffers");
- kfree(driver->req_tracking_tbl);
kfree(driver->dci_client_tbl);
kfree(driver->apps_dci_buf);
for (i = 0; i < NUM_SMD_DCI_CHANNELS; i++)
@@ -1302,7 +1363,7 @@
platform_driver_unregister(&msm_diag_dci_cmd_driver);
}
- kfree(driver->req_tracking_tbl);
+
kfree(driver->dci_client_tbl);
kfree(driver->apps_dci_buf);
mutex_destroy(&driver->dci_mutex);
diff --git a/drivers/char/diag/diag_dci.h b/drivers/char/diag/diag_dci.h
index e2c4158..c9be39a 100644
--- a/drivers/char/diag/diag_dci.h
+++ b/drivers/char/diag/diag_dci.h
@@ -24,7 +24,7 @@
#define DISABLE_LOG_MASK 0
#define MAX_EVENT_SIZE 512
#define DCI_CLIENT_INDEX_INVALID -1
-#define DCI_PKT_REQ_MIN_LEN 8
+#define DCI_PKT_REQ_MIN_LEN 5
#define DCI_LOG_CON_MIN_LEN 14
#define DCI_EVENT_CON_MIN_LEN 16
@@ -42,15 +42,18 @@
#define DCI_MAX_LOG_CODES 16
#define DCI_MAX_ITEMS_PER_LOG_CODE 512
+#define MIN_DELAYED_RSP_LEN 12
+
extern unsigned int dci_max_reg;
extern unsigned int dci_max_clients;
extern struct mutex dci_health_mutex;
-struct dci_pkt_req_tracking_tbl {
+struct dci_pkt_req_entry_t {
int pid;
int uid;
int tag;
-};
+ struct list_head track;
+} __packed;
struct diag_dci_client_tbl {
struct task_struct *client;
@@ -115,8 +118,6 @@
int diag_process_smd_dci_read_data(struct diag_smd_info *smd_info, void *buf,
int recd_bytes);
int diag_process_dci_transaction(unsigned char *buf, int len);
-int diag_send_dci_pkt(struct diag_master_table entry, unsigned char *buf,
- int len, int index);
void extract_dci_pkt_rsp(struct diag_smd_info *smd_info, unsigned char *buf);
int diag_dci_find_client_index(int client_id);
/* DCI Log streaming functions */
diff --git a/drivers/char/diag/diagchar.h b/drivers/char/diag/diagchar.h
index 5be77c4..606953d 100644
--- a/drivers/char/diag/diagchar.h
+++ b/drivers/char/diag/diagchar.h
@@ -301,7 +301,7 @@
/* Whether or not the peripheral supports STM */
int peripheral_supports_stm[NUM_SMD_CONTROL_CHANNELS];
/* DCI related variables */
- struct dci_pkt_req_tracking_tbl *req_tracking_tbl;
+ struct list_head dci_req_list;
struct diag_dci_client_tbl *dci_client_tbl;
int dci_tag;
int dci_client_id;
@@ -348,6 +348,7 @@
int separate_cmdrsp[NUM_SMD_CONTROL_CHANNELS];
unsigned char *usb_buf_out;
unsigned char *apps_rsp_buf;
+ unsigned char *user_space_data_buf;
/* buffer for updating mask to peripherals */
unsigned char *buf_msg_mask_update;
unsigned char *buf_log_mask_update;
diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c
index f7c0d24..6ead0ad 100644
--- a/drivers/char/diag/diagchar_core.c
+++ b/drivers/char/diag/diagchar_core.c
@@ -878,6 +878,8 @@
struct diag_log_event_stats le_stats;
struct diagpkt_delay_params delay_params;
struct real_time_vote_t rt_vote;
+ struct list_head *start, *req_temp;
+ struct dci_pkt_req_entry_t *req_entry = NULL;
switch (iocmd) {
case DIAG_IOCTL_COMMAND_REG:
@@ -993,10 +995,16 @@
}
result = i;
/* Delete this process from DCI table */
- for (i = 0; i < dci_max_reg; i++)
- if (driver->req_tracking_tbl[i].pid ==
- current->tgid)
- driver->req_tracking_tbl[i].pid = 0;
+ list_for_each_safe(start, req_temp,
+ &driver->dci_req_list) {
+ req_entry = list_entry(start,
+ struct dci_pkt_req_entry_t,
+ track);
+ if (req_entry->pid == current->tgid) {
+ list_del(&req_entry->track);
+ kfree(req_entry);
+ }
+ }
driver->dci_client_tbl[result].client = NULL;
kfree(driver->dci_client_tbl[result].dci_data);
driver->dci_client_tbl[result].dci_data = NULL;
@@ -1609,22 +1617,15 @@
goto fail_free_hdlc;
}
if (pkt_type == USER_SPACE_DATA_TYPE) {
- user_space_data = diagmem_alloc(driver, payload_size,
- POOL_TYPE_USER);
- if (!user_space_data) {
- driver->dropped_count++;
- return -ENOMEM;
- }
- err = copy_from_user(user_space_data, buf + 4,
+ err = copy_from_user(driver->user_space_data_buf, buf + 4,
payload_size);
if (err) {
pr_err("diag: copy failed for user space data\n");
- diagmem_free(driver, user_space_data, POOL_TYPE_USER);
- user_space_data = NULL;
return -EIO;
}
/* Check for proc_type */
- remote_proc = diag_get_remote(*(int *)user_space_data);
+ remote_proc =
+ diag_get_remote(*(int *)driver->user_space_data_buf);
if (remote_proc) {
token_offset = 4;
@@ -1634,12 +1635,9 @@
/* Check masks for On-Device logging */
if (driver->mask_check) {
- if (!mask_request_validate(user_space_data +
+ if (!mask_request_validate(driver->user_space_data_buf +
token_offset)) {
pr_alert("diag: mask request Invalid\n");
- diagmem_free(driver, user_space_data,
- POOL_TYPE_USER);
- user_space_data = NULL;
return -EFAULT;
}
}
@@ -1647,7 +1645,7 @@
#ifdef DIAG_DEBUG
pr_debug("diag: user space data %d\n", payload_size);
for (i = 0; i < payload_size; i++)
- pr_debug("\t %x", *((user_space_data
+ pr_debug("\t %x", *((driver->user_space_data_buf
+ token_offset)+i));
#endif
#ifdef CONFIG_DIAG_SDIO_PIPE
@@ -1658,7 +1656,7 @@
payload_size));
if (driver->sdio_ch && (payload_size > 0)) {
sdio_write(driver->sdio_ch, (void *)
- (user_space_data + token_offset),
+ (driver->user_space_data_buf + token_offset),
payload_size);
}
}
@@ -1689,8 +1687,8 @@
diag_hsic[index].in_busy_hsic_read_on_device =
0;
err = diag_bridge_write(index,
- user_space_data + token_offset,
- payload_size);
+ driver->user_space_data_buf +
+ token_offset, payload_size);
if (err) {
pr_err("diag: err sending mask to MDM: %d\n",
err);
@@ -1711,14 +1709,12 @@
&& driver->lcid) {
if (payload_size > 0) {
err = msm_smux_write(driver->lcid, NULL,
- user_space_data + token_offset,
+ driver->user_space_data_buf +
+ token_offset,
payload_size);
if (err) {
pr_err("diag:send mask to MDM err %d",
err);
- diagmem_free(driver, user_space_data,
- POOL_TYPE_USER);
- user_space_data = NULL;
return err;
}
}
@@ -1727,9 +1723,8 @@
/* send masks to 8k now */
if (!remote_proc)
diag_process_hdlc((void *)
- (user_space_data + token_offset), payload_size);
- diagmem_free(driver, user_space_data, POOL_TYPE_USER);
- user_space_data = NULL;
+ (driver->user_space_data_buf + token_offset),
+ payload_size);
return 0;
}
diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c
index ba3ecc2..395bea0 100644
--- a/drivers/char/diag/diagfwd.c
+++ b/drivers/char/diag/diagfwd.c
@@ -2480,7 +2480,7 @@
driver->buf_tbl_size = (buf_tbl_size < driver->poolsize_hdlc) ?
driver->poolsize_hdlc : buf_tbl_size;
driver->supports_separate_cmdrsp = device_supports_separate_cmdrsp();
- driver->supports_apps_hdlc_encoding = 0;
+ driver->supports_apps_hdlc_encoding = 1;
mutex_init(&driver->diag_hdlc_mutex);
mutex_init(&driver->diag_cntl_mutex);
@@ -2520,6 +2520,12 @@
&& (driver->hdlc_buf = kzalloc(HDLC_MAX, GFP_KERNEL)) == NULL)
goto err;
kmemleak_not_leak(driver->hdlc_buf);
+ if (driver->user_space_data_buf == NULL)
+ driver->user_space_data_buf = kzalloc(USER_SPACE_DATA,
+ GFP_KERNEL);
+ if (driver->user_space_data_buf == NULL)
+ goto err;
+ kmemleak_not_leak(driver->user_space_data_buf);
if (driver->client_map == NULL &&
(driver->client_map = kzalloc
((driver->num_clients) * sizeof(struct diag_client_map),
@@ -2607,6 +2613,7 @@
kfree(driver->pkt_buf);
kfree(driver->usb_read_ptr);
kfree(driver->apps_rsp_buf);
+ kfree(driver->user_space_data_buf);
if (driver->diag_wq)
destroy_workqueue(driver->diag_wq);
}
@@ -2646,5 +2653,6 @@
kfree(driver->pkt_buf);
kfree(driver->usb_read_ptr);
kfree(driver->apps_rsp_buf);
+ kfree(driver->user_space_data_buf);
destroy_workqueue(driver->diag_wq);
}
diff --git a/drivers/char/hw_random/msm_rng.c b/drivers/char/hw_random/msm_rng.c
index 369477f..4118a7a 100644
--- a/drivers/char/hw_random/msm_rng.c
+++ b/drivers/char/hw_random/msm_rng.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -25,6 +25,9 @@
#include <mach/msm_iomap.h>
#include <mach/socinfo.h>
#include <mach/msm_bus.h>
+#include <linux/qrng.h>
+#include <linux/fs.h>
+#include <linux/cdev.h>
#define DRIVER_NAME "msm_rng"
@@ -51,6 +54,29 @@
uint32_t qrng_perf_client;
};
+struct msm_rng_device msm_rng_device_info;
+
+static long msm_rng_ioctl(struct file *filp, unsigned int cmd,
+ unsigned long arg)
+{
+ long ret = 0;
+
+ pr_debug("ioctl: cmd = %d\n", cmd);
+ switch (cmd) {
+ case QRNG_IOCTL_RESET_BUS_BANDWIDTH:
+ pr_info("calling msm_rng_bus_scale(LOW)\n");
+ ret = msm_bus_scale_client_update_request(
+ msm_rng_device_info.qrng_perf_client, 0);
+ if (ret)
+ pr_err("failed qrng_reset_bus_bw, ret = %ld\n", ret);
+ break;
+ default:
+ pr_err("Unsupported IOCTL call");
+ break;
+ }
+ return ret;
+}
+
static int msm_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
{
struct msm_rng_device *msm_rng_dev;
@@ -79,12 +105,6 @@
dev_err(&pdev->dev, "failed to enable clock in callback\n");
return 0;
}
- if (msm_rng_dev->qrng_perf_client) {
- ret = msm_bus_scale_client_update_request(
- msm_rng_dev->qrng_perf_client, 1);
- if (ret)
- pr_err("bus_scale_client_update_req failed!\n");
- }
/* read random data from h/w */
do {
/* check status bit if data is available */
@@ -104,9 +124,6 @@
if ((maxsize - currsize) < 4)
break;
} while (currsize < maxsize);
- if (msm_rng_dev->qrng_perf_client)
- ret = msm_bus_scale_client_update_request(
- msm_rng_dev->qrng_perf_client, 0);
/* vote to turn off clock */
clk_disable_unprepare(msm_rng_dev->prng_clk);
@@ -161,19 +178,24 @@
mb();
}
clk_disable_unprepare(msm_rng_dev->prng_clk);
- if (msm_rng_dev->qrng_perf_client)
- ret = msm_bus_scale_client_update_request(
- msm_rng_dev->qrng_perf_client, 0);
-
return 0;
}
+static const struct file_operations msm_rng_fops = {
+ .unlocked_ioctl = msm_rng_ioctl,
+};
+static struct class *msm_rng_class;
+static struct cdev msm_rng_cdev;
+
static int __devinit msm_rng_probe(struct platform_device *pdev)
{
struct resource *res;
struct msm_rng_device *msm_rng_dev = NULL;
void __iomem *base = NULL;
int error = 0;
+ int ret = 0;
+ struct device *dev;
+
struct msm_bus_scale_pdata *qrng_platform_support = NULL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -220,6 +242,8 @@
qrng_platform_support = msm_bus_cl_get_pdata(pdev);
msm_rng_dev->qrng_perf_client = msm_bus_scale_register_client(
qrng_platform_support);
+ msm_rng_device_info.qrng_perf_client =
+ msm_rng_dev->qrng_perf_client;
if (!msm_rng_dev->qrng_perf_client)
pr_err("Unable to register bus client\n");
}
@@ -238,9 +262,27 @@
error = -EPERM;
goto rollback_clk;
}
+ ret = register_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME, &msm_rng_fops);
- return 0;
+ msm_rng_class = class_create(THIS_MODULE, "msm-rng");
+ if (IS_ERR(msm_rng_class)) {
+ pr_err("class_create failed\n");
+ return PTR_ERR(msm_rng_class);
+ }
+ dev = device_create(msm_rng_class, NULL, MKDEV(QRNG_IOC_MAGIC, 0),
+ NULL, "msm-rng");
+ if (IS_ERR(dev)) {
+ pr_err("Device create failed\n");
+ error = PTR_ERR(dev);
+ goto unregister_chrdev;
+ }
+ cdev_init(&msm_rng_cdev, &msm_rng_fops);
+
+ return ret;
+
+unregister_chrdev:
+ unregister_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME);
rollback_clk:
clk_put(msm_rng_dev->prng_clk);
err_clk_get:
@@ -254,7 +296,7 @@
static int __devexit msm_rng_remove(struct platform_device *pdev)
{
struct msm_rng_device *msm_rng_dev = platform_get_drvdata(pdev);
-
+ unregister_chrdev(QRNG_IOC_MAGIC, DRIVER_NAME);
hwrng_unregister(&msm_rng);
clk_put(msm_rng_dev->prng_clk);
iounmap(msm_rng_dev->base);
diff --git a/drivers/char/rdbg.c b/drivers/char/rdbg.c
new file mode 100644
index 0000000..dbbf4b0
--- /dev/null
+++ b/drivers/char/rdbg.c
@@ -0,0 +1,1150 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/cdev.h>
+#include <linux/gfp.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/completion.h>
+#include <linux/of_gpio.h>
+#include <linux/mutex.h>
+#include <mach/msm_smsm.h>
+#include <linux/uaccess.h>
+#include <asm/system.h>
+
+#define SMP2P_NUM_PROCS 8
+
+#define SM_VERSION 1
+#define SM_BLOCKSIZE 128
+
+#define SMQ_MAGIC_INIT 0xFF00FF00
+#define SMQ_MAGIC_PRODUCER (SMQ_MAGIC_INIT | 0x1)
+#define SMQ_MAGIC_CONSUMER (SMQ_MAGIC_INIT | 0x2)
+
+enum SMQ_STATUS {
+ SMQ_SUCCESS = 0,
+ SMQ_ENOMEMORY = -1,
+ SMQ_EBADPARM = -2,
+ SMQ_UNDERFLOW = -3,
+ SMQ_OVERFLOW = -4
+};
+
+enum smq_type {
+ PRODUCER = 1,
+ CONSUMER = 2,
+ INVALID = 3
+};
+
+struct smq_block_map {
+ uint32_t index_read;
+ uint32_t num_blocks;
+ uint8_t *map;
+};
+
+struct smq_node {
+ uint16_t index_block;
+ uint16_t num_blocks;
+} __attribute__ ((__packed__));
+
+struct smq_hdr {
+ uint8_t producer_version;
+ uint8_t consumer_version;
+} __attribute__ ((__packed__));
+
+struct smq_out_state {
+ uint32_t init;
+ uint32_t index_check_queue_for_reset;
+ uint32_t index_sent_write;
+ uint32_t index_free_read;
+} __attribute__ ((__packed__));
+
+struct smq_out {
+ struct smq_out_state s;
+ struct smq_node sent[1];
+};
+
+struct smq_in_state {
+ uint32_t init;
+ uint32_t index_check_queue_for_reset_ack;
+ uint32_t index_sent_read;
+ uint32_t index_free_write;
+} __attribute__ ((__packed__));
+
+struct smq_in {
+ struct smq_in_state s;
+ struct smq_node free[1];
+};
+
+struct smq {
+ struct smq_hdr *hdr;
+ struct smq_out *out;
+ struct smq_in *in;
+ uint8_t *blocks;
+ uint32_t num_blocks;
+ struct mutex *lock;
+ uint32_t initialized;
+ struct smq_block_map block_map;
+ enum smq_type type;
+};
+
+struct gpio_info {
+ int gpio_base_id;
+ int irq_base_id;
+};
+
+struct rdbg_data {
+ struct device *device;
+ struct completion work;
+ struct gpio_info in;
+ struct gpio_info out;
+ bool device_initialized;
+ int gpio_out_offset;
+ bool device_opened;
+ void *smem_addr;
+ size_t smem_size;
+ struct smq producer_smrb;
+ struct smq consumer_smrb;
+ struct mutex write_mutex;
+};
+
+struct rdbg_device {
+ struct cdev cdev;
+ struct class *class;
+ dev_t dev_no;
+ int num_devices;
+ struct rdbg_data *rdbg_data;
+};
+
+static struct rdbg_device g_rdbg_instance = {
+ { {0} },
+ NULL,
+ 0,
+ SMP2P_NUM_PROCS,
+ NULL
+};
+
+struct processor_specific_info {
+ char *name;
+ unsigned int smem_buffer_addr;
+ size_t smem_buffer_size;
+};
+
+static struct processor_specific_info proc_info[SMP2P_NUM_PROCS] = {
+ {0}, /*APPS*/
+ {"rdbg_modem", 0, 0}, /*MODEM*/
+ {"rdbg_adsp", SMEM_LC_DEBUGGER, 16*1024}, /*ADSP*/
+ {0}, /*SMP2P_RESERVED_PROC_1*/
+ {"rdbg_wcnss", 0, 0}, /*WCNSS*/
+ {0}, /*SMP2P_RESERVED_PROC_2*/
+ {0}, /*SMP2P_POWER_PROC*/
+ {0} /*SMP2P_REMOTE_MOCK_PROC*/
+};
+
+static int smq_blockmap_get(struct smq_block_map *block_map,
+ uint32_t *block_index, uint32_t n)
+{
+ uint32_t start;
+ uint32_t mark = 0;
+ uint32_t found = 0;
+ uint32_t i = 0;
+
+ start = block_map->index_read;
+
+ if (n == 1) {
+ do {
+ if (!block_map->map[block_map->index_read]) {
+ *block_index = block_map->index_read;
+ block_map->map[block_map->index_read] = 1;
+ block_map->index_read++;
+ block_map->index_read %= block_map->num_blocks;
+ return SMQ_SUCCESS;
+ }
+ block_map->index_read++;
+ } while (start != (block_map->index_read %=
+ block_map->num_blocks));
+ } else {
+ mark = block_map->num_blocks;
+
+ do {
+ if (!block_map->map[block_map->index_read]) {
+ if (mark > block_map->index_read) {
+ mark = block_map->index_read;
+ start = block_map->index_read;
+ found = 0;
+ }
+
+ found++;
+ if (found == n) {
+ *block_index = mark;
+ for (i = 0; i < n; i++)
+ block_map->map[mark + i] =
+ (uint8_t)(n - i);
+ block_map->index_read += block_map->map
+ [block_map->index_read] - 1;
+ return SMQ_SUCCESS;
+ }
+ } else {
+ found = 0;
+ block_map->index_read += block_map->map
+ [block_map->index_read] - 1;
+ mark = block_map->num_blocks;
+ }
+ block_map->index_read++;
+ } while (start != (block_map->index_read %=
+ block_map->num_blocks));
+ }
+
+ return SMQ_ENOMEMORY;
+}
+
+static void smq_blockmap_put(struct smq_block_map *block_map, uint32_t i)
+{
+ uint32_t num_blocks = block_map->map[i];
+
+ while (num_blocks--) {
+ block_map->map[i] = 0;
+ i++;
+ }
+}
+
+static int smq_blockmap_reset(struct smq_block_map *block_map)
+{
+ if (!block_map->map)
+ return SMQ_ENOMEMORY;
+ memset(block_map->map, 0 , block_map->num_blocks + 1);
+ block_map->index_read = 0;
+
+ return SMQ_SUCCESS;
+}
+
+static int smq_blockmap_ctor(struct smq_block_map *block_map,
+ uint32_t num_blocks)
+{
+ if (num_blocks <= 1)
+ return SMQ_ENOMEMORY;
+
+ block_map->map = kcalloc(num_blocks, sizeof(uint8_t), GFP_KERNEL);
+ if (!block_map->map)
+ return SMQ_ENOMEMORY;
+
+ block_map->num_blocks = num_blocks - 1;
+ smq_blockmap_reset(block_map);
+
+ return SMQ_SUCCESS;
+}
+
+static void smq_blockmap_dtor(struct smq_block_map *block_map)
+{
+ kfree(block_map->map);
+ block_map->map = NULL;
+}
+
+static int smq_free(struct smq *smq, void *data)
+{
+ struct smq_node node;
+ uint32_t index_block;
+ int err = SMQ_SUCCESS;
+
+ if (smq->lock)
+ mutex_lock(smq->lock);
+
+ if ((SM_VERSION != smq->hdr->producer_version) &&
+ (SMQ_MAGIC_PRODUCER != smq->out->s.init)) {
+ err = SMQ_UNDERFLOW;
+ goto bail;
+ }
+
+ index_block = ((uint8_t *)data - smq->blocks) / SM_BLOCKSIZE;
+ if (index_block >= smq->num_blocks) {
+ err = SMQ_EBADPARM;
+ goto bail;
+ }
+
+ node.index_block = (uint16_t)index_block;
+ node.num_blocks = 0;
+ *((struct smq_node *)(smq->in->free + smq->in->
+ s.index_free_write)) = node;
+
+ smq->in->s.index_free_write = (smq->in->s.index_free_write + 1)
+ % smq->num_blocks;
+
+bail:
+ if (smq->lock)
+ mutex_unlock(smq->lock);
+ return err;
+}
+
+static int smq_receive(struct smq *smq, void **pp, int *pnsize, int *pbmore)
+{
+ struct smq_node *node;
+ int err = SMQ_SUCCESS;
+ int more = 0;
+
+ if ((SM_VERSION != smq->hdr->producer_version) &&
+ (SMQ_MAGIC_PRODUCER != smq->out->s.init))
+ return SMQ_UNDERFLOW;
+
+ if (smq->in->s.index_sent_read == smq->out->s.index_sent_write) {
+ err = SMQ_UNDERFLOW;
+ goto bail;
+ }
+
+ node = (struct smq_node *)(smq->out->sent + smq->in->s.index_sent_read);
+ if (node->index_block >= smq->num_blocks) {
+ err = SMQ_EBADPARM;
+ goto bail;
+ }
+
+ smq->in->s.index_sent_read = (smq->in->s.index_sent_read + 1)
+ % smq->num_blocks;
+
+ *pp = smq->blocks + (node->index_block * SM_BLOCKSIZE);
+ *pnsize = SM_BLOCKSIZE * node->num_blocks;
+ rmb();
+ if (smq->in->s.index_sent_read != smq->out->s.index_sent_write)
+ more = 1;
+
+bail:
+ *pbmore = more;
+ return err;
+}
+
+static int smq_alloc_send(struct smq *smq, const uint8_t *pcb, int nsize)
+{
+ void *pv = 0;
+ int num_blocks;
+ uint32_t index_block = 0;
+ int err = SMQ_SUCCESS;
+ struct smq_node *node = NULL;
+
+ mutex_lock(smq->lock);
+
+ if ((SMQ_MAGIC_CONSUMER == smq->in->s.init) &&
+ (SM_VERSION == smq->hdr->consumer_version)) {
+ if (smq->out->s.index_check_queue_for_reset ==
+ smq->in->s.index_check_queue_for_reset_ack) {
+ while (smq->out->s.index_free_read !=
+ smq->in->s.index_free_write) {
+ node = (struct smq_node *)(
+ smq->in->free +
+ smq->out->s.index_free_read);
+ if (node->index_block >= smq->num_blocks) {
+ err = SMQ_EBADPARM;
+ goto bail;
+ }
+
+ smq->out->s.index_free_read =
+ (smq->out->s.index_free_read + 1)
+ % smq->num_blocks;
+
+ smq_blockmap_put(&smq->block_map,
+ node->index_block);
+ rmb();
+ }
+ }
+ }
+
+ num_blocks = ALIGN(nsize, SM_BLOCKSIZE)/SM_BLOCKSIZE;
+ err = smq_blockmap_get(&smq->block_map, &index_block, num_blocks);
+ if (SMQ_SUCCESS != err)
+ goto bail;
+
+ pv = smq->blocks + (SM_BLOCKSIZE * index_block);
+
+ err = copy_from_user((void *)pv, (void *)pcb, nsize);
+ if (0 != err)
+ goto bail;
+
+ ((struct smq_node *)(smq->out->sent +
+ smq->out->s.index_sent_write))->index_block
+ = (uint16_t)index_block;
+ ((struct smq_node *)(smq->out->sent +
+ smq->out->s.index_sent_write))->num_blocks
+ = (uint16_t)num_blocks;
+
+ smq->out->s.index_sent_write = (smq->out->s.index_sent_write + 1)
+ % smq->num_blocks;
+
+bail:
+ if (SMQ_SUCCESS != err) {
+ if (pv)
+ smq_blockmap_put(&smq->block_map, index_block);
+ }
+ mutex_unlock(smq->lock);
+ return err;
+}
+
+static int smq_reset_producer_queue_internal(struct smq *smq,
+ uint32_t reset_num)
+{
+ int retval = 0;
+ uint32_t i;
+
+ if (PRODUCER != smq->type)
+ goto bail;
+
+ mutex_lock(smq->lock);
+ if (smq->out->s.index_check_queue_for_reset != reset_num) {
+ smq->out->s.index_check_queue_for_reset = reset_num;
+ for (i = 0; i < smq->num_blocks; i++)
+ (smq->out->sent + i)->index_block = 0xFFFF;
+
+ smq_blockmap_reset(&smq->block_map);
+ smq->out->s.index_sent_write = 0;
+ smq->out->s.index_free_read = 0;
+ retval = 1;
+ }
+ mutex_unlock(smq->lock);
+
+bail:
+ return retval;
+}
+
+static int smq_check_queue_reset(struct smq *p_cons, struct smq *p_prod)
+{
+ int retval = 0;
+ uint32_t reset_num, i;
+
+ if ((CONSUMER != p_cons->type) ||
+ (SMQ_MAGIC_PRODUCER != p_cons->out->s.init) ||
+ (SM_VERSION != p_cons->hdr->producer_version))
+ goto bail;
+
+ reset_num = p_cons->out->s.index_check_queue_for_reset;
+ if (p_cons->in->s.index_check_queue_for_reset_ack != reset_num) {
+ p_cons->in->s.index_check_queue_for_reset_ack = reset_num;
+ for (i = 0; i < p_cons->num_blocks; i++)
+ (p_cons->in->free + i)->index_block = 0xFFFF;
+
+ p_cons->in->s.index_sent_read = 0;
+ p_cons->in->s.index_free_write = 0;
+
+ retval = smq_reset_producer_queue_internal(p_prod, reset_num);
+ }
+
+bail:
+ return retval;
+}
+
+static int check_subsystem_debug_enabled(void *base_addr, int size)
+{
+ int num_blocks;
+ uint8_t *pb_orig;
+ uint8_t *pb;
+ struct smq smq;
+ int err = 0;
+
+ pb = pb_orig = (uint8_t *)base_addr;
+ pb += sizeof(struct smq_hdr);
+ pb = PTR_ALIGN(pb, 8);
+ size -= pb - (uint8_t *)pb_orig;
+ num_blocks = (int)((size - sizeof(struct smq_out_state) -
+ sizeof(struct smq_in_state))/(SM_BLOCKSIZE +
+ sizeof(struct smq_node) * 2));
+ if (0 >= num_blocks) {
+ err = SMQ_EBADPARM;
+ goto bail;
+ }
+
+ pb += num_blocks * SM_BLOCKSIZE;
+ smq.out = (struct smq_out *)pb;
+ pb += sizeof(struct smq_out_state) + (num_blocks *
+ sizeof(struct smq_node));
+ smq.in = (struct smq_in *)pb;
+
+ if (SMQ_MAGIC_CONSUMER != smq.in->s.init) {
+ pr_err("%s, smq in consumer not initialized", __func__);
+ err = -ECOMM;
+ }
+
+bail:
+ return err;
+}
+
+static void smq_dtor(struct smq *smq)
+{
+ if (SMQ_MAGIC_INIT == smq->initialized) {
+ switch (smq->type) {
+ case PRODUCER:
+ smq->out->s.init = 0;
+ smq_blockmap_dtor(&smq->block_map);
+ break;
+ case CONSUMER:
+ smq->in->s.init = 0;
+ break;
+ default:
+ case INVALID:
+ break;
+ }
+
+ smq->initialized = 0;
+ }
+}
+
+/*
+ * The shared memory is used as a circular ring buffer in each direction.
+ * Thus we have a bi-directional shared memory channel between the AP
+ * and a subsystem. We call this SMQ. Each memory channel contains a header,
+ * data and a control mechanism that is used to synchronize read and write
+ * of data between the AP and the remote subsystem.
+ *
+ * Overall SMQ memory view:
+ *
+ * +------------------------------------------------+
+ * | SMEM buffer |
+ * |-----------------------+------------------------|
+ * |Producer: LA | Producer: Remote |
+ * |Consumer: Remote | subsystem |
+ * | subsystem | Consumer: LA |
+ * | | |
+ * | Producer| Consumer|
+ * +-----------------------+------------------------+
+ * | |
+ * | |
+ * | +--------------------------------------+
+ * | |
+ * | |
+ * v v
+ * +--------------------------------------------------------------+
+ * | Header | Data | Control |
+ * +-----------+---+---+---+-----+----+--+--+-----+---+--+--+-----+
+ * | | b | b | b | | S |n |n | | S |n |n | |
+ * | Producer | l | l | l | | M |o |o | | M |o |o | |
+ * | Ver | o | o | o | | Q |d |d | | Q |d |d | |
+ * |-----------| c | c | c | ... | |e |e | ... | |e |e | ... |
+ * | | k | k | k | | O | | | | I | | | |
+ * | Consumer | | | | | u |0 |1 | | n |0 |1 | |
+ * | Ver | 0 | 1 | 2 | | t | | | | | | | |
+ * +-----------+---+---+---+-----+----+--+--+-----+---+--+--+-----+
+ * | |
+ * + |
+ * |
+ * +------------------------+
+ * |
+ * v
+ * +----+----+----+----+
+ * | SMQ Nodes |
+ * |----|----|----|----|
+ * Node # | 0 | 1 | 2 | ...|
+ * |----|----|----|----|
+ * Starting Block Index # | 0 | 3 | 8 | ...|
+ * |----|----|----|----|
+ * # of blocks | 3 | 5 | 1 | ...|
+ * +----+----+----+----+
+ *
+ * Header: Contains version numbers for software compatibility to ensure
+ * that both producers and consumers on the AP and subsystems know how to
+ * read from and write to the queue.
+ * Both the producer and consumer versions are 1.
+ * +---------+-------------------+
+ * | Size | Field |
+ * +---------+-------------------+
+ * | 1 byte | Producer Version |
+ * +---------+-------------------+
+ * | 1 byte | Consumer Version |
+ * +---------+-------------------+
+ *
+ * Data: The data portion contains multiple blocks [0..N] of a fixed size.
+ * The block size SM_BLOCKSIZE is fixed to 128 bytes for header version #1.
+ * Payload sent from the debug agent app is split (if necessary) and placed
+ * in these blocks. The first data block is placed at the next 8 byte aligned
+ * address after the header.
+ *
+ * The number of blocks for a given SMEM allocation is derived as follows:
+ * Number of Blocks = ((Total Size - Alignment - Size of Header
+ * - Size of SMQIn - Size of SMQOut)/(SM_BLOCKSIZE))
+ *
+ * The producer maintains a private block map of each of these blocks to
+ * determine which of these blocks in the queue is available and which are free.
+ *
+ * Control:
+ * The control portion contains a list of nodes [0..N] where N is number
+ * of available data blocks. Each node identifies the data
+ * block indexes that contain a particular debug message to be transfered,
+ * and the number of blocks it took to hold the contents of the message.
+ *
+ * Each node has the following structure:
+ * +---------+-------------------+
+ * | Size | Field |
+ * +---------+-------------------+
+ * | 2 bytes |Staring Block Index|
+ * +---------+-------------------+
+ * | 2 bytes |Number of Blocks |
+ * +---------+-------------------+
+ *
+ * The producer and the consumer update different parts of the control channel
+ * (SMQOut / SMQIn) respectively. Each of these control data structures contains
+ * information about the last node that was written / read, and the actual nodes
+ * that were written/read.
+ *
+ * SMQOut Structure (R/W by producer, R by consumer):
+ * +---------+-------------------+
+ * | Size | Field |
+ * +---------+-------------------+
+ * | 4 bytes | Magic Init Number |
+ * +---------+-------------------+
+ * | 4 bytes | Reset |
+ * +---------+-------------------+
+ * | 4 bytes | Last Sent Index |
+ * +---------+-------------------+
+ * | 4 bytes | Index Free Read |
+ * +---------+-------------------+
+ *
+ * SMQIn Structure (R/W by consumer, R by producer):
+ * +---------+-------------------+
+ * | Size | Field |
+ * +---------+-------------------+
+ * | 4 bytes | Magic Init Number |
+ * +---------+-------------------+
+ * | 4 bytes | Reset ACK |
+ * +---------+-------------------+
+ * | 4 bytes | Last Read Index |
+ * +---------+-------------------+
+ * | 4 bytes | Index Free Write |
+ * +---------+-------------------+
+ *
+ * Magic Init Number:
+ * Both SMQ Out and SMQ In initialize this field with a predefined magic
+ * number so as to make sure that both the consumer and producer blocks
+ * have fully initialized and have valid data in the shared memory control area.
+ * Producer Magic #: 0xFF00FF01
+ * Consumer Magic #: 0xFF00FF02
+ */
+static int smq_ctor(struct smq *smq, void *base_addr, int size,
+ enum smq_type type, struct mutex *lock_ptr)
+{
+ int num_blocks;
+ uint8_t *pb_orig;
+ uint8_t *pb;
+ uint32_t i;
+ int err;
+
+ if (SMQ_MAGIC_INIT == smq->initialized) {
+ err = SMQ_EBADPARM;
+ goto bail;
+ }
+
+ if (!base_addr || !size) {
+ err = SMQ_EBADPARM;
+ goto bail;
+ }
+
+ if (type == PRODUCER)
+ smq->lock = lock_ptr;
+
+ pb_orig = (uint8_t *)base_addr;
+ smq->hdr = (struct smq_hdr *)pb_orig;
+ pb = pb_orig;
+ pb += sizeof(struct smq_hdr);
+ pb = PTR_ALIGN(pb, 8);
+ size -= pb - (uint8_t *)pb_orig;
+ num_blocks = (int)((size - sizeof(struct smq_out_state) -
+ sizeof(struct smq_in_state))/(SM_BLOCKSIZE +
+ sizeof(struct smq_node) * 2));
+ if (0 >= num_blocks) {
+ err = SMQ_ENOMEMORY;
+ goto bail;
+ }
+
+ smq->blocks = pb;
+ smq->num_blocks = num_blocks;
+ pb += num_blocks * SM_BLOCKSIZE;
+ smq->out = (struct smq_out *)pb;
+ pb += sizeof(struct smq_out_state) + (num_blocks *
+ sizeof(struct smq_node));
+ smq->in = (struct smq_in *)pb;
+ smq->type = type;
+ if (PRODUCER == type) {
+ smq->hdr->producer_version = SM_VERSION;
+ for (i = 0; i < smq->num_blocks; i++)
+ (smq->out->sent + i)->index_block = 0xFFFF;
+
+ err = smq_blockmap_ctor(&smq->block_map, smq->num_blocks);
+ if (SMQ_SUCCESS != err)
+ goto bail;
+
+ smq->out->s.index_sent_write = 0;
+ smq->out->s.index_free_read = 0;
+ if (smq->out->s.init == SMQ_MAGIC_PRODUCER) {
+ smq->out->s.index_check_queue_for_reset += 1;
+ } else {
+ smq->out->s.index_check_queue_for_reset = 1;
+ smq->out->s.init = SMQ_MAGIC_PRODUCER;
+ }
+ } else {
+ smq->hdr->consumer_version = SM_VERSION;
+ for (i = 0; i < smq->num_blocks; i++)
+ (smq->in->free + i)->index_block = 0xFFFF;
+
+ smq->in->s.index_sent_read = 0;
+ smq->in->s.index_free_write = 0;
+ if (smq->out->s.init == SMQ_MAGIC_PRODUCER) {
+ smq->in->s.index_check_queue_for_reset_ack =
+ smq->out->s.index_check_queue_for_reset;
+ } else {
+ smq->in->s.index_check_queue_for_reset_ack = 0;
+ }
+
+ smq->in->s.init = SMQ_MAGIC_CONSUMER;
+ }
+ smq->initialized = SMQ_MAGIC_INIT;
+ err = SMQ_SUCCESS;
+
+bail:
+ return err;
+}
+
+static void send_interrupt_to_subsystem(struct rdbg_data *rdbgdata)
+{
+ int offset = rdbgdata->gpio_out_offset;
+ int val = 1 ^ gpio_get_value(rdbgdata->out.gpio_base_id + offset);
+ gpio_set_value(rdbgdata->out.gpio_base_id + offset, val);
+ rdbgdata->gpio_out_offset = (offset + 1) % 32;
+
+ dev_dbg(rdbgdata->device, "%s: sent interrupt %d to subsystem",
+ __func__, val);
+}
+
+static irqreturn_t on_interrupt_from(int irq, void *ptr)
+{
+ struct rdbg_data *rdbgdata = (struct rdbg_data *) ptr;
+
+ dev_dbg(rdbgdata->device, "%s: Received interrupt %d from subsystem",
+ __func__, irq);
+
+ complete(&(rdbgdata->work));
+ return IRQ_HANDLED;
+}
+
+static int initialize_smq(struct rdbg_data *rdbgdata)
+{
+ int err = 0;
+
+ if (smq_ctor(&(rdbgdata->producer_smrb), (void *)(rdbgdata->smem_addr),
+ ((rdbgdata->smem_size)/2), PRODUCER, &rdbgdata->write_mutex)) {
+ dev_err(rdbgdata->device, "%s: smq producer allocation failed",
+ __func__);
+ err = -ENOMEM;
+ goto bail;
+ }
+
+ if (smq_ctor(&(rdbgdata->consumer_smrb), (void *)((uint32_t)
+ (rdbgdata->smem_addr) + ((rdbgdata->smem_size)/2)),
+ ((rdbgdata->smem_size)/2), CONSUMER, NULL)) {
+ dev_err(rdbgdata->device, "%s: smq conmsumer allocation failed",
+ __func__);
+ err = -ENOMEM;
+ }
+
+bail:
+ return err;
+
+}
+
+static int rdbg_open(struct inode *inode, struct file *filp)
+{
+ int device_id = -1;
+ struct rdbg_device *device = &g_rdbg_instance;
+ struct rdbg_data *rdbgdata = NULL;
+ int err = 0;
+
+ if (!inode || !device->rdbg_data) {
+ pr_err("Memory not allocated yet");
+ err = -ENODEV;
+ goto bail;
+ }
+
+ device_id = MINOR(inode->i_rdev);
+ rdbgdata = &device->rdbg_data[device_id];
+
+ if (rdbgdata->device_opened) {
+ dev_err(rdbgdata->device, "%s: Device already opened",
+ __func__);
+ err = -EEXIST;
+ goto bail;
+ }
+
+ rdbgdata->smem_size = proc_info[device_id].smem_buffer_size;
+ if (!rdbgdata->smem_size) {
+ dev_err(rdbgdata->device, "%s: smem not initialized", __func__);
+ err = -ENOMEM;
+ goto bail;
+ }
+
+ rdbgdata->smem_addr = smem_alloc(proc_info[device_id].smem_buffer_addr,
+ rdbgdata->smem_size);
+ if (!rdbgdata->smem_addr) {
+ dev_err(rdbgdata->device, "%s: Could not allocate smem memory",
+ __func__);
+ err = -ENOMEM;
+ goto bail;
+ }
+ dev_dbg(rdbgdata->device, "%s: SMEM address=0x%x smem_size=%d",
+ __func__, (unsigned int)rdbgdata->smem_addr,
+ rdbgdata->smem_size);
+
+ if (check_subsystem_debug_enabled(rdbgdata->smem_addr,
+ rdbgdata->smem_size/2)) {
+ dev_err(rdbgdata->device, "%s: Subsystem %s is not debug enabled",
+ __func__, proc_info[device_id].name);
+ err = -ECOMM;
+ goto bail;
+ }
+
+ init_completion(&rdbgdata->work);
+
+ err = request_irq(rdbgdata->in.irq_base_id, on_interrupt_from,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ proc_info[device_id].name,
+ (void *)&device->rdbg_data[device_id]);
+ if (err) {
+ dev_err(rdbgdata->device,
+ "%s: Failed to register interrupt.Err=%d,irqid=%d.",
+ __func__, err, rdbgdata->in.irq_base_id);
+ goto irq_bail;
+ }
+
+ err = enable_irq_wake(rdbgdata->in.irq_base_id);
+ if (err < 0) {
+ dev_dbg(rdbgdata->device, "enable_irq_wake() failed with err=%d",
+ err);
+ err = 0;
+ }
+
+ mutex_init(&rdbgdata->write_mutex);
+
+ err = initialize_smq(rdbgdata);
+ if (err) {
+ dev_err(rdbgdata->device, "Error initializing smq. Err=%d",
+ err);
+ goto smq_bail;
+ }
+
+ rdbgdata->device_opened = 1;
+
+ filp->private_data = (void *)rdbgdata;
+
+ return 0;
+
+smq_bail:
+ smq_dtor(&(rdbgdata->producer_smrb));
+ smq_dtor(&(rdbgdata->consumer_smrb));
+ mutex_destroy(&rdbgdata->write_mutex);
+irq_bail:
+ free_irq(rdbgdata->in.irq_base_id, (void *)
+ &device->rdbg_data[device_id]);
+bail:
+ return err;
+}
+
+static int rdbg_release(struct inode *inode, struct file *filp)
+{
+ int device_id = -1;
+ struct rdbg_device *rdbgdevice = &g_rdbg_instance;
+ struct rdbg_data *rdbgdata = NULL;
+ int err = 0;
+
+ if (!inode || !rdbgdevice->rdbg_data) {
+ pr_err("Memory not allocated yet");
+ err = -ENODEV;
+ goto bail;
+ }
+
+ device_id = MINOR(inode->i_rdev);
+ rdbgdata = &rdbgdevice->rdbg_data[device_id];
+
+ if (rdbgdata->device_opened == 1) {
+ dev_dbg(rdbgdata->device, "%s: Destroying %s.", __func__,
+ proc_info[device_id].name);
+ rdbgdata->device_opened = 0;
+ complete(&(rdbgdata->work));
+ free_irq(rdbgdata->in.irq_base_id, (void *)
+ &rdbgdevice->rdbg_data[device_id]);
+ if (rdbgdevice->rdbg_data[device_id].producer_smrb.initialized)
+ smq_dtor(&(rdbgdevice->rdbg_data[device_id].
+ producer_smrb));
+ if (rdbgdevice->rdbg_data[device_id].consumer_smrb.initialized)
+ smq_dtor(&(rdbgdevice->rdbg_data[device_id].
+ consumer_smrb));
+ mutex_destroy(&rdbgdata->write_mutex);
+ }
+
+ filp->private_data = NULL;
+
+bail:
+ return err;
+}
+
+static ssize_t rdbg_read(struct file *filp, char __user *buf, size_t size,
+ loff_t *offset)
+{
+ int err = 0;
+ struct rdbg_data *rdbgdata = filp->private_data;
+ void *p_sent_buffer = NULL;
+ int nsize = 0;
+ int more = 0;
+
+ if (!rdbgdata) {
+ pr_err("Invalid argument");
+ err = -EINVAL;
+ goto bail;
+ }
+
+ dev_dbg(rdbgdata->device, "%s: In receive", __func__);
+ err = wait_for_completion_interruptible(&(rdbgdata->work));
+ if (err) {
+ dev_err(rdbgdata->device, "%s: Error in wait", __func__);
+ goto bail;
+ }
+
+ smq_check_queue_reset(&(rdbgdata->consumer_smrb),
+ &(rdbgdata->producer_smrb));
+ if (SMQ_SUCCESS != smq_receive(&(rdbgdata->consumer_smrb),
+ &p_sent_buffer, &nsize, &more)) {
+ dev_err(rdbgdata->device, "%s: Error in smq_recv(). Err code = %d",
+ __func__, err);
+ err = -ENODATA;
+ goto bail;
+ }
+
+ size = ((size < nsize) ? size : nsize);
+ err = copy_to_user(buf, p_sent_buffer, size);
+ if (err != 0) {
+ dev_err(rdbgdata->device, "%s: Error in copy_to_user(). Err code = %d",
+ __func__, err);
+ err = -ENODATA;
+ goto bail;
+ }
+
+ smq_free(&(rdbgdata->consumer_smrb), p_sent_buffer);
+ err = size;
+ dev_dbg(rdbgdata->device, "%s: Read data to buffer with address 0x%x",
+ __func__, (unsigned int) buf);
+
+bail:
+ dev_dbg(rdbgdata->device, "%s: Returning from receive", __func__);
+ return err;
+}
+
+static ssize_t rdbg_write(struct file *filp, const char __user *buf,
+ size_t size, loff_t *offset)
+{
+ int err = 0;
+ struct rdbg_data *rdbgdata = filp->private_data;
+
+ if (!rdbgdata) {
+ pr_err("Invalid argument");
+ err = -EINVAL;
+ goto bail;
+ }
+
+ if (smq_alloc_send(&(rdbgdata->producer_smrb), buf, size)) {
+ dev_err(rdbgdata->device, "%s, Error sending", __func__);
+ err = -ECOMM;
+ goto bail;
+ }
+ send_interrupt_to_subsystem(rdbgdata);
+
+ err = size;
+
+bail:
+ return err;
+}
+
+
+static const struct file_operations rdbg_fops = {
+ .open = rdbg_open,
+ .read = rdbg_read,
+ .write = rdbg_write,
+ .release = rdbg_release,
+};
+
+static int register_smp2p(char *node_name, struct gpio_info *gpio_info_ptr)
+{
+ struct device_node *node = NULL;
+ int cnt = 0;
+ int id = 0;
+
+ node = of_find_compatible_node(NULL, NULL, node_name);
+ if (node) {
+ cnt = of_gpio_count(node);
+ if (cnt && gpio_info_ptr) {
+ id = of_get_gpio(node, 0);
+ gpio_info_ptr->gpio_base_id = id;
+ gpio_info_ptr->irq_base_id = gpio_to_irq(id);
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int __init rdbg_init(void)
+{
+ int err = 0;
+ struct rdbg_device *rdbgdevice = &g_rdbg_instance;
+ int minor = 0;
+ int major = 0;
+ int minor_nodes_created = 0;
+
+ char *rdbg_compatible_string = "qcom,smp2pgpio_client_rdbg_";
+ int max_len = strlen(rdbg_compatible_string) + strlen("xx_out");
+
+ char *node_name = kcalloc(max_len, sizeof(char), GFP_KERNEL);
+
+ if (!node_name) {
+ pr_err("Not enough memory");
+ err = -ENOMEM;
+ goto bail;
+ }
+
+ if (rdbgdevice->num_devices < 1 ||
+ rdbgdevice->num_devices > SMP2P_NUM_PROCS) {
+ pr_err("rgdb: invalid num_devices");
+ err = -EDOM;
+ goto name_bail;
+ }
+
+ rdbgdevice->rdbg_data = kcalloc(rdbgdevice->num_devices,
+ sizeof(struct rdbg_data), GFP_KERNEL);
+ if (!rdbgdevice->rdbg_data) {
+ pr_err("Not enough memory for rdbg devices");
+ err = -ENOMEM;
+ goto name_bail;
+ }
+
+ err = alloc_chrdev_region(&rdbgdevice->dev_no, 0,
+ rdbgdevice->num_devices, "rdbgctl");
+ if (err) {
+ pr_err("Error in alloc_chrdev_region.");
+ goto data_bail;
+ }
+ major = MAJOR(rdbgdevice->dev_no);
+
+ cdev_init(&rdbgdevice->cdev, &rdbg_fops);
+ rdbgdevice->cdev.owner = THIS_MODULE;
+ err = cdev_add(&rdbgdevice->cdev, MKDEV(major, 0),
+ rdbgdevice->num_devices);
+ if (err) {
+ pr_err("Error in cdev_add");
+ goto chrdev_bail;
+ }
+
+ rdbgdevice->class = class_create(THIS_MODULE, "rdbg");
+ if (IS_ERR(rdbgdevice->class)) {
+ err = PTR_ERR(rdbgdevice->class);
+ pr_err("Error in class_create");
+ goto cdev_bail;
+ }
+
+ for (minor = 0; minor < rdbgdevice->num_devices; minor++) {
+ if (!proc_info[minor].name)
+ continue;
+
+ if (snprintf(node_name, max_len, "%s%d_in",
+ rdbg_compatible_string, minor) <= 0) {
+ pr_err("Error in snprintf");
+ err = -ENOMEM;
+ goto device_bail;
+ }
+
+ if (register_smp2p(node_name,
+ &rdbgdevice->rdbg_data[minor].in)) {
+ pr_debug("No incoming device tree entry found for %s",
+ proc_info[minor].name);
+ continue;
+ }
+
+ if (snprintf(node_name, max_len, "%s%d_out",
+ rdbg_compatible_string, minor) <= 0) {
+ pr_err("Error in snprintf");
+ err = -ENOMEM;
+ goto device_bail;
+ }
+
+ if (register_smp2p(node_name,
+ &rdbgdevice->rdbg_data[minor].out)) {
+ pr_err("No outgoing device tree entry found for %s",
+ proc_info[minor].name);
+ err = -EINVAL;
+ goto device_bail;
+ }
+
+ rdbgdevice->rdbg_data[minor].device = device_create(
+ rdbgdevice->class, NULL, MKDEV(major, minor),
+ NULL, "%s", proc_info[minor].name);
+ if (IS_ERR(rdbgdevice->rdbg_data[minor].device)) {
+ err = PTR_ERR(rdbgdevice->rdbg_data[minor].device);
+ pr_err("Error in device_create");
+ goto device_bail;
+ }
+ rdbgdevice->rdbg_data[minor].device_initialized = 1;
+ minor_nodes_created++;
+ dev_dbg(rdbgdevice->rdbg_data[minor].device,
+ "%s: created /dev/%s c %d %d'", __func__,
+ proc_info[minor].name, major, minor);
+ }
+
+ if (!minor_nodes_created) {
+ pr_err("No device tree entries found");
+ err = -EINVAL;
+ goto class_bail;
+ }
+
+ goto name_bail;
+
+device_bail:
+ for (--minor; minor >= 0; minor--) {
+ if (rdbgdevice->rdbg_data[minor].device_initialized)
+ device_destroy(rdbgdevice->class,
+ MKDEV(MAJOR(rdbgdevice->dev_no), minor));
+ }
+class_bail:
+ class_destroy(rdbgdevice->class);
+cdev_bail:
+ cdev_del(&rdbgdevice->cdev);
+chrdev_bail:
+ unregister_chrdev_region(rdbgdevice->dev_no, rdbgdevice->num_devices);
+data_bail:
+ kfree(rdbgdevice->rdbg_data);
+name_bail:
+ kfree(node_name);
+bail:
+ return err;
+}
+
+static void __exit rdbg_exit(void)
+{
+ struct rdbg_device *rdbgdevice = &g_rdbg_instance;
+ int minor;
+
+ for (minor = 0; minor < rdbgdevice->num_devices; minor++) {
+ if (rdbgdevice->rdbg_data[minor].device_initialized) {
+ device_destroy(rdbgdevice->class,
+ MKDEV(MAJOR(rdbgdevice->dev_no), minor));
+ }
+ }
+ class_destroy(rdbgdevice->class);
+ cdev_del(&rdbgdevice->cdev);
+ unregister_chrdev_region(rdbgdevice->dev_no, 1);
+ kfree(rdbgdevice->rdbg_data);
+}
+
+module_init(rdbg_init);
+module_exit(rdbg_exit);
+
+MODULE_DESCRIPTION("rdbg module");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 46756c5..83ab92b 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -1,5 +1,5 @@
# CPUfreq core
-obj-$(CONFIG_CPU_FREQ) += cpufreq.o
+obj-$(CONFIG_CPU_FREQ) += cpufreq.o cpu-boost.o
# CPUfreq stats
obj-$(CONFIG_CPU_FREQ_STAT) += cpufreq_stats.o
diff --git a/drivers/cpufreq/cpu-boost.c b/drivers/cpufreq/cpu-boost.c
new file mode 100644
index 0000000..8cd5ef9
--- /dev/null
+++ b/drivers/cpufreq/cpu-boost.c
@@ -0,0 +1,342 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "cpu-boost: " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/notifier.h>
+#include <linux/cpufreq.h>
+#include <linux/sched.h>
+#include <linux/jiffies.h>
+#include <linux/kthread.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <linux/input.h>
+#include <linux/time.h>
+
+struct cpu_sync {
+ struct task_struct *thread;
+ wait_queue_head_t sync_wq;
+ struct delayed_work boost_rem;
+ struct delayed_work input_boost_rem;
+ int cpu;
+ spinlock_t lock;
+ bool pending;
+ int src_cpu;
+ unsigned int boost_min;
+ unsigned int input_boost_min;
+};
+
+static DEFINE_PER_CPU(struct cpu_sync, sync_info);
+static struct workqueue_struct *cpu_boost_wq;
+
+static struct work_struct input_boost_work;
+
+static unsigned int boost_ms;
+module_param(boost_ms, uint, 0644);
+
+static unsigned int sync_threshold;
+module_param(sync_threshold, uint, 0644);
+
+static unsigned int input_boost_freq;
+module_param(input_boost_freq, uint, 0644);
+
+static unsigned int input_boost_ms = 40;
+module_param(input_boost_ms, uint, 0644);
+
+static u64 last_input_time;
+#define MIN_INPUT_INTERVAL (150 * USEC_PER_MSEC)
+
+/*
+ * The CPUFREQ_ADJUST notifier is used to override the current policy min to
+ * make sure policy min >= boost_min. The cpufreq framework then does the job
+ * of enforcing the new policy.
+ */
+static int boost_adjust_notify(struct notifier_block *nb, unsigned long val, void *data)
+{
+ struct cpufreq_policy *policy = data;
+ unsigned int cpu = policy->cpu;
+ struct cpu_sync *s = &per_cpu(sync_info, cpu);
+ unsigned int b_min = s->boost_min;
+ unsigned int ib_min = s->input_boost_min;
+ unsigned int min;
+
+ if (val != CPUFREQ_ADJUST)
+ return NOTIFY_OK;
+
+ if (!b_min && !ib_min)
+ return NOTIFY_OK;
+
+ min = max(b_min, ib_min);
+
+ pr_debug("CPU%u policy min before boost: %u kHz\n",
+ cpu, policy->min);
+ pr_debug("CPU%u boost min: %u kHz\n", cpu, min);
+
+ cpufreq_verify_within_limits(policy, min, UINT_MAX);
+
+ pr_debug("CPU%u policy min after boost: %u kHz\n",
+ cpu, policy->min);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block boost_adjust_nb = {
+ .notifier_call = boost_adjust_notify,
+};
+
+static void do_boost_rem(struct work_struct *work)
+{
+ struct cpu_sync *s = container_of(work, struct cpu_sync,
+ boost_rem.work);
+
+ pr_debug("Removing boost for CPU%d\n", s->cpu);
+ s->boost_min = 0;
+ /* Force policy re-evaluation to trigger adjust notifier. */
+ cpufreq_update_policy(s->cpu);
+}
+
+static void do_input_boost_rem(struct work_struct *work)
+{
+ struct cpu_sync *s = container_of(work, struct cpu_sync,
+ input_boost_rem.work);
+
+ pr_debug("Removing input boost for CPU%d\n", s->cpu);
+ s->input_boost_min = 0;
+ /* Force policy re-evaluation to trigger adjust notifier. */
+ cpufreq_update_policy(s->cpu);
+}
+
+static int boost_mig_sync_thread(void *data)
+{
+ int dest_cpu = (int) data;
+ int src_cpu, ret;
+ struct cpu_sync *s = &per_cpu(sync_info, dest_cpu);
+ struct cpufreq_policy dest_policy;
+ struct cpufreq_policy src_policy;
+ unsigned long flags;
+
+ while(1) {
+ wait_event(s->sync_wq, s->pending || kthread_should_stop());
+
+ if (kthread_should_stop())
+ break;
+
+ spin_lock_irqsave(&s->lock, flags);
+ s->pending = false;
+ src_cpu = s->src_cpu;
+ spin_unlock_irqrestore(&s->lock, flags);
+
+ ret = cpufreq_get_policy(&src_policy, src_cpu);
+ if (ret)
+ continue;
+
+ ret = cpufreq_get_policy(&dest_policy, dest_cpu);
+ if (ret)
+ continue;
+
+ if (dest_policy.cur >= src_policy.cur ) {
+ pr_debug("No sync. CPU%d@%dKHz >= CPU%d@%dKHz\n",
+ dest_cpu, dest_policy.cur, src_cpu, src_policy.cur);
+ continue;
+ }
+
+ if (sync_threshold && (dest_policy.cur >= sync_threshold))
+ continue;
+
+ cancel_delayed_work_sync(&s->boost_rem);
+ if (sync_threshold) {
+ if (src_policy.cur >= sync_threshold)
+ s->boost_min = sync_threshold;
+ else
+ s->boost_min = src_policy.cur;
+ } else {
+ s->boost_min = src_policy.cur;
+ }
+ /* Force policy re-evaluation to trigger adjust notifier. */
+ cpufreq_update_policy(dest_cpu);
+ queue_delayed_work_on(s->cpu, cpu_boost_wq,
+ &s->boost_rem, msecs_to_jiffies(boost_ms));
+ }
+
+ return 0;
+}
+
+static int boost_migration_notify(struct notifier_block *nb,
+ unsigned long dest_cpu, void *arg)
+{
+ unsigned long flags;
+ struct cpu_sync *s = &per_cpu(sync_info, dest_cpu);
+
+ if (!boost_ms)
+ return NOTIFY_OK;
+
+ pr_debug("Migration: CPU%d --> CPU%d\n", (int) arg, (int) dest_cpu);
+ spin_lock_irqsave(&s->lock, flags);
+ s->pending = true;
+ s->src_cpu = (int) arg;
+ spin_unlock_irqrestore(&s->lock, flags);
+ wake_up(&s->sync_wq);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block boost_migration_nb = {
+ .notifier_call = boost_migration_notify,
+};
+
+static void do_input_boost(struct work_struct *work)
+{
+ unsigned int i, ret;
+ struct cpu_sync *i_sync_info;
+ struct cpufreq_policy policy;
+
+ for_each_online_cpu(i) {
+
+ i_sync_info = &per_cpu(sync_info, i);
+ ret = cpufreq_get_policy(&policy, i);
+ if (ret)
+ continue;
+ if (policy.cur >= input_boost_freq)
+ continue;
+
+ cancel_delayed_work_sync(&i_sync_info->input_boost_rem);
+ i_sync_info->input_boost_min = input_boost_freq;
+ cpufreq_update_policy(i);
+ queue_delayed_work_on(i_sync_info->cpu, cpu_boost_wq,
+ &i_sync_info->input_boost_rem,
+ msecs_to_jiffies(input_boost_ms));
+ }
+}
+
+static void cpuboost_input_event(struct input_handle *handle,
+ unsigned int type, unsigned int code, int value)
+{
+ u64 now;
+
+ if (!input_boost_freq)
+ return;
+
+ now = ktime_to_us(ktime_get());
+ if (now - last_input_time < MIN_INPUT_INTERVAL)
+ return;
+
+ if (work_pending(&input_boost_work))
+ return;
+
+ queue_work(cpu_boost_wq, &input_boost_work);
+ last_input_time = ktime_to_us(ktime_get());
+}
+
+static int cpuboost_input_connect(struct input_handler *handler,
+ struct input_dev *dev, const struct input_device_id *id)
+{
+ struct input_handle *handle;
+ int error;
+
+ handle = kzalloc(sizeof(struct input_handle), GFP_KERNEL);
+ if (!handle)
+ return -ENOMEM;
+
+ handle->dev = dev;
+ handle->handler = handler;
+ handle->name = "cpufreq";
+
+ error = input_register_handle(handle);
+ if (error)
+ goto err2;
+
+ error = input_open_device(handle);
+ if (error)
+ goto err1;
+
+ return 0;
+err1:
+ input_unregister_handle(handle);
+err2:
+ kfree(handle);
+ return error;
+}
+
+static void cpuboost_input_disconnect(struct input_handle *handle)
+{
+ input_close_device(handle);
+ input_unregister_handle(handle);
+ kfree(handle);
+}
+
+static const struct input_device_id cpuboost_ids[] = {
+ /* multi-touch touchscreen */
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
+ INPUT_DEVICE_ID_MATCH_ABSBIT,
+ .evbit = { BIT_MASK(EV_ABS) },
+ .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
+ BIT_MASK(ABS_MT_POSITION_X) |
+ BIT_MASK(ABS_MT_POSITION_Y) },
+ },
+ /* touchpad */
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_KEYBIT |
+ INPUT_DEVICE_ID_MATCH_ABSBIT,
+ .keybit = { [BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH) },
+ .absbit = { [BIT_WORD(ABS_X)] =
+ BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) },
+ },
+ /* Keypad */
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
+ .evbit = { BIT_MASK(EV_KEY) },
+ },
+ { },
+};
+
+static struct input_handler cpuboost_input_handler = {
+ .event = cpuboost_input_event,
+ .connect = cpuboost_input_connect,
+ .disconnect = cpuboost_input_disconnect,
+ .name = "cpu-boost",
+ .id_table = cpuboost_ids,
+};
+
+static int cpu_boost_init(void)
+{
+ int cpu, ret;
+ struct cpu_sync *s;
+
+ cpufreq_register_notifier(&boost_adjust_nb, CPUFREQ_POLICY_NOTIFIER);
+
+ cpu_boost_wq = alloc_workqueue("cpuboost_wq", WQ_HIGHPRI, 0);
+ if (!cpu_boost_wq)
+ return -EFAULT;
+
+ INIT_WORK(&input_boost_work, do_input_boost);
+
+ for_each_possible_cpu(cpu) {
+ s = &per_cpu(sync_info, cpu);
+ s->cpu = cpu;
+ init_waitqueue_head(&s->sync_wq);
+ spin_lock_init(&s->lock);
+ INIT_DELAYED_WORK(&s->boost_rem, do_boost_rem);
+ INIT_DELAYED_WORK(&s->input_boost_rem, do_input_boost_rem);
+ s->thread = kthread_run(boost_mig_sync_thread, (void *)cpu,
+ "boost_sync/%d", cpu);
+ }
+ atomic_notifier_chain_register(&migration_notifier_head,
+ &boost_migration_nb);
+
+ ret = input_register_handler(&cpuboost_input_handler);
+ return 0;
+}
+late_initcall(cpu_boost_init);
diff --git a/drivers/cpufreq/cpufreq_interactive.c b/drivers/cpufreq/cpufreq_interactive.c
index eb9cd2e..22448a1 100644
--- a/drivers/cpufreq/cpufreq_interactive.c
+++ b/drivers/cpufreq/cpufreq_interactive.c
@@ -53,6 +53,7 @@
u64 hispeed_validate_time;
struct rw_semaphore enable_sem;
int governor_enabled;
+ int prev_load;
};
static DEFINE_PER_CPU(struct cpufreq_interactive_cpuinfo, cpuinfo);
@@ -70,6 +71,9 @@
#define DEFAULT_GO_HISPEED_LOAD 99
static unsigned long go_hispeed_load = DEFAULT_GO_HISPEED_LOAD;
+/* Sampling down factor to be applied to min_sample_time at max freq */
+static unsigned int sampling_down_factor;
+
/* Target load. Lower values result in higher CPU speeds. */
#define DEFAULT_TARGET_LOAD 90
static unsigned int default_target_loads[] = {DEFAULT_TARGET_LOAD};
@@ -89,6 +93,9 @@
#define DEFAULT_TIMER_RATE (20 * USEC_PER_MSEC)
static unsigned long timer_rate = DEFAULT_TIMER_RATE;
+/* Busy SDF parameters*/
+#define MIN_BUSY_TIME (100 * USEC_PER_MSEC)
+
/*
* Wait this long before raising speed above hispeed, by default a single
* timer interval.
@@ -116,6 +123,13 @@
static bool io_is_busy;
+/*
+ * If the max load among the other CPUs is higher than sync_freq_load_threshold
+ * then do not let the frequency to drop below sync_freq
+ */
+static unsigned int sync_freq_load_threshold;
+static unsigned int sync_freq;
+
static int cpufreq_governor_interactive(struct cpufreq_policy *policy,
unsigned int event);
@@ -227,6 +241,8 @@
;
ret = above_hispeed_delay[i];
+ ret = (ret > (1 * USEC_PER_MSEC)) ? (ret - (1 * USEC_PER_MSEC)) : ret;
+
spin_unlock_irqrestore(&above_hispeed_delay_lock, flags);
return ret;
}
@@ -376,6 +392,9 @@
unsigned int index;
unsigned long flags;
bool boosted;
+ unsigned long mod_min_sample_time;
+ int i, max_load_other_cpu;
+ unsigned int max_freq_other_cpu;
if (!down_read_trylock(&pcpu->enable_sem))
return;
@@ -394,8 +413,23 @@
do_div(cputime_speedadj, delta_time);
loadadjfreq = (unsigned int)cputime_speedadj * 100;
cpu_load = loadadjfreq / pcpu->target_freq;
+ pcpu->prev_load = cpu_load;
boosted = boost_val || now < boostpulse_endtime;
+ max_load_other_cpu = 0;
+ max_freq_other_cpu = 0;
+ for_each_online_cpu(i) {
+ struct cpufreq_interactive_cpuinfo *picpu =
+ &per_cpu(cpuinfo, i);
+ if (i == data)
+ continue;
+ if (max_load_other_cpu < picpu->prev_load)
+ max_load_other_cpu = picpu->prev_load;
+
+ if (picpu->policy->cur > max_freq_other_cpu)
+ max_freq_other_cpu = picpu->policy->cur;
+ }
+
if (cpu_load >= go_hispeed_load || boosted) {
if (pcpu->target_freq < hispeed_freq) {
new_freq = hispeed_freq;
@@ -407,6 +441,10 @@
}
} else {
new_freq = choose_freq(pcpu, loadadjfreq);
+ if (sync_freq && (max_freq_other_cpu > sync_freq) &&
+ (max_load_other_cpu > sync_freq_load_threshold) &&
+ (new_freq < sync_freq))
+ new_freq = sync_freq;
}
if (pcpu->target_freq >= hispeed_freq &&
@@ -432,8 +470,14 @@
* Do not scale below floor_freq unless we have been at or above the
* floor frequency for the minimum sample time since last validated.
*/
+ if (pcpu->policy->cur == pcpu->policy->max) {
+ mod_min_sample_time = sampling_down_factor;
+ } else {
+ mod_min_sample_time = min_sample_time;
+ }
+
if (new_freq < pcpu->floor_freq) {
- if (now - pcpu->floor_validate_time < min_sample_time) {
+ if (now - pcpu->floor_validate_time < mod_min_sample_time) {
trace_cpufreq_interactive_notyet(
data, cpu_load, pcpu->target_freq,
pcpu->policy->cur, new_freq);
@@ -492,6 +536,7 @@
struct cpufreq_interactive_cpuinfo *pcpu =
&per_cpu(cpuinfo, smp_processor_id());
int pending;
+ u64 now;
if (!down_read_trylock(&pcpu->enable_sem))
return;
@@ -511,8 +556,17 @@
* min indefinitely. This should probably be a quirk of
* the CPUFreq driver.
*/
- if (!pending)
+ if (!pending) {
cpufreq_interactive_timer_resched(pcpu);
+
+ now = ktime_to_us(ktime_get());
+ if ((pcpu->policy->cur == pcpu->policy->max) &&
+ (now - pcpu->hispeed_validate_time) >
+ MIN_BUSY_TIME) {
+ pcpu->floor_validate_time = now;
+ }
+
+ }
}
up_read(&pcpu->enable_sem);
@@ -838,6 +892,29 @@
static struct global_attr hispeed_freq_attr = __ATTR(hispeed_freq, 0644,
show_hispeed_freq, store_hispeed_freq);
+static ssize_t show_sampling_down_factor(struct kobject *kobj,
+ struct attribute *attr, char *buf)
+{
+ return sprintf(buf, "%u\n", sampling_down_factor);
+}
+
+static ssize_t store_sampling_down_factor(struct kobject *kobj,
+ struct attribute *attr, const char *buf,
+ size_t count)
+{
+ int ret;
+ long unsigned int val;
+
+ ret = strict_strtoul(buf, 0, &val);
+ if (ret < 0)
+ return ret;
+ sampling_down_factor = val;
+ return count;
+}
+
+static struct global_attr sampling_down_factor_attr =
+ __ATTR(sampling_down_factor, 0644,
+ show_sampling_down_factor, store_sampling_down_factor);
static ssize_t show_go_hispeed_load(struct kobject *kobj,
struct attribute *attr, char *buf)
@@ -1022,6 +1099,52 @@
static struct global_attr io_is_busy_attr = __ATTR(io_is_busy, 0644,
show_io_is_busy, store_io_is_busy);
+static ssize_t show_sync_freq(struct kobject *kobj,
+ struct attribute *attr, char *buf)
+{
+ return sprintf(buf, "%u\n", sync_freq);
+}
+
+static ssize_t store_sync_freq(struct kobject *kobj,
+ struct attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned long val;
+
+ ret = kstrtoul(buf, 0, &val);
+ if (ret < 0)
+ return ret;
+ sync_freq = val;
+ return count;
+}
+
+static struct global_attr sync_freq_attr = __ATTR(sync_freq, 0644,
+ show_sync_freq, store_sync_freq);
+
+static ssize_t show_sync_freq_load_threshold(struct kobject *kobj,
+ struct attribute *attr, char *buf)
+{
+ return sprintf(buf, "%u\n", sync_freq_load_threshold);
+}
+
+static ssize_t store_sync_freq_load_threshold(struct kobject *kobj,
+ struct attribute *attr, const char *buf, size_t count)
+{
+ int ret;
+ unsigned long val;
+
+ ret = kstrtoul(buf, 0, &val);
+ if (ret < 0)
+ return ret;
+ sync_freq_load_threshold = val;
+ return count;
+}
+
+static struct global_attr sync_freq_load_threshold_attr =
+ __ATTR(sync_freq_load_threshold, 0644,
+ show_sync_freq_load_threshold, store_sync_freq_load_threshold);
+
+
static struct attribute *interactive_attributes[] = {
&target_loads_attr.attr,
&above_hispeed_delay_attr.attr,
@@ -1034,6 +1157,9 @@
&boostpulse.attr,
&boostpulse_duration.attr,
&io_is_busy_attr.attr,
+ &sampling_down_factor_attr.attr,
+ &sync_freq_attr.attr,
+ &sync_freq_load_threshold_attr.attr,
NULL,
};
diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c
index af494c6..8f7d39c 100644
--- a/drivers/cpufreq/cpufreq_ondemand.c
+++ b/drivers/cpufreq/cpufreq_ondemand.c
@@ -318,6 +318,7 @@
show_one(down_differential, down_differential);
show_one(sampling_down_factor, sampling_down_factor);
show_one(ignore_nice_load, ignore_nice);
+show_one(down_differential_multi_core, down_differential_multi_core);
show_one(optimal_freq, optimal_freq);
show_one(up_threshold_any_cpu_load, up_threshold_any_cpu_load);
show_one(sync_freq, sync_freq);
@@ -437,6 +438,20 @@
return count;
}
+static ssize_t store_down_differential_multi_core(struct kobject *a,
+ struct attribute *b, const char *buf, size_t count)
+{
+ unsigned int input;
+ int ret;
+
+ ret = sscanf(buf, "%u", &input);
+ if (ret != 1)
+ return -EINVAL;
+ dbs_tuners_ins.down_differential_multi_core = input;
+ return count;
+}
+
+
static ssize_t store_optimal_freq(struct kobject *a, struct attribute *b,
const char *buf, size_t count)
{
@@ -625,10 +640,13 @@
cpumask_set_cpu(cpu, &cpus_timer_done);
if (dbs_info->cur_policy) {
+ dbs_timer_exit(dbs_info);
/* restart dbs timer */
+ mutex_lock(&dbs_info->timer_mutex);
dbs_timer_init(dbs_info);
/* Enable frequency synchronization
* of CPUs */
+ mutex_unlock(&dbs_info->timer_mutex);
atomic_set(&dbs_info->sync_enabled, 1);
}
skip_this_cpu:
@@ -692,6 +710,7 @@
define_one_global_rw(ignore_nice_load);
define_one_global_rw(powersave_bias);
define_one_global_rw(up_threshold_multi_core);
+define_one_global_rw(down_differential_multi_core);
define_one_global_rw(optimal_freq);
define_one_global_rw(up_threshold_any_cpu_load);
define_one_global_rw(sync_freq);
@@ -707,6 +726,7 @@
&powersave_bias.attr,
&io_is_busy.attr,
&up_threshold_multi_core.attr,
+ &down_differential_multi_core.attr,
&optimal_freq.attr,
&up_threshold_any_cpu_load.attr,
&sync_freq.attr,
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index e81cfda..d048a91 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -23,6 +23,7 @@
#include "cpuidle.h"
DEFINE_PER_CPU(struct cpuidle_device *, cpuidle_devices);
+DEFINE_PER_CPU(struct cpuidle_device, cpuidle_dev);
DEFINE_MUTEX(cpuidle_lock);
LIST_HEAD(cpuidle_detected_devices);
@@ -484,6 +485,77 @@
EXPORT_SYMBOL_GPL(cpuidle_unregister_device);
+/*
+ * cpuidle_unregister: unregister a driver and the devices. This function
+ * can be used only if the driver has been previously registered through
+ * the cpuidle_register function.
+ *
+ * @drv: a valid pointer to a struct cpuidle_driver
+ */
+void cpuidle_unregister(struct cpuidle_driver *drv)
+{
+ int cpu;
+ struct cpuidle_device *device;
+
+ for_each_possible_cpu(cpu) {
+ device = &per_cpu(cpuidle_dev, cpu);
+ cpuidle_unregister_device(device);
+ }
+
+ cpuidle_unregister_driver(drv);
+}
+EXPORT_SYMBOL_GPL(cpuidle_unregister);
+
+/**
+ * cpuidle_register: registers the driver and the cpu devices with the
+ * coupled_cpus passed as parameter. This function is used for all common
+ * initialization pattern there are in the arch specific drivers. The
+ * devices is globally defined in this file.
+ *
+ * @drv : a valid pointer to a struct cpuidle_driver
+ * @coupled_cpus: a cpumask for the coupled states
+ *
+ * Returns 0 on success, < 0 otherwise
+ */
+int cpuidle_register(struct cpuidle_driver *drv,
+ const struct cpumask *const coupled_cpus)
+{
+ int ret, cpu;
+ struct cpuidle_device *device;
+
+ ret = cpuidle_register_driver(drv);
+ if (ret) {
+ pr_err("failed to register cpuidle driver\n");
+ return ret;
+ }
+
+ for_each_possible_cpu(cpu) {
+ device = &per_cpu(cpuidle_dev, cpu);
+ device->cpu = cpu;
+
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+ /*
+ * On multiplatform for ARM, the coupled idle states could
+ * enabled in the kernel even if the cpuidle driver does not
+ * use it. Note, coupled_cpus is a struct copy.
+ */
+ if (coupled_cpus)
+ device->coupled_cpus = *coupled_cpus;
+#endif
+ ret = cpuidle_register_device(device);
+ if (!ret)
+ continue;
+
+ pr_err("Failed to register cpuidle device for cpu%d\n", cpu);
+
+ cpuidle_unregister(drv);
+ break;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(cpuidle_register);
+
#ifdef CONFIG_SMP
static void smp_callback(void *v)
diff --git a/drivers/devfreq/governor_msm_adreno_tz.c b/drivers/devfreq/governor_msm_adreno_tz.c
index 57323cb..8c97fe9 100644
--- a/drivers/devfreq/governor_msm_adreno_tz.c
+++ b/drivers/devfreq/governor_msm_adreno_tz.c
@@ -29,6 +29,11 @@
* per frame for 60fps content.
*/
#define FLOOR 5000
+#define LONG_FLOOR 50000
+#define HIST 5
+#define TARGET 80
+#define CAP 75
+
/*
* CEILING is 50msec, larger than any standard
* frame length, but less than the idle timer.
@@ -63,6 +68,17 @@
return ret;
}
+static void _update_cutoff(struct devfreq_msm_adreno_tz_data *priv,
+ unsigned int norm_max)
+{
+ int i;
+
+ priv->bus.max = norm_max;
+ for (i = 0; i < priv->bus.num; i++) {
+ priv->bus.up[i] = priv->bus.p_up[i] * norm_max / 100;
+ priv->bus.down[i] = priv->bus.p_down[i] * norm_max / 100;
+ }
+}
static int tz_get_target_freq(struct devfreq *devfreq, unsigned long *freq,
u32 *flag)
@@ -70,8 +86,16 @@
int result = 0;
struct devfreq_msm_adreno_tz_data *priv = devfreq->data;
struct devfreq_dev_status stats;
+ struct xstats b;
int val, level = 0;
+ int act_level;
+ int norm_cycles;
+ int gpu_percent;
+ if (priv->bus.num)
+ stats.private_data = &b;
+ else
+ stats.private_data = NULL;
result = devfreq->profile->get_dev_status(devfreq->dev.parent, &stats);
if (result) {
pr_err(TAG "get_status failed %d\n", result);
@@ -79,8 +103,16 @@
}
*freq = stats.current_frequency;
+ *flag = 0;
priv->bin.total_time += stats.total_time;
priv->bin.busy_time += stats.busy_time;
+ if (priv->bus.num) {
+ priv->bus.total_time += stats.total_time;
+ priv->bus.gpu_time += stats.busy_time;
+ priv->bus.ram_time += b.ram_time;
+ priv->bus.ram_time += b.ram_wait;
+ }
+
/*
* Do not waste CPU cycles running this algorithm if
* the GPU just started, or if less than FLOOR time
@@ -92,6 +124,7 @@
}
level = devfreq_get_freq_level(devfreq, stats.current_frequency);
+
if (level < 0) {
pr_err(TAG "bad freq %ld\n", stats.current_frequency);
return level;
@@ -102,7 +135,7 @@
* increase frequency. Otherwise run the normal algorithm.
*/
if (priv->bin.busy_time > CEILING) {
- val = -1;
+ val = -1 * level;
} else {
val = __secure_tz_entry3(TZ_UPDATE_ID,
level,
@@ -113,23 +146,54 @@
priv->bin.busy_time = 0;
/*
- * If the decision is to move to a lower level, make sure the GPU
- * frequency drops.
+ * If the decision is to move to a different level, make sure the GPU
+ * frequency changes.
*/
- level += val;
- level = max(level, 0);
- level = min_t(int, level, devfreq->profile->max_state);
- *freq = devfreq->profile->freq_table[level];
-
- /*
- * By setting freq as UINT_MAX we notify the kgsl target function
- * to go up one power level without considering the freq value
- */
- if (val < 0) {
- *flag = DEVFREQ_FLAG_FAST_HINT;
- *freq = UINT_MAX;
+ if (val) {
+ level += val;
+ level = max(level, 0);
+ level = min_t(int, level, devfreq->profile->max_state);
+ goto clear;
}
+ if (priv->bus.total_time < LONG_FLOOR)
+ goto end;
+ norm_cycles = (unsigned int)priv->bus.ram_time /
+ (unsigned int) priv->bus.total_time;
+ gpu_percent = (100 * (unsigned int)priv->bus.gpu_time) /
+ (unsigned int) priv->bus.total_time;
+ /*
+ * If there's a new high watermark, update the cutoffs and send the
+ * FAST hint. Otherwise check the current value against the current
+ * cutoffs.
+ */
+ if (norm_cycles > priv->bus.max) {
+ _update_cutoff(priv, norm_cycles);
+ *flag = DEVFREQ_FLAG_FAST_HINT;
+ } else {
+ /*
+ * Normalize by gpu_time unless it is a small fraction of
+ * the total time interval.
+ */
+ norm_cycles = (100 * norm_cycles) / TARGET;
+ act_level = priv->bus.index[level] + b.mod;
+ act_level = (act_level < 0) ? 0 : act_level;
+ act_level = (act_level >= priv->bus.num) ?
+ (priv->bus.num - 1) : act_level;
+ if (norm_cycles > priv->bus.up[act_level] &&
+ gpu_percent > CAP)
+ *flag = DEVFREQ_FLAG_FAST_HINT;
+ else if (norm_cycles < priv->bus.down[act_level] && level)
+ *flag = DEVFREQ_FLAG_SLOW_HINT;
+ }
+
+clear:
+ priv->bus.total_time = 0;
+ priv->bus.gpu_time = 0;
+ priv->bus.ram_time = 0;
+
+end:
+ *freq = devfreq->profile->freq_table[level];
return 0;
}
@@ -157,6 +221,7 @@
{
struct devfreq_msm_adreno_tz_data *priv;
unsigned int tz_pwrlevels[MSM_ADRENO_MAX_PWRLEVELS + 1];
+ unsigned int t1, t2 = 2 * HIST;
int i, out, ret;
if (devfreq->data == NULL) {
@@ -183,6 +248,24 @@
if (ret != 0)
pr_err(TAG "tz_init failed\n");
+ /* Set up the cut-over percentages for the bus calculation. */
+ if (priv->bus.num) {
+ for (i = 0; i < priv->bus.num; i++) {
+ t1 = (u32)(100 * priv->bus.ib[i]) /
+ (u32)priv->bus.ib[priv->bus.num - 1];
+ priv->bus.p_up[i] = t1 - HIST;
+ priv->bus.p_down[i] = t2 - 2 * HIST;
+ t2 = t1;
+ }
+ /* Set the upper-most and lower-most bounds correctly. */
+ priv->bus.p_down[0] = 0;
+ priv->bus.p_down[1] = (priv->bus.p_down[1] > (2 * HIST)) ?
+ priv->bus.p_down[1] : (2 * HIST);
+ if (priv->bus.num - 1 >= 0)
+ priv->bus.p_up[priv->bus.num - 1] = 100;
+ _update_cutoff(priv, priv->bus.max);
+ }
+
return kgsl_devfreq_add_notifier(devfreq->dev.parent, &priv->nb);
}
@@ -202,8 +285,7 @@
freq = profile->initial_freq;
- return profile->target(devfreq->dev.parent, &freq,
- DEVFREQ_FLAG_LEAST_UPPER_BOUND);
+ return profile->target(devfreq->dev.parent, &freq, 0);
}
static int tz_suspend(struct devfreq *devfreq)
@@ -214,6 +296,9 @@
priv->bin.total_time = 0;
priv->bin.busy_time = 0;
+ priv->bus.total_time = 0;
+ priv->bus.gpu_time = 0;
+ priv->bus.ram_time = 0;
return 0;
}
diff --git a/drivers/gpu/ion/ion.c b/drivers/gpu/ion/ion.c
index c791c49..0809308 100644
--- a/drivers/gpu/ion/ion.c
+++ b/drivers/gpu/ion/ion.c
@@ -1784,6 +1784,28 @@
}
EXPORT_SYMBOL(ion_secure_heap);
+int ion_walk_heaps(struct ion_client *client, int heap_id, void *data,
+ int (*f)(struct ion_heap *heap, void *data))
+{
+ int ret_val = -EINVAL;
+ struct ion_heap *heap;
+ struct ion_device *dev = client->dev;
+ /*
+ * traverse the list of heaps available in this system
+ * and find the heap that is specified.
+ */
+ down_write(&dev->lock);
+ plist_for_each_entry(heap, &dev->heaps, node) {
+ if (ION_HEAP(heap->id) != heap_id)
+ continue;
+ ret_val = f(heap, data);
+ break;
+ }
+ up_write(&dev->lock);
+ return ret_val;
+}
+EXPORT_SYMBOL(ion_walk_heaps);
+
int ion_unsecure_heap(struct ion_device *dev, int heap_id, int version,
void *data)
{
diff --git a/drivers/gpu/ion/ion_cma_secure_heap.c b/drivers/gpu/ion/ion_cma_secure_heap.c
index bdf48b3..d375c00 100644
--- a/drivers/gpu/ion/ion_cma_secure_heap.c
+++ b/drivers/gpu/ion/ion_cma_secure_heap.c
@@ -38,19 +38,72 @@
* This needs to come first for compatibility with the secure buffer API
*/
struct ion_cp_buffer secure;
- void *cpu_addr;
- dma_addr_t handle;
+ dma_addr_t phys;
struct sg_table *table;
bool is_cached;
};
+struct ion_cma_alloc_chunk {
+ void *cpu_addr;
+ struct list_head entry;
+ dma_addr_t handle;
+ unsigned long chunk_size;
+ atomic_t cnt;
+};
+
+struct ion_cma_secure_heap {
+ struct device *dev;
+ /*
+ * Protects against races between threads allocating memory/adding to
+ * pool at the same time. (e.g. thread 1 adds to pool, thread 2
+ * allocates thread 1's memory before thread 1 knows it needs to
+ * allocate more.
+ * Admittedly this is fairly coarse grained right now but the chance for
+ * contention on this lock is unlikely right now. This can be changed if
+ * this ever changes in the future
+ */
+ struct mutex alloc_lock;
+ /*
+ * protects the list of memory chunks in this pool
+ */
+ struct mutex chunk_lock;
+ struct ion_heap heap;
+ /*
+ * Bitmap for allocation. This contains the aggregate of all chunks. */
+ unsigned long *bitmap;
+ /*
+ * List of all allocated chunks
+ *
+ * This is where things get 'clever'. Individual allocations from
+ * dma_alloc_coherent must be allocated and freed in one chunk.
+ * We don't just want to limit the allocations to those confined
+ * within a single chunk (if clients allocate n small chunks we would
+ * never be able to use the combined size). The bitmap allocator is
+ * used to find the contiguous region and the parts of the chunks are
+ * marked off as used. The chunks won't be freed in the shrinker until
+ * the usage is actually zero.
+ */
+ struct list_head chunks;
+ int npages;
+ ion_phys_addr_t base;
+ struct work_struct work;
+ unsigned long last_alloc;
+ struct shrinker shrinker;
+ atomic_t total_allocated;
+ atomic_t total_pool_size;
+ unsigned long heap_size;
+ unsigned long default_prefetch_size;
+};
+
+static void ion_secure_pool_pages(struct work_struct *work);
+
/*
* Create scatter-list for the already allocated DMA buffer.
* This function could be replace by dma_common_get_sgtable
* as soon as it will avalaible.
*/
int ion_secure_cma_get_sgtable(struct device *dev, struct sg_table *sgt,
- void *cpu_addr, dma_addr_t handle, size_t size)
+ dma_addr_t handle, size_t size)
{
struct page *page = phys_to_page(handle);
int ret;
@@ -64,47 +117,364 @@
return 0;
}
+static int ion_secure_cma_add_to_pool(
+ struct ion_cma_secure_heap *sheap,
+ unsigned long len)
+{
+ void *cpu_addr;
+ dma_addr_t handle;
+ DEFINE_DMA_ATTRS(attrs);
+ int ret = 0;
+ struct ion_cma_alloc_chunk *chunk;
+
+ mutex_lock(&sheap->chunk_lock);
+
+ chunk = kzalloc(sizeof(*chunk), GFP_KERNEL);
+ if (!chunk) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
+
+ cpu_addr = dma_alloc_attrs(sheap->dev, len, &handle, GFP_KERNEL,
+ &attrs);
+
+ if (!cpu_addr) {
+ ret = -ENOMEM;
+ goto out_free;
+ }
+
+ chunk->cpu_addr = cpu_addr;
+ chunk->handle = handle;
+ chunk->chunk_size = len;
+ atomic_set(&chunk->cnt, 0);
+ list_add(&chunk->entry, &sheap->chunks);
+ atomic_add(len, &sheap->total_pool_size);
+ /* clear the bitmap to indicate this region can be allocated from */
+ bitmap_clear(sheap->bitmap, (handle - sheap->base) >> PAGE_SHIFT,
+ len >> PAGE_SHIFT);
+ goto out;
+
+out_free:
+ kfree(chunk);
+out:
+ mutex_unlock(&sheap->chunk_lock);
+ return ret;
+}
+
+static void ion_secure_pool_pages(struct work_struct *work)
+{
+ struct ion_cma_secure_heap *sheap = container_of(work,
+ struct ion_cma_secure_heap, work);
+
+ ion_secure_cma_add_to_pool(sheap, sheap->last_alloc);
+}
+/*
+ * @s1: start of the first region
+ * @l1: length of the first region
+ * @s2: start of the second region
+ * @l2: length of the second region
+ *
+ * Returns the total number of bytes that intersect.
+ *
+ * s1 is the region we are trying to clear so s2 may be subsumed by s1 but the
+ * maximum size to clear should only ever be l1
+ *
+ */
+static unsigned int intersect(unsigned long s1, unsigned long l1,
+ unsigned long s2, unsigned long l2)
+{
+ unsigned long base1 = s1;
+ unsigned long end1 = s1 + l1;
+ unsigned long base2 = s2;
+ unsigned long end2 = s2 + l2;
+
+ /* Case 0: The regions don't overlap at all */
+ if (!(base1 < end2 && base2 < end1))
+ return 0;
+
+ /* Case 1: region 2 is subsumed by region 1 */
+ if (base1 <= base2 && end2 <= end1)
+ return l2;
+
+ /* case 2: region 1 is subsumed by region 2 */
+ if (base2 <= base1 && end1 <= end2)
+ return l1;
+
+ /* case 3: region1 overlaps region2 on the bottom */
+ if (base2 < end1 && base2 > base1)
+ return end1 - base2;
+
+ /* case 4: region 2 overlaps region1 on the bottom */
+ if (base1 < end2 && base1 > base2)
+ return end2 - base1;
+
+ pr_err("Bad math! Did not detect chunks correctly! %lx %lx %lx %lx\n",
+ s1, l1, s2, l2);
+ BUG();
+}
+
+int ion_secure_cma_prefetch(struct ion_heap *heap, void *data)
+{
+ unsigned long len = (unsigned long)data;
+ struct ion_cma_secure_heap *sheap =
+ container_of(heap, struct ion_cma_secure_heap, heap);
+ unsigned long diff;
+
+ if ((int) heap->type != ION_HEAP_TYPE_SECURE_DMA)
+ return -EINVAL;
+
+ if (len == 0)
+ len = sheap->default_prefetch_size;
+
+ /*
+ * Only prefetch as much space as there is left in the pool so
+ * check against the current free size of the heap.
+ * This is slightly racy if someone else is allocating at the same
+ * time. CMA has a restricted size for the heap so worst case
+ * the prefetch doesn't work because the allocation fails.
+ */
+ diff = sheap->heap_size - atomic_read(&sheap->total_pool_size);
+
+ if (len > diff)
+ len = diff;
+
+ sheap->last_alloc = len;
+ schedule_work(&sheap->work);
+
+ return 0;
+}
+
+static void bad_math_dump(unsigned long len, int total_overlap,
+ struct ion_cma_secure_heap *sheap,
+ bool alloc, dma_addr_t paddr)
+{
+ struct list_head *entry;
+
+ pr_err("Bad math! expected total was %lx actual was %x\n",
+ len, total_overlap);
+ pr_err("attempted %s address was %pa len %lx\n",
+ alloc ? "allocation" : "free", &paddr, len);
+ pr_err("chunks:\n");
+ list_for_each(entry, &sheap->chunks) {
+ struct ion_cma_alloc_chunk *chunk =
+ container_of(entry,
+ struct ion_cma_alloc_chunk, entry);
+ pr_info("--- pa %pa len %lx\n",
+ &chunk->handle, chunk->chunk_size);
+ }
+ BUG();
+
+}
+
+static int ion_secure_cma_alloc_from_pool(
+ struct ion_cma_secure_heap *sheap,
+ dma_addr_t *phys,
+ unsigned long len)
+{
+ dma_addr_t paddr;
+ unsigned long page_no;
+ int ret = 0;
+ int total_overlap = 0;
+ struct list_head *entry;
+
+ mutex_lock(&sheap->chunk_lock);
+
+ page_no = bitmap_find_next_zero_area(sheap->bitmap,
+ sheap->npages, 0, len >> PAGE_SHIFT, 0);
+ if (page_no >= sheap->npages) {
+ ret = -ENOMEM;
+ goto out;
+ }
+ bitmap_set(sheap->bitmap, page_no, len >> PAGE_SHIFT);
+ paddr = sheap->base + (page_no << PAGE_SHIFT);
+
+
+ list_for_each(entry, &sheap->chunks) {
+ struct ion_cma_alloc_chunk *chunk = container_of(entry,
+ struct ion_cma_alloc_chunk, entry);
+ int overlap = intersect(chunk->handle,
+ chunk->chunk_size, paddr, len);
+
+ atomic_add(overlap, &chunk->cnt);
+ total_overlap += overlap;
+ }
+
+ if (total_overlap != len)
+ bad_math_dump(len, total_overlap, sheap, 1, paddr);
+
+ *phys = paddr;
+out:
+ mutex_unlock(&sheap->chunk_lock);
+ return ret;
+}
+
+static void ion_secure_cma_free_chunk(struct ion_cma_secure_heap *sheap,
+ struct ion_cma_alloc_chunk *chunk)
+{
+ /* This region is 'allocated' and not available to allocate from */
+ bitmap_set(sheap->bitmap, (chunk->handle - sheap->base) >> PAGE_SHIFT,
+ chunk->chunk_size >> PAGE_SHIFT);
+ dma_free_coherent(sheap->dev, chunk->chunk_size, chunk->cpu_addr,
+ chunk->handle);
+ atomic_sub(chunk->chunk_size, &sheap->total_pool_size);
+ list_del(&chunk->entry);
+ kfree(chunk);
+
+}
+
+int ion_secure_cma_drain_pool(struct ion_heap *heap, void *unused)
+{
+ struct ion_cma_secure_heap *sheap =
+ container_of(heap, struct ion_cma_secure_heap, heap);
+ struct list_head *entry, *_n;
+
+ mutex_lock(&sheap->chunk_lock);
+ list_for_each_safe(entry, _n, &sheap->chunks) {
+ struct ion_cma_alloc_chunk *chunk = container_of(entry,
+ struct ion_cma_alloc_chunk, entry);
+
+ if (atomic_read(&chunk->cnt) == 0)
+ ion_secure_cma_free_chunk(sheap, chunk);
+ }
+ mutex_unlock(&sheap->chunk_lock);
+
+ return 0;
+}
+
+static int ion_secure_cma_shrinker(struct shrinker *shrinker,
+ struct shrink_control *sc)
+{
+ struct ion_cma_secure_heap *sheap = container_of(shrinker,
+ struct ion_cma_secure_heap, shrinker);
+ int nr_to_scan = sc->nr_to_scan;
+ struct list_head *entry, *_n;
+
+ if (nr_to_scan == 0)
+ return atomic_read(&sheap->total_pool_size);
+
+ /*
+ * CMA pages can only be used for movable allocation so don't free if
+ * the allocation isn't movable
+ */
+ if (!(sc->gfp_mask & __GFP_MOVABLE))
+ return atomic_read(&sheap->total_pool_size);
+
+ /*
+ * Allocation path may recursively call the shrinker. Don't shrink if
+ * that happens.
+ */
+ if (!mutex_trylock(&sheap->chunk_lock))
+ return -1;
+
+ list_for_each_safe(entry, _n, &sheap->chunks) {
+ struct ion_cma_alloc_chunk *chunk = container_of(entry,
+ struct ion_cma_alloc_chunk, entry);
+
+ if (nr_to_scan < 0)
+ break;
+
+ if (atomic_read(&chunk->cnt) == 0) {
+ nr_to_scan -= chunk->chunk_size;
+ ion_secure_cma_free_chunk(sheap, chunk);
+ }
+ }
+ mutex_unlock(&sheap->chunk_lock);
+
+ return atomic_read(&sheap->total_pool_size);
+}
+
+static void ion_secure_cma_free_from_pool(struct ion_cma_secure_heap *sheap,
+ dma_addr_t handle,
+ unsigned long len)
+{
+ struct list_head *entry, *_n;
+ int total_overlap = 0;
+
+ mutex_lock(&sheap->chunk_lock);
+ bitmap_clear(sheap->bitmap, (handle - sheap->base) >> PAGE_SHIFT,
+ len >> PAGE_SHIFT);
+
+ list_for_each_safe(entry, _n, &sheap->chunks) {
+ struct ion_cma_alloc_chunk *chunk = container_of(entry,
+ struct ion_cma_alloc_chunk, entry);
+ int overlap = intersect(chunk->handle,
+ chunk->chunk_size, handle, len);
+
+ /*
+ * Don't actually free this from the pool list yet, let either
+ * an explicit drain call or the shrinkers take care of the
+ * pool.
+ */
+ atomic_sub_return(overlap, &chunk->cnt);
+ BUG_ON(atomic_read(&chunk->cnt) < 0);
+
+ total_overlap += overlap;
+ }
+
+ BUG_ON(atomic_read(&sheap->total_pool_size) < 0);
+
+ if (total_overlap != len)
+ bad_math_dump(len, total_overlap, sheap, 0, handle);
+
+ mutex_unlock(&sheap->chunk_lock);
+}
+
/* ION CMA heap operations functions */
static struct ion_secure_cma_buffer_info *__ion_secure_cma_allocate(
struct ion_heap *heap, struct ion_buffer *buffer,
unsigned long len, unsigned long align,
unsigned long flags)
{
- struct device *dev = heap->priv;
+ struct ion_cma_secure_heap *sheap =
+ container_of(heap, struct ion_cma_secure_heap, heap);
struct ion_secure_cma_buffer_info *info;
- DEFINE_DMA_ATTRS(attrs);
- dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
+ int ret;
- dev_dbg(dev, "Request buffer allocation len %ld\n", len);
+ dev_dbg(sheap->dev, "Request buffer allocation len %ld\n", len);
info = kzalloc(sizeof(struct ion_secure_cma_buffer_info), GFP_KERNEL);
if (!info) {
- dev_err(dev, "Can't allocate buffer info\n");
+ dev_err(sheap->dev, "Can't allocate buffer info\n");
return ION_CMA_ALLOCATE_FAILED;
}
- info->cpu_addr = dma_alloc_attrs(dev, len, &(info->handle), GFP_KERNEL,
- &attrs);
+ mutex_lock(&sheap->alloc_lock);
+ ret = ion_secure_cma_alloc_from_pool(sheap, &info->phys, len);
- if (!info->cpu_addr) {
- dev_err(dev, "Fail to allocate buffer\n");
- goto err;
+ if (ret) {
+ ret = ion_secure_cma_add_to_pool(sheap, len);
+ if (ret) {
+ dev_err(sheap->dev, "Fail to allocate buffer\n");
+ goto err;
+ }
+ ret = ion_secure_cma_alloc_from_pool(sheap, &info->phys, len);
+ if (ret) {
+ /*
+ * We just added memory to the pool, we shouldn't be
+ * failing to get memory
+ */
+ BUG();
+ }
}
+ mutex_unlock(&sheap->alloc_lock);
+ atomic_add(len, &sheap->total_allocated);
info->table = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
if (!info->table) {
- dev_err(dev, "Fail to allocate sg table\n");
+ dev_err(sheap->dev, "Fail to allocate sg table\n");
goto err;
}
- ion_secure_cma_get_sgtable(dev,
- info->table, info->cpu_addr, info->handle, len);
+ ion_secure_cma_get_sgtable(sheap->dev,
+ info->table, info->phys, len);
- info->secure.buffer = info->handle;
+ info->secure.buffer = info->phys;
/* keep this for memory release */
buffer->priv_virt = info;
- dev_dbg(dev, "Allocate buffer %p\n", buffer);
+ dev_dbg(sheap->dev, "Allocate buffer %p\n", buffer);
return info;
err:
@@ -167,16 +537,18 @@
static void ion_secure_cma_free(struct ion_buffer *buffer)
{
- struct device *dev = buffer->heap->priv;
+ struct ion_cma_secure_heap *sheap =
+ container_of(buffer->heap, struct ion_cma_secure_heap, heap);
struct ion_secure_cma_buffer_info *info = buffer->priv_virt;
- dev_dbg(dev, "Release buffer %p\n", buffer);
-
+ dev_dbg(sheap->dev, "Release buffer %p\n", buffer);
ion_cp_unsecure_buffer(buffer, 1);
+ atomic_sub(buffer->size, &sheap->total_allocated);
+ BUG_ON(atomic_read(&sheap->total_allocated) < 0);
/* release memory */
- dma_free_coherent(dev, buffer->size, info->cpu_addr, info->handle);
- sg_free_table(info->table);
+ ion_secure_cma_free_from_pool(sheap, info->phys, buffer->size);
/* release sg table */
+ sg_free_table(info->table);
kfree(info->table);
kfree(info);
}
@@ -184,13 +556,14 @@
static int ion_secure_cma_phys(struct ion_heap *heap, struct ion_buffer *buffer,
ion_phys_addr_t *addr, size_t *len)
{
- struct device *dev = heap->priv;
+ struct ion_cma_secure_heap *sheap =
+ container_of(heap, struct ion_cma_secure_heap, heap);
struct ion_secure_cma_buffer_info *info = buffer->priv_virt;
- dev_dbg(dev, "Return buffer %p physical address 0x%pa\n", buffer,
- &info->handle);
+ dev_dbg(sheap->dev, "Return buffer %p physical address 0x%pa\n", buffer,
+ &info->phys);
- *addr = info->handle;
+ *addr = info->phys;
*len = buffer->size;
return 0;
@@ -236,6 +609,9 @@
static int ion_secure_cma_print_debug(struct ion_heap *heap, struct seq_file *s,
const struct list_head *mem_map)
{
+ struct ion_cma_secure_heap *sheap =
+ container_of(heap, struct ion_cma_secure_heap, heap);
+
if (mem_map) {
struct mem_map_data *data;
@@ -257,6 +633,10 @@
data->size, data->size);
}
}
+ seq_printf(s, "Total allocated: %x\n",
+ atomic_read(&sheap->total_allocated));
+ seq_printf(s, "Total pool size: %x\n",
+ atomic_read(&sheap->total_pool_size));
return 0;
}
@@ -276,22 +656,53 @@
struct ion_heap *ion_secure_cma_heap_create(struct ion_platform_heap *data)
{
- struct ion_heap *heap;
+ struct ion_cma_secure_heap *sheap;
+ int map_size = BITS_TO_LONGS(data->size >> PAGE_SHIFT) * sizeof(long);
- heap = kzalloc(sizeof(struct ion_heap), GFP_KERNEL);
-
- if (!heap)
+ sheap = kzalloc(sizeof(*sheap), GFP_KERNEL);
+ if (!sheap)
return ERR_PTR(-ENOMEM);
- heap->ops = &ion_secure_cma_ops;
- /* set device as private heaps data, later it will be
- * used to make the link with reserved CMA memory */
- heap->priv = data->priv;
- heap->type = ION_HEAP_TYPE_SECURE_DMA;
- return heap;
+ sheap->dev = data->priv;
+ mutex_init(&sheap->chunk_lock);
+ mutex_init(&sheap->alloc_lock);
+ sheap->heap.ops = &ion_secure_cma_ops;
+ sheap->heap.type = ION_HEAP_TYPE_SECURE_DMA;
+ sheap->npages = data->size >> PAGE_SHIFT;
+ sheap->base = data->base;
+ sheap->heap_size = data->size;
+ sheap->bitmap = kmalloc(map_size, GFP_KERNEL);
+ INIT_LIST_HEAD(&sheap->chunks);
+ INIT_WORK(&sheap->work, ion_secure_pool_pages);
+ sheap->shrinker.seeks = DEFAULT_SEEKS;
+ sheap->shrinker.batch = 0;
+ sheap->shrinker.shrink = ion_secure_cma_shrinker;
+ sheap->default_prefetch_size = sheap->heap_size;
+ register_shrinker(&sheap->shrinker);
+
+ if (!sheap->bitmap) {
+ kfree(sheap);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ if (data->extra_data) {
+ struct ion_cma_pdata *extra = data->extra_data;
+ sheap->default_prefetch_size = extra->default_prefetch_size;
+ }
+
+ /*
+ * we initially mark everything in the allocator as being free so that
+ * allocations can come in later
+ */
+ bitmap_fill(sheap->bitmap, sheap->npages);
+
+ return &sheap->heap;
}
void ion_secure_cma_heap_destroy(struct ion_heap *heap)
{
- kfree(heap);
+ struct ion_cma_secure_heap *sheap =
+ container_of(heap, struct ion_cma_secure_heap, heap);
+
+ kfree(sheap);
}
diff --git a/drivers/gpu/ion/ion_priv.h b/drivers/gpu/ion/ion_priv.h
index 2b00ee6..f5d0287 100644
--- a/drivers/gpu/ion/ion_priv.h
+++ b/drivers/gpu/ion/ion_priv.h
@@ -393,4 +393,7 @@
int ion_page_pool_shrink(struct ion_page_pool *pool, gfp_t gfp_mask,
int nr_to_scan);
+int ion_walk_heaps(struct ion_client *client, int heap_id, void *data,
+ int (*f)(struct ion_heap *heap, void *data));
+
#endif /* _ION_PRIV_H */
diff --git a/drivers/gpu/ion/msm/msm_ion.c b/drivers/gpu/ion/msm/msm_ion.c
index c77bac7..213bcb1 100644
--- a/drivers/gpu/ion/msm/msm_ion.c
+++ b/drivers/gpu/ion/msm/msm_ion.c
@@ -19,6 +19,7 @@
#include <linux/memory_alloc.h>
#include <linux/of.h>
#include <linux/of_platform.h>
+#include <linux/of_address.h>
#include <linux/mm.h>
#include <linux/mm_types.h>
#include <linux/sched.h>
@@ -26,6 +27,7 @@
#include <linux/uaccess.h>
#include <linux/memblock.h>
#include <linux/dma-mapping.h>
+#include <linux/dma-contiguous.h>
#include <mach/ion.h>
#include <mach/msm_memtypes.h>
#include <asm/cacheflush.h>
@@ -552,7 +554,8 @@
}
#ifdef CONFIG_OF
-static int msm_init_extra_data(struct ion_platform_heap *heap,
+static int msm_init_extra_data(struct device_node *node,
+ struct ion_platform_heap *heap,
const struct ion_heap_desc *heap_desc)
{
int ret = 0;
@@ -578,6 +581,28 @@
ret = -ENOMEM;
break;
}
+ case ION_HEAP_TYPE_SECURE_DMA:
+ {
+ unsigned int val;
+
+ ret = of_property_read_u32(node,
+ "qcom,default-prefetch-size", &val);
+
+ if (!ret) {
+ heap->extra_data = kzalloc(sizeof(struct ion_cma_pdata),
+ GFP_KERNEL);
+
+ if (!heap->extra_data) {
+ ret = -ENOMEM;
+ } else {
+ struct ion_cma_pdata *extra = heap->extra_data;
+ extra->default_prefetch_size = val;
+ }
+ } else {
+ ret = 0;
+ }
+ break;
+ }
default:
heap->extra_data = 0;
break;
@@ -637,7 +662,8 @@
if (ret)
break;
heap->type = heap_type;
- ret = msm_init_extra_data(heap, &ion_heap_meta[i]);
+ ret = msm_init_extra_data(node, heap,
+ &ion_heap_meta[i]);
break;
}
}
@@ -699,6 +725,7 @@
int ret = 0;
u32 out_values[2];
const char *memory_name_prop;
+ struct device_node *pnode;
ret = of_property_read_u32(node, "qcom,memory-reservation-size", &val);
if (!ret) {
@@ -720,14 +747,33 @@
__func__);
ret = -EINVAL;
}
- } else {
- ret = of_property_read_u32_array(node, "qcom,memory-fixed",
- out_values, 2);
- if (!ret)
- heap->size = out_values[1];
- else
- ret = 0;
+ goto out;
}
+
+ ret = of_property_read_u32_array(node, "qcom,memory-fixed",
+ out_values, 2);
+ if (!ret) {
+ heap->size = out_values[1];
+ goto out;
+ }
+
+ pnode = of_parse_phandle(node, "linux,contiguous-region", 0);
+ if (pnode != NULL) {
+ const u32 *addr;
+ u64 size;
+
+ addr = of_get_address(pnode, 0, &size, NULL);
+ if (!addr) {
+ of_node_put(pnode);
+ ret = -EINVAL;
+ goto out;
+ }
+ heap->size = (u32) size;
+ ret = 0;
+ of_node_put(pnode);
+ }
+
+ ret = 0;
out:
return ret;
}
@@ -737,11 +783,19 @@
{
u32 out_values[2];
int ret = 0;
+ struct device_node *pnode;
ret = of_property_read_u32_array(node, "qcom,memory-fixed",
out_values, 2);
if (!ret)
heap->base = out_values[0];
+
+ pnode = of_parse_phandle(node, "linux,contiguous-region", 0);
+ if (pnode != NULL) {
+ heap->base = cma_get_base(heap->priv);
+ of_node_put(pnode);
+ }
+
return;
}
@@ -957,6 +1011,31 @@
break;
}
+ case ION_IOC_PREFETCH:
+ {
+ struct ion_prefetch_data data;
+
+ if (copy_from_user(&data, (void __user *)arg,
+ sizeof(struct ion_prefetch_data)))
+ return -EFAULT;
+
+ ion_walk_heaps(client, data.heap_id, (void *)data.len,
+ ion_secure_cma_prefetch);
+ break;
+ }
+ case ION_IOC_DRAIN:
+ {
+ struct ion_prefetch_data data;
+
+ if (copy_from_user(&data, (void __user *)arg,
+ sizeof(struct ion_prefetch_data)))
+ return -EFAULT;
+
+ ion_walk_heaps(client, data.heap_id, (void *)data.len,
+ ion_secure_cma_drain_pool);
+ break;
+ }
+
default:
return -ENOTTY;
}
diff --git a/drivers/gpu/ion/msm_ion_priv.h b/drivers/gpu/ion/msm_ion_priv.h
index 412ead2..83cc7b5 100644
--- a/drivers/gpu/ion/msm_ion_priv.h
+++ b/drivers/gpu/ion/msm_ion_priv.h
@@ -55,6 +55,24 @@
struct ion_heap *ion_secure_cma_heap_create(struct ion_platform_heap *);
void ion_secure_cma_heap_destroy(struct ion_heap *);
+
+int ion_secure_cma_prefetch(struct ion_heap *heap, void *data);
+
+int ion_secure_cma_drain_pool(struct ion_heap *heap, void *unused);
+
+#else
+static inline int ion_secure_cma_prefetch(struct ion_heap *heap, void *data)
+{
+ return -ENODEV;
+}
+
+static inline int ion_secure_cma_drain_pool(struct ion_heap *heap, void *unused)
+{
+ return -ENODEV;
+}
+
+
+
#endif
struct ion_heap *ion_removed_heap_create(struct ion_platform_heap *);
diff --git a/drivers/gpu/msm/a3xx_reg.h b/drivers/gpu/msm/a3xx_reg.h
index 676f46d..758d5c5 100644
--- a/drivers/gpu/msm/a3xx_reg.h
+++ b/drivers/gpu/msm/a3xx_reg.h
@@ -775,6 +775,9 @@
#define SP0_ICL1_MISSES 0x1A
#define SP_FS_CFLOW_INSTRUCTIONS 0x0C
+/* COUNTABLE FOR TSE PERFCOUNTER */
+#define TSE_INPUT_PRIM_NUM 0x0
+
/* VBIF PERFCOUNTER ENA/CLR values */
#define VBIF_PERF_CNT_0 BIT(0)
#define VBIF_PERF_CNT_1 BIT(1)
@@ -789,6 +792,7 @@
#define VBIF_PERF_CNT_1_SEL_MASK 0x7f00
/* VBIF countables */
+#define VBIF_AXI_TOTAL_BEATS 85
#define VBIF_DDR_TOTAL_CYCLES 110
#endif
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index e9cf64b..070b5ac 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -19,6 +19,7 @@
#include <linux/of_device.h>
#include <linux/delay.h>
#include <linux/of_coresight.h>
+#include <linux/input.h>
#include <mach/socinfo.h>
#include <mach/msm_bus_board.h>
@@ -77,6 +78,9 @@
#define KGSL_LOG_LEVEL_DEFAULT 3
+static void adreno_start_work(struct work_struct *work);
+static void adreno_input_work(struct work_struct *work);
+
/*
* The default values for the simpleondemand governor are 90 and 5,
* we use different values here.
@@ -88,6 +92,9 @@
};
static struct devfreq_msm_adreno_tz_data adreno_tz_data = {
+ .bus = {
+ .max = 450,
+ },
.device_id = KGSL_DEVICE_3D0,
};
@@ -144,10 +151,16 @@
.ft_pf_policy = KGSL_FT_PAGEFAULT_DEFAULT_POLICY,
.fast_hang_detect = 1,
.long_ib_detect = 1,
+ .start_work = __WORK_INITIALIZER(device_3d0.start_work,
+ adreno_start_work),
+ .input_work = __WORK_INITIALIZER(device_3d0.input_work,
+ adreno_input_work),
};
unsigned int ft_detect_regs[FT_DETECT_REGS_COUNT];
+static struct workqueue_struct *adreno_wq;
+
/*
* This is the master list of all GPU cores that are supported by this
* driver.
@@ -241,6 +254,122 @@
512, 0, 2, SZ_128K, 0x3FF037, 0x3FF016 },
};
+/* Nice level for the higher priority GPU start thread */
+static unsigned int _wake_nice = -7;
+
+/* Number of milliseconds to stay active active after a wake on touch */
+static unsigned int _wake_timeout = 100;
+
+/*
+ * A workqueue callback responsible for actually turning on the GPU after a
+ * touch event. kgsl_pwrctrl_wake() is used without any active_count protection
+ * to avoid the need to maintain state. Either somebody will start using the
+ * GPU or the idle timer will fire and put the GPU back into slumber
+ */
+static void adreno_input_work(struct work_struct *work)
+{
+ struct adreno_device *adreno_dev = container_of(work,
+ struct adreno_device, input_work);
+ struct kgsl_device *device = &adreno_dev->dev;
+
+ mutex_lock(&device->mutex);
+
+ device->flags |= KGSL_FLAG_WAKE_ON_TOUCH;
+
+ /*
+ * Don't schedule adreno_start in a high priority workqueue, we are
+ * already in a workqueue which should be sufficient
+ */
+ kgsl_pwrctrl_wake(device, 0);
+
+ /*
+ * When waking up from a touch event we want to stay active long enough
+ * for the user to send a draw command. The default idle timer timeout
+ * is shorter than we want so go ahead and push the idle timer out
+ * further for this special case
+ */
+ mod_timer(&device->idle_timer,
+ jiffies + msecs_to_jiffies(_wake_timeout));
+ mutex_unlock(&device->mutex);
+}
+
+/*
+ * Process input events and schedule work if needed. At this point we are only
+ * interested in groking EV_ABS touchscreen events
+ */
+static void adreno_input_event(struct input_handle *handle, unsigned int type,
+ unsigned int code, int value)
+{
+ struct kgsl_device *device = handle->handler->private;
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+
+ /*
+ * Only queue the work under certain circumstances: we have to be in
+ * slumber, the event has to be EV_EBS and we had to have processed an
+ * IB since the last time we called wake on touch.
+ */
+ if ((type == EV_ABS) &&
+ !(device->flags & KGSL_FLAG_WAKE_ON_TOUCH) &&
+ (device->state == KGSL_STATE_SLUMBER))
+ schedule_work(&adreno_dev->input_work);
+}
+
+static int adreno_input_connect(struct input_handler *handler,
+ struct input_dev *dev, const struct input_device_id *id)
+{
+ struct input_handle *handle;
+ int ret;
+
+ handle = kzalloc(sizeof(*handle), GFP_KERNEL);
+ if (handle == NULL)
+ return -ENOMEM;
+
+ handle->dev = dev;
+ handle->handler = handler;
+ handle->name = handler->name;
+
+ ret = input_register_handle(handle);
+ if (ret) {
+ kfree(handle);
+ return ret;
+ }
+
+ ret = input_open_device(handle);
+ if (ret) {
+ input_unregister_handle(handle);
+ kfree(handle);
+ }
+
+ return ret;
+}
+
+static void adreno_input_disconnect(struct input_handle *handle)
+{
+ input_close_device(handle);
+ input_unregister_handle(handle);
+ kfree(handle);
+}
+
+/*
+ * We are only interested in EV_ABS events so only register handlers for those
+ * input devices that have EV_ABS events
+ */
+static const struct input_device_id adreno_input_ids[] = {
+ {
+ .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
+ .evbit = { BIT_MASK(EV_ABS) },
+ },
+ { },
+};
+
+static struct input_handler adreno_input_handler = {
+ .event = adreno_input_event,
+ .connect = adreno_input_connect,
+ .disconnect = adreno_input_disconnect,
+ .name = "kgsl",
+ .id_table = adreno_input_ids,
+};
+
/**
* adreno_perfcounter_init: Reserve kernel performance counters
* @device: device to configure
@@ -497,6 +626,18 @@
return 0;
}
+static inline void refcount_group(struct adreno_perfcount_group *group,
+ unsigned int reg, unsigned int flags, unsigned int *lo)
+{
+ if (flags & PERFCOUNTER_FLAG_KERNEL)
+ group->regs[reg].kernelcount++;
+ else
+ group->regs[reg].usercount++;
+
+ if (lo)
+ *lo = group->regs[reg].offset;
+}
+
/**
* adreno_perfcounter_get: Try to put a countable in an available counter
* @adreno_dev: Adreno device to configure
@@ -516,7 +657,7 @@
{
struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;
struct adreno_perfcount_group *group;
- unsigned int i, empty = -1;
+ unsigned int empty = -1;
int ret = 0;
/* always clear return variables */
@@ -531,26 +672,41 @@
group = &(counters->groups[groupid]);
- /*
- * Check if the countable is already associated with a counter.
- * Refcount and return the offset, otherwise, try and find an empty
- * counter and assign the countable to it.
- */
- for (i = 0; i < group->reg_count; i++) {
- if (group->regs[i].countable == countable) {
- /* Countable already associated with counter */
- if (flags & PERFCOUNTER_FLAG_KERNEL)
- group->regs[i].kernelcount++;
- else
- group->regs[i].usercount++;
+ if (group->flags & ADRENO_PERFCOUNTER_GROUP_FIXED) {
+ /*
+ * In fixed groups the countable equals the fixed register the
+ * user wants. First make sure it is in range
+ */
- if (offset)
- *offset = group->regs[i].offset;
- return 0;
- } else if (group->regs[i].countable ==
+ if (countable >= group->reg_count)
+ return -EINVAL;
+
+ /* If it is already reserved, just increase the refcounts */
+ if ((group->regs[countable].kernelcount != 0) ||
+ (group->regs[countable].usercount != 0)) {
+ refcount_group(group, countable, flags, offset);
+ return 0;
+ }
+
+ empty = countable;
+ } else {
+ unsigned int i;
+
+ /*
+ * Check if the countable is already associated with a counter.
+ * Refcount and return the offset, otherwise, try and find an
+ * empty counter and assign the countable to it.
+ */
+
+ for (i = 0; i < group->reg_count; i++) {
+ if (group->regs[i].countable == countable) {
+ refcount_group(group, i, flags, offset);
+ return 0;
+ } else if (group->regs[i].countable ==
KGSL_PERFCOUNTER_NOT_USED) {
- /* keep track of unused counter */
- empty = i;
+ /* keep track of unused counter */
+ empty = i;
+ }
}
}
@@ -637,6 +793,33 @@
return -EINVAL;
}
+/**
+ * adreno_perfcounter_restore() - Restore performance counters
+ * @adreno_dev: adreno device to configure
+ *
+ * Load the physical performance counters with 64 bit value which are
+ * saved on GPU power collapse.
+ */
+static inline void adreno_perfcounter_restore(struct adreno_device *adreno_dev)
+{
+ if (adreno_dev->gpudev->perfcounter_restore)
+ adreno_dev->gpudev->perfcounter_restore(adreno_dev);
+}
+
+/**
+ * adreno_perfcounter_save() - Save performance counters
+ * @adreno_dev: adreno device to configure
+ *
+ * Save the performance counter values before GPU power collapse.
+ * The saved values are restored on restart.
+ * This ensures physical counters are coherent across power-collapse.
+ */
+static inline void adreno_perfcounter_save(struct adreno_device *adreno_dev)
+{
+ if (adreno_dev->gpudev->perfcounter_save)
+ adreno_dev->gpudev->perfcounter_save(adreno_dev);
+}
+
static irqreturn_t adreno_irq_handler(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
@@ -652,8 +835,6 @@
kgsl_mmu_unmap(pagetable, &rb->buffer_desc);
- kgsl_mmu_unmap(pagetable, &rb->memptrs_desc);
-
kgsl_mmu_unmap(pagetable, &device->memstore);
kgsl_mmu_unmap(pagetable, &adreno_dev->pwron_fixup);
@@ -674,14 +855,11 @@
/*
* ALERT: Order of these mapping is important to
- * Keep the most used entries like memptrs, memstore
+ * Keep the most used entries like memstore
* and mmu setstate memory by TLB prefetcher.
*/
if (!result)
- result = kgsl_mmu_map_global(pagetable, &rb->memptrs_desc);
-
- if (!result)
result = kgsl_mmu_map_global(pagetable, &device->memstore);
if (!result)
@@ -976,11 +1154,10 @@
num_iommu_units = kgsl_mmu_get_num_iommu_units(&device->mmu);
context = kgsl_context_get(device, context_id);
- if (context == NULL) {
- kgsl_mmu_device_setstate(&device->mmu, KGSL_CONTEXT_INVALID);
- return -EINVAL;
+ if (!context) {
+ kgsl_mmu_device_setstate(&device->mmu, flags);
+ return 0;
}
-
adreno_ctx = ADRENO_CONTEXT(context);
result = kgsl_mmu_enable_clk(&device->mmu, KGSL_IOMMU_CONTEXT_USER);
@@ -1385,15 +1562,6 @@
&pdata->init_level))
pdata->init_level = 1;
- /*
- * qcom,step-pwrlevel isn't required so don't spam the kernel log
- * if it isn't found
- */
-
- if (of_property_read_u32(parent, "qcom,step-pwrlevel",
- &pdata->step_mul))
- pdata->step_mul = 1;
-
if (pdata->init_level < 0 || pdata->init_level > pdata->num_levels) {
KGSL_CORE_ERR("Initial power level out of range\n");
pdata->init_level = 1;
@@ -1527,6 +1695,9 @@
pdata->strtstp_sleepwake = of_property_read_bool(pdev->dev.of_node,
"qcom,strtstp-sleepwake");
+ pdata->bus_control = of_property_read_bool(pdev->dev.of_node,
+ "qcom,bus-control");
+
if (adreno_of_read_property(pdev->dev.of_node, "qcom,clk-map",
&pdata->clk_map))
goto err;
@@ -1658,11 +1829,21 @@
kgsl_pwrscale_init(&pdev->dev, CONFIG_MSM_ADRENO_DEFAULT_GOVERNOR);
+
device->flags &= ~KGSL_FLAGS_SOFT_RESET;
pdata = kgsl_device_get_drvdata(device);
adreno_coresight_init(pdev);
+ adreno_input_handler.private = device;
+
+ /*
+ * It isn't fatal if we cannot register the input handler. Sad,
+ * perhaps, but not fatal
+ */
+ if (input_register_handler(&adreno_input_handler))
+ KGSL_DRV_ERR(device, "Unable to register the input handler\n");
+
return 0;
error_close_device:
@@ -1683,6 +1864,8 @@
device = (struct kgsl_device *)pdev->id_entry->driver_data;
adreno_dev = ADRENO_DEVICE(device);
+ input_unregister_handler(&adreno_input_handler);
+
adreno_coresight_remove(pdev);
adreno_profile_close(device);
@@ -1704,6 +1887,9 @@
int i;
int ret;
+ /* Make a high priority workqueue for starting the GPU */
+ adreno_wq = alloc_workqueue("adreno", WQ_HIGHPRI | WQ_UNBOUND, 1);
+
kgsl_pwrctrl_set_state(device, KGSL_STATE_INIT);
/*
* initialization only needs to be done once initially until
@@ -1780,10 +1966,17 @@
return ret;
}
-static int adreno_start(struct kgsl_device *device)
+/**
+ * _adreno_start - Power up the GPU and prepare to accept commands
+ * @adreno_dev: Pointer to an adreno_device structure
+ *
+ * The core function that powers up and initalizes the GPU. This function is
+ * called at init and after coming out of SLUMBER
+ */
+static int _adreno_start(struct adreno_device *adreno_dev)
{
+ struct kgsl_device *device = &adreno_dev->dev;
int status = -EINVAL;
- struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
unsigned int state = device->state;
unsigned int regulator_left_on = 0;
@@ -1836,6 +2029,9 @@
adreno_dev->gpudev->soft_reset(adreno_dev);
}
+ /* Restore performance counter registers with saved values */
+ adreno_perfcounter_restore(adreno_dev);
+
/* Start the GPU */
adreno_dev->gpudev->start(adreno_dev);
@@ -1873,6 +2069,58 @@
return status;
}
+static int _status;
+
+/**
+ * _adreno_start_work() - Work handler for the low latency adreno_start
+ * @work: Pointer to the work_struct for
+ *
+ * The work callbak for the low lantecy GPU start - this executes the core
+ * _adreno_start function in the workqueue.
+ */
+static void adreno_start_work(struct work_struct *work)
+{
+ struct adreno_device *adreno_dev = container_of(work,
+ struct adreno_device, start_work);
+ struct kgsl_device *device = &adreno_dev->dev;
+
+ /* Nice ourselves to be higher priority but not too high priority */
+ set_user_nice(current, _wake_nice);
+
+ mutex_lock(&device->mutex);
+ _status = _adreno_start(adreno_dev);
+ mutex_unlock(&device->mutex);
+}
+
+/**
+ * adreno_start() - Power up and initialize the GPU
+ * @device: Pointer to the KGSL device to power up
+ * @priority: Boolean flag to specify of the start should be scheduled in a low
+ * latency work queue
+ *
+ * Power up the GPU and initialize it. If priority is specified then queue the
+ * start function in a high priority queue for lower latency.
+ */
+static int adreno_start(struct kgsl_device *device, int priority)
+{
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+
+ /* No priority (normal latency) call the core start function directly */
+ if (!priority)
+ return _adreno_start(adreno_dev);
+
+ /*
+ * If priority is specified (low latency) then queue the work in a
+ * higher priority work queue and wait for it to finish
+ */
+ queue_work(adreno_wq, &adreno_dev->start_work);
+ mutex_unlock(&device->mutex);
+ flush_work(&adreno_dev->start_work);
+ mutex_lock(&device->mutex);
+
+ return _status;
+}
+
static int adreno_stop(struct kgsl_device *device)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
@@ -1893,6 +2141,9 @@
adreno_ocmem_gmem_free(adreno_dev);
+ /* Save physical performance counter values before GPU power down*/
+ adreno_perfcounter_save(adreno_dev);
+
/* Power down the device */
kgsl_pwrctrl_disable(device);
@@ -1927,7 +2178,7 @@
/* Keep trying to start the device until it works */
for (i = 0; i < NUM_TIMES_RESET_RETRY; i++) {
- ret = adreno_start(device);
+ ret = adreno_start(device, 0);
if (!ret)
break;
@@ -2109,12 +2360,29 @@
const char *buf, size_t count)
{
struct adreno_device *adreno_dev = _get_adreno_dev(dev);
- int ret;
+ int ret, tmp;
+
if (adreno_dev == NULL)
return 0;
mutex_lock(&adreno_dev->dev.mutex);
+
+ tmp = adreno_dev->fast_hang_detect;
+
ret = _ft_sysfs_store(buf, count, &adreno_dev->fast_hang_detect);
+
+ if (tmp != adreno_dev->fast_hang_detect) {
+ if (adreno_dev->fast_hang_detect) {
+ if (adreno_dev->gpudev->fault_detect_start)
+ adreno_dev->gpudev->fault_detect_start(
+ adreno_dev);
+ } else {
+ if (adreno_dev->gpudev->fault_detect_stop)
+ adreno_dev->gpudev->fault_detect_stop(
+ adreno_dev);
+ }
+ }
+
mutex_unlock(&adreno_dev->dev.mutex);
return ret;
@@ -2185,6 +2453,36 @@
(adreno_dev->long_ib_detect ? 1 : 0));
}
+/**
+ * _wake_timeout_store() - Store the amount of time to extend idle check after
+ * wake on touch
+ * @dev: device ptr
+ * @attr: Device attribute
+ * @buf: value to write
+ * @count: size of the value to write
+ *
+ */
+static ssize_t _wake_timeout_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ return _ft_sysfs_store(buf, count, &_wake_timeout);
+}
+
+/**
+ * _wake_timeout_show() - Show the amount of time idle check gets extended
+ * after wake on touch
+ * detect policy
+ * @dev: device ptr
+ * @attr: Device attribute
+ * @buf: value read
+ */
+static ssize_t _wake_timeout_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return snprintf(buf, PAGE_SIZE, "%d\n", _wake_timeout);
+}
#define FT_DEVICE_ATTR(name) \
DEVICE_ATTR(name, 0644, _ ## name ## _show, _ ## name ## _store);
@@ -2194,12 +2492,16 @@
FT_DEVICE_ATTR(ft_fast_hang_detect);
FT_DEVICE_ATTR(ft_long_ib_detect);
+static DEVICE_INT_ATTR(wake_nice, 0644, _wake_nice);
+static FT_DEVICE_ATTR(wake_timeout);
const struct device_attribute *ft_attr_list[] = {
&dev_attr_ft_policy,
&dev_attr_ft_pagefault_policy,
&dev_attr_ft_fast_hang_detect,
&dev_attr_ft_long_ib_detect,
+ &dev_attr_wake_nice.attr,
+ &dev_attr_wake_timeout,
NULL,
};
@@ -2335,11 +2637,19 @@
if (enable) {
device->pwrctrl.ctrl_flags = 0;
adreno_dev->fast_hang_detect = 1;
+
+ if (adreno_dev->gpudev->fault_detect_start)
+ adreno_dev->gpudev->fault_detect_start(
+ adreno_dev);
+
kgsl_pwrscale_enable(device);
} else {
- kgsl_pwrctrl_wake(device);
+ kgsl_pwrctrl_wake(device, 0);
device->pwrctrl.ctrl_flags = KGSL_PWR_ON;
adreno_dev->fast_hang_detect = 0;
+ if (adreno_dev->gpudev->fault_detect_stop)
+ adreno_dev->gpudev->fault_detect_stop(
+ adreno_dev);
kgsl_pwrscale_disable(device);
}
@@ -2422,9 +2732,15 @@
/* Make sure we are totally awake */
kgsl_pwrctrl_enable(device);
+ /* save physical performance counter values before GPU soft reset */
+ adreno_perfcounter_save(adreno_dev);
+
/* Reset the GPU */
adreno_dev->gpudev->soft_reset(adreno_dev);
+ /* Restore physical performance counter values after soft reset */
+ adreno_perfcounter_restore(adreno_dev);
+
/* Reinitialize the GPU */
adreno_dev->gpudev->start(adreno_dev);
@@ -2599,9 +2915,6 @@
if (kgsl_gpuaddr_in_memdesc(&ringbuffer->buffer_desc, gpuaddr, size))
return &ringbuffer->buffer_desc;
- if (kgsl_gpuaddr_in_memdesc(&ringbuffer->memptrs_desc, gpuaddr, size))
- return &ringbuffer->memptrs_desc;
-
if (kgsl_gpuaddr_in_memdesc(&device->memstore, gpuaddr, size))
return &device->memstore;
@@ -2861,10 +3174,10 @@
}
-static inline s64 adreno_ticks_to_us(u32 ticks, u32 gpu_freq)
+static inline s64 adreno_ticks_to_us(u32 ticks, u32 freq)
{
- gpu_freq /= 1000000;
- return ticks / gpu_freq;
+ freq /= 1000000;
+ return ticks / freq;
}
static void adreno_power_stats(struct kgsl_device *device,
@@ -2872,7 +3185,7 @@
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
- unsigned int cycles = 0;
+ struct adreno_busy_data busy_data;
memset(stats, 0, sizeof(*stats));
/*
@@ -2881,10 +3194,12 @@
* any cycles since the last time this function was called.
*/
if (device->state == KGSL_STATE_ACTIVE)
- cycles = adreno_dev->gpudev->busy_cycles(adreno_dev);
+ adreno_dev->gpudev->busy_cycles(adreno_dev, &busy_data);
- stats->busy_time = adreno_ticks_to_us(cycles,
+ stats->busy_time = adreno_ticks_to_us(busy_data.gpu_busy,
kgsl_pwrctrl_active_freq(pwr));
+ stats->ram_time = busy_data.vbif_ram_cycles;
+ stats->ram_wait = busy_data.vbif_starved_ram;
}
void adreno_irqctrl(struct kgsl_device *device, int state)
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 5498766..1b538a7 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -149,6 +149,12 @@
struct adreno_gpudev;
+struct adreno_busy_data {
+ unsigned int gpu_busy;
+ unsigned int vbif_ram_cycles;
+ unsigned int vbif_starved_ram;
+};
+
struct adreno_device {
struct kgsl_device dev; /* Must be first field in this struct */
unsigned long priv;
@@ -189,11 +195,15 @@
unsigned int gpulist_index;
struct ocmem_buf *ocmem_hdl;
unsigned int ocmem_base;
- unsigned int gpu_cycles;
struct adreno_profile profile;
struct kgsl_memdesc pwron_fixup;
unsigned int pwron_fixup_dwords;
struct adreno_dispatcher dispatcher;
+ struct adreno_busy_data busy_data;
+
+ struct work_struct start_work;
+ struct work_struct input_work;
+ unsigned int ram_cycles_lo;
};
/**
@@ -221,6 +231,7 @@
* @offset: register hardware offset
* @load_bit: The bit number in LOAD register which corresponds to this counter
* @select: The countable register offset
+ * @value: The 64 bit countable register value
*/
struct adreno_perfcount_register {
unsigned int countable;
@@ -229,6 +240,7 @@
unsigned int offset;
int load_bit;
unsigned int select;
+ uint64_t value;
};
/**
@@ -241,8 +253,19 @@
struct adreno_perfcount_register *regs;
unsigned int reg_count;
const char *name;
+ unsigned long flags;
};
+/*
+ * ADRENO_PERFCOUNTER_GROUP_FIXED indicates that a perfcounter group is fixed -
+ * instead of having configurable countables like the other groups, registers in
+ * fixed groups have a hardwired countable. So when the user requests a
+ * countable in one of these groups, that countable should be used as the
+ * register offset to return
+ */
+
+#define ADRENO_PERFCOUNTER_GROUP_FIXED BIT(0)
+
/**
* adreno_perfcounts: all available perfcounter groups
* @groups: available groups for this device
@@ -254,7 +277,11 @@
};
#define ADRENO_PERFCOUNTER_GROUP(core, name) { core##_perfcounters_##name, \
- ARRAY_SIZE(core##_perfcounters_##name), __stringify(name) }
+ ARRAY_SIZE(core##_perfcounters_##name), __stringify(name), 0 }
+
+#define ADRENO_PERFCOUNTER_GROUP_FLAGS(core, name, flags) \
+ { core##_perfcounters_##name, \
+ ARRAY_SIZE(core##_perfcounters_##name), __stringify(name), flags }
/**
* adreno_regs: List of registers that are used in kgsl driver for all
@@ -351,12 +378,18 @@
int (*rb_init)(struct adreno_device *, struct adreno_ringbuffer *);
int (*perfcounter_init)(struct adreno_device *);
void (*perfcounter_close)(struct adreno_device *);
+ void (*perfcounter_save)(struct adreno_device *);
+ void (*perfcounter_restore)(struct adreno_device *);
+ void (*fault_detect_start)(struct adreno_device *);
+ void (*fault_detect_stop)(struct adreno_device *);
void (*start)(struct adreno_device *);
- unsigned int (*busy_cycles)(struct adreno_device *);
int (*perfcounter_enable)(struct adreno_device *, unsigned int group,
unsigned int counter, unsigned int countable);
+ void (*busy_cycles)(struct adreno_device *, struct adreno_busy_data *);
uint64_t (*perfcounter_read)(struct adreno_device *adreno_dev,
unsigned int group, unsigned int counter);
+ void (*perfcounter_write)(struct adreno_device *adreno_dev,
+ unsigned int group, unsigned int counter);
int (*coresight_enable) (struct kgsl_device *device);
void (*coresight_disable) (struct kgsl_device *device);
void (*coresight_config_debug_reg) (struct kgsl_device *device,
@@ -365,7 +398,7 @@
void (*postmortem_dump)(struct adreno_device *adreno_dev);
};
-#define FT_DETECT_REGS_COUNT 12
+#define FT_DETECT_REGS_COUNT 14
struct log_field {
bool show;
@@ -846,4 +879,19 @@
return 0;
}
+/**
+ * adreno_get_rptr() - Get the current ringbuffer read pointer
+ * @rb: Pointer the ringbuffer to query
+ *
+ * Get the current read pointer from the GPU register.
+ */
+static inline unsigned int
+adreno_get_rptr(struct adreno_ringbuffer *rb)
+{
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(rb->device);
+ unsigned int result;
+ adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_RPTR, &result);
+ return result;
+}
+
#endif /*__ADRENO_H */
diff --git a/drivers/gpu/msm/adreno_a2xx.c b/drivers/gpu/msm/adreno_a2xx.c
index 24a0933..622350d3 100644
--- a/drivers/gpu/msm/adreno_a2xx.c
+++ b/drivers/gpu/msm/adreno_a2xx.c
@@ -1971,17 +1971,19 @@
return 0;
}
-static unsigned int a2xx_busy_cycles(struct adreno_device *adreno_dev)
+static void a2xx_busy_cycles(struct adreno_device *adreno_dev,
+ struct adreno_busy_data *data)
{
struct kgsl_device *device = &adreno_dev->dev;
- unsigned int reg, val;
+ unsigned int reg;
+ memset(data, 0, sizeof(*data));
/* Freeze the counter */
kgsl_regwrite(device, REG_CP_PERFMON_CNTL,
REG_PERF_MODE_CNT | REG_PERF_STATE_FREEZE);
/* Get the value */
- kgsl_regread(device, REG_RBBM_PERFCOUNTER1_LO, &val);
+ kgsl_regread(device, REG_RBBM_PERFCOUNTER1_LO, &data->gpu_busy);
/* Reset the counter */
kgsl_regwrite(device, REG_CP_PERFMON_CNTL,
@@ -1994,7 +1996,6 @@
kgsl_regwrite(device, REG_CP_PERFMON_CNTL,
REG_PERF_MODE_CNT | REG_PERF_STATE_ENABLE);
- return val;
}
static void a2xx_gmeminit(struct adreno_device *adreno_dev)
diff --git a/drivers/gpu/msm/adreno_a3xx.c b/drivers/gpu/msm/adreno_a3xx.c
index df1794f..e5f5ad7 100644
--- a/drivers/gpu/msm/adreno_a3xx.c
+++ b/drivers/gpu/msm/adreno_a3xx.c
@@ -95,6 +95,11 @@
#define _SET(_shift, _val) ((_val) << (_shift))
+/* EN/CLR mask for the VBIF counters we care about */
+#define VBIF_PERF_MASK (VBIF_PERF_CNT_0 | VBIF_PERF_PWR_CNT_0)
+#define RBBM_PERF_ENABLE_MASK (RBBM_RBBM_CTL_ENABLE_PWR_CTR1)
+#define RBBM_PERF_RESET_MASK (RBBM_RBBM_CTL_RESET_PWR_CTR1)
+
/*
****************************************************************************
*
@@ -3376,6 +3381,136 @@
return (((uint64_t) hi) << 32) | lo;
}
+/*
+ * values cannot be loaded into physical performance
+ * counters belonging to these groups.
+ */
+static inline int loadable_perfcounter_group(unsigned int groupid)
+{
+ return ((groupid == KGSL_PERFCOUNTER_GROUP_VBIF_PWR) ||
+ (groupid == KGSL_PERFCOUNTER_GROUP_VBIF) ||
+ (groupid == KGSL_PERFCOUNTER_GROUP_PWR)) ? 0 : 1;
+}
+
+/*
+ * Return true if the countable is used and not broken
+ */
+static inline int active_countable(unsigned int countable)
+{
+ return ((countable != KGSL_PERFCOUNTER_NOT_USED) &&
+ (countable != KGSL_PERFCOUNTER_BROKEN));
+}
+
+/**
+ * a3xx_perfcounter_save() - Save the physical performance counter values
+ * @adreno_dev - Adreno device whose registers need to be saved
+ *
+ * Read all the physical performance counter's values and save them
+ * before GPU power collapse.
+ */
+static void a3xx_perfcounter_save(struct adreno_device *adreno_dev)
+{
+ struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;
+ struct adreno_perfcount_group *group;
+ unsigned int regid, groupid;
+
+ for (groupid = 0; groupid < counters->group_count; groupid++) {
+ if (!loadable_perfcounter_group(groupid))
+ continue;
+
+ group = &(counters->groups[groupid]);
+
+ /* group/counter iterator */
+ for (regid = 0; regid < group->reg_count; regid++) {
+ if (!active_countable(group->regs[regid].countable))
+ continue;
+
+ group->regs[regid].value =
+ adreno_dev->gpudev->perfcounter_read(
+ adreno_dev, groupid, regid);
+ }
+ }
+}
+
+/**
+ * a3xx_perfcounter_write() - Write the physical performance counter values.
+ * @adreno_dev - Adreno device whose registers are to be written to.
+ * @group - group to which the physical counter belongs to.
+ * @counter - register id of the physical counter to which the value is
+ * written to.
+ *
+ * This function loads the 64 bit saved value into the particular physical
+ * counter by enabling the corresponding bit in A3XX_RBBM_PERFCTR_LOAD_CMD*
+ * register.
+ */
+static void a3xx_perfcounter_write(struct adreno_device *adreno_dev,
+ unsigned int group, unsigned int counter)
+{
+ struct kgsl_device *device = &(adreno_dev->dev);
+ struct adreno_perfcount_register *reg;
+ unsigned int val;
+
+ reg = &(adreno_dev->gpudev->perfcounters->groups[group].regs[counter]);
+
+ /* Clear the load cmd registers */
+ kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD0, 0);
+ kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD1, 0);
+
+ /* Write the saved value to PERFCTR_LOAD_VALUE* registers. */
+ kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_VALUE_LO,
+ (uint32_t)reg->value);
+ kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_VALUE_HI,
+ (uint32_t)(reg->value >> 32));
+
+ /*
+ * Set the load bit in PERFCTR_LOAD_CMD for the physical counter
+ * we want to restore. The value in PERFCTR_LOAD_VALUE* is loaded
+ * into the corresponding physical counter.
+ */
+ if (reg->load_bit < 32) {
+ val = 1 << reg->load_bit;
+ kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD0, val);
+ } else {
+ val = 1 << (reg->load_bit - 32);
+ kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD1, val);
+ }
+}
+
+/**
+ * a3xx_perfcounter_restore() - Restore the physical performance counter values.
+ * @adreno_dev - Adreno device whose registers are to be restored.
+ *
+ * This function together with a3xx_perfcounter_save make sure that performance
+ * counters are coherent across GPU power collapse.
+ */
+static void a3xx_perfcounter_restore(struct adreno_device *adreno_dev)
+{
+ struct kgsl_device *device = &adreno_dev->dev;
+ struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;
+ struct adreno_perfcount_group *group;
+ unsigned int regid, groupid;
+
+ for (groupid = 0; groupid < counters->group_count; groupid++) {
+ if (!loadable_perfcounter_group(groupid))
+ continue;
+
+ group = &(counters->groups[groupid]);
+
+ /* group/counter iterator */
+ for (regid = 0; regid < group->reg_count; regid++) {
+ if (!active_countable(group->regs[regid].countable))
+ continue;
+
+ a3xx_perfcounter_write(adreno_dev, groupid, regid);
+ }
+ }
+
+ /* Clear the load cmd registers */
+ kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD0, 0);
+ kgsl_regwrite(device, A3XX_RBBM_PERFCTR_LOAD_CMD1, 0);
+
+}
+
#define A3XX_IRQ_CALLBACK(_c) { .func = _c }
#define A3XX_INT_MASK \
@@ -3474,32 +3609,63 @@
return (status & A3XX_INT_MASK) ? 1 : 0;
}
-static unsigned int a3xx_busy_cycles(struct adreno_device *adreno_dev)
+static unsigned int counter_delta(struct adreno_device *adreno_dev,
+ unsigned int reg, unsigned int *counter)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int val;
unsigned int ret = 0;
/* Read the value */
- kgsl_regread(device, A3XX_RBBM_PERFCTR_PWR_1_LO, &val);
+ if (reg == ADRENO_REG_RBBM_PERFCTR_PWR_1_LO)
+ adreno_readreg(adreno_dev, reg, &val);
+ else
+ kgsl_regread(device, reg, &val);
/* Return 0 for the first read */
- if (adreno_dev->gpu_cycles != 0) {
- if (val < adreno_dev->gpu_cycles)
- ret = (0xFFFFFFFF - adreno_dev->gpu_cycles) + val;
+ if (*counter != 0) {
+ if (val < *counter)
+ ret = (0xFFFFFFFF - *counter) + val;
else
- ret = val - adreno_dev->gpu_cycles;
+ ret = val - *counter;
}
- adreno_dev->gpu_cycles = val;
+ *counter = val;
return ret;
}
+/*
+ * a3xx_busy_cycles() - Returns number of gpu cycles
+ * @adreno_dev: Pointer to device ehose cycles are checked
+ *
+ * Returns number of busy cycles since the last time this function is called
+ * Function is common between a3xx and a4xx devices
+ */
+void a3xx_busy_cycles(struct adreno_device *adreno_dev,
+ struct adreno_busy_data *data)
+{
+ struct adreno_busy_data *busy = &adreno_dev->busy_data;
+ struct kgsl_device *device = &adreno_dev->dev;
+
+ memset(data, 0, sizeof(*data));
+
+ data->gpu_busy = counter_delta(adreno_dev,
+ ADRENO_REG_RBBM_PERFCTR_PWR_1_LO,
+ &busy->gpu_busy);
+ if (device->pwrctrl.bus_control) {
+ data->vbif_ram_cycles = counter_delta(adreno_dev,
+ adreno_dev->ram_cycles_lo,
+ &busy->vbif_ram_cycles);
+ data->vbif_starved_ram = counter_delta(adreno_dev,
+ A3XX_VBIF_PERF_PWR_CNT0_LO,
+ &busy->vbif_starved_ram);
+ }
+}
+
struct a3xx_vbif_data {
unsigned int reg;
unsigned int val;
};
-
/* VBIF registers start after 0x3000 so use 0x0 as end of list marker */
static struct a3xx_vbif_data a305_vbif[] = {
/* Set up 16 deep read/write request queues */
@@ -3779,9 +3945,11 @@
ADRENO_PERFCOUNTER_GROUP(a3xx, tp),
ADRENO_PERFCOUNTER_GROUP(a3xx, sp),
ADRENO_PERFCOUNTER_GROUP(a3xx, rb),
- ADRENO_PERFCOUNTER_GROUP(a3xx, pwr),
+ ADRENO_PERFCOUNTER_GROUP_FLAGS(a3xx, pwr,
+ ADRENO_PERFCOUNTER_GROUP_FIXED),
ADRENO_PERFCOUNTER_GROUP(a3xx, vbif),
- ADRENO_PERFCOUNTER_GROUP(a3xx, vbif_pwr),
+ ADRENO_PERFCOUNTER_GROUP_FLAGS(a3xx, vbif_pwr,
+ ADRENO_PERFCOUNTER_GROUP_FIXED),
};
static struct adreno_perfcounters a3xx_perfcounters = {
@@ -3789,27 +3957,123 @@
ARRAY_SIZE(a3xx_perfcounter_groups),
};
-/*
- * a3xx_perfcounter_close() - Return counters that were initialized in
+static inline int _get_counter(struct adreno_device *adreno_dev,
+ int group, int countable, unsigned int *lo,
+ unsigned int *hi)
+{
+ int ret = 0;
+
+ if (*lo == 0) {
+ *hi = 0;
+
+ ret = adreno_perfcounter_get(adreno_dev, group, countable,
+ lo, PERFCOUNTER_FLAG_KERNEL);
+
+ if (ret == 0)
+ *hi = *lo + 1;
+ else {
+ struct kgsl_device *device = &adreno_dev->dev;
+
+ KGSL_DRV_ERR(device,
+ "Unable to allocate fault detect performance counter %d/%d\n",
+ group, countable);
+ KGSL_DRV_ERR(device,
+ "GPU fault detect will be less reliable\n");
+ }
+ }
+
+ return ret;
+}
+
+static inline void _put_counter(struct adreno_device *adreno_dev,
+ int group, int countable, unsigned int *lo,
+ unsigned int *hi)
+{
+ if (*lo != 0) {
+ adreno_perfcounter_put(adreno_dev, group, countable,
+ PERFCOUNTER_FLAG_KERNEL);
+ }
+
+ *lo = 0;
+ *hi = 0;
+}
+
+/**
+ * a3xx_fault_detect_start() - Allocate performance counters used for fast fault
+ * detection
+ * @adreno_dev: Pointer to an adreno_device structure
+ *
+ * Allocate the series of performance counters that should be periodically
+ * checked to verify that the GPU is still moving
+ */
+void a3xx_fault_detect_start(struct adreno_device *adreno_dev)
+{
+ _get_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
+ SP_ALU_ACTIVE_CYCLES,
+ &ft_detect_regs[6], &ft_detect_regs[7]);
+
+ _get_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
+ SP0_ICL1_MISSES,
+ &ft_detect_regs[8], &ft_detect_regs[9]);
+
+ _get_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
+ SP_FS_CFLOW_INSTRUCTIONS,
+ &ft_detect_regs[10], &ft_detect_regs[11]);
+
+ _get_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_TSE,
+ TSE_INPUT_PRIM_NUM,
+ &ft_detect_regs[12], &ft_detect_regs[13]);
+}
+/**
+ * a3xx_fault_detect_stop() - Release performance counters used for fast fault
+ * detection
+ * @adreno_dev: Pointer to an adreno_device structure
+ *
+ * Release the counters allocated in a3xx_fault_detect_start
+ */
+void a3xx_fault_detect_stop(struct adreno_device *adreno_dev)
+{
+ _put_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
+ SP_ALU_ACTIVE_CYCLES,
+ &ft_detect_regs[6], &ft_detect_regs[7]);
+
+ _put_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
+ SP0_ICL1_MISSES,
+ &ft_detect_regs[8], &ft_detect_regs[9]);
+
+ _put_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
+ SP_FS_CFLOW_INSTRUCTIONS,
+ &ft_detect_regs[10], &ft_detect_regs[11]);
+
+ _put_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_TSE,
+ TSE_INPUT_PRIM_NUM,
+ &ft_detect_regs[12], &ft_detect_regs[13]);
+}
+
+/**
+ * a3xx_perfcounter_close() - Put counters that were initialized in
* a3xx_perfcounter_init
- * @adreno_dev: The device for which counters were initialized
+ * @adreno_dev: Pointer to an adreno_device structure
*/
static void a3xx_perfcounter_close(struct adreno_device *adreno_dev)
{
- adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
- SP_FS_FULL_ALU_INSTRUCTIONS,
+ adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_PWR, 1,
PERFCOUNTER_FLAG_KERNEL);
- adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
- SP_FS_CFLOW_INSTRUCTIONS,
+
+ adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_VBIF_PWR, 0,
PERFCOUNTER_FLAG_KERNEL);
- adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
- SP0_ICL1_MISSES,
- PERFCOUNTER_FLAG_KERNEL);
- adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
- SP_ALU_ACTIVE_CYCLES,
- PERFCOUNTER_FLAG_KERNEL);
+
+ adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_VBIF,
+ VBIF_AXI_TOTAL_BEATS, PERFCOUNTER_FLAG_KERNEL);
+
+ if (adreno_dev->fast_hang_detect)
+ a3xx_fault_detect_stop(adreno_dev);
}
+/**
+ * a3xx_perfcounter_init() - Allocate performance counters for use in the kernel
+ * @adreno_dev: Pointer to an adreno_device structure
+ */
static int a3xx_perfcounter_init(struct adreno_device *adreno_dev)
{
int ret;
@@ -3817,57 +4081,26 @@
if (adreno_is_a330(adreno_dev))
a3xx_perfcounters_sp[3].countable = KGSL_PERFCOUNTER_BROKEN;
- /*
- * Set SP to count SP_ALU_ACTIVE_CYCLES, it includes
- * all ALU instruction execution regardless precision or shader ID.
- * Set SP to count SP0_ICL1_MISSES, It counts
- * USP L1 instruction miss request.
- * Set SP to count SP_FS_FULL_ALU_INSTRUCTIONS, it
- * counts USP flow control instruction execution.
- * we will use this to augment our hang detection
- */
- if (adreno_dev->fast_hang_detect) {
- ret = adreno_perfcounter_get(adreno_dev,
- KGSL_PERFCOUNTER_GROUP_SP,
- SP_ALU_ACTIVE_CYCLES, &ft_detect_regs[6],
- PERFCOUNTER_FLAG_KERNEL);
- if (ret)
- goto err;
- ft_detect_regs[7] = ft_detect_regs[6] + 1;
- ret = adreno_perfcounter_get(adreno_dev,
- KGSL_PERFCOUNTER_GROUP_SP,
- SP0_ICL1_MISSES, &ft_detect_regs[8],
- PERFCOUNTER_FLAG_KERNEL);
- if (ret)
- goto err;
- ft_detect_regs[9] = ft_detect_regs[8] + 1;
- ret = adreno_perfcounter_get(adreno_dev,
- KGSL_PERFCOUNTER_GROUP_SP,
- SP_FS_CFLOW_INSTRUCTIONS, &ft_detect_regs[10],
- PERFCOUNTER_FLAG_KERNEL);
- if (ret)
- goto err;
- ft_detect_regs[11] = ft_detect_regs[10] + 1;
- }
-
- ret = adreno_perfcounter_get(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
- SP_FS_FULL_ALU_INSTRUCTIONS, NULL, PERFCOUNTER_FLAG_KERNEL);
- if (ret)
- goto err;
+ if (adreno_dev->fast_hang_detect)
+ a3xx_fault_detect_start(adreno_dev);
/* Reserve and start countable 1 in the PWR perfcounter group */
ret = adreno_perfcounter_get(adreno_dev, KGSL_PERFCOUNTER_GROUP_PWR, 1,
NULL, PERFCOUNTER_FLAG_KERNEL);
- if (ret)
- goto err;
+
+ /* VBIF waiting for RAM */
+ ret |= adreno_perfcounter_get(adreno_dev,
+ KGSL_PERFCOUNTER_GROUP_VBIF_PWR, 0,
+ NULL, PERFCOUNTER_FLAG_KERNEL);
+ /* VBIF DDR cycles */
+ ret |= adreno_perfcounter_get(adreno_dev, KGSL_PERFCOUNTER_GROUP_VBIF,
+ VBIF_AXI_TOTAL_BEATS,
+ &adreno_dev->ram_cycles_lo,
+ PERFCOUNTER_FLAG_KERNEL);
/* Default performance counter profiling to false */
adreno_dev->profile.enabled = false;
return ret;
-
-err:
- a3xx_perfcounter_close(adreno_dev);
- return ret;
}
/**
@@ -3973,12 +4206,9 @@
/* Turn on performance counters */
kgsl_regwrite(device, A3XX_RBBM_PERFCTR_CTL, 0x01);
- /* Turn on the GPU busy counter and let it run free */
-
- adreno_dev->gpu_cycles = 0;
-
/* the CP_DEBUG register offset and value are same as A2XX */
kgsl_regwrite(device, REG_CP_DEBUG, A2XX_CP_DEBUG_DEFAULT);
+ memset(&adreno_dev->busy_data, 0, sizeof(adreno_dev->busy_data));
}
/**
@@ -4345,6 +4575,8 @@
.rb_init = a3xx_rb_init,
.perfcounter_init = a3xx_perfcounter_init,
.perfcounter_close = a3xx_perfcounter_close,
+ .perfcounter_save = a3xx_perfcounter_save,
+ .perfcounter_restore = a3xx_perfcounter_restore,
.irq_control = a3xx_irq_control,
.irq_handler = a3xx_irq_handler,
.irq_pending = a3xx_irq_pending,
@@ -4353,9 +4585,12 @@
.snapshot = a3xx_snapshot,
.perfcounter_enable = a3xx_perfcounter_enable,
.perfcounter_read = a3xx_perfcounter_read,
+ .perfcounter_write = a3xx_perfcounter_write,
.coresight_enable = a3xx_coresight_enable,
.coresight_disable = a3xx_coresight_disable,
.coresight_config_debug_reg = a3xx_coresight_config_debug_reg,
+ .fault_detect_start = a3xx_fault_detect_start,
+ .fault_detect_stop = a3xx_fault_detect_stop,
.soft_reset = a3xx_soft_reset,
.postmortem_dump = a3xx_postmortem_dump,
};
diff --git a/drivers/gpu/msm/adreno_drawctxt.c b/drivers/gpu/msm/adreno_drawctxt.c
index 8ff07ac..6007a3f 100644
--- a/drivers/gpu/msm/adreno_drawctxt.c
+++ b/drivers/gpu/msm/adreno_drawctxt.c
@@ -589,7 +589,6 @@
int adreno_context_restore(struct adreno_device *adreno_dev,
struct adreno_context *context)
{
- int ret;
struct kgsl_device *device;
unsigned int cmds[5];
@@ -597,6 +596,7 @@
return -EINVAL;
device = &adreno_dev->dev;
+
/* write the context identifier to the ringbuffer */
cmds[0] = cp_nop_packet(1);
cmds[1] = KGSL_CONTEXT_TO_MEM_IDENTIFIER;
@@ -604,14 +604,8 @@
cmds[3] = device->memstore.gpuaddr +
KGSL_MEMSTORE_OFFSET(KGSL_MEMSTORE_GLOBAL, current_context);
cmds[4] = context->base.id;
- ret = adreno_ringbuffer_issuecmds(device, context, KGSL_CMD_FLAGS_NONE,
- cmds, 5);
- if (ret)
- return ret;
-
- return kgsl_mmu_setstate(&device->mmu,
- context->base.proc_priv->pagetable,
- context->base.id);
+ return adreno_ringbuffer_issuecmds(device, context,
+ KGSL_CMD_FLAGS_NONE, cmds, 5);
}
@@ -710,9 +704,6 @@
return ret;
}
- /* Put the old instance of the active drawctxt */
- kgsl_context_put(&adreno_dev->drawctxt_active->base);
- adreno_dev->drawctxt_active = NULL;
}
/* Get a refcount to the new instance */
@@ -720,6 +711,11 @@
if (!_kgsl_context_get(&drawctxt->base))
return -EINVAL;
+ ret = kgsl_mmu_setstate(&device->mmu,
+ drawctxt->base.proc_priv->pagetable,
+ adreno_dev->drawctxt_active ?
+ adreno_dev->drawctxt_active->base.id :
+ KGSL_CONTEXT_INVALID);
/* Set the new context */
ret = drawctxt->ops->restore(adreno_dev, drawctxt);
if (ret) {
@@ -737,9 +733,11 @@
*/
ret = kgsl_mmu_setstate(&device->mmu,
device->mmu.defaultpagetable,
- KGSL_CONTEXT_INVALID);
+ adreno_dev->drawctxt_active->base.id);
}
-
+ /* Put the old instance of the active drawctxt */
+ if (adreno_dev->drawctxt_active)
+ kgsl_context_put(&adreno_dev->drawctxt_active->base);
adreno_dev->drawctxt_active = drawctxt;
return 0;
}
diff --git a/drivers/gpu/msm/adreno_profile.c b/drivers/gpu/msm/adreno_profile.c
index 8d3efd6..28fd6d6 100644
--- a/drivers/gpu/msm/adreno_profile.c
+++ b/drivers/gpu/msm/adreno_profile.c
@@ -441,6 +441,11 @@
profile, *(ptr + buf_off++));
if (assigns_list == NULL) {
*log_ptr = (unsigned int) -1;
+
+ shared_buf_inc(profile->shared_size,
+ &profile->shared_tail,
+ SIZE_SHARED_ENTRY(cnt));
+
goto err;
} else {
*log_ptr = assigns_list->groupid << 16 |
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index a43bd54..1383a20 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -368,61 +368,26 @@
*/
void _ringbuffer_setup_common(struct adreno_ringbuffer *rb)
{
- union reg_cp_rb_cntl cp_rb_cntl;
- unsigned int rb_cntl;
struct kgsl_device *device = rb->device;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
- kgsl_sharedmem_set(rb->device, &rb->memptrs_desc, 0, 0,
- sizeof(struct kgsl_rbmemptrs));
-
kgsl_sharedmem_set(rb->device, &rb->buffer_desc, 0, 0xAA,
(rb->sizedwords << 2));
- if (adreno_is_a2xx(adreno_dev)) {
- kgsl_regwrite(device, REG_CP_RB_WPTR_BASE,
- (rb->memptrs_desc.gpuaddr
- + GSL_RB_MEMPTRS_WPTRPOLL_OFFSET));
-
- /* setup WPTR delay */
- kgsl_regwrite(device, REG_CP_RB_WPTR_DELAY,
- 0 /*0x70000010 */);
- }
-
- /*setup REG_CP_RB_CNTL */
- adreno_readreg(adreno_dev, ADRENO_REG_CP_RB_CNTL, &rb_cntl);
- cp_rb_cntl.val = rb_cntl;
-
/*
* The size of the ringbuffer in the hardware is the log2
- * representation of the size in quadwords (sizedwords / 2)
+ * representation of the size in quadwords (sizedwords / 2).
+ * Also disable the host RPTR shadow register as it might be unreliable
+ * in certain circumstances.
*/
- cp_rb_cntl.f.rb_bufsz = ilog2(rb->sizedwords >> 1);
- /*
- * Specify the quadwords to read before updating mem RPTR.
- * Like above, pass the log2 representation of the blocksize
- * in quadwords.
- */
- cp_rb_cntl.f.rb_blksz = ilog2(KGSL_RB_BLKSIZE >> 3);
-
- if (adreno_is_a2xx(adreno_dev)) {
- /* WPTR polling */
- cp_rb_cntl.f.rb_poll_en = GSL_RB_CNTL_POLL_EN;
- }
-
- /* mem RPTR writebacks */
- cp_rb_cntl.f.rb_no_update = GSL_RB_CNTL_NO_UPDATE;
-
- adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL, cp_rb_cntl.val);
+ adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL,
+ (ilog2(rb->sizedwords >> 1) & 0x3F) |
+ (1 << 27));
adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_BASE,
rb->buffer_desc.gpuaddr);
- adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_RPTR_ADDR,
- rb->memptrs_desc.gpuaddr +
- GSL_RB_MEMPTRS_RPTR_OFFSET);
-
if (adreno_is_a2xx(adreno_dev)) {
/* explicitly clear all cp interrupts */
kgsl_regwrite(device, REG_CP_INT_ACK, 0xFFFFFFFF);
@@ -621,20 +586,6 @@
return status;
}
- /* allocate memory for polling and timestamps */
- /* This really can be at 4 byte alignment boundry but for using MMU
- * we need to make it at page boundary */
- status = kgsl_allocate_contiguous(&rb->memptrs_desc,
- sizeof(struct kgsl_rbmemptrs));
-
- if (status != 0) {
- adreno_ringbuffer_close(rb);
- return status;
- }
-
- /* overlay structure on memptrs memory */
- rb->memptrs = (struct kgsl_rbmemptrs *) rb->memptrs_desc.hostptr;
-
rb->global_ts = 0;
return 0;
@@ -645,7 +596,6 @@
struct adreno_device *adreno_dev = ADRENO_DEVICE(rb->device);
kgsl_sharedmem_free(&rb->buffer_desc);
- kgsl_sharedmem_free(&rb->memptrs_desc);
kfree(adreno_dev->pfp_fw);
kfree(adreno_dev->pm4_fw);
@@ -1156,6 +1106,13 @@
/* wait for the suspend gate */
wait_for_completion(&device->cmdbatch_gate);
+ /*
+ * Clear the wake on touch bit to indicate an IB has been submitted
+ * since the last time we set it
+ */
+
+ device->flags &= ~KGSL_FLAG_WAKE_ON_TOUCH;
+
/* Queue the command in the ringbuffer */
ret = adreno_dispatcher_queue_cmd(adreno_dev, drawctxt, cmdbatch,
timestamp);
diff --git a/drivers/gpu/msm/adreno_ringbuffer.h b/drivers/gpu/msm/adreno_ringbuffer.h
index eee4127..697e113 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.h
+++ b/drivers/gpu/msm/adreno_ringbuffer.h
@@ -19,7 +19,6 @@
*/
#define KGSL_RB_SIZE (32 * 1024)
-#define KGSL_RB_BLKSIZE 16
/* CP timestamp register */
#define REG_CP_TIMESTAMP REG_SCRATCH_REG0
@@ -28,27 +27,12 @@
struct kgsl_device;
struct kgsl_device_private;
-#define GSL_RB_MEMPTRS_SCRATCH_COUNT 8
-struct kgsl_rbmemptrs {
- int rptr;
- int wptr_poll;
-};
-
-#define GSL_RB_MEMPTRS_RPTR_OFFSET \
- (offsetof(struct kgsl_rbmemptrs, rptr))
-
-#define GSL_RB_MEMPTRS_WPTRPOLL_OFFSET \
- (offsetof(struct kgsl_rbmemptrs, wptr_poll))
-
struct adreno_ringbuffer {
struct kgsl_device *device;
uint32_t flags;
struct kgsl_memdesc buffer_desc;
- struct kgsl_memdesc memptrs_desc;
- struct kgsl_rbmemptrs *memptrs;
-
/*ringbuffer size */
unsigned int sizedwords;
@@ -70,25 +54,6 @@
/* enable timestamp (...scratch0) memory shadowing */
#define GSL_RB_MEMPTRS_SCRATCH_MASK 0x1
-/* mem rptr */
-#define GSL_RB_CNTL_NO_UPDATE 0x0 /* enable */
-
-/**
- * adreno_get_rptr - Get the current ringbuffer read pointer
- * @rb - the ringbuffer
- *
- * Get the current read pointer, which is written by the GPU.
- */
-static inline unsigned int
-adreno_get_rptr(struct adreno_ringbuffer *rb)
-{
- unsigned int result = rb->memptrs->rptr;
- rmb();
- return result;
-}
-
-#define GSL_RB_CNTL_POLL_EN 0x0 /* disable */
-
/*
* protected mode error checking below register address 0x800
* note: if CP_INTERRUPT packet is used then checking needs
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index 6c1ed92..9aefda6 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -60,6 +60,9 @@
struct sg_table *table;
};
+static void kgsl_put_process_private(struct kgsl_device *device,
+ struct kgsl_process_private *private);
+
static void kgsl_mem_entry_detach_process(struct kgsl_mem_entry *entry);
static void
@@ -341,14 +344,19 @@
*/
static int
kgsl_mem_entry_attach_process(struct kgsl_mem_entry *entry,
- struct kgsl_process_private *process)
+ struct kgsl_device_private *dev_priv)
{
int ret;
+ struct kgsl_process_private *process = dev_priv->process_priv;
+
+ ret = kref_get_unless_zero(&process->refcount);
+ if (!ret)
+ return -EBADF;
while (1) {
if (idr_pre_get(&process->mem_idr, GFP_KERNEL) == 0) {
ret = -ENOMEM;
- goto err;
+ goto err_put_proc_priv;
}
spin_lock(&process->mem_lock);
@@ -359,9 +367,10 @@
if (ret == 0)
break;
else if (ret != -EAGAIN)
- goto err;
+ goto err_put_proc_priv;
}
entry->priv = process;
+ entry->dev_priv = dev_priv;
spin_lock(&process->mem_lock);
ret = kgsl_mem_entry_track_gpuaddr(process, entry);
@@ -369,14 +378,17 @@
idr_remove(&process->mem_idr, entry->id);
spin_unlock(&process->mem_lock);
if (ret)
- goto err;
+ goto err_put_proc_priv;
/* map the memory after unlocking if gpuaddr has been assigned */
if (entry->memdesc.gpuaddr) {
ret = kgsl_mmu_map(process->pagetable, &entry->memdesc);
if (ret)
kgsl_mem_entry_detach_process(entry);
}
-err:
+ return ret;
+
+err_put_proc_priv:
+ kgsl_put_process_private(dev_priv->device, process);
return ret;
}
@@ -399,6 +411,7 @@
entry->priv->stats[entry->memtype].cur -= entry->memdesc.size;
spin_unlock(&entry->priv->mem_lock);
+ kgsl_put_process_private(entry->dev_priv->device, entry->priv);
entry->priv = NULL;
}
@@ -764,11 +777,6 @@
*/
static void kgsl_destroy_process_private(struct kref *kref)
{
-
- struct kgsl_mem_entry *entry = NULL;
- int next = 0;
-
-
struct kgsl_process_private *private = container_of(kref,
struct kgsl_process_private, refcount);
@@ -792,20 +800,6 @@
if (private->debug_root)
debugfs_remove_recursive(private->debug_root);
- while (1) {
- spin_lock(&private->mem_lock);
- entry = idr_get_next(&private->mem_idr, &next);
- spin_unlock(&private->mem_lock);
- if (entry == NULL)
- break;
- kgsl_mem_entry_put(entry);
- /*
- * Always start back at the beginning, to
- * ensure all entries are removed,
- * like list_for_each_entry_safe.
- */
- next = 0;
- }
idr_destroy(&private->mem_idr);
kgsl_mmu_putpagetable(private->pagetable);
@@ -950,6 +944,7 @@
struct kgsl_process_private *private = dev_priv->process_priv;
struct kgsl_device *device = dev_priv->device;
struct kgsl_context *context;
+ struct kgsl_mem_entry *entry;
int next = 0;
filep->private_data = NULL;
@@ -978,6 +973,25 @@
next = next + 1;
}
+ next = 0;
+ while (1) {
+ spin_lock(&private->mem_lock);
+ entry = idr_get_next(&private->mem_idr, &next);
+ spin_unlock(&private->mem_lock);
+ if (entry == NULL)
+ break;
+ /*
+ * If the free pending flag is not set it means that user space
+ * did not free it's reference to this entry, in that case
+ * free a reference to this entry, other references are from
+ * within kgsl so they will be freed eventually by kgsl
+ */
+ if (entry->dev_priv == dev_priv && !entry->pending_free) {
+ entry->pending_free = 1;
+ kgsl_mem_entry_put(entry);
+ }
+ next = next + 1;
+ }
/*
* Clean up any to-be-freed entries that belong to this
* process and this device. This is done after the context
@@ -1014,7 +1028,7 @@
if (result)
goto err;
- result = device->ftbl->start(device);
+ result = device->ftbl->start(device, 0);
if (result)
goto err;
/*
@@ -2740,7 +2754,7 @@
/* echo back flags */
param->flags = entry->memdesc.flags;
- result = kgsl_mem_entry_attach_process(entry, private);
+ result = kgsl_mem_entry_attach_process(entry, dev_priv);
if (result)
goto error_attach;
@@ -2864,7 +2878,7 @@
bool full_flush = false;
if (param->id_list == NULL || param->count == 0
- || param->count > (UINT_MAX/sizeof(unsigned int)))
+ || param->count > (PAGE_SIZE / sizeof(unsigned int)))
return -EINVAL;
id_list = kzalloc(param->count * sizeof(unsigned int), GFP_KERNEL);
@@ -3028,7 +3042,7 @@
if (result)
return result;
- result = kgsl_mem_entry_attach_process(entry, private);
+ result = kgsl_mem_entry_attach_process(entry, dev_priv);
if (result != 0)
goto err;
@@ -3061,7 +3075,7 @@
if (result != 0)
goto err;
- result = kgsl_mem_entry_attach_process(entry, private);
+ result = kgsl_mem_entry_attach_process(entry, dev_priv);
if (result != 0)
goto err;
@@ -4051,7 +4065,7 @@
del_timer_sync(&device->idle_timer);
/* Force on the clocks */
- kgsl_pwrctrl_wake(device);
+ kgsl_pwrctrl_wake(device, 0);
/* Disable the irq */
kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF);
diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h
index ee7a485..6da4a86 100644
--- a/drivers/gpu/msm/kgsl.h
+++ b/drivers/gpu/msm/kgsl.h
@@ -200,6 +200,7 @@
struct kgsl_process_private *priv;
/* Initialized to 0, set to 1 when entry is marked for freeing */
int pending_free;
+ struct kgsl_device_private *dev_priv;
};
#ifdef CONFIG_MSM_KGSL_MMU_PAGE_FAULT
diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h
index b76e9ff..7fc6fae 100644
--- a/drivers/gpu/msm/kgsl_device.h
+++ b/drivers/gpu/msm/kgsl_device.h
@@ -62,6 +62,8 @@
#define KGSL_EVENT_TIMESTAMP_RETIRED 0
#define KGSL_EVENT_CANCELLED 1
+#define KGSL_FLAG_WAKE_ON_TOUCH BIT(0)
+
/*
* "list" of event types for ftrace symbolic magic
*/
@@ -91,7 +93,7 @@
bool (*isidle) (struct kgsl_device *device);
int (*suspend_context) (struct kgsl_device *device);
int (*init) (struct kgsl_device *device);
- int (*start) (struct kgsl_device *device);
+ int (*start) (struct kgsl_device *device, int priority);
int (*stop) (struct kgsl_device *device);
int (*getproperty) (struct kgsl_device *device,
enum kgsl_property_type type, void *value,
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c
index 769abfc..3e15580 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -17,6 +17,7 @@
#include <linux/pm_runtime.h>
#include <mach/msm_iomap.h>
#include <mach/msm_bus.h>
+#include <mach/msm_bus_board.h>
#include <linux/ktime.h>
#include <linux/delay.h>
@@ -123,13 +124,34 @@
return level;
}
+void kgsl_pwrctrl_buslevel_update(struct kgsl_device *device,
+ bool on)
+{
+ struct kgsl_pwrctrl *pwr = &device->pwrctrl;
+ int cur = pwr->pwrlevels[pwr->active_pwrlevel].bus_freq;
+ int buslevel = 0;
+ if (!pwr->pcl)
+ return;
+ /*
+ * If the bus should remain on calculate our request and submit it,
+ * otherwise request bus level 0, off.
+ */
+ if (on) {
+ buslevel = min_t(int, pwr->pwrlevels[0].bus_freq,
+ cur + pwr->bus_mod);
+ buslevel = max_t(int, buslevel, 1);
+ }
+ msm_bus_scale_client_update_request(pwr->pcl, buslevel);
+ trace_kgsl_pwrlevel(device, pwr->active_pwrlevel, buslevel);
+}
+EXPORT_SYMBOL(kgsl_pwrctrl_buslevel_update);
+
void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device,
unsigned int new_level)
{
struct kgsl_pwrctrl *pwr = &device->pwrctrl;
struct kgsl_pwrlevel *pwrlevel;
- int delta;
- int level;
+ int delta, level;
/* Adjust the power level to the current constraints */
new_level = _adjust_pwrlevel(pwr, new_level);
@@ -150,14 +172,12 @@
*/
pwr->active_pwrlevel = new_level;
+ pwr->bus_mod = 0;
pwrlevel = &pwr->pwrlevels[pwr->active_pwrlevel];
if (test_bit(KGSL_PWRFLAGS_AXI_ON, &pwr->power_flags)) {
-
- if (pwr->pcl)
- msm_bus_scale_client_update_request(pwr->pcl,
- pwrlevel->bus_freq);
- else if (pwr->ebi1_clk)
+ kgsl_pwrctrl_buslevel_update(device, true);
+ if (pwr->ebi1_clk)
clk_set_rate(pwr->ebi1_clk, pwrlevel->bus_freq);
}
@@ -735,6 +755,42 @@
return __force_on_store(dev, attr, buf, count, KGSL_PWRFLAGS_POWER_ON);
}
+static ssize_t kgsl_pwrctrl_bus_split_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct kgsl_device *device = kgsl_device_from_dev(dev);
+ if (device == NULL)
+ return 0;
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ device->pwrctrl.bus_control);
+}
+
+static ssize_t kgsl_pwrctrl_bus_split_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ char temp[20];
+ unsigned long val;
+ struct kgsl_device *device = kgsl_device_from_dev(dev);
+ int rc;
+
+ if (device == NULL)
+ return 0;
+
+ snprintf(temp, sizeof(temp), "%.*s",
+ (int)min(count, sizeof(temp) - 1), buf);
+ rc = kstrtoul(temp, 0, &val);
+ if (rc)
+ return rc;
+
+ mutex_lock(&device->mutex);
+ device->pwrctrl.bus_control = val ? true : false;
+ mutex_unlock(&device->mutex);
+
+ return count;
+}
+
DEVICE_ATTR(gpuclk, 0644, kgsl_pwrctrl_gpuclk_show, kgsl_pwrctrl_gpuclk_store);
DEVICE_ATTR(max_gpuclk, 0644, kgsl_pwrctrl_max_gpuclk_show,
kgsl_pwrctrl_max_gpuclk_store);
@@ -774,6 +830,9 @@
DEVICE_ATTR(force_rail_on, 0644,
kgsl_pwrctrl_force_rail_on_show,
kgsl_pwrctrl_force_rail_on_store);
+DEVICE_ATTR(bus_split, 0644,
+ kgsl_pwrctrl_bus_split_show,
+ kgsl_pwrctrl_bus_split_store);
static const struct device_attribute *pwrctrl_attr_list[] = {
&dev_attr_gpuclk,
@@ -791,6 +850,7 @@
&dev_attr_force_clk_on,
&dev_attr_force_bus_on,
&dev_attr_force_rail_on,
+ &dev_attr_bus_split,
NULL
};
@@ -917,9 +977,7 @@
clk_set_rate(pwr->ebi1_clk, 0);
clk_disable_unprepare(pwr->ebi1_clk);
}
- if (pwr->pcl)
- msm_bus_scale_client_update_request(pwr->pcl,
- 0);
+ kgsl_pwrctrl_buslevel_update(device, false);
}
} else if (state == KGSL_PWRFLAGS_ON) {
if (!test_and_set_bit(KGSL_PWRFLAGS_AXI_ON,
@@ -931,10 +989,7 @@
pwr->pwrlevels[pwr->active_pwrlevel].
bus_freq);
}
- if (pwr->pcl)
- msm_bus_scale_client_update_request(pwr->pcl,
- pwr->pwrlevels[pwr->active_pwrlevel].
- bus_freq);
+ kgsl_pwrctrl_buslevel_update(device, true);
}
}
}
@@ -1004,7 +1059,7 @@
int kgsl_pwrctrl_init(struct kgsl_device *device)
{
- int i, result = 0;
+ int i, k, m, n = 0, result = 0;
struct clk *clk;
struct platform_device *pdev =
container_of(device->parentdev, struct platform_device, dev);
@@ -1085,26 +1140,61 @@
clk_set_rate(pwr->ebi1_clk,
pwr->pwrlevels[pwr->active_pwrlevel].
bus_freq);
- if (pdata->bus_scale_table != NULL) {
- pwr->pcl = msm_bus_scale_register_client(pdata->
- bus_scale_table);
- if (!pwr->pcl) {
- KGSL_PWR_ERR(device,
- "msm_bus_scale_register_client failed: "
- "id %d table %p", device->id,
- pdata->bus_scale_table);
- result = -EINVAL;
- goto done;
- }
- }
-
- /* Set the power level step multiplier with 1 as the default */
- pwr->step_mul = pdata->step_mul ? pdata->step_mul : 1;
/* Set the CPU latency to 501usec to allow low latency PC modes */
pwr->pm_qos_latency = 501;
pm_runtime_enable(device->parentdev);
+
+ if (pdata->bus_scale_table == NULL)
+ return result;
+
+ pwr->pcl = msm_bus_scale_register_client(pdata->
+ bus_scale_table);
+ if (!pwr->pcl) {
+ KGSL_PWR_ERR(device,
+ "msm_bus_scale_register_client failed: "
+ "id %d table %p", device->id,
+ pdata->bus_scale_table);
+ result = -EINVAL;
+ goto done;
+ }
+
+ /* Set if independent bus BW voting is supported */
+ pwr->bus_control = pdata->bus_control;
+ /*
+ * Pull the BW vote out of the bus table. They will be used to
+ * calculate the ratio between the votes.
+ */
+ for (i = 0; i < pdata->bus_scale_table->num_usecases; i++) {
+ struct msm_bus_paths *usecase =
+ &pdata->bus_scale_table->usecase[i];
+ struct msm_bus_vectors *vector = &usecase->vectors[0];
+ if (vector->dst == MSM_BUS_SLAVE_EBI_CH0 &&
+ vector->ib != 0) {
+ for (k = 0; k < n; k++)
+ if (vector->ib == pwr->bus_ib[k])
+ break;
+ /* if this is a new ib value, save it */
+ if (k == n) {
+ pwr->bus_ib[k] = vector->ib;
+ n++;
+ /* find which pwrlevels use this ib */
+ for (m = 0; m < pwr->num_pwrlevels - 1; m++) {
+ if (pdata->bus_scale_table->
+ usecase[pwr->pwrlevels[m].
+ bus_freq].vectors[0].ib
+ == vector->ib)
+ pwr->bus_index[m] = k;
+ }
+ printk("kgsl bus ib [%d] = %llu\n", k, vector->ib);
+ }
+ }
+ }
+
+ for (m = 0; m < pwr->num_pwrlevels - 1; m++)
+ printk("kgsl bus index is %d for pwrlevel %d\n", pwr->bus_index[m], m);
+
return result;
clk_err:
@@ -1279,9 +1369,9 @@
/*
* Read HW busy counters before going to NAP state.
- * The data might be used by power scale govenors
+ * The data might be used by power scale governors
* independently of the HW activity. For example
- * the simple-on-demand governer will get the latest
+ * the simple-on-demand governor will get the latest
* busy_time data even if the gpu isn't active.
*/
device->ftbl->power_stats(device, &stats);
@@ -1404,9 +1494,16 @@
}
EXPORT_SYMBOL(kgsl_pwrctrl_sleep);
-/******************************************************************/
-/* Caller must hold the device mutex. */
-int kgsl_pwrctrl_wake(struct kgsl_device *device)
+/**
+ * kgsl_pwrctrl_wake() - Power up the GPU from a slumber/sleep state
+ * @device - Pointer to the kgsl_device struct
+ * @priority - Boolean flag to indicate that the GPU start should be run in the
+ * higher priority thread
+ *
+ * Resume the GPU from a lower power state to ACTIVE. The caller to this
+ * fucntion must host the kgsl_device mutex.
+ */
+int kgsl_pwrctrl_wake(struct kgsl_device *device, int priority)
{
int status = 0;
unsigned int context_id;
@@ -1417,7 +1514,8 @@
kgsl_pwrctrl_request_state(device, KGSL_STATE_ACTIVE);
switch (device->state) {
case KGSL_STATE_SLUMBER:
- status = device->ftbl->start(device);
+ status = device->ftbl->start(device, priority);
+
if (status) {
kgsl_pwrctrl_request_state(device, KGSL_STATE_NONE);
KGSL_DRV_ERR(device, "start failed %d\n", status);
@@ -1550,7 +1648,7 @@
wait_for_completion(&device->hwaccess_gate);
mutex_lock(&device->mutex);
- ret = kgsl_pwrctrl_wake(device);
+ ret = kgsl_pwrctrl_wake(device, 1);
}
if (ret == 0)
atomic_inc(&device->active_cnt);
@@ -1606,6 +1704,8 @@
mod_timer(&device->idle_timer,
jiffies + device->pwrctrl.interval_timeout);
+ } else {
+ kgsl_pwrscale_update(device);
}
trace_kgsl_active_count(device,
diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h
index ba5ccd6..6ec809d 100644
--- a/drivers/gpu/msm/kgsl_pwrctrl.h
+++ b/drivers/gpu/msm/kgsl_pwrctrl.h
@@ -64,7 +64,9 @@
* @clk_stats - structure of clock statistics
* @pm_qos_req_dma - the power management quality of service structure
* @pm_qos_latency - allowed CPU latency in microseconds
- * @step_mul - multiplier for moving between power levels
+ * @bus_control - true if the bus calculation is independent
+ * @bus_index - default bus index into the bus_ib table
+ * @bus_ib - the set of unique ib requests needed for the bus calculation
*/
struct kgsl_pwrctrl {
@@ -88,11 +90,14 @@
uint32_t pcl;
unsigned int idle_needed;
const char *irq_name;
+ bool irq_last;
struct kgsl_clk_stats clk_stats;
struct pm_qos_request pm_qos_req_dma;
unsigned int pm_qos_latency;
- unsigned int step_mul;
- unsigned int irq_last;
+ bool bus_control;
+ int bus_mod;
+ unsigned int bus_index[KGSL_MAX_PWRLEVELS];
+ uint64_t bus_ib[KGSL_MAX_PWRLEVELS];
};
void kgsl_pwrctrl_irq(struct kgsl_device *device, int state);
@@ -102,9 +107,11 @@
void kgsl_idle_check(struct work_struct *work);
void kgsl_pre_hwaccess(struct kgsl_device *device);
int kgsl_pwrctrl_sleep(struct kgsl_device *device);
-int kgsl_pwrctrl_wake(struct kgsl_device *device);
+int kgsl_pwrctrl_wake(struct kgsl_device *device, int priority);
void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device,
unsigned int level);
+void kgsl_pwrctrl_buslevel_update(struct kgsl_device *device,
+ bool on);
int kgsl_pwrctrl_init_sysfs(struct kgsl_device *device);
void kgsl_pwrctrl_uninit_sysfs(struct kgsl_device *device);
void kgsl_pwrctrl_enable(struct kgsl_device *device);
diff --git a/drivers/gpu/msm/kgsl_pwrscale.c b/drivers/gpu/msm/kgsl_pwrscale.c
index 140cb7b..52732cf 100644
--- a/drivers/gpu/msm/kgsl_pwrscale.c
+++ b/drivers/gpu/msm/kgsl_pwrscale.c
@@ -19,6 +19,9 @@
#include "kgsl_device.h"
#include "kgsl_trace.h"
+#define FAST_BUS 1
+#define SLOW_BUS -1
+
static void do_devfreq_suspend(struct work_struct *work);
static void do_devfreq_resume(struct work_struct *work);
static void do_devfreq_notify(struct work_struct *work);
@@ -96,11 +99,12 @@
* Read hardware busy counters when the device is likely to be
* on and accumulate the results between devfreq get_dev_status
* calls. This is limits the need to turn on clocks to read these
- * values for governers that run independtly of hardware
+ * values for governors that run independently of hardware
* activity (for example, by time based polling).
*/
void kgsl_pwrscale_update(struct kgsl_device *device)
{
+ struct kgsl_power_stats stats;
BUG_ON(!mutex_is_locked(&device->mutex));
if (!device->pwrscale.enabled)
@@ -115,9 +119,17 @@
device->pwrscale.next_governor_call = jiffies
+ msecs_to_jiffies(KGSL_GOVERNOR_CALL_INTERVAL);
+ if (device->state == KGSL_STATE_ACTIVE) {
+ device->ftbl->power_stats(device, &stats);
+ device->pwrscale.accum_stats.busy_time += stats.busy_time;
+ device->pwrscale.accum_stats.ram_time += stats.ram_time;
+ device->pwrscale.accum_stats.ram_wait += stats.ram_wait;
+ }
+
/* to call srcu_notifier_call_chain() from a kernel thread */
- queue_work(device->pwrscale.devfreq_wq,
- &device->pwrscale.devfreq_notify_ws);
+ if (device->requested_state != KGSL_STATE_SLUMBER)
+ queue_work(device->pwrscale.devfreq_wq,
+ &device->pwrscale.devfreq_notify_ws);
}
EXPORT_SYMBOL(kgsl_pwrscale_update);
@@ -172,55 +184,50 @@
int kgsl_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
{
struct kgsl_device *device = dev_get_drvdata(dev);
- struct devfreq_dev_profile *profile;
struct kgsl_pwrctrl *pwr;
- int level = -1, i;
+ int level, i, b;
unsigned long cur_freq;
- int bus_mod = 0;
if (device == NULL)
return -ENODEV;
if (freq == NULL)
return -EINVAL;
- profile = &device->pwrscale.profile;
- pwr = &device->pwrctrl;
+ if (!device->pwrscale.enabled)
+ return 0;
- if (flags & DEVFREQ_FLAG_FAST_HINT)
- bus_mod = 1;
+ pwr = &device->pwrctrl;
mutex_lock(&device->mutex);
cur_freq = kgsl_pwrctrl_active_freq(pwr);
+ level = pwr->active_pwrlevel;
- if (*freq > cur_freq && pwr->active_pwrlevel > 0) {
- /*
- * If FAST is requested, move up just one level,
- * otherwise - move up until required freq or higher
- */
- level = pwr->active_pwrlevel - 1;
- if (!bus_mod)
- while (*freq > pwr->pwrlevels[level].gpu_freq
- && level > 0)
- level--;
- } else if (*freq < cur_freq
- && pwr->active_pwrlevel < (pwr->num_pwrlevels - 2)) {
- /*
- * Move down at least 1 frequency. If we fall out the bottom
- * of the loop, use the lowest frequency.
- */
- level = (pwr->num_pwrlevels - 1);
- for (i = pwr->active_pwrlevel; i < level; i += pwr->step_mul)
- if (pwr->pwrlevels[i].gpu_freq <= *freq) {
+ if (*freq != cur_freq) {
+ level = pwr->max_pwrlevel;
+ for (i = pwr->min_pwrlevel; i >= pwr->max_pwrlevel; i--)
+ if (*freq <= pwr->pwrlevels[i].gpu_freq) {
level = i;
break;
}
- } else {
- /* already at current freq, min, or max */
- level = pwr->active_pwrlevel;
+ } else if (flags && pwr->bus_control) {
+ /*
+ * Signal for faster or slower bus. If KGSL isn't already
+ * running at the desired speed for the given level, modify
+ * its vote.
+ */
+ b = pwr->bus_mod;
+ if ((flags & DEVFREQ_FLAG_FAST_HINT) &&
+ (pwr->bus_mod != FAST_BUS))
+ pwr->bus_mod = (pwr->bus_mod == SLOW_BUS) ?
+ 0 : FAST_BUS;
+ else if ((flags & DEVFREQ_FLAG_SLOW_HINT) &&
+ (pwr->bus_mod != SLOW_BUS))
+ pwr->bus_mod = (pwr->bus_mod == FAST_BUS) ?
+ 0 : SLOW_BUS;
+ if (pwr->bus_mod != b)
+ kgsl_pwrctrl_buslevel_update(device, true);
}
- if (device->pwrscale.enabled)
- kgsl_pwrctrl_pwrlevel_change(device, level);
-
+ kgsl_pwrctrl_pwrlevel_change(device, level);
*freq = kgsl_pwrctrl_active_freq(pwr);
mutex_unlock(&device->mutex);
@@ -249,7 +256,6 @@
return -EINVAL;
pwrscale = &device->pwrscale;
- memset(stat, 0, sizeof(*stat));
mutex_lock(&device->mutex);
/* make sure we don't turn on clocks just to read stats */
@@ -257,6 +263,8 @@
struct kgsl_power_stats extra;
device->ftbl->power_stats(device, &extra);
device->pwrscale.accum_stats.busy_time += extra.busy_time;
+ device->pwrscale.accum_stats.ram_time += extra.ram_time;
+ device->pwrscale.accum_stats.ram_wait += extra.ram_wait;
}
tmp = ktime_to_us(ktime_get());
@@ -267,6 +275,13 @@
stat->current_frequency = kgsl_pwrctrl_active_freq(&device->pwrctrl);
+ if (stat->private_data) {
+ struct xstats *b = (struct xstats *)stat->private_data;
+ b->ram_time = device->pwrscale.accum_stats.ram_time;
+ b->ram_wait = device->pwrscale.accum_stats.ram_wait;
+ b->mod = device->pwrctrl.bus_mod;
+ }
+
trace_kgsl_pwrstats(device, stat->total_time, &pwrscale->accum_stats);
memset(&pwrscale->accum_stats, 0, sizeof(pwrscale->accum_stats));
@@ -364,6 +379,8 @@
struct kgsl_pwrscale *pwrscale;
struct kgsl_pwrctrl *pwr;
struct devfreq *devfreq;
+ struct devfreq_dev_profile *profile;
+ struct devfreq_msm_adreno_tz_data *data;
int i, out = 0;
int ret;
@@ -373,26 +390,56 @@
pwrscale = &device->pwrscale;
pwr = &device->pwrctrl;
+ profile = &pwrscale->profile;
srcu_init_notifier_head(&pwrscale->nh);
- pwrscale->profile.initial_freq =
+ profile->initial_freq =
pwr->pwrlevels[pwr->default_pwrlevel].gpu_freq;
/* Let's start with 10 ms and tune in later */
- pwrscale->profile.polling_ms = 10;
+ profile->polling_ms = 10;
/* do not include the 'off' level or duplicate freq. levels */
- for (i = 0; i < (pwr->num_pwrlevels - 1); i += pwr->step_mul)
+ for (i = 0; i < (pwr->num_pwrlevels - 1); i++)
pwrscale->freq_table[out++] = pwr->pwrlevels[i].gpu_freq;
- pwrscale->profile.max_state = out;
+ profile->max_state = out;
/* link storage array to the devfreq profile pointer */
- pwrscale->profile.freq_table = pwrscale->freq_table;
+ profile->freq_table = pwrscale->freq_table;
/* if there is only 1 freq, no point in running a governor */
- if (pwrscale->profile.max_state == 1)
+ if (profile->max_state == 1)
governor = "performance";
+ /* initialize any governor specific data here */
+ for (i = 0; i < profile->num_governor_data; i++) {
+ if (strncmp("msm-adreno-tz",
+ profile->governor_data[i].name,
+ DEVFREQ_NAME_LEN) == 0) {
+ data = (struct devfreq_msm_adreno_tz_data *)
+ profile->governor_data[i].data;
+ /*
+ * If there is a separate GX power rail, allow
+ * independent modification to its voltage through
+ * the bus bandwidth vote.
+ */
+ if (pwr->bus_control) {
+ out = 0;
+ while (pwr->bus_ib[out]) {
+ pwr->bus_ib[out] =
+ pwr->bus_ib[out] >> 20;
+ out++;
+ }
+ data->bus.num = out;
+ data->bus.ib = &pwr->bus_ib[0];
+ data->bus.index = &pwr->bus_index[0];
+ printk("kgsl: num bus is %d\n", out);
+ } else {
+ data->bus.num = 0;
+ }
+ }
+ }
+
devfreq = devfreq_add_device(dev, &pwrscale->profile, governor, NULL);
if (IS_ERR(devfreq))
return PTR_ERR(devfreq);
diff --git a/drivers/gpu/msm/kgsl_pwrscale.h b/drivers/gpu/msm/kgsl_pwrscale.h
index 9737b65..866964c 100644
--- a/drivers/gpu/msm/kgsl_pwrscale.h
+++ b/drivers/gpu/msm/kgsl_pwrscale.h
@@ -22,6 +22,8 @@
struct kgsl_power_stats {
u64 busy_time;
+ u64 ram_time;
+ u64 ram_wait;
};
struct kgsl_pwrscale {
diff --git a/drivers/gpu/msm/kgsl_sharedmem.h b/drivers/gpu/msm/kgsl_sharedmem.h
index 3986c61..505be69 100644
--- a/drivers/gpu/msm/kgsl_sharedmem.h
+++ b/drivers/gpu/msm/kgsl_sharedmem.h
@@ -141,6 +141,9 @@
static inline void *kgsl_sg_alloc(unsigned int sglen)
{
+ if (sglen >= ULONG_MAX / sizeof(struct scatterlist))
+ return NULL;
+
if ((sglen * sizeof(struct scatterlist)) < PAGE_SIZE)
return kzalloc(sglen * sizeof(struct scatterlist), GFP_KERNEL);
else
diff --git a/drivers/gpu/msm/kgsl_trace.h b/drivers/gpu/msm/kgsl_trace.h
index 1fd555d..c737cc8 100644
--- a/drivers/gpu/msm/kgsl_trace.h
+++ b/drivers/gpu/msm/kgsl_trace.h
@@ -287,31 +287,6 @@
)
);
-TRACE_EVENT(kgsl_pwrstats,
- TP_PROTO(struct kgsl_device *device, u64 total_time,
- struct kgsl_power_stats *pstats),
-
- TP_ARGS(device, total_time, pstats),
-
- TP_STRUCT__entry(
- __string(device_name, device->name)
- __field(u64, total_time)
- __field(u64, busy_time)
- ),
-
- TP_fast_assign(
- __assign_str(device_name, device->name);
- __entry->total_time = total_time;
- __entry->busy_time = pstats->busy_time;
- ),
-
- TP_printk(
- "d_name=%s total=%lld busy=%lld",
- __get_str(device_name),
- __entry->total_time, __entry->busy_time
- )
-);
-
DECLARE_EVENT_CLASS(kgsl_pwrstate_template,
TP_PROTO(struct kgsl_device *device, unsigned int state),
@@ -821,6 +796,37 @@
)
);
+
+TRACE_EVENT(kgsl_pwrstats,
+ TP_PROTO(struct kgsl_device *device, s64 time,
+ struct kgsl_power_stats *pstats),
+
+ TP_ARGS(device, time, pstats),
+
+ TP_STRUCT__entry(
+ __string(device_name, device->name)
+ __field(s64, total_time)
+ __field(u64, busy_time)
+ __field(u64, ram_time)
+ __field(u64, ram_wait)
+ ),
+
+ TP_fast_assign(
+ __assign_str(device_name, device->name);
+ __entry->total_time = time;
+ __entry->busy_time = pstats->busy_time;
+ __entry->ram_time = pstats->ram_time;
+ __entry->ram_wait = pstats->ram_wait;
+ ),
+
+ TP_printk(
+ "d_name=%s total=%lld busy=%lld ram_time=%lld ram_wait=%lld",
+ __get_str(device_name), __entry->total_time, __entry->busy_time,
+ __entry->ram_time, __entry->ram_wait
+ )
+);
+
+
#endif /* _KGSL_TRACE_H */
/* This part must be outside protection */
diff --git a/drivers/gpu/msm/z180.c b/drivers/gpu/msm/z180.c
index 7e58771..270a7a6 100644
--- a/drivers/gpu/msm/z180.c
+++ b/drivers/gpu/msm/z180.c
@@ -94,7 +94,7 @@
#define Z180_CMDWINDOW_ADDR_SHIFT 8
static int z180_init(struct kgsl_device *device);
-static int z180_start(struct kgsl_device *device);
+static int z180_start(struct kgsl_device *device, int priority);
static int z180_stop(struct kgsl_device *device);
static int z180_wait(struct kgsl_device *device,
struct kgsl_context *context,
@@ -594,7 +594,7 @@
return 0;
}
-static int z180_start(struct kgsl_device *device)
+static int z180_start(struct kgsl_device *device, int priority)
{
int status = 0;
diff --git a/drivers/hwmon/qpnp-adc-current.c b/drivers/hwmon/qpnp-adc-current.c
index adaff41..9839595 100644
--- a/drivers/hwmon/qpnp-adc-current.c
+++ b/drivers/hwmon/qpnp-adc-current.c
@@ -147,7 +147,6 @@
struct list_head list;
int64_t die_temp;
struct delayed_work iadc_work;
- struct mutex iadc_vadc_lock;
bool iadc_mode_sel;
struct qpnp_iadc_comp iadc_comp;
struct qpnp_vadc_chip *vadc_dev;
@@ -1012,12 +1011,10 @@
if (qpnp_iadc_is_valid(iadc) < 0)
return -EPROBE_DEFER;
- if (!iadc->iadc_mode_sel) {
- rc = qpnp_check_pmic_temp(iadc);
- if (rc) {
- pr_err("Error checking pmic therm temp\n");
- return rc;
- }
+ rc = qpnp_check_pmic_temp(iadc);
+ if (rc) {
+ pr_err("Error checking pmic therm temp\n");
+ return rc;
}
mutex_lock(&iadc->adc->adc_lock);
@@ -1121,24 +1118,21 @@
enum qpnp_iadc_channels i_channel, struct qpnp_iadc_result *i_result,
enum qpnp_vadc_channels v_channel, struct qpnp_vadc_result *v_result)
{
- int rc = 0;
+ int rc = 0, mode_sel = 0, num = 0, rsense_n_ohms = 0, sign = 0;
+ uint16_t raw_data;
+ int32_t rsense_u_ohms = 0;
+ int64_t result_current;
if (qpnp_iadc_is_valid(iadc) < 0)
return -EPROBE_DEFER;
- mutex_lock(&iadc->iadc_vadc_lock);
+ mutex_lock(&iadc->adc->adc_lock);
if (iadc->iadc_poll_eoc) {
pr_debug("acquiring iadc eoc wakelock\n");
pm_stay_awake(iadc->dev);
}
- rc = qpnp_check_pmic_temp(iadc);
- if (rc) {
- pr_err("PMIC die temp check failed\n");
- goto fail;
- }
-
iadc->iadc_mode_sel = true;
rc = qpnp_vadc_iadc_sync_request(iadc->vadc_dev, v_channel);
@@ -1147,11 +1141,43 @@
goto fail;
}
- rc = qpnp_iadc_read(iadc, i_channel, i_result);
- if (rc)
- pr_err("Configuring IADC failed\n");
- /* Intentional fall through to release VADC */
+ rc = qpnp_iadc_configure(iadc, i_channel, &raw_data, mode_sel);
+ if (rc < 0) {
+ pr_err("qpnp adc result read failed with %d\n", rc);
+ goto fail_release_vadc;
+ }
+ rc = qpnp_iadc_get_rsense(iadc, &rsense_n_ohms);
+ pr_debug("current raw:0%x and rsense:%d\n",
+ raw_data, rsense_n_ohms);
+ rsense_u_ohms = rsense_n_ohms/1000;
+ num = raw_data - iadc->adc->calib.offset_raw;
+ if (num < 0) {
+ sign = 1;
+ num = -num;
+ }
+
+ i_result->result_uv = (num * QPNP_ADC_GAIN_NV)/
+ (iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw);
+ result_current = i_result->result_uv;
+ result_current *= QPNP_IADC_NANO_VOLTS_FACTOR;
+ /* Intentional fall through. Process the result w/o comp */
+ do_div(result_current, rsense_u_ohms);
+
+ if (sign) {
+ i_result->result_uv = -i_result->result_uv;
+ result_current = -result_current;
+ }
+ result_current *= -1;
+ rc = qpnp_iadc_comp_result(iadc, &result_current);
+ if (rc < 0)
+ pr_err("Error during compensating the IADC\n");
+ rc = 0;
+ result_current *= -1;
+
+ i_result->result_ua = (int32_t) result_current;
+
+fail_release_vadc:
rc = qpnp_vadc_iadc_sync_complete_request(iadc->vadc_dev, v_channel,
v_result);
if (rc)
@@ -1163,7 +1189,7 @@
pr_debug("releasing iadc eoc wakelock\n");
pm_relax(iadc->dev);
}
- mutex_unlock(&iadc->iadc_vadc_lock);
+ mutex_unlock(&iadc->adc->adc_lock);
return rc;
}
@@ -1306,7 +1332,6 @@
goto fail;
}
- mutex_init(&iadc->iadc_vadc_lock);
INIT_WORK(&iadc->trigger_completion_work, qpnp_iadc_trigger_completion);
INIT_DELAYED_WORK(&iadc->iadc_work, qpnp_iadc_work);
rc = qpnp_iadc_comp_info(iadc);
@@ -1347,7 +1372,6 @@
int i = 0;
cancel_delayed_work(&iadc->iadc_work);
- mutex_destroy(&iadc->iadc_vadc_lock);
for_each_child_of_node(node, child) {
device_remove_file(&spmi->dev,
&iadc->sens_attr[i].dev_attr);
diff --git a/drivers/input/input.c b/drivers/input/input.c
index 8921c61..b773e1b 100644
--- a/drivers/input/input.c
+++ b/drivers/input/input.c
@@ -1574,9 +1574,11 @@
* Keys that have been pressed at suspend time are unlikely
* to be still pressed when we resume.
*/
- spin_lock_irq(&dev->event_lock);
- input_dev_release_keys(dev);
- spin_unlock_irq(&dev->event_lock);
+ if (!test_bit(INPUT_PROP_NO_DUMMY_RELEASE, dev->propbit)) {
+ spin_lock_irq(&dev->event_lock);
+ input_dev_release_keys(dev);
+ spin_unlock_irq(&dev->event_lock);
+ }
}
mutex_unlock(&dev->mutex);
diff --git a/drivers/input/misc/bmp18x-core.c b/drivers/input/misc/bmp18x-core.c
index 4b5b710..001a804 100644
--- a/drivers/input/misc/bmp18x-core.c
+++ b/drivers/input/misc/bmp18x-core.c
@@ -50,6 +50,7 @@
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/input.h>
+#include <linux/sensors.h>
#include <linux/workqueue.h>
#include <linux/module.h>
#ifdef CONFIG_HAS_EARLYSUSPEND
@@ -103,6 +104,20 @@
u32 enable;
};
+static struct sensors_classdev sensors_cdev = {
+ .name = "bmp18x-pressure",
+ .vendor = "Bosch",
+ .version = 1,
+ .handle = SENSORS_PRESSURE_HANDLE,
+ .type = SENSOR_TYPE_PRESSURE,
+ .max_range = "1100.0",
+ .resolution = "0.01",
+ .sensor_power = "0.67",
+ .min_delay = 20000,
+ .fifo_reserved_event_count = 0,
+ .fifo_max_event_count = 0,
+};
+
#ifdef CONFIG_HAS_EARLYSUSPEND
static void bmp18x_early_suspend(struct early_suspend *h);
static void bmp18x_late_resume(struct early_suspend *h);
@@ -612,6 +627,13 @@
err = sysfs_create_group(&data->input->dev.kobj, &bmp18x_attr_group);
if (err)
goto error_sysfs;
+
+ err = sensors_classdev_register(&data->input->dev, &sensors_cdev);
+ if (err) {
+ pr_err("class device create failed: %d\n", err);
+ goto error_class_sysfs;
+ }
+
/* workqueue init */
INIT_DELAYED_WORK(&data->work, bmp18x_work_func);
data->delay = BMP_DELAY_DEFAULT;
@@ -627,6 +649,8 @@
dev_info(dev, "Succesfully initialized bmp18x!\n");
return 0;
+error_class_sysfs:
+ sysfs_remove_group(&data->input->dev.kobj, &bmp18x_attr_group);
error_sysfs:
bmp18x_input_delete(data);
exit_free:
diff --git a/drivers/input/misc/cm36283.c b/drivers/input/misc/cm36283.c
index 17127a8..ceeb67b 100644
--- a/drivers/input/misc/cm36283.c
+++ b/drivers/input/misc/cm36283.c
@@ -20,6 +20,7 @@
#include <linux/earlysuspend.h>
#include <linux/i2c.h>
#include <linux/input.h>
+#include <linux/sensors.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
@@ -63,6 +64,35 @@
#define CM36283_PS_MAX_POLL_DELAY 1000
#define CM36283_PS_DEFAULT_POLL_DELAY 100
+static struct sensors_classdev sensors_light_cdev = {
+ .name = "cm36283-light",
+ .vendor = "Capella",
+ .version = 1,
+ .handle = SENSORS_LIGHT_HANDLE,
+ .type = SENSOR_TYPE_LIGHT,
+ .max_range = "6553",
+ .resolution = "0.0125",
+ .sensor_power = "0.15",
+ .min_delay = 0,
+ .fifo_reserved_event_count = 0,
+ .fifo_max_event_count = 0,
+};
+
+static struct sensors_classdev sensors_proximity_cdev = {
+ .name = "cm36283-proximity",
+ .vendor = "Capella",
+ .version = 1,
+ .handle = SENSORS_PROXIMITY_HANDLE,
+ .type = SENSOR_TYPE_PROXIMITY,
+ .max_range = "5.0",
+ .resolution = "5.0",
+ .sensor_power = "0.18",
+ .min_delay = 0,
+ .fifo_reserved_event_count = 0,
+ .fifo_max_event_count = 0,
+};
+
+
static const int als_range[] = {
[CM36283_ALS_IT0] = 6554,
[CM36283_ALS_IT1] = 3277,
@@ -674,17 +704,9 @@
{
int ret = -EIO;
unsigned int delay;
-
- mutex_lock(&als_enable_mutex);
- if (lpi->als_enable) {
- dev_err(&lpi->i2c_client->dev, "%s: already enabled\n",
- __func__);
- ret = 0;
- } else {
- ret = control_and_report(lpi, CONTROL_ALS, 1, 0);
- }
-
+ mutex_lock(&als_enable_mutex);
+ ret = control_and_report(lpi, CONTROL_ALS, 1, 0);
mutex_unlock(&als_enable_mutex);
delay = atomic_read(&lpi->ls_poll_delay);
@@ -1565,7 +1587,7 @@
__func__, lpi->ls_cmd);
if (pdata->ls_cmd == 0) {
- lpi->ls_cmd = CM36283_ALS_IT_160ms | CM36283_ALS_GAIN_2;
+ lpi->ls_cmd = CM36283_ALS_IT_80ms | CM36283_ALS_GAIN_2;
}
lp_info = lpi;
@@ -1582,17 +1604,17 @@
mutex_init(&ps_get_adc_mutex);
- //SET LUX STEP FACTOR HERE
- // if adc raw value one step = 5/100 = 1/20 = 0.05 lux
- // the following will set the factor 0.05 = 1/20
- // and lpi->golden_adc = 1;
- // set als_kadc = (ALS_CALIBRATED <<16) | 20;
+ /*
+ * SET LUX STEP FACTOR HERE
+ * if adc raw value one step = 5/100 = 1/20 = 0.05 lux
+ * the following will set the factor 0.05 = 1/20
+ * and lpi->golden_adc = 1;
+ * set als_kadc = (ALS_CALIBRATED << 16) | 20;
+ */
- als_kadc = (ALS_CALIBRATED <<16) | 20;
- lpi->golden_adc = 1;
-
- //ls calibrate always set to 1
- lpi->ls_calibrate = 1;
+ als_kadc = (ALS_CALIBRATED << 16) | 10;
+ lpi->golden_adc = 100;
+ lpi->ls_calibrate = 0;
lightsensor_set_kvalue(lpi);
ret = lightsensor_update_table(lpi);
@@ -1729,6 +1751,13 @@
lpi->early_suspend.resume = cm36283_late_resume;
register_early_suspend(&lpi->early_suspend);
#endif
+ ret = sensors_classdev_register(&client->dev, &sensors_light_cdev);
+ if (ret)
+ goto err_create_ps_device_file;
+
+ ret = sensors_classdev_register(&client->dev, &sensors_proximity_cdev);
+ if (ret)
+ goto err_create_class_sysfs;
mutex_init(&wq_lock);
INIT_DELAYED_WORK(&lpi->ldwork, lsensor_delay_work_handler);
@@ -1736,7 +1765,8 @@
dev_dbg(&lpi->i2c_client->dev, "%s: Probe success!\n", __func__);
return ret;
-
+err_create_class_sysfs:
+ sensors_classdev_unregister(&sensors_light_cdev);
err_create_ps_device_file:
device_unregister(lpi->ps_dev);
err_create_ps_device:
@@ -2009,27 +2039,40 @@
struct cm36283_info *lpi = lp_info;
if (lpi->als_enable) {
- lightsensor_disable(lpi);
+ if (lightsensor_disable(lpi))
+ goto out;
lpi->als_enable = 1;
}
- cm36283_power_set(lpi, 0);
+ if (cm36283_power_set(lpi, 0))
+ goto out;
return 0;
+
+out:
+ dev_err(&lpi->i2c_client->dev, "%s:failed during resume operation.\n",
+ __func__);
+ return -EIO;
}
static int cm36283_resume(struct device *dev)
{
struct cm36283_info *lpi = lp_info;
- cm36283_power_set(lpi, 1);
+ if (cm36283_power_set(lpi, 1))
+ goto out;
if (lpi->als_enable) {
- cm36283_setup(lpi);
- lightsensor_setup(lpi);
- psensor_setup(lpi);
- lightsensor_enable(lpi);
+ ls_initial_cmd(lpi);
+ psensor_initial_cmd(lpi);
+ if (lightsensor_enable(lpi))
+ goto out;
}
return 0;
+
+out:
+ dev_err(&lpi->i2c_client->dev, "%s:failed during resume operation.\n",
+ __func__);
+ return -EIO;
}
#endif
diff --git a/drivers/input/misc/kxtj9.c b/drivers/input/misc/kxtj9.c
index f879d78..f5d8441 100644
--- a/drivers/input/misc/kxtj9.c
+++ b/drivers/input/misc/kxtj9.c
@@ -20,6 +20,7 @@
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/input.h>
+#include <linux/sensors.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/slab.h>
@@ -79,6 +80,21 @@
* The following table lists the maximum appropriate poll interval for each
* available output data rate.
*/
+
+static struct sensors_classdev sensors_cdev = {
+ .name = "kxtj9-accel",
+ .vendor = "Kionix",
+ .version = 1,
+ .handle = 0,
+ .type = 1,
+ .max_range = "19.6",
+ .resolution = "0.01",
+ .sensor_power = "0.2",
+ .min_delay = 2000,
+ .fifo_reserved_event_count = 0,
+ .fifo_max_event_count = 0,
+};
+
static const struct {
unsigned int cutoff;
u8 mask;
@@ -415,19 +431,16 @@
}
}
- tj9->enable = true;
return 0;
fail:
kxtj9_device_power_off(tj9);
- tj9->enable = false;
return err;
}
static void kxtj9_disable(struct kxtj9_data *tj9)
{
kxtj9_device_power_off(tj9);
- tj9->enable = false;
}
@@ -496,18 +509,21 @@
if (error)
return error;
mutex_lock(&input_dev->mutex);
- disable_irq(client->irq);
- if (data == 0)
+ if (data == 0) {
+ disable_irq(client->irq);
kxtj9_disable(tj9);
- else if (data == 1)
- kxtj9_enable(tj9);
- else {
+ tj9->enable = false;
+ } else if (data == 1) {
+ if (!kxtj9_enable(tj9)) {
+ enable_irq(client->irq);
+ tj9->enable = true;
+ }
+ } else {
dev_err(&tj9->client->dev,
"Invalid value of input, input=%ld\n", data);
}
- enable_irq(client->irq);
mutex_unlock(&input_dev->mutex);
return count;
@@ -555,7 +571,8 @@
/* Lock the device to prevent races with open/close (and itself) */
mutex_lock(&input_dev->mutex);
- disable_irq(client->irq);
+ if (tj9->enable)
+ disable_irq(client->irq);
/*
* Set current interval to the greater of the minimum interval or
@@ -563,9 +580,10 @@
*/
tj9->last_poll_interval = max(interval, tj9->pdata.min_interval);
- kxtj9_update_odr(tj9, tj9->last_poll_interval);
-
- enable_irq(client->irq);
+ if (tj9->enable) {
+ kxtj9_update_odr(tj9, tj9->last_poll_interval);
+ enable_irq(client->irq);
+ }
mutex_unlock(&input_dev->mutex);
return count;
@@ -840,6 +858,12 @@
tj9->ctrl_reg1 = tj9->pdata.res_ctl | tj9->pdata.g_range;
tj9->last_poll_interval = tj9->pdata.init_interval;
+ err = sensors_classdev_register(&client->dev, &sensors_cdev);
+ if (err) {
+ dev_err(&client->dev, "class device create failed: %d\n", err);
+ goto err_power_off;
+ }
+
if (client->irq) {
/* If in irq mode, populate INT_CTRL_REG1 and enable DRDY. */
tj9->int_ctrl |= KXTJ9_IEN | KXTJ9_IEA | KXTJ9_IEL;
@@ -857,6 +881,8 @@
goto err_destroy_input;
}
+ disable_irq(tj9->client->irq);
+
err = sysfs_create_group(&client->dev.kobj, &kxtj9_attribute_group);
if (err) {
dev_err(&client->dev, "sysfs create failed: %d\n", err);
@@ -923,7 +949,7 @@
mutex_lock(&input_dev->mutex);
- if (input_dev->users)
+ if (input_dev->users && tj9->enable)
kxtj9_disable(tj9);
mutex_unlock(&input_dev->mutex);
@@ -939,7 +965,7 @@
mutex_lock(&input_dev->mutex);
- if (input_dev->users)
+ if (input_dev->users && tj9->enable)
kxtj9_enable(tj9);
mutex_unlock(&input_dev->mutex);
diff --git a/drivers/input/misc/mma8x5x.c b/drivers/input/misc/mma8x5x.c
index 91aa928..d5053eb 100644
--- a/drivers/input/misc/mma8x5x.c
+++ b/drivers/input/misc/mma8x5x.c
@@ -27,6 +27,7 @@
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/input-polldev.h>
+#include <linux/sensors.h>
#include <linux/regulator/consumer.h>
#include <linux/of_gpio.h>
@@ -55,6 +56,20 @@
#define MMA_SHUTTEDDOWN (1 << 31)
#define MMA_STATE_MASK (~MMA_SHUTTEDDOWN)
+static struct sensors_classdev sensors_cdev = {
+ .name = "mma8x5x-accel",
+ .vendor = "Freescale",
+ .version = 1,
+ .handle = SENSORS_ACCELERATION_HANDLE,
+ .type = SENSOR_TYPE_ACCELEROMETER,
+ .max_range = "19.6",
+ .resolution = "0.01",
+ .sensor_power = "0.2",
+ .min_delay = 2000,
+ .fifo_reserved_event_count = 0,
+ .fifo_max_event_count = 0,
+};
+
struct sensor_regulator {
struct regulator *vreg;
const char *name;
@@ -644,11 +659,19 @@
result = -EINVAL;
goto err_create_sysfs;
}
+ result = sensors_classdev_register(&client->dev, &sensors_cdev);
+ if (result) {
+ dev_err(&client->dev, "create class device file failed!\n");
+ result = -EINVAL;
+ goto err_create_class_sysfs;
+ }
dev_info(&client->dev,
"%s:mma8x5x device driver probe successfully, position =%d\n",
__func__, pdata->position);
return 0;
+err_create_class_sysfs:
+ sysfs_remove_group(&idev->dev.kobj, &mma8x5x_attr_group);
err_create_sysfs:
input_unregister_polled_device(pdata->poll_dev);
err_register_polled_device:
diff --git a/drivers/input/misc/mpu3050.c b/drivers/input/misc/mpu3050.c
index 642975d..3b7bf5a 100644
--- a/drivers/input/misc/mpu3050.c
+++ b/drivers/input/misc/mpu3050.c
@@ -37,6 +37,7 @@
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/input.h>
+#include <linux/sensors.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
@@ -128,6 +129,20 @@
u32 enable;
};
+static struct sensors_classdev sensors_cdev = {
+ .name = "mpu3050-gyro",
+ .vendor = "Invensense",
+ .version = 1,
+ .handle = SENSORS_GYROSCOPE_HANDLE,
+ .type = SENSOR_TYPE_GYROSCOPE,
+ .max_range = "35.0",
+ .resolution = "0.06",
+ .sensor_power = "0.2",
+ .min_delay = 2000,
+ .fifo_reserved_event_count = 0,
+ .fifo_max_event_count = 0,
+};
+
struct sensor_regulator {
struct regulator *vreg;
const char *name;
@@ -804,10 +819,16 @@
goto err_free_irq;
}
+ error = sensors_classdev_register(&client->dev, &sensors_cdev);
+ if (error < 0) {
+ dev_err(&client->dev, "failed to create class device\n");
+ goto err_input_cleanup;
+ }
+
error = create_sysfs_interfaces(&idev->dev);
if (error < 0) {
dev_err(&client->dev, "failed to create sysfs\n");
- goto err_input_cleanup;
+ goto err_class_sysfs;
}
pm_runtime_enable(&client->dev);
@@ -815,6 +836,8 @@
return 0;
+err_class_sysfs:
+ sensors_classdev_unregister(&sensors_cdev);
err_input_cleanup:
input_unregister_device(idev);
err_free_irq:
diff --git a/drivers/input/misc/stk3x1x.c b/drivers/input/misc/stk3x1x.c
index b753d55..f1b060e 100644
--- a/drivers/input/misc/stk3x1x.c
+++ b/drivers/input/misc/stk3x1x.c
@@ -32,6 +32,7 @@
#include <linux/kdev_t.h>
#include <linux/fs.h>
#include <linux/input.h>
+#include <linux/sensors.h>
#include <linux/workqueue.h>
#include <linux/irq.h>
#include <linux/delay.h>
@@ -181,6 +182,35 @@
#define STK_FIR_LEN 16
#define MAX_FIR_LEN 32
+
+static struct sensors_classdev sensors_light_cdev = {
+ .name = "stk3x1x-light",
+ .vendor = "Sensortek",
+ .version = 1,
+ .handle = SENSORS_LIGHT_HANDLE,
+ .type = SENSOR_TYPE_LIGHT,
+ .max_range = "6500",
+ .resolution = "0.0625",
+ .sensor_power = "0.09",
+ .min_delay = 0,
+ .fifo_reserved_event_count = 0,
+ .fifo_max_event_count = 0,
+};
+
+static struct sensors_classdev sensors_proximity_cdev = {
+ .name = "stk3x1x-proximity",
+ .vendor = "Sensortek",
+ .version = 1,
+ .handle = SENSORS_PROXIMITY_HANDLE,
+ .type = SENSOR_TYPE_PROXIMITY,
+ .max_range = "5.0",
+ .resolution = "5.0",
+ .sensor_power = "0.1",
+ .min_delay = 0,
+ .fifo_reserved_event_count = 0,
+ .fifo_max_event_count = 0,
+};
+
struct data_filter {
u16 raw[MAX_FIR_LEN];
int sum;
@@ -2363,6 +2393,14 @@
ps_data->stk_early_suspend.resume = stk3x1x_late_resume;
register_early_suspend(&ps_data->stk_early_suspend);
#endif
+ /* make sure everything is ok before registering the class device */
+ err = sensors_classdev_register(&client->dev, &sensors_light_cdev);
+ if (err)
+ goto err_power_on;
+ err = sensors_classdev_register(&client->dev, &sensors_proximity_cdev);
+ if (err)
+ goto err_class_sysfs;
+
/* enable device power only when it is enabled */
err = stk3x1x_power_ctl(ps_data, false);
if (err)
@@ -2373,6 +2411,9 @@
err_init_all_setting:
stk3x1x_power_ctl(ps_data, false);
+ sensors_classdev_unregister(&sensors_proximity_cdev);
+err_class_sysfs:
+ sensors_classdev_unregister(&sensors_light_cdev);
err_power_on:
stk3x1x_power_init(ps_data, false);
err_power_init:
diff --git a/drivers/input/touchscreen/cyttsp-i2c-qc.c b/drivers/input/touchscreen/cyttsp-i2c-qc.c
index 6c4e6b7..2b1360e 100644
--- a/drivers/input/touchscreen/cyttsp-i2c-qc.c
+++ b/drivers/input/touchscreen/cyttsp-i2c-qc.c
@@ -2873,6 +2873,21 @@
return rc;
}
+static void cyttsp_release_all(struct cyttsp *ts)
+{
+ int id;
+
+ for (id = 0; id < CY_NUM_MT_TCH_ID; id++) {
+ input_mt_slot(ts->input, id);
+ input_mt_report_slot_state(ts->input, MT_TOOL_FINGER, 0);
+ }
+
+ input_report_key(ts->input, BTN_TOUCH, 0);
+ input_report_key(ts->input, BTN_TOOL_FINGER, 0);
+
+ input_sync(ts->input);
+}
+
/* Function to manage power-on resume */
static int cyttsp_resume(struct device *dev)
{
@@ -2978,6 +2993,8 @@
else
disable_irq(ts->client->irq);
+ cyttsp_release_all(ts);
+
if (!(retval < CY_OK)) {
if (ts->platform_data->use_sleep &&
(ts->platform_data->power_state == CY_ACTIVE_STATE)) {
diff --git a/drivers/input/touchscreen/gt9xx/gt9xx.c b/drivers/input/touchscreen/gt9xx/gt9xx.c
index ba38061..b39cb0d 100644
--- a/drivers/input/touchscreen/gt9xx/gt9xx.c
+++ b/drivers/input/touchscreen/gt9xx/gt9xx.c
@@ -1139,53 +1139,70 @@
struct i2c_client *client = ts->client;
struct goodix_ts_platform_data *pdata = ts->pdata;
int ret;
+
if (gpio_is_valid(pdata->irq_gpio)) {
ret = gpio_request(pdata->irq_gpio, "goodix_ts_irq_gpio");
if (ret) {
- dev_err(&client->dev, "irq gpio request failed\n");
- goto pwr_off;
+ dev_err(&client->dev, "Unable to request irq gpio [%d]\n",
+ pdata->irq_gpio);
+ goto err_pwr_off;
}
ret = gpio_direction_input(pdata->irq_gpio);
if (ret) {
- dev_err(&client->dev,
- "set_direction for irq gpio failed\n");
- goto free_irq_gpio;
+ dev_err(&client->dev, "Unable to set direction for irq gpio [%d]\n",
+ pdata->irq_gpio);
+ goto err_free_irq_gpio;
}
} else {
- dev_err(&client->dev, "irq gpio is invalid!\n");
+ dev_err(&client->dev, "Invalid irq gpio [%d]!\n",
+ pdata->irq_gpio);
ret = -EINVAL;
- goto free_irq_gpio;
+ goto err_pwr_off;
}
if (gpio_is_valid(pdata->reset_gpio)) {
- ret = gpio_request(pdata->reset_gpio, "goodix_ts__reset_gpio");
+ ret = gpio_request(pdata->reset_gpio, "goodix_ts_reset_gpio");
if (ret) {
- dev_err(&client->dev, "reset gpio request failed\n");
- goto free_irq_gpio;
+ dev_err(&client->dev, "Unable to request reset gpio [%d]\n",
+ pdata->reset_gpio);
+ goto err_free_irq_gpio;
}
ret = gpio_direction_output(pdata->reset_gpio, 0);
if (ret) {
- dev_err(&client->dev,
- "set_direction for reset gpio failed\n");
- goto free_reset_gpio;
+ dev_err(&client->dev, "Unable to set direction for reset gpio [%d]\n",
+ pdata->reset_gpio);
+ goto err_free_reset_gpio;
}
} else {
- dev_err(&client->dev, "reset gpio is invalid!\n");
+ dev_err(&client->dev, "Invalid irq gpio [%d]!\n",
+ pdata->reset_gpio);
ret = -EINVAL;
- goto free_reset_gpio;
+ goto err_free_irq_gpio;
}
- gpio_direction_input(pdata->reset_gpio);
+ /* IRQ GPIO is an input signal, but we are setting it to output
+ * direction and pulling it down, to comply with power up timing
+ * requirements, mentioned in power up timing section of device
+ * datasheet.
+ */
+ ret = gpio_direction_output(pdata->irq_gpio, 0);
+ if (ret)
+ dev_warn(&client->dev,
+ "pull down interrupt gpio failed\n");
+ ret = gpio_direction_output(pdata->reset_gpio, 0);
+ if (ret)
+ dev_warn(&client->dev,
+ "pull down reset gpio failed\n");
return ret;
-free_reset_gpio:
+err_free_reset_gpio:
if (gpio_is_valid(pdata->reset_gpio))
gpio_free(pdata->reset_gpio);
-free_irq_gpio:
+err_free_irq_gpio:
if (gpio_is_valid(pdata->irq_gpio))
gpio_free(pdata->irq_gpio);
-pwr_off:
+err_pwr_off:
return ret;
}
@@ -1771,10 +1788,16 @@
ts->gtp_rawdiff_mode = 0;
ts->power_on = false;
+ ret = gtp_request_io_port(ts);
+ if (ret) {
+ dev_err(&client->dev, "GTP request IO port failed.\n");
+ goto exit_free_client_data;
+ }
+
ret = goodix_power_init(ts);
if (ret) {
dev_err(&client->dev, "GTP power init failed\n");
- goto exit_free_client_data;
+ goto exit_free_io_port;
}
ret = goodix_power_on(ts);
@@ -1783,18 +1806,12 @@
goto exit_deinit_power;
}
- ret = gtp_request_io_port(ts);
- if (ret) {
- dev_err(&client->dev, "GTP request IO port failed.\n");
- goto exit_power_off;
- }
-
gtp_reset_guitar(ts, 20);
ret = gtp_i2c_test(client);
if (ret != 2) {
dev_err(&client->dev, "I2C communication ERROR!\n");
- goto exit_free_io_port;
+ goto exit_power_off;
}
if (pdata->fw_name)
@@ -1900,15 +1917,15 @@
}
exit_free_inputdev:
kfree(ts->config_data);
+exit_power_off:
+ goodix_power_off(ts);
+exit_deinit_power:
+ goodix_power_deinit(ts);
exit_free_io_port:
if (gpio_is_valid(pdata->reset_gpio))
gpio_free(pdata->reset_gpio);
if (gpio_is_valid(pdata->irq_gpio))
gpio_free(pdata->irq_gpio);
-exit_power_off:
- goodix_power_off(ts);
-exit_deinit_power:
- goodix_power_deinit(ts);
exit_free_client_data:
i2c_set_clientdata(client, NULL);
kfree(ts);
@@ -1988,9 +2005,10 @@
Output:
None.
*******************************************************/
-static void goodix_ts_suspend(struct goodix_ts_data *ts)
+static int goodix_ts_suspend(struct device *dev)
{
- int ret = -1, i;
+ struct goodix_ts_data *ts = dev_get_drvdata(dev);
+ int ret = 0, i;
mutex_lock(&ts->lock);
#if GTP_ESD_PROTECT
@@ -2020,6 +2038,8 @@
*/
msleep(58);
mutex_unlock(&ts->lock);
+
+ return ret;
}
/*******************************************************
@@ -2030,9 +2050,10 @@
Output:
None.
*******************************************************/
-static void goodix_ts_resume(struct goodix_ts_data *ts)
+static int goodix_ts_resume(struct device *dev)
{
- int ret = -1;
+ struct goodix_ts_data *ts = dev_get_drvdata(dev);
+ int ret = 0;
mutex_lock(&ts->lock);
ret = gtp_wakeup_sleep(ts);
@@ -2055,6 +2076,8 @@
gtp_esd_switch(ts->client, SWITCH_ON);
#endif
mutex_unlock(&ts->lock);
+
+ return ret;
}
#if defined(CONFIG_FB)
@@ -2070,9 +2093,9 @@
ts && ts->client) {
blank = evdata->data;
if (*blank == FB_BLANK_UNBLANK)
- goodix_ts_resume(ts);
+ goodix_ts_resume(&ts->client->dev);
else if (*blank == FB_BLANK_POWERDOWN)
- goodix_ts_suspend(ts);
+ goodix_ts_suspend(&ts->client->dev);
}
return 0;
@@ -2091,7 +2114,7 @@
struct goodix_ts_data *ts;
ts = container_of(h, struct goodix_ts_data, early_suspend);
- goodix_ts_suspend(ts);
+ goodix_ts_suspend(&ts->client->dev);
return;
}
@@ -2245,6 +2268,9 @@
}
#endif
+static SIMPLE_DEV_PM_OPS(goodix_ts_dev_pm_ops, goodix_ts_suspend,
+ goodix_ts_resume);
+
static const struct i2c_device_id goodix_ts_id[] = {
{ GTP_I2C_NAME, 0 },
{ }
@@ -2267,6 +2293,9 @@
.name = GTP_I2C_NAME,
.owner = THIS_MODULE,
.of_match_table = goodix_match_table,
+#if CONFIG_PM
+ .pm = &goodix_ts_dev_pm_ops,
+#endif
},
};
@@ -2303,7 +2332,7 @@
i2c_del_driver(&goodix_ts_driver);
}
-late_initcall(goodix_ts_init);
+module_init(goodix_ts_init);
module_exit(goodix_ts_exit);
MODULE_DESCRIPTION("GTP Series Driver");
diff --git a/drivers/input/touchscreen/synaptics_fw_update.c b/drivers/input/touchscreen/synaptics_fw_update.c
index 7282c2e..7da0376 100644
--- a/drivers/input/touchscreen/synaptics_fw_update.c
+++ b/drivers/input/touchscreen/synaptics_fw_update.c
@@ -352,7 +352,6 @@
(data->options_firmware_id == (1 << OPTION_BUILD_INFO));
if (img->is_contain_build_info) {
- img->firmware_id = extract_uint(data->firmware_id);
img->package_id = (data->pkg_id_msb << 8) |
data->pkg_id_lsb;
img->package_revision_id = (data->pkg_id_rev_msb << 8) |
@@ -2054,26 +2053,26 @@
__ATTR(fw_name, S_IRUGO | S_IWUSR | S_IWGRP,
fwu_sysfs_image_name_show,
fwu_sysfs_image_name_store),
- __ATTR(force_update_fw, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(force_update_fw, S_IWUSR | S_IWGRP,
+ NULL,
fwu_sysfs_force_reflash_store),
- __ATTR(update_fw, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(update_fw, S_IWUSR | S_IWGRP,
+ NULL,
fwu_sysfs_do_reflash_store),
- __ATTR(writeconfig, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(writeconfig, S_IWUSR | S_IWGRP,
+ NULL,
fwu_sysfs_write_config_store),
- __ATTR(writelockdown, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(writelockdown, S_IWUSR | S_IWGRP,
+ NULL,
fwu_sysfs_write_lockdown_store),
- __ATTR(readconfig, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(readconfig, S_IWUSR | S_IWGRP,
+ NULL,
fwu_sysfs_read_config_store),
- __ATTR(configarea, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(configarea, S_IWUSR | S_IWGRP,
+ NULL,
fwu_sysfs_config_area_store),
- __ATTR(imagesize, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(imagesize, S_IWUSR | S_IWGRP,
+ NULL,
fwu_sysfs_image_size_store),
__ATTR(blocksize, S_IRUGO,
fwu_sysfs_block_size_show,
diff --git a/drivers/input/touchscreen/synaptics_i2c_rmi4.c b/drivers/input/touchscreen/synaptics_i2c_rmi4.c
index d21b6c1..755084c 100644
--- a/drivers/input/touchscreen/synaptics_i2c_rmi4.c
+++ b/drivers/input/touchscreen/synaptics_i2c_rmi4.c
@@ -67,10 +67,10 @@
#define F11_STD_CTRL_LEN 10
#define F11_STD_DATA_LEN 12
-#define NORMAL_OPERATION (0 << 0)
-#define SENSOR_SLEEP (1 << 0)
-#define NO_SLEEP_OFF (0 << 2)
-#define NO_SLEEP_ON (1 << 2)
+#define NORMAL_OPERATION 0
+#define SENSOR_SLEEP 1
+#define NO_SLEEP_OFF 0
+#define NO_SLEEP_ON 1
enum device_status {
STATUS_NO_ERROR = 0x00,
@@ -111,6 +111,13 @@
static int synaptics_rmi4_reset_device(struct synaptics_rmi4_data *rmi4_data);
+static void synaptics_rmi4_sensor_wake(struct synaptics_rmi4_data *rmi4_data);
+
+static void synaptics_rmi4_sensor_sleep(struct synaptics_rmi4_data *rmi4_data);
+
+static int synaptics_rmi4_check_configuration(struct synaptics_rmi4_data
+ *rmi4_data);
+
#ifdef CONFIG_PM
static int synaptics_rmi4_suspend(struct device *dev);
@@ -392,8 +399,8 @@
synaptics_rmi4_full_pm_cycle_show,
synaptics_rmi4_full_pm_cycle_store),
#endif
- __ATTR(reset, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(reset, S_IWUSR | S_IWGRP,
+ NULL,
synaptics_rmi4_f01_reset_store),
__ATTR(productinfo, S_IRUGO,
synaptics_rmi4_f01_productinfo_show,
@@ -600,6 +607,7 @@
if (rmi4_data->button_0d_enabled == input)
return count;
+ mutex_lock(&rmi->support_fn_list_mutex);
if (!list_empty(&rmi->support_fn_list)) {
list_for_each_entry(fhandler, &rmi->support_fn_list, link) {
if (fhandler->fn_number == SYNAPTICS_RMI4_F1A) {
@@ -611,7 +619,7 @@
&intr_enable,
sizeof(intr_enable));
if (retval < 0)
- return retval;
+ goto exit;
if (input == 1)
intr_enable |= fhandler->intr_mask;
@@ -624,14 +632,17 @@
&intr_enable,
sizeof(intr_enable));
if (retval < 0)
- return retval;
+ goto exit;
}
}
}
-
+ mutex_unlock(&rmi->support_fn_list_mutex);
rmi4_data->button_0d_enabled = input;
return count;
+exit:
+ mutex_unlock(&rmi->support_fn_list_mutex);
+ return retval;
}
static ssize_t synaptics_rmi4_flipx_show(struct device *dev,
@@ -1306,6 +1317,7 @@
* Traverse the function handler list and service the source(s)
* of the interrupt accordingly.
*/
+ mutex_lock(&rmi->support_fn_list_mutex);
if (!list_empty(&rmi->support_fn_list)) {
list_for_each_entry(fhandler, &rmi->support_fn_list, link) {
if (fhandler->num_of_data_sources) {
@@ -1317,6 +1329,7 @@
}
}
}
+ mutex_unlock(&rmi->support_fn_list_mutex);
mutex_lock(&exp_fn_list_mutex);
if (!list_empty(&exp_fn_list)) {
@@ -2051,6 +2064,32 @@
return 0;
}
+/*
+* This function checks whether the fhandler already existis in the
+* support_fn_list or not.
+* If it exists then return 1 as found or return 0 as not found.
+*
+* Called by synaptics_rmi4_query_device().
+*/
+static int synaptics_rmi4_check_fn_list(struct synaptics_rmi4_data *rmi4_data,
+ struct synaptics_rmi4_fn *fhandler)
+{
+ int found = 0;
+ struct synaptics_rmi4_fn *new_fhandler;
+ struct synaptics_rmi4_device_info *rmi;
+
+ rmi = &(rmi4_data->rmi4_mod_info);
+
+ mutex_lock(&rmi->support_fn_list_mutex);
+ if (!list_empty(&rmi->support_fn_list))
+ list_for_each_entry(new_fhandler, &rmi->support_fn_list, link)
+ if (new_fhandler->fn_number == fhandler->fn_number)
+ found = 1;
+ mutex_unlock(&rmi->support_fn_list_mutex);
+
+ return found;
+}
+
/**
* synaptics_rmi4_query_device()
*
@@ -2066,7 +2105,7 @@
*/
static int synaptics_rmi4_query_device(struct synaptics_rmi4_data *rmi4_data)
{
- int retval;
+ int retval, found;
unsigned char ii;
unsigned char page_number;
unsigned char intr_count = 0;
@@ -2080,8 +2119,6 @@
rmi = &(rmi4_data->rmi4_mod_info);
- INIT_LIST_HEAD(&rmi->support_fn_list);
-
/* Scan the page description tables of the pages to service */
for (page_number = 0; page_number < PAGES_TO_SERVICE; page_number++) {
for (pdt_entry_addr = PDT_START; pdt_entry_addr > PDT_END;
@@ -2096,7 +2133,7 @@
return retval;
fhandler = NULL;
-
+ found = 0;
if (rmi_fd.fn_number == 0) {
dev_dbg(&rmi4_data->i2c_client->dev,
"%s: Reached end of PDT\n",
@@ -2215,8 +2252,31 @@
intr_count += (rmi_fd.intr_src_count & MASK_3BIT);
if (fhandler && rmi_fd.intr_src_count) {
- list_add_tail(&fhandler->link,
- &rmi->support_fn_list);
+ /* Want to check whether the fhandler already
+ exists in the support_fn_list or not.
+ If not found then add it to the list, otherwise
+ free the memory allocated to it.
+ */
+ found = synaptics_rmi4_check_fn_list(rmi4_data,
+ fhandler);
+
+ if (!found) {
+ mutex_lock(&rmi->support_fn_list_mutex);
+ list_add_tail(&fhandler->link,
+ &rmi->support_fn_list);
+ mutex_unlock(
+ &rmi->support_fn_list_mutex);
+ } else {
+ if (fhandler->fn_number ==
+ SYNAPTICS_RMI4_F1A) {
+ synaptics_rmi4_f1a_kfree(
+ fhandler);
+ } else {
+ kfree(fhandler->data);
+ kfree(fhandler->extra);
+ }
+ kfree(fhandler);
+ }
}
}
}
@@ -2233,20 +2293,25 @@
* Map out the interrupt bit masks for the interrupt sources
* from the registered function handlers.
*/
+ mutex_lock(&rmi->support_fn_list_mutex);
if (!list_empty(&rmi->support_fn_list)) {
list_for_each_entry(fhandler, &rmi->support_fn_list, link)
data_sources += fhandler->num_of_data_sources;
}
+ mutex_unlock(&rmi->support_fn_list_mutex);
+
if (data_sources) {
+ mutex_lock(&rmi->support_fn_list_mutex);
if (!list_empty(&rmi->support_fn_list)) {
list_for_each_entry(fhandler,
&rmi->support_fn_list, link) {
if (fhandler->num_of_data_sources) {
rmi4_data->intr_mask[fhandler->intr_reg_num] |=
- fhandler->intr_mask;
+ fhandler->intr_mask;
}
}
}
+ mutex_unlock(&rmi->support_fn_list_mutex);
}
/* Enable the interrupt sources */
@@ -2851,6 +2916,9 @@
init_waitqueue_head(&rmi4_data->wait);
mutex_init(&(rmi4_data->rmi4_io_ctrl_mutex));
+ INIT_LIST_HEAD(&rmi->support_fn_list);
+ mutex_init(&rmi->support_fn_list_mutex);
+
retval = synaptics_rmi4_query_device(rmi4_data);
if (retval < 0) {
dev_err(&client->dev,
@@ -2904,12 +2972,14 @@
i2c_set_clientdata(client, rmi4_data);
f1a = NULL;
+ mutex_lock(&rmi->support_fn_list_mutex);
if (!list_empty(&rmi->support_fn_list)) {
list_for_each_entry(fhandler, &rmi->support_fn_list, link) {
if (fhandler->fn_number == SYNAPTICS_RMI4_F1A)
f1a = fhandler->data;
}
}
+ mutex_unlock(&rmi->support_fn_list_mutex);
if (f1a) {
for (ii = 0; ii < f1a->valid_button_count; ii++) {
@@ -2987,6 +3057,9 @@
goto err_sysfs;
}
}
+
+ synaptics_rmi4_sensor_wake(rmi4_data);
+
retval = synaptics_rmi4_irq_enable(rmi4_data, true);
if (retval < 0) {
dev_err(&client->dev,
@@ -2995,6 +3068,12 @@
goto err_sysfs;
}
+ retval = synaptics_rmi4_check_configuration(rmi4_data);
+ if (retval < 0) {
+ dev_err(&client->dev, "Failed to check configuration\n");
+ return retval;
+ }
+
return retval;
err_sysfs:
@@ -3013,6 +3092,7 @@
input_unregister_device(rmi4_data->input_dev);
err_register_input:
+ mutex_lock(&rmi->support_fn_list_mutex);
if (!list_empty(&rmi->support_fn_list)) {
list_for_each_entry_safe(fhandler, next_fhandler,
&rmi->support_fn_list, link) {
@@ -3025,6 +3105,7 @@
kfree(fhandler);
}
}
+ mutex_unlock(&rmi->support_fn_list_mutex);
err_free_gpios:
if (gpio_is_valid(rmi4_data->board->reset_gpio))
gpio_free(rmi4_data->board->reset_gpio);
@@ -3080,6 +3161,7 @@
input_unregister_device(rmi4_data->input_dev);
+ mutex_lock(&rmi->support_fn_list_mutex);
if (!list_empty(&rmi->support_fn_list)) {
list_for_each_entry_safe(fhandler, next_fhandler,
&rmi->support_fn_list, link) {
@@ -3092,6 +3174,7 @@
kfree(fhandler);
}
}
+ mutex_unlock(&rmi->support_fn_list_mutex);
if (gpio_is_valid(rmi4_data->board->reset_gpio))
gpio_free(rmi4_data->board->reset_gpio);
@@ -3175,6 +3258,12 @@
return;
}
+ if (device_ctrl.nosleep == NO_SLEEP_OFF &&
+ device_ctrl.sleep_mode == NORMAL_OPERATION) {
+ rmi4_data->sensor_sleep = false;
+ return;
+ }
+
device_ctrl.sleep_mode = NORMAL_OPERATION;
device_ctrl.nosleep = NO_SLEEP_OFF;
@@ -3558,6 +3647,22 @@
static const struct dev_pm_ops synaptics_rmi4_dev_pm_ops = {
};
#endif
+#else
+static void synaptics_rmi4_sensor_wake(struct synaptics_rmi4_data *rmi4_data)
+{
+ return;
+};
+
+static void synaptics_rmi4_sensor_sleep(struct synaptics_rmi4_data *rmi4_data)
+{
+ return;
+};
+
+static int synaptics_rmi4_check_configuration(struct synaptics_rmi4_data
+ *rmi4_data)
+{
+ return 0;
+};
#endif
static const struct i2c_device_id synaptics_rmi4_id_table[] = {
diff --git a/drivers/input/touchscreen/synaptics_i2c_rmi4.h b/drivers/input/touchscreen/synaptics_i2c_rmi4.h
index ef39bb7..df227fb 100644
--- a/drivers/input/touchscreen/synaptics_i2c_rmi4.h
+++ b/drivers/input/touchscreen/synaptics_i2c_rmi4.h
@@ -161,6 +161,7 @@
unsigned char product_id_string[SYNAPTICS_RMI4_PRODUCT_ID_SIZE + 1];
unsigned char build_id[SYNAPTICS_RMI4_BUILD_ID_SIZE];
unsigned char config_id[3];
+ struct mutex support_fn_list_mutex;
struct list_head support_fn_list;
};
@@ -286,14 +287,6 @@
void (*func_attn)(struct synaptics_rmi4_data *rmi4_data,
unsigned char intr_mask));
-static inline ssize_t synaptics_rmi4_show_error(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- dev_warn(dev, "%s Attempted to read from write-only attribute %s\n",
- __func__, attr->attr.name);
- return -EPERM;
-}
-
static inline ssize_t synaptics_rmi4_store_error(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
diff --git a/drivers/input/touchscreen/synaptics_rmi_dev.c b/drivers/input/touchscreen/synaptics_rmi_dev.c
index c60ca23..7abd909 100644
--- a/drivers/input/touchscreen/synaptics_rmi_dev.c
+++ b/drivers/input/touchscreen/synaptics_rmi_dev.c
@@ -73,19 +73,19 @@
};
static struct device_attribute attrs[] = {
- __ATTR(open, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(open, S_IWUSR | S_IWGRP,
+ NULL,
rmidev_sysfs_open_store),
- __ATTR(release, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(release, S_IWUSR | S_IWGRP,
+ NULL,
rmidev_sysfs_release_store),
- __ATTR(address, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(address, S_IWUSR | S_IWGRP,
+ NULL,
rmidev_sysfs_address_store),
- __ATTR(length, S_IRUGO | S_IWUSR | S_IWGRP,
- synaptics_rmi4_show_error,
+ __ATTR(length, S_IWUSR | S_IWGRP,
+ NULL,
rmidev_sysfs_length_store),
- __ATTR(data, (S_IRUGO | S_IWUSR | S_IWGRP),
+ __ATTR(data, (S_IWUSR | S_IWGRP),
rmidev_sysfs_data_show,
rmidev_sysfs_data_store),
};
diff --git a/drivers/leds/leds-qpnp.c b/drivers/leds/leds-qpnp.c
index 8ae5671..7954296 100644
--- a/drivers/leds/leds-qpnp.c
+++ b/drivers/leds/leds-qpnp.c
@@ -2761,7 +2761,7 @@
rc = of_property_read_u32(node, "qcom,duration", &val);
if (!rc)
- led->flash_cfg->duration = (((u8) val) - 10) / 10;
+ led->flash_cfg->duration = (u8)((val - 10) / 10);
else if (rc == -EINVAL)
led->flash_cfg->duration = FLASH_DURATION_200ms;
else
diff --git a/drivers/media/dvb/dvb-core/dmxdev.c b/drivers/media/dvb/dvb-core/dmxdev.c
index a1cac54..937fb8c 100644
--- a/drivers/media/dvb/dvb-core/dmxdev.c
+++ b/drivers/media/dvb/dvb-core/dmxdev.c
@@ -899,7 +899,9 @@
} else {
int i;
+ spin_lock(&dmxdev->dvr_in_lock);
dmxdev->dvr_in_exit = 1;
+ spin_unlock(&dmxdev->dvr_in_lock);
wake_up_all(&dmxdev->dvr_cmd_buffer.queue);
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_buf_mgr.c b/drivers/media/platform/msm/camera_v2/isp/msm_buf_mgr.c
index 2be1f01..dcf3483 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_buf_mgr.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_buf_mgr.c
@@ -122,6 +122,8 @@
{
int i, rc = -1;
struct msm_isp_buffer_mapped_info *mapped_info;
+ struct buffer_cmd *buf_pending = NULL;
+
for (i = 0; i < v4l2_buf->length; i++) {
mapped_info = &buf_info->mapped_info[i];
mapped_info->handle =
@@ -144,6 +146,15 @@
mapped_info->paddr += v4l2_buf->m.planes[i].data_offset;
CDBG("%s: plane: %d addr:%lu\n",
__func__, i, mapped_info->paddr);
+
+ buf_pending = kzalloc(sizeof(struct buffer_cmd), GFP_ATOMIC);
+ if (!buf_pending) {
+ pr_err("No free memory for buf_pending\n");
+ return rc;
+ }
+
+ buf_pending->mapped_info = mapped_info;
+ list_add_tail(&buf_pending->list, &buf_mgr->buffer_q);
}
buf_info->num_planes = v4l2_buf->length;
return 0;
@@ -163,11 +174,26 @@
{
int i;
struct msm_isp_buffer_mapped_info *mapped_info;
+ struct buffer_cmd *buf_pending = NULL;
+
for (i = 0; i < buf_info->num_planes; i++) {
mapped_info = &buf_info->mapped_info[i];
- ion_unmap_iommu(buf_mgr->client, mapped_info->handle,
- buf_mgr->iommu_domain_num, 0);
- ion_free(buf_mgr->client, mapped_info->handle);
+
+ list_for_each_entry(buf_pending, &buf_mgr->buffer_q, list) {
+ if (!buf_pending)
+ break;
+
+ if (buf_pending->mapped_info == mapped_info) {
+ ion_unmap_iommu(buf_mgr->client,
+ mapped_info->handle,
+ buf_mgr->iommu_domain_num, 0);
+ ion_free(buf_mgr->client, mapped_info->handle);
+
+ list_del_init(&buf_pending->list);
+ kfree(buf_pending);
+ break;
+ }
+ }
}
return;
}
@@ -691,6 +717,7 @@
if (!bufq->bufq_handle)
continue;
msm_isp_buf_unprepare(buf_mgr, bufq->bufq_handle);
+
kfree(bufq->bufs);
msm_isp_free_buf_handle(buf_mgr, bufq->bufq_handle);
}
@@ -739,9 +766,10 @@
pr_err("Invalid buffer queue number\n");
return rc;
}
-
CDBG("%s: E\n", __func__);
+
msm_isp_attach_ctx(buf_mgr);
+ INIT_LIST_HEAD(&buf_mgr->buffer_q);
buf_mgr->num_buf_q = num_buf_q;
buf_mgr->bufq =
kzalloc(sizeof(struct msm_isp_bufq) * num_buf_q,
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_buf_mgr.h b/drivers/media/platform/msm/camera_v2/isp/msm_buf_mgr.h
index 6d6ff9d..d8d3ba2 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_buf_mgr.h
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_buf_mgr.h
@@ -44,6 +44,11 @@
struct ion_handle *handle;
};
+struct buffer_cmd {
+ struct list_head list;
+ struct msm_isp_buffer_mapped_info *mapped_info;
+};
+
struct msm_isp_buffer {
/*Common Data structure*/
int num_planes;
@@ -138,6 +143,7 @@
int num_iommu_ctx;
struct device *iommu_ctx[2];
+ struct list_head buffer_q;
};
int msm_isp_create_isp_buf_mgr(struct msm_isp_buf_mgr *buf_mgr,
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c
index 2c5e136..80a0073 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c
@@ -140,6 +140,7 @@
&vfe_vb2_ops, &vfe_layout);
if (rc < 0) {
pr_err("%s: Unable to create buffer manager\n", __func__);
+ msm_sd_unregister(&vfe_dev->subdev);
kfree(vfe_dev);
return -EINVAL;
}
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
index bf906dc..1732c21 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
@@ -629,7 +629,10 @@
msm_camera_io_w_mb(0x0, vfe_dev->vfe_base + 0x1E0);
vfe_dev->axi_data.src_info[VFE_PIX_0].active = 0;
} else if (update_state == DISABLE_CAMIF_IMMEDIATELY) {
- msm_camera_io_w_mb(0x2, vfe_dev->vfe_base + 0x1E0);
+ msm_camera_io_w_mb(0x6, vfe_dev->vfe_base + 0x1E0);
+ vfe_dev->hw_info->vfe_ops.axi_ops.halt(vfe_dev);
+ vfe_dev->hw_info->vfe_ops.core_ops.reset_hw(vfe_dev);
+ vfe_dev->hw_info->vfe_ops.core_ops.init_hw_reg(vfe_dev);
vfe_dev->axi_data.src_info[VFE_PIX_0].active = 0;
}
}
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c
index 3651779..4a3f51b 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c
@@ -875,7 +875,10 @@
msm_camera_io_w_mb(0x0, vfe_dev->vfe_base + 0x2F4);
vfe_dev->axi_data.src_info[VFE_PIX_0].active = 0;
} else if (update_state == DISABLE_CAMIF_IMMEDIATELY) {
- msm_camera_io_w_mb(0x2, vfe_dev->vfe_base + 0x2F4);
+ msm_camera_io_w_mb(0x6, vfe_dev->vfe_base + 0x2F4);
+ vfe_dev->hw_info->vfe_ops.axi_ops.halt(vfe_dev);
+ vfe_dev->hw_info->vfe_ops.core_ops.reset_hw(vfe_dev);
+ vfe_dev->hw_info->vfe_ops.core_ops.init_hw_reg(vfe_dev);
vfe_dev->axi_data.src_info[VFE_PIX_0].active = 0;
}
}
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c
index f098dda..5f3e036 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c
@@ -318,7 +318,8 @@
stream_info->state == PAUSED ||
stream_info->state == RESUME_PENDING ||
stream_info->state == RESUMING) &&
- stream_cfg_cmd->cmd == STOP_STREAM) {
+ (stream_cfg_cmd->cmd == STOP_STREAM ||
+ stream_cfg_cmd->cmd == STOP_IMMEDIATELY)) {
stream_info->state = ACTIVE;
} else {
pr_err("%s: Invalid stream state: %d\n",
@@ -663,7 +664,9 @@
}
}
- if (vfe_dev->axi_data.pipeline_update == DISABLE_CAMIF) {
+ if (vfe_dev->axi_data.pipeline_update == DISABLE_CAMIF ||
+ (vfe_dev->axi_data.pipeline_update ==
+ DISABLE_CAMIF_IMMEDIATELY)) {
vfe_dev->hw_info->vfe_ops.stats_ops.
enable_module(vfe_dev, 0xFF, 0);
vfe_dev->axi_data.pipeline_update = NO_UPDATE;
@@ -874,6 +877,10 @@
(cur_pix_stream_cnt - pix_stream_cnt) == 0 &&
stream_cfg_cmd->cmd == STOP_STREAM)
return DISABLE_CAMIF;
+ else if (cur_pix_stream_cnt &&
+ (cur_pix_stream_cnt - pix_stream_cnt) == 0 &&
+ stream_cfg_cmd->cmd == STOP_IMMEDIATELY)
+ return DISABLE_CAMIF_IMMEDIATELY;
}
return NO_UPDATE;
}
@@ -1162,8 +1169,14 @@
* since for burst case, write masters already skip
* all frames.
*/
+ if (stream_info->stream_src == RDI_INTF_0 ||
+ stream_info->stream_src == RDI_INTF_1 ||
+ stream_info->stream_src == RDI_INTF_2)
+ wait_for_complete = 1;
+ else {
msm_isp_axi_stream_enable_cfg(vfe_dev, stream_info);
stream_info->state = INACTIVE;
+ }
} else {
wait_for_complete = 1;
}
@@ -1179,6 +1192,9 @@
if (camif_update == DISABLE_CAMIF)
vfe_dev->hw_info->vfe_ops.core_ops.
update_camif_state(vfe_dev, DISABLE_CAMIF);
+ else if (camif_update == DISABLE_CAMIF_IMMEDIATELY)
+ vfe_dev->hw_info->vfe_ops.core_ops.
+ update_camif_state(vfe_dev, DISABLE_CAMIF_IMMEDIATELY);
msm_isp_update_camif_output_count(vfe_dev, stream_cfg_cmd);
for (i = 0; i < stream_cfg_cmd->num_streams; i++) {
diff --git a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_common.h b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_common.h
index 04af6b6..634beca 100644
--- a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_common.h
+++ b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_common.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -20,7 +20,7 @@
#endif
#define JPEG_PR_ERR pr_err
-#define JPEG_DBG_HIGH pr_err
+#define JPEG_DBG_HIGH pr_debug
enum JPEG_MODE {
JPEG_MODE_DISABLE,
diff --git a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_hw.c b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_hw.c
index 0a0fa04..44a4014 100644
--- a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_hw.c
+++ b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_hw.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -216,15 +216,15 @@
if (pingpong_index == 0) {
hw_cmd_p = &hw_cmd_we_ping_update[0];
hw_cmd_p->data = p_input->y_buffer_addr;
- JPEG_PR_ERR("%s Output pln0 buffer address is %x\n", __func__,
+ JPEG_DBG_HIGH("%s Output pln0 buffer address is %x\n", __func__,
p_input->y_buffer_addr);
msm_jpeg_hw_write(hw_cmd_p++, base);
hw_cmd_p->data = p_input->cbcr_buffer_addr;
- JPEG_PR_ERR("%s Output pln1 buffer address is %x\n", __func__,
+ JPEG_DBG_HIGH("%s Output pln1 buffer address is %x\n", __func__,
p_input->cbcr_buffer_addr);
msm_jpeg_hw_write(hw_cmd_p++, base);
hw_cmd_p->data = p_input->pln2_addr;
- JPEG_PR_ERR("%s Output pln2 buffer address is %x\n", __func__,
+ JPEG_DBG_HIGH("%s Output pln2 buffer address is %x\n", __func__,
p_input->pln2_addr);
msm_jpeg_hw_write(hw_cmd_p++, base);
}
@@ -337,6 +337,11 @@
__LINE__, hw_cmd_p->offset, max_size);
return -EFAULT;
}
+ if (hw_cmd_p->offset & 0x3) {
+ JPEG_PR_ERR("%s:%d] %d Invalid alignment\n", __func__,
+ __LINE__, hw_cmd_p->offset);
+ return -EFAULT;
+ }
switch (hw_cmd_p->type) {
case MSM_JPEG_HW_CMD_TYPE_READ:
diff --git a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c
index d6fa2b0..407b81f 100644
--- a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c
+++ b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.c
@@ -28,6 +28,24 @@
#include "msm_jpeg_common.h"
#include "msm_jpeg_hw.h"
+int msm_jpeg_platform_set_clk_rate(struct msm_jpeg_device *pgmn_dev,
+ long clk_rate)
+{
+ int rc = 0;
+ struct clk *jpeg_clk;
+
+ jpeg_clk = clk_get(&pgmn_dev->pdev->dev, "core_clk");
+ if (IS_ERR(jpeg_clk)) {
+ JPEG_PR_ERR("%s get failed\n", "core_clk");
+ rc = PTR_ERR(jpeg_clk);
+ return rc;
+ }
+
+ rc = clk_set_rate(jpeg_clk, clk_rate);
+
+ return rc;
+}
+
void msm_jpeg_platform_p2v(struct msm_jpeg_device *pgmn_dev, struct file *file,
struct ion_handle **ionhandle, int domain_num)
{
@@ -135,8 +153,8 @@
{
.src = MSM_BUS_MASTER_JPEG,
.dst = MSM_BUS_SLAVE_EBI_CH0,
- .ab = JPEG_CLK_RATE * 2.5,
- .ib = JPEG_CLK_RATE * 2.5,
+ .ab = JPEG_MAX_CLK_RATE * 2.5,
+ .ib = JPEG_MAX_CLK_RATE * 2.5,
},
};
diff --git a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.h b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.h
index a14b8ee..7be9e19 100644
--- a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.h
+++ b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_platform.h
@@ -20,7 +20,10 @@
#include <mach/iommu.h>
#include "msm_jpeg_sync.h"
#define JPEG_CLK_RATE 266670000
+#define JPEG_MAX_CLK_RATE 320000000
+int msm_jpeg_platform_set_clk_rate(struct msm_jpeg_device *pgmn_dev,
+ long clk_rate);
void msm_jpeg_platform_p2v(struct msm_jpeg_device *pgmn_dev, struct file *file,
struct ion_handle **ionhandle, int domain_num);
uint32_t msm_jpeg_platform_v2p(struct msm_jpeg_device *pgmn_dev, int fd,
diff --git a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_sync.c b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_sync.c
index 80ff9e5..5cc51ff 100644
--- a/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_sync.c
+++ b/drivers/media/platform/msm/camera_v2/jpeg_10/msm_jpeg_sync.c
@@ -669,6 +669,8 @@
JPEG_PR_ERR("%s:%d] failed\n", __func__, __LINE__);
return -EFAULT;
}
+ } else {
+ return is_copy_to_user;
}
return 0;
@@ -804,6 +806,36 @@
return 0;
}
+int msm_jpeg_ioctl_set_clk_rate(struct msm_jpeg_device *pgmn_dev,
+ unsigned long arg)
+{
+ long clk_rate;
+ int rc;
+
+ if ((pgmn_dev->state != MSM_JPEG_INIT) &&
+ (pgmn_dev->state != MSM_JPEG_RESET)) {
+ JPEG_PR_ERR("%s:%d] failed\n", __func__, __LINE__);
+ return -EFAULT;
+ }
+ if (get_user(clk_rate, (long __user *)arg)) {
+ JPEG_PR_ERR("%s:%d] failed\n", __func__, __LINE__);
+ return -EFAULT;
+ }
+ JPEG_DBG("%s:%d] Requested clk rate %ld\n", __func__, __LINE__,
+ clk_rate);
+ if (clk_rate < 0) {
+ JPEG_PR_ERR("%s:%d] failed\n", __func__, __LINE__);
+ return -EFAULT;
+ }
+ rc = msm_jpeg_platform_set_clk_rate(pgmn_dev, clk_rate);
+ if (rc < 0) {
+ JPEG_PR_ERR("%s: clk failed rc = %d\n", __func__, rc);
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
long __msm_jpeg_ioctl(struct msm_jpeg_device *pgmn_dev,
unsigned int cmd, unsigned long arg)
{
@@ -873,6 +905,9 @@
rc = msm_jpeg_ioctl_test_dump_region(pgmn_dev, arg);
break;
+ case MSM_JPEG_IOCTL_SET_CLK_RATE:
+ rc = msm_jpeg_ioctl_set_clk_rate(pgmn_dev, arg);
+ break;
default:
JPEG_PR_ERR(KERN_INFO "%s:%d] cmd = %d not supported\n",
__func__, __LINE__, _IOC_NR(cmd));
diff --git a/drivers/media/platform/msm/camera_v2/msm.c b/drivers/media/platform/msm/camera_v2/msm.c
index efa3ad0..8a2c8e5 100644
--- a/drivers/media/platform/msm/camera_v2/msm.c
+++ b/drivers/media/platform/msm/camera_v2/msm.c
@@ -438,7 +438,7 @@
static inline int __msm_destroy_session_streams(void *d1, void *d2)
{
struct msm_stream *stream = d1;
-
+ pr_err("%s: Destroyed here due to list is not empty\n", __func__);
INIT_LIST_HEAD(&stream->queued_list);
return 0;
}
@@ -1001,8 +1001,10 @@
video_set_drvdata(pvdev->vdev, pvdev);
msm_session_q = kzalloc(sizeof(*msm_session_q), GFP_KERNEL);
- if (WARN_ON(!msm_session_q))
- goto v4l2_fail;
+ if (WARN_ON(!msm_session_q)) {
+ rc = -ENOMEM;
+ goto session_fail;
+ }
msm_init_queue(msm_session_q);
spin_lock_init(&msm_eventq_lock);
@@ -1010,6 +1012,8 @@
INIT_LIST_HEAD(&ordered_sd_list);
goto probe_end;
+session_fail:
+ video_unregister_device(pvdev->vdev);
v4l2_fail:
v4l2_device_unregister(pvdev->vdev->v4l2_dev);
register_fail:
diff --git a/drivers/media/platform/msm/camera_v2/msm_buf_mgr/msm_generic_buf_mgr.c b/drivers/media/platform/msm/camera_v2/msm_buf_mgr/msm_generic_buf_mgr.c
index 154ee87..7520ce5 100644
--- a/drivers/media/platform/msm/camera_v2/msm_buf_mgr/msm_generic_buf_mgr.c
+++ b/drivers/media/platform/msm/camera_v2/msm_buf_mgr/msm_generic_buf_mgr.c
@@ -100,6 +100,24 @@
return ret;
}
+static void msm_buf_mngr_sd_shutdown(struct msm_buf_mngr_device *buf_mngr_dev)
+{
+ unsigned long flags;
+ struct msm_get_bufs *bufs, *save;
+
+ spin_lock_irqsave(&buf_mngr_dev->buf_q_spinlock, flags);
+ if (!list_empty(&buf_mngr_dev->buf_qhead)) {
+ list_for_each_entry_safe(bufs,
+ save, &buf_mngr_dev->buf_qhead, entry) {
+ pr_err("%s: Delete invalid bufs =%x\n", __func__,
+ (unsigned int)bufs);
+ list_del_init(&bufs->entry);
+ kfree(bufs);
+ }
+ }
+ spin_unlock_irqrestore(&buf_mngr_dev->buf_q_spinlock, flags);
+}
+
static long msm_buf_mngr_subdev_ioctl(struct v4l2_subdev *sd,
unsigned int cmd, void *arg)
{
@@ -123,6 +141,9 @@
case VIDIOC_MSM_BUF_MNGR_PUT_BUF:
rc = msm_buf_mngr_put_buf(buf_mngr_dev, argp);
break;
+ case MSM_SD_SHUTDOWN:
+ msm_buf_mngr_sd_shutdown(buf_mngr_dev);
+ break;
default:
return -ENOIOCTLCMD;
}
diff --git a/drivers/media/platform/msm/camera_v2/msm_vb2/msm_vb2.c b/drivers/media/platform/msm/camera_v2/msm_vb2/msm_vb2.c
index 8fa8f8d..0fbaeca 100644
--- a/drivers/media/platform/msm/camera_v2/msm_vb2/msm_vb2.c
+++ b/drivers/media/platform/msm/camera_v2/msm_vb2/msm_vb2.c
@@ -251,6 +251,7 @@
unsigned long flags;
struct msm_vb2_buffer *msm_vb2;
struct msm_stream *stream;
+ struct vb2_buffer *vb2_buf = NULL;
int rc = 0;
stream = msm_get_stream(session_id, stream_id);
@@ -258,6 +259,18 @@
return 0;
spin_lock_irqsave(&stream->stream_lock, flags);
if (vb) {
+ list_for_each_entry(msm_vb2, &(stream->queued_list), list) {
+ vb2_buf = &(msm_vb2->vb2_buf);
+ if (vb2_buf == vb)
+ break;
+ }
+ if (vb2_buf != vb) {
+ pr_err("%s:%d VB buffer is INVALID vb=%x, ses_id=%d, str_id=%d\n",
+ __func__, __LINE__, (unsigned int)vb,
+ session_id, stream_id);
+ rc = -EINVAL;
+ goto out;
+ }
msm_vb2 =
container_of(vb, struct msm_vb2_buffer, vb2_buf);
/* put buf before buf done */
@@ -268,10 +281,11 @@
} else
rc = -EINVAL;
} else {
- pr_err("%s: VB buffer is null\n", __func__);
+ pr_err("%s:%d VB buffer is NULL for ses_id=%d, str_id=%d\n",
+ __func__, __LINE__, session_id, stream_id);
rc = -EINVAL;
}
-
+out:
spin_unlock_irqrestore(&stream->stream_lock, flags);
return rc;
}
diff --git a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c
index 63973b4..532bebc 100644
--- a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c
+++ b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c
@@ -57,14 +57,12 @@
};
struct msm_cpp_timer_t {
- uint8_t used;
+ atomic_t used;
struct msm_cpp_timer_data_t data;
struct timer_list cpp_timer;
};
-struct msm_cpp_timer_t cpp_timers[2];
-static int del_timer_idx;
-static int set_timer_idx;
+struct msm_cpp_timer_t cpp_timer;
/* dump the frame command before writing to the hardware */
#define MSM_CPP_DUMP_FRM_CMD 0
@@ -596,24 +594,20 @@
if (msg_id == MSM_CPP_MSG_ID_FRAME_ACK) {
CPP_DBG("Frame done!!\n");
/* delete CPP timer */
- CPP_DBG("delete timer %d.\n",
- del_timer_idx);
- timer = &cpp_timers[del_timer_idx];
+ CPP_DBG("delete timer.\n");
+ timer = &cpp_timer;
+ atomic_set(&timer->used, 0);
del_timer(&timer->cpp_timer);
- timer->used = 0;
timer->data.processed_frame = NULL;
- del_timer_idx = 1 - del_timer_idx;
msm_cpp_notify_frame_done(cpp_dev);
} else if (msg_id ==
MSM_CPP_MSG_ID_FRAME_NACK) {
pr_err("NACK error from hw!!\n");
- CPP_DBG("delete timer %d.\n",
- del_timer_idx);
- timer = &cpp_timers[del_timer_idx];
+ CPP_DBG("delete timer.\n");
+ timer = &cpp_timer;
+ atomic_set(&timer->used, 0);
del_timer(&timer->cpp_timer);
- timer->used = 0;
timer->data.processed_frame = NULL;
- del_timer_idx = 1 - del_timer_idx;
msm_cpp_notify_frame_done(cpp_dev);
}
i += cmd_len + 2;
@@ -1077,97 +1071,62 @@
{
int ret;
uint32_t i = 0;
- struct msm_cpp_frame_info_t *this_frame =
- cpp_timers[del_timer_idx].data.processed_frame;
- struct msm_cpp_frame_info_t *second_frame = NULL;
+ struct msm_cpp_frame_info_t *this_frame = NULL;
- pr_err("cpp_timer_callback called idx:%d. (jiffies=%lu)\n",
- del_timer_idx, jiffies);
- if (!work || !this_frame) {
- pr_err("Invalid work:%p, this_frame:%p, del_idx:%d\n",
- work, this_frame, del_timer_idx);
+ pr_err("cpp_timer_callback called. (jiffies=%lu)\n",
+ jiffies);
+ if (!work) {
+ pr_err("Invalid work:%p\n", work);
return;
}
- pr_err("fatal: cpp_timer expired for identity=0x%x, frame_id=%03d",
- this_frame->identity, this_frame->frame_id);
- cpp_timers[del_timer_idx].used = 0;
- cpp_timers[del_timer_idx].data.processed_frame = NULL;
- del_timer_idx = 1 - del_timer_idx;
-
- if (cpp_timers[del_timer_idx].used == 1) {
- pr_err("deleting cpp_timer %d.\n", del_timer_idx);
- del_timer(&cpp_timers[del_timer_idx].cpp_timer);
- cpp_timers[del_timer_idx].used = 0;
- second_frame = cpp_timers[del_timer_idx].data.processed_frame;
- cpp_timers[del_timer_idx].data.processed_frame = NULL;
- del_timer_idx = 1 - del_timer_idx;
+ if (!atomic_read(&cpp_timer.used)) {
+ pr_err("Delayed trigger, IRQ serviced\n");
+ return;
}
- disable_irq(cpp_timers[del_timer_idx].data.cpp_dev->irq->start);
+ disable_irq(cpp_timer.data.cpp_dev->irq->start);
pr_err("Reloading firmware\n");
- cpp_load_fw(cpp_timers[del_timer_idx].data.cpp_dev, NULL);
+ cpp_load_fw(cpp_timer.data.cpp_dev, NULL);
pr_err("Firmware loading done\n");
- enable_irq(cpp_timers[del_timer_idx].data.cpp_dev->irq->start);
- msm_camera_io_w_mb(0x8, cpp_timers[del_timer_idx].data.cpp_dev->base +
+ enable_irq(cpp_timer.data.cpp_dev->irq->start);
+ msm_camera_io_w_mb(0x8, cpp_timer.data.cpp_dev->base +
MSM_CPP_MICRO_IRQGEN_MASK);
msm_camera_io_w_mb(0xFFFF,
- cpp_timers[del_timer_idx].data.cpp_dev->base +
+ cpp_timer.data.cpp_dev->base +
MSM_CPP_MICRO_IRQGEN_CLR);
- cpp_timers[set_timer_idx].data.processed_frame = this_frame;
- cpp_timers[set_timer_idx].used = 1;
- pr_err("ReInstalling cpp_timer %d\n", set_timer_idx);
- setup_timer(&cpp_timers[set_timer_idx].cpp_timer, cpp_timer_callback,
- (unsigned long)&cpp_timers[0]);
+ if (!atomic_read(&cpp_timer.used)) {
+ pr_err("Delayed trigger, IRQ serviced\n");
+ return;
+ }
+
+ this_frame = cpp_timer.data.processed_frame;
+ pr_err("ReInstalling cpp_timer\n");
+ setup_timer(&cpp_timer.cpp_timer, cpp_timer_callback,
+ (unsigned long)&cpp_timer);
pr_err("Starting timer to fire in %d ms. (jiffies=%lu)\n",
CPP_CMD_TIMEOUT_MS, jiffies);
- ret = mod_timer(&cpp_timers[set_timer_idx].cpp_timer,
+ ret = mod_timer(&cpp_timer.cpp_timer,
jiffies + msecs_to_jiffies(CPP_CMD_TIMEOUT_MS));
if (ret)
pr_err("error in mod_timer\n");
- set_timer_idx = 1 - set_timer_idx;
- pr_err("Rescheduling for identity=0x%x, frame_id=%03d",
+ pr_err("Rescheduling for identity=0x%x, frame_id=%03d\n",
this_frame->identity, this_frame->frame_id);
- msm_cpp_write(0x6, cpp_timers[set_timer_idx].data.cpp_dev->base);
+ msm_cpp_write(0x6, cpp_timer.data.cpp_dev->base);
msm_cpp_dump_frame_cmd(this_frame->cpp_cmd_msg,
this_frame->msg_len);
for (i = 0; i < this_frame->msg_len; i++)
msm_cpp_write(this_frame->cpp_cmd_msg[i],
- cpp_timers[set_timer_idx].data.cpp_dev->base);
-
-
- if (second_frame != NULL) {
- cpp_timers[set_timer_idx].data.processed_frame = second_frame;
- cpp_timers[set_timer_idx].used = 1;
- pr_err("ReInstalling cpp_timer %d\n", set_timer_idx);
- setup_timer(&cpp_timers[set_timer_idx].cpp_timer,
- cpp_timer_callback, (unsigned long)&cpp_timers[0]);
- pr_err("Starting timer to fire in %d ms. (jiffies=%lu)\n",
- CPP_CMD_TIMEOUT_MS, jiffies);
- ret = mod_timer(&cpp_timers[set_timer_idx].cpp_timer,
- jiffies + msecs_to_jiffies(CPP_CMD_TIMEOUT_MS));
- if (ret)
- pr_err("error in mod_timer\n");
-
- set_timer_idx = 1 - set_timer_idx;
- pr_err("Rescheduling for identity=0x%x, frame_id=%03d",
- second_frame->identity, second_frame->frame_id);
- msm_cpp_write(0x6,
- cpp_timers[set_timer_idx].data.cpp_dev->base);
- msm_cpp_dump_frame_cmd(second_frame->cpp_cmd_msg,
- second_frame->msg_len);
- for (i = 0; i < second_frame->msg_len; i++)
- msm_cpp_write(second_frame->cpp_cmd_msg[i],
- cpp_timers[set_timer_idx].data.cpp_dev->base);
- }
+ cpp_timer.data.cpp_dev->base);
+ return;
}
void cpp_timer_callback(unsigned long data)
{
struct msm_cpp_work_t *work =
- cpp_timers[set_timer_idx].data.cpp_dev->work;
- queue_work(cpp_timers[set_timer_idx].data.cpp_dev->timer_wq,
+ cpp_timer.data.cpp_dev->work;
+ queue_work(cpp_timer.data.cpp_dev->timer_wq,
(struct work_struct *)work);
}
@@ -1184,21 +1143,19 @@
msm_enqueue(&cpp_dev->processing_q,
&frame_qcmd->list_frame);
- cpp_timers[set_timer_idx].data.processed_frame = process_frame;
- cpp_timers[set_timer_idx].used = 1;
+ cpp_timer.data.processed_frame = process_frame;
+ atomic_set(&cpp_timer.used, 1);
/* install timer for cpp timeout */
- CPP_DBG("Installing cpp_timer %d\n", set_timer_idx);
- setup_timer(&cpp_timers[set_timer_idx].cpp_timer,
- cpp_timer_callback, (unsigned long)&cpp_timers[0]);
+ CPP_DBG("Installing cpp_timer\n");
+ setup_timer(&cpp_timer.cpp_timer,
+ cpp_timer_callback, (unsigned long)&cpp_timer);
CPP_DBG("Starting timer to fire in %d ms. (jiffies=%lu)\n",
CPP_CMD_TIMEOUT_MS, jiffies);
- ret = mod_timer(&cpp_timers[set_timer_idx].cpp_timer,
+ ret = mod_timer(&cpp_timer.cpp_timer,
jiffies + msecs_to_jiffies(CPP_CMD_TIMEOUT_MS));
if (ret)
pr_err("error in mod_timer\n");
- set_timer_idx = 1 - set_timer_idx;
-
msm_cpp_write(0x6, cpp_dev->base);
msm_cpp_dump_frame_cmd(process_frame->cpp_cmd_msg,
process_frame->msg_len);
@@ -1888,13 +1845,16 @@
cpp_dev->timer_wq = create_workqueue("msm_cpp_workqueue");
cpp_dev->work = kmalloc(sizeof(struct msm_cpp_work_t),
GFP_KERNEL);
+ if (!cpp_dev->work) {
+ pr_err("cpp_dev->work is NULL\n");
+ rc = -ENOMEM;
+ goto ERROR3;
+ }
INIT_WORK((struct work_struct *)cpp_dev->work, msm_cpp_do_timeout_work);
cpp_dev->cpp_open_cnt = 0;
cpp_dev->is_firmware_loaded = 0;
- cpp_timers[0].data.cpp_dev = cpp_dev;
- cpp_timers[1].data.cpp_dev = cpp_dev;
- cpp_timers[0].used = 0;
- cpp_timers[1].used = 0;
+ cpp_timer.data.cpp_dev = cpp_dev;
+ atomic_set(&cpp_timer.used, 0);
cpp_dev->fw_name_bin = NULL;
return rc;
ERROR3:
diff --git a/drivers/media/platform/msm/camera_v2/sensor/eeprom/msm_eeprom.c b/drivers/media/platform/msm/camera_v2/sensor/eeprom/msm_eeprom.c
index 45db19c..69c1faa 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/eeprom/msm_eeprom.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/eeprom/msm_eeprom.c
@@ -809,6 +809,7 @@
e_ctrl->is_supported = 0;
if (!of_node) {
pr_err("%s dev.of_node NULL\n", __func__);
+ kfree(e_ctrl);
return -EINVAL;
}
@@ -817,6 +818,7 @@
CDBG("cell-index %d, rc %d\n", pdev->id, rc);
if (rc < 0) {
pr_err("failed rc %d\n", rc);
+ kfree(e_ctrl);
return rc;
}
e_ctrl->subdev_id = pdev->id;
@@ -826,12 +828,14 @@
CDBG("qcom,cci-master %d, rc %d\n", e_ctrl->cci_master, rc);
if (rc < 0) {
pr_err("%s failed rc %d\n", __func__, rc);
+ kfree(e_ctrl);
return rc;
}
rc = of_property_read_u32(of_node, "qcom,slave-addr",
&temp);
if (rc < 0) {
pr_err("%s failed rc %d\n", __func__, rc);
+ kfree(e_ctrl);
return rc;
}
@@ -844,6 +848,7 @@
struct msm_camera_cci_client), GFP_KERNEL);
if (!e_ctrl->i2c_client.cci_client) {
pr_err("%s failed no memory\n", __func__);
+ kfree(e_ctrl);
return -ENOMEM;
}
@@ -936,6 +941,7 @@
kfree(e_ctrl->eboard_info);
cciclient_free:
kfree(e_ctrl->i2c_client.cci_client);
+ kfree(e_ctrl);
return rc;
}
diff --git a/drivers/media/platform/msm/camera_v2/sensor/flash/msm_led_flash.h b/drivers/media/platform/msm/camera_v2/sensor/flash/msm_led_flash.h
index 9f3a81c..a4d7f15 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/flash/msm_led_flash.h
+++ b/drivers/media/platform/msm/camera_v2/sensor/flash/msm_led_flash.h
@@ -53,9 +53,11 @@
const char *flash_trigger_name[MAX_LED_TRIGGERS];
struct led_trigger *flash_trigger[MAX_LED_TRIGGERS];
uint32_t flash_op_current[MAX_LED_TRIGGERS];
+ uint32_t flash_max_current[MAX_LED_TRIGGERS];
const char *torch_trigger_name;
struct led_trigger *torch_trigger;
uint32_t torch_op_current;
+ uint32_t torch_max_current;
void *data;
uint32_t num_sources;
enum msm_camera_device_type_t flash_device_type;
diff --git a/drivers/media/platform/msm/camera_v2/sensor/flash/msm_led_trigger.c b/drivers/media/platform/msm/camera_v2/sensor/flash/msm_led_trigger.c
index 01d2c13..699142a 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/flash/msm_led_trigger.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/flash/msm_led_trigger.c
@@ -51,6 +51,7 @@
int rc = 0;
struct msm_camera_led_cfg_t *cfg = (struct msm_camera_led_cfg_t *)data;
uint32_t i;
+ uint32_t curr_l, max_curr_l;
CDBG("called led_state %d\n", cfg->cfgtype);
if (!fctrl) {
@@ -68,18 +69,38 @@
break;
case MSM_CAMERA_LED_LOW:
- if (fctrl->torch_trigger)
+ if (fctrl->torch_trigger) {
+ max_curr_l = fctrl->torch_max_current;
+ if (cfg->led_current > 0 &&
+ cfg->led_current < max_curr_l) {
+ curr_l = cfg->led_current;
+ } else {
+ curr_l = fctrl->torch_op_current;
+ pr_err("LED current clamped to %d\n",
+ curr_l);
+ }
led_trigger_event(fctrl->torch_trigger,
- fctrl->torch_op_current);
+ curr_l);
+ }
break;
case MSM_CAMERA_LED_HIGH:
if (fctrl->torch_trigger)
led_trigger_event(fctrl->torch_trigger, 0);
for (i = 0; i < fctrl->num_sources; i++)
- if (fctrl->flash_trigger[i])
+ if (fctrl->flash_trigger[i]) {
+ max_curr_l = fctrl->flash_max_current[i];
+ if (cfg->led_current > 0 &&
+ cfg->led_current < max_curr_l) {
+ curr_l = cfg->led_current;
+ } else {
+ curr_l = fctrl->flash_op_current[i];
+ pr_err("LED current clamped to %d\n",
+ curr_l);
+ }
led_trigger_event(fctrl->flash_trigger[i],
- fctrl->flash_op_current[i]);
+ curr_l);
+ }
break;
case MSM_CAMERA_LED_INIT:
@@ -116,7 +137,7 @@
static int32_t msm_led_trigger_probe(struct platform_device *pdev)
{
- int32_t rc = 0, i = 0;
+ int32_t rc = 0, rc_1 = 0, i = 0;
struct device_node *of_node = pdev->dev.of_node;
struct device_node *flash_src_node = NULL;
uint32_t count = 0;
@@ -181,7 +202,10 @@
rc = of_property_read_u32(flash_src_node,
"qcom,current",
&fctrl.flash_op_current[i]);
- if (rc < 0) {
+ rc_1 = of_property_read_u32(flash_src_node,
+ "qcom,max-current",
+ &fctrl.flash_max_current[i]);
+ if ((rc < 0) || (rc_1 < 0)) {
pr_err("current: read failed\n");
of_node_put(flash_src_node);
continue;
@@ -229,7 +253,11 @@
rc = of_property_read_u32(flash_src_node,
"qcom,current",
&fctrl.torch_op_current);
- if (rc < 0) {
+ rc_1 = of_property_read_u32(flash_src_node,
+ "qcom,max-current",
+ &fctrl.torch_max_current);
+
+ if ((rc < 0) || (rc_1 < 0)) {
pr_err("current: read failed\n");
goto torch_failed;
}
diff --git a/drivers/media/platform/msm/camera_v2/sensor/io/msm_camera_dt_util.c b/drivers/media/platform/msm/camera_v2/sensor/io/msm_camera_dt_util.c
index 484dd69..336c922 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/io/msm_camera_dt_util.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/io/msm_camera_dt_util.c
@@ -669,7 +669,9 @@
}
gpio_set_value_cansleep(
ctrl->gpio_conf->gpio_num_info->gpio_num
- [power_setting->seq_val], GPIOF_OUT_INIT_LOW);
+ [power_setting->seq_val],
+ ctrl->gpio_conf->gpio_num_info->gpio_num
+ [power_setting->config_val]);
break;
case SENSOR_VREG:
if (power_setting->seq_val >= CAM_VREG_MAX) {
diff --git a/drivers/media/platform/msm/camera_v2/sensor/msm_sensor.c b/drivers/media/platform/msm/camera_v2/sensor/msm_sensor.c
index 0083378..03145c8 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/msm_sensor.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/msm_sensor.c
@@ -1797,6 +1797,8 @@
(struct msm_sensor_ctrl_t *)data;
struct msm_camera_cci_client *cci_client = NULL;
uint32_t session_id;
+ unsigned long mount_pos;
+
s_ctrl->pdev = pdev;
s_ctrl->dev = &pdev->dev;
CDBG("%s called data %p\n", __func__, data);
@@ -1862,6 +1864,11 @@
s_ctrl->msm_sd.sd.entity.group_id = MSM_CAMERA_SUBDEV_SENSOR;
s_ctrl->msm_sd.sd.entity.name =
s_ctrl->msm_sd.sd.name;
+ mount_pos = s_ctrl->sensordata->sensor_init_params->position;
+ mount_pos = mount_pos << 8;
+ mount_pos = mount_pos |
+ (s_ctrl->sensordata->sensor_init_params->sensor_mount_angle / 90);
+ s_ctrl->msm_sd.sd.entity.flags = mount_pos;
rc = camera_init_v4l2(&s_ctrl->pdev->dev, &session_id);
CDBG("%s rc %d session_id %d\n", __func__, rc, session_id);
@@ -1880,6 +1887,8 @@
{
int rc = 0;
uint32_t session_id;
+ unsigned long mount_pos;
+
CDBG("%s %s_i2c_probe called\n", __func__, client->name);
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
pr_err("%s %s i2c_check_functionality failed\n",
@@ -1976,6 +1985,12 @@
s_ctrl->msm_sd.sd.entity.name =
s_ctrl->msm_sd.sd.name;
+ mount_pos = s_ctrl->sensordata->sensor_init_params->position;
+ mount_pos = mount_pos << 8;
+ mount_pos = mount_pos |
+ (s_ctrl->sensordata->sensor_init_params->sensor_mount_angle / 90);
+ s_ctrl->msm_sd.sd.entity.flags = mount_pos;
+
rc = camera_init_v4l2(&s_ctrl->sensor_i2c_client->client->dev,
&session_id);
CDBG("%s rc %d session_id %d\n", __func__, rc, session_id);
diff --git a/drivers/media/platform/msm/camera_v2/sensor/sp1628.c b/drivers/media/platform/msm/camera_v2/sensor/sp1628.c
old mode 100644
new mode 100755
index 82e4b7c..9a422c0
--- a/drivers/media/platform/msm/camera_v2/sensor/sp1628.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/sp1628.c
@@ -866,6 +866,42 @@
}
break;
}
+ case CFG_SET_SATURATION: {
+
+ break;
+ }
+ case CFG_SET_CONTRAST: {
+
+ break;
+ }
+ case CFG_SET_SHARPNESS: {
+
+ break;
+ }
+ case CFG_SET_ISO: {
+
+ break;
+ }
+ case CFG_SET_EXPOSURE_COMPENSATION: {
+
+ break;
+ }
+ case CFG_SET_EFFECT: {
+
+ break;
+ }
+ case CFG_SET_ANTIBANDING: {
+
+ break;
+ }
+ case CFG_SET_BESTSHOT_MODE: {
+
+ break;
+ }
+ case CFG_SET_WHITE_BALANCE: {
+
+ break;
+ }
default:
rc = -EFAULT;
break;
diff --git a/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.c b/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.c
index d3b9c0a..5694658 100644
--- a/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.c
+++ b/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.c
@@ -1933,7 +1933,7 @@
spin_lock(&feed_data->video_buffer_lock);
if (feed_data->video_buffer == NULL) {
- MPQ_DVB_ERR_PRINT(
+ MPQ_DVB_DBG_PRINT(
"%s: video_buffer released\n",
__func__);
spin_unlock(&feed_data->video_buffer_lock);
@@ -2328,7 +2328,7 @@
stream_buffer = feed_data->video_buffer;
if (stream_buffer == NULL) {
- MPQ_DVB_ERR_PRINT("%s: video_buffer released\n", __func__);
+ MPQ_DVB_DBG_PRINT("%s: video_buffer released\n", __func__);
spin_unlock(&feed_data->video_buffer_lock);
return;
}
@@ -2405,7 +2405,7 @@
stream_buffer = feed_data->video_buffer;
if (stream_buffer == NULL) {
- MPQ_DVB_ERR_PRINT("%s: video_buffer released\n", __func__);
+ MPQ_DVB_DBG_PRINT("%s: video_buffer released\n", __func__);
spin_unlock(&feed_data->video_buffer_lock);
return;
}
@@ -2495,7 +2495,7 @@
stream_buffer = feed_data->video_buffer;
if (stream_buffer == NULL) {
- MPQ_DVB_ERR_PRINT(
+ MPQ_DVB_DBG_PRINT(
"%s: video_buffer released\n",
__func__);
spin_unlock(&feed_data->video_buffer_lock);
@@ -2792,7 +2792,8 @@
&(meta_data.info.framing.pts_dts_info));
mpq_dmx_save_pts_dts(feed_data);
- packet.raw_data_len = feed_data->pending_pattern_len;
+ packet.raw_data_len = feed_data->pending_pattern_len -
+ framing_res.info[i].used_prefix_size;
packet.raw_data_offset = feed_data->frame_offset;
meta_data.info.framing.pattern_type =
feed_data->last_framing_match_type;
@@ -2835,11 +2836,51 @@
feed->data_ready_cb.ts(&feed->feed.ts, &data);
- feed_data->pending_pattern_len = 0;
mpq_streambuffer_get_data_rw_offset(
feed_data->video_buffer,
NULL,
&feed_data->frame_offset);
+
+ /*
+ * In linear buffers, after writing the packet
+ * we switched over to a new linear buffer for the new
+ * frame. In that case, we should re-write the prefix
+ * of the existing frame if any exists.
+ */
+ if ((MPQ_STREAMBUFFER_BUFFER_MODE_LINEAR ==
+ feed_data->video_buffer->mode) &&
+ framing_res.info[i].used_prefix_size) {
+ ret = mpq_streambuffer_data_write(stream_buffer,
+ feed_data->prev_pattern +
+ DVB_DMX_MAX_PATTERN_LEN -
+ framing_res.info[i].used_prefix_size,
+ framing_res.info[i].used_prefix_size);
+
+ if (ret < 0) {
+ feed_data->pending_pattern_len = 0;
+ mpq_demux->decoder_drop_count +=
+ framing_res.info[i].used_prefix_size;
+ feed_data->ts_dropped_bytes +=
+ framing_res.info[i].used_prefix_size;
+ } else {
+ feed_data->pending_pattern_len =
+ framing_res.info[i].used_prefix_size;
+ }
+ } else {
+ s32 offset = (s32)feed_data->frame_offset;
+ u32 buff_size =
+ feed_data->video_buffer->buffers[0].size;
+
+ offset -= framing_res.info[i].used_prefix_size;
+ offset += (offset < 0) ? buff_size : 0;
+ feed_data->pending_pattern_len =
+ framing_res.info[i].used_prefix_size;
+
+ if (MPQ_STREAMBUFFER_BUFFER_MODE_RING ==
+ feed_data->video_buffer->mode) {
+ feed_data->frame_offset = (u32)offset;
+ }
+ }
}
/* save the last match for next time */
@@ -2856,11 +2897,23 @@
feed_data->prev_stc = curr_stc;
feed_data->first_prefix_size = 0;
+ /*
+ * Save the trailing of the TS packet as we might have a pattern
+ * split that we need to re-use when closing the next
+ * video linear buffer.
+ */
+ if (MPQ_STREAMBUFFER_BUFFER_MODE_LINEAR ==
+ feed_data->video_buffer->mode)
+ memcpy(feed_data->prev_pattern,
+ buf + 188 - DVB_DMX_MAX_PATTERN_LEN,
+ DVB_DMX_MAX_PATTERN_LEN);
+
if (pending_data_len) {
ret = mpq_streambuffer_data_write(
stream_buffer,
(buf + ts_payload_offset + bytes_written),
pending_data_len);
+
if (ret < 0) {
mpq_demux->decoder_drop_count += pending_data_len;
feed_data->ts_dropped_bytes += pending_data_len;
@@ -2905,7 +2958,7 @@
spin_lock(&feed_data->video_buffer_lock);
stream_buffer = feed_data->video_buffer;
if (stream_buffer == NULL) {
- MPQ_DVB_ERR_PRINT(
+ MPQ_DVB_DBG_PRINT(
"%s: video_buffer released\n",
__func__);
spin_unlock(&feed_data->video_buffer_lock);
@@ -3268,7 +3321,7 @@
stream_buffer = feed_data->video_buffer;
if (stream_buffer == NULL) {
- MPQ_DVB_ERR_PRINT("%s: video_buffer released\n", __func__);
+ MPQ_DVB_DBG_PRINT("%s: video_buffer released\n", __func__);
spin_unlock(&feed_data->video_buffer_lock);
return 0;
}
@@ -3911,6 +3964,58 @@
}
EXPORT_SYMBOL(mpq_dmx_set_cipher_ops);
+static int mpq_sdmx_invalidate_buffer(struct mpq_feed *mpq_feed)
+{
+ struct dvb_demux_feed *feed = mpq_feed->dvb_demux_feed;
+ struct mpq_video_feed_info *feed_data;
+ struct dvb_ringbuffer *buffer;
+ struct ion_handle *ion_handle;
+ int ret = 0;
+ int i;
+
+ if (!dvb_dmx_is_video_feed(feed)) {
+ if (dvb_dmx_is_sec_feed(feed) ||
+ dvb_dmx_is_pcr_feed(feed)) {
+ buffer = (struct dvb_ringbuffer *)
+ &mpq_feed->sdmx_buf;
+ ion_handle = mpq_feed->sdmx_buf_handle;
+ } else {
+ buffer = (struct dvb_ringbuffer *)
+ feed->feed.ts.buffer.ringbuff;
+ ion_handle = feed->feed.ts.buffer.priv_handle;
+ }
+
+ ret = msm_ion_do_cache_op(mpq_feed->mpq_demux->ion_client,
+ ion_handle, buffer->data,
+ buffer->size, ION_IOC_INV_CACHES);
+ if (ret)
+ MPQ_DVB_ERR_PRINT(
+ "%s: msm_ion_do_cache_op failed, ret = %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* Video buffers */
+ feed_data = &mpq_feed->video_info;
+ for (i = 0; i < feed_data->buffer_desc.decoder_buffers_num; i++) {
+ if (feed_data->buffer_desc.desc[i].base) {
+ /* Non-secured buffer */
+ ret = msm_ion_do_cache_op(
+ mpq_feed->mpq_demux->ion_client,
+ feed_data->buffer_desc.ion_handle[i],
+ feed_data->buffer_desc.desc[i].base,
+ feed_data->buffer_desc.desc[i].size,
+ ION_IOC_INV_CACHES);
+ if (ret)
+ MPQ_DVB_ERR_PRINT(
+ "%s: msm_ion_do_cache_op failed, ret = %d\n",
+ __func__, ret);
+ }
+ }
+
+ return ret;
+}
+
static void mpq_sdmx_prepare_filter_status(struct mpq_demux *mpq_demux,
struct sdmx_filter_status *filter_sts,
struct mpq_feed *mpq_feed)
@@ -3960,7 +4065,7 @@
spin_lock(&mpq_feed->video_info.video_buffer_lock);
sbuff = feed_data->video_buffer;
if (sbuff == NULL) {
- MPQ_DVB_ERR_PRINT(
+ MPQ_DVB_DBG_PRINT(
"%s: video_buffer released\n",
__func__);
spin_unlock(&feed_data->video_buffer_lock);
@@ -4463,7 +4568,7 @@
sbuf = mpq_feed->video_info.video_buffer;
if (sbuf == NULL) {
- MPQ_DVB_ERR_PRINT(
+ MPQ_DVB_DBG_PRINT(
"%s: video_buffer released\n",
__func__);
spin_unlock(&mpq_feed->video_info.video_buffer_lock);
@@ -4704,6 +4809,9 @@
mpq_feed->session_id))
continue;
+ /* Invalidate output buffer before processing the results */
+ mpq_sdmx_invalidate_buffer(mpq_feed);
+
if (sts->error_indicators & SDMX_FILTER_ERR_MD_BUF_FULL)
MPQ_DVB_ERR_PRINT(
"%s: meta-data buff for pid %d overflowed!\n",
@@ -4778,7 +4886,6 @@
for (i = 0; i < MPQ_MAX_DMX_FILES; i++) {
mpq_feed = &mpq_demux->feeds[i];
if ((mpq_feed->sdmx_filter_handle != SDMX_INVALID_FILTER_HANDLE)
- && (mpq_feed->dvb_demux_feed->state == DMX_STATE_GO)
&& (!mpq_feed->secondary_feed)) {
sts = mpq_demux->sdmx_filters_state.status +
filter_index;
@@ -4897,6 +5004,10 @@
const char *buf,
size_t count)
{
+ struct ion_handle *ion_handle =
+ mpq_demux->demux.dmx.dvr_input.priv_handle;
+ struct dvb_ringbuffer *rbuf = (struct dvb_ringbuffer *)
+ mpq_demux->demux.dmx.dvr_input.ringbuff;
struct sdmx_buff_descr buf_desc;
u32 read_offset;
int ret;
@@ -4915,6 +5026,19 @@
}
read_offset = mpq_demux->demux.dmx.dvr_input.ringbuff->pread;
+
+ /*
+ * We must flush the buffer before SDMX starts reading from it
+ * so that it gets a valid data in memory.
+ */
+ ret = msm_ion_do_cache_op(mpq_demux->ion_client,
+ ion_handle, rbuf->data,
+ rbuf->size, ION_IOC_CLEAN_CACHES);
+ if (ret)
+ MPQ_DVB_ERR_PRINT(
+ "%s: msm_ion_do_cache_op failed, ret = %d\n",
+ __func__, ret);
+
return mpq_sdmx_process(mpq_demux, &buf_desc, count,
read_offset, mpq_demux->demux.ts_packet_size);
}
diff --git a/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.h b/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.h
index adc4261..b362c5b 100644
--- a/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.h
+++ b/drivers/media/platform/msm/dvb/demux/mpq_dmx_plugin_common.h
@@ -238,6 +238,7 @@
* with this stream buffer.
* @patterns: pointer to the framing patterns to look for.
* @patterns_num: number of framing patterns.
+ * @prev_pattern: holds the trailing data of the last processed video packet.
* @frame_offset: Saves data buffer offset to which a new frame will be written
* @last_pattern_offset: Holds the previous pattern offset
* @pending_pattern_len: Accumulated number of data bytes that will be
@@ -288,6 +289,7 @@
const struct dvb_dmx_video_patterns
*patterns[DVB_DMX_MAX_SEARCH_PATTERN_NUM];
int patterns_num;
+ char prev_pattern[DVB_DMX_MAX_PATTERN_LEN];
u32 frame_offset;
u32 last_pattern_offset;
u32 pending_pattern_len;
diff --git a/drivers/media/platform/msm/vidc/hfi_packetization.c b/drivers/media/platform/msm/vidc/hfi_packetization.c
index 2fb3c35..4da0f6f 100644
--- a/drivers/media/platform/msm/vidc/hfi_packetization.c
+++ b/drivers/media/platform/msm/vidc/hfi_packetization.c
@@ -565,7 +565,7 @@
u32 session_id, struct vidc_seq_hdr *seq_hdr)
{
int rc = 0;
- if (!pkt || !session_id || seq_hdr)
+ if (!pkt || !session_id || !seq_hdr)
return -EINVAL;
pkt->size = sizeof(struct hfi_cmd_session_parse_sequence_header_packet);
diff --git a/drivers/media/platform/msm/vidc/msm_smem.c b/drivers/media/platform/msm/vidc/msm_smem.c
index 5140a03..9604a09 100644
--- a/drivers/media/platform/msm/vidc/msm_smem.c
+++ b/drivers/media/platform/msm/vidc/msm_smem.c
@@ -171,8 +171,10 @@
mem->smem_priv = hndl;
mem->device_addr = iova;
mem->size = buffer_size;
- dprintk(VIDC_DBG, "NOTE: Buffer device address: 0x%lx, size: %d\n",
- mem->device_addr, mem->size);
+ dprintk(VIDC_DBG,
+ "%s: ion_handle = 0x%p, fd = %d, device_addr = 0x%x, size = %d, kvaddr = 0x%p, buffer_type = %d\n",
+ __func__, mem->smem_priv, fd, (u32)mem->device_addr,
+ mem->size, mem->kvaddr, mem->buffer_type);
return rc;
fail_device_address:
ion_free(client->clnt, hndl);
@@ -241,10 +243,11 @@
goto fail_device_address;
}
mem->device_addr = iova;
- dprintk(VIDC_DBG,
- "device_address = 0x%lx, kvaddr = 0x%p, size = %d\n",
- mem->device_addr, mem->kvaddr, size);
mem->size = size;
+ dprintk(VIDC_DBG,
+ "%s: ion_handle = 0x%p, device_addr = 0x%x, size = %d, kvaddr = 0x%p, buffer_type = %d\n",
+ __func__, mem->smem_priv, (u32)mem->device_addr,
+ mem->size, mem->kvaddr, mem->buffer_type);
return rc;
fail_device_address:
ion_unmap_kernel(client->clnt, hndl);
@@ -258,6 +261,10 @@
{
int domain, partition, rc;
+ dprintk(VIDC_DBG,
+ "%s: ion_handle = 0x%p, device_addr = 0x%x, size = %d, kvaddr = 0x%p, buffer_type = %d\n",
+ __func__, mem->smem_priv, (u32)mem->device_addr,
+ mem->size, mem->kvaddr, mem->buffer_type);
rc = msm_smem_get_domain_partition((void *)client, mem->flags,
mem->buffer_type, &domain, &partition);
if (rc) {
diff --git a/drivers/media/platform/msm/vidc/msm_smem.h b/drivers/media/platform/msm/vidc/msm_smem.h
index 7bd6443..ca92e73 100644
--- a/drivers/media/platform/msm/vidc/msm_smem.h
+++ b/drivers/media/platform/msm/vidc/msm_smem.h
@@ -28,41 +28,6 @@
SMEM_SECURE = ION_FLAG_SECURE,
};
-/* NOTE: if you change this enum you MUST update the
- * "buffer-type-tz-usage-table" for any affected target
- * in arch/arm/boot/dts/<arch>.dtsi
- */
-enum hal_buffer {
- HAL_BUFFER_INPUT = 0x1,
- HAL_BUFFER_OUTPUT = 0x2,
- HAL_BUFFER_OUTPUT2 = 0x4,
- HAL_BUFFER_EXTRADATA_INPUT = 0x8,
- HAL_BUFFER_EXTRADATA_OUTPUT = 0x10,
- HAL_BUFFER_EXTRADATA_OUTPUT2 = 0x20,
- HAL_BUFFER_INTERNAL_SCRATCH = 0x40,
- HAL_BUFFER_INTERNAL_SCRATCH_1 = 0x80,
- HAL_BUFFER_INTERNAL_SCRATCH_2 = 0x100,
- HAL_BUFFER_INTERNAL_PERSIST = 0x200,
- HAL_BUFFER_INTERNAL_PERSIST_1 = 0x400,
- HAL_BUFFER_INTERNAL_CMD_QUEUE = 0x800,
-};
-
-struct msm_smem {
- int mem_type;
- size_t size;
- void *kvaddr;
- unsigned long device_addr;
- u32 flags;
- void *smem_priv;
- enum hal_buffer buffer_type;
-};
-
-enum smem_cache_ops {
- SMEM_CACHE_CLEAN,
- SMEM_CACHE_INVALIDATE,
- SMEM_CACHE_CLEAN_INVALIDATE,
-};
-
void *msm_smem_new_client(enum smem_type mtype,
struct msm_vidc_platform_resources *res);
struct msm_smem *msm_smem_alloc(void *clt, size_t size, u32 align, u32 flags,
@@ -73,7 +38,6 @@
enum smem_cache_ops);
struct msm_smem *msm_smem_user_to_kernel(void *clt, int fd, u32 offset,
enum hal_buffer buffer_type);
-int msm_smem_clean_invalidate(void *clt, struct msm_smem *mem);
int msm_smem_get_domain_partition(void *clt, u32 flags, enum hal_buffer
buffer_type, int *domain_num, int *partition_num);
#endif
diff --git a/drivers/media/platform/msm/vidc/msm_vdec.c b/drivers/media/platform/msm/vidc/msm_vdec.c
index efa195e..9dd4e93 100644
--- a/drivers/media/platform/msm/vidc/msm_vdec.c
+++ b/drivers/media/platform/msm/vidc/msm_vdec.c
@@ -971,6 +971,14 @@
rc = -EINVAL;
goto err_invalid_fmt;
}
+ if (!(get_hal_codec_type(fmt->fourcc) &
+ inst->core->dec_codec_supported)) {
+ dprintk(VIDC_ERR,
+ "Codec(0x%x) not supported\n",
+ get_hal_codec_type(fmt->fourcc));
+ rc = -EINVAL;
+ goto err_invalid_fmt;
+ }
inst->fmts[fmt->type] = fmt;
rc = msm_comm_try_state(inst, MSM_VIDC_OPEN_DONE);
if (rc) {
diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c
index 6ed94e4..9da1220 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc.c
@@ -356,7 +356,7 @@
struct v4l2_plane *p, enum hal_buffer buffer_type)
{
struct msm_smem *handle = NULL;
- handle = msm_smem_user_to_kernel(inst->mem_client,
+ handle = msm_comm_smem_user_to_kernel(inst,
p->reserved[0],
p->reserved[1],
buffer_type);
@@ -365,7 +365,7 @@
"%s: Failed to get device buffer address\n", __func__);
return NULL;
}
- if (msm_smem_cache_operations(inst->mem_client, handle,
+ if (msm_comm_smem_cache_operations(inst, handle,
SMEM_CACHE_CLEAN))
dprintk(VIDC_WARN,
"CACHE Clean failed: %d, %d, %d\n",
@@ -489,6 +489,7 @@
temp->handle[plane]->device_addr + binfo->buff_off[i];
b->m.planes[i].m.userptr = binfo->device_addr[i];
binfo->mapped[i] = false;
+ binfo->handle[i] = temp->handle[i];
} else {
if (inst->map_output_buffer) {
binfo->handle[i] =
@@ -498,9 +499,6 @@
rc = -EINVAL;
goto exit;
}
- dprintk(VIDC_DBG,
- "[MAP] - mapped handle[%d] = %p fd[%d] = %d",
- i, binfo->handle[i], i, binfo->fd[i]);
binfo->mapped[i] = true;
binfo->device_addr[i] =
binfo->handle[i]->device_addr +
@@ -511,10 +509,6 @@
binfo->device_addr[i] =
b->m.planes[i].m.userptr;
}
- dprintk(VIDC_DBG, "Registering buffer: %d, %d, %d\n",
- b->m.planes[i].reserved[0],
- b->m.planes[i].reserved[1],
- b->m.planes[i].length);
}
/* We maintain one ref count for all planes*/
if ((i == 0) && is_dynamic_output_buffer_mode(b, inst)) {
@@ -522,8 +516,12 @@
if (rc < 0)
return rc;
}
+ dprintk(VIDC_DBG,
+ "%s: [MAP] binfo = %p, handle[%d] = %p, device_addr = 0x%x, fd = %d, offset = %d, mapped = %d\n",
+ __func__, binfo, i, binfo->handle[i],
+ binfo->device_addr[i], binfo->fd[i],
+ binfo->buff_off[i], binfo->mapped[i]);
}
- dprintk(VIDC_DBG, "[MAP] Adding binfo = %p to list\n", binfo);
mutex_lock(&inst->lock);
list_add_tail(&binfo->list, &inst->registered_bufs);
mutex_unlock(&inst->lock);
@@ -570,6 +568,11 @@
goto exit;
for (i = 0; i < temp->num_planes; i++) {
+ dprintk(VIDC_DBG,
+ "%s: [UNMAP] binfo = %p, handle[%d] = %p, device_addr = 0x%x, fd = %d, offset = %d, mapped = %d\n",
+ __func__, temp, i, temp->handle[i],
+ temp->device_addr[i], temp->fd[i],
+ temp->buff_off[i], temp->mapped[i]);
/*
* Unmap the handle only if the buffer has been mapped and no
* other buffer has a reference to this buffer.
@@ -584,7 +587,7 @@
dprintk(VIDC_DBG,
"[UNMAP] - handle[%d] = %p fd[%d] = %d",
i, temp->handle[i], i, temp->fd[i]);
- msm_smem_free(inst->mem_client,
+ msm_comm_smem_free(inst,
temp->handle[i]);
}
@@ -660,7 +663,7 @@
for (i = 0; i < binfo->num_planes; i++) {
if (binfo->handle[i]) {
- rc = msm_smem_cache_operations(inst->mem_client,
+ rc = msm_comm_smem_cache_operations(inst,
binfo->handle[i], SMEM_CACHE_INVALIDATE);
if (rc) {
dprintk(VIDC_ERR,
@@ -668,7 +671,8 @@
__func__, rc);
return -EINVAL;
}
- }
+ } else
+ dprintk(VIDC_ERR, "%s: WARN: NULL handle", __func__);
}
return 0;
}
@@ -742,11 +746,18 @@
buffer_info.m.planes[0].reserved[0],
buffer_info.m.planes[0].reserved[1],
buffer_info.m.planes[0].length);
+
list_del(&bi->list);
for (i = 0; i < bi->num_planes; i++) {
- if (bi->handle[i])
- msm_smem_free(inst->mem_client,
+ if (bi->handle[i] && bi->mapped[i]) {
+ dprintk(VIDC_DBG,
+ "%s: [UNMAP] binfo = %p, handle[%d] = %p, device_addr = 0x%x, fd = %d, offset = %d, mapped = %d\n",
+ __func__, bi, i, bi->handle[i],
+ bi->device_addr[i], bi->fd[i],
+ bi->buff_off[i], bi->mapped[i]);
+ msm_comm_smem_free(inst,
bi->handle[i]);
+ }
}
kfree(bi);
}
@@ -824,7 +835,7 @@
if ((inst->fmts[OUTPUT_PORT]->fourcc ==
V4L2_PIX_FMT_HEVC_HYBRID) && binfo->handle[i] &&
(b->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)) {
- rc = msm_smem_cache_operations(inst->mem_client,
+ rc = msm_comm_smem_cache_operations(inst,
binfo->handle[i], SMEM_CACHE_INVALIDATE);
if (rc) {
dprintk(VIDC_ERR,
@@ -835,7 +846,7 @@
if (binfo->handle[i] &&
(b->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)) {
- rc = msm_smem_cache_operations(inst->mem_client,
+ rc = msm_comm_smem_cache_operations(inst,
binfo->handle[i], SMEM_CACHE_CLEAN);
if (rc) {
dprintk(VIDC_ERR,
@@ -970,6 +981,57 @@
fsize->stepwise.step_height = capability->height.step_size;
return 0;
}
+
+struct msm_smem *msm_vidc_smem_alloc(void *instance,
+ size_t size, u32 align, u32 flags,
+ enum hal_buffer buffer_type, int map_kernel)
+{
+ return msm_comm_smem_alloc((struct msm_vidc_inst *)instance,
+ size, align, flags, buffer_type, map_kernel);
+
+}
+
+void msm_vidc_smem_free(void *instance, struct msm_smem *mem)
+{
+ msm_comm_smem_free((struct msm_vidc_inst *)instance, mem);
+}
+
+int msm_vidc_smem_cache_operations(void *instance, struct msm_smem *mem,
+ enum smem_cache_ops cache_ops)
+{
+ return msm_comm_smem_cache_operations(
+ (struct msm_vidc_inst *)instance, mem, cache_ops);
+}
+
+struct msm_smem *msm_vidc_smem_user_to_kernel(void *instance, int fd,
+ u32 offset, enum hal_buffer buffer_type)
+{
+ return msm_comm_smem_user_to_kernel(
+ (struct msm_vidc_inst *)instance,
+ fd, offset, buffer_type);
+}
+
+int msm_vidc_smem_get_domain_partition(void *instance, u32 flags,
+ enum hal_buffer buffer_type, int *domain_num,
+ int *partition_num)
+{
+ return msm_comm_smem_get_domain_partition(
+ (struct msm_vidc_inst *)instance,
+ flags, buffer_type, domain_num, partition_num);
+}
+
+void *msm_vidc_smem_get_client(void *instance)
+{
+ struct msm_vidc_inst *inst = instance;
+
+ if (!inst || !inst->mem_client) {
+ dprintk(VIDC_ERR, "%s: invalid instance or client = %p %p\n",
+ __func__, inst, inst->mem_client);
+ return NULL;
+ }
+
+ return inst->mem_client;
+}
static void *vidc_get_userptr(void *alloc_ctx, unsigned long vaddr,
unsigned long size, int write)
{
@@ -1189,7 +1251,7 @@
list);
list_del(&buf->list);
mutex_unlock(&inst->lock);
- msm_smem_free(inst->mem_client, buf->handle);
+ msm_comm_smem_free(inst, buf->handle);
kfree(buf);
mutex_lock(&inst->lock);
}
@@ -1200,7 +1262,7 @@
list);
list_del(&buf->list);
mutex_unlock(&inst->lock);
- msm_smem_free(inst->mem_client, buf->handle);
+ msm_comm_smem_free(inst, buf->handle);
kfree(buf);
mutex_lock(&inst->lock);
}
@@ -1211,14 +1273,14 @@
list);
list_del(&buf->list);
mutex_unlock(&inst->lock);
- msm_smem_free(inst->mem_client, buf->handle);
+ msm_comm_smem_free(inst, buf->handle);
kfree(buf);
mutex_lock(&inst->lock);
}
}
if (inst->extradata_handle) {
mutex_unlock(&inst->lock);
- msm_smem_free(inst->mem_client, inst->extradata_handle);
+ msm_comm_smem_free(inst, inst->extradata_handle);
mutex_lock(&inst->lock);
}
mutex_unlock(&inst->lock);
@@ -1247,8 +1309,7 @@
for (i = 0; (i < bi->num_planes)
&& (i < VIDEO_MAX_PLANES); i++) {
if (bi->handle[i])
- msm_smem_free(inst->mem_client,
- bi->handle[i]);
+ msm_comm_smem_free(inst, bi->handle[i]);
}
kfree(bi);
}
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c
index c63af6c..7588994 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_common.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c
@@ -277,14 +277,17 @@
dprintk(VIDC_ERR, "Wrong device_id received\n");
return;
}
- dprintk(VIDC_DBG, "index = %d\n", index);
- dprintk(VIDC_DBG, "ptr = %p\n", &(core->completions[index]));
- complete(&(core->completions[index]));
sys_init_msg = response->data;
if (!sys_init_msg) {
dprintk(VIDC_ERR, "sys_init_done message not proper\n");
return;
}
+ core->enc_codec_supported = sys_init_msg->enc_codec_supported;
+ core->dec_codec_supported = sys_init_msg->dec_codec_supported;
+ dprintk(VIDC_DBG, "supported_codecs: enc = 0x%x, dec = 0x%x\n",
+ core->enc_codec_supported, core->dec_codec_supported);
+ dprintk(VIDC_DBG, "ptr[%d] = %p\n", index, &(core->completions[index]));
+ complete(&(core->completions[index]));
}
static void handle_session_release_buf_done(enum command_response cmd,
@@ -765,6 +768,7 @@
mutex_lock(&core->lock);
core->state = VIDC_CORE_INVALID;
mutex_unlock(&core->lock);
+ mutex_lock(&core->sync_lock);
list_for_each_entry(inst, &core->instances,
list) {
mutex_lock(&inst->lock);
@@ -786,6 +790,7 @@
msm_vidc_queue_v4l2_event(inst,
V4L2_EVENT_MSM_VIDC_SYS_ERROR);
}
+ mutex_unlock(&core->sync_lock);
} else {
dprintk(VIDC_ERR,
"Got SYS_ERR but unable to identify core");
@@ -813,6 +818,7 @@
mutex_lock(&core->lock);
core->state = VIDC_CORE_INVALID;
mutex_unlock(&core->lock);
+ mutex_lock(&core->sync_lock);
list_for_each_entry(inst, &core->instances, list) {
if (inst) {
msm_vidc_queue_v4l2_event(inst,
@@ -834,6 +840,7 @@
mutex_unlock(&inst->lock);
}
}
+ mutex_unlock(&core->sync_lock);
}
static void handle_session_close(enum command_response cmd, void *data)
@@ -937,6 +944,12 @@
V4L2_QCOM_BUF_DATA_CORRUPT;
}
}
+ dprintk(VIDC_DBG,
+ "Got ebd from hal: device_addr: 0x%x, alloc: %d, status: 0x%x, pic_type: 0x%x, flags: 0x%x\n",
+ (u32)empty_buf_done->packet_buffer,
+ empty_buf_done->alloc_len, empty_buf_done->status,
+ empty_buf_done->picture_type, empty_buf_done->flags);
+
mutex_lock(&inst->bufq[OUTPUT_PORT].lock);
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
mutex_unlock(&inst->bufq[OUTPUT_PORT].lock);
@@ -1095,6 +1108,7 @@
struct vb2_buffer *vb = NULL;
struct vidc_hal_fbd *fill_buf_done;
enum hal_buffer buffer_type;
+ int64_t time_usec = 0;
if (!response) {
dprintk(VIDC_ERR, "Invalid response from vidc_hal\n");
@@ -1134,7 +1148,7 @@
if (!(fill_buf_done->flags1 &
HAL_BUFFERFLAG_TIMESTAMPINVALID) &&
fill_buf_done->filled_len1) {
- int64_t time_usec = fill_buf_done->timestamp_hi;
+ time_usec = fill_buf_done->timestamp_hi;
time_usec = (time_usec << 32) |
fill_buf_done->timestamp_lo;
vb->v4l2_buf.timestamp =
@@ -1187,10 +1201,14 @@
msm_vidc_debugfs_update(inst,
MSM_VIDC_DEBUGFS_EVENT_FBD);
- dprintk(VIDC_DBG, "Filled length = %d; offset = %d; flags %x\n",
- vb->v4l2_planes[0].bytesused,
- vb->v4l2_planes[0].data_offset,
- vb->v4l2_buf.flags);
+ dprintk(VIDC_DBG,
+ "Got fbd from hal: device_addr: 0x%x, alloc: %d, filled: %d, offset: %d, ts: %lld, flags: 0x%x, crop: %d %d %d %d, pic_type: 0x%x\n",
+ (u32)fill_buf_done->packet_buffer1, fill_buf_done->alloc_len1,
+ fill_buf_done->filled_len1, fill_buf_done->offset1, time_usec,
+ fill_buf_done->flags1, fill_buf_done->start_x_coord,
+ fill_buf_done->start_y_coord, fill_buf_done->frame_width,
+ fill_buf_done->frame_height, fill_buf_done->picture_type);
+
mutex_lock(&inst->bufq[CAPTURE_PORT].lock);
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
mutex_unlock(&inst->bufq[CAPTURE_PORT].lock);
@@ -1594,7 +1612,7 @@
return domain;
}
-static enum hal_video_codec get_hal_codec_type(int fourcc)
+enum hal_video_codec get_hal_codec_type(int fourcc)
{
enum hal_video_codec codec;
dprintk(VIDC_DBG, "codec is 0x%x", fourcc);
@@ -1994,7 +2012,7 @@
if (output_buf->buffer_size) {
for (i = 0; i < output_buf->buffer_count_actual;
i++) {
- handle = msm_smem_alloc(inst->mem_client,
+ handle = msm_comm_smem_alloc(inst,
buffer_size, 1, smem_flags,
buffer_type, 0);
if (!handle) {
@@ -2003,7 +2021,7 @@
rc = -ENOMEM;
goto err_no_mem;
}
- rc = msm_smem_cache_operations(inst->mem_client,
+ rc = msm_comm_smem_cache_operations(inst,
handle, SMEM_CACHE_CLEAN);
if (rc) {
dprintk(VIDC_WARN,
@@ -2048,7 +2066,7 @@
fail_set_buffers:
kfree(binfo);
fail_kzalloc:
- msm_smem_free(inst->mem_client, handle);
+ msm_comm_smem_free(inst, handle);
err_no_mem:
return rc;
}
@@ -2085,7 +2103,7 @@
if (scratch_buf->buffer_size) {
for (i = 0; i < scratch_buf->buffer_count_actual;
i++) {
- handle = msm_smem_alloc(inst->mem_client,
+ handle = msm_comm_smem_alloc(inst,
scratch_buf->buffer_size, 1, smem_flags,
buffer_type, 0);
if (!handle) {
@@ -2094,7 +2112,7 @@
rc = -ENOMEM;
goto err_no_mem;
}
- rc = msm_smem_cache_operations(inst->mem_client,
+ rc = msm_comm_smem_cache_operations(inst,
handle, SMEM_CACHE_CLEAN);
if (rc) {
dprintk(VIDC_WARN,
@@ -2130,7 +2148,7 @@
fail_set_buffers:
kfree(binfo);
fail_kzalloc:
- msm_smem_free(inst->mem_client, handle);
+ msm_comm_smem_free(inst, handle);
err_no_mem:
return rc;
}
@@ -2172,7 +2190,7 @@
if (persist_buf->buffer_size) {
for (i = 0; i < persist_buf->buffer_count_actual; i++) {
- handle = msm_smem_alloc(inst->mem_client,
+ handle = msm_comm_smem_alloc(inst,
persist_buf->buffer_size, 1, smem_flags,
buffer_type, 0);
if (!handle) {
@@ -2181,7 +2199,7 @@
rc = -ENOMEM;
goto err_no_mem;
}
- rc = msm_smem_cache_operations(inst->mem_client,
+ rc = msm_comm_smem_cache_operations(inst,
handle, SMEM_CACHE_CLEAN);
if (rc) {
dprintk(VIDC_WARN,
@@ -2217,7 +2235,7 @@
fail_set_buffers:
kfree(binfo);
fail_kzalloc:
- msm_smem_free(inst->mem_client, handle);
+ msm_comm_smem_free(inst, handle);
err_no_mem:
return rc;
}
@@ -2426,11 +2444,10 @@
V4L2_QCOM_BUF_TIMESTAMP_INVALID)
frame_data.timestamp = LLONG_MAX;
dprintk(VIDC_DBG,
- "Sending etb to hal: device_addr: 0x%x"
- "Alloc: %d, filled: %d, offset: %d\n",
- frame_data.device_addr,
- frame_data.alloc_len, frame_data.filled_len,
- frame_data.offset);
+ "Sending etb to hal: device_addr: 0x%x, alloc: %d, filled: %d, offset: %d, ts: %lld, flags = 0x%x\n",
+ frame_data.device_addr, frame_data.alloc_len,
+ frame_data.filled_len, frame_data.offset,
+ frame_data.timestamp, frame_data.flags);
rc = call_hfi_op(hdev, session_etb, (void *)
inst->session, &frame_data);
if (!rc)
@@ -2455,11 +2472,10 @@
vb->v4l2_planes[extra_idx].length;
}
dprintk(VIDC_DBG,
- "Sending ftb to hal: Alloc: %d :filled: %d",
- frame_data.alloc_len, frame_data.filled_len);
- dprintk(VIDC_DBG,
- " extradata_addr: %d\n",
- frame_data.extradata_addr);
+ "Sending ftb to hal: device_addr: 0x%x, alloc: %d, buffer_type: %d, ts: %lld, flags = 0x%x\n",
+ frame_data.device_addr, frame_data.alloc_len,
+ frame_data.buffer_type, frame_data.timestamp,
+ frame_data.flags);
if (!inst->ftb_count &&
inst->session_type == MSM_VIDC_ENCODER) {
seq_hdr.seq_hdr = (u8 *) vb->v4l2_planes[0].
@@ -2475,9 +2491,9 @@
} else {
rc = call_hfi_op(hdev, session_ftb,
(void *) inst->session, &frame_data);
- if (!rc)
- msm_vidc_debugfs_update(inst,
- MSM_VIDC_DEBUGFS_EVENT_FTB);
+ if (!rc)
+ msm_vidc_debugfs_update(inst,
+ MSM_VIDC_DEBUGFS_EVENT_FTB);
}
inst->ftb_count++;
} else {
@@ -2589,7 +2605,7 @@
}
list_del(&buf->list);
mutex_unlock(&inst->lock);
- msm_smem_free(inst->mem_client, buf->handle);
+ msm_comm_smem_free(inst, buf->handle);
kfree(buf);
mutex_lock(&inst->lock);
}
@@ -2660,7 +2676,7 @@
}
list_del(&buf->list);
mutex_unlock(&inst->lock);
- msm_smem_free(inst->mem_client, buf->handle);
+ msm_comm_smem_free(inst, buf->handle);
kfree(buf);
mutex_lock(&inst->lock);
}
@@ -2731,7 +2747,7 @@
}
list_del(&buf->list);
mutex_unlock(&inst->lock);
- msm_smem_free(inst->mem_client, buf->handle);
+ msm_comm_smem_free(inst, buf->handle);
kfree(buf);
mutex_lock(&inst->lock);
}
@@ -3145,7 +3161,7 @@
{
int rc = 0;
struct hfi_device *hdev;
- if (!core && !core->device) {
+ if (!core || !core->device) {
dprintk(VIDC_WARN, "Invalid parameters: %p\n", core);
return -EINVAL;
}
@@ -3161,10 +3177,12 @@
int num_mbs_per_sec = 0;
if (inst->state == MSM_VIDC_OPEN_DONE) {
+ mutex_lock(&inst->core->sync_lock);
num_mbs_per_sec = msm_comm_get_load(inst->core,
MSM_VIDC_DECODER);
num_mbs_per_sec += msm_comm_get_load(inst->core,
MSM_VIDC_ENCODER);
+ mutex_unlock(&inst->core->sync_lock);
if (num_mbs_per_sec > inst->core->resources.max_load) {
dprintk(VIDC_ERR,
"H/w is overloaded. needed: %d max: %d\n",
@@ -3337,3 +3355,85 @@
change_inst_state(inst, MSM_VIDC_CLOSE_DONE);
return rc;
}
+
+static inline int power_on_for_smem(struct msm_vidc_inst *inst)
+{
+ struct hfi_device *hdev = NULL;
+ int rc = 0;
+
+ if (!inst || !inst->core || !inst->core->device) {
+ dprintk(VIDC_ERR, "%s: invalid inst handle\n", __func__);
+ return -EINVAL;
+ }
+ hdev = inst->core->device;
+ rc = call_hfi_op(hdev, power_enable, hdev->hfi_device_data);
+ if (rc)
+ dprintk(VIDC_ERR, "%s: failed to power on fw\n", __func__);
+ return rc;
+}
+
+struct msm_smem *msm_comm_smem_alloc(struct msm_vidc_inst *inst,
+ size_t size, u32 align, u32 flags,
+ enum hal_buffer buffer_type, int map_kernel)
+{
+ if (!inst) {
+ dprintk(VIDC_ERR, "%s: invalid inst: %p\n", __func__, inst);
+ return NULL;
+ }
+ if (power_on_for_smem(inst))
+ return NULL;
+
+ return msm_smem_alloc(inst->mem_client, size, align,
+ flags, buffer_type, map_kernel);
+}
+
+void msm_comm_smem_free(struct msm_vidc_inst *inst, struct msm_smem *mem)
+{
+ if (!inst || !mem) {
+ dprintk(VIDC_ERR,
+ "%s: invalid params: %p %p\n", __func__, inst, mem);
+ return;
+ }
+ if (power_on_for_smem(inst))
+ return;
+
+ return msm_smem_free(inst->mem_client, mem);
+}
+
+int msm_comm_smem_cache_operations(struct msm_vidc_inst *inst,
+ struct msm_smem *mem, enum smem_cache_ops cache_ops)
+{
+ if (!inst || !mem) {
+ dprintk(VIDC_ERR,
+ "%s: invalid params: %p %p\n", __func__, inst, mem);
+ return -EINVAL;
+ }
+ return msm_smem_cache_operations(inst->mem_client, mem, cache_ops);
+}
+
+struct msm_smem *msm_comm_smem_user_to_kernel(struct msm_vidc_inst *inst,
+ int fd, u32 offset, enum hal_buffer buffer_type)
+{
+ if (!inst) {
+ dprintk(VIDC_ERR, "%s: invalid inst: %p\n", __func__, inst);
+ return NULL;
+ }
+ if (power_on_for_smem(inst))
+ return NULL;
+
+ return msm_smem_user_to_kernel(inst->mem_client,
+ fd, offset, buffer_type);
+}
+
+int msm_comm_smem_get_domain_partition(struct msm_vidc_inst *inst,
+ u32 flags, enum hal_buffer buffer_type,
+ int *domain_num, int *partition_num)
+{
+ if (!inst || !domain_num || !partition_num) {
+ dprintk(VIDC_ERR, "%s: invalid params: %p %p %p\n",
+ __func__, inst, domain_num, partition_num);
+ return -EINVAL;
+ }
+ return msm_smem_get_domain_partition(inst->mem_client, flags,
+ buffer_type, domain_num, partition_num);
+}
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.h b/drivers/media/platform/msm/vidc/msm_vidc_common.h
index 195fa7e..e2f7b61 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_common.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_common.h
@@ -52,5 +52,16 @@
int msm_comm_recover_from_session_error(struct msm_vidc_inst *inst);
enum multi_stream msm_comm_get_stream_output_mode(struct msm_vidc_inst *inst);
enum hal_buffer msm_comm_get_hal_output_buffer(struct msm_vidc_inst *inst);
-
+struct msm_smem *msm_comm_smem_alloc(struct msm_vidc_inst *inst,
+ size_t size, u32 align, u32 flags,
+ enum hal_buffer buffer_type, int map_kernel);
+void msm_comm_smem_free(struct msm_vidc_inst *inst, struct msm_smem *mem);
+int msm_comm_smem_cache_operations(struct msm_vidc_inst *inst,
+ struct msm_smem *mem, enum smem_cache_ops cache_ops);
+struct msm_smem *msm_comm_smem_user_to_kernel(struct msm_vidc_inst *inst,
+ int fd, u32 offset, enum hal_buffer buffer_type);
+int msm_comm_smem_get_domain_partition(struct msm_vidc_inst *inst,
+ u32 flags, enum hal_buffer buffer_type,
+ int *domain_num, int *partition_num);
+enum hal_video_codec get_hal_codec_type(int fourcc);
#endif
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_internal.h b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
index 2b1471c..e4f920f 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_internal.h
+++ b/drivers/media/platform/msm/vidc/msm_vidc_internal.h
@@ -207,6 +207,8 @@
struct completion completions[SYS_MSG_END - SYS_MSG_START + 1];
enum msm_vidc_hfi_type hfi_type;
struct msm_vidc_platform_resources resources;
+ u32 enc_codec_supported;
+ u32 dec_codec_supported;
};
struct msm_vidc_inst {
diff --git a/drivers/media/platform/msm/vidc/msm_vidc_res_parse.c b/drivers/media/platform/msm/vidc/msm_vidc_res_parse.c
index 394ecdc5..ecfff85 100644
--- a/drivers/media/platform/msm/vidc/msm_vidc_res_parse.c
+++ b/drivers/media/platform/msm/vidc/msm_vidc_res_parse.c
@@ -289,7 +289,7 @@
bus_pdata->usecase[i].vectors = kzalloc(
sizeof(*bus_pdata->usecase[i].vectors) * num_ports,
GFP_KERNEL);
- if (!bus_pdata->usecase) {
+ if (!bus_pdata->usecase[i].vectors) {
dprintk(VIDC_ERR,
"%s Failed to alloc bus_pdata usecase\n",
__func__);
diff --git a/drivers/media/platform/msm/vidc/venus_hfi.c b/drivers/media/platform/msm/vidc/venus_hfi.c
index 8cd3889..2596a30 100644
--- a/drivers/media/platform/msm/vidc/venus_hfi.c
+++ b/drivers/media/platform/msm/vidc/venus_hfi.c
@@ -25,10 +25,12 @@
#include <mach/subsystem_restart.h>
#include <mach/msm_smem.h>
#include <asm/memory.h>
+#include <linux/iopoll.h>
#include "hfi_packetization.h"
#include "venus_hfi.h"
#include "vidc_hfi_io.h"
#include "msm_vidc_debug.h"
+#include <linux/iopoll.h>
#define FIRMWARE_SIZE 0X00A00000
#define REG_ADDR_OFFSET_BITMASK 0x000FFFFF
@@ -65,6 +67,9 @@
#define TZBSP_VIDEO_SET_STATE 0xa
+/* Poll interval in uS */
+#define POLL_INTERVAL_US 50
+
enum tzbsp_video_state {
TZBSP_VIDEO_STATE_SUSPEND = 0,
TZBSP_VIDEO_STATE_RESUME
@@ -75,6 +80,11 @@
u32 spare; /*reserved for future, should be zero*/
};
+
+static inline int venus_hfi_clk_gating_off(struct venus_hfi_device *device);
+
+static int venus_hfi_power_enable(void *dev);
+
static void venus_hfi_dump_packet(u8 *packet)
{
u32 c = 0, packet_size = *(u32 *)packet;
@@ -402,21 +412,24 @@
return rc;
}
-static int venus_hfi_alloc(void *mem, void *clnt, u32 size, u32 align,
- u32 flags, u32 usage)
+static int venus_hfi_alloc(struct venus_hfi_device *dev, void *mem,
+ u32 size, u32 align, u32 flags, u32 usage)
{
- struct vidc_mem_addr *vmem;
- struct msm_smem *alloc;
+ struct vidc_mem_addr *vmem = NULL;
+ struct msm_smem *alloc = NULL;
int rc = 0;
- if (!mem || !clnt || !size) {
+ if (!dev || !dev->hal_client || !mem || !size) {
dprintk(VIDC_ERR, "Invalid Params");
return -EINVAL;
}
+
vmem = (struct vidc_mem_addr *)mem;
dprintk(VIDC_INFO, "start to alloc: size:%d, Flags: %d", size, flags);
- alloc = msm_smem_alloc(clnt, size, align, flags, usage, 1);
+ venus_hfi_power_enable(dev);
+
+ alloc = msm_smem_alloc(dev->hal_client, size, align, flags, usage, 1);
dprintk(VIDC_DBG, "Alloc done");
if (!alloc) {
dprintk(VIDC_ERR, "Alloc failed\n");
@@ -425,7 +438,7 @@
}
dprintk(VIDC_DBG, "venus_hfi_alloc:ptr=%p,size=%d",
alloc->kvaddr, size);
- rc = msm_smem_cache_operations(clnt, alloc,
+ rc = msm_smem_cache_operations(dev->hal_client, alloc,
SMEM_CACHE_CLEAN);
if (rc) {
dprintk(VIDC_WARN, "Failed to clean cache\n");
@@ -440,9 +453,14 @@
return rc;
}
-static void venus_hfi_free(struct smem_client *clnt, struct msm_smem *mem)
+static void venus_hfi_free(struct venus_hfi_device *dev, struct msm_smem *mem)
{
- msm_smem_free(clnt, mem);
+ if (!dev || !mem) {
+ dprintk(VIDC_ERR, "invalid param %p %p\n", dev, mem);
+ return;
+ }
+ venus_hfi_power_enable(dev);
+ msm_smem_free(dev->hal_client, mem);
}
static void venus_hfi_write_register(struct venus_hfi_device *device, u32 reg,
@@ -511,7 +529,7 @@
u32 ctrl_status = 0, count = 0, rc = 0;
int max_tries = 100;
venus_hfi_write_register(device,
- VIDC_WRAPPER_INTR_MASK, 0x8, 0);
+ VIDC_WRAPPER_INTR_MASK, VIDC_WRAPPER_INTR_MASK_A2HVCODEC_BMSK, 0);
venus_hfi_write_register(device,
VIDC_CPU_CS_SCIACMDARG3, 1, 0);
@@ -865,6 +883,34 @@
static DECLARE_COMPLETION(pc_prep_done);
+static int venus_hfi_halt_axi(struct venus_hfi_device *device)
+{
+ u32 reg;
+ int rc = 0;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid input: %p\n", device);
+ return -EINVAL;
+ }
+ if (venus_hfi_clk_gating_off(device)) {
+ dprintk(VIDC_ERR, "Failed to turn off clk gating\n");
+ return -EIO;
+ }
+ /* Halt AXI and AXI OCMEM VBIF Access */
+ reg = venus_hfi_read_register(device, VENUS_VBIF_AXI_HALT_CTRL0);
+ reg |= VENUS_VBIF_AXI_HALT_CTRL0_HALT_REQ;
+ venus_hfi_write_register(device, VENUS_VBIF_AXI_HALT_CTRL0, reg, 0);
+
+ /* Request for AXI bus port halt */
+ rc = readl_poll_timeout((u32)device->hal_data->register_base_addr
+ + VENUS_VBIF_AXI_HALT_CTRL1,
+ reg, reg & VENUS_VBIF_AXI_HALT_CTRL1_HALT_ACK,
+ POLL_INTERVAL_US,
+ VENUS_VBIF_AXI_HALT_ACK_TIMEOUT_US);
+ if (rc)
+ dprintk(VIDC_WARN, "AXI bus port halt timeout\n");
+ return rc;
+}
+
static inline int venus_hfi_power_off(struct venus_hfi_device *device)
{
int rc = 0;
@@ -972,6 +1018,22 @@
return rc;
}
+static int venus_hfi_power_enable(void *dev)
+{
+ int rc = 0;
+ struct venus_hfi_device *device = dev;
+ if (!device) {
+ dprintk(VIDC_ERR, "Invalid params: %p\n", device);
+ return -EINVAL;
+ }
+ mutex_lock(&device->clk_pwr_lock);
+ if (!device->power_enabled)
+ rc = venus_hfi_power_on(device);
+ mutex_unlock(&device->clk_pwr_lock);
+
+ return rc;
+}
+
static void venus_hfi_pm_hndlr(struct work_struct *work);
static DECLARE_DELAYED_WORK(venus_hfi_pm_work, venus_hfi_pm_hndlr);
@@ -1000,6 +1062,8 @@
dprintk(VIDC_ERR, "Failed venus clock enable");
goto fail_clk_power_on;
}
+ venus_hfi_write_register(device,
+ VIDC_WRAPPER_INTR_MASK, VIDC_WRAPPER_INTR_MASK_A2HVCODEC_BMSK, 0);
}
already_enabled:
device->clocks_enabled = 1;
@@ -1217,10 +1281,10 @@
(unsigned long)(mem_map[i].virtual_addr),
domain, partition, SZ_4K);
}
- venus_hfi_free(device->hal_client, device->qdss.mem_data);
+ venus_hfi_free(device, device->qdss.mem_data);
}
- venus_hfi_free(device->hal_client, device->iface_q_table.mem_data);
- venus_hfi_free(device->hal_client, device->sfr.mem_data);
+ venus_hfi_free(device, device->iface_q_table.mem_data);
+ venus_hfi_free(device, device->sfr.mem_data);
for (i = 0; i < VIDC_IFACEQ_NUMQ; i++) {
device->iface_queues[i].q_hdr = NULL;
@@ -1296,8 +1360,8 @@
int num_entries = sizeof(venus_qdss_entries)/(2 * sizeof(u32));
int domain, partition;
mem_addr = &dev->mem_addr;
- rc = venus_hfi_alloc((void *) mem_addr,
- dev->hal_client, QUEUE_SIZE, 1, 0,
+ rc = venus_hfi_alloc(dev, (void *) mem_addr,
+ QUEUE_SIZE, 1, 0,
HAL_BUFFER_INTERNAL_CMD_QUEUE);
if (rc) {
dprintk(VIDC_ERR, "iface_q_table_alloc_fail");
@@ -1323,8 +1387,8 @@
venus_hfi_set_queue_hdr_defaults(iface_q->q_hdr);
}
- rc = venus_hfi_alloc((void *) mem_addr,
- dev->hal_client, QDSS_SIZE, 1, 0,
+ rc = venus_hfi_alloc(dev, (void *) mem_addr,
+ QDSS_SIZE, 1, 0,
HAL_BUFFER_INTERNAL_CMD_QUEUE);
if (rc) {
dprintk(VIDC_WARN,
@@ -1336,8 +1400,8 @@
dev->qdss.mem_size = QDSS_SIZE;
dev->qdss.mem_data = mem_addr->mem_data;
}
- rc = venus_hfi_alloc((void *) mem_addr,
- dev->hal_client, SFR_SIZE, 1, 0,
+ rc = venus_hfi_alloc(dev, (void *) mem_addr,
+ SFR_SIZE, 1, 0,
HAL_BUFFER_INTERNAL_CMD_QUEUE);
if (rc) {
dprintk(VIDC_WARN, "sfr_alloc_fail: SFR not will work");
@@ -1402,7 +1466,7 @@
if (rc) {
dprintk(VIDC_ERR,
"IOMMU mapping failed, Freeing qdss memdata");
- venus_hfi_free(dev->hal_client, dev->qdss.mem_data);
+ venus_hfi_free(dev, dev->qdss.mem_data);
dev->qdss.mem_data = NULL;
}
if (!IS_ERR_OR_NULL(dev->qdss.align_device_addr))
@@ -1601,6 +1665,11 @@
dprintk(VIDC_DBG, "Clocks are already disabled");
goto already_disabled;
}
+ /*SYS Idle should be last message so mask any further interrupts
+ * until clocks are enabled again.*/
+ venus_hfi_write_register(device,
+ VIDC_WRAPPER_INTR_MASK,
+ VIDC_WRAPPER_INTR_MASK_A2HVCODEC_BMSK | VIDC_WRAPPER_INTR_MASK_A2HCPU_BMSK, 0);
venus_hfi_clk_disable(device);
if (!queue_delayed_work(device->venus_pm_workq, &venus_hfi_pm_work,
msecs_to_jiffies(msm_vidc_pwr_collapse_delay)))
@@ -1612,7 +1681,7 @@
static void venus_hfi_core_clear_interrupt(struct venus_hfi_device *device)
{
u32 intr_status = 0;
- int rc = 0, ctrl_status;
+ int rc = 0;
if (!device->callback)
return;
@@ -1646,19 +1715,6 @@
VIDC_CPU_CS_A2HSOFTINTCLR, 1, 0);
venus_hfi_write_register(device,
VIDC_WRAPPER_INTR_CLEAR, intr_status, 0);
- rc = venus_hfi_is_cmd_pending(device);
- ctrl_status = venus_hfi_read_register(
- device,
- VIDC_CPU_CS_SCIACMDARG0);
- dprintk(VIDC_INFO,
- "CLEAR INTERRUPT - cmd_pending %d, ctrl_status 0x%x\n",
- rc, ctrl_status);
- if ((ctrl_status & VIDC_CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK)
- && !rc) {
- dprintk(VIDC_DBG, "SYS_IDLE interrupt, disable clocks\n");
- venus_hfi_clk_gating_on(device);
- }
-
dprintk(VIDC_DBG, "Cleared WRAPPER/A2H interrupt");
err_clk_gating_off:
mutex_unlock(&device->clk_pwr_lock);
@@ -3007,9 +3063,10 @@
ocmem->vidc_ocmem_nb.notifier_call = venus_hfi_ocmem_notify_handler;
ocmem->handle =
ocmem_notifier_register(OCMEM_VIDEO, &ocmem->vidc_ocmem_nb);
- if (!ocmem->handle) {
- dprintk(VIDC_WARN, "Failed to register OCMEM notifier.");
- dprintk(VIDC_INFO, " Performance will be impacted\n");
+ if (IS_ERR_OR_NULL(ocmem->handle)) {
+ dprintk(VIDC_WARN,
+ "Failed to register OCMEM notifier. Performance might be impacted\n");
+ ocmem->handle = NULL;
}
}
@@ -3280,15 +3337,21 @@
if (device->resources.fw.cookie) {
flush_workqueue(device->vidc_workq);
flush_workqueue(device->venus_pm_workq);
+ subsystem_put(device->resources.fw.cookie);
+ venus_hfi_interface_queues_release(dev);
+ /* IOMMU operations need to be done before AXI halt.*/
+ venus_hfi_iommu_detach(device);
+ /* Halt the AXI to make sure there are no pending transactions.
+ * Clocks should be unprepared after making sure axi is halted.
+ */
+ if(venus_hfi_halt_axi(device))
+ dprintk(VIDC_WARN, "Failed to halt AXI\n");
venus_hfi_disable_clks(device);
mutex_lock(&device->clk_pwr_lock);
- subsystem_put(device->resources.fw.cookie);
regulator_disable(device->gdsc);
device->power_enabled = 0;
--device->pwr_cnt;
mutex_unlock(&device->clk_pwr_lock);
- venus_hfi_interface_queues_release(dev);
- venus_hfi_iommu_detach(device);
device->resources.fw.cookie = NULL;
}
}
@@ -3581,6 +3644,7 @@
hdev->get_stride_scanline = venus_hfi_get_stride_scanline;
hdev->capability_check = venus_hfi_capability_check;
hdev->get_core_capabilities = venus_hfi_get_core_capabilities;
+ hdev->power_enable = venus_hfi_power_enable;
}
int venus_hfi_initialize(struct hfi_device *hdev, u32 device_id,
diff --git a/drivers/media/platform/msm/vidc/vidc_hfi_api.h b/drivers/media/platform/msm/vidc/vidc_hfi_api.h
index ee83eee..846171e 100644
--- a/drivers/media/platform/msm/vidc/vidc_hfi_api.h
+++ b/drivers/media/platform/msm/vidc/vidc_hfi_api.h
@@ -1130,6 +1130,7 @@
u32 *max_width, u32 *max_height);
int (*session_clean)(void *sess);
int (*get_core_capabilities)(void);
+ int (*power_enable)(void *dev);
};
typedef void (*hfi_cmd_response_callback) (enum command_response cmd,
diff --git a/drivers/media/platform/msm/vidc/vidc_hfi_io.h b/drivers/media/platform/msm/vidc/vidc_hfi_io.h
index 6377fbf..b811948 100644
--- a/drivers/media/platform/msm/vidc/vidc_hfi_io.h
+++ b/drivers/media/platform/msm/vidc/vidc_hfi_io.h
@@ -88,8 +88,10 @@
#define VIDC_WRAPPER_INTR_MASK (VIDC_WRAPPER_BASE_OFFS + 0x10)
#define VIDC_WRAPPER_INTR_MASK_A2HWD_BMSK 0x10
#define VIDC_WRAPPER_INTR_MASK_A2HWD_SHFT 0x4
-#define VIDC_WRAPPER_INTR_MASK_A2H_BMSK 0x4
-#define VIDC_WRAPPER_INTR_MASK_A2H_SHFT 0x2
+#define VIDC_WRAPPER_INTR_MASK_A2HVCODEC_BMSK 0x8
+#define VIDC_WRAPPER_INTR_MASK_A2HVCODEC_SHFT 0x3
+#define VIDC_WRAPPER_INTR_MASK_A2HCPU_BMSK 0x4
+#define VIDC_WRAPPER_INTR_MASK_A2HCPU_SHFT 0x2
#define VIDC_WRAPPER_INTR_CLEAR (VIDC_WRAPPER_BASE_OFFS + 0x14)
#define VIDC_WRAPPER_INTR_CLEAR_A2HWD_BMSK 0x10
@@ -131,6 +133,15 @@
#define VIDC_VBIF_AT_OLD_HIGH (VIDC_VBIF_BASE_OFFS + 0xC08)
#define VIDC_VBIF_AT_NEW_BASE (VIDC_VBIF_BASE_OFFS + 0xC10)
#define VIDC_VBIF_AT_NEW_HIGH (VIDC_VBIF_BASE_OFFS + 0xC18)
+#define VENUS_VBIF_AXI_HALT_CTRL0 (VIDC_VBIF_BASE_OFFS + 0x208)
+#define VENUS_VBIF_AXI_HALT_CTRL1 (VIDC_VBIF_BASE_OFFS + 0x20C)
+
+#define VENUS_VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
+#define VENUS_VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
+#define VENUS_VBIF_AXI_HALT_ACK_TIMEOUT_US 500000
+/* Poll interval in uS */
+#define POLL_INTERVAL_US 50
+
#define VIDC_VENUS0_WRAPPER_VBIF_REQ_PRIORITY \
(VIDC_WRAPPER_BASE_OFFS + 0x20)
diff --git a/drivers/media/radio/radio-iris.c b/drivers/media/radio/radio-iris.c
index 9e25e42..a554749 100644
--- a/drivers/media/radio/radio-iris.c
+++ b/drivers/media/radio/radio-iris.c
@@ -496,8 +496,15 @@
static void iris_q_event(struct iris_device *radio,
enum iris_evt_t event)
{
- struct kfifo *data_b = &radio->data_buf[IRIS_BUF_EVENTS];
+ struct kfifo *data_b;
unsigned char evt = event;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
+ data_b = &radio->data_buf[IRIS_BUF_EVENTS];
if (kfifo_in_locked(data_b, &evt, 1, &radio->buf_lock[IRIS_BUF_EVENTS]))
wake_up_interruptible(&radio->event_queue);
}
@@ -582,8 +589,6 @@
skb_queue_head_init(&hdev->cmd_q);
skb_queue_head_init(&hdev->raw_q);
- if (!radio)
- FMDERR(":radio is null");
radio->fm_hdev = hdev;
@@ -674,6 +679,10 @@
struct iris_device *radio = video_get_drvdata(video_get_dev());
__u16 opcode = 0;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
opcode = hci_opcode_pack(HCI_OGF_FM_DIAGNOSTIC_CMD_REQ,
HCI_FM_SET_INTERNAL_TONE_GENRATOR);
return radio_hci_send_cmd(hdev, opcode,
@@ -1144,7 +1153,7 @@
return radio_hci_send_cmd(hdev, opcode, 0, NULL);
}
-static int radio_hci_err(__u16 code)
+static int radio_hci_err(__u32 code)
{
switch (code) {
case 0:
@@ -1642,6 +1651,11 @@
__u8 status = *((__u8 *) skb->data);
struct iris_device *radio = video_get_drvdata(video_get_dev());
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
if ((radio->mode == FM_TURNING_OFF) && (status == 0)) {
iris_q_event(radio, IRIS_EVT_RADIO_DISABLED);
radio_hci_req_complete(hdev, status);
@@ -1659,6 +1673,10 @@
struct hci_fm_conf_rsp *rsp = (void *)skb->data;
struct iris_device *radio = video_get_drvdata(video_get_dev());
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
if (rsp->status)
return;
@@ -1672,6 +1690,11 @@
struct hci_fm_get_trans_conf_rsp *rsp = (void *)skb->data;
struct iris_device *radio = video_get_drvdata(video_get_dev());
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
if (rsp->status)
return;
memcpy((void *)&radio->trans_conf, (void*)&rsp->trans_conf_rsp,
@@ -1685,6 +1708,11 @@
struct hci_fm_conf_rsp *rsp = (void *)skb->data;
struct iris_device *radio = video_get_drvdata(video_get_dev());
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
if (rsp->status) {
radio_hci_req_complete(hdev, rsp->status);
return;
@@ -1707,6 +1735,11 @@
struct hci_fm_conf_rsp *rsp = (void *)skb->data;
struct iris_device *radio = video_get_drvdata(video_get_dev());
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
if (rsp->status)
return;
@@ -1722,6 +1755,11 @@
struct hci_fm_sig_threshold_rsp *rsp = (void *)skb->data;
struct iris_device *radio = video_get_drvdata(video_get_dev());
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
if (rsp->status)
return;
@@ -1733,6 +1771,12 @@
{
struct iris_device *radio = video_get_drvdata(video_get_dev());
struct hci_fm_station_rsp *rsp = (void *)skb->data;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
radio->fm_st_rsp = *(rsp);
/* Tune is always succesful */
@@ -1772,9 +1816,16 @@
static void hci_cc_feature_list_rsp(struct radio_hci_dev *hdev,
struct sk_buff *skb)
{
+ struct v4l2_capability *v4l_cap;
struct hci_fm_feature_list_rsp *rsp = (void *)skb->data;
struct iris_device *radio = video_get_drvdata(video_get_dev());
- struct v4l2_capability *v4l_cap = radio->g_cap;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
+ v4l_cap = radio->g_cap;
if (rsp->status)
return;
@@ -1789,8 +1840,13 @@
{
struct iris_device *radio = video_get_drvdata(video_get_dev());
struct hci_fm_dbg_param_rsp *rsp = (void *)skb->data;
- radio->st_dbg_param = *(rsp);
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
+ radio->st_dbg_param = *(rsp);
if (radio->st_dbg_param.status)
return;
@@ -1800,7 +1856,13 @@
static void iris_q_evt_data(struct iris_device *radio,
char *data, int len, int event)
{
- struct kfifo *data_b = &radio->data_buf[event];
+ struct kfifo *data_b;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+ data_b = &radio->data_buf[event];
if (kfifo_in_locked(data_b, data, len, &radio->buf_lock[event]))
wake_up_interruptible(&radio->event_queue);
}
@@ -1837,6 +1899,11 @@
__u8 status = *((__u8 *) skb->data);
__u8 len;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
+
if (status)
return;
len = skb->data[1];
@@ -1917,6 +1984,11 @@
{
struct iris_device *radio = video_get_drvdata(video_get_dev());
u8 status = skb->data[0];
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
if (status) {
FMDERR("status = %d", status);
return;
@@ -2050,6 +2122,10 @@
int i;
struct iris_device *radio = video_get_drvdata(video_get_dev());
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
memcpy(&radio->fm_st_rsp.station_rsp, &skb->data[0],
sizeof(struct hci_ev_tune_status));
iris_q_event(radio, IRIS_EVT_TUNE_SUCC);
@@ -2092,6 +2168,10 @@
int abs_freq;
int len;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
ev = kmalloc(sizeof(*ev), GFP_ATOMIC);
if (!ev) {
FMDERR("Memory allocation failed");
@@ -2150,6 +2230,10 @@
radio = video_get_drvdata(video_get_dev());
index = RDSGRP_DATA_OFFSET;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return;
+ }
for (blocknum = 0; blocknum < RDS_BLOCKS_NUM; blocknum++) {
temp.rdsBlk[blocknum].rdsLsb =
(skb->data[index]);
@@ -2556,9 +2640,15 @@
static int iris_search(struct iris_device *radio, int on, int dir)
{
int retval = 0;
- enum search_t srch = radio->g_search_mode & SRCH_MODE;
- radio->search_on = on;
+ enum search_t srch;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
+ srch = radio->g_search_mode & SRCH_MODE;
+ radio->search_on = on;
if (on) {
switch (srch) {
case SCAN_FOR_STRONG:
@@ -2600,6 +2690,12 @@
int rds_grps_proc = 0x00;
int retval = 0;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
if (radio->power_mode != power_mode) {
if (power_mode) {
@@ -2638,6 +2734,12 @@
static int iris_recv_set_region(struct iris_device *radio, int req_region)
{
int retval;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
radio->region = req_region;
retval = hci_set_fm_recv_conf(
@@ -2651,6 +2753,11 @@
static int iris_trans_set_region(struct iris_device *radio, int req_region)
{
int retval;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
radio->region = req_region;
retval = hci_set_fm_trans_conf(
@@ -2664,6 +2771,11 @@
{
int retval;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
retval = hci_fm_tune_station(&freq, radio->fm_hdev);
if (retval < 0)
FMDERR("Error while setting the frequency : %d\n", retval);
@@ -2693,6 +2805,11 @@
char cal_mode = 0x00;
int retval = 0x00;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
cal_mode = PROCS_CALIB_MODE;
radio->mode = FM_CALIB;
retval = hci_cmd(HCI_FM_ENABLE_RECV_CMD,
@@ -2727,6 +2844,11 @@
struct hci_fm_def_data_rd_req rd;
int lsb, msb;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
switch (ctrl->id) {
case V4L2_CID_AUDIO_VOLUME:
break;
@@ -3012,6 +3134,11 @@
struct iris_device *radio = video_get_drvdata(video_devdata(file));
struct hci_fm_def_data_rd_req default_data_rd;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
switch ((ctrl->controls[0]).id) {
case V4L2_CID_PRIVATE_IRIS_READ_DEFAULT:
data = (ctrl->controls[0]).string;
@@ -3041,6 +3168,10 @@
struct iris_device *radio = video_get_drvdata(video_devdata(file));
char *data = NULL;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
switch ((ctrl->controls[0]).id) {
case V4L2_CID_RDS_TX_PS_NAME:
FMDBG("In V4L2_CID_RDS_TX_PS_NAME\n");
@@ -3164,6 +3295,11 @@
char sinr_th, sinr;
__u8 intf_det_low_th, intf_det_high_th, intf_det_out;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
switch (ctrl->id) {
case V4L2_CID_PRIVATE_IRIS_TX_TONE:
radio->tone_freq = ctrl->value;
@@ -3846,6 +3982,10 @@
/* Pass the mode of SPUR_CLK */
default_data.mode = CKK_SPUR;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
temp = radio->spur_table_size;
for (cnt = 0; cnt < (temp / 5); cnt++) {
offset = 0;
@@ -3916,6 +4056,10 @@
int retval;
struct iris_device *radio = video_get_drvdata(video_devdata(file));
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
if (tuner->index > 0) {
FMDERR("Invalid Tuner Index");
return -EINVAL;
@@ -3959,6 +4103,12 @@
{
struct iris_device *radio = video_get_drvdata(video_devdata(file));
int retval = 0;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
if (tuner->index > 0)
return -EINVAL;
@@ -4010,6 +4160,10 @@
int retval = -1;
freq->frequency = freq->frequency / TUNE_PARAM;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
if (freq->type != V4L2_TUNER_RADIO)
return -EINVAL;
@@ -4137,6 +4291,11 @@
{
struct iris_device *radio;
radio = video_get_drvdata(video_devdata(file));
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
strlcpy(capability->driver, DRIVER_NAME, sizeof(capability->driver));
strlcpy(capability->card, DRIVER_CARD, sizeof(capability->card));
capability->capabilities = V4L2_CAP_TUNER | V4L2_CAP_RADIO;
@@ -4148,6 +4307,11 @@
{
int retval;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
radio->mute_mode.soft_mute = CTRL_ON;
retval = hci_set_fm_mute_mode(&radio->mute_mode,
radio->fm_hdev);
@@ -4185,7 +4349,14 @@
static int initialise_trans(struct iris_device *radio)
{
- int retval = hci_cmd(HCI_FM_GET_TX_CONFIG, radio->fm_hdev);
+ int retval;
+
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
+ retval = hci_cmd(HCI_FM_GET_TX_CONFIG, radio->fm_hdev);
if (retval < 0)
FMDERR("get frequency failed %d\n", retval);
@@ -4196,6 +4367,11 @@
{
int retval = 1;
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
+
if (radio->mode == FM_OFF || radio->mode == FM_RECV)
retval = 0;
@@ -4338,6 +4514,10 @@
int i;
struct iris_device *radio = platform_get_drvdata(pdev);
+ if (radio == NULL) {
+ FMDERR(":radio is null");
+ return -EINVAL;
+ }
video_unregister_device(radio->videodev);
for (i = 0; i < IRIS_BUF_MAX; i++)
diff --git a/drivers/media/video/v4l2-ctrls.c b/drivers/media/video/v4l2-ctrls.c
index 9dd06ee..127a231 100644
--- a/drivers/media/video/v4l2-ctrls.c
+++ b/drivers/media/video/v4l2-ctrls.c
@@ -310,6 +310,7 @@
"Scalable High",
"Scalable High Intra",
"Multiview High",
+ "Constrained High",
NULL,
};
static const char * const vui_sar_idc[] = {
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index 093b001..0bc18fb 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -251,6 +251,12 @@
break;
}
spin_unlock_irqrestore(&qseecom.registered_listener_list_lock, flags);
+
+ if ((entry != NULL) && (entry->svc.listener_id != listener_id)) {
+ pr_err("Service id: %u is not found\n", listener_id);
+ return NULL;
+ }
+
return entry;
}
@@ -494,6 +500,11 @@
}
spin_unlock_irqrestore(&qseecom.registered_listener_list_lock,
flags);
+
+ if (ptr_svc == NULL) {
+ pr_err("Listener Svc %d does not exist\n", lstnr);
+ return -EINVAL;
+ }
if (ptr_svc->svc.listener_id != lstnr) {
pr_warning("Service requested for does on exist\n");
return -ERESTARTSYS;
@@ -855,14 +866,42 @@
struct qseecom_client_send_service_ireq *send_svc_ireq_ptr)
{
int ret = 0;
+ void *req_buf = NULL;
+
if ((req_ptr == NULL) || (send_svc_ireq_ptr == NULL)) {
pr_err("Error with pointer: req_ptr = %p, send_svc_ptr = %p\n",
req_ptr, send_svc_ireq_ptr);
return -EINVAL;
}
+
+ if ((!req_ptr->cmd_req_buf) || (!req_ptr->resp_buf)) {
+ pr_err("Invalid req/resp buffer, exiting\n");
+ return -EINVAL;
+ }
+
+ if (((uint32_t)req_ptr->cmd_req_buf <
+ data_ptr->client.user_virt_sb_base)
+ || ((uint32_t)req_ptr->cmd_req_buf >=
+ (data_ptr->client.user_virt_sb_base +
+ data_ptr->client.sb_length))) {
+ pr_err("cmd buffer address not within shared bufffer\n");
+ return -EINVAL;
+ }
+
+
+ if (((uint32_t)req_ptr->resp_buf < data_ptr->client.user_virt_sb_base)
+ || ((uint32_t)req_ptr->resp_buf >=
+ (data_ptr->client.user_virt_sb_base +
+ data_ptr->client.sb_length))){
+ pr_err("response buffer address not within shared bufffer\n");
+ return -EINVAL;
+ }
+
+ req_buf = data_ptr->client.sb_virt;
+
send_svc_ireq_ptr->qsee_cmd_id = req_ptr->cmd_id;
send_svc_ireq_ptr->key_type =
- ((struct qseecom_rpmb_provision_key *)req_ptr->cmd_req_buf)->key_type;
+ ((struct qseecom_rpmb_provision_key *)req_buf)->key_type;
send_svc_ireq_ptr->req_len = req_ptr->cmd_req_len;
send_svc_ireq_ptr->rsp_ptr = (void *)(__qseecom_uvirt_to_kphys(data_ptr,
(uint32_t)req_ptr->resp_buf));
@@ -1063,8 +1102,6 @@
if (ret)
return ret;
- pr_debug("sending cmd_req->rsp size: %u, ptr: 0x%p\n",
- req.resp_len, req.resp_buf);
return ret;
}
@@ -1254,8 +1291,7 @@
ret = __qseecom_update_cmd_buf(&req, true, data, false);
if (ret)
return ret;
- pr_debug("sending cmd_req->rsp size: %u, ptr: 0x%p\n",
- req.resp_len, req.resp_buf);
+
return ret;
}
@@ -1273,6 +1309,11 @@
struct qseecom_registered_listener_list *this_lstnr;
this_lstnr = __qseecom_find_svc(data->listener.id);
+ if (!this_lstnr) {
+ pr_err("Invalid listener ID\n");
+ return -ENODATA;
+ }
+
while (1) {
if (wait_event_freezable(this_lstnr->rcv_req_wq,
__qseecom_listener_has_rcvd_req(data,
diff --git a/drivers/misc/smsc_hub.c b/drivers/misc/smsc_hub.c
index 0147e66..6f98dc7 100644
--- a/drivers/misc/smsc_hub.c
+++ b/drivers/misc/smsc_hub.c
@@ -385,26 +385,27 @@
static int __devinit smsc_hub_probe(struct platform_device *pdev)
{
int ret = 0;
- const struct smsc_hub_platform_data *pdata;
+ struct smsc_hub_platform_data *pdata;
struct device_node *node = pdev->dev.of_node;
struct i2c_adapter *i2c_adap;
struct i2c_board_info i2c_info;
+ struct of_dev_auxdata *hsic_host_auxdata;
if (pdev->dev.of_node) {
dev_dbg(&pdev->dev, "device tree enabled\n");
- pdev->dev.platform_data = msm_hub_dt_to_pdata(pdev);
- if (IS_ERR(pdev->dev.platform_data))
- return PTR_ERR(pdev->dev.platform_data);
-
- dev_set_name(&pdev->dev, smsc_hub_driver.driver.name);
+ hsic_host_auxdata = dev_get_platdata(&pdev->dev);
+ pdata = msm_hub_dt_to_pdata(pdev);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+ } else {
+ pdata = pdev->dev.platform_data;
}
- if (!pdev->dev.platform_data) {
+ if (!pdata) {
dev_err(&pdev->dev, "No platform data\n");
return -ENODEV;
}
- pdata = pdev->dev.platform_data;
if (!pdata->hub_reset)
return -EINVAL;
@@ -413,7 +414,7 @@
return -ENOMEM;
smsc_hub->dev = &pdev->dev;
- smsc_hub->pdata = pdev->dev.platform_data;
+ smsc_hub->pdata = pdata;
smsc_hub->hub_vbus_reg = devm_regulator_get(&pdev->dev, "hub_vbus");
ret = PTR_ERR(smsc_hub->hub_vbus_reg);
@@ -494,7 +495,7 @@
i2c_put_adapter(i2c_adap);
i2c_add_fail:
- ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
+ ret = of_platform_populate(node, NULL, hsic_host_auxdata, &pdev->dev);
if (ret) {
dev_err(&pdev->dev, "failed to add child node, ret=%d\n", ret);
goto uninit_gpio;
@@ -523,7 +524,7 @@
{
const struct smsc_hub_platform_data *pdata;
- pdata = pdev->dev.platform_data;
+ pdata = smsc_hub->pdata;
if (smsc_hub->client) {
i2c_unregister_device(smsc_hub->client);
smsc_hub->client = NULL;
diff --git a/drivers/misc/tspp.c b/drivers/misc/tspp.c
index 3d69473..19f26f2 100644
--- a/drivers/misc/tspp.c
+++ b/drivers/misc/tspp.c
@@ -1706,6 +1706,8 @@
dma_free_coherent(NULL, config->desc.size, config->desc.base,
config->desc.phys_base);
+ sps_free_endpoint(channel->pipe);
+
tspp_destroy_buffers(channel_id, channel);
if (channel->dma_pool) {
dma_pool_destroy(channel->dma_pool);
diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
index eb5d365..b36faff 100644
--- a/drivers/mmc/core/bus.c
+++ b/drivers/mmc/core/bus.c
@@ -414,14 +414,12 @@
#endif
mmc_init_context_info(card->host);
- if (mmc_use_core_runtime_pm(card->host)) {
- ret = pm_runtime_set_active(&card->dev);
- if (ret)
- pr_err("%s: %s: failed setting runtime active: ret: %d\n",
- mmc_hostname(card->host), __func__, ret);
- else if (!mmc_card_sdio(card))
- pm_runtime_enable(&card->dev);
- }
+ ret = pm_runtime_set_active(&card->dev);
+ if (ret)
+ pr_err("%s: %s: failed setting runtime active: ret: %d\n",
+ mmc_hostname(card->host), __func__, ret);
+ else if (!mmc_card_sdio(card) && mmc_use_core_runtime_pm(card->host))
+ pm_runtime_enable(&card->dev);
ret = device_add(&card->dev);
if (ret)
@@ -469,6 +467,7 @@
}
kfree(card->wr_pack_stats.packing_events);
+ kfree(card->cached_ext_csd);
put_device(&card->dev);
}
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index edd6a5d..c7fa876 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -78,7 +78,7 @@
struct mmc_host *host = cls_dev_to_mmc_host(dev);
int ret = 0;
- if (!mmc_use_core_runtime_pm(host))
+ if (!mmc_use_core_pm(host))
return 0;
if (!pm_runtime_suspended(dev)) {
@@ -95,7 +95,7 @@
struct mmc_host *host = cls_dev_to_mmc_host(dev);
int ret = 0;
- if (!mmc_use_core_runtime_pm(host))
+ if (!mmc_use_core_pm(host))
return 0;
if (!pm_runtime_suspended(dev)) {
@@ -686,14 +686,13 @@
WARN_ON((host->caps & MMC_CAP_SDIO_IRQ) &&
!host->ops->enable_sdio_irq);
- if (mmc_use_core_runtime_pm(host)) {
- err = pm_runtime_set_active(&host->class_dev);
- if (err)
- pr_err("%s: %s: failed setting runtime active: err: %d\n",
- mmc_hostname(host), __func__, err);
- else
- pm_runtime_enable(&host->class_dev);
- }
+ err = pm_runtime_set_active(&host->class_dev);
+ if (err)
+ pr_err("%s: %s: failed setting runtime active: err: %d\n",
+ mmc_hostname(host), __func__, err);
+ else if (mmc_use_core_runtime_pm(host))
+ pm_runtime_enable(&host->class_dev);
+
err = device_add(&host->class_dev);
if (err)
return err;
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 997e14b..b295bb8 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1189,9 +1189,9 @@
mmc_set_timing(card->host, MMC_TIMING_LEGACY);
mmc_set_clock(card->host, MMC_HIGH_26_MAX_DTR);
- err = mmc_select_hs(card, &card->cached_ext_csd);
+ err = mmc_select_hs(card, card->cached_ext_csd);
} else {
- err = mmc_select_hs400(card, &card->cached_ext_csd);
+ err = mmc_select_hs400(card, card->cached_ext_csd);
}
return err;
@@ -1439,7 +1439,7 @@
err = mmc_get_ext_csd(card, &ext_csd);
if (err)
goto free_card;
- memcpy(&card->cached_ext_csd, ext_csd, sizeof(card->ext_csd));
+ card->cached_ext_csd = ext_csd;
err = mmc_read_ext_csd(card, ext_csd);
if (err)
goto free_card;
@@ -1637,15 +1637,12 @@
if (!oldcard)
host->card = card;
- mmc_free_ext_csd(ext_csd);
return 0;
free_card:
if (!oldcard)
mmc_remove_card(card);
err:
- mmc_free_ext_csd(ext_csd);
-
return err;
}
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index b93eaf4..e391a06 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -317,6 +317,7 @@
bool tuning_done;
bool calibration_done;
u8 saved_tuning_phase;
+ atomic_t controller_clock;
};
enum vdd_io_level {
@@ -2213,6 +2214,50 @@
return sel_clk;
}
+static int sdhci_msm_enable_controller_clock(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_msm_host *msm_host = pltfm_host->priv;
+ int rc = 0;
+
+ if (atomic_read(&msm_host->controller_clock))
+ return 0;
+
+ sdhci_msm_bus_voting(host, 1);
+
+ if (!IS_ERR(msm_host->pclk)) {
+ rc = clk_prepare_enable(msm_host->pclk);
+ if (rc) {
+ pr_err("%s: %s: failed to enable the pclk with error %d\n",
+ mmc_hostname(host->mmc), __func__, rc);
+ goto remove_vote;
+ }
+ }
+
+ rc = clk_prepare_enable(msm_host->clk);
+ if (rc) {
+ pr_err("%s: %s: failed to enable the host-clk with error %d\n",
+ mmc_hostname(host->mmc), __func__, rc);
+ goto disable_pclk;
+ }
+
+ atomic_set(&msm_host->controller_clock, 1);
+ pr_debug("%s: %s: enabled controller clock\n",
+ mmc_hostname(host->mmc), __func__);
+ goto out;
+
+disable_pclk:
+ if (!IS_ERR(msm_host->pclk))
+ clk_disable_unprepare(msm_host->pclk);
+remove_vote:
+ if (msm_host->msm_bus_vote.client_handle)
+ sdhci_msm_bus_cancel_work_and_set_vote(host, 0);
+out:
+ return rc;
+}
+
+
+
static int sdhci_msm_prepare_clocks(struct sdhci_host *host, bool enable)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -2223,36 +2268,32 @@
pr_debug("%s: request to enable clocks\n",
mmc_hostname(host->mmc));
- sdhci_msm_bus_voting(host, 1);
+ /*
+ * The bus-width or the clock rate might have changed
+ * after controller clocks are enbaled, update bus vote
+ * in such case.
+ */
+ if (atomic_read(&msm_host->controller_clock))
+ sdhci_msm_bus_voting(host, 1);
+
+ rc = sdhci_msm_enable_controller_clock(host);
+ if (rc)
+ goto remove_vote;
if (!IS_ERR_OR_NULL(msm_host->bus_clk)) {
rc = clk_prepare_enable(msm_host->bus_clk);
if (rc) {
pr_err("%s: %s: failed to enable the bus-clock with error %d\n",
mmc_hostname(host->mmc), __func__, rc);
- goto remove_vote;
+ goto disable_controller_clk;
}
}
- if (!IS_ERR(msm_host->pclk)) {
- rc = clk_prepare_enable(msm_host->pclk);
- if (rc) {
- pr_err("%s: %s: failed to enable the pclk with error %d\n",
- mmc_hostname(host->mmc), __func__, rc);
- goto disable_bus_clk;
- }
- }
- rc = clk_prepare_enable(msm_host->clk);
- if (rc) {
- pr_err("%s: %s: failed to enable the host-clk with error %d\n",
- mmc_hostname(host->mmc), __func__, rc);
- goto disable_pclk;
- }
if (!IS_ERR(msm_host->ff_clk)) {
rc = clk_prepare_enable(msm_host->ff_clk);
if (rc) {
pr_err("%s: %s: failed to enable the ff_clk with error %d\n",
mmc_hostname(host->mmc), __func__, rc);
- goto disable_clk;
+ goto disable_bus_clk;
}
}
if (!IS_ERR(msm_host->sleep_clk)) {
@@ -2280,6 +2321,7 @@
if (!IS_ERR_OR_NULL(msm_host->bus_clk))
clk_disable_unprepare(msm_host->bus_clk);
+ atomic_set(&msm_host->controller_clock, 0);
sdhci_msm_bus_voting(host, 0);
}
atomic_set(&msm_host->clks_on, enable);
@@ -2287,15 +2329,15 @@
disable_ff_clk:
if (!IS_ERR_OR_NULL(msm_host->ff_clk))
clk_disable_unprepare(msm_host->ff_clk);
-disable_clk:
- if (!IS_ERR_OR_NULL(msm_host->clk))
- clk_disable_unprepare(msm_host->clk);
-disable_pclk:
- if (!IS_ERR_OR_NULL(msm_host->pclk))
- clk_disable_unprepare(msm_host->pclk);
disable_bus_clk:
if (!IS_ERR_OR_NULL(msm_host->bus_clk))
clk_disable_unprepare(msm_host->bus_clk);
+disable_controller_clk:
+ if (!IS_ERR_OR_NULL(msm_host->clk))
+ clk_disable_unprepare(msm_host->clk);
+ if (!IS_ERR_OR_NULL(msm_host->pclk))
+ clk_disable_unprepare(msm_host->pclk);
+ atomic_set(&msm_host->controller_clock, 0);
remove_vote:
if (msm_host->msm_bus_vote.client_handle)
sdhci_msm_bus_cancel_work_and_set_vote(host, 0);
@@ -2558,6 +2600,7 @@
.get_min_clock = sdhci_msm_get_min_clock,
.get_max_clock = sdhci_msm_get_max_clock,
.disable_data_xfer = sdhci_msm_disable_data_xfer,
+ .enable_controller_clock = sdhci_msm_enable_controller_clock,
};
static int __devinit sdhci_msm_probe(struct platform_device *pdev)
@@ -2637,6 +2680,7 @@
if (ret)
goto bus_clk_disable;
}
+ atomic_set(&msm_host->controller_clock, 1);
/* Setup SDC MMC clock */
msm_host->clk = devm_clk_get(&pdev->dev, "core_clk");
@@ -2840,6 +2884,7 @@
msm_host->mmc->caps2 |= MMC_CAP2_CLK_SCALE;
msm_host->mmc->caps2 |= MMC_CAP2_STOP_REQUEST;
msm_host->mmc->caps2 |= MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE;
+ msm_host->mmc->caps2 |= MMC_CAP2_CORE_PM;
msm_host->mmc->pm_caps |= MMC_PM_KEEP_POWER;
if (msm_host->pdata->nonremovable)
@@ -2896,7 +2941,7 @@
if (ret)
pr_err("%s: %s: pm_runtime_set_active failed: err: %d\n",
mmc_hostname(host->mmc), __func__, ret);
- else
+ else if (mmc_use_core_runtime_pm(host->mmc))
pm_runtime_enable(&pdev->dev);
/* Successful initialization */
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 513ddfb..830223d 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1577,6 +1577,7 @@
unsigned long flags;
int vdd_bit = -1;
u8 ctrl;
+ int ret;
mutex_lock(&host->ios_mutex);
if (host->flags & SDHCI_DEVICE_DEAD) {
@@ -1589,6 +1590,29 @@
if (ios->clock)
sdhci_set_clock(host, ios->clock);
+ /*
+ * The controller clocks may be off during power-up and we may end up
+ * enabling card clock before giving power to the card. Hence, during
+ * MMC_POWER_UP enable the controller clock and turn-on the regulators.
+ * The mmc_power_up would provide the necessary delay before turning on
+ * the clocks to the card.
+ */
+ if (ios->power_mode & MMC_POWER_UP) {
+ if (host->ops->enable_controller_clock) {
+ ret = host->ops->enable_controller_clock(host);
+ if (ret) {
+ pr_err("%s: enabling controller clock: failed: %d\n",
+ mmc_hostname(host->mmc), ret);
+ } else {
+ vdd_bit = sdhci_set_power(host, ios->vdd);
+
+ if (host->vmmc && vdd_bit != -1)
+ mmc_regulator_set_ocr(host->mmc,
+ host->vmmc,
+ vdd_bit);
+ }
+ }
+ }
spin_lock_irqsave(&host->lock, flags);
if (!host->clock) {
spin_unlock_irqrestore(&host->lock, flags);
@@ -1597,14 +1621,16 @@
}
spin_unlock_irqrestore(&host->lock, flags);
- if (ios->power_mode & (MMC_POWER_UP | MMC_POWER_ON))
+ if (!host->ops->enable_controller_clock && (ios->power_mode &
+ (MMC_POWER_UP |
+ MMC_POWER_ON))) {
vdd_bit = sdhci_set_power(host, ios->vdd);
- if (host->vmmc && vdd_bit != -1)
- mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
+ if (host->vmmc && vdd_bit != -1)
+ mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
+ }
spin_lock_irqsave(&host->lock, flags);
-
if (host->ops->platform_send_init_74_clocks)
host->ops->platform_send_init_74_clocks(host, ios->power_mode);
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 3db99c4..db4806d 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -295,6 +295,7 @@
unsigned int (*get_max_segments)(void);
void (*platform_bus_voting)(struct sdhci_host *host, u32 enable);
void (*disable_data_xfer)(struct sdhci_host *host);
+ int (*enable_controller_clock)(struct sdhci_host *host);
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
diff --git a/drivers/net/wireless/wcnss/wcnss_wlan.c b/drivers/net/wireless/wcnss/wcnss_wlan.c
index 8dc30ee..76eb15b 100644
--- a/drivers/net/wireless/wcnss/wcnss_wlan.c
+++ b/drivers/net/wireless/wcnss/wcnss_wlan.c
@@ -142,6 +142,7 @@
#define MSM_PRONTO_PLL_BASE 0xfb21b1c0
#define PRONTO_PLL_STATUS_OFFSET 0x1c
+#define MSM_PRONTO_TXP_STATUS 0xfb08040c
#define MSM_PRONTO_TXP_PHY_ABORT 0xfb080488
#define MSM_PRONTO_BRDG_ERR_SRC 0xfb080fb0
@@ -154,6 +155,7 @@
#define WCNSS_CTRL_CHANNEL "WCNSS_CTRL"
#define WCNSS_MAX_FRAME_SIZE (4*1024)
#define WCNSS_VERSION_LEN 30
+#define WCNSS_MAX_BUILD_VER_LEN 256
/* message types */
#define WCNSS_CTRL_MSG_START 0x01000000
@@ -166,6 +168,8 @@
#define WCNSS_CALDATA_DNLD_REQ (WCNSS_CTRL_MSG_START + 6)
#define WCNSS_CALDATA_DNLD_RSP (WCNSS_CTRL_MSG_START + 7)
#define WCNSS_VBATT_LEVEL_IND (WCNSS_CTRL_MSG_START + 8)
+#define WCNSS_BUILD_VER_REQ (WCNSS_CTRL_MSG_START + 9)
+#define WCNSS_BUILD_VER_RSP (WCNSS_CTRL_MSG_START + 10)
#define VALID_VERSION(version) \
@@ -339,10 +343,10 @@
void __iomem *pronto_ccpu_base;
void __iomem *pronto_saw2_base;
void __iomem *pronto_pll_base;
+ void __iomem *wlan_tx_status;
void __iomem *wlan_tx_phy_aborts;
void __iomem *wlan_brdg_err_source;
void __iomem *fiq_reg;
- int ssr_boot;
int nv_downloaded;
unsigned char *fw_cal_data;
unsigned char *user_cal_data;
@@ -515,6 +519,10 @@
pr_info_ratelimited("%s: PRONTO_PMU_SOFT_RESET %08x\n",
__func__, reg);
+ reg_addr = penv->pronto_saw2_base + PRONTO_SAW2_SPM_STS_OFFSET;
+ reg = readl_relaxed(reg_addr);
+ pr_info_ratelimited("%s: PRONTO_SAW2_SPM_STS %08x\n", __func__, reg);
+
reg_addr = penv->msm_wcnss_base + PRONTO_PMU_COM_GDSCR_OFFSET;
reg = readl_relaxed(reg_addr);
pr_info_ratelimited("%s: PRONTO_PMU_COM_GDSCR %08x\n",
@@ -563,10 +571,6 @@
reg = readl_relaxed(reg_addr);
pr_info_ratelimited("%s: CCU_CCPU_LAST_ADDR2 %08x\n", __func__, reg);
- reg_addr = penv->pronto_saw2_base + PRONTO_SAW2_SPM_STS_OFFSET;
- reg = readl_relaxed(reg_addr);
- pr_info_ratelimited("%s: PRONTO_SAW2_SPM_STS %08x\n", __func__, reg);
-
reg_addr = penv->pronto_pll_base + PRONTO_PLL_STATUS_OFFSET;
reg = readl_relaxed(reg_addr);
pr_info_ratelimited("%s: PRONTO_PLL_STATUS %08x\n", __func__, reg);
@@ -664,6 +668,8 @@
reg = readl_relaxed(penv->wlan_brdg_err_source);
pr_info_ratelimited("%s: WLAN_BRDG_ERR_SOURCE %08x\n", __func__, reg);
+ reg = readl_relaxed(penv->wlan_tx_status);
+ pr_info_ratelimited("%s: WLAN_TX_STATUS %08x\n", __func__, reg);
}
EXPORT_SYMBOL(wcnss_pronto_log_debug_regs);
@@ -755,8 +761,6 @@
case SMD_EVENT_CLOSE:
pr_debug("wcnss: closing WCNSS SMD channel :%s",
WCNSS_CTRL_CHANNEL);
- /* This SMD is closed only during SSR */
- penv->ssr_boot = true;
penv->nv_downloaded = 0;
break;
@@ -1348,6 +1352,17 @@
goto exit;
}
+ if (penv->fw_cal_available) {
+ /* ignore cal upload from SSR */
+ smd_read(penv->smd_ch, NULL, calhdr.frag_size);
+ penv->fw_cal_exp_frag++;
+ if (calhdr.msg_flags & LAST_FRAGMENT) {
+ penv->fw_cal_exp_frag = 0;
+ goto exit;
+ }
+ return;
+ }
+
if (0 == calhdr.frag_number) {
if (calhdr.total_size > MAX_CALIBRATED_DATA_SIZE) {
pr_err("wcnss: Invalid cal data size %d",
@@ -1411,7 +1426,9 @@
int len = 0;
int rc = 0;
unsigned char buf[sizeof(struct wcnss_version)];
+ unsigned char build[WCNSS_MAX_BUILD_VER_LEN+1];
struct smd_msg_hdr *phdr;
+ struct smd_msg_hdr smd_msg;
struct wcnss_version *pversion;
int hw_type;
unsigned char fw_status = 0;
@@ -1468,6 +1485,12 @@
break;
case WCNSS_PRONTO_HW:
+ smd_msg.msg_type = WCNSS_BUILD_VER_REQ;
+ smd_msg.msg_len = sizeof(smd_msg);
+ rc = wcnss_smd_tx(&smd_msg, smd_msg.msg_len);
+ if (rc < 0)
+ pr_err("wcnss: smd tx failed: %s\n", __func__);
+
/* supported only if pronto major >= 1 and minor >= 4 */
if ((pversion->major >= 1) && (pversion->minor >= 4)) {
pr_info("wcnss: schedule dnld work for pronto\n");
@@ -1482,6 +1505,21 @@
}
break;
+ case WCNSS_BUILD_VER_RSP:
+ if (len > WCNSS_MAX_BUILD_VER_LEN) {
+ pr_err("wcnss: invalid build version data from wcnss %d\n",
+ len);
+ return;
+ }
+ rc = smd_read(penv->smd_ch, build, len);
+ if (rc < len) {
+ pr_err("wcnss: incomplete data read from smd\n");
+ return;
+ }
+ build[len] = 0;
+ pr_info("wcnss: build version %s\n", build);
+ break;
+
case WCNSS_NVBIN_DNLD_RSP:
penv->nv_downloaded = true;
fw_status = wcnss_fw_status();
@@ -1498,7 +1536,6 @@
break;
case WCNSS_CALDATA_UPLD_REQ:
- penv->fw_cal_available = 0;
extract_cal_data(len);
break;
@@ -1748,21 +1785,12 @@
while (!penv->user_cal_available && retry++ < 5)
msleep(500);
}
-
- /* only cal data is sent during ssr (if available) */
- if (penv->fw_cal_available && penv->ssr_boot) {
- pr_info_ratelimited("wcnss: cal download during SSR, using fw cal");
- wcnss_caldata_dnld(penv->fw_cal_data, penv->fw_cal_rcvd, false);
- return;
-
- } else if (penv->user_cal_available && penv->ssr_boot) {
- pr_info_ratelimited("wcnss: cal download during SSR, using user cal");
- wcnss_caldata_dnld(penv->user_cal_data,
- penv->user_cal_rcvd, false);
- return;
+ if (penv->fw_cal_available) {
+ pr_info_ratelimited("wcnss: cal download, using fw cal");
+ wcnss_caldata_dnld(penv->fw_cal_data, penv->fw_cal_rcvd, true);
} else if (penv->user_cal_available) {
- pr_info_ratelimited("wcnss: cal download during cold boot, using user cal");
+ pr_info_ratelimited("wcnss: cal download, using user cal");
wcnss_caldata_dnld(penv->user_cal_data,
penv->user_cal_rcvd, true);
}
@@ -1965,7 +1993,12 @@
pr_err("%s: ioremap wlan BRDG ERR failed\n", __func__);
goto fail_ioremap8;
}
-
+ penv->wlan_tx_status = ioremap(MSM_PRONTO_TXP_STATUS, SZ_8);
+ if (!penv->wlan_tx_status) {
+ ret = -ENOMEM;
+ pr_err("%s: ioremap wlan TX STATUS failed\n", __func__);
+ goto fail_ioremap9;
+ }
}
penv->adc_tm_dev = qpnp_get_adc_tm(&penv->pdev->dev, "wcnss");
if (IS_ERR(penv->adc_tm_dev)) {
@@ -1991,6 +2024,9 @@
fail_pil:
if (penv->riva_ccu_base)
iounmap(penv->riva_ccu_base);
+ if (penv->wlan_tx_status)
+ iounmap(penv->wlan_tx_status);
+fail_ioremap9:
if (penv->wlan_brdg_err_source)
iounmap(penv->wlan_brdg_err_source);
fail_ioremap8:
diff --git a/drivers/nfc/nfc-nci.c b/drivers/nfc/nfc-nci.c
index 043f9bc..99e17a6 100644
--- a/drivers/nfc/nfc-nci.c
+++ b/drivers/nfc/nfc-nci.c
@@ -757,7 +757,8 @@
r = of_property_read_string(np, "qcom,clk-src", &pdata->clk_src);
- if (!strcmp(pdata->clk_src, "GPCLK"))
+ if ((!strcmp(pdata->clk_src, "GPCLK")) ||
+ (!strcmp(pdata->clk_src, "GPCLK2")))
pdata->clk_src_gpio = of_get_named_gpio(np,
"qcom,clk-en-gpio", 0);
@@ -874,6 +875,14 @@
} else {
goto err_dis_gpio;
}
+ } else if (!strcmp(platform_data->clk_src, "GPCLK2")) {
+ if (gpio_is_valid(platform_data->clk_src_gpio)) {
+ nfc_clk = clk_get(&client->dev, "core_clk_pvt");
+ if (nfc_clk == NULL)
+ goto err_dis_gpio;
+ } else {
+ goto err_dis_gpio;
+ }
} else {
nfc_clk = NULL;
}
@@ -974,7 +983,8 @@
r = gpio_direction_input(platform_data->dis_gpio);
if (r)
dev_err(&client->dev, "nfc-nci probe: Unable to set direction\n");
- if (!strcmp(platform_data->clk_src, "GPCLK")) {
+ if ((!strcmp(platform_data->clk_src, "GPCLK")) ||
+ (!strcmp(platform_data->clk_src, "GPCLK2"))) {
r = gpio_direction_input(platform_data->clk_src_gpio);
if (r)
dev_err(&client->dev, "nfc-nci probe: Unable to set direction\n");
diff --git a/drivers/of/of_batterydata.c b/drivers/of/of_batterydata.c
index b0d40f1..32aae74 100644
--- a/drivers/of/of_batterydata.c
+++ b/drivers/of/of_batterydata.c
@@ -228,7 +228,7 @@
OF_PROP_READ(batt_data->rbatt_capacitive_mohm,
"rbatt-capacitive-mohm", node, rc, false);
OF_PROP_READ(batt_data->flat_ocv_threshold_uv,
- "flat-ocv-threshold", node, rc, true);
+ "flat-ocv-threshold-uv", node, rc, true);
OF_PROP_READ(batt_data->max_voltage_uv,
"max-voltage-uv", node, rc, true);
OF_PROP_READ(batt_data->cutoff_uv, "v-cutoff-uv", node, rc, true);
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 5f0ba94..9ccb993 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -327,10 +327,9 @@
for(; lookup->compatible != NULL; lookup++) {
if (!of_device_is_compatible(np, lookup->compatible))
continue;
- if (of_address_to_resource(np, 0, &res))
- continue;
- if (res.start != lookup->phys_addr)
- continue;
+ if (!of_address_to_resource(np, 0, &res))
+ if (res.start != lookup->phys_addr)
+ continue;
pr_debug("%s: devname=%s\n", np->full_name, lookup->name);
return lookup;
}
diff --git a/drivers/platform/msm/qpnp-power-on.c b/drivers/platform/msm/qpnp-power-on.c
index 50d5f7b..b55b66b 100644
--- a/drivers/platform/msm/qpnp-power-on.c
+++ b/drivers/platform/msm/qpnp-power-on.c
@@ -705,6 +705,8 @@
pon->pon_input->phys = "qpnp_pon/input0";
}
+ /* don't send dummy release event when system resumes */
+ __set_bit(INPUT_PROP_NO_DUMMY_RELEASE, pon->pon_input->propbit);
input_set_capability(pon->pon_input, EV_KEY, cfg->key_code);
return 0;
@@ -1116,8 +1118,8 @@
}
static struct of_device_id spmi_match_table[] = {
- { .compatible = "qcom,qpnp-power-on",
- }
+ { .compatible = "qcom,qpnp-power-on", },
+ {}
};
static struct spmi_driver qpnp_pon_driver = {
diff --git a/drivers/platform/msm/sps/sps.c b/drivers/platform/msm/sps/sps.c
index 4f10cf8..c621d2a 100644
--- a/drivers/platform/msm/sps/sps.c
+++ b/drivers/platform/msm/sps/sps.c
@@ -664,6 +664,11 @@
return SPS_ERROR;
}
+ if (sps == NULL || !sps->is_ready) {
+ SPS_DBG2("sps:%s:sps driver is not ready.\n", __func__);
+ return -EPROBE_DEFER;
+ }
+
mutex_lock(&sps->lock);
/* Search for the target BAM device */
bam = sps_h2bam(dev);
@@ -1100,6 +1105,11 @@
SPS_DBG("sps:%s.", __func__);
+ if (sps == NULL || !sps->is_ready) {
+ SPS_DBG2("sps:%s:sps driver is not ready.\n", __func__);
+ return -EPROBE_DEFER;
+ }
+
if (handle == NULL) {
SPS_ERR("sps:%s:handle is NULL.\n", __func__);
return SPS_ERROR;
@@ -1142,6 +1152,11 @@
return SPS_ERROR;
}
+ if (sps == NULL || !sps->is_ready) {
+ SPS_DBG2("sps:%s:sps driver is not ready.\n", __func__);
+ return -EPROBE_DEFER;
+ }
+
if (use_offset) {
if ((addr + size) <= sps->pipemem_size)
mem_buffer->phys_base = sps->pipemem_phys_base + addr;
@@ -1752,6 +1767,11 @@
return SPS_ERROR;
}
+ if (sps == NULL || !sps->is_ready) {
+ SPS_DBG2("sps:%s:sps driver is not ready.\n", __func__);
+ return -EPROBE_DEFER;
+ }
+
mutex_lock(&sps->lock);
/* Search for the target BAM device */
bam = sps_h2bam(dev);
@@ -1997,8 +2017,10 @@
SPS_DBG("sps:%s.", __func__);
- if (!sps->is_ready)
+ if (sps == NULL || !sps->is_ready) {
+ SPS_DBG2("sps:%s:sps driver is not ready.\n", __func__);
return -EPROBE_DEFER;
+ }
if (clk_on == true) {
SPS_DBG("sps:vote for bam dma clk.\n");
@@ -2039,8 +2061,10 @@
return SPS_ERROR;
}
- if (sps == NULL)
- return SPS_ERROR;
+ if (sps == NULL) {
+ SPS_DBG2("sps:%s:sps driver is not ready.\n", __func__);
+ return -EPROBE_DEFER;
+ }
/* BAM-DMA is registered internally during power-up */
if ((!sps->is_ready) && !(bam_props->options & SPS_BAM_OPT_BAMDMA)) {
@@ -2507,7 +2531,7 @@
sps->dfab_clk = clk_get(sps->dev, "dfab_clk");
if (IS_ERR(sps->dfab_clk)) {
- if (IS_ERR(sps->dfab_clk) == -EPROBE_DEFER)
+ if (PTR_ERR(sps->dfab_clk) == -EPROBE_DEFER)
ret = -EPROBE_DEFER;
else
SPS_ERR("sps:fail to get dfab_clk.");
@@ -2524,7 +2548,7 @@
if (!d_type) {
sps->pmem_clk = clk_get(sps->dev, "mem_clk");
if (IS_ERR(sps->pmem_clk)) {
- if (IS_ERR(sps->pmem_clk) == -EPROBE_DEFER)
+ if (PTR_ERR(sps->pmem_clk) == -EPROBE_DEFER)
ret = -EPROBE_DEFER;
else
SPS_ERR("sps:fail to get pmem_clk.");
@@ -2541,7 +2565,7 @@
#ifdef CONFIG_SPS_SUPPORT_BAMDMA
sps->bamdma_clk = clk_get(sps->dev, "dma_bam_pclk");
if (IS_ERR(sps->bamdma_clk)) {
- if (IS_ERR(sps->bamdma_clk) == -EPROBE_DEFER)
+ if (PTR_ERR(sps->bamdma_clk) == -EPROBE_DEFER)
ret = -EPROBE_DEFER;
else
SPS_ERR("sps:fail to get bamdma_clk.");
diff --git a/drivers/power/power_supply_sysfs.c b/drivers/power/power_supply_sysfs.c
index b918110..4688514 100644
--- a/drivers/power/power_supply_sysfs.c
+++ b/drivers/power/power_supply_sysfs.c
@@ -152,6 +152,7 @@
POWER_SUPPLY_ATTR(current_max),
POWER_SUPPLY_ATTR(input_current_max),
POWER_SUPPLY_ATTR(input_current_trim),
+ POWER_SUPPLY_ATTR(input_current_settled),
POWER_SUPPLY_ATTR(current_now),
POWER_SUPPLY_ATTR(current_avg),
POWER_SUPPLY_ATTR(power_now),
diff --git a/drivers/power/qpnp-bms.c b/drivers/power/qpnp-bms.c
index aa4e016..85a70ea 100644
--- a/drivers/power/qpnp-bms.c
+++ b/drivers/power/qpnp-bms.c
@@ -765,10 +765,22 @@
return get_battery_status(chip) == POWER_SUPPLY_STATUS_FULL;
}
+#define BAT_PRES_BIT BIT(7)
static bool is_battery_present(struct qpnp_bms_chip *chip)
{
union power_supply_propval ret = {0,};
+ int rc;
+ u8 batt_pres;
+ /* first try to use the batt_pres register if given */
+ if (chip->batt_pres_addr) {
+ rc = qpnp_read_wrapper(chip, &batt_pres,
+ chip->batt_pres_addr, 1);
+ if (!rc && (batt_pres & BAT_PRES_BIT))
+ return true;
+ else
+ return false;
+ }
if (chip->batt_psy == NULL)
chip->batt_psy = power_supply_get_by_name("battery");
if (chip->batt_psy) {
@@ -922,14 +934,67 @@
}
}
+#define SIGN(x) ((x) < 0 ? -1 : 1)
+#define UV_PER_SPIN 50000
+static int find_ocv_for_pc(struct qpnp_bms_chip *chip, int batt_temp, int pc)
+{
+ int new_pc;
+ int batt_temp_degc = batt_temp / 10;
+ int ocv_mv;
+ int delta_mv = 5;
+ int max_spin_count;
+ int count = 0;
+ int sign, new_sign;
+
+ ocv_mv = interpolate_ocv(chip->pc_temp_ocv_lut, batt_temp_degc, pc);
+
+ new_pc = interpolate_pc(chip->pc_temp_ocv_lut, batt_temp_degc, ocv_mv);
+ pr_debug("test revlookup pc = %d for ocv = %d\n", new_pc, ocv_mv);
+ max_spin_count = 1 + (chip->max_voltage_uv - chip->v_cutoff_uv)
+ / UV_PER_SPIN;
+ sign = SIGN(pc - new_pc);
+
+ while (abs(new_pc - pc) != 0 && count < max_spin_count) {
+ /*
+ * If the newly interpolated pc is larger than the lookup pc,
+ * the ocv should be reduced and vice versa
+ */
+ new_sign = SIGN(pc - new_pc);
+ /*
+ * If the sign has changed, then we have passed the lookup pc.
+ * reduce the ocv step size to get finer results.
+ *
+ * If we have already reduced the ocv step size and still
+ * passed the lookup pc, just stop and use the current ocv.
+ * This can only happen if the batterydata profile is
+ * non-monotonic anyways.
+ */
+ if (new_sign != sign) {
+ if (delta_mv > 1)
+ delta_mv = 1;
+ else
+ break;
+ }
+ sign = new_sign;
+
+ ocv_mv = ocv_mv + delta_mv * sign;
+ new_pc = interpolate_pc(chip->pc_temp_ocv_lut,
+ batt_temp_degc, ocv_mv);
+ pr_debug("test revlookup pc = %d for ocv = %d\n",
+ new_pc, ocv_mv);
+ count++;
+ }
+
+ return ocv_mv * 1000;
+}
+
#define OCV_RAW_UNINITIALIZED 0xFFFF
#define MIN_OCV_UV 2000000
static int read_soc_params_raw(struct qpnp_bms_chip *chip,
struct raw_soc_params *raw,
int batt_temp)
{
- int warm_reset;
- int rc;
+ int warm_reset, rc;
mutex_lock(&chip->bms_output_lock);
@@ -977,8 +1042,8 @@
chip->done_charging = false;
/* if we just finished charging, reset CC and fake 100% */
chip->ocv_reading_at_100 = raw->last_good_ocv_raw;
- chip->last_ocv_uv = chip->max_voltage_uv;
- raw->last_good_ocv_uv = chip->max_voltage_uv;
+ chip->last_ocv_uv = find_ocv_for_pc(chip, batt_temp, 100);
+ raw->last_good_ocv_uv = chip->last_ocv_uv;
raw->cc = 0;
raw->shdw_cc = 0;
reset_cc(chip, CLEAR_CC | CLEAR_SHDW_CC);
@@ -1355,60 +1420,6 @@
return pc;
}
-#define SIGN(x) ((x) < 0 ? -1 : 1)
-#define UV_PER_SPIN 50000
-static int find_ocv_for_pc(struct qpnp_bms_chip *chip, int batt_temp, int pc)
-{
- int new_pc;
- int batt_temp_degc = batt_temp / 10;
- int ocv_mv;
- int delta_mv = 5;
- int max_spin_count;
- int count = 0;
- int sign, new_sign;
-
- ocv_mv = interpolate_ocv(chip->pc_temp_ocv_lut, batt_temp_degc, pc);
-
- new_pc = interpolate_pc(chip->pc_temp_ocv_lut, batt_temp_degc, ocv_mv);
- pr_debug("test revlookup pc = %d for ocv = %d\n", new_pc, ocv_mv);
- max_spin_count = 1 + (chip->max_voltage_uv - chip->v_cutoff_uv)
- / UV_PER_SPIN;
- sign = SIGN(pc - new_pc);
-
- while (abs(new_pc - pc) != 0 && count < max_spin_count) {
- /*
- * If the newly interpolated pc is larger than the lookup pc,
- * the ocv should be reduced and vice versa
- */
- new_sign = SIGN(pc - new_pc);
- /*
- * If the sign has changed, then we have passed the lookup pc.
- * reduce the ocv step size to get finer results.
- *
- * If we have already reduced the ocv step size and still
- * passed the lookup pc, just stop and use the current ocv.
- * This can only happen if the batterydata profile is
- * non-monotonic anyways.
- */
- if (new_sign != sign) {
- if (delta_mv > 1)
- delta_mv = 1;
- else
- break;
- }
- sign = new_sign;
-
- ocv_mv = ocv_mv + delta_mv * sign;
- new_pc = interpolate_pc(chip->pc_temp_ocv_lut,
- batt_temp_degc, ocv_mv);
- pr_debug("test revlookup pc = %d for ocv = %d\n",
- new_pc, ocv_mv);
- count++;
- }
-
- return ocv_mv * 1000;
-}
-
static int get_current_time(unsigned long *now_tm_sec)
{
struct rtc_time tm;
@@ -1677,10 +1688,13 @@
rc = qpnp_write_wrapper(chip, &temp, chip->base + IAVG_STORAGE_REG, 1);
- /* don't store soc if temperature is below 5degC */
+ /* store an invalid soc if temperature is below 5degC */
if (batt_temp > IGNORE_SOC_TEMP_DECIDEG)
qpnp_masked_write_base(chip, chip->soc_storage_addr,
SOC_STORAGE_MASK, (soc + 1) << 1);
+ else
+ qpnp_masked_write_base(chip, chip->soc_storage_addr,
+ SOC_STORAGE_MASK, SOC_STORAGE_MASK);
}
static int scale_soc_while_chg(struct qpnp_bms_chip *chip, int chg_time_sec,
@@ -1817,8 +1831,15 @@
chip->catch_up_time_sec,
soc, chip->last_soc);
- soc_change = min((int)abs(chip->last_soc - soc),
- time_since_last_change_sec / SOC_CHANGE_PER_SEC);
+ /* if the battery is close to cutoff allow more change */
+ if (wake_lock_active(&chip->low_voltage_wake_lock))
+ soc_change = min((int)abs(chip->last_soc - soc),
+ time_since_last_change_sec);
+ else
+ soc_change = min((int)abs(chip->last_soc - soc),
+ time_since_last_change_sec
+ / SOC_CHANGE_PER_SEC);
+
if (chip->last_soc_unbound) {
chip->last_soc_unbound = false;
} else {
@@ -1994,7 +2015,7 @@
}
}
-#define NO_ADJUST_HIGH_SOC_THRESHOLD 90
+#define NO_ADJUST_HIGH_SOC_THRESHOLD 98
static int adjust_soc(struct qpnp_bms_chip *chip, struct soc_params *params,
int soc, int batt_temp)
{
@@ -2050,9 +2071,10 @@
* because we might pull it low
* and cause a bad user experience
*/
- if (soc_est == soc
- || soc_est > chip->adjust_soc_low_threshold
- || soc >= NO_ADJUST_HIGH_SOC_THRESHOLD)
+ if (!wake_lock_active(&chip->low_voltage_wake_lock) &&
+ (soc_est == soc
+ || soc_est > chip->adjust_soc_low_threshold
+ || soc >= NO_ADJUST_HIGH_SOC_THRESHOLD))
goto out;
if (chip->last_soc_est == -EINVAL)
@@ -2097,8 +2119,11 @@
pr_debug("new delta ocv = %d\n", delta_ocv_uv);
}
- if (wake_lock_active(&chip->low_voltage_wake_lock))
+ if (wake_lock_active(&chip->low_voltage_wake_lock)) {
+ /* when in the cutoff region, do not correct upwards */
+ delta_ocv_uv = max(0, delta_ocv_uv);
goto skip_limits;
+ }
if (chip->last_ocv_uv > chip->flat_ocv_threshold_uv)
correction_limit_uv = chip->high_ocv_correction_limit_uv;
@@ -2246,6 +2271,8 @@
qpnp_write_wrapper(chip, (u8 *)&ocv_raw,
chip->base + BMS1_OCV_THR0, 2);
+ enable_bms_irq(&chip->ocv_thr_irq);
+ enable_bms_irq(&chip->sw_cc_thr_irq);
pr_debug("current sw_cc_raw = 0x%llx, current ocv = 0x%hx\n",
current_shdw_cc_raw, (uint16_t)current_ocv_raw);
pr_debug("target_cc_uah = %lld, raw64 = 0x%llx, raw 36 = 0x%llx, ocv_raw = 0x%hx\n",
@@ -2254,6 +2281,7 @@
(uint16_t)ocv_raw);
}
+#define BAD_SOC_THRESH -10
static int calculate_raw_soc(struct qpnp_bms_chip *chip,
struct raw_soc_params *raw,
struct soc_params *params,
@@ -2270,7 +2298,7 @@
soc = DIV_ROUND_CLOSEST((remaining_usable_charge_uah * 100),
(params->fcc_uah - params->uuc_uah));
- if (chip->first_time_calc_soc && soc < 0) {
+ if (chip->first_time_calc_soc && soc > BAD_SOC_THRESH && soc < 0) {
/*
* first time calcualtion and the pon ocv is too low resulting
* in a bad soc. Adjust ocv to get 0 soc
@@ -2295,7 +2323,7 @@
if (soc > 100)
soc = 100;
- if (soc < 0) {
+ if (soc > BAD_SOC_THRESH && soc < 0) {
pr_debug("bad rem_usb_chg = %d rem_chg %d, cc_uah %d, unusb_chg %d\n",
remaining_usable_charge_uah,
params->ocv_charge_uah,
@@ -2376,9 +2404,13 @@
* If the battery is full, configure the cc threshold so the system
* wakes up after SoC changes
*/
- if (is_battery_full(chip))
+ if (is_battery_full(chip)) {
configure_soc_wakeup(chip, ¶ms,
batt_temp, bound_soc(new_calculated_soc - 1));
+ } else {
+ disable_bms_irq(&chip->ocv_thr_irq);
+ disable_bms_irq(&chip->sw_cc_thr_irq);
+ }
done_calculating:
mutex_lock(&chip->last_soc_mutex);
previous_soc = chip->calculated_soc;
@@ -3220,8 +3252,6 @@
if (status == POWER_SUPPLY_STATUS_FULL) {
pr_debug("battery full\n");
- enable_bms_irq(&chip->ocv_thr_irq);
- enable_bms_irq(&chip->sw_cc_thr_irq);
recalculate_soc(chip);
} else if (chip->battery_status
== POWER_SUPPLY_STATUS_FULL) {
@@ -3488,7 +3518,7 @@
|| shutdown_soc_out_of_limit) {
chip->battery_removed = true;
chip->shutdown_soc_invalid = true;
- chip->shutdown_iavg_ma = 0;
+ chip->shutdown_iavg_ma = MIN_IAVG_MA;
pr_debug("Ignoring shutdown SoC: invalid = %d, offmode = %d, out_of_limit = %d\n",
invalid_stored_soc, offmode_battery_replaced,
shutdown_soc_out_of_limit);
@@ -3520,6 +3550,7 @@
struct qpnp_bms_chip *chip = _chip;
pr_debug("sw_cc_thr irq triggered\n");
+ disable_bms_irq(&chip->sw_cc_thr_irq);
bms_stay_awake(&chip->soc_wake_source);
schedule_work(&chip->recalc_work);
return IRQ_HANDLED;
diff --git a/drivers/power/qpnp-charger.c b/drivers/power/qpnp-charger.c
index a627ec2..6ea4ea6 100644
--- a/drivers/power/qpnp-charger.c
+++ b/drivers/power/qpnp-charger.c
@@ -70,8 +70,9 @@
#define CHGR_IBAT_TERM_CHGR 0x5B
#define CHGR_IBAT_TERM_BMS 0x5C
#define CHGR_VBAT_DET 0x5D
+#define CHGR_TTRKL_MAX_EN 0x5E
#define CHGR_TTRKL_MAX 0x5F
-#define CHGR_TTRKL_MAX_EN 0x60
+#define CHGR_TCHG_MAX_EN 0x60
#define CHGR_TCHG_MAX 0x61
#define CHGR_CHG_WDOG_TIME 0x62
#define CHGR_CHG_WDOG_DLY 0x63
@@ -101,6 +102,7 @@
#define BUCK_VCHG_OV 0x77
#define BUCK_TEST_SMBC_MODES 0xE6
#define BUCK_CTRL_TRIM1 0xF1
+#define BUCK_CTRL_TRIM3 0xF3
#define SEC_ACCESS 0xD0
#define BAT_IF_VREF_BAT_THM_CTRL 0x4A
#define BAT_IF_BPD_CTRL 0x48
@@ -310,6 +312,9 @@
bool btc_disabled;
bool use_default_batt_values;
bool duty_cycle_100p;
+ bool ibat_calibration_enabled;
+ bool aicl_settled;
+ bool use_external_rsense;
unsigned int bpd_detection;
unsigned int max_bat_chg_current;
unsigned int warm_bat_chg_ma;
@@ -335,6 +340,7 @@
unsigned int cold_batt_p;
int warm_bat_decidegc;
int cool_bat_decidegc;
+ int fake_battery_soc;
unsigned int safe_current;
unsigned int revision;
unsigned int type;
@@ -362,6 +368,7 @@
bool batfet_ext_en;
struct work_struct batfet_lcl_work;
struct qpnp_vadc_chip *vadc_dev;
+ struct qpnp_iadc_chip *iadc_dev;
struct qpnp_adc_tm_chip *adc_tm_dev;
struct mutex jeita_configure_lock;
spinlock_t usbin_health_monitor_lock;
@@ -421,6 +428,16 @@
return -EINVAL;
}
+static bool
+is_within_range(int value, int left, int right)
+{
+ if (left >= right && left >= value && value >= right)
+ return 1;
+ if (left <= right && left <= value && value <= right)
+ return 1;
+ return 0;
+}
+
static int
qpnp_chg_read(struct qpnp_chg_chip *chip, u8 *val,
u16 base, int count)
@@ -623,6 +640,22 @@
return (usbin_valid_rt_sts & USB_VALID_BIT) ? 1 : 0;
}
+static bool
+qpnp_chg_is_ibat_loop_active(struct qpnp_chg_chip *chip)
+{
+ int rc;
+ u8 buck_sts;
+
+ rc = qpnp_chg_read(chip, &buck_sts,
+ INT_RT_STS(chip->buck_base), 1);
+ if (rc) {
+ pr_err("failed to read buck RT status rc=%d\n", rc);
+ return 0;
+ }
+
+ return !!(buck_sts & IBAT_LOOP_IRQ);
+}
+
#define USB_VALID_MASK 0xC0
#define USB_COARSE_DET 0x10
#define USB_VALID_UVP_VALUE 0x00
@@ -1156,9 +1189,16 @@
qpnp_chg_usb_chg_gone_irq_handler(int irq, void *_chip)
{
struct qpnp_chg_chip *chip = _chip;
+ u8 usb_sts;
+ int rc;
+
+ rc = qpnp_chg_read(chip, &usb_sts,
+ INT_RT_STS(chip->usb_chgpth_base), 1);
+ if (rc)
+ pr_err("failed to read usb_chgpth_sts rc=%d\n", rc);
pr_debug("chg_gone triggered\n");
- if (qpnp_chg_is_usb_chg_plugged_in(chip)) {
+ if (qpnp_chg_is_usb_chg_plugged_in(chip) && (usb_sts & CHG_GONE_IRQ)) {
qpnp_chg_charge_en(chip, 0);
qpnp_chg_force_run_on_batt(chip, 1);
schedule_delayed_work(&chip->arb_stop_work,
@@ -1245,6 +1285,21 @@
return 0;
}
+static int
+qpnp_chg_vddmax_get(struct qpnp_chg_chip *chip)
+{
+ int rc;
+ u8 vddmax = 0;
+
+ rc = qpnp_chg_read(chip, &vddmax, chip->chgr_base + CHGR_VDD_MAX, 1);
+ if (rc) {
+ pr_err("Failed to write vddmax: %d\n", rc);
+ return rc;
+ }
+
+ return QPNP_CHG_V_MIN_MV + (int)vddmax * QPNP_CHG_V_STEP_MV;
+}
+
/* JEITA compliance logic */
static void
qpnp_chg_set_appropriate_vddmax(struct qpnp_chg_chip *chip)
@@ -1404,10 +1459,10 @@
(chip->usb_valid_check_ovp)) {
usbin_health =
qpnp_chg_check_usbin_health(chip);
- if (chip->usbin_health != usbin_health) {
+ if ((chip->usbin_health != usbin_health)
+ && (usbin_health == USBIN_OVP)) {
chip->usbin_health = usbin_health;
- if (usbin_health == USBIN_OVP)
- psy_health_sts =
+ psy_health_sts =
POWER_SUPPLY_HEALTH_OVERVOLTAGE;
power_supply_set_health_state(
chip->usb_psy,
@@ -1420,8 +1475,9 @@
qpnp_chg_set_appropriate_vddmax(chip);
chip->chg_done = false;
}
- qpnp_chg_usb_suspend_enable(chip, 1);
+ qpnp_chg_usb_suspend_enable(chip, 0);
chip->prev_usb_max_ma = -EINVAL;
+ chip->aicl_settled = false;
} else {
/* when OVP clamped usbin, and then decrease
* the charger voltage to lower than the OVP
@@ -1432,10 +1488,10 @@
(chip->usb_valid_check_ovp)) {
usbin_health =
qpnp_chg_check_usbin_health(chip);
- if (chip->usbin_health != usbin_health) {
+ if ((chip->usbin_health != usbin_health)
+ && (usbin_health == USBIN_OK)) {
chip->usbin_health = usbin_health;
- if (usbin_health == USBIN_OK)
- psy_health_sts =
+ psy_health_sts =
POWER_SUPPLY_HEALTH_GOOD;
power_supply_set_health_state(
chip->usb_psy,
@@ -1656,9 +1712,11 @@
case POWER_SUPPLY_PROP_SYSTEM_TEMP_LEVEL:
case POWER_SUPPLY_PROP_INPUT_CURRENT_MAX:
case POWER_SUPPLY_PROP_INPUT_CURRENT_TRIM:
+ case POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED:
case POWER_SUPPLY_PROP_VOLTAGE_MIN:
case POWER_SUPPLY_PROP_COOL_TEMP:
case POWER_SUPPLY_PROP_WARM_TEMP:
+ case POWER_SUPPLY_PROP_CAPACITY:
return 1;
default:
break;
@@ -1769,6 +1827,7 @@
POWER_SUPPLY_PROP_CURRENT_NOW,
POWER_SUPPLY_PROP_INPUT_CURRENT_MAX,
POWER_SUPPLY_PROP_INPUT_CURRENT_TRIM,
+ POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED,
POWER_SUPPLY_PROP_VOLTAGE_MIN,
POWER_SUPPLY_PROP_INPUT_VOLTAGE_REGULATION,
POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
@@ -2013,6 +2072,9 @@
union power_supply_propval ret = {0,};
int battery_status, bms_status, soc, charger_in;
+ if (chip->fake_battery_soc >= 0)
+ return chip->fake_battery_soc;
+
if (chip->use_default_batt_values || !get_prop_batt_present(chip))
return DEFAULT_CAPACITY;
@@ -2030,6 +2092,8 @@
if (battery_status != POWER_SUPPLY_STATUS_CHARGING
&& bms_status != POWER_SUPPLY_STATUS_CHARGING
&& charger_in
+ && !chip->bat_is_cool
+ && !chip->bat_is_warm
&& !chip->resuming_charging
&& !chip->charging_disabled
&& chip->soc_resume_limit
@@ -2133,7 +2197,8 @@
if (ret.intval <= 2 && !chip->use_default_batt_values &&
get_prop_batt_present(chip)) {
- qpnp_chg_usb_suspend_enable(chip, 1);
+ if (ret.intval == 2)
+ qpnp_chg_usb_suspend_enable(chip, 1);
qpnp_chg_iusbmax_set(chip, QPNP_CHG_I_MAX_MIN_100);
} else {
qpnp_chg_usb_suspend_enable(chip, 0);
@@ -2243,6 +2308,9 @@
case POWER_SUPPLY_PROP_INPUT_CURRENT_TRIM:
val->intval = qpnp_chg_iusb_trim_get(chip);
break;
+ case POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED:
+ val->intval = chip->aicl_settled;
+ break;
case POWER_SUPPLY_PROP_VOLTAGE_MIN:
val->intval = qpnp_chg_vinmin_get(chip) * 1000;
break;
@@ -2349,22 +2417,63 @@
QPNP_CHG_I_MASK, temp, 1);
}
+static int
+qpnp_chg_ibatmax_get(struct qpnp_chg_chip *chip, int *chg_current)
+{
+ int rc;
+ u8 temp;
+
+ *chg_current = 0;
+ rc = qpnp_chg_read(chip, &temp, chip->chgr_base + CHGR_IBAT_MAX, 1);
+ if (rc) {
+ pr_err("failed read ibat_max rc=%d\n", rc);
+ return rc;
+ }
+
+ *chg_current = ((temp & QPNP_CHG_I_MASK) * QPNP_CHG_I_STEP_MA);
+
+ return 0;
+}
+
#define QPNP_CHG_TCHG_MASK 0x7F
+#define QPNP_CHG_TCHG_EN_MASK 0x80
#define QPNP_CHG_TCHG_MIN 4
#define QPNP_CHG_TCHG_MAX 512
#define QPNP_CHG_TCHG_STEP 4
static int qpnp_chg_tchg_max_set(struct qpnp_chg_chip *chip, int minutes)
{
u8 temp;
+ int rc;
if (minutes < QPNP_CHG_TCHG_MIN || minutes > QPNP_CHG_TCHG_MAX) {
pr_err("bad max minutes =%d asked to set\n", minutes);
return -EINVAL;
}
- temp = (minutes - 1)/QPNP_CHG_TCHG_STEP;
- return qpnp_chg_masked_write(chip, chip->chgr_base + CHGR_TCHG_MAX,
+ rc = qpnp_chg_masked_write(chip, chip->chgr_base + CHGR_TCHG_MAX_EN,
+ QPNP_CHG_TCHG_EN_MASK, 0, 1);
+ if (rc) {
+ pr_err("failed write tchg_max_en rc=%d\n", rc);
+ return rc;
+ }
+
+ temp = minutes / QPNP_CHG_TCHG_STEP - 1;
+
+ rc = qpnp_chg_masked_write(chip, chip->chgr_base + CHGR_TCHG_MAX,
QPNP_CHG_TCHG_MASK, temp, 1);
+ if (rc) {
+ pr_err("failed write tchg_max_en rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_chg_masked_write(chip, chip->chgr_base + CHGR_TCHG_MAX_EN,
+ QPNP_CHG_TCHG_EN_MASK, QPNP_CHG_TCHG_EN_MASK, 1);
+ if (rc) {
+ pr_err("failed write tchg_max_en rc=%d\n", rc);
+ return rc;
+ }
+
+ return 0;
}
static int
@@ -2383,6 +2492,155 @@
chip->chgr_base + CHGR_VDD_SAFE, 1);
}
+#define IBAT_TRIM_TGT_MA 500
+#define IBAT_TRIM_OFFSET_MASK 0x7F
+#define IBAT_TRIM_GOOD_BIT BIT(7)
+#define IBAT_TRIM_LOW_LIM 20
+#define IBAT_TRIM_HIGH_LIM 114
+#define IBAT_TRIM_MEAN 64
+
+static void
+qpnp_chg_trim_ibat(struct qpnp_chg_chip *chip, u8 ibat_trim)
+{
+ int ibat_now_ma, ibat_diff_ma, rc;
+ struct qpnp_iadc_result i_result;
+ enum qpnp_iadc_channels iadc_channel;
+
+ iadc_channel = chip->use_external_rsense ?
+ EXTERNAL_RSENSE : INTERNAL_RSENSE;
+ rc = qpnp_iadc_read(chip->iadc_dev, iadc_channel, &i_result);
+ if (rc) {
+ pr_err("Unable to read bat rc=%d\n", rc);
+ return;
+ }
+
+ ibat_now_ma = i_result.result_ua / 1000;
+
+ if (qpnp_chg_is_ibat_loop_active(chip)) {
+ ibat_diff_ma = ibat_now_ma - IBAT_TRIM_TGT_MA;
+
+ if (abs(ibat_diff_ma) > 50) {
+ ibat_trim += (ibat_diff_ma / 20);
+ ibat_trim &= IBAT_TRIM_OFFSET_MASK;
+ /* reject new ibat_trim if it is outside limits */
+ if (!is_within_range(ibat_trim, IBAT_TRIM_LOW_LIM,
+ IBAT_TRIM_HIGH_LIM))
+ return;
+ }
+ ibat_trim |= IBAT_TRIM_GOOD_BIT;
+ rc = qpnp_chg_write(chip, &ibat_trim,
+ chip->buck_base + BUCK_CTRL_TRIM3, 1);
+ if (rc)
+ pr_err("failed to set IBAT_TRIM rc=%d\n", rc);
+
+ pr_debug("ibat_now=%dmA, itgt=%dmA, ibat_diff=%dmA, ibat_trim=%x\n",
+ ibat_now_ma, IBAT_TRIM_TGT_MA,
+ ibat_diff_ma, ibat_trim);
+ } else {
+ pr_debug("ibat loop not active - cannot calibrate ibat\n");
+ }
+}
+
+static int
+qpnp_chg_input_current_settled(struct qpnp_chg_chip *chip)
+{
+ int rc, ibat_max_ma;
+ u8 reg, chgr_sts, ibat_trim, i;
+
+ chip->aicl_settled = true;
+
+ /*
+ * Perform the ibat calibration.
+ * This is for devices which have a IBAT_TRIM error
+ * which can show IBAT_MAX out of spec.
+ */
+ if (!chip->ibat_calibration_enabled)
+ return 0;
+
+ if (chip->type != SMBB)
+ return 0;
+
+ rc = qpnp_chg_read(chip, ®,
+ chip->buck_base + BUCK_CTRL_TRIM3, 1);
+ if (rc) {
+ pr_err("failed to read BUCK_CTRL_TRIM3 rc=%d\n", rc);
+ return rc;
+ }
+ if (reg & IBAT_TRIM_GOOD_BIT) {
+ pr_debug("IBAT_TRIM_GOOD bit already set. Quitting!\n");
+ return 0;
+ }
+ ibat_trim = reg & IBAT_TRIM_OFFSET_MASK;
+
+ if (!is_within_range(ibat_trim, IBAT_TRIM_LOW_LIM,
+ IBAT_TRIM_HIGH_LIM)) {
+ pr_debug("Improper ibat_trim value=%x setting to value=%x\n",
+ ibat_trim, IBAT_TRIM_MEAN);
+ ibat_trim = IBAT_TRIM_MEAN;
+ rc = qpnp_chg_masked_write(chip,
+ chip->buck_base + BUCK_CTRL_TRIM3,
+ IBAT_TRIM_OFFSET_MASK, ibat_trim, 1);
+ if (rc) {
+ pr_err("failed to set ibat_trim to %x rc=%d\n",
+ IBAT_TRIM_MEAN, rc);
+ return rc;
+ }
+ }
+
+ rc = qpnp_chg_read(chip, &chgr_sts,
+ INT_RT_STS(chip->chgr_base), 1);
+ if (rc) {
+ pr_err("failed to read interrupt sts rc=%d\n", rc);
+ return rc;
+ }
+ if (!(chgr_sts & FAST_CHG_ON_IRQ)) {
+ pr_debug("Not in fastchg\n");
+ return rc;
+ }
+
+ /* save the ibat_max to restore it later */
+ rc = qpnp_chg_ibatmax_get(chip, &ibat_max_ma);
+ if (rc) {
+ pr_debug("failed to save ibatmax rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = qpnp_chg_ibatmax_set(chip, IBAT_TRIM_TGT_MA);
+ if (rc) {
+ pr_err("failed to set ibatmax rc=%d\n", rc);
+ return rc;
+ }
+
+ for (i = 0; i < 3; i++) {
+ /*
+ * ibat settling delay - to make sure the BMS controller
+ * has sufficient time to sample ibat for the configured
+ * ibat_max
+ */
+ msleep(20);
+ if (qpnp_chg_is_ibat_loop_active(chip))
+ qpnp_chg_trim_ibat(chip, ibat_trim);
+ else
+ pr_debug("ibat loop not active\n");
+
+ /* read the adjusted ibat_trim for further adjustments */
+ rc = qpnp_chg_read(chip, &ibat_trim,
+ chip->buck_base + BUCK_CTRL_TRIM3, 1);
+ if (rc) {
+ pr_err("failed to read BUCK_CTRL_TRIM3 rc=%d\n", rc);
+ break;
+ }
+ }
+
+ /* restore IBATMAX */
+ rc = qpnp_chg_ibatmax_set(chip, ibat_max_ma);
+ if (rc)
+ pr_err("failed to restore ibatmax rc=%d\n", rc);
+
+ return rc;
+}
+
+
#define BOOST_MIN_UV 4200000
#define BOOST_MAX_UV 5500000
#define BOOST_STEP_UV 50000
@@ -2877,10 +3135,17 @@
count = 0;
} else {
if (count == CONSECUTIVE_COUNT) {
- pr_info("End of Charging\n");
+ if (!chip->bat_is_cool && !chip->bat_is_warm) {
+ pr_info("End of Charging\n");
+ chip->chg_done = true;
+ } else {
+ pr_info("stop charging: battery is %s, vddmax = %d reached\n",
+ chip->bat_is_cool
+ ? "cool" : "warm",
+ qpnp_chg_vddmax_get(chip));
+ }
chip->delta_vddmax_mv = 0;
qpnp_chg_set_appropriate_vddmax(chip);
- chip->chg_done = true;
qpnp_chg_charge_en(chip, 0);
/* sleep for a second before enabling */
msleep(2000);
@@ -3354,6 +3619,10 @@
case POWER_SUPPLY_PROP_WARM_TEMP:
rc = qpnp_chg_configure_jeita(chip, psp, val->intval);
break;
+ case POWER_SUPPLY_PROP_CAPACITY:
+ chip->fake_battery_soc = val->intval;
+ power_supply_changed(&chip->batt_psy);
+ break;
case POWER_SUPPLY_PROP_CHARGING_ENABLED:
chip->charging_disabled = !(val->intval);
if (chip->charging_disabled) {
@@ -3377,6 +3646,9 @@
case POWER_SUPPLY_PROP_INPUT_CURRENT_TRIM:
qpnp_chg_iusb_trim_set(chip, val->intval);
break;
+ case POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED:
+ qpnp_chg_input_current_settled(chip);
+ break;
case POWER_SUPPLY_PROP_VOLTAGE_MIN:
qpnp_chg_vinmin_set(chip, val->intval / 1000);
break;
@@ -4098,6 +4370,11 @@
return rc;
}
+ /* Get the use-external-rsense property */
+ chip->use_external_rsense = of_property_read_bool(
+ chip->spmi->dev.of_node,
+ "qcom,use-external-rsense");
+
/* Get the btc-disabled property */
chip->btc_disabled = of_property_read_bool(chip->spmi->dev.of_node,
"qcom,btc-disabled");
@@ -4130,17 +4407,21 @@
of_property_read_bool(chip->spmi->dev.of_node,
"qcom,power-stage-reduced");
+ chip->ibat_calibration_enabled =
+ of_property_read_bool(chip->spmi->dev.of_node,
+ "qcom,ibat-calibration-enabled");
+
of_get_property(chip->spmi->dev.of_node, "qcom,thermal-mitigation",
&(chip->thermal_levels));
if (chip->thermal_levels > sizeof(int)) {
- chip->thermal_mitigation = kzalloc(
+ chip->thermal_mitigation = devm_kzalloc(chip->dev,
chip->thermal_levels,
GFP_KERNEL);
if (chip->thermal_mitigation == NULL) {
pr_err("thermal mitigation kzalloc() failed.\n");
- return rc;
+ return -ENOMEM;
}
chip->thermal_levels /= sizeof(int);
@@ -4165,13 +4446,15 @@
struct spmi_resource *spmi_resource;
int rc = 0;
- chip = kzalloc(sizeof *chip, GFP_KERNEL);
+ chip = devm_kzalloc(&spmi->dev,
+ sizeof(struct qpnp_chg_chip), GFP_KERNEL);
if (chip == NULL) {
pr_err("kzalloc() failed.\n");
return -ENOMEM;
}
chip->prev_usb_max_ma = -EINVAL;
+ chip->fake_battery_soc = -EINVAL;
chip->dev = &(spmi->dev);
chip->spmi = spmi;
@@ -4197,7 +4480,7 @@
/* Get all device tree properties */
rc = qpnp_charger_read_dt_props(chip);
if (rc)
- goto fail_chg_enable;
+ return rc;
/*
* Check if bat_if is set in DT and make sure VADC is present
@@ -4237,6 +4520,17 @@
goto fail_chg_enable;
}
+ if (subtype == SMBB_BAT_IF_SUBTYPE) {
+ chip->iadc_dev = qpnp_get_iadc(chip->dev,
+ "chg");
+ if (IS_ERR(chip->iadc_dev)) {
+ rc = PTR_ERR(chip->iadc_dev);
+ if (rc != -EPROBE_DEFER)
+ pr_err("iadc property missing\n");
+ goto fail_chg_enable;
+ }
+ }
+
rc = qpnp_chg_load_battery_data(chip);
if (rc)
goto fail_chg_enable;
@@ -4479,6 +4773,7 @@
goto unregister_dc_psy;
}
+ qpnp_chg_usb_chg_gone_irq_handler(chip->chg_gone.irq, chip);
qpnp_chg_usb_usbin_valid_irq_handler(chip->usbin_valid.irq, chip);
qpnp_chg_dc_dcin_valid_irq_handler(chip->dcin_valid.irq, chip);
power_supply_set_present(chip->usb_psy,
@@ -4509,9 +4804,6 @@
fail_chg_enable:
regulator_unregister(chip->otg_vreg.rdev);
regulator_unregister(chip->boost_vreg.rdev);
- kfree(chip->thermal_mitigation);
- kfree(chip);
- dev_set_drvdata(&spmi->dev, NULL);
return rc;
}
@@ -4524,15 +4816,27 @@
qpnp_adc_tm_disable_chan_meas(chip->adc_tm_dev,
&chip->adc_param);
}
- cancel_work_sync(&chip->adc_measure_work);
+
+ cancel_delayed_work_sync(&chip->aicl_check_work);
+ power_supply_unregister(&chip->dc_psy);
+ cancel_work_sync(&chip->soc_check_work);
+ cancel_delayed_work_sync(&chip->usbin_health_check);
+ cancel_delayed_work_sync(&chip->arb_stop_work);
cancel_delayed_work_sync(&chip->eoc_work);
+ cancel_work_sync(&chip->adc_disable_work);
+ cancel_work_sync(&chip->adc_measure_work);
+ power_supply_unregister(&chip->batt_psy);
+ cancel_work_sync(&chip->batfet_lcl_work);
+ cancel_work_sync(&chip->insertion_ocv_work);
+ cancel_work_sync(&chip->reduce_power_stage_work);
+ alarm_cancel(&chip->reduce_power_stage_alarm);
+
+ mutex_destroy(&chip->batfet_vreg_lock);
+ mutex_destroy(&chip->jeita_configure_lock);
regulator_unregister(chip->otg_vreg.rdev);
regulator_unregister(chip->boost_vreg.rdev);
- dev_set_drvdata(&spmi->dev, NULL);
- kfree(chip);
-
return 0;
}
diff --git a/drivers/sensors/Kconfig b/drivers/sensors/Kconfig
new file mode 100644
index 0000000..2d81924
--- /dev/null
+++ b/drivers/sensors/Kconfig
@@ -0,0 +1,5 @@
+config SENSORS
+ bool "Sensors Class Support"
+ help
+ This option enables the sensor sysfs class in /sys/class/sensors.
+ You'll need this to do anything useful with sensorss. If unsure, say N.
diff --git a/drivers/sensors/Makefile b/drivers/sensors/Makefile
new file mode 100644
index 0000000..3a2a848
--- /dev/null
+++ b/drivers/sensors/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SENSORS) += sensors_class.o
diff --git a/drivers/sensors/sensors_class.c b/drivers/sensors/sensors_class.c
new file mode 100644
index 0000000..74e0d8d
--- /dev/null
+++ b/drivers/sensors/sensors_class.c
@@ -0,0 +1,175 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/ctype.h>
+#include <linux/rwsem.h>
+#include <linux/sensors.h>
+
+static struct class *sensors_class;
+
+DECLARE_RWSEM(sensors_list_lock);
+LIST_HEAD(sensors_list);
+
+static ssize_t sensors_name_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%s\n", sensors_cdev->name);
+}
+
+static ssize_t sensors_vendor_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%s\n", sensors_cdev->vendor);
+}
+
+static ssize_t sensors_version_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%d\n", sensors_cdev->version);
+}
+
+static ssize_t sensors_handle_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%d\n", sensors_cdev->handle);
+}
+
+static ssize_t sensors_type_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%d\n", sensors_cdev->type);
+}
+
+static ssize_t sensors_max_range_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%s\n", sensors_cdev->max_range);
+}
+
+static ssize_t sensors_resolution_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%s\n", sensors_cdev->resolution);
+}
+
+static ssize_t sensors_power_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%s\n", sensors_cdev->sensor_power);
+}
+
+static ssize_t sensors_min_delay_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%d\n", sensors_cdev->min_delay);
+}
+
+static ssize_t sensors_fifo_event_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ sensors_cdev->fifo_reserved_event_count);
+}
+
+static ssize_t sensors_fifo_max_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct sensors_classdev *sensors_cdev = dev_get_drvdata(dev);
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ sensors_cdev->fifo_max_event_count);
+}
+
+static struct device_attribute sensors_class_attrs[] = {
+ __ATTR(name, 0444, sensors_name_show, NULL),
+ __ATTR(vendor, 0444, sensors_vendor_show, NULL),
+ __ATTR(version, 0444, sensors_version_show, NULL),
+ __ATTR(handle, 0444, sensors_handle_show, NULL),
+ __ATTR(type, 0444, sensors_type_show, NULL),
+ __ATTR(max_range, 0444, sensors_max_range_show, NULL),
+ __ATTR(resolution, 0444, sensors_resolution_show, NULL),
+ __ATTR(sensor_power, 0444, sensors_power_show, NULL),
+ __ATTR(min_delay, 0444, sensors_min_delay_show, NULL),
+ __ATTR(fifo_reserved_event_count, 0444, sensors_fifo_event_show, NULL),
+ __ATTR(fifo_max_event_count, 0444, sensors_fifo_max_show, NULL),
+ __ATTR_NULL,
+};
+
+/**
+ * sensors_classdev_register - register a new object of sensors_classdev class.
+ * @parent: The device to register.
+ * @sensors_cdev: the sensors_classdev structure for this device.
+*/
+int sensors_classdev_register(struct device *parent,
+ struct sensors_classdev *sensors_cdev)
+{
+ sensors_cdev->dev = device_create(sensors_class, parent, 0,
+ sensors_cdev, "%s", sensors_cdev->name);
+ if (IS_ERR(sensors_cdev->dev))
+ return PTR_ERR(sensors_cdev->dev);
+
+ down_write(&sensors_list_lock);
+ list_add_tail(&sensors_cdev->node, &sensors_list);
+ up_write(&sensors_list_lock);
+
+ pr_debug("Registered sensors device: %s\n",
+ sensors_cdev->name);
+ return 0;
+}
+EXPORT_SYMBOL(sensors_classdev_register);
+
+/**
+ * sensors_classdev_unregister - unregister a object of sensors class.
+ * @sensors_cdev: the sensor device to unregister
+ * Unregister a previously registered via sensors_classdev_register object.
+*/
+void sensors_classdev_unregister(struct sensors_classdev *sensors_cdev)
+{
+ device_unregister(sensors_cdev->dev);
+ down_write(&sensors_list_lock);
+ list_del(&sensors_cdev->node);
+ up_write(&sensors_list_lock);
+}
+EXPORT_SYMBOL(sensors_classdev_unregister);
+
+static int __init sensors_init(void)
+{
+ sensors_class = class_create(THIS_MODULE, "sensors");
+ if (IS_ERR(sensors_class))
+ return PTR_ERR(sensors_class);
+ sensors_class->dev_attrs = sensors_class_attrs;
+ return 0;
+}
+
+static void __exit sensors_exit(void)
+{
+ class_destroy(sensors_class);
+}
+
+subsys_initcall(sensors_init);
+module_exit(sensors_exit);
diff --git a/drivers/staging/android/lowmemorykiller.c b/drivers/staging/android/lowmemorykiller.c
index 4251968..1ad0054 100644
--- a/drivers/staging/android/lowmemorykiller.c
+++ b/drivers/staging/android/lowmemorykiller.c
@@ -40,6 +40,7 @@
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/swap.h>
+#include <linux/fs.h>
#ifdef CONFIG_HIGHMEM
#define _ZONE ZONE_HIGHMEM
@@ -246,8 +247,14 @@
}
other_free = global_page_state(NR_FREE_PAGES);
- other_file = global_page_state(NR_FILE_PAGES) -
- global_page_state(NR_SHMEM);
+
+ if (global_page_state(NR_SHMEM) + total_swapcache_pages <
+ global_page_state(NR_FILE_PAGES))
+ other_file = global_page_state(NR_FILE_PAGES) -
+ global_page_state(NR_SHMEM) -
+ total_swapcache_pages;
+ else
+ other_file = 0;
tune_lmk_param(&other_free, &other_file, sc);
diff --git a/drivers/staging/zsmalloc/zsmalloc-main.c b/drivers/staging/zsmalloc/zsmalloc-main.c
index 523b937..41a6803 100644
--- a/drivers/staging/zsmalloc/zsmalloc-main.c
+++ b/drivers/staging/zsmalloc/zsmalloc-main.c
@@ -430,7 +430,12 @@
return next;
}
-/* Encode <page, obj_idx> as a single handle value */
+/*
+ * Encode <page, obj_idx> as a single handle value.
+ * On hardware platforms with physical memory starting at 0x0 the pfn
+ * could be 0 so we ensure that the handle will never be 0 by adjusting the
+ * encoded obj_idx value before encoding.
+ */
static void *obj_location_to_handle(struct page *page, unsigned long obj_idx)
{
unsigned long handle;
@@ -441,17 +446,21 @@
}
handle = page_to_pfn(page) << OBJ_INDEX_BITS;
- handle |= (obj_idx & OBJ_INDEX_MASK);
+ handle |= ((obj_idx + 1) & OBJ_INDEX_MASK);
return (void *)handle;
}
-/* Decode <page, obj_idx> pair from the given object handle */
+/*
+ * Decode <page, obj_idx> pair from the given object handle. We adjust the
+ * decoded obj_idx back to its original value since it was adjusted in
+ * obj_location_to_handle().
+ */
static void obj_handle_to_location(unsigned long handle, struct page **page,
unsigned long *obj_idx)
{
*page = pfn_to_page(handle >> OBJ_INDEX_BITS);
- *obj_idx = handle & OBJ_INDEX_MASK;
+ *obj_idx = (handle & OBJ_INDEX_MASK) - 1;
}
static unsigned long obj_idx_to_offset(struct page *page,
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 01dce2d..0d17026 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -7,7 +7,7 @@
obj-$(CONFIG_THERMAL_TSENS) += msm_tsens.o
obj-$(CONFIG_THERMAL_TSENS8960) += msm8960_tsens.o
obj-$(CONFIG_THERMAL_PM8XXX) += pm8xxx-tm.o
-obj-$(CONFIG_THERMAL_MONITOR) += msm_thermal.o
+obj-$(CONFIG_THERMAL_MONITOR) += msm_thermal.o msm_thermal-dev.o
obj-$(CONFIG_SPEAR_THERMAL) += spear_thermal.o
obj-$(CONFIG_THERMAL_TSENS8974) += msm8974-tsens.o
obj-$(CONFIG_THERMAL_QPNP) += qpnp-temp-alarm.o
diff --git a/drivers/thermal/msm_thermal-dev.c b/drivers/thermal/msm_thermal-dev.c
new file mode 100644
index 0000000..c34dd27
--- /dev/null
+++ b/drivers/thermal/msm_thermal-dev.c
@@ -0,0 +1,224 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/types.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/msm_thermal_ioctl.h>
+#include <linux/msm_thermal.h>
+#include <linux/uaccess.h>
+#include <linux/cdev.h>
+#include <linux/semaphore.h>
+#include <linux/module.h>
+
+struct msm_thermal_ioctl_dev {
+ struct semaphore sem;
+ struct cdev char_dev;
+};
+
+static int msm_thermal_major;
+static struct class *thermal_class;
+static struct msm_thermal_ioctl_dev *msm_thermal_dev;
+
+static int msm_thermal_ioctl_open(struct inode *node, struct file *filep)
+{
+ int ret = 0;
+ struct msm_thermal_ioctl_dev *dev;
+
+ dev = container_of(node->i_cdev, struct msm_thermal_ioctl_dev,
+ char_dev);
+ filep->private_data = dev;
+
+ return ret;
+}
+
+static int msm_thermal_ioctl_release(struct inode *node, struct file *filep)
+{
+ pr_debug("%s: IOCTL: release\n", KBUILD_MODNAME);
+ return 0;
+}
+
+static long validate_and_copy(unsigned int *cmd, unsigned long *arg,
+ struct msm_thermal_ioctl *query)
+{
+ long ret = 0, err_val = 0;
+
+ if ((_IOC_TYPE(*cmd) != MSM_THERMAL_MAGIC_NUM) ||
+ (_IOC_NR(*cmd) >= MSM_CMD_MAX_NR)) {
+ ret = -ENOTTY;
+ goto validate_exit;
+ }
+
+ if (_IOC_DIR(*cmd) & _IOC_READ) {
+ err_val = !access_ok(VERIFY_WRITE, (void __user *)*arg,
+ _IOC_SIZE(*cmd));
+ } else if (_IOC_DIR(*cmd) & _IOC_WRITE) {
+ err_val = !access_ok(VERIFY_READ, (void __user *)*arg,
+ _IOC_SIZE(*cmd));
+ }
+ if (err_val) {
+ ret = -EFAULT;
+ goto validate_exit;
+ }
+
+ if (copy_from_user(query, (void __user *)(*arg),
+ sizeof(struct msm_thermal_ioctl))) {
+ ret = -EACCES;
+ goto validate_exit;
+ }
+
+ if (query->size != sizeof(struct msm_thermal_ioctl)) {
+ pr_err("%s: Invalid input argument size\n", __func__);
+ ret = -EINVAL;
+ goto validate_exit;
+ }
+
+ switch (*cmd) {
+ case MSM_THERMAL_SET_CPU_MAX_FREQUENCY:
+ case MSM_THERMAL_SET_CPU_MIN_FREQUENCY:
+ if (query->cpu_freq.cpu_num >= num_possible_cpus()) {
+ pr_err("%s: Invalid CPU number: %u\n", __func__,
+ query->cpu_freq.cpu_num);
+ ret = -EINVAL;
+ goto validate_exit;
+ }
+ break;
+ default:
+ ret = -ENOTTY;
+ goto validate_exit;
+ break;
+ }
+
+validate_exit:
+ return ret;
+}
+
+static long msm_thermal_ioctl_process(struct file *filep, unsigned int cmd,
+ unsigned long arg)
+{
+ long ret = 0;
+ struct msm_thermal_ioctl query;
+
+ pr_debug("%s: IOCTL: processing cmd:%u\n", KBUILD_MODNAME, cmd);
+
+ ret = validate_and_copy(&cmd, &arg, &query);
+ if (ret)
+ goto process_exit;
+
+ switch (cmd) {
+ case MSM_THERMAL_SET_CPU_MAX_FREQUENCY:
+ ret = msm_thermal_set_frequency(query.cpu_freq.cpu_num,
+ query.cpu_freq.freq_req, true);
+ break;
+ case MSM_THERMAL_SET_CPU_MIN_FREQUENCY:
+ ret = msm_thermal_set_frequency(query.cpu_freq.cpu_num,
+ query.cpu_freq.freq_req, false);
+ break;
+ default:
+ ret = -ENOTTY;
+ goto process_exit;
+ }
+process_exit:
+ return ret;
+}
+
+static const struct file_operations msm_thermal_fops = {
+ .owner = THIS_MODULE,
+ .open = msm_thermal_ioctl_open,
+ .unlocked_ioctl = msm_thermal_ioctl_process,
+ .release = msm_thermal_ioctl_release,
+};
+
+int msm_thermal_ioctl_init()
+{
+ int ret = 0;
+ dev_t thermal_dev;
+ struct device *therm_device;
+
+ ret = alloc_chrdev_region(&thermal_dev, 0, 1,
+ MSM_THERMAL_IOCTL_NAME);
+ if (ret < 0) {
+ pr_err("%s: Error in allocating char device region. Err:%d\n",
+ KBUILD_MODNAME, ret);
+ goto ioctl_init_exit;
+ }
+
+ msm_thermal_major = MAJOR(thermal_dev);
+
+ thermal_class = class_create(THIS_MODULE, "msm_thermal");
+ if (IS_ERR(thermal_class)) {
+ pr_err("%s: Error in creating class\n",
+ KBUILD_MODNAME);
+ ret = PTR_ERR(thermal_class);
+ goto ioctl_class_fail;
+ }
+
+ therm_device = device_create(thermal_class, NULL, thermal_dev, NULL,
+ MSM_THERMAL_IOCTL_NAME);
+ if (IS_ERR(therm_device)) {
+ pr_err("%s: Error in creating character device\n",
+ KBUILD_MODNAME);
+ ret = PTR_ERR(therm_device);
+ goto ioctl_dev_fail;
+ }
+ msm_thermal_dev = kmalloc(sizeof(struct msm_thermal_ioctl_dev),
+ GFP_KERNEL);
+ if (!msm_thermal_dev) {
+ pr_err("%s: Error allocating memory\n",
+ KBUILD_MODNAME);
+ ret = -ENOMEM;
+ goto ioctl_clean_all;
+ }
+
+ memset(msm_thermal_dev, 0, sizeof(struct msm_thermal_ioctl_dev));
+ sema_init(&msm_thermal_dev->sem, 1);
+ cdev_init(&msm_thermal_dev->char_dev, &msm_thermal_fops);
+ ret = cdev_add(&msm_thermal_dev->char_dev, thermal_dev, 1);
+ if (ret < 0) {
+ pr_err("%s: Error in adding character device\n",
+ KBUILD_MODNAME);
+ goto ioctl_clean_all;
+ }
+
+ return ret;
+
+ioctl_clean_all:
+ device_destroy(thermal_class, thermal_dev);
+ioctl_dev_fail:
+ class_destroy(thermal_class);
+ioctl_class_fail:
+ unregister_chrdev_region(thermal_dev, 1);
+ioctl_init_exit:
+ return ret;
+}
+
+void msm_thermal_ioctl_cleanup()
+{
+ dev_t thermal_dev = MKDEV(msm_thermal_major, 0);
+
+ if (!msm_thermal_dev) {
+ pr_err("%s: Thermal IOCTL cleanup already done\n",
+ KBUILD_MODNAME);
+ return;
+ }
+
+ device_destroy(thermal_class, thermal_dev);
+ class_destroy(thermal_class);
+ cdev_del(&msm_thermal_dev->char_dev);
+ unregister_chrdev_region(thermal_dev, 1);
+ kfree(msm_thermal_dev);
+ msm_thermal_dev = NULL;
+ thermal_class = NULL;
+}
diff --git a/drivers/thermal/msm_thermal.c b/drivers/thermal/msm_thermal.c
index c6f6f03..c366086 100644
--- a/drivers/thermal/msm_thermal.c
+++ b/drivers/thermal/msm_thermal.c
@@ -35,12 +35,13 @@
#include <mach/rpm-regulator.h>
#include <mach/rpm-regulator-smd.h>
#include <linux/regulator/consumer.h>
+#include <linux/msm_thermal_ioctl.h>
+#define MAX_CURRENT_UA 1000000
#define MAX_RAILS 5
+#define MAX_THRESHOLD 2
static struct msm_thermal_data msm_thermal_info;
-static uint32_t limited_max_freq = UINT_MAX;
-static uint32_t limited_min_freq;
static struct delayed_work check_temp_work;
static bool core_control_enabled;
static uint32_t cpus_offlined;
@@ -51,11 +52,14 @@
static struct kobject *cc_kobj;
static struct work_struct timer_work;
static struct task_struct *hotplug_task;
+static struct task_struct *freq_mitigation_task;
static struct completion hotplug_notify_complete;
+static struct completion freq_mitigation_complete;
static int enabled;
static int rails_cnt;
static int psm_rails_cnt;
+static int ocr_rail_cnt;
static int limit_idx;
static int limit_idx_low;
static int limit_idx_high;
@@ -69,16 +73,39 @@
static bool psm_enabled;
static bool psm_nodes_called;
static bool psm_probed;
+static bool hotplug_enabled;
+static bool freq_mitigation_enabled;
+static bool ocr_enabled;
+static bool ocr_nodes_called;
+static bool ocr_probed;
static int *tsens_id_map;
static DEFINE_MUTEX(vdd_rstr_mutex);
static DEFINE_MUTEX(psm_mutex);
+static DEFINE_MUTEX(ocr_mutex);
+static uint32_t min_freq_limit;
+
+enum thermal_threshold {
+ HOTPLUG_THRESHOLD_HIGH,
+ HOTPLUG_THRESHOLD_LOW,
+ FREQ_THRESHOLD_HIGH,
+ FREQ_THRESHOLD_LOW,
+ THRESHOLD_MAX_NR,
+};
struct cpu_info {
uint32_t cpu;
+ const char *sensor_type;
+ uint32_t sensor_id;
bool offline;
bool user_offline;
- const char *sensor_type;
- struct sensor_threshold thresh[2];
+ bool hotplug_thresh_clear;
+ struct sensor_threshold threshold[THRESHOLD_MAX_NR];
+ bool max_freq;
+ uint32_t user_max_freq;
+ uint32_t user_min_freq;
+ uint32_t limited_max_freq;
+ uint32_t limited_min_freq;
+ bool freq_thresh_clear;
};
struct rail {
@@ -100,10 +127,12 @@
uint8_t mode;
struct kobj_attribute mode_attr;
struct rpm_regulator *reg;
+ struct regulator *phase_reg;
struct attribute_group attr_gp;
};
static struct psm_rail *psm_rails;
+static struct psm_rail *ocr_rails;
static struct rail *rails;
static struct cpu_info cpus[NR_CPUS];
@@ -119,6 +148,12 @@
PMIC_PWM_MODE = RPM_REGULATOR_MODE_HPM,
};
+enum ocr_request {
+ OPTIMUM_CURRENT_MIN,
+ OPTIMUM_CURRENT_MAX,
+ OPTIMUM_CURRENT_NR,
+};
+
#define VDD_RES_RO_ATTRIB(_rail, ko_attr, j, _name) \
ko_attr.attr.name = __stringify(_name); \
ko_attr.attr.mode = 444; \
@@ -144,6 +179,14 @@
#define VDD_RSTR_REG_LEVEL_FROM_ATTRIBS(attr) \
(container_of(attr, struct rail, level_attr));
+#define OCR_RW_ATTRIB(_rail, ko_attr, j, _name) \
+ ko_attr.attr.name = __stringify(_name); \
+ ko_attr.attr.mode = 644; \
+ ko_attr.show = ocr_reg_##_name##_show; \
+ ko_attr.store = ocr_reg_##_name##_store; \
+ sysfs_attr_init(&ko_attr.attr); \
+ _rail.attr_gp.attrs[j] = &ko_attr.attr;
+
#define PSM_RW_ATTRIB(_rail, ko_attr, j, _name) \
ko_attr.attr.name = __stringify(_name); \
ko_attr.attr.mode = 644; \
@@ -159,11 +202,20 @@
unsigned long event, void *data)
{
struct cpufreq_policy *policy = data;
+ uint32_t max_freq_req = cpus[policy->cpu].limited_max_freq;
+ uint32_t min_freq_req = cpus[policy->cpu].limited_min_freq;
switch (event) {
case CPUFREQ_INCOMPATIBLE:
- cpufreq_verify_within_limits(policy, limited_min_freq,
- limited_max_freq);
+ pr_debug("%s: mitigating cpu %d to freq max: %u min: %u\n",
+ KBUILD_MODNAME, policy->cpu, max_freq_req, min_freq_req);
+
+ cpufreq_verify_within_limits(policy, min_freq_req,
+ max_freq_req);
+
+ if (max_freq_req < min_freq_req)
+ pr_err("Invalid frequency request Max:%u Min:%u\n",
+ max_freq_req, min_freq_req);
break;
}
return NOTIFY_OK;
@@ -189,9 +241,17 @@
return ret;
}
+static void update_cpu_freq(int cpu)
+{
+ if (cpu_online(cpu)) {
+ if (cpufreq_update_policy(cpu))
+ pr_err("Unable to update policy for cpu:%d\n", cpu);
+ }
+}
+
static int update_cpu_min_freq_all(uint32_t min)
{
- int cpu = 0;
+ uint32_t cpu = 0;
int ret = 0;
if (!freq_table_get) {
@@ -204,15 +264,17 @@
/* If min is larger than allowed max */
min = min(min, table[limit_idx_high].frequency);
- limited_min_freq = min;
-
- get_online_cpus();
- for_each_online_cpu(cpu) {
- if (cpufreq_update_policy(cpu))
- pr_info("%s: Unable to update policy for cpu:%d\n",
- KBUILD_MODNAME, cpu);
+ if (freq_mitigation_task) {
+ min_freq_limit = min;
+ complete(&freq_mitigation_complete);
+ } else {
+ get_online_cpus();
+ for_each_possible_cpu(cpu) {
+ cpus[cpu].limited_min_freq = min;
+ update_cpu_freq(cpu);
+ }
+ put_online_cpus();
}
- put_online_cpus();
return ret;
}
@@ -442,6 +504,92 @@
return count;
}
+static int request_optimum_current(struct psm_rail *rail, enum ocr_request req)
+{
+ int ret = 0;
+
+ if ((!rail) || (req >= OPTIMUM_CURRENT_NR) ||
+ (req < 0)) {
+ pr_err("%s:%s Invalid input\n", KBUILD_MODNAME, __func__);
+ ret = -EINVAL;
+ goto request_ocr_exit;
+ }
+
+ ret = regulator_set_optimum_mode(rail->phase_reg,
+ (req == OPTIMUM_CURRENT_MAX) ? MAX_CURRENT_UA : 0);
+ if (ret < 0) {
+ pr_err("%s: Optimum current request failed\n", KBUILD_MODNAME);
+ goto request_ocr_exit;
+ }
+ ret = 0; /*regulator_set_optimum_mode returns the mode on success*/
+ pr_debug("%s: Requested optimum current mode: %d\n",
+ KBUILD_MODNAME, req);
+
+request_ocr_exit:
+ return ret;
+}
+
+static int ocr_set_mode_all(enum ocr_request req)
+{
+ int ret = 0, i;
+
+ for (i = 0; i < ocr_rail_cnt; i++) {
+ if (ocr_rails[i].mode == req)
+ continue;
+ ret = request_optimum_current(&ocr_rails[i], req);
+ if (ret)
+ goto ocr_set_mode_exit;
+ ocr_rails[i].mode = req;
+ }
+
+ocr_set_mode_exit:
+ return ret;
+}
+
+static int ocr_reg_mode_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ struct psm_rail *reg = PSM_REG_MODE_FROM_ATTRIBS(attr);
+ return snprintf(buf, PAGE_SIZE, "%d\n", reg->mode);
+}
+
+static ssize_t ocr_reg_mode_store(struct kobject *kobj,
+ struct kobj_attribute *attr, const char *buf, size_t count)
+{
+ int ret = 0;
+ int val = 0;
+ struct psm_rail *reg = PSM_REG_MODE_FROM_ATTRIBS(attr);
+
+ if (!ocr_enabled)
+ return count;
+
+ mutex_lock(&ocr_mutex);
+ ret = kstrtoint(buf, 10, &val);
+ if (ret) {
+ pr_err("%s: Invalid input %s for mode\n",
+ KBUILD_MODNAME, buf);
+ goto done_ocr_store;
+ }
+
+ if ((val != OPTIMUM_CURRENT_MAX) &&
+ (val != OPTIMUM_CURRENT_MIN)) {
+ pr_err("%s: Invalid value %d for mode\n",
+ KBUILD_MODNAME, val);
+ goto done_ocr_store;
+ }
+
+ if (val != reg->mode) {
+ ret = request_optimum_current(reg, val);
+ if (ret)
+ goto done_ocr_store;
+ reg->mode = val;
+ }
+
+done_ocr_store:
+ mutex_unlock(&ocr_mutex);
+ return count;
+}
+
static int psm_reg_mode_show(
struct kobject *kobj, struct kobj_attribute *attr, char *buf)
{
@@ -603,24 +751,73 @@
return ret;
}
-static int update_cpu_max_freq(int cpu, uint32_t max_freq)
+static int set_and_activate_threshold(uint32_t sensor_id,
+ struct sensor_threshold *threshold)
{
int ret = 0;
- if (max_freq != UINT_MAX)
- pr_info("%s: Limiting cpu%d max frequency to %d\n",
- KBUILD_MODNAME, cpu, max_freq);
- else
- pr_info("%s: Max frequency reset for cpu%d\n",
- KBUILD_MODNAME, cpu);
- get_online_cpus();
- for_each_online_cpu(cpu) {
- if (cpufreq_update_policy(cpu))
- pr_info("%s: Unable to update policy for cpu:%d\n",
- KBUILD_MODNAME, cpu);
+ ret = sensor_set_trip(sensor_id, threshold);
+ if (ret != 0) {
+ pr_err("%s: Error in setting trip %d\n",
+ KBUILD_MODNAME, threshold->trip);
+ goto set_done;
}
- put_online_cpus();
+ ret = sensor_activate_trip(sensor_id, threshold, true);
+ if (ret != 0) {
+ pr_err("%s: Error in enabling trip %d\n",
+ KBUILD_MODNAME, threshold->trip);
+ goto set_done;
+ }
+
+set_done:
+ return ret;
+}
+
+static int set_threshold(uint32_t sensor_id,
+ struct sensor_threshold *threshold)
+{
+ struct tsens_device tsens_dev;
+ int i = 0, ret = 0;
+ long temp;
+
+ if ((!threshold) || check_sensor_id(sensor_id)) {
+ pr_err("%s: Invalid input\n", KBUILD_MODNAME);
+ ret = -EINVAL;
+ goto set_threshold_exit;
+ }
+
+ tsens_dev.sensor_num = sensor_id;
+ ret = tsens_get_temp(&tsens_dev, &temp);
+ if (ret) {
+ pr_err("%s: Unable to read TSENS sensor %d\n",
+ KBUILD_MODNAME, tsens_dev.sensor_num);
+ goto set_threshold_exit;
+ }
+ while (i < MAX_THRESHOLD) {
+ switch (threshold[i].trip) {
+ case THERMAL_TRIP_CONFIGURABLE_HI:
+ if (threshold[i].temp >= temp) {
+ ret = set_and_activate_threshold(sensor_id,
+ &threshold[i]);
+ if (ret)
+ goto set_threshold_exit;
+ }
+ break;
+ case THERMAL_TRIP_CONFIGURABLE_LOW:
+ if (threshold[i].temp <= temp) {
+ ret = set_and_activate_threshold(sensor_id,
+ &threshold[i]);
+ if (ret)
+ goto set_threshold_exit;
+ }
+ break;
+ default:
+ break;
+ }
+ i++;
+ }
+set_threshold_exit:
return ret;
}
@@ -677,7 +874,7 @@
/* Call with core_control_mutex locked */
static int __ref update_offline_cores(int val)
{
- int cpu = 0;
+ uint32_t cpu = 0;
int ret = 0;
if (!core_control_enabled)
@@ -701,8 +898,7 @@
static __ref int do_hotplug(void *data)
{
int ret = 0;
- int cpu = 0;
- uint32_t mask = 0;
+ uint32_t cpu = 0, mask = 0;
if (!core_control_enabled)
return -EINVAL;
@@ -714,6 +910,13 @@
mutex_lock(&core_control_mutex);
for_each_possible_cpu(cpu) {
+ if (hotplug_enabled &&
+ cpus[cpu].hotplug_thresh_clear) {
+ set_threshold(cpus[cpu].sensor_id,
+ &cpus[cpu].threshold[HOTPLUG_THRESHOLD_HIGH]);
+
+ cpus[cpu].hotplug_thresh_clear = false;
+ }
if (cpus[cpu].offline || cpus[cpu].user_offline)
mask |= BIT(cpu);
}
@@ -737,6 +940,63 @@
}
#endif
+static int do_ocr(void)
+{
+ struct tsens_device tsens_dev;
+ long temp = 0;
+ int ret = 0;
+ int i = 0, j = 0;
+ int auto_cnt = 0;
+
+ if (!ocr_enabled)
+ return ret;
+
+ mutex_lock(&ocr_mutex);
+ for (i = 0; i < max_tsens_num; i++) {
+ tsens_dev.sensor_num = tsens_id_map[i];
+ ret = tsens_get_temp(&tsens_dev, &temp);
+ if (ret) {
+ pr_debug("%s: Unable to read TSENS sensor %d\n",
+ __func__, tsens_dev.sensor_num);
+ auto_cnt++;
+ continue;
+ }
+
+ if (temp > msm_thermal_info.ocr_temp_degC) {
+ if (ocr_rails[0].init != OPTIMUM_CURRENT_NR)
+ for (j = 0; j < ocr_rail_cnt; j++)
+ ocr_rails[j].init = OPTIMUM_CURRENT_NR;
+ ret = ocr_set_mode_all(OPTIMUM_CURRENT_MAX);
+ if (ret)
+ pr_err("Error setting max optimum current\n");
+ goto do_ocr_exit;
+ } else if (temp <= (msm_thermal_info.ocr_temp_degC -
+ msm_thermal_info.ocr_temp_hyst_degC))
+ auto_cnt++;
+ }
+
+ if (auto_cnt == max_tsens_num ||
+ ocr_rails[0].init != OPTIMUM_CURRENT_NR) {
+ /* 'init' not equal to OPTIMUM_CURRENT_NR means this is the
+ ** first polling iteration after device probe. During first
+ ** iteration, if temperature is less than the set point, clear
+ ** the max current request made and reset the 'init'.
+ */
+ if (ocr_rails[0].init != OPTIMUM_CURRENT_NR)
+ for (j = 0; j < ocr_rail_cnt; j++)
+ ocr_rails[j].init = OPTIMUM_CURRENT_NR;
+ ret = ocr_set_mode_all(OPTIMUM_CURRENT_MIN);
+ if (ret) {
+ pr_err("Error setting min optimum current\n");
+ goto do_ocr_exit;
+ }
+ }
+
+do_ocr_exit:
+ mutex_unlock(&ocr_mutex);
+ return ret;
+}
+
static int do_vdd_restriction(void)
{
struct tsens_device tsens_dev;
@@ -836,14 +1096,14 @@
static void __ref do_freq_control(long temp)
{
- int cpu = 0;
- uint32_t max_freq = limited_max_freq;
+ uint32_t cpu = 0;
+ uint32_t max_freq = cpus[cpu].limited_max_freq;
if (temp >= msm_thermal_info.limit_temp_degC) {
if (limit_idx == limit_idx_low)
return;
- limit_idx -= msm_thermal_info.freq_step;
+ limit_idx -= msm_thermal_info.bootup_freq_step;
if (limit_idx < limit_idx_low)
limit_idx = limit_idx_low;
max_freq = table[limit_idx].frequency;
@@ -852,7 +1112,7 @@
if (limit_idx == limit_idx_high)
return;
- limit_idx += msm_thermal_info.freq_step;
+ limit_idx += msm_thermal_info.bootup_freq_step;
if (limit_idx >= limit_idx_high) {
limit_idx = limit_idx_high;
max_freq = UINT_MAX;
@@ -860,16 +1120,18 @@
max_freq = table[limit_idx].frequency;
}
- if (max_freq == limited_max_freq)
+ if (max_freq == cpus[cpu].limited_max_freq)
return;
- limited_max_freq = max_freq;
/* Update new limits */
+ get_online_cpus();
for_each_possible_cpu(cpu) {
- if (!(msm_thermal_info.freq_control_mask & BIT(cpu)))
+ if (!(msm_thermal_info.bootup_freq_control_mask & BIT(cpu)))
continue;
- update_cpu_max_freq(cpu, max_freq);
+ cpus[cpu].limited_max_freq = max_freq;
+ update_cpu_freq(cpu);
}
+ put_online_cpus();
}
static void __ref check_temp(struct work_struct *work)
@@ -898,6 +1160,7 @@
do_core_control(temp);
do_vdd_restriction();
do_psm();
+ do_ocr();
do_freq_control(temp);
reschedule:
@@ -909,7 +1172,7 @@
static int __ref msm_thermal_cpu_callback(struct notifier_block *nfb,
unsigned long action, void *hcpu)
{
- unsigned int cpu = (unsigned long)hcpu;
+ uint32_t cpu = (uint32_t)hcpu;
if (action == CPU_UP_PREPARE || action == CPU_UP_PREPARE_FROZEN) {
if (core_control_enabled &&
@@ -984,10 +1247,12 @@
default:
break;
}
- if (hotplug_task)
+ if (hotplug_task) {
+ cpu_node->hotplug_thresh_clear = true;
complete(&hotplug_notify_complete);
- else
+ } else {
pr_err("%s: Hotplug task is not initialized\n", KBUILD_MODNAME);
+ }
return 0;
}
/* Adjust cpus offlined bit based on temperature reading. */
@@ -995,17 +1260,20 @@
{
struct tsens_device tsens_dev;
long temp = 0;
- int cpu = 0;
+ uint32_t cpu = 0;
+
+ if (!hotplug_enabled)
+ return 0;
mutex_lock(&core_control_mutex);
for_each_possible_cpu(cpu) {
if (!(msm_thermal_info.core_control_mask & BIT(cpus[cpu].cpu)))
continue;
- tsens_dev.sensor_num = sensor_get_id(\
- (char *)cpus[cpu].sensor_type);
+ tsens_dev.sensor_num = cpus[cpu].sensor_id;
if (tsens_get_temp(&tsens_dev, &temp)) {
pr_err("%s: Unable to read TSENS sensor %d\n",
KBUILD_MODNAME, tsens_dev.sensor_num);
+ mutex_unlock(&core_control_mutex);
return -EINVAL;
}
@@ -1029,31 +1297,34 @@
static void hotplug_init(void)
{
- int cpu = 0;
+ uint32_t cpu = 0;
+ struct sensor_threshold *hi_thresh = NULL, *low_thresh = NULL;
if (hotplug_task)
return;
+ if (!hotplug_enabled)
+ goto init_kthread;
+
for_each_possible_cpu(cpu) {
+ cpus[cpu].sensor_id =
+ sensor_get_id((char *)cpus[cpu].sensor_type);
if (!(msm_thermal_info.core_control_mask & BIT(cpus[cpu].cpu)))
continue;
- cpus[cpu].cpu = (uint32_t)cpu;
- cpus[cpu].thresh[0].temp = msm_thermal_info.hotplug_temp_degC;
- cpus[cpu].thresh[0].trip = THERMAL_TRIP_CONFIGURABLE_HI;
- cpus[cpu].thresh[0].notify = hotplug_notify;
- cpus[cpu].thresh[0].data = (void *)&cpus[cpu];
- sensor_set_trip(sensor_get_id((char *)cpus[cpu].sensor_type),
- &cpus[cpu].thresh[0]);
- cpus[cpu].thresh[1].temp = msm_thermal_info.hotplug_temp_degC -
+ hi_thresh = &cpus[cpu].threshold[HOTPLUG_THRESHOLD_HIGH];
+ low_thresh = &cpus[cpu].threshold[HOTPLUG_THRESHOLD_LOW];
+ hi_thresh->temp = msm_thermal_info.hotplug_temp_degC;
+ hi_thresh->trip = THERMAL_TRIP_CONFIGURABLE_HI;
+ low_thresh->temp = msm_thermal_info.hotplug_temp_degC -
msm_thermal_info.hotplug_temp_hysteresis_degC;
- cpus[cpu].thresh[1].trip = THERMAL_TRIP_CONFIGURABLE_LOW;
- cpus[cpu].thresh[1].notify = hotplug_notify;
- cpus[cpu].thresh[1].data = (void *)&cpus[cpu];
- sensor_set_trip(sensor_get_id((char *)cpus[cpu].sensor_type),
- &cpus[cpu].thresh[1]);
+ low_thresh->trip = THERMAL_TRIP_CONFIGURABLE_LOW;
+ hi_thresh->notify = low_thresh->notify = hotplug_notify;
+ hi_thresh->data = low_thresh->data = (void *)&cpus[cpu];
+ set_threshold(cpus[cpu].sensor_id, hi_thresh);
}
+init_kthread:
init_completion(&hotplug_notify_complete);
hotplug_task = kthread_run(do_hotplug, NULL, "msm_thermal:hotplug");
if (IS_ERR(hotplug_task)) {
@@ -1069,6 +1340,167 @@
kthread_stop(hotplug_task);
}
+static __ref int do_freq_mitigation(void *data)
+{
+ int ret = 0;
+ uint32_t cpu = 0, max_freq_req = 0, min_freq_req = 0;
+
+ while (!kthread_should_stop()) {
+ wait_for_completion(&freq_mitigation_complete);
+ INIT_COMPLETION(freq_mitigation_complete);
+
+ get_online_cpus();
+ for_each_possible_cpu(cpu) {
+ max_freq_req = (cpus[cpu].max_freq) ?
+ msm_thermal_info.freq_limit :
+ UINT_MAX;
+ max_freq_req = min(max_freq_req,
+ cpus[cpu].user_max_freq);
+
+ min_freq_req = max(min_freq_limit,
+ cpus[cpu].user_min_freq);
+
+ if ((max_freq_req == cpus[cpu].limited_max_freq)
+ && (min_freq_req ==
+ cpus[cpu].limited_min_freq))
+ goto reset_threshold;
+
+ cpus[cpu].limited_max_freq = max_freq_req;
+ cpus[cpu].limited_min_freq = min_freq_req;
+ update_cpu_freq(cpu);
+reset_threshold:
+ if (freq_mitigation_enabled &&
+ cpus[cpu].freq_thresh_clear) {
+ set_threshold(cpus[cpu].sensor_id,
+ &cpus[cpu].threshold[FREQ_THRESHOLD_HIGH]);
+
+ cpus[cpu].freq_thresh_clear = false;
+ }
+ }
+ put_online_cpus();
+ }
+ return ret;
+}
+
+static int freq_mitigation_notify(enum thermal_trip_type type,
+ int temp, void *data)
+{
+ struct cpu_info *cpu_node = (struct cpu_info *) data;
+
+ pr_debug("%s: %s reached temp threshold: %d\n", KBUILD_MODNAME,
+ cpu_node->sensor_type, temp);
+
+ if (!(msm_thermal_info.freq_mitig_control_mask &
+ BIT(cpu_node->cpu)))
+ return 0;
+
+ switch (type) {
+ case THERMAL_TRIP_CONFIGURABLE_HI:
+ if (!cpu_node->max_freq) {
+ pr_info("%s: Mitigating cpu %d frequency to %d\n",
+ KBUILD_MODNAME, cpu_node->cpu,
+ msm_thermal_info.freq_limit);
+
+ cpu_node->max_freq = true;
+ }
+ break;
+ case THERMAL_TRIP_CONFIGURABLE_LOW:
+ if (cpu_node->max_freq) {
+ pr_info("%s: Removing frequency mitigation for cpu%d\n",
+ KBUILD_MODNAME, cpu_node->cpu);
+
+ cpu_node->max_freq = false;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (freq_mitigation_task) {
+ cpu_node->freq_thresh_clear = true;
+ complete(&freq_mitigation_complete);
+ } else {
+ pr_err("%s: Frequency mitigation task is not initialized\n",
+ KBUILD_MODNAME);
+ }
+
+ return 0;
+}
+
+static void freq_mitigation_init(void)
+{
+ uint32_t cpu = 0;
+ struct sensor_threshold *hi_thresh = NULL, *low_thresh = NULL;
+
+ if (freq_mitigation_task)
+ return;
+ if (!freq_mitigation_enabled)
+ goto init_freq_thread;
+
+ for_each_possible_cpu(cpu) {
+ if (!(msm_thermal_info.freq_mitig_control_mask & BIT(cpu)))
+ continue;
+ hi_thresh = &cpus[cpu].threshold[FREQ_THRESHOLD_HIGH];
+ low_thresh = &cpus[cpu].threshold[FREQ_THRESHOLD_LOW];
+
+ hi_thresh->temp = msm_thermal_info.freq_mitig_temp_degc;
+ hi_thresh->trip = THERMAL_TRIP_CONFIGURABLE_HI;
+ low_thresh->temp = msm_thermal_info.freq_mitig_temp_degc -
+ msm_thermal_info.freq_mitig_temp_hysteresis_degc;
+ low_thresh->trip = THERMAL_TRIP_CONFIGURABLE_LOW;
+ hi_thresh->notify = low_thresh->notify =
+ freq_mitigation_notify;
+ hi_thresh->data = low_thresh->data = (void *)&cpus[cpu];
+
+ set_threshold(cpus[cpu].sensor_id, hi_thresh);
+ }
+init_freq_thread:
+ init_completion(&freq_mitigation_complete);
+ freq_mitigation_task = kthread_run(do_freq_mitigation, NULL,
+ "msm_thermal:freq_mitig");
+
+ if (IS_ERR(freq_mitigation_task)) {
+ pr_err("%s: Failed to create frequency mitigation thread\n",
+ KBUILD_MODNAME);
+ return;
+ }
+}
+
+int msm_thermal_set_frequency(uint32_t cpu, uint32_t freq, bool is_max)
+{
+ int ret = 0;
+
+ if (cpu >= num_possible_cpus()) {
+ pr_err("%s: Invalid input\n", KBUILD_MODNAME);
+ ret = -EINVAL;
+ goto set_freq_exit;
+ }
+
+ if (is_max) {
+ if (cpus[cpu].user_max_freq == freq)
+ goto set_freq_exit;
+
+ cpus[cpu].user_max_freq = freq;
+ } else {
+ if (cpus[cpu].user_min_freq == freq)
+ goto set_freq_exit;
+
+ cpus[cpu].user_min_freq = freq;
+ }
+
+ if (freq_mitigation_task) {
+ complete(&freq_mitigation_complete);
+ } else {
+ pr_err("%s: Frequency mitigation task is not initialized\n",
+ KBUILD_MODNAME);
+ ret = -ESRCH;
+ goto set_freq_exit;
+ }
+
+set_freq_exit:
+ return ret;
+}
+
/*
* We will reset the cpu frequencies limits here. The core online/offline
* status will be carried over to the process stopping the msm_thermal, as
@@ -1076,21 +1508,20 @@
*/
static void __ref disable_msm_thermal(void)
{
- int cpu = 0;
+ uint32_t cpu = 0;
/* make sure check_temp is no longer running */
cancel_delayed_work(&check_temp_work);
flush_scheduled_work();
- if (limited_max_freq == UINT_MAX)
- return;
-
- limited_max_freq = UINT_MAX;
get_online_cpus();
- for_each_online_cpu(cpu) {
- if (cpufreq_update_policy(cpu))
- pr_info("%s: Unable to update policy for cpu:%d\n",
- KBUILD_MODNAME, cpu);
+ for_each_possible_cpu(cpu) {
+ if (cpus[cpu].limited_max_freq == UINT_MAX &&
+ cpus[cpu].limited_min_freq == 0)
+ continue;
+ cpus[cpu].limited_max_freq = UINT_MAX;
+ cpus[cpu].limited_min_freq = 0;
+ update_cpu_freq(cpu);
}
put_online_cpus();
}
@@ -1103,6 +1534,7 @@
if (!enabled) {
disable_msm_thermal();
hotplug_init();
+ freq_mitigation_init();
} else
pr_info("%s: no action for enabled = %d\n",
KBUILD_MODNAME, enabled);
@@ -1170,7 +1602,7 @@
{
int ret = 0;
uint32_t val = 0;
- int cpu;
+ uint32_t cpu;
mutex_lock(&core_control_mutex);
ret = kstrtouint(buf, 10, &val);
@@ -1335,6 +1767,7 @@
int __devinit msm_thermal_init(struct msm_thermal_data *pdata)
{
int ret = 0;
+ uint32_t cpu;
BUG_ON(!pdata);
tsens_get_max_sensor_num(&max_tsens_num);
@@ -1346,13 +1779,15 @@
return -EINVAL;
enabled = 1;
-
+ for_each_possible_cpu(cpu) {
+ cpus[cpu].limited_max_freq = UINT_MAX;
+ cpus[cpu].limited_min_freq = 0;
+ }
ret = cpufreq_register_notifier(&msm_thermal_cpufreq_notifier,
CPUFREQ_POLICY_NOTIFIER);
if (ret)
pr_err("%s: cannot register cpufreq notifier\n",
KBUILD_MODNAME);
-
INIT_DELAYED_WORK(&check_temp_work, check_temp);
schedule_delayed_work(&check_temp_work, 0);
@@ -1362,6 +1797,42 @@
return ret;
}
+static int ocr_reg_init(struct platform_device *pdev)
+{
+ int ret = 0;
+ int i, j;
+
+ for (i = 0; i < ocr_rail_cnt; i++) {
+ /* Check if vdd_restriction has already initialized any
+ * regualtor handle. If so use the same handle.*/
+ for (j = 0; j < rails_cnt; j++) {
+ if (!strcmp(ocr_rails[i].name, rails[j].name)) {
+ if (rails[j].reg == NULL)
+ break;
+ ocr_rails[i].phase_reg = rails[j].reg;
+ goto reg_init;
+ }
+
+ }
+ ocr_rails[i].phase_reg = devm_regulator_get(&pdev->dev,
+ ocr_rails[i].name);
+ if (IS_ERR_OR_NULL(ocr_rails[i].phase_reg)) {
+ ret = PTR_ERR(ocr_rails[i].phase_reg);
+ if (ret != -EPROBE_DEFER) {
+ pr_err("%s, could not get regulator: %s\n",
+ __func__, ocr_rails[i].name);
+ ocr_rails[i].phase_reg = NULL;
+ ocr_rails[i].mode = 0;
+ ocr_rails[i].init = 0;
+ }
+ return ret;
+ }
+reg_init:
+ ocr_rails[i].mode = OPTIMUM_CURRENT_MIN;
+ }
+ return ret;
+}
+
static int vdd_restriction_reg_init(struct platform_device *pdev)
{
int ret = 0;
@@ -1531,6 +2002,80 @@
return rc;
}
+static int msm_thermal_add_ocr_nodes(void)
+{
+ struct kobject *module_kobj = NULL;
+ struct kobject *ocr_kobj = NULL;
+ struct kobject *ocr_reg_kobj[MAX_RAILS] = {0};
+ int rc = 0;
+ int i = 0;
+
+ if (!ocr_probed) {
+ ocr_nodes_called = true;
+ return rc;
+ }
+
+ if (ocr_probed && ocr_rail_cnt == 0)
+ return rc;
+
+ module_kobj = kset_find_obj(module_kset, KBUILD_MODNAME);
+ if (!module_kobj) {
+ pr_err("%s: cannot find kobject for module %s\n",
+ __func__, KBUILD_MODNAME);
+ rc = -ENOENT;
+ goto ocr_node_exit;
+ }
+
+ ocr_kobj = kobject_create_and_add("opt_curr_req", module_kobj);
+ if (!ocr_kobj) {
+ pr_err("%s: cannot create ocr kobject\n", KBUILD_MODNAME);
+ rc = -ENOMEM;
+ goto ocr_node_exit;
+ }
+
+ for (i = 0; i < ocr_rail_cnt; i++) {
+ ocr_reg_kobj[i] = kobject_create_and_add(ocr_rails[i].name,
+ ocr_kobj);
+ if (!ocr_reg_kobj[i]) {
+ pr_err("%s: cannot create for kobject for %s\n",
+ KBUILD_MODNAME, ocr_rails[i].name);
+ rc = -ENOMEM;
+ goto ocr_node_exit;
+ }
+ ocr_rails[i].attr_gp.attrs = kzalloc( \
+ sizeof(struct attribute *) * 2, GFP_KERNEL);
+ if (!ocr_rails[i].attr_gp.attrs) {
+ rc = -ENOMEM;
+ goto ocr_node_exit;
+ }
+
+ OCR_RW_ATTRIB(ocr_rails[i], ocr_rails[i].mode_attr, 0, mode);
+ ocr_rails[i].attr_gp.attrs[1] = NULL;
+
+ rc = sysfs_create_group(ocr_reg_kobj[i], &ocr_rails[i].attr_gp);
+ if (rc) {
+ pr_err("%s: cannot create attribute group for %s\n",
+ KBUILD_MODNAME, ocr_rails[i].name);
+ goto ocr_node_exit;
+ }
+ }
+
+ocr_node_exit:
+ if (rc) {
+ for (i = 0; i < ocr_rail_cnt; i++) {
+ if (ocr_reg_kobj[i])
+ kobject_del(ocr_reg_kobj[i]);
+ if (ocr_rails[i].attr_gp.attrs) {
+ kfree(ocr_rails[i].attr_gp.attrs);
+ ocr_rails[i].attr_gp.attrs = NULL;
+ }
+ }
+ if (ocr_kobj)
+ kobject_del(ocr_kobj);
+ }
+ return rc;
+}
+
static int msm_thermal_add_psm_nodes(void)
{
struct kobject *module_kobj = NULL;
@@ -1703,6 +2248,83 @@
return ret;
}
+static int probe_ocr(struct device_node *node, struct msm_thermal_data *data,
+ struct platform_device *pdev)
+{
+ int ret = 0;
+ int j = 0;
+ char *key = NULL;
+
+ if (ocr_probed) {
+ pr_info("%s: Nodes already probed\n",
+ __func__);
+ goto read_ocr_exit;
+ }
+ ocr_rails = NULL;
+
+ key = "qti,pmic-opt-curr-temp";
+ ret = of_property_read_u32(node, key, &data->ocr_temp_degC);
+ if (ret)
+ goto read_ocr_fail;
+
+ key = "qti,pmic-opt-curr-temp-hysteresis";
+ ret = of_property_read_u32(node, key, &data->ocr_temp_hyst_degC);
+ if (ret)
+ goto read_ocr_fail;
+
+ key = "qti,pmic-opt-curr-regs";
+ ocr_rail_cnt = of_property_count_strings(node, key);
+ ocr_rails = kzalloc(sizeof(struct psm_rail) * ocr_rail_cnt,
+ GFP_KERNEL);
+ if (!ocr_rails) {
+ pr_err("%s: Fail to allocate memory for ocr rails\n", __func__);
+ ocr_rail_cnt = 0;
+ return -ENOMEM;
+ }
+
+ for (j = 0; j < ocr_rail_cnt; j++) {
+ ret = of_property_read_string_index(node, key, j,
+ &ocr_rails[j].name);
+ if (ret)
+ goto read_ocr_fail;
+ ocr_rails[j].phase_reg = NULL;
+ ocr_rails[j].init = OPTIMUM_CURRENT_MAX;
+ }
+
+ if (ocr_rail_cnt) {
+ ret = ocr_reg_init(pdev);
+ if (ret) {
+ pr_info("%s:Failed to get regulators. KTM continues.\n",
+ __func__);
+ goto read_ocr_fail;
+ }
+ ocr_enabled = true;
+ ocr_nodes_called = false;
+ /*
+ * Vote for max optimum current by default until we have made
+ * our first temp reading
+ */
+ if (ocr_set_mode_all(OPTIMUM_CURRENT_MAX))
+ pr_err("Set max optimum current failed\n");
+ }
+
+read_ocr_fail:
+ ocr_probed = true;
+ if (ret) {
+ dev_info(&pdev->dev,
+ "%s:Failed reading node=%s, key=%s. KTM continues\n",
+ __func__, node->full_name, key);
+ if (ocr_rails)
+ kfree(ocr_rails);
+ ocr_rails = NULL;
+ ocr_rail_cnt = 0;
+ }
+ if (ret == -EPROBE_DEFER)
+ ocr_probed = false;
+read_ocr_exit:
+ return ret;
+}
+
static int probe_psm(struct device_node *node, struct msm_thermal_data *data,
struct platform_device *pdev)
{
@@ -1767,9 +2389,14 @@
struct platform_device *pdev)
{
char *key = NULL;
- int cpu_cnt = 0;
+ uint32_t cpu_cnt = 0;
int ret = 0;
- int cpu = 0;
+ uint32_t cpu = 0;
+
+ if (num_possible_cpus() > 1) {
+ core_control_enabled = 1;
+ hotplug_enabled = 1;
+ }
key = "qcom,core-limit-temp";
ret = of_property_read_u32(node, key, &data->core_limit_temp_degC);
@@ -1789,34 +2416,33 @@
key = "qcom,hotplug-temp";
ret = of_property_read_u32(node, key, &data->hotplug_temp_degC);
if (ret)
- goto read_node_fail;
+ goto hotplug_node_fail;
key = "qcom,hotplug-temp-hysteresis";
ret = of_property_read_u32(node, key,
&data->hotplug_temp_hysteresis_degC);
if (ret)
- goto read_node_fail;
+ goto hotplug_node_fail;
key = "qcom,cpu-sensors";
cpu_cnt = of_property_count_strings(node, key);
if (cpu_cnt != num_possible_cpus()) {
pr_err("%s: Wrong number of cpu\n", KBUILD_MODNAME);
- goto read_node_fail;
+ ret = -EINVAL;
+ goto hotplug_node_fail;
}
for_each_possible_cpu(cpu) {
cpus[cpu].cpu = cpu;
cpus[cpu].offline = 0;
cpus[cpu].user_offline = 0;
+ cpus[cpu].hotplug_thresh_clear = false;
ret = of_property_read_string_index(node, key, cpu,
&cpus[cpu].sensor_type);
if (ret)
- goto read_node_fail;
+ goto hotplug_node_fail;
}
- if (num_possible_cpus() > 1)
- core_control_enabled = 1;
-
read_node_fail:
if (ret) {
dev_info(&pdev->dev,
@@ -1826,6 +2452,65 @@
}
return ret;
+
+hotplug_node_fail:
+ if (ret) {
+ dev_info(&pdev->dev,
+ "%s:Failed reading node=%s, key=%s. KTM continues\n",
+ KBUILD_MODNAME, node->full_name, key);
+ hotplug_enabled = 0;
+ }
+
+ return ret;
+}
+
+static int probe_freq_mitigation(struct device_node *node,
+ struct msm_thermal_data *data,
+ struct platform_device *pdev)
+{
+ char *key = NULL;
+ int ret = 0;
+ uint32_t cpu;
+
+ key = "qcom,freq-mitigation-temp";
+ ret = of_property_read_u32(node, key, &data->freq_mitig_temp_degc);
+ if (ret)
+ goto PROBE_FREQ_EXIT;
+
+ key = "qcom,freq-mitigation-temp-hysteresis";
+ ret = of_property_read_u32(node, key,
+ &data->freq_mitig_temp_hysteresis_degc);
+ if (ret)
+ goto PROBE_FREQ_EXIT;
+
+ key = "qcom,freq-mitigation-value";
+ ret = of_property_read_u32(node, key, &data->freq_limit);
+ if (ret)
+ goto PROBE_FREQ_EXIT;
+
+ key = "qcom,freq-mitigation-control-mask";
+ ret = of_property_read_u32(node, key, &data->freq_mitig_control_mask);
+ if (ret)
+ goto PROBE_FREQ_EXIT;
+
+ freq_mitigation_enabled = 1;
+ for_each_possible_cpu(cpu) {
+ cpus[cpu].max_freq = false;
+ cpus[cpu].user_max_freq = UINT_MAX;
+ cpus[cpu].user_min_freq = 0;
+ cpus[cpu].limited_max_freq = UINT_MAX;
+ cpus[cpu].limited_min_freq = 0;
+ cpus[cpu].freq_thresh_clear = false;
+ }
+
+PROBE_FREQ_EXIT:
+ if (ret) {
+ dev_info(&pdev->dev,
+ "%s:Failed reading node=%s, key=%s. KTM continues\n",
+ __func__, node->full_name, key);
+ freq_mitigation_enabled = 0;
+ }
+ return ret;
}
static int __devinit msm_thermal_dev_probe(struct platform_device *pdev)
@@ -1858,18 +2543,23 @@
goto fail;
key = "qcom,freq-step";
- ret = of_property_read_u32(node, key, &data.freq_step);
+ ret = of_property_read_u32(node, key, &data.bootup_freq_step);
if (ret)
goto fail;
key = "qcom,freq-control-mask";
- ret = of_property_read_u32(node, key, &data.freq_control_mask);
+ ret = of_property_read_u32(node, key, &data.bootup_freq_control_mask);
ret = probe_cc(node, &data, pdev);
+
+ ret = probe_freq_mitigation(node, &data, pdev);
/*
* Probe optional properties below. Call probe_psm before
* probe_vdd_rstr because rpm_regulator_get has to be called
* before devm_regulator_get
+ * probe_ocr should be called after probe_vdd_rstr to reuse the
+ * regualtor handle. calling devm_regulator_get more than once
+ * will fail.
*/
ret = probe_psm(node, &data, pdev);
if (ret == -EPROBE_DEFER)
@@ -1877,6 +2567,9 @@
ret = probe_vdd_rstr(node, &data, pdev);
if (ret == -EPROBE_DEFER)
goto fail;
+ ret = probe_ocr(node, &data, pdev);
+ if (ret == -EPROBE_DEFER)
+ goto fail;
/*
* In case sysfs add nodes get called before probe function.
@@ -1890,6 +2583,11 @@
msm_thermal_add_vdd_rstr_nodes();
vdd_rstr_nodes_called = false;
}
+ if (ocr_nodes_called) {
+ msm_thermal_add_ocr_nodes();
+ ocr_nodes_called = false;
+ }
+ msm_thermal_ioctl_init();
ret = msm_thermal_init(&data);
return ret;
@@ -1901,6 +2599,11 @@
return ret;
}
+static int msm_thermal_dev_exit(struct platform_device *inp_dev)
+{
+ msm_thermal_ioctl_cleanup();
+ return 0;
+}
static struct of_device_id msm_thermal_match_table[] = {
{.compatible = "qcom,msm-thermal"},
@@ -1914,6 +2617,7 @@
.owner = THIS_MODULE,
.of_match_table = msm_thermal_match_table,
},
+ .remove = msm_thermal_dev_exit,
};
int __init msm_thermal_device_init(void)
@@ -1927,6 +2631,7 @@
msm_thermal_add_cc_nodes();
msm_thermal_add_psm_nodes();
msm_thermal_add_vdd_rstr_nodes();
+ msm_thermal_add_ocr_nodes();
alarm_init(&thermal_rtc, ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP,
thermal_rtc_callback);
INIT_WORK(&timer_work, timer_work_fn);
diff --git a/drivers/thermal/thermal_sys.c b/drivers/thermal/thermal_sys.c
index 8d9da6b..739696d 100644
--- a/drivers/thermal/thermal_sys.c
+++ b/drivers/thermal/thermal_sys.c
@@ -89,30 +89,21 @@
}
EXPORT_SYMBOL(sensor_get_id);
-static long get_min(struct sensor_info *sensor, long temp)
+static int __update_sensor_thresholds(struct sensor_info *sensor)
{
- long min = LONG_MIN;
- struct sensor_threshold *pos, *var;
-
- list_for_each_entry_safe(pos, var, &sensor->threshold_list, list) {
- if (pos->trip == THERMAL_TRIP_CONFIGURABLE_LOW)
- if (pos->temp < temp && pos->temp > min)
- min = pos->temp;
- }
-
- return min;
-}
-
-static void __update_sensor_thresholds(struct sensor_info *sensor)
-{
- long min = LONG_MIN;
- long max = LONG_MAX;
- long max_of_min = LONG_MIN;
- long min_of_max = LONG_MAX;
+ long max_of_low_thresh = LONG_MIN;
+ long min_of_high_thresh = LONG_MAX;
struct sensor_threshold *pos, *var;
enum thermal_trip_type type;
- int i;
- long curr_temp;
+ int i, ret = 0;
+
+ if (!sensor->tz->ops->set_trip_temp ||
+ !sensor->tz->ops->activate_trip_type ||
+ !sensor->tz->ops->get_trip_type ||
+ !sensor->tz->ops->get_trip_temp) {
+ ret = -ENODEV;
+ goto update_done;
+ }
for (i = 0; ((sensor->max_idx == -1) || (sensor->min_idx == -1)) &&
(sensor->tz->ops->get_trip_type) && (i < sensor->tz->trips);
@@ -128,60 +119,85 @@
THERMAL_TRIP_CONFIGURABLE_HI, &sensor->threshold_max);
}
- sensor->tz->ops->get_temp(sensor->tz, &curr_temp);
list_for_each_entry_safe(pos, var, &sensor->threshold_list, list) {
+ if (!pos->active)
+ continue;
if (pos->trip == THERMAL_TRIP_CONFIGURABLE_LOW) {
- if (pos->temp > max_of_min)
- max_of_min = pos->temp;
- if (pos->temp < curr_temp && pos->temp > min)
- min = pos->temp;
+ if (pos->temp > max_of_low_thresh)
+ max_of_low_thresh = pos->temp;
}
if (pos->trip == THERMAL_TRIP_CONFIGURABLE_HI) {
- if (pos->temp < min_of_max)
- min_of_max = pos->temp;
- if (pos->temp > curr_temp && pos->temp < max)
- max = pos->temp;
+ if (pos->temp < min_of_high_thresh)
+ min_of_high_thresh = pos->temp;
}
}
- pr_debug("sensor %d: min of max: %ld max of min: %ld\n",
- sensor->sensor_id, max_of_min, min_of_max);
+ pr_debug("sensor %d: Thresholds: max of low: %ld min of high: %ld\n",
+ sensor->sensor_id, max_of_low_thresh,
+ min_of_high_thresh);
- /* If we haven't found a max and min bounding the curr_temp,
- * use the min of max and max of min instead.
- */
- if (max == LONG_MAX)
- max = min_of_max;
- if (min == LONG_MIN) {
- min = get_min(sensor, max);
- if (min == LONG_MIN)
- min = max_of_min;
+ if ((min_of_high_thresh != sensor->threshold_max) &&
+ (min_of_high_thresh != LONG_MAX)) {
+ ret = sensor->tz->ops->set_trip_temp(sensor->tz,
+ sensor->max_idx, min_of_high_thresh);
+ if (ret) {
+ pr_err("sensor %d: Unable to set high threshold %d",
+ sensor->sensor_id, ret);
+ goto update_done;
+ }
+ sensor->threshold_max = min_of_high_thresh;
+ }
+ ret = sensor->tz->ops->activate_trip_type(sensor->tz,
+ sensor->max_idx,
+ (min_of_high_thresh == LONG_MAX) ?
+ THERMAL_TRIP_ACTIVATION_DISABLED :
+ THERMAL_TRIP_ACTIVATION_ENABLED);
+ if (ret) {
+ pr_err("sensor %d: Unable to activate high threshold %d",
+ sensor->sensor_id, ret);
+ goto update_done;
}
- if (sensor->tz->ops->set_trip_temp) {
- if (max != sensor->threshold_max) {
- sensor->tz->ops->set_trip_temp(sensor->tz,
- sensor->max_idx, max);
- sensor->threshold_max = max;
+ if ((max_of_low_thresh != sensor->threshold_min) &&
+ (max_of_low_thresh != LONG_MIN)) {
+ ret = sensor->tz->ops->set_trip_temp(sensor->tz,
+ sensor->min_idx, max_of_low_thresh);
+ if (ret) {
+ pr_err("sensor %d: Unable to set low threshold %d",
+ sensor->sensor_id, ret);
+ goto update_done;
}
- if (min != sensor->threshold_min) {
- sensor->tz->ops->set_trip_temp(sensor->tz,
- sensor->min_idx, min);
- sensor->threshold_min = min;
- }
+ sensor->threshold_min = max_of_low_thresh;
+ }
+ ret = sensor->tz->ops->activate_trip_type(sensor->tz,
+ sensor->min_idx,
+ (max_of_low_thresh == LONG_MIN) ?
+ THERMAL_TRIP_ACTIVATION_DISABLED :
+ THERMAL_TRIP_ACTIVATION_ENABLED);
+ if (ret) {
+ pr_err("sensor %d: Unable to activate low threshold %d",
+ sensor->sensor_id, ret);
+ goto update_done;
}
- pr_debug("sensor %d: curr_temp: %ld min: %ld max: %ld\n",
- sensor->sensor_id, curr_temp,
+ pr_debug("sensor %d: low: %ld high: %ld\n",
+ sensor->sensor_id,
sensor->threshold_min, sensor->threshold_max);
+
+update_done:
+ return ret;
}
static void sensor_update_work(struct work_struct *work)
{
struct sensor_info *sensor = container_of(work, struct sensor_info,
work);
+ int ret = 0;
mutex_lock(&sensor->lock);
- __update_sensor_thresholds(sensor);
+ ret = __update_sensor_thresholds(sensor);
+ if (ret)
+ pr_err("sensor %d: Error %d setting threshold\n",
+ sensor->sensor_id, ret);
mutex_unlock(&sensor->lock);
}
@@ -202,7 +218,7 @@
return 0;
list_for_each_entry_safe(pos, var, &tz->sensor.threshold_list, list) {
- if (pos->trip != trip)
+ if ((pos->trip != trip) || (!pos->active))
continue;
if (((trip == THERMAL_TRIP_CONFIGURABLE_LOW) &&
(pos->temp <= tz->sensor.threshold_min) &&
@@ -210,6 +226,7 @@
((trip == THERMAL_TRIP_CONFIGURABLE_HI) &&
(pos->temp >= tz->sensor.threshold_max) &&
(pos->temp <= temp))) {
+ pos->active = 0;
pos->notify(trip, temp, pos->data);
}
}
@@ -220,6 +237,29 @@
}
EXPORT_SYMBOL(thermal_sensor_trip);
+int sensor_activate_trip(uint32_t sensor_id,
+ struct sensor_threshold *threshold, bool enable)
+{
+ struct sensor_info *sensor = get_sensor(sensor_id);
+ int ret = 0;
+
+ if (!sensor || !threshold) {
+ pr_err("Sensor %d: uninitialized data\n",
+ sensor_id);
+ ret = -ENODEV;
+ goto activate_trip_exit;
+ }
+
+ mutex_lock(&sensor->lock);
+ threshold->active = (enable) ? 1 : 0;
+ ret = __update_sensor_thresholds(sensor);
+ mutex_unlock(&sensor->lock);
+
+activate_trip_exit:
+ return ret;
+}
+EXPORT_SYMBOL(sensor_activate_trip);
+
int sensor_set_trip(uint32_t sensor_id, struct sensor_threshold *threshold)
{
struct sensor_threshold *pos, *var;
@@ -241,8 +281,7 @@
INIT_LIST_HEAD(&threshold->list);
list_add(&threshold->list, &sensor->threshold_list);
}
-
- __update_sensor_thresholds(sensor);
+ threshold->active = 0; /* Do not allow active threshold right away */
mutex_unlock(&sensor->lock);
return 0;
@@ -254,6 +293,7 @@
{
struct sensor_threshold *pos, *var;
struct sensor_info *sensor = get_sensor(sensor_id);
+ int ret = 0;
if (!sensor)
return -ENODEV;
@@ -261,15 +301,16 @@
mutex_lock(&sensor->lock);
list_for_each_entry_safe(pos, var, &sensor->threshold_list, list) {
if (pos == threshold) {
+ pos->active = 0;
list_del(&pos->list);
break;
}
}
- __update_sensor_thresholds(sensor);
+ ret = __update_sensor_thresholds(sensor);
mutex_unlock(&sensor->lock);
- return 0;
+ return ret;
}
EXPORT_SYMBOL(sensor_cancel_trip);
@@ -283,36 +324,36 @@
return 0;
}
+static void get_trip_threshold(struct thermal_zone_device *tz, int trip,
+ struct sensor_threshold **threshold)
+{
+ enum thermal_trip_type type;
+
+ tz->ops->get_trip_type(tz, trip, &type);
+
+ if (type == THERMAL_TRIP_CONFIGURABLE_HI)
+ *threshold = &tz->tz_threshold[0];
+ else if (type == THERMAL_TRIP_CONFIGURABLE_LOW)
+ *threshold = &tz->tz_threshold[1];
+ else
+ *threshold = NULL;
+}
+
int sensor_set_trip_temp(struct thermal_zone_device *tz,
int trip, long temp)
{
int ret = 0;
- enum thermal_trip_type type;
+ struct sensor_threshold *threshold = NULL;
if (!tz->ops->get_trip_type)
return -EPERM;
- tz->ops->get_trip_type(tz, trip, &type);
- switch (type) {
- case THERMAL_TRIP_CONFIGURABLE_HI:
- tz->tz_threshold[0].temp = temp;
- tz->tz_threshold[0].trip = THERMAL_TRIP_CONFIGURABLE_HI;
- tz->tz_threshold[0].notify = tz_notify_trip;
- tz->tz_threshold[0].data = tz;
- ret = sensor_set_trip(tz->sensor.sensor_id,
- &tz->tz_threshold[0]);
- break;
- case THERMAL_TRIP_CONFIGURABLE_LOW:
- tz->tz_threshold[1].temp = temp;
- tz->tz_threshold[1].trip = THERMAL_TRIP_CONFIGURABLE_LOW;
- tz->tz_threshold[1].notify = tz_notify_trip;
- tz->tz_threshold[1].data = tz;
- ret = sensor_set_trip(tz->sensor.sensor_id,
- &tz->tz_threshold[1]);
- break;
- default:
+ get_trip_threshold(tz, trip, &threshold);
+ if (threshold) {
+ threshold->temp = temp;
+ ret = sensor_set_trip(tz->sensor.sensor_id, threshold);
+ } else {
ret = tz->ops->set_trip_temp(tz, trip, temp);
- break;
}
return ret;
@@ -333,10 +374,12 @@
INIT_LIST_HEAD(&sensor->threshold_list);
INIT_LIST_HEAD(&tz->tz_threshold[0].list);
INIT_LIST_HEAD(&tz->tz_threshold[1].list);
- tz->tz_threshold[0].notify = NULL;
- tz->tz_threshold[0].data = NULL;
- tz->tz_threshold[1].notify = NULL;
- tz->tz_threshold[1].data = NULL;
+ tz->tz_threshold[0].notify = tz_notify_trip;
+ tz->tz_threshold[0].data = tz;
+ tz->tz_threshold[0].trip = THERMAL_TRIP_CONFIGURABLE_HI;
+ tz->tz_threshold[1].notify = tz_notify_trip;
+ tz->tz_threshold[1].data = tz;
+ tz->tz_threshold[1].trip = THERMAL_TRIP_CONFIGURABLE_LOW;
list_add(&sensor->sensor_list, &sensor_info_list);
INIT_WORK(&sensor->work, sensor_update_work);
@@ -489,23 +532,40 @@
const char *buf, size_t count)
{
struct thermal_zone_device *tz = to_thermal_zone(dev);
- int trip, result;
+ int trip, result = 0;
+ bool activate;
+ struct sensor_threshold *threshold = NULL;
- if (!tz->ops->activate_trip_type)
- return -EPERM;
+ if (!tz->ops->get_trip_type ||
+ !tz->ops->activate_trip_type) {
+ result = -EPERM;
+ goto trip_activate_exit;
+ }
- if (!sscanf(attr->attr.name, "trip_point_%d_type", &trip))
- return -EINVAL;
-
- if (!strncmp(buf, "enabled", sizeof("enabled")))
- result = tz->ops->activate_trip_type(tz, trip,
- THERMAL_TRIP_ACTIVATION_ENABLED);
- else if (!strncmp(buf, "disabled", sizeof("disabled")))
- result = tz->ops->activate_trip_type(tz, trip,
- THERMAL_TRIP_ACTIVATION_DISABLED);
- else
+ if (!sscanf(attr->attr.name, "trip_point_%d_type", &trip)) {
result = -EINVAL;
+ goto trip_activate_exit;
+ }
+ if (!strcmp(buf, "enabled")) {
+ activate = true;
+ } else if (!strcmp(buf, "disabled")) {
+ activate = false;
+ } else {
+ result = -EINVAL;
+ goto trip_activate_exit;
+ }
+
+ get_trip_threshold(tz, trip, &threshold);
+ if (threshold)
+ result = sensor_activate_trip(tz->sensor.sensor_id,
+ threshold, activate);
+ else
+ result = tz->ops->activate_trip_type(tz, trip,
+ activate ? THERMAL_TRIP_ACTIVATION_ENABLED :
+ THERMAL_TRIP_ACTIVATION_DISABLED);
+
+trip_activate_exit:
if (result)
return result;
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index 078929b..ecfacc0 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -67,14 +67,65 @@
#include <mach/sps.h>
#include <mach/msm_serial_hs.h>
#include <mach/msm_bus.h>
-
+#include <mach/msm_ipc_logging.h>
#include "msm_serial_hs_hwreg.h"
#define UART_SPS_CONS_PERIPHERAL 0
#define UART_SPS_PROD_PERIPHERAL 1
-static int hs_serial_debug_mask = 1;
+static void *ipc_msm_hs_log_ctxt;
+#define IPC_MSM_HS_LOG_PAGES 5
+
+/* If the debug_mask gets set to FATAL_LEV,
+ * a fatal error has happened and further IPC logging
+ * is disabled so that this problem can be detected
+ */
+enum {
+ FATAL_LEV = 0U,
+ ERR_LEV = 1U,
+ WARN_LEV = 2U,
+ INFO_LEV = 3U,
+ DBG_LEV = 4U,
+};
+
+/* Default IPC log level INFO */
+static int hs_serial_debug_mask = INFO_LEV;
module_param_named(debug_mask, hs_serial_debug_mask,
int, S_IRUGO | S_IWUSR | S_IWGRP);
+
+#define MSM_HS_DBG(x...) do { \
+ if (hs_serial_debug_mask >= DBG_LEV) { \
+ pr_debug(x); \
+ if (ipc_msm_hs_log_ctxt) \
+ ipc_log_string(ipc_msm_hs_log_ctxt, x); \
+ } \
+} while (0)
+
+#define MSM_HS_INFO(x...) do { \
+ if (hs_serial_debug_mask >= INFO_LEV) {\
+ pr_info(x); \
+ if (ipc_msm_hs_log_ctxt) \
+ ipc_log_string(ipc_msm_hs_log_ctxt, x); \
+ } \
+} while (0)
+
+/* warnings and errors show up on console always */
+#define MSM_HS_WARN(x...) do { \
+ pr_warn(x); \
+ if (ipc_msm_hs_log_ctxt && hs_serial_debug_mask >= WARN_LEV) \
+ ipc_log_string(ipc_msm_hs_log_ctxt, x); \
+} while (0)
+
+/* ERROR condition in the driver sets the hs_serial_debug_mask
+ * to ERR_FATAL level, so that this message can be seen
+ * in IPC logging. Further errors continue to log on the console
+ */
+#define MSM_HS_ERR(x...) do { \
+ pr_err(x); \
+ if (ipc_msm_hs_log_ctxt && hs_serial_debug_mask >= ERR_LEV) { \
+ ipc_log_string(ipc_msm_hs_log_ctxt, x); \
+ hs_serial_debug_mask = FATAL_LEV; \
+ } \
+} while (0)
/*
* There are 3 different kind of UART Core available on MSM.
* High Speed UART (i.e. Legacy HSUART), GSBI based HSUART
@@ -316,19 +367,19 @@
switch (cmd) {
case MSM_ENABLE_UART_CLOCK: {
- pr_debug("%s():ENABLE UART CLOCK: cmd=%d\n", __func__, cmd);
+ MSM_HS_DBG("%s():ENABLE UART CLOCK: cmd=%d\n", __func__, cmd);
msm_hs_request_clock_on(&msm_uport->uport);
break;
}
case MSM_DISABLE_UART_CLOCK: {
- pr_debug("%s():DISABLE UART CLOCK: cmd=%d\n", __func__, cmd);
+ MSM_HS_DBG("%s():DISABLE UART CLOCK: cmd=%d\n", __func__, cmd);
msm_hs_request_clock_off(&msm_uport->uport);
break;
}
case MSM_GET_UART_CLOCK_STATUS: {
/* Return value 0 - UART CLOCK is OFF
* Return value 1 - UART CLOCK is ON */
- pr_debug("%s():GET UART CLOCK STATUS: cmd=%d\n", __func__, cmd);
+ MSM_HS_DBG("%s():GET UART CLOCK STATUS: cmd=%d\n", __func__, cmd);
spin_lock_irqsave(&msm_uport->uport.lock, flags);
clk_state = msm_uport->clk_state;
spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
@@ -338,7 +389,7 @@
break;
}
default: {
- pr_debug("%s():Unknown cmd specified: cmd=%d\n", __func__, cmd);
+ MSM_HS_DBG("%s():Unknown cmd specified: cmd=%d\n", __func__, cmd);
ret = -ENOIOCTLCMD;
break;
}
@@ -470,11 +521,11 @@
int ret;
if (is_blsp_uart(msm_uport) && msm_uport->bus_perf_client) {
- pr_debug("Bus voting:%d\n", vote);
+ MSM_HS_DBG("Bus voting:%d\n", vote);
ret = msm_bus_scale_client_update_request(
msm_uport->bus_perf_client, vote);
if (ret)
- pr_err("%s(): Failed for Bus voting: %d\n",
+ MSM_HS_ERR("%s(): Failed for Bus voting: %d\n",
__func__, vote);
}
}
@@ -500,6 +551,37 @@
writel_relaxed(value, uport->membase + offset);
}
+static void hex_dump_ipc(char *prefix, char *string, int size)
+{
+ char linebuf[512];
+
+ hex_dump_to_buffer(string, size, 16, 1, linebuf, sizeof(linebuf), 1);
+ MSM_HS_DBG("%s : %s", prefix, linebuf);
+}
+
+/*
+ * This API read and provides UART Core registers information.
+*/
+static void dump_uart_hs_registers(struct msm_hs_port *msm_uport)
+{
+ msm_hs_clock_vote(msm_uport);
+ MSM_HS_DBG("============= UART Registers ================\n");
+ MSM_HS_DBG("UART_DM_MR1:%x\n", msm_hs_read(&(msm_uport->uport),
+ UART_DM_MR1));
+ MSM_HS_DBG("UART_DM_MR2:%x\n", msm_hs_read(&(msm_uport->uport),
+ UART_DM_MR2));
+ MSM_HS_DBG("UART_DM_IPR:%x\n", msm_hs_read(&(msm_uport->uport),
+ UART_DM_IPR));
+ MSM_HS_DBG("UART_DM_RFWR:%x\n", msm_hs_read(&(msm_uport->uport),
+ UART_DM_RFWR));
+ MSM_HS_DBG("UART_DM_SR:%x\n", msm_hs_read(&(msm_uport->uport),
+ UART_DM_SR));
+ MSM_HS_DBG("UART_DM_IMR: %x\n", msm_hs_read(&(msm_uport->uport),
+ UART_DM_IMR));
+ MSM_HS_DBG("=============================================\n");
+ msm_hs_clock_unvote(msm_uport);
+}
+
static void msm_hs_release_port(struct uart_port *port)
{
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(port);
@@ -626,7 +708,7 @@
&loopback_enable_fops);
if (IS_ERR_OR_NULL(msm_uport->loopback_dir))
- pr_err("%s(): Cannot create loopback.%d debug entry",
+ MSM_HS_ERR("%s(): Cannot create loopback.%d debug entry",
__func__, id);
}
@@ -637,7 +719,7 @@
struct device *dev;
if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
- printk(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
+ MSM_HS_ERR(KERN_ERR "Invalid plaform device ID = %d\n", pdev->id);
return -EINVAL;
}
@@ -691,13 +773,13 @@
/* Set up the MREG/NREG/DREG/MNDREG */
ret = clk_set_rate(msm_uport->clk, uport->uartclk);
if (ret) {
- printk(KERN_WARNING "Error setting clock rate on UART\n");
+ MSM_HS_WARN("Error setting clock rate on UART\n");
return ret;
}
ret = msm_hs_clock_vote(msm_uport);
if (ret) {
- printk(KERN_ERR "Error could not turn on UART clk\n");
+ MSM_HS_ERR("Error could not turn on UART clk\n");
return ret;
}
@@ -728,14 +810,14 @@
/* Establish connection between peripheral and memory endpoint */
ret = sps_connect(sps_pipe_handle, sps_config);
if (ret) {
- pr_err("msm_serial_hs: sps_connect() failed for tx!!\n"
+ MSM_HS_ERR("msm_serial_hs: sps_connect() failed for tx!!\n"
"pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
return ret;
}
/* Register callback event for EOT (End of transfer) event. */
ret = sps_register_event(sps_pipe_handle, sps_event);
if (ret) {
- pr_err("msm_serial_hs: sps_connect() failed for tx!!\n"
+ MSM_HS_ERR("msm_serial_hs: sps_connect() failed for tx!!\n"
"pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
goto reg_event_err;
}
@@ -769,14 +851,14 @@
/* Establish connection between peripheral and memory endpoint */
ret = sps_connect(sps_pipe_handle, sps_config);
if (ret) {
- pr_err("msm_serial_hs: sps_connect() failed for rx!!\n"
+ MSM_HS_ERR("msm_serial_hs: sps_connect() failed for rx!!\n"
"pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
return ret;
}
/* Register callback event for DESC_DONE event. */
ret = sps_register_event(sps_pipe_handle, sps_event);
if (ret) {
- pr_err("msm_serial_hs: sps_connect() failed for rx!!\n"
+ MSM_HS_ERR("msm_serial_hs: sps_connect() failed for rx!!\n"
"pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
goto reg_event_err;
}
@@ -909,7 +991,7 @@
}
if (clk_set_rate(msm_uport->clk, uport->uartclk)) {
- printk(KERN_WARNING "Error setting clock rate on UART\n");
+ MSM_HS_WARN("Error setting clock rate on UART\n");
WARN_ON(1);
}
@@ -998,6 +1080,9 @@
mutex_lock(&msm_uport->clk_mutex);
msm_hs_write(uport, UART_DM_IMR, 0);
+ MSM_HS_DBG("Entering %s\n", __func__);
+ dump_uart_hs_registers(msm_uport);
+
/* Clear the Rx Ready Ctl bit - This ensures that
* flow control lines stop the other side from sending
* data while we change the parameters
@@ -1108,7 +1193,7 @@
RX_FLUSH_COMPLETE_TIMEOUT);
ret = sps_disconnect(sps_pipe_handle);
if (ret)
- pr_err("%s(): sps_disconnect failed\n",
+ MSM_HS_ERR("%s(): sps_disconnect failed\n",
__func__);
msm_hs_spsconnect_rx(uport);
msm_serial_hs_rx_tlet((unsigned long) &rx->tlet);
@@ -1116,13 +1201,13 @@
msm_uport->rx_discard_flush_issued = true;
/* do discard flush */
msm_dmov_flush(msm_uport->dma_rx_channel, 0);
- pr_debug("%s(): wainting for flush completion.\n",
+ MSM_HS_DBG("%s(): wainting for flush completion.\n",
__func__);
ret = wait_event_timeout(msm_uport->rx.wait,
msm_uport->rx_discard_flush_issued == false,
RX_FLUSH_COMPLETE_TIMEOUT);
if (!ret)
- pr_err("%s(): Discard flush pending.\n",
+ MSM_HS_ERR("%s(): Discard flush pending.\n",
__func__);
}
}
@@ -1144,6 +1229,8 @@
msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg);
mb();
mutex_unlock(&msm_uport->clk_mutex);
+ MSM_HS_DBG("Exit %s\n", __func__);
+ dump_uart_hs_registers(msm_uport);
}
/*
@@ -1157,7 +1244,7 @@
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
msm_hs_clock_vote(msm_uport);
- data = msm_hs_read(uport, UARTDM_SR_ADDR);
+ data = msm_hs_read(uport, UART_DM_SR);
msm_hs_clock_unvote(msm_uport);
if (data & UARTDM_SR_TXEMT_BMSK)
@@ -1190,7 +1277,7 @@
ret = sps_disconnect(sps_pipe_handle);
if (ret)
- pr_err("%s(): sps_disconnect failed\n", __func__);
+ MSM_HS_ERR("%s(): sps_disconnect failed\n", __func__);
wake_lock_timeout(&msm_uport->rx.wake_lock, HZ / 2);
msm_uport->rx.flush = FLUSH_SHUTDOWN;
@@ -1268,7 +1355,8 @@
if (tx_count > left)
tx_count = left;
-
+ MSM_HS_DBG("%s(): [UART_TX]<%d>\n", __func__, tx_count);
+ hex_dump_ipc("HSUART write: ", &tx_buf->buf[tx_buf->tail], tx_count);
src_addr = tx->dma_base + tx_buf->tail;
/* Mask the src_addr to align on a cache
* and add those bytes to tx_count */
@@ -1316,7 +1404,10 @@
sizeof(u32), DMA_TO_DEVICE);
msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer);
+
}
+ MSM_HS_DBG("%s:Enqueue Tx Cmd\n", __func__);
+ dump_uart_hs_registers(msm_uport);
}
/* Start to receive the next chunk of data */
@@ -1331,7 +1422,7 @@
msm_uport->rx.buffer_pending = 0;
if (buffer_pending && hs_serial_debug_mask)
- printk(KERN_ERR "Error: rx started in buffer state = %x",
+ MSM_HS_ERR("Error: rx started in buffer state = %x",
buffer_pending);
msm_hs_write(uport, UART_DM_CR, RESET_STALE_INT);
@@ -1383,6 +1474,8 @@
msm_dmov_enqueue_cmd(msm_uport->dma_rx_channel,
&msm_uport->rx.xfer);
}
+ MSM_HS_DBG("%s:Enqueue Rx Cmd\n", __func__);
+ dump_uart_hs_registers(msm_uport);
}
static void flip_insert_work(struct work_struct *work)
@@ -1397,7 +1490,7 @@
spin_lock_irqsave(&msm_uport->uport.lock, flags);
if (msm_uport->rx.buffer_pending == NONE_PENDING) {
if (hs_serial_debug_mask)
- printk(KERN_ERR "Error: No buffer pending in %s",
+ MSM_HS_ERR("Error: No buffer pending in %s",
__func__);
return;
}
@@ -1429,11 +1522,7 @@
else
if ((msm_uport->clk_state == MSM_HS_CLK_ON) &&
(msm_uport->rx.flush <= FLUSH_IGNORE)) {
- if (hs_serial_debug_mask)
- printk(KERN_WARNING
- "msm_serial_hs: "
- "Pending buffers cleared. "
- "Restarting\n");
+ MSM_HS_WARN("Pending buffers cleared,restarting\n");
msm_hs_start_rx_locked(&msm_uport->uport);
}
spin_unlock_irqrestore(&msm_uport->uport.lock, flags);
@@ -1470,6 +1559,9 @@
if (!is_blsp_uart(msm_uport))
msm_hs_write(uport, UART_DM_CR, STALE_EVENT_DISABLE);
+ MSM_HS_DBG("In %s\n", __func__);
+ dump_uart_hs_registers(msm_uport);
+
/* overflow is not connect to data in a FIFO */
if (unlikely((status & UARTDM_SR_OVERRUN_BMSK) &&
(uport->read_status_mask & CREAD))) {
@@ -1486,7 +1578,7 @@
if (unlikely(status & UARTDM_SR_PAR_FRAME_BMSK)) {
/* Can not tell difference between parity & frame error */
if (hs_serial_debug_mask)
- printk(KERN_WARNING "msm_serial_hs: parity error\n");
+ MSM_HS_WARN("msm_serial_hs: parity error\n");
uport->icount.parity++;
error_f = 1;
if (!(uport->ignore_status_mask & IGNPAR)) {
@@ -1498,7 +1590,7 @@
if (unlikely(status & UARTDM_SR_RX_BREAK_BMSK)) {
if (hs_serial_debug_mask)
- printk(KERN_WARNING "msm_serial_hs: Rx break\n");
+ MSM_HS_WARN("msm_serial_hs: Rx break\n");
uport->icount.brk++;
error_f = 1;
if (!(uport->ignore_status_mask & IGNBRK)) {
@@ -1533,15 +1625,20 @@
rmb();
}
+ MSM_HS_DBG("%s():[UART_RX]<%d>\n", __func__, rx_count);
+ hex_dump_ipc("HSUART Read: ", msm_uport->rx.buffer, rx_count);
if (0 != (uport->read_status_mask & CREAD)) {
retval = tty_insert_flip_string(tty, msm_uport->rx.buffer,
rx_count);
if (retval != rx_count) {
+ MSM_HS_DBG("%s(): retval %d rx_count %d", __func__,
+ retval, rx_count);
msm_uport->rx.buffer_pending |= CHARS_NORMAL |
retval << 5 | (rx_count - retval) << 16;
}
}
+ MSM_HS_DBG("%s() read rx buffer complete", __func__);
/* order the read of rx.buffer and the start of next rx xfer */
wmb();
@@ -1561,11 +1658,7 @@
}
out:
if (msm_uport->rx.buffer_pending) {
- if (hs_serial_debug_mask)
- printk(KERN_WARNING
- "msm_serial_hs: "
- "tty buffer exhausted. "
- "Stalling\n");
+ MSM_HS_WARN("tty buffer exhausted.Stalling\n");
schedule_delayed_work(&msm_uport->rx.flip_insert_work
, msecs_to_jiffies(RETRY_TIMEOUT));
}
@@ -1606,7 +1699,7 @@
((struct sps_event_notify *)notify)->user;
msm_uport->notify = *notify;
- pr_debug("%s: sps ev_id=%d, addr=0x%x, size=0x%x, flags=0x%x\n",
+ MSM_HS_DBG("%s: sps ev_id=%d, addr=0x%x, size=0x%x, flags=0x%x\n",
__func__, notify->event_id,
notify->data.transfer.iovec.addr,
notify->data.transfer.iovec.size,
@@ -1659,6 +1752,8 @@
mb();
spin_unlock_irqrestore(&(msm_uport->uport.lock), flags);
+ MSM_HS_DBG("In %s()\n", __func__);
+ dump_uart_hs_registers(msm_uport);
}
/**
@@ -1681,7 +1776,7 @@
uport = &(msm_uport->uport);
msm_uport->notify = *notify;
- pr_debug("%s: sps ev_id=%d, addr=0x%x, size=0x%x, flags=0x%x\n",
+ MSM_HS_DBG("%s: sps ev_id=%d, addr=0x%x, size=0x%x, flags=0x%x\n",
__func__, notify->event_id,
notify->data.transfer.iovec.addr,
notify->data.transfer.iovec.size,
@@ -1713,7 +1808,7 @@
msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer);
uport = &(msm_uport->uport);
- pr_debug("%s(): called result:%x\n", __func__, result);
+ MSM_HS_DBG("%s(): called result:%x\n", __func__, result);
if (!(result & DMOV_RSLT_ERROR)) {
if (result & DMOV_RSLT_FLUSH) {
if (msm_uport->rx_discard_flush_issued) {
@@ -1935,13 +2030,13 @@
spin_unlock_irqrestore(&uport->lock, flags);
if (msm_uport->rx_discard_flush_issued) {
- pr_debug("%s(): wainting for flush completion.\n",
+ MSM_HS_DBG("%s(): wainting for flush completion.\n",
__func__);
ret = wait_event_timeout(msm_uport->rx.wait,
msm_uport->rx_discard_flush_issued == false,
RX_FLUSH_COMPLETE_TIMEOUT);
if (!ret)
- pr_err("%s(): Flush complete pending.\n",
+ MSM_HS_ERR("%s(): Flush complete pending.\n",
__func__);
}
@@ -2005,10 +2100,13 @@
spin_lock_irqsave(&uport->lock, flags);
isr_status = msm_hs_read(uport, UART_DM_MISR);
+ MSM_HS_DBG("%s:UART_DM_MISR %lx", __func__, isr_status);
+ dump_uart_hs_registers(msm_uport);
/* Uart RX starting */
if (isr_status & UARTDM_ISR_RXLEV_BMSK) {
wake_lock(&rx->wake_lock); /* hold wakelock while rx dma */
+ MSM_HS_DBG("%s:UARTDM_ISR_RXLEV_BMSK\n", __func__);
msm_uport->imr_reg &= ~UARTDM_ISR_RXLEV_BMSK;
msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg);
/* Complete device write for IMR. Hence mb() requires. */
@@ -2023,6 +2121,7 @@
* mb() requires here.
*/
mb();
+ MSM_HS_DBG("%s:Stal Interrupt\n", __func__);
if (msm_uport->clk_req_off_state ==
CLK_REQ_OFF_RXSTALE_ISSUED)
@@ -2036,6 +2135,7 @@
}
/* tx ready interrupt */
if (isr_status & UARTDM_ISR_TX_READY_BMSK) {
+ MSM_HS_DBG("%s: ISR_TX_READY Interrupt\n", __func__);
/* Clear TX Ready */
msm_hs_write(uport, UART_DM_CR, CLEAR_TX_READY);
@@ -2114,7 +2214,7 @@
msm_uport->clk_state = MSM_HS_CLK_REQUEST_OFF;
msm_uport->clk_req_off_state = CLK_REQ_OFF_START;
msm_uport->imr_reg |= UARTDM_ISR_TXLEV_BMSK;
- msm_hs_write(uport, UARTDM_IMR, msm_uport->imr_reg);
+ msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg);
/*
* Complete device write before retuning back.
* Hence mb() requires here.
@@ -2252,7 +2352,7 @@
if (gpio_is_valid(pdata->uart_rfr_gpio))
gpio_free(pdata->uart_rfr_gpio);
} else {
- pr_err("Error:Pdata is NULL.\n");
+ MSM_HS_ERR("Error:Pdata is NULL.\n");
}
}
@@ -2272,7 +2372,7 @@
ret = gpio_request(pdata->uart_tx_gpio,
"UART_TX_GPIO");
if (unlikely(ret)) {
- pr_err("gpio request failed for:%d\n",
+ MSM_HS_ERR("gpio request failed for:%d\n",
pdata->uart_tx_gpio);
goto exit_uart_config;
}
@@ -2282,7 +2382,7 @@
ret = gpio_request(pdata->uart_rx_gpio,
"UART_RX_GPIO");
if (unlikely(ret)) {
- pr_err("gpio request failed for:%d\n",
+ MSM_HS_ERR("gpio request failed for:%d\n",
pdata->uart_rx_gpio);
goto uart_tx_unconfig;
}
@@ -2292,7 +2392,7 @@
ret = gpio_request(pdata->uart_cts_gpio,
"UART_CTS_GPIO");
if (unlikely(ret)) {
- pr_err("gpio request failed for:%d\n",
+ MSM_HS_ERR("gpio request failed for:%d\n",
pdata->uart_cts_gpio);
goto uart_rx_unconfig;
}
@@ -2302,13 +2402,13 @@
ret = gpio_request(pdata->uart_rfr_gpio,
"UART_RFR_GPIO");
if (unlikely(ret)) {
- pr_err("gpio request failed for:%d\n",
+ MSM_HS_ERR("gpio request failed for:%d\n",
pdata->uart_rfr_gpio);
goto uart_cts_unconfig;
}
}
} else {
- pr_err("Pdata is NULL.\n");
+ MSM_HS_ERR("Pdata is NULL.\n");
ret = -EINVAL;
}
return ret;
@@ -2354,7 +2454,7 @@
/* turn on uart clk */
ret = msm_hs_init_clk(uport);
if (unlikely(ret)) {
- pr_err("Turning ON uartclk error\n");
+ MSM_HS_ERR("Turning ON uartclk error\n");
wake_unlock(&msm_uport->dma_wake_lock);
return ret;
}
@@ -2362,7 +2462,7 @@
if (is_blsp_uart(msm_uport)) {
ret = msm_hs_config_uart_gpios(uport);
if (ret) {
- pr_err("Uart GPIO request failed\n");
+ MSM_HS_ERR("Uart GPIO request failed\n");
goto deinit_uart_clk;
}
} else {
@@ -2376,14 +2476,14 @@
/* SPS connect for TX */
ret = msm_hs_spsconnect_tx(uport);
if (ret) {
- pr_err("msm_serial_hs: SPS connect failed for TX");
+ MSM_HS_ERR("msm_serial_hs: SPS connect failed for TX");
goto unconfig_uart_gpios;
}
/* SPS connect for RX */
ret = msm_hs_spsconnect_rx(uport);
if (ret) {
- pr_err("msm_serial_hs: SPS connect failed for RX");
+ MSM_HS_ERR("msm_serial_hs: SPS connect failed for RX");
goto sps_disconnect_tx;
}
}
@@ -2461,7 +2561,7 @@
if (use_low_power_wakeup(msm_uport)) {
ret = irq_set_irq_wake(msm_uport->wakeup.irq, 1);
if (unlikely(ret)) {
- pr_err("%s():Err setting wakeup irq\n", __func__);
+ MSM_HS_ERR("%s():Err setting wakeup irq\n", __func__);
goto sps_disconnect_rx;
}
}
@@ -2469,7 +2569,7 @@
ret = request_irq(uport->irq, msm_hs_isr, IRQF_TRIGGER_HIGH,
"msm_hs_uart", msm_uport);
if (unlikely(ret)) {
- pr_err("%s():Error getting uart irq\n", __func__);
+ MSM_HS_ERR("%s():Error getting uart irq\n", __func__);
goto free_wake_irq;
}
if (use_low_power_wakeup(msm_uport)) {
@@ -2480,7 +2580,7 @@
"msm_hs_wakeup", msm_uport);
if (unlikely(ret)) {
- pr_err("%s():Err getting uart wakeup_irq\n", __func__);
+ MSM_HS_ERR("%s():Err getting uart wakeup_irq\n", __func__);
goto free_uart_irq;
}
disable_irq(msm_uport->wakeup.irq);
@@ -2543,14 +2643,14 @@
rx->pool = dma_pool_create("rx_buffer_pool", uport->dev,
UARTDM_RX_BUF_SIZE, 16, 0);
if (!rx->pool) {
- pr_err("%s(): cannot allocate rx_buffer_pool", __func__);
+ MSM_HS_ERR("%s(): cannot allocate rx_buffer_pool", __func__);
ret = -ENOMEM;
goto exit_tasket_init;
}
rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer);
if (!rx->buffer) {
- pr_err("%s(): cannot allocate rx->buffer", __func__);
+ MSM_HS_ERR("%s(): cannot allocate rx->buffer", __func__);
ret = -ENOMEM;
goto free_pool;
}
@@ -2589,14 +2689,15 @@
/* Allocate the command pointer. Needs to be 64 bit aligned */
rx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
if (!rx->command_ptr) {
- pr_err("%s(): cannot allocate rx->command_ptr", __func__);
+ MSM_HS_ERR("%s(): cannot allocate rx->command_ptr", __func__);
ret = -ENOMEM;
goto free_tx_command_ptr_ptr;
}
rx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA);
if (!rx->command_ptr_ptr) {
- pr_err("%s(): cannot allocate rx->command_ptr_ptr", __func__);
+ MSM_HS_ERR("%s(): cannot allocate rx->command_ptr_ptr",
+ __func__);
ret = -ENOMEM;
goto free_rx_command_ptr;
}
@@ -2664,7 +2765,7 @@
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata) {
- pr_err("unable to allocate memory for platform data\n");
+ MSM_HS_ERR("unable to allocate memory for platform data\n");
return ERR_PTR(-ENOMEM);
}
@@ -2672,25 +2773,25 @@
pdata->uart_tx_gpio = of_get_named_gpio(node,
"qcom,tx-gpio", 0);
if (pdata->uart_tx_gpio < 0)
- pr_debug("uart_tx_gpio is not available\n");
+ MSM_HS_DBG("uart_tx_gpio is not available\n");
/* UART RX GPIO */
pdata->uart_rx_gpio = of_get_named_gpio(node,
"qcom,rx-gpio", 0);
if (pdata->uart_rx_gpio < 0)
- pr_debug("uart_rx_gpio is not available\n");
+ MSM_HS_DBG("uart_rx_gpio is not available\n");
/* UART CTS GPIO */
pdata->uart_cts_gpio = of_get_named_gpio(node,
"qcom,cts-gpio", 0);
if (pdata->uart_cts_gpio < 0)
- pr_debug("uart_cts_gpio is not available\n");
+ MSM_HS_DBG("uart_cts_gpio is not available\n");
/* UART RFR GPIO */
pdata->uart_rfr_gpio = of_get_named_gpio(node,
"qcom,rfr-gpio", 0);
if (pdata->uart_rfr_gpio < 0)
- pr_debug("uart_rfr_gpio is not available\n");
+ MSM_HS_DBG("uart_rfr_gpio is not available\n");
pdata->inject_rx_on_wakeup = of_property_read_bool(node,
"qcom,inject-rx-on-wakeup");
@@ -2699,7 +2800,7 @@
ret = of_property_read_u32(node, "qcom,rx-char-to-inject",
&rx_to_inject);
if (ret < 0) {
- pr_err("Error: Rx_char_to_inject not specified.\n");
+ MSM_HS_ERR("Error: Rx_char_to_inject not specified.\n");
return ERR_PTR(ret);
}
pdata->rx_to_inject = (char)rx_to_inject;
@@ -2708,30 +2809,30 @@
ret = of_property_read_u32(node, "qcom,bam-tx-ep-pipe-index",
&pdata->bam_tx_ep_pipe_index);
if (ret < 0) {
- pr_err("Error: Getting UART BAM TX EP Pipe Index.\n");
+ MSM_HS_ERR("Error: Getting UART BAM TX EP Pipe Index.\n");
return ERR_PTR(ret);
}
if (!(pdata->bam_tx_ep_pipe_index >= BAM_PIPE_MIN &&
pdata->bam_tx_ep_pipe_index <= BAM_PIPE_MAX)) {
- pr_err("Error: Invalid UART BAM TX EP Pipe Index.\n");
+ MSM_HS_ERR("Error: Invalid UART BAM TX EP Pipe Index.\n");
return ERR_PTR(-EINVAL);
}
ret = of_property_read_u32(node, "qcom,bam-rx-ep-pipe-index",
&pdata->bam_rx_ep_pipe_index);
if (ret < 0) {
- pr_err("Error: Getting UART BAM RX EP Pipe Index.\n");
+ MSM_HS_ERR("Error: Getting UART BAM RX EP Pipe Index.\n");
return ERR_PTR(ret);
}
if (!(pdata->bam_rx_ep_pipe_index >= BAM_PIPE_MIN &&
pdata->bam_rx_ep_pipe_index <= BAM_PIPE_MAX)) {
- pr_err("Error: Invalid UART BAM RX EP Pipe Index.\n");
+ MSM_HS_ERR("Error: Invalid UART BAM RX EP Pipe Index.\n");
return ERR_PTR(-EINVAL);
}
- pr_debug("tx_ep_pipe_index:%d rx_ep_pipe_index:%d\n"
+ MSM_HS_DBG("tx_ep_pipe_index:%d rx_ep_pipe_index:%d\n"
"tx_gpio:%d rx_gpio:%d rfr_gpio:%d cts_gpio:%d",
pdata->bam_tx_ep_pipe_index, pdata->bam_rx_ep_pipe_index,
pdata->uart_tx_gpio, pdata->uart_rx_gpio, pdata->uart_cts_gpio,
@@ -2787,7 +2888,7 @@
/* Allocate endpoint context */
sps_pipe_handle = sps_alloc_endpoint();
if (!sps_pipe_handle) {
- pr_err("msm_serial_hs: sps_alloc_endpoint() failed!!\n"
+ MSM_HS_ERR("msm_serial_hs: sps_alloc_endpoint() failed!!\n"
"is_producer=%d", is_producer);
rc = -ENOMEM;
goto out;
@@ -2796,7 +2897,7 @@
/* Get default connection configuration for an endpoint */
rc = sps_get_config(sps_pipe_handle, sps_config);
if (rc) {
- pr_err("msm_serial_hs: sps_get_config() failed!!\n"
+ MSM_HS_ERR("msm_serial_hs: sps_get_config() failed!!\n"
"pipe_handle=0x%x rc=%d", (u32)sps_pipe_handle, rc);
goto get_config_err;
}
@@ -2832,7 +2933,7 @@
GFP_KERNEL);
if (!sps_config->desc.base) {
rc = -ENOMEM;
- pr_err("msm_serial_hs: dma_alloc_coherent() failed!!\n");
+ MSM_HS_ERR("msm_serial_hs: dma_alloc_coherent() failed!!\n");
goto get_config_err;
}
memset(sps_config->desc.base, 0x00, sps_config->desc.size);
@@ -2851,7 +2952,7 @@
/* Now save the sps pipe handle */
ep->pipe_handle = sps_pipe_handle;
- pr_debug("msm_serial_hs: success !! %s: pipe_handle=0x%x\n"
+ MSM_HS_DBG("msm_serial_hs: success !! %s: pipe_handle=0x%x\n"
"desc_fifo.phys_base=0x%llx\n",
is_producer ? "READ" : "WRITE",
(u32) sps_pipe_handle, (u64) sps_config->desc.phys_base);
@@ -2895,18 +2996,18 @@
bam.irq = (u32)msm_uport->bam_irq;
bam.manage = SPS_BAM_MGR_DEVICE_REMOTE;
- pr_debug("msm_serial_hs: bam physical base=0x%x\n",
+ MSM_HS_DBG("msm_serial_hs: bam physical base=0x%x\n",
(u32)bam.phys_addr);
- pr_debug("msm_serial_hs: bam virtual base=0x%x\n",
+ MSM_HS_DBG("msm_serial_hs: bam virtual base=0x%x\n",
(u32)bam.virt_addr);
/* Register UART Peripheral BAM device to SPS driver */
rc = sps_register_bam_device(&bam, &bam_handle);
if (rc) {
- pr_err("msm_serial_hs: BAM device register failed\n");
+ MSM_HS_ERR("msm_serial_hs: BAM device register failed\n");
return rc;
}
- pr_info("msm_serial_hs: BAM device registered. bam_handle=0x%x",
+ MSM_HS_INFO("msm_serial_hs: BAM device registered. bam_handle=0x%x",
msm_uport->bam_handle);
}
msm_uport->bam_handle = bam_handle;
@@ -2914,14 +3015,14 @@
rc = msm_hs_sps_init_ep_conn(msm_uport, &msm_uport->rx.prod,
UART_SPS_PROD_PERIPHERAL);
if (rc) {
- pr_err("%s: Failed to Init Producer BAM-pipe", __func__);
+ MSM_HS_ERR("%s: Failed to Init Producer BAM-pipe", __func__);
goto deregister_bam;
}
rc = msm_hs_sps_init_ep_conn(msm_uport, &msm_uport->tx.cons,
UART_SPS_CONS_PERIPHERAL);
if (rc) {
- pr_err("%s: Failed to Init Consumer BAM-pipe", __func__);
+ MSM_HS_ERR("%s: Failed to Init Consumer BAM-pipe", __func__);
goto deinit_ep_conn_prod;
}
return 0;
@@ -2973,7 +3074,7 @@
if (deviceid[alias_num] == 0) {
pdev->id = alias_num;
} else {
- pr_err("alias_num=%d already used\n",
+ MSM_HS_ERR("alias_num=%d already used\n",
alias_num);
return -EINVAL;
}
@@ -2986,7 +3087,7 @@
}
if (pdev->id < 0 || pdev->id >= UARTDM_NR) {
- pr_err("Invalid plaform device ID = %d\n", pdev->id);
+ MSM_HS_ERR("Invalid plaform device ID = %d\n", pdev->id);
return -EINVAL;
}
@@ -3014,39 +3115,39 @@
wakeup_irqres = platform_get_irq_byname(pdev, "wakeup_irq");
if (!core_resource) {
- pr_err("Invalid core HSUART Resources.\n");
+ MSM_HS_ERR("Invalid core HSUART Resources.\n");
return -ENXIO;
}
if (!bam_resource) {
- pr_err("Invalid BAM HSUART Resources.\n");
+ MSM_HS_ERR("Invalid BAM HSUART Resources.\n");
return -ENXIO;
}
if (!core_irqres) {
- pr_err("Invalid core irqres Resources.\n");
+ MSM_HS_ERR("Invalid core irqres Resources.\n");
return -ENXIO;
}
if (!bam_irqres) {
- pr_err("Invalid bam irqres Resources.\n");
+ MSM_HS_ERR("Invalid bam irqres Resources.\n");
return -ENXIO;
}
if (!wakeup_irqres)
- pr_debug("Wakeup irq not specified.\n");
+ MSM_HS_DBG("Wakeup irq not specified.\n");
uport->mapbase = core_resource->start;
uport->membase = ioremap(uport->mapbase,
resource_size(core_resource));
if (unlikely(!uport->membase)) {
- pr_err("UART Resource ioremap Failed.\n");
+ MSM_HS_ERR("UART Resource ioremap Failed.\n");
return -ENOMEM;
}
msm_uport->bam_mem = bam_resource->start;
msm_uport->bam_base = ioremap(msm_uport->bam_mem,
resource_size(bam_resource));
if (unlikely(!msm_uport->bam_base)) {
- pr_err("UART BAM Resource ioremap Failed.\n");
+ MSM_HS_ERR("UART BAM Resource ioremap Failed.\n");
iounmap(uport->membase);
return -ENOMEM;
}
@@ -3057,13 +3158,13 @@
msm_uport->bus_scale_table = msm_bus_cl_get_pdata(pdev);
if (!msm_uport->bus_scale_table) {
- pr_err("BLSP UART: Bus scaling is disabled.\n");
+ MSM_HS_ERR("BLSP UART: Bus scaling is disabled.\n");
} else {
msm_uport->bus_perf_client =
msm_bus_scale_register_client
(msm_uport->bus_scale_table);
if (IS_ERR(&msm_uport->bus_perf_client)) {
- pr_err("%s(): Bus client register failed.\n",
+ MSM_HS_ERR("%s(): Bus client register failed.\n",
__func__);
ret = -EINVAL;
goto unmap_memory;
@@ -3082,7 +3183,7 @@
uport->irq = platform_get_irq(pdev, 0);
if (unlikely((int)uport->irq < 0)) {
- pr_err("UART IRQ Failed.\n");
+ MSM_HS_ERR("UART IRQ Failed.\n");
iounmap(uport->membase);
return -ENXIO;
}
@@ -3155,14 +3256,14 @@
ret = clk_set_rate(msm_uport->clk, uport->uartclk);
if (ret) {
- printk(KERN_WARNING "Error setting clock rate on UART\n");
+ MSM_HS_WARN("Error setting clock rate on UART\n");
goto put_clk;
}
msm_uport->hsuart_wq = alloc_workqueue("k_hsuart",
WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
if (!msm_uport->hsuart_wq) {
- pr_err("%s(): Unable to create workqueue hsuart_wq\n",
+ MSM_HS_ERR("%s(): Unable to create workqueue hsuart_wq\n",
__func__);
ret = -ENOMEM;
goto put_clk;
@@ -3181,7 +3282,7 @@
if (is_blsp_uart(msm_uport)) {
ret = msm_hs_sps_init(msm_uport);
if (unlikely(ret)) {
- pr_err("SPS Initialization failed ! err=%d", ret);
+ MSM_HS_ERR("SPS Initialization failed ! err=%d", ret);
goto destroy_mutex;
}
}
@@ -3254,28 +3355,33 @@
int ret;
int i;
+ ipc_msm_hs_log_ctxt = ipc_log_context_create(IPC_MSM_HS_LOG_PAGES,
+ "msm_serial_hs");
+ if (!ipc_msm_hs_log_ctxt)
+ MSM_HS_WARN("%s: error creating logging context", __func__);
+
/* Init all UARTS as non-configured */
for (i = 0; i < UARTDM_NR; i++)
q_uart_port[i].uport.type = PORT_UNKNOWN;
ret = uart_register_driver(&msm_hs_driver);
if (unlikely(ret)) {
- printk(KERN_ERR "%s failed to load\n", __FUNCTION__);
+ MSM_HS_WARN("%s failed to load\n", __func__);
return ret;
}
debug_base = debugfs_create_dir("msm_serial_hs", NULL);
if (IS_ERR_OR_NULL(debug_base))
- pr_info("msm_serial_hs: Cannot create debugfs dir\n");
+ MSM_HS_INFO("msm_serial_hs: Cannot create debugfs dir\n");
ret = platform_driver_register(&msm_serial_hs_platform_driver);
if (ret) {
- printk(KERN_ERR "%s failed to load\n", __FUNCTION__);
+ MSM_HS_ERR("%s failed to load\n", __FUNCTION__);
debugfs_remove_recursive(debug_base);
uart_unregister_driver(&msm_hs_driver);
return ret;
}
- printk(KERN_INFO "msm_serial_hs module loaded\n");
+ MSM_HS_INFO("msm_serial_hs module loaded\n");
return ret;
}
@@ -3318,12 +3424,12 @@
ret = wait_event_timeout(msm_uport->tx.wait,
msm_uport->tx.flush == FLUSH_SHUTDOWN, 100);
if (!ret)
- pr_err("%s():HSUART TX Stalls.\n", __func__);
+ MSM_HS_ERR("%s():HSUART TX Stalls.\n", __func__);
} else {
/* BAM Disconnect for TX */
ret = sps_disconnect(sps_pipe_handle);
if (ret)
- pr_err("%s(): sps_disconnect failed\n",
+ MSM_HS_ERR("%s(): sps_disconnect failed\n",
__func__);
}
}
@@ -3378,7 +3484,7 @@
static void __exit msm_serial_hs_exit(void)
{
- printk(KERN_INFO "msm_serial_hs module removed\n");
+ MSM_HS_INFO("msm_serial_hs module removed\n");
debugfs_remove_recursive(debug_base);
platform_driver_unregister(&msm_serial_hs_platform_driver);
uart_unregister_driver(&msm_hs_driver);
diff --git a/drivers/tty/serial/msm_serial_hs_lite.c b/drivers/tty/serial/msm_serial_hs_lite.c
index a4a4f28..0ff8ad7 100644
--- a/drivers/tty/serial/msm_serial_hs_lite.c
+++ b/drivers/tty/serial/msm_serial_hs_lite.c
@@ -523,6 +523,10 @@
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
+ if (port->suspended) {
+ pr_err("%s: System is in Suspend state\n", __func__);
+ return;
+ }
msm_hsl_port->imr |= UARTDM_ISR_TXLEV_BMSK;
msm_hsl_write(port, msm_hsl_port->imr,
regmap[msm_hsl_port->ver_id][UARTDM_IMR]);
diff --git a/drivers/usb/gadget/android.c b/drivers/usb/gadget/android.c
index c65ed25..877b944 100644
--- a/drivers/usb/gadget/android.c
+++ b/drivers/usb/gadget/android.c
@@ -1770,7 +1770,7 @@
struct fsg_common *common;
int err;
int i;
- const char *name[2];
+ const char *name[3];
config = kzalloc(sizeof(struct mass_storage_function_config),
GFP_KERNEL);
diff --git a/drivers/usb/misc/diag_bridge.c b/drivers/usb/misc/diag_bridge.c
index 22e2a25..ccd48ca 100644
--- a/drivers/usb/misc/diag_bridge.c
+++ b/drivers/usb/misc/diag_bridge.c
@@ -464,12 +464,7 @@
pr_err("unable to allocate dev");
return -ENOMEM;
}
- dev->pdev = platform_device_alloc("diag_bridge", devid);
- if (!dev->pdev) {
- pr_err("unable to allocate platform device");
- kfree(dev);
- return -ENOMEM;
- }
+
__dev[devid] = dev;
dev->id = devid;
@@ -498,7 +493,13 @@
usb_set_intfdata(ifc, dev);
diag_bridge_debugfs_init();
- platform_device_add(dev->pdev);
+ dev->pdev = platform_device_register_simple("diag_bridge", devid,
+ NULL, 0);
+ if (IS_ERR(dev->pdev)) {
+ pr_err("unable to allocate platform device");
+ ret = PTR_ERR(dev->pdev);
+ goto error;
+ }
dev_dbg(&dev->ifc->dev, "%s: complete\n", __func__);
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 45fbfa8..8287ad7 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -629,6 +629,10 @@
pm8xxx_usb_id_pullup(1);
}
+ if (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)
+ writel_relaxed(readl_relaxed(USB_OTGSC) & ~(OTGSC_IDPU),
+ USB_OTGSC);
+
return 0;
}
@@ -889,6 +893,7 @@
u32 phy_ctrl_val = 0, cmd_val;
unsigned ret;
u32 portsc, config2;
+ u32 func_ctrl;
if (atomic_read(&motg->in_lpm))
return 0;
@@ -956,6 +961,15 @@
ulpi_write(phy, 0x08, 0x09);
}
+ if (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED) {
+ /* put the controller in non-driving mode */
+ func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
+ func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
+ func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
+ ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
+ ulpi_write(phy, ULPI_IFC_CTRL_AUTORESUME,
+ ULPI_CLR(ULPI_IFC_CTRL));
+ }
/* Set the PHCD bit, only if it is not set by the controller.
* PHY may take some time or even fail to enter into low power
@@ -1021,8 +1035,13 @@
}
if (host_bus_suspend)
phy_ctrl_val |= PHY_CLAMP_DPDMSE_EN;
- writel_relaxed(phy_ctrl_val & ~PHY_RETEN, USB_PHY_CTRL);
- motg->lpm_flags |= PHY_RETENTIONED;
+
+ if (!(motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)) {
+ writel_relaxed(phy_ctrl_val & ~PHY_RETEN, USB_PHY_CTRL);
+ motg->lpm_flags |= PHY_RETENTIONED;
+ } else {
+ writel_relaxed(phy_ctrl_val, USB_PHY_CTRL);
+ }
}
/* Ensure that above operation is completed before turning off clocks */
@@ -1063,7 +1082,8 @@
motg->lpm_flags |= PHY_REGULATORS_LPM;
}
- if (motg->lpm_flags & PHY_RETENTIONED) {
+ if (motg->lpm_flags & PHY_RETENTIONED ||
+ (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)) {
msm_hsusb_config_vddcx(0);
msm_hsusb_mhl_switch_enable(motg, 0);
}
@@ -1116,6 +1136,7 @@
unsigned temp;
u32 phy_ctrl_val = 0;
unsigned ret;
+ u32 func_ctrl;
if (!atomic_read(&motg->in_lpm))
return 0;
@@ -1159,7 +1180,8 @@
motg->lpm_flags &= ~PHY_REGULATORS_LPM;
}
- if (motg->lpm_flags & PHY_RETENTIONED) {
+ if (motg->lpm_flags & PHY_RETENTIONED ||
+ (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED)) {
msm_hsusb_mhl_switch_enable(motg, 1);
msm_hsusb_config_vddcx(1);
phy_ctrl_val = readl_relaxed(USB_PHY_CTRL);
@@ -1205,6 +1227,14 @@
}
skip_phy_resume:
+ if (motg->caps & ALLOW_VDD_MIN_WITH_RETENTION_DISABLED) {
+ /* put the controller in normal mode */
+ func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
+ func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
+ func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
+ ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
+ }
+
if (device_may_wakeup(phy->dev)) {
if (motg->async_irq)
disable_irq_wake(motg->async_irq);
@@ -4183,6 +4213,8 @@
"qcom,hsusb-l1-supported");
pdata->enable_ahb2ahb_bypass = of_property_read_bool(node,
"qcom,ahb-async-bridge-bypass");
+ pdata->disable_retention_with_vdd_min = of_property_read_bool(node,
+ "qcom,disable-retention-with-vdd-min");
return pdata;
}
@@ -4568,6 +4600,9 @@
if (motg->pdata->enable_lpm_on_dev_suspend)
motg->caps |= ALLOW_LPM_ON_DEV_SUSPEND;
+ if (motg->pdata->disable_retention_with_vdd_min)
+ motg->caps |= ALLOW_VDD_MIN_WITH_RETENTION_DISABLED;
+
wake_lock(&motg->wlock);
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
diff --git a/drivers/video/fbcmap.c b/drivers/video/fbcmap.c
index 31e93a5..f26570d 100644
--- a/drivers/video/fbcmap.c
+++ b/drivers/video/fbcmap.c
@@ -203,11 +203,13 @@
fromoff = to->start - from->start;
else
tooff = from->start - to->start;
+ if ((to->len <= tooff) || (from->len <= fromoff))
+ return -EINVAL;
+
size = to->len - tooff;
+
if (size > (int) (from->len - fromoff))
size = from->len - fromoff;
- if (size <= 0)
- return -EINVAL;
size *= sizeof(u16);
if (from->red && to->red)
diff --git a/drivers/video/msm/mdss/Kconfig b/drivers/video/msm/mdss/Kconfig
index b49e08e..01edf92 100644
--- a/drivers/video/msm/mdss/Kconfig
+++ b/drivers/video/msm/mdss/Kconfig
@@ -28,3 +28,10 @@
seconds) by sending Bus-Turn-Around (BTA) command. If DSI controller
fails to acknowledge the BTA command, it sends PANEL_ALIVE=0 status
to HAL layer to reset the controller.
+
+config FB_MSM_MDSS_MDP3
+ depends on FB_MSM_MDSS
+ bool "MDP3 display controller"
+ ---help---
+ The MDP3 provides support for an older version display controller
+ included in latest display sub-system, known as MDSS.
diff --git a/drivers/video/msm/mdss/Makefile b/drivers/video/msm/mdss/Makefile
index 8f5fa26..fd03b63 100644
--- a/drivers/video/msm/mdss/Makefile
+++ b/drivers/video/msm/mdss/Makefile
@@ -1,6 +1,6 @@
mdss-mdp3-objs = mdp3.o mdp3_dma.o mdp3_ctrl.o
mdss-mdp3-objs += mdp3_ppp.o mdp3_ppp_hwio.o mdp3_ppp_data.o
-obj-$(CONFIG_FB_MSM_MDSS) += mdss-mdp3.o
+obj-$(CONFIG_FB_MSM_MDSS_MDP3) += mdss-mdp3.o
mdss-mdp-objs := mdss_mdp.o mdss_mdp_ctl.o mdss_mdp_pipe.o mdss_mdp_util.o
mdss-mdp-objs += mdss_mdp_pp.o
@@ -17,9 +17,9 @@
endif
dsi-v2-objs = dsi_v2.o dsi_host_v2.o dsi_io_v2.o
-obj-$(CONFIG_FB_MSM_MDSS) += dsi-v2.o
+obj-$(CONFIG_FB_MSM_MDSS_MDP3) += dsi-v2.o
-mdss-dsi-objs := mdss_dsi.o mdss_dsi_host.o
+mdss-dsi-objs := mdss_dsi.o mdss_dsi_host.o mdss_dsi_cmd.o
mdss-dsi-objs += mdss_dsi_panel.o
mdss-dsi-objs += msm_mdss_io_8974.o
obj-$(CONFIG_FB_MSM_MDSS) += mdss-dsi.o
@@ -42,4 +42,8 @@
obj-$(CONFIG_FB_MSM_MDSS) += mdss_fb.o
+ifeq ($(CONFIG_FB_MSM_MDSS_MDP3),y)
+obj-$(CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS) += dsi_status_v2.o
+else
obj-$(CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS) += mdss_dsi_status.o
+endif
diff --git a/drivers/video/msm/mdss/dsi_host_v2.c b/drivers/video/msm/mdss/dsi_host_v2.c
index 7d57f64..4173e3f 100644
--- a/drivers/video/msm/mdss/dsi_host_v2.c
+++ b/drivers/video/msm/mdss/dsi_host_v2.c
@@ -31,21 +31,24 @@
#define DSI_POLL_TIMEOUT_US 16000
#define DSI_ESC_CLK_RATE 19200000
#define DSI_DMA_CMD_TIMEOUT_MS 200
+#define VSYNC_PERIOD 17
+#define DSI_MAX_PKT_SIZE 10
+#define DSI_SHORT_PKT_DATA_SIZE 2
+#define DSI_MAX_BYTES_TO_READ 16
struct dsi_host_v2_private {
- struct completion dma_comp;
- int irq_enabled;
- spinlock_t irq_lock;
-
int irq_no;
unsigned char *dsi_base;
size_t dsi_reg_size;
struct device dis_dev;
+ int clk_count;
+ int dsi_on;
void (*debug_enable_clk)(int on);
};
static struct dsi_host_v2_private *dsi_host_private;
+static int msm_dsi_clk_ctrl(struct mdss_panel_data *pdata, int enable);
int msm_dsi_init(void)
{
@@ -58,8 +61,6 @@
}
}
- init_completion(&dsi_host_private->dma_comp);
- spin_lock_init(&dsi_host_private->irq_lock);
return 0;
}
@@ -77,6 +78,9 @@
if (status) {
MIPI_OUTP(ctrl_base + DSI_ACK_ERR_STATUS, status);
+
+ /* Writing of an extra 0 needed to clear error bits */
+ MIPI_OUTP(ctrl_base + DSI_ACK_ERR_STATUS, 0);
pr_err("%s: status=%x\n", __func__, status);
}
}
@@ -137,61 +141,104 @@
msm_dsi_dln0_phy_err(ctrl_base);
}
-void msm_dsi_enable_irq(void)
+static void msm_dsi_set_irq_mask(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask)
+{
+ u32 intr_ctrl;
+ intr_ctrl = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL);
+ intr_ctrl |= mask;
+ MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, intr_ctrl);
+}
+
+static void msm_dsi_clear_irq_mask(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask)
+{
+ u32 intr_ctrl;
+ intr_ctrl = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL);
+ intr_ctrl &= ~mask;
+ MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, intr_ctrl);
+}
+
+static void msm_dsi_set_irq(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask)
{
unsigned long flags;
- spin_lock_irqsave(&dsi_host_private->irq_lock, flags);
- dsi_host_private->irq_enabled++;
- if (dsi_host_private->irq_enabled == 1)
+ spin_lock_irqsave(&ctrl->irq_lock, flags);
+ if (ctrl->dsi_irq_mask & mask) {
+ spin_unlock_irqrestore(&ctrl->irq_lock, flags);
+ return;
+ }
+ if (ctrl->dsi_irq_mask == 0) {
enable_irq(dsi_host_private->irq_no);
+ pr_debug("%s: IRQ Enable, mask=%x term=%x\n", __func__,
+ (int)ctrl->dsi_irq_mask, (int)mask);
+ }
- spin_unlock_irqrestore(&dsi_host_private->irq_lock, flags);
+ msm_dsi_set_irq_mask(ctrl, mask);
+ ctrl->dsi_irq_mask |= mask;
+ spin_unlock_irqrestore(&ctrl->irq_lock, flags);
}
-void msm_dsi_disable_irq(void)
+static void msm_dsi_clear_irq(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask)
{
unsigned long flags;
- spin_lock_irqsave(&dsi_host_private->irq_lock, flags);
- dsi_host_private->irq_enabled--;
- if (dsi_host_private->irq_enabled == 0)
+ spin_lock_irqsave(&ctrl->irq_lock, flags);
+ if (!(ctrl->dsi_irq_mask & mask)) {
+ spin_unlock_irqrestore(&ctrl->irq_lock, flags);
+ return;
+ }
+ ctrl->dsi_irq_mask &= ~mask;
+ if (ctrl->dsi_irq_mask == 0) {
disable_irq(dsi_host_private->irq_no);
-
- spin_unlock_irqrestore(&dsi_host_private->irq_lock, flags);
+ pr_debug("%s: IRQ Disable, mask=%x term=%x\n", __func__,
+ (int)ctrl->dsi_irq_mask, (int)mask);
+ }
+ msm_dsi_clear_irq_mask(ctrl, mask);
+ spin_unlock_irqrestore(&ctrl->irq_lock, flags);
}
-void msm_dsi_disable_irq_nosync(void)
-{
- spin_lock(&dsi_host_private->irq_lock);
- dsi_host_private->irq_enabled--;
- if (dsi_host_private->irq_enabled == 0)
- disable_irq_nosync(dsi_host_private->irq_no);
- spin_unlock(&dsi_host_private->irq_lock);
-}
-
-irqreturn_t msm_dsi_isr(int irq, void *ptr)
+irqreturn_t msm_dsi_isr_handler(int irq, void *ptr)
{
u32 isr;
+ struct mdss_dsi_ctrl_pdata *ctrl =
+ (struct mdss_dsi_ctrl_pdata *)ptr;
+
isr = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL);
MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, isr);
- if (isr & DSI_INTR_ERROR)
+ pr_debug("%s: isr=%x", __func__, isr);
+
+ if (isr & DSI_INTR_ERROR) {
+ pr_err("%s: isr=%x %x", __func__, isr, (int)DSI_INTR_ERROR);
msm_dsi_error(dsi_host_private->dsi_base);
+ }
+
+ spin_lock(&ctrl->mdp_lock);
+
+ if (isr & DSI_INTR_VIDEO_DONE)
+ complete(&ctrl->video_comp);
if (isr & DSI_INTR_CMD_DMA_DONE)
- complete(&dsi_host_private->dma_comp);
+ complete(&ctrl->dma_comp);
+
+ spin_unlock(&ctrl->mdp_lock);
+
+ if (isr & DSI_INTR_BTA_DONE)
+ complete(&ctrl->bta_comp);
+
+ if (isr & DSI_INTR_CMD_MDP_DONE)
+ complete(&ctrl->mdp_comp);
return IRQ_HANDLED;
}
-int msm_dsi_irq_init(struct device *dev, int irq_no)
+int msm_dsi_irq_init(struct device *dev, int irq_no,
+ struct mdss_dsi_ctrl_pdata *ctrl)
{
int ret;
- ret = devm_request_irq(dev, irq_no, msm_dsi_isr,
- IRQF_DISABLED, "DSI", NULL);
+ ret = devm_request_irq(dev, irq_no, msm_dsi_isr_handler,
+ IRQF_DISABLED, "DSI", ctrl);
if (ret) {
pr_err("msm_dsi_irq_init request_irq() failed!\n");
return ret;
@@ -201,9 +248,119 @@
return 0;
}
+static void msm_dsi_get_cmd_engine(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ unsigned char *ctrl_base = dsi_host_private->dsi_base;
+ u32 dsi_ctrl;
+
+ if (ctrl->panel_mode == DSI_VIDEO_MODE) {
+ dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL);
+ MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl | 0x04);
+ }
+}
+
+static void msm_dsi_release_cmd_engine(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ unsigned char *ctrl_base = dsi_host_private->dsi_base;
+ u32 dsi_ctrl;
+ if (ctrl->panel_mode == DSI_VIDEO_MODE) {
+ dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL);
+ dsi_ctrl &= ~0x04;
+ MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl);
+ }
+}
+
+static int msm_dsi_wait4mdp_done(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ int rc;
+ unsigned long flag;
+
+ spin_lock_irqsave(&ctrl->mdp_lock, flag);
+ INIT_COMPLETION(ctrl->mdp_comp);
+ msm_dsi_set_irq(ctrl, DSI_INTR_CMD_MDP_DONE_MASK);
+ spin_unlock_irqrestore(&ctrl->mdp_lock, flag);
+
+ rc = wait_for_completion_timeout(&ctrl->mdp_comp,
+ msecs_to_jiffies(VSYNC_PERIOD * 4));
+
+ if (rc == 0) {
+ pr_err("DSI wait 4 mdp done time out\n");
+ rc = -ETIME;
+ } else if (!IS_ERR_VALUE(rc)) {
+ rc = 0;
+ }
+
+ msm_dsi_clear_irq(ctrl, DSI_INTR_CMD_MDP_DONE_MASK);
+
+ return rc;
+}
+
+void msm_dsi_cmd_mdp_busy(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ int rc;
+ u32 dsi_status;
+ unsigned char *ctrl_base = dsi_host_private->dsi_base;
+
+ if (ctrl->panel_mode == DSI_VIDEO_MODE)
+ return;
+
+ dsi_status = MIPI_INP(ctrl_base + DSI_STATUS);
+ if (dsi_status & 0x04) {
+ pr_debug("dsi command engine is busy\n");
+ rc = msm_dsi_wait4mdp_done(ctrl);
+ if (rc)
+ pr_err("Timed out waiting for mdp done");
+ }
+}
+
+static int msm_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ int rc;
+ unsigned long flag;
+
+ spin_lock_irqsave(&ctrl->mdp_lock, flag);
+ INIT_COMPLETION(ctrl->video_comp);
+ msm_dsi_set_irq(ctrl, DSI_INTR_VIDEO_DONE_MASK);
+ spin_unlock_irqrestore(&ctrl->mdp_lock, flag);
+
+ rc = wait_for_completion_timeout(&ctrl->video_comp,
+ msecs_to_jiffies(VSYNC_PERIOD * 4));
+
+ if (rc == 0) {
+ pr_err("DSI wait 4 video done time out\n");
+ rc = -ETIME;
+ } else if (!IS_ERR_VALUE(rc)) {
+ rc = 0;
+ }
+
+ msm_dsi_clear_irq(ctrl, DSI_INTR_VIDEO_DONE_MASK);
+
+ return rc;
+}
+
+static int msm_dsi_wait4video_eng_busy(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ int rc = 0;
+ u32 dsi_status;
+ unsigned char *ctrl_base = dsi_host_private->dsi_base;
+
+ if (ctrl->panel_mode == DSI_CMD_MODE)
+ return rc;
+
+ dsi_status = MIPI_INP(ctrl_base + DSI_STATUS);
+ if (dsi_status & 0x08) {
+ pr_debug("dsi command in video mode wait for active region\n");
+ rc = msm_dsi_wait4video_done(ctrl);
+ /* delay 4-5 ms to skip BLLP */
+ if (!rc)
+ usleep_range(4000, 5000);
+ }
+ return rc;
+}
+
void msm_dsi_host_init(struct mipi_panel_info *pinfo)
{
- u32 dsi_ctrl, intr_ctrl, data;
+ u32 dsi_ctrl, data;
unsigned char *ctrl_base = dsi_host_private->dsi_base;
pr_debug("msm_dsi_host_init\n");
@@ -262,8 +419,6 @@
pr_err("%s: Unknown DSI mode=%d\n", __func__, pinfo->mode);
dsi_ctrl = BIT(8) | BIT(2); /* clock enable & cmd mode */
- intr_ctrl = 0;
- intr_ctrl = (DSI_INTR_CMD_DMA_DONE_MASK | DSI_INTR_CMD_MDP_DONE_MASK);
if (pinfo->crc_check)
dsi_ctrl |= BIT(24);
@@ -312,9 +467,6 @@
/* DSI_ERR_INT_MASK0 */
MIPI_OUTP(ctrl_base + DSI_ERR_INT_MASK0, 0x13ff3fe0);
- intr_ctrl |= DSI_INTR_ERROR_MASK;
- MIPI_OUTP(ctrl_base + DSI_INT_CTRL, intr_ctrl);
-
/* turn esc, byte, dsi, pclk, sclk, hclk on */
MIPI_OUTP(ctrl_base + DSI_CLK_CTRL, 0x23f);
@@ -404,7 +556,7 @@
void msm_dsi_op_mode_config(int mode, struct mdss_panel_data *pdata)
{
- u32 dsi_ctrl, intr_ctrl;
+ u32 dsi_ctrl;
unsigned char *ctrl_base = dsi_host_private->dsi_base;
pr_debug("msm_dsi_op_mode_config\n");
@@ -415,46 +567,24 @@
dsi_ctrl &= ~0x06;
- if (mode == DSI_VIDEO_MODE) {
+ if (mode == DSI_VIDEO_MODE)
dsi_ctrl |= 0x02;
- intr_ctrl = DSI_INTR_CMD_DMA_DONE_MASK;
- } else { /* command mode */
+ else
dsi_ctrl |= 0x04;
- intr_ctrl = DSI_INTR_CMD_DMA_DONE_MASK | DSI_INTR_ERROR_MASK |
- DSI_INTR_CMD_MDP_DONE_MASK;
- }
+ pr_debug("%s: dsi_ctrl=%x\n", __func__, dsi_ctrl);
- pr_debug("%s: dsi_ctrl=%x intr=%x\n", __func__, dsi_ctrl, intr_ctrl);
-
- MIPI_OUTP(ctrl_base + DSI_INT_CTRL, intr_ctrl);
MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl);
wmb();
}
-int msm_dsi_cmd_reg_tx(u32 data)
-{
- unsigned char *ctrl_base = dsi_host_private->dsi_base;
-
- MIPI_OUTP(ctrl_base + DSI_TRIG_CTRL, 0x04);/* sw trigger */
- MIPI_OUTP(ctrl_base + DSI_CTRL, 0x135);
- wmb();
-
- MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_DMA_CTRL, data);
- wmb();
- MIPI_OUTP(ctrl_base + DSI_CMD_MODE_DMA_SW_TRIGGER, 0x01);
- wmb();
-
- udelay(300); /*per spec*/
-
- return 0;
-}
-
-int msm_dsi_cmd_dma_tx(struct dsi_buf *tp)
+int msm_dsi_cmd_dma_tx(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dsi_buf *tp)
{
int len, rc;
unsigned long size, addr;
unsigned char *ctrl_base = dsi_host_private->dsi_base;
+ unsigned long flag;
len = ALIGN(tp->len, 4);
size = ALIGN(tp->len, SZ_4K);
@@ -468,7 +598,12 @@
addr = tp->dmap;
- INIT_COMPLETION(dsi_host_private->dma_comp);
+ msm_dsi_get_cmd_engine(ctrl);
+
+ spin_lock_irqsave(&ctrl->mdp_lock, flag);
+ INIT_COMPLETION(ctrl->dma_comp);
+ msm_dsi_set_irq(ctrl, DSI_INTR_CMD_DMA_DONE_MASK);
+ spin_unlock_irqrestore(&ctrl->mdp_lock, flag);
MIPI_OUTP(ctrl_base + DSI_DMA_CMD_OFFSET, addr);
MIPI_OUTP(ctrl_base + DSI_DMA_CMD_LENGTH, len);
@@ -477,7 +612,7 @@
MIPI_OUTP(ctrl_base + DSI_CMD_MODE_DMA_SW_TRIGGER, 0x01);
wmb();
- rc = wait_for_completion_timeout(&dsi_host_private->dma_comp,
+ rc = wait_for_completion_timeout(&ctrl->dma_comp,
msecs_to_jiffies(DSI_DMA_CMD_TIMEOUT_MS));
if (rc == 0) {
pr_err("DSI command transaction time out\n");
@@ -489,10 +624,16 @@
dma_unmap_single(&dsi_host_private->dis_dev, tp->dmap, size,
DMA_TO_DEVICE);
tp->dmap = 0;
+
+ msm_dsi_clear_irq(ctrl, DSI_INTR_CMD_DMA_DONE_MASK);
+
+ msm_dsi_release_cmd_engine(ctrl);
+
return rc;
}
-int msm_dsi_cmd_dma_rx(struct dsi_buf *rp, int rlen)
+int msm_dsi_cmd_dma_rx(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dsi_buf *rp, int rlen)
{
u32 *lp, data;
int i, off, cnt;
@@ -518,202 +659,317 @@
rp->len += sizeof(*lp);
}
- return 0;
+ return rlen;
}
-int msm_dsi_cmds_tx(struct mdss_panel_data *pdata,
- struct dsi_buf *tp, struct dsi_cmd_desc *cmds, int cnt)
+static int msm_dsi_cmds_tx(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dsi_cmd_desc *cmds, int cnt)
{
+ struct dsi_buf *tp;
struct dsi_cmd_desc *cm;
- u32 dsi_ctrl, ctrl;
- int i, video_mode, rc = 0;
- unsigned char *ctrl_base = dsi_host_private->dsi_base;
+ struct dsi_ctrl_hdr *dchdr;
+ int len;
+ int rc = 0;
- /* turn on cmd mode
- * for video mode, do not send cmds more than
- * one pixel line, since it only transmit it
- * during BLLP.
- */
- dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL);
- video_mode = dsi_ctrl & 0x02; /* VIDEO_MODE_EN */
- if (video_mode) {
- ctrl = dsi_ctrl | 0x04; /* CMD_MODE_EN */
- MIPI_OUTP(ctrl_base + DSI_CTRL, ctrl);
- }
- msm_dsi_enable_irq();
-
+ tp = &ctrl->tx_buf;
+ mdss_dsi_buf_init(tp);
cm = cmds;
- for (i = 0; i < cnt; i++) {
- dsi_buf_init(tp);
- dsi_cmd_dma_add(tp, cm);
- rc = msm_dsi_cmd_dma_tx(tp);
- if (IS_ERR_VALUE(rc)) {
- pr_err("%s: failed to call cmd_dma_tx\n", __func__);
- break;
+ len = 0;
+ while (cnt--) {
+ dchdr = &cm->dchdr;
+ mdss_dsi_buf_reserve(tp, len);
+ len = mdss_dsi_cmd_dma_add(tp, cm);
+ if (!len) {
+ pr_err("%s: failed to add cmd = 0x%x\n",
+ __func__, cm->payload[0]);
+ rc = -EINVAL;
+ goto dsi_cmds_tx_err;
}
- if (cm->dchdr.wait)
- msleep(cm->dchdr.wait);
+
+ if (dchdr->last) {
+ tp->data = tp->start; /* begin of buf */
+ rc = msm_dsi_wait4video_eng_busy(ctrl);
+ if (rc) {
+ pr_err("%s: wait4video_eng failed\n", __func__);
+ goto dsi_cmds_tx_err;
+
+ }
+
+ rc = msm_dsi_cmd_dma_tx(ctrl, tp);
+ if (IS_ERR_VALUE(len)) {
+ pr_err("%s: failed to call cmd_dma_tx for cmd = 0x%x\n",
+ __func__, cmds->payload[0]);
+ goto dsi_cmds_tx_err;
+ }
+
+ if (dchdr->wait)
+ usleep(dchdr->wait * 1000);
+
+ mdss_dsi_buf_init(tp);
+ len = 0;
+ }
cm++;
}
- msm_dsi_disable_irq();
-
- if (video_mode)
- MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl);
+dsi_cmds_tx_err:
return rc;
}
-/* MDSS_DSI_MRPS, Maximum Return Packet Size */
-static char max_pktsize[2] = {0x00, 0x00}; /* LSB tx first, 10 bytes */
-
-static struct dsi_cmd_desc pkt_size_cmd[] = {
- {{DTYPE_MAX_PKTSIZE, 1, 0, 0, 0,
- sizeof(max_pktsize)}, max_pktsize}
-};
-
-/*
- * DSI panel reply with MAX_RETURN_PACKET_SIZE bytes of data
- * plus DCS header, ECC and CRC for DCS long read response
- * mdss_dsi_controller only have 4x32 bits register ( 16 bytes) to
- * hold data per transaction.
- * MDSS_DSI_LEN equal to 8
- * len should be either 4 or 8
- * any return data more than MDSS_DSI_LEN need to be break down
- * to multiple transactions.
- *
- * ov_mutex need to be acquired before call this function.
- */
-int msm_dsi_cmds_rx(struct mdss_panel_data *pdata,
- struct dsi_buf *tp, struct dsi_buf *rp,
- struct dsi_cmd_desc *cmds, int rlen)
+static int msm_dsi_parse_rx_response(struct dsi_buf *rp)
{
- int cnt, len, diff, pkt_size, rc = 0;
- char cmd;
- unsigned char *ctrl_base = dsi_host_private->dsi_base;
- u32 dsi_ctrl, data;
- int video_mode;
-
- /* turn on cmd mode for video mode */
- dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL);
- video_mode = dsi_ctrl & 0x02; /* VIDEO_MODE_EN */
- if (video_mode) {
- data = dsi_ctrl | 0x04; /* CMD_MODE_EN */
- MIPI_OUTP(ctrl_base + DSI_CTRL, data);
- }
-
- if (pdata->panel_info.mipi.no_max_pkt_size)
- rlen = ALIGN(rlen, 4); /* Only support rlen = 4*n */
-
- len = rlen;
- diff = 0;
-
- if (len <= 2) {
- cnt = 4; /* short read */
- } else {
- if (len > MDSS_DSI_LEN)
- len = MDSS_DSI_LEN; /* 8 bytes at most */
-
- len = ALIGN(len, 4); /* len 4 bytes align */
- diff = len - rlen;
- /*
- * add extra 2 bytes to len to have overall
- * packet size is multipe by 4. This also make
- * sure 4 bytes dcs headerlocates within a
- * 32 bits register after shift in.
- * after all, len should be either 6 or 10.
- */
- len += 2;
- cnt = len + 6; /* 4 bytes header + 2 bytes crc */
- }
-
- msm_dsi_enable_irq();
-
- if (!pdata->panel_info.mipi.no_max_pkt_size) {
- /* packet size need to be set at every read */
- pkt_size = len;
- max_pktsize[0] = pkt_size;
- dsi_buf_init(tp);
- dsi_cmd_dma_add(tp, pkt_size_cmd);
- rc = msm_dsi_cmd_dma_tx(tp);
- if (IS_ERR_VALUE(rc)) {
- msm_dsi_disable_irq();
- pr_err("%s: dma_tx failed\n", __func__);
- rp->len = 0;
- goto end;
- }
- pr_debug("%s: Max packet size sent\n", __func__);
- }
-
- dsi_buf_init(tp);
- dsi_cmd_dma_add(tp, cmds);
-
- /* transmit read comamnd to client */
- msm_dsi_cmd_dma_tx(tp);
- if (IS_ERR_VALUE(rc)) {
- msm_dsi_disable_irq();
- pr_err("%s: dma_tx failed\n", __func__);
- rp->len = 0;
- goto end;
- }
- /*
- * once cmd_dma_done interrupt received,
- * return data from client is ready and stored
- * at RDBK_DATA register already
- */
- dsi_buf_init(rp);
- if (pdata->panel_info.mipi.no_max_pkt_size) {
- /*
- * expect rlen = n * 4
- * short alignement for start addr
- */
- rp->data += 2;
- }
-
- msm_dsi_cmd_dma_rx(rp, cnt);
-
- msm_dsi_disable_irq();
-
- if (pdata->panel_info.mipi.no_max_pkt_size) {
- /*
- * remove extra 2 bytes from previous
- * rx transaction at shift register
- * which was inserted during copy
- * shift registers to rx buffer
- * rx payload start from long alignment addr
- */
- rp->data += 2;
- }
+ int rc = 0;
+ unsigned char cmd;
cmd = rp->data[0];
switch (cmd) {
case DTYPE_ACK_ERR_RESP:
pr_debug("%s: rx ACK_ERR_PACLAGE\n", __func__);
+ rc = -EINVAL;
break;
case DTYPE_GEN_READ1_RESP:
case DTYPE_DCS_READ1_RESP:
- dsi_short_read1_resp(rp);
+ mdss_dsi_short_read1_resp(rp);
break;
case DTYPE_GEN_READ2_RESP:
case DTYPE_DCS_READ2_RESP:
- dsi_short_read2_resp(rp);
+ mdss_dsi_short_read2_resp(rp);
break;
case DTYPE_GEN_LREAD_RESP:
case DTYPE_DCS_LREAD_RESP:
- dsi_long_read_resp(rp);
- rp->len -= 2; /* extra 2 bytes added */
- rp->len -= diff; /* align bytes */
+ mdss_dsi_long_read_resp(rp);
break;
default:
- pr_debug("%s: Unknown cmd received\n", __func__);
+ rc = -EINVAL;
+ pr_warn("%s: Unknown cmd received\n", __func__);
break;
}
- if (video_mode)
- MIPI_OUTP(ctrl_base + DSI_CTRL,
- dsi_ctrl); /* restore */
-end:
- return rp->len;
+ return rc;
+}
+
+/* MIPI_DSI_MRPS, Maximum Return Packet Size */
+static char max_pktsize[2] = {0x00, 0x00}; /* LSB tx first, 10 bytes */
+
+static struct dsi_cmd_desc pkt_size_cmd = {
+ {DTYPE_MAX_PKTSIZE, 1, 0, 0, 0, sizeof(max_pktsize)},
+ max_pktsize,
+};
+
+static int msm_dsi_set_max_packet_size(struct mdss_dsi_ctrl_pdata *ctrl,
+ int size)
+{
+ struct dsi_buf *tp;
+ int rc;
+
+ tp = &ctrl->tx_buf;
+ mdss_dsi_buf_init(tp);
+ max_pktsize[0] = size;
+
+ rc = mdss_dsi_cmd_dma_add(tp, &pkt_size_cmd);
+ if (!rc) {
+ pr_err("%s: failed to add max_pkt_size\n", __func__);
+ return -EINVAL;
+ }
+
+ rc = msm_dsi_wait4video_eng_busy(ctrl);
+ if (rc) {
+ pr_err("%s: failed to wait4video_eng\n", __func__);
+ return rc;
+ }
+
+ rc = msm_dsi_cmd_dma_tx(ctrl, tp);
+ if (IS_ERR_VALUE(rc)) {
+ pr_err("%s: failed to tx max_pkt_size\n", __func__);
+ return rc;
+ }
+ pr_debug("%s: max_pkt_size=%d sent\n", __func__, size);
+ return rc;
+}
+
+/* read data length is less than or equal to 10 bytes*/
+static int msm_dsi_cmds_rx_1(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dsi_cmd_desc *cmds, int rlen)
+{
+ int rc;
+ struct dsi_buf *tp, *rp;
+
+ tp = &ctrl->tx_buf;
+ rp = &ctrl->rx_buf;
+ mdss_dsi_buf_init(rp);
+ mdss_dsi_buf_init(tp);
+
+ rc = mdss_dsi_cmd_dma_add(tp, cmds);
+ if (!rc) {
+ pr_err("%s: dsi_cmd_dma_add failed\n", __func__);
+ rc = -EINVAL;
+ goto dsi_cmds_rx_1_error;
+ }
+
+ rc = msm_dsi_wait4video_eng_busy(ctrl);
+ if (rc) {
+ pr_err("%s: wait4video_eng failed\n", __func__);
+ goto dsi_cmds_rx_1_error;
+ }
+
+ rc = msm_dsi_cmd_dma_tx(ctrl, tp);
+ if (IS_ERR_VALUE(rc)) {
+ pr_err("%s: msm_dsi_cmd_dma_tx failed\n", __func__);
+ goto dsi_cmds_rx_1_error;
+ }
+
+ if (rlen <= DSI_SHORT_PKT_DATA_SIZE) {
+ msm_dsi_cmd_dma_rx(ctrl, rp, rlen);
+ } else {
+ msm_dsi_cmd_dma_rx(ctrl, rp, rlen + DSI_HOST_HDR_SIZE);
+ rp->len = rlen + DSI_HOST_HDR_SIZE;
+ }
+ rc = msm_dsi_parse_rx_response(rp);
+
+dsi_cmds_rx_1_error:
+ if (rc)
+ rp->len = 0;
+
+ return rc;
+}
+
+/* read data length is more than 10 bytes, which requires multiple DSI read*/
+static int msm_dsi_cmds_rx_2(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dsi_cmd_desc *cmds, int rlen)
+{
+ int rc;
+ struct dsi_buf *tp, *rp;
+ int pkt_size, data_bytes, total;
+
+ tp = &ctrl->tx_buf;
+ rp = &ctrl->rx_buf;
+ mdss_dsi_buf_init(rp);
+ pkt_size = DSI_MAX_PKT_SIZE;
+ data_bytes = MDSS_DSI_LEN;
+ total = 0;
+
+ while (true) {
+ rc = msm_dsi_set_max_packet_size(ctrl, pkt_size);
+ if (rc)
+ break;
+
+ mdss_dsi_buf_init(tp);
+ rc = mdss_dsi_cmd_dma_add(tp, cmds);
+ if (!rc) {
+ pr_err("%s: dsi_cmd_dma_add failed\n", __func__);
+ rc = -EINVAL;
+ break;
+ }
+ rc = msm_dsi_wait4video_eng_busy(ctrl);
+ if (rc) {
+ pr_err("%s: wait4video_eng failed\n", __func__);
+ break;
+ }
+
+ rc = msm_dsi_cmd_dma_tx(ctrl, tp);
+ if (IS_ERR_VALUE(rc)) {
+ pr_err("%s: msm_dsi_cmd_dma_tx failed\n", __func__);
+ break;
+ }
+
+ msm_dsi_cmd_dma_rx(ctrl, rp, DSI_MAX_BYTES_TO_READ);
+
+ rp->data += DSI_MAX_BYTES_TO_READ - DSI_HOST_HDR_SIZE;
+ total += data_bytes;
+ if (total >= rlen)
+ break;
+
+ data_bytes = DSI_MAX_BYTES_TO_READ - DSI_HOST_HDR_SIZE;
+ pkt_size += data_bytes;
+ }
+
+ if (!rc) {
+ rp->data = rp->start;
+ rp->len = rlen + DSI_HOST_HDR_SIZE;
+ rc = msm_dsi_parse_rx_response(rp);
+ }
+
+ if (rc)
+ rp->len = 0;
+
+ return rc;
+}
+
+int msm_dsi_cmds_rx(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dsi_cmd_desc *cmds, int rlen)
+{
+ int rc;
+ if (rlen <= DSI_MAX_PKT_SIZE)
+ rc = msm_dsi_cmds_rx_1(ctrl, cmds, rlen);
+ else
+ rc = msm_dsi_cmds_rx_2(ctrl, cmds, rlen);
+
+ return rc;
+}
+
+void msm_dsi_cmdlist_tx(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dcs_cmd_req *req)
+{
+ int ret;
+
+ ret = msm_dsi_cmds_tx(ctrl, req->cmds, req->cmds_cnt);
+
+ if (req->cb)
+ req->cb(ret);
+}
+
+void msm_dsi_cmdlist_rx(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dcs_cmd_req *req)
+{
+ struct dsi_buf *rp;
+ int len = 0;
+
+ if (req->rbuf) {
+ rp = &ctrl->rx_buf;
+ len = msm_dsi_cmds_rx(ctrl, req->cmds, req->rlen);
+ memcpy(req->rbuf, rp->data, rp->len);
+ } else {
+ pr_err("%s: No rx buffer provided\n", __func__);
+ }
+
+ if (req->cb)
+ req->cb(len);
+}
+int msm_dsi_cmdlist_commit(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp)
+{
+ struct dcs_cmd_req *req;
+ int dsi_on;
+ int ret = -EINVAL;
+
+ mutex_lock(&ctrl->mutex);
+ dsi_on = dsi_host_private->dsi_on;
+ mutex_unlock(&ctrl->mutex);
+ if (!dsi_on) {
+ pr_err("try to send DSI commands while dsi is off\n");
+ return ret;
+ }
+
+ mutex_lock(&ctrl->cmd_mutex);
+ req = mdss_dsi_cmdlist_get(ctrl);
+
+ if (!req) {
+ mutex_unlock(&ctrl->cmd_mutex);
+ return ret;
+ }
+
+ msm_dsi_clk_ctrl(&ctrl->panel_data, 1);
+ dsi_set_tx_power_mode(0);
+
+ if (req->flags & CMD_REQ_RX)
+ msm_dsi_cmdlist_rx(ctrl, req);
+ else
+ msm_dsi_cmdlist_tx(ctrl, req);
+
+ dsi_set_tx_power_mode(1);
+ msm_dsi_clk_ctrl(&ctrl->panel_data, 0);
+
+ mutex_unlock(&ctrl->cmd_mutex);
+ return 0;
}
static int msm_dsi_cal_clk_rate(struct mdss_panel_data *pdata,
@@ -785,11 +1041,14 @@
ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
panel_data);
+ mutex_lock(&ctrl_pdata->mutex);
+
ret = msm_dss_enable_vreg(
ctrl_pdata->power_data.vreg_config,
ctrl_pdata->power_data.num_vreg, 1);
if (ret) {
pr_err("%s: DSI power on failed\n", __func__);
+ mutex_unlock(&ctrl_pdata->mutex);
return ret;
}
@@ -876,6 +1135,11 @@
msm_dsi_op_mode_config(mipi->mode, pdata);
+ msm_dsi_set_irq(ctrl_pdata, DSI_INTR_ERROR_MASK);
+ dsi_host_private->clk_count = 1;
+ dsi_host_private->dsi_on = 1;
+ mutex_unlock(&ctrl_pdata->mutex);
+
return ret;
}
@@ -894,6 +1158,8 @@
panel_data);
pr_debug("msm_dsi_off\n");
+ mutex_lock(&ctrl_pdata->mutex);
+ msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask);
msm_dsi_controller_cfg(0);
msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, 0, 0, 0);
msm_dsi_clk_disable();
@@ -906,8 +1172,11 @@
ctrl_pdata->power_data.num_vreg, 0);
if (ret) {
pr_err("%s: Panel power off failed\n", __func__);
- return ret;
}
+ dsi_host_private->clk_count = 0;
+ dsi_host_private->dsi_on = 0;
+
+ mutex_unlock(&ctrl_pdata->mutex);
return ret;
}
@@ -931,20 +1200,58 @@
panel_data);
pinfo = &pdata->panel_info;
+ mutex_lock(&ctrl_pdata->mutex);
ret = msm_dss_enable_vreg(
ctrl_pdata->power_data.vreg_config,
ctrl_pdata->power_data.num_vreg, 1);
if (ret) {
pr_err("%s: DSI power on failed\n", __func__);
+ mutex_unlock(&ctrl_pdata->mutex);
return ret;
}
msm_dsi_ahb_ctrl(1);
msm_dsi_prepare_clocks();
msm_dsi_clk_enable();
+ msm_dsi_set_irq(ctrl_pdata, DSI_INTR_ERROR_MASK);
+ dsi_host_private->clk_count = 1;
+ dsi_host_private->dsi_on = 1;
+ mutex_unlock(&ctrl_pdata->mutex);
return 0;
}
+int msm_dsi_bta_status_check(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
+{
+ int ret = 0;
+
+ if (ctrl_pdata == NULL) {
+ pr_err("%s: Invalid input data\n", __func__);
+ return 0;
+ }
+
+ mutex_lock(&ctrl_pdata->cmd_mutex);
+ msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 1);
+ msm_dsi_cmd_mdp_busy(ctrl_pdata);
+ msm_dsi_set_irq(ctrl_pdata, DSI_INTR_BTA_DONE_MASK);
+ INIT_COMPLETION(ctrl_pdata->bta_comp);
+
+ /* BTA trigger */
+ MIPI_OUTP(dsi_host_private->dsi_base + DSI_CMD_MODE_BTA_SW_TRIGGER,
+ 0x01);
+ wmb();
+ ret = wait_for_completion_killable_timeout(&ctrl_pdata->bta_comp,
+ HZ/10);
+ msm_dsi_clear_irq(ctrl_pdata, DSI_INTR_BTA_DONE_MASK);
+ msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 0);
+ mutex_unlock(&ctrl_pdata->cmd_mutex);
+
+ if (ret <= 0)
+ pr_err("%s: DSI BTA error: %i\n", __func__, __LINE__);
+
+ pr_debug("%s: BTA done with ret: %d\n", __func__, ret);
+ return ret;
+}
+
static void msm_dsi_debug_enable_clock(int on)
{
if (dsi_host_private->debug_enable_clk)
@@ -1070,6 +1377,58 @@
return dsi_pan_node;
}
+static int msm_dsi_clk_ctrl(struct mdss_panel_data *pdata, int enable)
+{
+ u32 bitclk_rate = 0, byteclk_rate = 0, pclk_rate = 0, dsiclk_rate = 0;
+ struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
+
+ pr_debug("%s:\n", __func__);
+
+ ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
+ panel_data);
+
+ mutex_lock(&ctrl_pdata->mutex);
+
+ if (enable) {
+ dsi_host_private->clk_count++;
+ if (dsi_host_private->clk_count == 1) {
+ msm_dsi_ahb_ctrl(1);
+ msm_dsi_cal_clk_rate(pdata, &bitclk_rate, &dsiclk_rate,
+ &byteclk_rate, &pclk_rate);
+ msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, dsiclk_rate,
+ byteclk_rate, pclk_rate);
+ msm_dsi_clk_enable();
+ }
+ } else {
+ dsi_host_private->clk_count--;
+ if (dsi_host_private->clk_count == 0) {
+ msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, 0, 0, 0);
+ msm_dsi_clk_disable();
+ msm_dsi_ahb_ctrl(0);
+ }
+ }
+ mutex_unlock(&ctrl_pdata->mutex);
+ return 0;
+}
+
+void msm_dsi_ctrl_init(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ init_completion(&ctrl->dma_comp);
+ init_completion(&ctrl->mdp_comp);
+ init_completion(&ctrl->bta_comp);
+ init_completion(&ctrl->video_comp);
+ spin_lock_init(&ctrl->irq_lock);
+ spin_lock_init(&ctrl->mdp_lock);
+ mutex_init(&ctrl->mutex);
+ mutex_init(&ctrl->cmd_mutex);
+ complete(&ctrl->mdp_comp);
+ dsi_buf_alloc(&ctrl->tx_buf, SZ_4K);
+ dsi_buf_alloc(&ctrl->rx_buf, SZ_4K);
+ ctrl->cmdlist_commit = msm_dsi_cmdlist_commit;
+ ctrl->panel_mode = ctrl->panel_data.panel_info.mipi.mode;
+ ctrl->check_status = msm_dsi_bta_status_check;
+}
+
static int __devinit msm_dsi_probe(struct platform_device *pdev)
{
struct dsi_interface intf;
@@ -1130,7 +1489,8 @@
rc = -ENODEV;
goto error_irq_resource;
} else {
- rc = msm_dsi_irq_init(&pdev->dev, mdss_dsi_mres->start);
+ rc = msm_dsi_irq_init(&pdev->dev, mdss_dsi_mres->start,
+ ctrl_pdata);
if (rc) {
dev_err(&pdev->dev, "%s: failed to init irq, rc=%d\n",
__func__, rc);
@@ -1188,15 +1548,16 @@
intf.on = msm_dsi_on;
intf.off = msm_dsi_off;
intf.cont_on = msm_dsi_cont_on;
+ intf.clk_ctrl = msm_dsi_clk_ctrl;
intf.op_mode_config = msm_dsi_op_mode_config;
- intf.tx = msm_dsi_cmds_tx;
- intf.rx = msm_dsi_cmds_rx;
intf.index = 0;
intf.private = NULL;
dsi_register_interface(&intf);
msm_dsi_debug_init();
+ msm_dsi_ctrl_init(ctrl_pdata);
+
rc = dsi_panel_device_register_v2(pdev, ctrl_pdata);
if (rc) {
pr_err("%s: dsi panel dev reg failed\n", __func__);
@@ -1211,7 +1572,7 @@
error_pan_node:
of_node_put(dsi_pan_node);
error_platform_pop:
- msm_dsi_disable_irq();
+ msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask);
error_irq_resource:
if (dsi_host_private->dsi_base) {
iounmap(dsi_host_private->dsi_base);
@@ -1233,7 +1594,7 @@
return -ENODEV;
}
- msm_dsi_disable_irq();
+ msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask);
msm_dsi_io_deinit(pdev, &(ctrl_pdata->power_data));
dsi_ctrl_config_deinit(pdev, ctrl_pdata);
iounmap(dsi_host_private->dsi_base);
diff --git a/drivers/video/msm/mdss/dsi_host_v2.h b/drivers/video/msm/mdss/dsi_host_v2.h
index cec9774..b297452 100644
--- a/drivers/video/msm/mdss/dsi_host_v2.h
+++ b/drivers/video/msm/mdss/dsi_host_v2.h
@@ -17,6 +17,8 @@
#define DSI_INTR_ERROR_MASK BIT(25)
#define DSI_INTR_ERROR BIT(24)
+#define DSI_INTR_BTA_DONE_MASK BIT(21)
+#define DSI_INTR_BTA_DONE BIT(20)
#define DSI_INTR_VIDEO_DONE_MASK BIT(17)
#define DSI_INTR_VIDEO_DONE BIT(16)
#define DSI_INTR_CMD_MDP_DONE_MASK BIT(9)
@@ -24,6 +26,8 @@
#define DSI_INTR_CMD_DMA_DONE_MASK BIT(1)
#define DSI_INTR_CMD_DMA_DONE BIT(0)
+#define DSI_BTA_TERM BIT(1)
+
#define DSI_CTRL 0x0000
#define DSI_STATUS 0x0004
#define DSI_FIFO_STATUS 0x0008
diff --git a/drivers/video/msm/mdss/dsi_status_v2.c b/drivers/video/msm/mdss/dsi_status_v2.c
new file mode 100644
index 0000000..d62ddf3
--- /dev/null
+++ b/drivers/video/msm/mdss/dsi_status_v2.c
@@ -0,0 +1,188 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/fb.h>
+#include <linux/notifier.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <linux/iopoll.h>
+#include <linux/kobject.h>
+#include <linux/string.h>
+#include <linux/sysfs.h>
+
+#include "mdss_fb.h"
+#include "mdss_dsi.h"
+#include "mdss_panel.h"
+#include "mdp3_ctrl.h"
+
+#define STATUS_CHECK_INTERVAL 5000
+
+/**
+ * dsi_status_data - Stores all the data necessary for this module
+ * @fb_notif: Used to egister for the fb events
+ * @live_status: Delayed worker structure, used to associate the
+ * delayed worker function
+ * @mfd: Used to store the msm_fb_data_type received when the notifier
+ * call back happens
+ * @root: Stores the dir created by debuugfs
+ * @debugfs_reset_panel: The debugfs variable used to inject errors
+ */
+
+struct dsi_status_data {
+ struct notifier_block fb_notifier;
+ struct delayed_work check_status;
+ struct msm_fb_data_type *mfd;
+ uint32_t check_interval;
+};
+struct dsi_status_data *pstatus_data;
+static uint32_t interval = STATUS_CHECK_INTERVAL;
+
+void check_dsi_ctrl_status(struct work_struct *work)
+{
+ struct dsi_status_data *pdsi_status = NULL;
+ struct mdss_panel_data *pdata = NULL;
+ struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
+ struct mdp3_session_data *mdp3_session = NULL;
+ int ret = 0;
+
+ pdsi_status = container_of(to_delayed_work(work),
+ struct dsi_status_data, check_status);
+ if (!pdsi_status) {
+ pr_err("%s: DSI status data not available\n", __func__);
+ return;
+ }
+
+ pdata = dev_get_platdata(&pdsi_status->mfd->pdev->dev);
+ if (!pdata) {
+ pr_err("%s: Panel data not available\n", __func__);
+ return;
+ }
+ ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
+ panel_data);
+ if (!ctrl_pdata || !ctrl_pdata->check_status) {
+ pr_err("%s: DSI ctrl or status_check callback not avilable\n",
+ __func__);
+ return;
+ }
+ mdp3_session = pdsi_status->mfd->mdp.private1;
+ mutex_lock(&mdp3_session->lock);
+
+ ret = ctrl_pdata->check_status(ctrl_pdata);
+
+ mutex_unlock(&mdp3_session->lock);
+
+ if ((pdsi_status->mfd->panel_power_on)) {
+ if (ret > 0) {
+ schedule_delayed_work(&pdsi_status->check_status,
+ msecs_to_jiffies(pdsi_status->check_interval));
+ } else {
+ char *envp[2] = {"PANEL_ALIVE=0", NULL};
+ pdata->panel_info.panel_dead = true;
+ ret = kobject_uevent_env(
+ &pdsi_status->mfd->fbi->dev->kobj,
+ KOBJ_CHANGE, envp);
+ pr_err("%s: Panel has gone bad, sending uevent - %s\n",
+ __func__, envp[0]);
+ }
+ }
+}
+
+/**
+ * fb_notifier_callback() - Call back function for the fb_register_client()
+ * notifying events
+ * @self : notifier block
+ * @event : The event that was triggered
+ * @data : Of type struct fb_event
+ *
+ * - This function listens for FB_BLANK_UNBLANK and FB_BLANK_POWERDOWN events
+ * - Based on the event the delayed work is either scheduled again after
+ * PANEL_STATUS_CHECK_INTERVAL or cancelled
+ */
+static int fb_event_callback(struct notifier_block *self,
+ unsigned long event, void *data)
+{
+ struct fb_event *evdata = (struct fb_event *)data;
+ struct dsi_status_data *pdata = container_of(self,
+ struct dsi_status_data, fb_notifier);
+ pdata->mfd = (struct msm_fb_data_type *)evdata->info->par;
+
+ if (event == FB_EVENT_BLANK && evdata) {
+ int *blank = evdata->data;
+ switch (*blank) {
+ case FB_BLANK_UNBLANK:
+ schedule_delayed_work(&pdata->check_status,
+ msecs_to_jiffies(STATUS_CHECK_INTERVAL));
+ break;
+ case FB_BLANK_POWERDOWN:
+ cancel_delayed_work(&pdata->check_status);
+ break;
+ }
+ }
+ return 0;
+}
+
+int __init mdss_dsi_status_init(void)
+{
+ int rc;
+
+ pstatus_data = kzalloc(sizeof(struct dsi_status_data), GFP_KERNEL);
+ if (!pstatus_data) {
+ pr_err("%s: can't alloc mem\n", __func__);
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ memset(pstatus_data, 0, sizeof(struct dsi_status_data));
+
+ pstatus_data->fb_notifier.notifier_call = fb_event_callback;
+
+ rc = fb_register_client(&pstatus_data->fb_notifier);
+ if (rc < 0) {
+ pr_err("%s: fb_register_client failed, returned with rc=%d\n",
+ __func__, rc);
+ kfree(pstatus_data);
+ return -EPERM;
+ }
+
+ pstatus_data->check_interval = interval;
+ pr_info("%s: DSI status check interval:%d\n", __func__, interval);
+
+ INIT_DELAYED_WORK(&pstatus_data->check_status, check_dsi_ctrl_status);
+
+ pr_debug("%s: DSI ctrl status thread initialized\n", __func__);
+
+ return rc;
+}
+
+void __exit mdss_dsi_status_exit(void)
+{
+ fb_unregister_client(&pstatus_data->fb_notifier);
+ cancel_delayed_work_sync(&pstatus_data->check_status);
+ kfree(pstatus_data);
+ pr_debug("%s: DSI ctrl status thread removed\n", __func__);
+}
+
+module_param(interval, uint, 0);
+MODULE_PARM_DESC(interval,
+ "Duration in milliseconds to send BTA command for checking"
+ "DSI status periodically");
+
+module_init(mdss_dsi_status_init);
+module_exit(mdss_dsi_status_exit);
+
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/msm/mdss/dsi_v2.c b/drivers/video/msm/mdss/dsi_v2.c
index 65cca0e..ccde545 100644
--- a/drivers/video/msm/mdss/dsi_v2.c
+++ b/drivers/video/msm/mdss/dsi_v2.c
@@ -21,7 +21,6 @@
#include "dsi_v2.h"
static struct dsi_interface dsi_intf;
-static struct dsi_buf dsi_panel_tx_buf;
static int dsi_off(struct mdss_panel_data *pdata)
{
@@ -67,21 +66,13 @@
if (enable) {
dsi_ctrl_gpio_request(ctrl_pdata);
mdss_dsi_panel_reset(pdata, 1);
-
- rc = dsi_cmds_tx_v2(pdata, &dsi_panel_tx_buf,
- ctrl_pdata->on_cmds.cmds,
- ctrl_pdata->on_cmds.cmd_cnt);
-
+ rc = ctrl_pdata->on(pdata);
if (rc)
pr_err("dsi_panel_handler panel on failed %d\n", rc);
} else {
if (dsi_intf.op_mode_config)
dsi_intf.op_mode_config(DSI_CMD_MODE, pdata);
-
- dsi_cmds_tx_v2(pdata, &dsi_panel_tx_buf,
- ctrl_pdata->off_cmds.cmds,
- ctrl_pdata->off_cmds.cmd_cnt);
-
+ rc = ctrl_pdata->off(pdata);
mdss_dsi_panel_reset(pdata, 0);
dsi_ctrl_gpio_free(ctrl_pdata);
}
@@ -104,6 +95,18 @@
return rc;
}
+static int dsi_clk_ctrl(struct mdss_panel_data *pdata, int enable)
+{
+ int rc = 0;
+
+ pr_debug("%s:\n", __func__);
+
+ if (dsi_intf.clk_ctrl)
+ rc = dsi_intf.clk_ctrl(pdata, enable);
+
+ return rc;
+}
+
static int dsi_event_handler(struct mdss_panel_data *pdata,
int event, void *arg)
{
@@ -130,6 +133,9 @@
case MDSS_EVENT_CONT_SPLASH_BEGIN:
rc = dsi_splash_on(pdata);
break;
+ case MDSS_EVENT_PANEL_CLK_CTRL:
+ rc = dsi_clk_ctrl(pdata, (int)arg);
+ break;
default:
pr_debug("%s: unhandled event=%d\n", __func__, event);
break;
@@ -557,19 +563,12 @@
ctrl_pdata->panel_data.event_handler = dsi_event_handler;
- rc = dsi_buf_alloc(&dsi_panel_tx_buf,
- ALIGN(DSI_BUF_SIZE,
- SZ_4K));
- if (rc)
- return rc;
-
/*
* register in mdp driver
*/
rc = mdss_register_panel(dev, &(ctrl_pdata->panel_data));
if (rc) {
dev_err(&dev->dev, "unable to register MIPI DSI panel\n");
- kfree(dsi_panel_tx_buf.start);
return rc;
}
@@ -582,72 +581,6 @@
dsi_intf = *intf;
}
-int dsi_cmds_tx_v2(struct mdss_panel_data *pdata,
- struct dsi_buf *tp, struct dsi_cmd_desc *cmds,
- int cnt)
-{
- int rc = 0;
-
- if (!dsi_intf.tx)
- return -EINVAL;
-
- rc = dsi_intf.tx(pdata, tp, cmds, cnt);
- return rc;
-}
-
-int dsi_cmds_rx_v2(struct mdss_panel_data *pdata,
- struct dsi_buf *tp, struct dsi_buf *rp,
- struct dsi_cmd_desc *cmds, int rlen)
-{
- int rc = 0;
-
- if (pdata == NULL) {
- pr_err("%s: Invalid input data\n", __func__);
- return -EINVAL;
- }
-
- if (!dsi_intf.rx)
- return -EINVAL;
-
- rc = dsi_intf.rx(pdata, tp, rp, cmds, rlen);
- return rc;
-}
-
-static char *dsi_buf_reserve(struct dsi_buf *dp, int len)
-{
- dp->data += len;
- return dp->data;
-}
-
-
-static char *dsi_buf_push(struct dsi_buf *dp, int len)
-{
- dp->data -= len;
- dp->len += len;
- return dp->data;
-}
-
-static char *dsi_buf_reserve_hdr(struct dsi_buf *dp, int hlen)
-{
- dp->hdr = (u32 *)dp->data;
- return dsi_buf_reserve(dp, hlen);
-}
-
-char *dsi_buf_init(struct dsi_buf *dp)
-{
- int off;
-
- dp->data = dp->start;
- off = (int)dp->data;
- /* 8 byte align */
- off &= 0x07;
- if (off)
- off = 8 - off;
- dp->data += off;
- dp->len = 0;
- return dp->data;
-}
-
int dsi_buf_alloc(struct dsi_buf *dp, int size)
{
dp->start = kmalloc(size, GFP_KERNEL);
@@ -669,507 +602,3 @@
return 0;
}
-/*
- * mipi dsi generic long write
- */
-static int dsi_generic_lwrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- char *bp;
- u32 *hp;
- int i, len;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- bp = dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
-
- /* fill up payload */
- if (cm->payload) {
- len = dchdr->dlen;
- len += 3;
- len &= ~0x03; /* multipled by 4 */
- for (i = 0; i < dchdr->dlen; i++)
- *bp++ = cm->payload[i];
-
- /* append 0xff to the end */
- for (; i < len; i++)
- *bp++ = 0xff;
-
- dp->len += len;
- }
-
- /* fill up header */
- hp = dp->hdr;
- *hp = 0;
- *hp = DSI_HDR_WC(dchdr->dlen);
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_LONG_PKT;
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_LWRITE);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len;
-}
-
-/*
- * mipi dsi generic short write with 0, 1 2 parameters
- */
-static int dsi_generic_swrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- int len;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- if (dchdr->dlen && cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return 0;
- }
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- len = (dchdr->dlen > 2) ? 2 : dchdr->dlen;
-
- if (len == 1) {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_WRITE1);
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(0);
- } else if (len == 2) {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_WRITE2);
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(cm->payload[1]);
- } else {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_WRITE);
- *hp |= DSI_HDR_DATA1(0);
- *hp |= DSI_HDR_DATA2(0);
- }
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len;
-}
-
-/*
- * mipi dsi gerneric read with 0, 1 2 parameters
- */
-static int dsi_generic_read(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- int len;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- if (dchdr->dlen && cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return 0;
- }
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_BTA;
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- len = (dchdr->dlen > 2) ? 2 : dchdr->dlen;
-
- if (len == 1) {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_READ1);
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(0);
- } else if (len == 2) {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_READ2);
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(cm->payload[1]);
- } else {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_READ);
- *hp |= DSI_HDR_DATA1(0);
- *hp |= DSI_HDR_DATA2(0);
- }
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return dp->len;
-}
-
-/*
- * mipi dsi dcs long write
- */
-static int dsi_dcs_lwrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- char *bp;
- u32 *hp;
- int i, len;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- bp = dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
-
- /*
- * fill up payload
- * dcs command byte (first byte) followed by payload
- */
- if (cm->payload) {
- len = dchdr->dlen;
- len += 3;
- len &= ~0x03; /* multipled by 4 */
- for (i = 0; i < dchdr->dlen; i++)
- *bp++ = cm->payload[i];
-
- /* append 0xff to the end */
- for (; i < len; i++)
- *bp++ = 0xff;
-
- dp->len += len;
- }
-
- /* fill up header */
- hp = dp->hdr;
- *hp = 0;
- *hp = DSI_HDR_WC(dchdr->dlen);
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_LONG_PKT;
- *hp |= DSI_HDR_DTYPE(DTYPE_DCS_LWRITE);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len;
-}
-
-/*
- * mipi dsi dcs short write with 0 parameters
- */
-static int dsi_dcs_swrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- int len;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- if (cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return -EINVAL;
- }
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- if (dchdr->ack)
- *hp |= DSI_HDR_BTA;
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- len = (dchdr->dlen > 1) ? 1 : dchdr->dlen;
-
- *hp |= DSI_HDR_DTYPE(DTYPE_DCS_WRITE);
- *hp |= DSI_HDR_DATA1(cm->payload[0]); /* dcs command byte */
- *hp |= DSI_HDR_DATA2(0);
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return dp->len;
-}
-
-/*
- * mipi dsi dcs short write with 1 parameters
- */
-static int dsi_dcs_swrite1(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- if (dchdr->dlen < 2 || cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return -EINVAL;
- }
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- if (dchdr->ack)
- *hp |= DSI_HDR_BTA;
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- *hp |= DSI_HDR_DTYPE(DTYPE_DCS_WRITE1);
- *hp |= DSI_HDR_DATA1(cm->payload[0]); /* dcs comamnd byte */
- *hp |= DSI_HDR_DATA2(cm->payload[1]); /* parameter */
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len;
-}
-
-/*
- * mipi dsi dcs read with 0 parameters
- */
-static int dsi_dcs_read(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- if (cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return -EINVAL;
- }
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_BTA;
- *hp |= DSI_HDR_DTYPE(DTYPE_DCS_READ);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- *hp |= DSI_HDR_DATA1(cm->payload[0]); /* dcs command byte */
- *hp |= DSI_HDR_DATA2(0);
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len; /* 4 bytes */
-}
-
-static int dsi_cm_on(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_CM_ON);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len; /* 4 bytes */
-}
-
-static int dsi_cm_off(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_CM_OFF);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len; /* 4 bytes */
-}
-
-static int dsi_peripheral_on(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_PERIPHERAL_ON);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len; /* 4 bytes */
-}
-
-static int dsi_peripheral_off(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_PERIPHERAL_OFF);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len; /* 4 bytes */
-}
-
-static int dsi_set_max_pktsize(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- if (cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return 0;
- }
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_MAX_PKTSIZE);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(cm->payload[1]);
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len; /* 4 bytes */
-}
-
-static int dsi_null_pkt(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp = DSI_HDR_WC(dchdr->dlen);
- *hp |= DSI_HDR_LONG_PKT;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_NULL_PKT);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len; /* 4 bytes */
-}
-
-static int dsi_blank_pkt(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- u32 *hp;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp = DSI_HDR_WC(dchdr->dlen);
- *hp |= DSI_HDR_LONG_PKT;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_BLANK_PKT);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- return dp->len; /* 4 bytes */
-}
-
-/*
- * prepare cmd buffer to be txed
- */
-int dsi_cmd_dma_add(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- int len = 0;
- struct dsi_ctrl_hdr *dchdr = &cm->dchdr;
-
- switch (dchdr->dtype) {
- case DTYPE_GEN_WRITE:
- case DTYPE_GEN_WRITE1:
- case DTYPE_GEN_WRITE2:
- len = dsi_generic_swrite(dp, cm);
- break;
- case DTYPE_GEN_LWRITE:
- len = dsi_generic_lwrite(dp, cm);
- break;
- case DTYPE_GEN_READ:
- case DTYPE_GEN_READ1:
- case DTYPE_GEN_READ2:
- len = dsi_generic_read(dp, cm);
- break;
- case DTYPE_DCS_LWRITE:
- len = dsi_dcs_lwrite(dp, cm);
- break;
- case DTYPE_DCS_WRITE:
- len = dsi_dcs_swrite(dp, cm);
- break;
- case DTYPE_DCS_WRITE1:
- len = dsi_dcs_swrite1(dp, cm);
- break;
- case DTYPE_DCS_READ:
- len = dsi_dcs_read(dp, cm);
- break;
- case DTYPE_MAX_PKTSIZE:
- len = dsi_set_max_pktsize(dp, cm);
- break;
- case DTYPE_NULL_PKT:
- len = dsi_null_pkt(dp, cm);
- break;
- case DTYPE_BLANK_PKT:
- len = dsi_blank_pkt(dp, cm);
- break;
- case DTYPE_CM_ON:
- len = dsi_cm_on(dp, cm);
- break;
- case DTYPE_CM_OFF:
- len = dsi_cm_off(dp, cm);
- break;
- case DTYPE_PERIPHERAL_ON:
- len = dsi_peripheral_on(dp, cm);
- break;
- case DTYPE_PERIPHERAL_OFF:
- len = dsi_peripheral_off(dp, cm);
- break;
- default:
- pr_debug("%s: dtype=%x NOT supported\n",
- __func__, dchdr->dtype);
- break;
-
- }
-
- return len;
-}
-
-/*
- * mdss_dsi_short_read1_resp: 1 parameter
- */
-int dsi_short_read1_resp(struct dsi_buf *rp)
-{
- /* strip out dcs type */
- rp->data++;
- rp->len = 1;
- return rp->len;
-}
-
-/*
- * mdss_dsi_short_read2_resp: 2 parameter
- */
-int dsi_short_read2_resp(struct dsi_buf *rp)
-{
- /* strip out dcs type */
- rp->data++;
- rp->len = 2;
- return rp->len;
-}
-
-int dsi_long_read_resp(struct dsi_buf *rp)
-{
- short len;
-
- len = rp->data[2];
- len <<= 8;
- len |= rp->data[1];
- /* strip out dcs header */
- rp->data += 4;
- rp->len -= 4;
- /* strip out 2 bytes of checksum */
- rp->len -= 2;
- return len;
-}
diff --git a/drivers/video/msm/mdss/dsi_v2.h b/drivers/video/msm/mdss/dsi_v2.h
index e15f640..b8c91da 100644
--- a/drivers/video/msm/mdss/dsi_v2.h
+++ b/drivers/video/msm/mdss/dsi_v2.h
@@ -27,12 +27,8 @@
int (*on)(struct mdss_panel_data *pdata);
int (*off)(struct mdss_panel_data *pdata);
int (*cont_on)(struct mdss_panel_data *pdata);
+ int (*clk_ctrl)(struct mdss_panel_data *pdata, int enable);
void (*op_mode_config)(int mode, struct mdss_panel_data *pdata);
- int (*tx)(struct mdss_panel_data *pdata,
- struct dsi_buf *tp, struct dsi_cmd_desc *cmds, int cnt);
- int (*rx)(struct mdss_panel_data *pdata,
- struct dsi_buf *tp, struct dsi_buf *rp,
- struct dsi_cmd_desc *cmds, int len);
int index;
void *private;
};
@@ -42,26 +38,8 @@
void dsi_register_interface(struct dsi_interface *intf);
-int dsi_cmds_rx_v2(struct mdss_panel_data *pdata,
- struct dsi_buf *tp, struct dsi_buf *rp,
- struct dsi_cmd_desc *cmds, int len);
-
-int dsi_cmds_tx_v2(struct mdss_panel_data *pdata,
- struct dsi_buf *tp, struct dsi_cmd_desc *cmds,
- int cnt);
-
-char *dsi_buf_init(struct dsi_buf *dp);
-
int dsi_buf_alloc(struct dsi_buf *dp, int size);
-int dsi_cmd_dma_add(struct dsi_buf *dp, struct dsi_cmd_desc *cm);
-
-int dsi_short_read1_resp(struct dsi_buf *rp);
-
-int dsi_short_read2_resp(struct dsi_buf *rp);
-
-int dsi_long_read_resp(struct dsi_buf *rp);
-
void dsi_set_tx_power_mode(int mode);
void dsi_ctrl_config_deinit(struct platform_device *pdev,
diff --git a/drivers/video/msm/mdss/mdp3.c b/drivers/video/msm/mdss/mdp3.c
index c4986ef..3999db9 100644
--- a/drivers/video/msm/mdss/mdp3.c
+++ b/drivers/video/msm/mdss/mdp3.c
@@ -38,7 +38,7 @@
#include <linux/major.h>
#include <linux/bootmem.h>
#include <linux/memblock.h>
-
+#include <linux/iopoll.h>
#include <mach/board.h>
#include <mach/clk.h>
#include <mach/hardware.h>
@@ -55,6 +55,10 @@
#include "mdp3_ppp.h"
#include "mdss_debug.h"
+#define MISR_POLL_SLEEP 2000
+#define MISR_POLL_TIMEOUT 32000
+#define MDP3_REG_CAPTURED_DSI_PCLK_MASK 1
+
#define MDP_CORE_HW_VERSION 0x03040310
struct mdp3_hw_resource *mdp3_res;
@@ -1086,6 +1090,7 @@
static int mdp3_parse_dt(struct platform_device *pdev)
{
struct resource *res;
+ struct property *prop = NULL;
int rc;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mdp_phys");
@@ -1120,9 +1125,44 @@
return rc;
}
+ prop = of_find_property(pdev->dev.of_node, "batfet-supply", NULL);
+ mdp3_res->batfet_required = prop ? true : false;
+
return 0;
}
+void mdp3_batfet_ctrl(int enable)
+{
+ int rc;
+ if (!mdp3_res->batfet_required)
+ return;
+
+ if (!mdp3_res->batfet) {
+ if (enable) {
+ mdp3_res->batfet =
+ devm_regulator_get(&mdp3_res->pdev->dev,
+ "batfet");
+ if (IS_ERR_OR_NULL(mdp3_res->batfet)) {
+ pr_debug("unable to get batfet reg. rc=%d\n",
+ PTR_RET(mdp3_res->batfet));
+ mdp3_res->batfet = NULL;
+ return;
+ }
+ } else {
+ pr_debug("Batfet regulator disable w/o enable\n");
+ return;
+ }
+ }
+
+ if (enable)
+ rc = regulator_enable(mdp3_res->batfet);
+ else
+ rc = regulator_disable(mdp3_res->batfet);
+
+ if (rc < 0)
+ pr_err("%s: reg enable/disable failed", __func__);
+}
+
static void mdp3_iommu_heap_unmap_iommu(struct mdp3_iommu_meta *meta)
{
unsigned int domain_num;
@@ -1754,6 +1794,11 @@
return mdp3_res->domains[MDP3_DMA_IOMMU_DOMAIN].domain_idx;
}
+int mdp3_get_cont_spash_en(void)
+{
+ return mdp3_res->cont_splash_en;
+}
+
int mdp3_continuous_splash_copy(struct mdss_panel_data *pdata)
{
unsigned long splash_phys, phys;
@@ -1823,6 +1868,9 @@
pr_debug("mdp3__continuous_splash_on\n");
+ mdp3_clk_set_rate(MDP3_CLK_VSYNC, MDP_VSYNC_CLK_RATE,
+ MDP3_CLIENT_DMA_P);
+
rc = mdp3_clk_prepare();
if (rc) {
pr_err("fail to prepare clk\n");
@@ -1866,6 +1914,9 @@
mdp3_res->intf[MDP3_DMA_OUTPUT_SEL_DSI_VIDEO].active = 1;
else
mdp3_res->intf[MDP3_DMA_OUTPUT_SEL_DSI_CMD].active = 1;
+
+ mdp3_batfet_ctrl(true);
+ mdp3_res->cont_splash_en = 1;
return 0;
splash_on_err:
@@ -2001,6 +2052,105 @@
return rc;
}
+int mdp3_misr_get(struct mdp_misr *misr_resp)
+{
+ int result = 0, ret = -1;
+ int crc = 0;
+ pr_debug("%s CRC Capture on DSI\n", __func__);
+ switch (misr_resp->block_id) {
+ case DISPLAY_MISR_DSI0:
+ MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_EN, 0);
+ /* Sleep for one vsync after DSI video engine is disabled */
+ msleep(20);
+ /* Enable DSI_VIDEO_0 MISR Block */
+ MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x20);
+ /* Reset MISR Block */
+ MDP3_REG_WRITE(MDP3_REG_MISR_RESET_DSI_PCLK, 1);
+ /* Clear MISR capture done bit */
+ MDP3_REG_WRITE(MDP3_REG_CAPTURED_DSI_PCLK, 0);
+ /* Enable MDP DSI interface */
+ MDP3_REG_WRITE(MDP3_REG_DSI_VIDEO_EN, 1);
+ ret = readl_poll_timeout(mdp3_res->mdp_base +
+ MDP3_REG_CAPTURED_DSI_PCLK, result,
+ result & MDP3_REG_CAPTURED_DSI_PCLK_MASK,
+ MISR_POLL_SLEEP, MISR_POLL_TIMEOUT);
+ MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0);
+ if (ret == 0) {
+ /* Disable DSI MISR interface */
+ MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x0);
+ crc = MDP3_REG_READ(MDP3_REG_MISR_CAPT_VAL_DSI_PCLK);
+ pr_debug("CRC Val %d\n", crc);
+ } else {
+ pr_err("CRC Read Timed Out\n");
+ }
+ break;
+
+ case DISPLAY_MISR_DSI_CMD:
+ /* Select DSI PCLK Domain */
+ MDP3_REG_WRITE(MDP3_REG_SEL_CLK_OR_HCLK_TEST_BUS, 0x004);
+ /* Select Block id DSI_CMD */
+ MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x10);
+ /* Reset MISR Block */
+ MDP3_REG_WRITE(MDP3_REG_MISR_RESET_DSI_PCLK, 1);
+ /* Drive Data on Test Bus */
+ MDP3_REG_WRITE(MDP3_REG_EXPORT_MISR_DSI_PCLK, 0);
+ /* Kikk off DMA_P */
+ MDP3_REG_WRITE(MDP3_REG_DMA_P_START, 0x11);
+ /* Wait for DMA_P Done */
+ ret = readl_poll_timeout(mdp3_res->mdp_base +
+ MDP3_REG_INTR_STATUS, result,
+ result & MDP3_INTR_DMA_P_DONE_BIT,
+ MISR_POLL_SLEEP, MISR_POLL_TIMEOUT);
+ if (ret == 0) {
+ crc = MDP3_REG_READ(MDP3_REG_MISR_CURR_VAL_DSI_PCLK);
+ pr_debug("CRC Val %d\n", crc);
+ } else {
+ pr_err("CRC Read Timed Out\n");
+ }
+ break;
+
+ default:
+ pr_err("%s CRC Capture not supported\n", __func__);
+ ret = -EINVAL;
+ break;
+ }
+
+ misr_resp->crc_value[0] = crc;
+ pr_debug("%s, CRC Capture on DSI Param Block = 0x%x, CRC 0x%x\n",
+ __func__, misr_resp->block_id, misr_resp->crc_value[0]);
+ return ret;
+}
+
+int mdp3_misr_set(struct mdp_misr *misr_req)
+{
+ int ret = 0;
+ pr_debug("%s Parameters Block = %d Cframe Count = %d CRC = %d\n",
+ __func__, misr_req->block_id, misr_req->frame_count,
+ misr_req->crc_value[0]);
+
+ switch (misr_req->block_id) {
+ case DISPLAY_MISR_DSI0:
+ pr_debug("In the case DISPLAY_MISR_DSI0\n");
+ MDP3_REG_WRITE(MDP3_REG_SEL_CLK_OR_HCLK_TEST_BUS, 1);
+ MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x20);
+ MDP3_REG_WRITE(MDP3_REG_MISR_RESET_DSI_PCLK, 0x1);
+ break;
+
+ case DISPLAY_MISR_DSI_CMD:
+ pr_debug("In the case DISPLAY_MISR_DSI_CMD\n");
+ MDP3_REG_WRITE(MDP3_REG_SEL_CLK_OR_HCLK_TEST_BUS, 1);
+ MDP3_REG_WRITE(MDP3_REG_MODE_DSI_PCLK, 0x10);
+ MDP3_REG_WRITE(MDP3_REG_MISR_RESET_DSI_PCLK, 0x1);
+ break;
+
+ default:
+ pr_err("%s CRC Capture not supported\n", __func__);
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
static int mdp3_probe(struct platform_device *pdev)
{
int rc;
@@ -2118,11 +2268,13 @@
static int mdp3_suspend_sub(struct mdp3_hw_resource *mdata)
{
+ mdp3_batfet_ctrl(false);
return 0;
}
static int mdp3_resume_sub(struct mdp3_hw_resource *mdata)
{
+ mdp3_batfet_ctrl(true);
return 0;
}
diff --git a/drivers/video/msm/mdss/mdp3.h b/drivers/video/msm/mdss/mdp3.h
index e0dd021..28997ec 100644
--- a/drivers/video/msm/mdss/mdp3.h
+++ b/drivers/video/msm/mdss/mdp3.h
@@ -25,6 +25,8 @@
#include "mdp3_dma.h"
#include "mdss_fb.h"
+#define MDP_VSYNC_CLK_RATE 19200000
+
enum {
MDP3_CLK_AHB,
MDP3_CLK_CORE,
@@ -154,6 +156,10 @@
u32 splash_mem_size;
int clk_prepare_count;
+ int cont_splash_en;
+
+ bool batfet_required;
+ struct regulator *batfet;
};
struct mdp3_img_data {
@@ -191,8 +197,13 @@
int mdp3_parse_dt_splash(struct msm_fb_data_type *mfd);
void mdp3_release_splash_memory(void);
int mdp3_create_sysfs_link(struct device *dev);
+int mdp3_get_cont_spash_en(void);
int mdp3_get_mdp_dsi_clk(void);
int mdp3_put_mdp_dsi_clk(void);
+void mdp3_batfet_ctrl(int enable);
+
+int mdp3_misr_set(struct mdp_misr *misr_req);
+int mdp3_misr_get(struct mdp_misr *misr_resp);
#define MDP3_REG_WRITE(addr, val) writel_relaxed(val, mdp3_res->mdp_base + addr)
#define MDP3_REG_READ(addr) readl_relaxed(mdp3_res->mdp_base + addr)
diff --git a/drivers/video/msm/mdss/mdp3_ctrl.c b/drivers/video/msm/mdss/mdp3_ctrl.c
index de4e9a1..4537845 100644
--- a/drivers/video/msm/mdss/mdp3_ctrl.c
+++ b/drivers/video/msm/mdss/mdp3_ctrl.c
@@ -26,12 +26,15 @@
#include "mdp3_ppp.h"
#define MDP_CORE_CLK_RATE 100000000
-#define MDP_VSYNC_CLK_RATE 19200000
+#define VSYNC_EXPIRE_TICK 4
static void mdp3_ctrl_pan_display(struct msm_fb_data_type *mfd);
static int mdp3_overlay_unset(struct msm_fb_data_type *mfd, int ndx);
static int mdp3_histogram_stop(struct mdp3_session_data *session,
u32 block);
+static int mdp3_ctrl_clk_enable(struct msm_fb_data_type *mfd, int enable);
+static int mdp3_ctrl_vsync_enable(struct msm_fb_data_type *mfd, int enable);
+static int mdp3_ctrl_get_intf_type(struct msm_fb_data_type *mfd);
static void mdp3_bufq_init(struct mdp3_buffer_queue *bufq)
{
@@ -88,6 +91,29 @@
return bufq->count;
}
+static void mdp3_dispatch_clk_off(struct work_struct *work)
+{
+ struct mdp3_session_data *session;
+
+ pr_debug("%s\n", __func__);
+ session = container_of(work, struct mdp3_session_data,
+ clk_off_work);
+ if (!session)
+ return;
+
+ mutex_lock(&session->lock);
+ if (session->vsync_enabled ||
+ atomic_read(&session->vsync_countdown) != 0) {
+ mutex_unlock(&session->lock);
+ pr_debug("Ignoring clk shut down\n");
+ return;
+ }
+
+ mdp3_ctrl_vsync_enable(session->mfd, 0);
+ mdp3_ctrl_clk_enable(session->mfd, 0);
+ mutex_unlock(&session->lock);
+}
+
void vsync_notify_handler(void *arg)
{
struct mdp3_session_data *session = (struct mdp3_session_data *)arg;
@@ -95,6 +121,22 @@
sysfs_notify_dirent(session->vsync_event_sd);
}
+void vsync_count_down(void *arg)
+{
+ struct mdp3_session_data *session = (struct mdp3_session_data *)arg;
+ /* We are counting down to turn off clocks */
+ atomic_dec(&session->vsync_countdown);
+ if (atomic_read(&session->vsync_countdown) == 0)
+ schedule_work(&session->clk_off_work);
+}
+
+void mdp3_ctrl_reset_countdown(struct mdp3_session_data *session,
+ struct msm_fb_data_type *mfd)
+{
+ if (mdp3_ctrl_get_intf_type(mfd) == MDP3_DMA_OUTPUT_SEL_DSI_CMD)
+ atomic_set(&session->vsync_countdown, VSYNC_EXPIRE_TICK);
+}
+
static int mdp3_ctrl_vsync_enable(struct msm_fb_data_type *mfd, int enable)
{
struct mdp3_session_data *mdp3_session;
@@ -115,26 +157,44 @@
vsync_client.handler = vsync_notify_handler;
vsync_client.arg = mdp3_session;
arg = &vsync_client;
+ } else if (atomic_read(&mdp3_session->vsync_countdown)) {
+ /*
+ * Now that vsync is no longer needed we will
+ * shutdown dsi clocks as soon as cnt down == 0
+ * for cmd mode panels
+ */
+ vsync_client.handler = vsync_count_down;
+ vsync_client.arg = mdp3_session;
+ arg = &vsync_client;
+ enable = 1;
}
- mutex_lock(&mdp3_session->lock);
mdp3_clk_enable(1, 0);
mdp3_session->dma->vsync_enable(mdp3_session->dma, arg);
mdp3_clk_enable(0, 0);
- if (enable && mdp3_session->status == 1 && !mdp3_session->intf->active)
+
+ /*
+ * Need to fake vsync whenever dsi interface is not
+ * active or when dsi clocks are currently off
+ */
+ if (enable && mdp3_session->status == 1
+ && mdp3_session->vsync_before_commit) {
mod_timer(&mdp3_session->vsync_timer,
jiffies + msecs_to_jiffies(mdp3_session->vsync_period));
- else if (!enable)
+ } else if (enable && !mdp3_session->clk_on) {
+ mdp3_ctrl_reset_countdown(mdp3_session, mfd);
+ mdp3_ctrl_clk_enable(mfd, 1);
+ } else if (!enable) {
del_timer(&mdp3_session->vsync_timer);
+ }
- mutex_unlock(&mdp3_session->lock);
return 0;
}
void mdp3_vsync_timer_func(unsigned long arg)
{
struct mdp3_session_data *session = (struct mdp3_session_data *)arg;
- if (session->status == 1 && !session->intf->active) {
+ if (session->status == 1 && session->vsync_before_commit) {
pr_debug("mdp3_vsync_timer_func trigger\n");
vsync_notify_handler(session);
mod_timer(&session->vsync_timer,
@@ -211,6 +271,33 @@
.attrs = vsync_fs_attrs,
};
+static int mdp3_ctrl_clk_enable(struct msm_fb_data_type *mfd, int enable)
+{
+ struct mdp3_session_data *session;
+ struct mdss_panel_data *panel;
+ int rc = 0;
+
+ pr_debug("mdp3_ctrl_clk_enable %d\n", enable);
+
+ session = mfd->mdp.private1;
+ panel = session->panel;
+
+ if (!panel->event_handler)
+ return 0;
+
+ if ((enable && session->clk_on == 0) ||
+ (!enable && session->clk_on == 1)) {
+ rc = panel->event_handler(panel,
+ MDSS_EVENT_PANEL_CLK_CTRL, (void *)enable);
+ rc |= mdp3_clk_enable(enable, 1);
+ } else {
+ pr_debug("enable = %d, clk_on=%d\n", enable, session->clk_on);
+ }
+
+ session->clk_on = enable;
+ return rc;
+}
+
static int mdp3_ctrl_res_req_bus(struct msm_fb_data_type *mfd, int status)
{
int rc = 0;
@@ -439,6 +526,8 @@
goto on_error;
}
+ mdp3_batfet_ctrl(true);
+
rc = mdp3_iommu_enable(MDP3_CLIENT_DMA_P);
if (rc) {
pr_err("fail to attach MDP DMA SMMU\n");
@@ -487,6 +576,7 @@
goto on_error;
}
+ mdp3_session->clk_on = 1;
pr_debug("mdp3_ctrl_on dma start\n");
if (mfd->fbi->screen_base) {
rc = mdp3_session->dma->start(mdp3_session->dma,
@@ -523,15 +613,12 @@
panel = mdp3_session->panel;
mutex_lock(&mdp3_session->lock);
- if (panel && panel->set_backlight)
- panel->set_backlight(panel, 0);
-
if (!mdp3_session->status) {
pr_debug("fb%d is off already", mfd->index);
goto off_error;
}
- mdp3_clk_enable(1, 0);
+ mdp3_ctrl_clk_enable(mfd, 1);
mdp3_histogram_stop(mdp3_session, MDP_BLOCK_DMA_P);
@@ -539,7 +626,6 @@
if (rc)
pr_debug("fail to stop the MDP3 dma\n");
- mdp3_clk_enable(0, 0);
if (panel->event_handler)
rc = panel->event_handler(panel, MDSS_EVENT_PANEL_OFF, NULL);
@@ -549,15 +635,19 @@
mdp3_irq_deregister();
pr_debug("mdp3_ctrl_off stop clock\n");
- rc = mdp3_ctrl_res_req_clk(mfd, 0);
- if (rc)
- pr_err("mdp clock resource release failed\n");
+ if (mdp3_session->clk_on) {
+ rc = mdp3_clk_enable(0, 1);
+ if (rc)
+ pr_err("mdp clock resource release failed\n");
- pr_debug("mdp3_ctrl_off stop dsi controller\n");
- if (panel->event_handler)
- rc = panel->event_handler(panel, MDSS_EVENT_BLANK, NULL);
- if (rc)
- pr_err("fail to turn off the panel\n");
+ pr_debug("mdp3_ctrl_off stop dsi controller\n");
+ if (panel->event_handler)
+ rc = panel->event_handler(panel,
+ MDSS_EVENT_BLANK, NULL);
+ if (rc)
+ pr_err("fail to turn off the panel\n");
+ }
+ mdp3_clk_unprepare();
pr_debug("mdp3_ctrl_off release bus\n");
rc = mdp3_ctrl_res_req_bus(mfd, 0);
@@ -568,6 +658,10 @@
if (rc)
pr_err("fail to dettach MDP DMA SMMU\n");
+ mdp3_batfet_ctrl(false);
+ mdp3_session->vsync_enabled = 0;
+ atomic_set(&mdp3_session->vsync_countdown, 0);
+ mdp3_session->clk_on = 0;
off_error:
mdp3_session->status = 0;
mdp3_bufq_deinit(&mdp3_session->bufq_out);
@@ -741,6 +835,14 @@
{
int rc = 0;
struct mdp3_session_data *mdp3_session = mfd->mdp.private1;
+ struct fb_var_screeninfo *var;
+ struct fb_fix_screeninfo *fix;
+ struct fb_info *fbi = mfd->fbi;
+ int stride;
+
+ fix = &fbi->fix;
+ var = &fbi->var;
+ stride = req->src.width * var->bits_per_pixel/8;
mutex_lock(&mdp3_session->lock);
@@ -749,6 +851,9 @@
mdp3_session->overlay = *req;
if (req->id == MSMFB_NEW_REQUEST) {
+ if (fix->line_length != stride)
+ mdp3_session->dma->config_stride(
+ mdp3_session->dma, stride);
mdp3_session->overlay.id = 1;
req->id = 1;
}
@@ -762,10 +867,15 @@
{
int rc = 0;
struct mdp3_session_data *mdp3_session = mfd->mdp.private1;
+ struct fb_info *fbi = mfd->fbi;
+ struct fb_fix_screeninfo *fix;
+ fix = &fbi->fix;
mutex_lock(&mdp3_session->lock);
if (mdp3_session->overlay.id == ndx && ndx == 1) {
+ mdp3_session->dma->config_stride(mdp3_session->dma,
+ fix->line_length);
mdp3_session->overlay.id = MSMFB_NEW_REQUEST;
mdp3_bufq_deinit(&mdp3_session->bufq_in);
} else {
@@ -861,11 +971,11 @@
data = mdp3_bufq_pop(&mdp3_session->bufq_in);
if (data) {
- mdp3_clk_enable(1, 0);
+ mdp3_ctrl_reset_countdown(mdp3_session, mfd);
+ mdp3_ctrl_clk_enable(mfd, 1);
mdp3_session->dma->update(mdp3_session->dma,
(void *)data->addr,
mdp3_session->intf);
- mdp3_clk_enable(0, 0);
mdp3_bufq_push(&mdp3_session->bufq_out, data);
}
@@ -879,6 +989,8 @@
msleep(1000 / panel_info->mipi.frame_rate);
mdp3_session->first_commit = false;
}
+
+ mdp3_session->vsync_before_commit = 0;
if (reset_done && (panel && panel->set_backlight))
panel->set_backlight(panel, panel->panel_info.bl_max);
@@ -930,16 +1042,18 @@
goto pan_error;
}
- mdp3_clk_enable(1, 0);
if (mfd->fbi->screen_base) {
+ mdp3_ctrl_reset_countdown(mdp3_session, mfd);
+ mdp3_ctrl_clk_enable(mfd, 1);
mdp3_session->dma->update(mdp3_session->dma,
(void *)mfd->iova + offset,
mdp3_session->intf);
} else {
pr_debug("mdp3_ctrl_pan_display no memory, stop interface");
+ mdp3_clk_enable(1, 0);
mdp3_session->dma->stop(mdp3_session->dma, mdp3_session->intf);
+ mdp3_clk_enable(0, 0);
}
- mdp3_clk_enable(0, 0);
if (mdp3_session->first_commit) {
/*wait for one frame time to ensure frame is sent to panel*/
@@ -947,10 +1061,28 @@
mdp3_session->first_commit = false;
}
+ mdp3_session->vsync_before_commit = 0;
+
pan_error:
mutex_unlock(&mdp3_session->lock);
}
+static int mdp3_set_metadata(struct msm_fb_data_type *mfd,
+ struct msmfb_metadata *metadata_ptr)
+{
+ int ret = 0;
+ switch (metadata_ptr->op) {
+ case metadata_op_crc:
+ ret = mdp3_misr_set(&metadata_ptr->data.misr_request);
+ break;
+ default:
+ pr_warn("Unsupported request to MDP SET META IOCTL.\n");
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
static int mdp3_get_metadata(struct msm_fb_data_type *mfd,
struct msmfb_metadata *metadata)
{
@@ -966,8 +1098,11 @@
metadata->data.caps.vig_pipes = 0;
metadata->data.caps.dma_pipes = 1;
break;
+ case metadata_op_crc:
+ ret = mdp3_misr_get(&metadata->data.misr_request);
+ break;
default:
- pr_warn("Unsupported request to MDP META IOCTL.\n");
+ pr_warn("Unsupported request to MDP GET META IOCTL.\n");
ret = -EINVAL;
break;
}
@@ -1084,8 +1219,7 @@
session->histo_status = 1;
histogram_start_err:
- if (ret)
- mdp3_clk_enable(0, 0);
+ mdp3_clk_enable(0, 0);
mutex_unlock(&session->histo_lock);
return ret;
}
@@ -1108,6 +1242,7 @@
goto histogram_stop_err;
}
+ mdp3_clk_enable(1, 0);
ret = session->dma->histo_op(session->dma, MDP3_DMA_HISTO_OP_CANCEL);
mdp3_clk_enable(0, 0);
if (ret)
@@ -1126,11 +1261,17 @@
int ret;
struct mdp3_dma_histogram_data *mdp3_histo;
+ pr_debug("%s\n", __func__);
if (!session->dma->get_histo) {
pr_err("mdp3_histogram_collect not supported\n");
return -EINVAL;
}
+ if (!session->clk_on) {
+ pr_debug("mdp/dsi clock off currently\n");
+ return -EPERM;
+ }
+
mutex_lock(&session->histo_lock);
if (!session->histo_status) {
@@ -1141,7 +1282,9 @@
mutex_unlock(&session->histo_lock);
+ mdp3_clk_enable(1, 0);
ret = session->dma->get_histo(session->dma);
+ mdp3_clk_enable(0, 0);
if (ret) {
pr_debug("mdp3_histogram_collect error = %d\n", ret);
return ret;
@@ -1414,7 +1557,10 @@
case MSMFB_VSYNC_CTRL:
case MSMFB_OVERLAY_VSYNC_CTRL:
if (!copy_from_user(&val, argp, sizeof(val))) {
+ mutex_lock(&mdp3_session->lock);
+ mdp3_session->vsync_enabled = val;
rc = mdp3_ctrl_vsync_enable(mfd, val);
+ mutex_unlock(&mdp3_session->lock);
} else {
pr_err("MSMFB_OVERLAY_VSYNC_CTRL failed\n");
rc = -EFAULT;
@@ -1428,11 +1574,19 @@
break;
case MSMFB_METADATA_GET:
rc = copy_from_user(&metadata, argp, sizeof(metadata));
- if (rc)
- return rc;
- rc = mdp3_get_metadata(mfd, &metadata);
+ if (!rc)
+ rc = mdp3_get_metadata(mfd, &metadata);
if (!rc)
rc = copy_to_user(argp, &metadata, sizeof(metadata));
+ if (rc)
+ pr_err("mdp3_get_metadata failed (%d)\n", rc);
+ break;
+ case MSMFB_METADATA_SET:
+ rc = copy_from_user(&metadata, argp, sizeof(metadata));
+ if (!rc)
+ rc = mdp3_set_metadata(mfd, &metadata);
+ if (rc)
+ pr_err("mdp3_set_metadata failed (%d)\n", rc);
break;
case MSMFB_OVERLAY_GET:
rc = copy_from_user(req, argp, sizeof(*req));
@@ -1503,6 +1657,8 @@
}
memset(mdp3_session, 0, sizeof(struct mdp3_session_data));
mutex_init(&mdp3_session->lock);
+ INIT_WORK(&mdp3_session->clk_off_work, mdp3_dispatch_clk_off);
+ atomic_set(&mdp3_session->vsync_countdown, 0);
mutex_init(&mdp3_session->histo_lock);
mdp3_session->dma = mdp3_get_dma_pipe(MDP3_DMA_CAP_ALL);
if (!mdp3_session->dma) {
@@ -1570,6 +1726,10 @@
mdp3_ctrl_off(mfd);
}
+ if (mdp3_get_cont_spash_en())
+ mdp3_session->clk_on = 1;
+
+ mdp3_session->vsync_before_commit = true;
init_done:
if (IS_ERR_VALUE(rc))
kfree(mdp3_session);
diff --git a/drivers/video/msm/mdss/mdp3_ctrl.h b/drivers/video/msm/mdss/mdp3_ctrl.h
index 66ed3d5..f2484ef 100644
--- a/drivers/video/msm/mdss/mdp3_ctrl.h
+++ b/drivers/video/msm/mdss/mdp3_ctrl.h
@@ -48,11 +48,17 @@
struct mdp_overlay req_overlay;
struct mdp3_buffer_queue bufq_in;
struct mdp3_buffer_queue bufq_out;
+ struct work_struct clk_off_work;
int histo_status;
struct mutex histo_lock;
int lut_sel;
int cc_vect_sel;
+ bool vsync_before_commit;
bool first_commit;
+ int clk_on;
+
+ int vsync_enabled;
+ atomic_t vsync_countdown; /* Used to count down */
};
int mdp3_ctrl_init(struct msm_fb_data_type *mfd);
diff --git a/drivers/video/msm/mdss/mdp3_dma.c b/drivers/video/msm/mdss/mdp3_dma.c
index 3a2c94b..2ebcb8a 100644
--- a/drivers/video/msm/mdss/mdp3_dma.c
+++ b/drivers/video/msm/mdss/mdp3_dma.c
@@ -268,6 +268,23 @@
return 0;
}
+static void mdp3_dma_stride_config(struct mdp3_dma *dma, int stride)
+{
+ struct mdp3_dma_source *source_config;
+ u32 dma_stride_offset;
+
+ if (dma->dma_sel == MDP3_DMA_P)
+ dma_stride_offset = MDP3_REG_DMA_P_IBUF_Y_STRIDE;
+ else
+ dma_stride_offset = MDP3_REG_DMA_S_IBUF_Y_STRIDE;
+
+ source_config = &dma->source_config;
+ source_config->stride = stride;
+ pr_debug("%s: Update the fb stride for DMA to %d", __func__,
+ (u32)source_config->stride);
+ MDP3_REG_WRITE(dma_stride_offset, source_config->stride);
+}
+
static int mdp3_dmap_config(struct mdp3_dma *dma,
struct mdp3_dma_source *source_config,
struct mdp3_dma_output_config *output_config)
@@ -855,6 +872,7 @@
dma->vsync_enable = mdp3_dma_vsync_enable;
dma->start = mdp3_dma_start;
dma->stop = mdp3_dma_stop;
+ dma->config_stride = mdp3_dma_stride_config;
break;
case MDP3_DMA_S:
dma->dma_config = mdp3_dmas_config;
@@ -869,6 +887,7 @@
dma->vsync_enable = mdp3_dma_vsync_enable;
dma->start = mdp3_dma_start;
dma->stop = mdp3_dma_stop;
+ dma->config_stride = mdp3_dma_stride_config;
break;
case MDP3_DMA_E:
default:
diff --git a/drivers/video/msm/mdss/mdp3_dma.h b/drivers/video/msm/mdss/mdp3_dma.h
index 6983e55..9d439ad 100644
--- a/drivers/video/msm/mdss/mdp3_dma.h
+++ b/drivers/video/msm/mdss/mdp3_dma.h
@@ -287,6 +287,8 @@
int (*histo_op)(struct mdp3_dma *dma, u32 op);
+ void (*config_stride)(struct mdp3_dma *dma, int stride);
+
void (*vsync_enable)(struct mdp3_dma *dma,
struct mdp3_vsync_notification *vsync_client);
};
diff --git a/drivers/video/msm/mdss/mdp3_hwio.h b/drivers/video/msm/mdss/mdp3_hwio.h
index 8846ec5..b457c10 100644
--- a/drivers/video/msm/mdss/mdp3_hwio.h
+++ b/drivers/video/msm/mdss/mdp3_hwio.h
@@ -55,6 +55,7 @@
#define MDP3_REG_HW_VERSION 0x0070
#define MDP3_REG_SW_RESET 0x0074
+#define MDP3_REG_SEL_CLK_OR_HCLK_TEST_BUS 0x007C
/*EBI*/
#define MDP3_REG_EBI2_LCD0 0x003c
@@ -117,6 +118,46 @@
#define MDP3_REG_DMA_S_IBUF_Y_STRIDE 0xA000C
#define MDP3_REG_DMA_S_OUT_XY 0xA0010
+/*MISR*/
+#define MDP3_REG_MODE_CLK 0x000D0000
+#define MDP3_REG_MISR_RESET_CLK 0x000D0004
+#define MDP3_REG_EXPORT_MISR_CLK 0x000D0008
+#define MDP3_REG_MISR_CURR_VAL_CLK 0x000D000C
+#define MDP3_REG_MODE_HCLK 0x000D0100
+#define MDP3_REG_MISR_RESET_HCLK 0x000D0104
+#define MDP3_REG_EXPORT_MISR_HCLK 0x000D0108
+#define MDP3_REG_MISR_CURR_VAL_HCLK 0x000D010C
+#define MDP3_REG_MODE_DCLK 0x000D0200
+#define MDP3_REG_MISR_RESET_DCLK 0x000D0204
+#define MDP3_REG_EXPORT_MISR_DCLK 0x000D0208
+#define MDP3_REG_MISR_CURR_VAL_DCLK 0x000D020C
+#define MDP3_REG_CAPTURED_DCLK 0x000D0210
+#define MDP3_REG_MISR_CAPT_VAL_DCLK 0x000D0214
+#define MDP3_REG_MODE_TVCLK 0x000D0300
+#define MDP3_REG_MISR_RESET_TVCLK 0x000D0304
+#define MDP3_REG_EXPORT_MISR_TVCLK 0x000D0308
+#define MDP3_REG_MISR_CURR_VAL_TVCLK 0x000D030C
+#define MDP3_REG_CAPTURED_TVCLK 0x000D0310
+#define MDP3_REG_MISR_CAPT_VAL_TVCLK 0x000D0314
+
+/* Select DSI operation type(CMD/VIDEO) */
+#define MDP3_REG_MODE_DSI_PCLK 0x000D0400
+#define MDP3_REG_MODE_DSI_PCLK_BLOCK_DSI_CMD 0x10
+#define MDP3_REG_MODE_DSI_PCLK_BLOCK_DSI_VIDEO1 0x20
+#define MDP3_REG_MODE_DSI_PCLK_BLOCK_DSI_VIDEO2 0x30
+/* RESET DSI MISR STATE */
+#define MDP3_REG_MISR_RESET_DSI_PCLK 0x000D0404
+
+/* For reading MISR State(1) and driving data on test bus(0) */
+#define MDP3_REG_EXPORT_MISR_DSI_PCLK 0x000D0408
+/* Read MISR signature */
+#define MDP3_REG_MISR_CURR_VAL_DSI_PCLK 0x000D040C
+
+/* MISR status Bit0 (1) Capture Done */
+#define MDP3_REG_CAPTURED_DSI_PCLK 0x000D0410
+#define MDP3_REG_MISR_CAPT_VAL_DSI_PCLK 0x000D0414
+#define MDP3_REG_MISR_TESTBUS_CAPT_VAL 0x000D0600
+
/*interface*/
#define MDP3_REG_LCDC_EN 0xE0000
#define MDP3_REG_LCDC_HSYNC_CTL 0xE0004
diff --git a/drivers/video/msm/mdss/mdp3_ppp.c b/drivers/video/msm/mdss/mdp3_ppp.c
index 6187db4..d778af8 100644
--- a/drivers/video/msm/mdss/mdp3_ppp.c
+++ b/drivers/video/msm/mdss/mdp3_ppp.c
@@ -412,12 +412,47 @@
mdp3_ppp_kickoff();
}
-static void mdp3_ppp_process_req(struct ppp_blit_op *blit_op,
+static int solid_fill_workaround(struct mdp_blit_req *req,
+ struct ppp_blit_op *blit_op)
+{
+ /* Make width 2 when there is a solid fill of width 1, and make
+ sure width does not become zero while trying to avoid odd width */
+ if (blit_op->dst.roi.width == 1) {
+ if (req->dst_rect.x + 2 > req->dst.width) {
+ pr_err("%s: Unable to handle solid fill of width 1",
+ __func__);
+ return -EINVAL;
+ }
+ blit_op->dst.roi.width = 2;
+ }
+ if (blit_op->src.roi.width == 1) {
+ if (req->src_rect.x + 2 > req->src.width) {
+ pr_err("%s: Unable to handle solid fill of width 1",
+ __func__);
+ return -EINVAL;
+ }
+ blit_op->src.roi.width = 2;
+ }
+
+ /* Avoid odd width, as it could hang ppp during solid fill */
+ blit_op->dst.roi.width = (blit_op->dst.roi.width / 2) * 2;
+ blit_op->src.roi.width = (blit_op->src.roi.width / 2) * 2;
+
+ /* Avoid RGBA format, as it could hang ppp during solid fill */
+ if (blit_op->src.color_fmt == MDP_RGBA_8888)
+ blit_op->src.color_fmt = MDP_RGBX_8888;
+ if (blit_op->dst.color_fmt == MDP_RGBA_8888)
+ blit_op->dst.color_fmt = MDP_RGBX_8888;
+ return 0;
+}
+
+static int mdp3_ppp_process_req(struct ppp_blit_op *blit_op,
struct mdp_blit_req *req, struct mdp3_img_data *src_data,
struct mdp3_img_data *dst_data)
{
unsigned long srcp0_start, srcp0_len, dst_start, dst_len;
uint32_t dst_width, dst_height;
+ int ret = 0;
srcp0_start = (unsigned long) src_data->addr;
srcp0_len = (unsigned long) src_data->len;
@@ -510,24 +545,19 @@
blit_op->mdp_op |= MDPOP_ASCALE | MDPOP_BLUR;
if (req->flags & MDP_SOLID_FILL) {
- blit_op->solid_fill = true;
+ ret = solid_fill_workaround(req, blit_op);
+ if (ret)
+ return ret;
- /* Avoid odd width, as it could hang ppp during solid fill */
- blit_op->dst.roi.width = (blit_op->dst.roi.width / 2) * 2;
- blit_op->src.roi.width = (blit_op->src.roi.width / 2) * 2;
-
- /* Avoid RGBA format, as it could hang ppp during solid fill */
- if (blit_op->src.color_fmt == MDP_RGBA_8888)
- blit_op->src.color_fmt = MDP_RGBX_8888;
- if (blit_op->dst.color_fmt == MDP_RGBA_8888)
- blit_op->dst.color_fmt = MDP_RGBX_8888;
blit_op->solid_fill_color = (req->const_color.g & 0xFF)|
- (req->const_color.b & 0xFF) << 8 |
- (req->const_color.r & 0xFF) << 16 |
+ (req->const_color.r & 0xFF) << 8 |
+ (req->const_color.b & 0xFF) << 16 |
(req->const_color.alpha & 0xFF) << 24;
+ blit_op->solid_fill = true;
} else {
blit_op->solid_fill = false;
}
+ return ret;
}
static void mdp3_ppp_tile_workaround(struct ppp_blit_op *blit_op,
@@ -626,6 +656,7 @@
struct mdp3_img_data *dst_data)
{
struct ppp_blit_op blit_op;
+ int ret = 0;
memset(&blit_op, 0, sizeof(blit_op));
@@ -639,7 +670,11 @@
return -EINVAL;
}
- mdp3_ppp_process_req(&blit_op, req, src_data, dst_data);
+ ret = mdp3_ppp_process_req(&blit_op, req, src_data, dst_data);
+ if (ret) {
+ pr_err("%s: Failed to process the blit request", __func__);
+ return ret;
+ }
if (((blit_op.mdp_op & (MDPOP_TRANSP | MDPOP_ALPHAB)) ||
(req->src.format == MDP_ARGB_8888) ||
diff --git a/drivers/video/msm/mdss/mdss.h b/drivers/video/msm/mdss/mdss.h
index 61c4acd..ce4005e 100644
--- a/drivers/video/msm/mdss/mdss.h
+++ b/drivers/video/msm/mdss/mdss.h
@@ -66,6 +66,19 @@
void (*debug_enable_clock)(int on);
};
+#define MDSS_IRQ_SUSPEND -1
+#define MDSS_IRQ_RESUME 1
+#define MDSS_IRQ_REQ 0
+
+struct mdss_intr {
+ /* requested intr */
+ u32 req;
+ /* currently enabled intr */
+ u32 curr;
+ int state;
+ spinlock_t lock;
+};
+
struct mdss_data_type {
u32 mdp_rev;
struct clk *mdp_clk[MDSS_MAX_CLK];
@@ -107,6 +120,9 @@
u32 rot_block_size;
+ u32 max_bw_low;
+ u32 max_bw_high;
+
struct mdss_hw_settings *hw_settings;
struct mdss_mdp_pipe *vig_pipes;
@@ -130,10 +146,14 @@
u32 nintf;
u32 pp_bus_hdl;
+ struct mdss_mdp_ad *ad_off;
struct mdss_ad_info *ad_cfgs;
u32 nad_cfgs;
+ u32 nmax_concurrent_ad_hw;
struct workqueue_struct *ad_calc_wq;
+ struct mdss_intr hist_intr;
+
struct ion_client *iclient;
int iommu_attached;
struct mdss_iommu_map_type *iommu_map;
diff --git a/drivers/video/msm/mdss/mdss_debug.c b/drivers/video/msm/mdss/mdss_debug.c
index f933c8e..0d0240f 100644
--- a/drivers/video/msm/mdss/mdss_debug.c
+++ b/drivers/video/msm/mdss/mdss_debug.c
@@ -23,12 +23,13 @@
#include "mdss.h"
#include "mdss_mdp.h"
+#include "mdss_mdp_hwio.h"
#include "mdss_debug.h"
#define DEFAULT_BASE_REG_CNT 0x100
#define GROUP_BYTES 4
#define ROW_BYTES 16
-
+#define MAX_VSYNC_COUNT 0xFFFFFFF
struct mdss_debug_data {
struct dentry *root;
struct list_head base_list;
@@ -409,28 +410,63 @@
return 0;
}
+int vsync_count;
static struct mdss_mdp_misr_map {
u32 ctrl_reg;
u32 value_reg;
u32 crc_op_mode;
u32 crc_index;
- u32 crc_value[MISR_CRC_BATCH_SIZE];
+ bool use_ping;
+ bool is_ping_full;
+ bool is_pong_full;
+ struct mutex crc_lock;
+ u32 crc_ping[MISR_CRC_BATCH_SIZE];
+ u32 crc_pong[MISR_CRC_BATCH_SIZE];
} mdss_mdp_misr_table[DISPLAY_MISR_MAX] = {
[DISPLAY_MISR_DSI0] = {
.ctrl_reg = MDSS_MDP_LP_MISR_CTRL_DSI0,
.value_reg = MDSS_MDP_LP_MISR_SIGN_DSI0,
+ .crc_op_mode = 0,
+ .crc_index = 0,
+ .use_ping = true,
+ .is_ping_full = false,
+ .is_pong_full = false,
},
[DISPLAY_MISR_DSI1] = {
.ctrl_reg = MDSS_MDP_LP_MISR_CTRL_DSI1,
.value_reg = MDSS_MDP_LP_MISR_SIGN_DSI1,
+ .crc_op_mode = 0,
+ .crc_index = 0,
+ .use_ping = true,
+ .is_ping_full = false,
+ .is_pong_full = false,
},
[DISPLAY_MISR_EDP] = {
.ctrl_reg = MDSS_MDP_LP_MISR_CTRL_EDP,
.value_reg = MDSS_MDP_LP_MISR_SIGN_EDP,
+ .crc_op_mode = 0,
+ .crc_index = 0,
+ .use_ping = true,
+ .is_ping_full = false,
+ .is_pong_full = false,
},
[DISPLAY_MISR_HDMI] = {
.ctrl_reg = MDSS_MDP_LP_MISR_CTRL_HDMI,
.value_reg = MDSS_MDP_LP_MISR_SIGN_HDMI,
+ .crc_op_mode = 0,
+ .crc_index = 0,
+ .use_ping = true,
+ .is_ping_full = false,
+ .is_pong_full = false,
+ },
+ [DISPLAY_MISR_MDP] = {
+ .ctrl_reg = MDSS_MDP_LP_MISR_CTRL_MDP,
+ .value_reg = MDSS_MDP_LP_MISR_SIGN_MDP,
+ .crc_op_mode = 0,
+ .crc_index = 0,
+ .use_ping = true,
+ .is_ping_full = false,
+ .is_pong_full = false,
},
};
@@ -438,7 +474,7 @@
{
struct mdss_mdp_misr_map *map;
- if (block_id > DISPLAY_MISR_LCDC) {
+ if (block_id > DISPLAY_MISR_MDP) {
pr_err("MISR Block id (%d) out of range\n", block_id);
return NULL;
}
@@ -452,23 +488,51 @@
return map;
}
-int mdss_misr_crc_set(struct mdss_data_type *mdata, struct mdp_misr *req)
+int mdss_misr_set(struct mdss_data_type *mdata,
+ struct mdp_misr *req,
+ struct mdss_mdp_ctl *ctl)
{
struct mdss_mdp_misr_map *map;
- u32 config = 0;
-
+ struct mdss_mdp_mixer *mixer;
+ u32 config = 0, val = 0;
+ u32 mixer_num = 0;
+ bool is_valid_wb_mixer = true;
map = mdss_misr_get_map(req->block_id);
if (!map) {
pr_err("Invalid MISR Block=%d\n", req->block_id);
return -EINVAL;
}
-
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+ if (req->block_id == DISPLAY_MISR_MDP) {
+ mixer = mdss_mdp_mixer_get(ctl, MDSS_MDP_MIXER_MUX_DEFAULT);
+ mixer_num = mixer->num;
+ pr_debug("SET MDP MISR BLK to MDSS_MDP_LP_MISR_SEL_LMIX%d_GC\n",
+ req->block_id);
+ switch (mixer_num) {
+ case MDSS_MDP_INTF_LAYERMIXER0:
+ pr_debug("Use Layer Mixer 0 for WB CRC\n");
+ val = MDSS_MDP_LP_MISR_SEL_LMIX0_GC;
+ break;
+ case MDSS_MDP_INTF_LAYERMIXER1:
+ pr_debug("Use Layer Mixer 1 for WB CRC\n");
+ val = MDSS_MDP_LP_MISR_SEL_LMIX1_GC;
+ break;
+ case MDSS_MDP_INTF_LAYERMIXER2:
+ pr_debug("Use Layer Mixer 2 for WB CRC\n");
+ val = MDSS_MDP_LP_MISR_SEL_LMIX2_GC;
+ break;
+ default:
+ pr_err("Invalid Layer Mixer %d selected for WB CRC\n",
+ mixer_num);
+ is_valid_wb_mixer = false;
+ break;
+ }
+ if (is_valid_wb_mixer)
+ writel_relaxed(val,
+ mdata->mdp_base + MDSS_MDP_LP_MISR_SEL);
+ }
+ vsync_count = 0;
map->crc_op_mode = req->crc_op_mode;
- memset(map->crc_value, 0, sizeof(map->crc_value));
-
- pr_debug("MISR Config (BlockId %d) (Frame Count = %d)\n",
- req->block_id, req->frame_count);
-
config = (MDSS_MDP_LP_MISR_CTRL_FRAME_COUNT_MASK & req->frame_count) |
(MDSS_MDP_LP_MISR_CTRL_ENABLE);
@@ -476,24 +540,32 @@
mdata->mdp_base + map->ctrl_reg);
/* ensure clear is done */
wmb();
- if (MISR_OP_BM == map->crc_op_mode) {
- writel_relaxed(MISR_CRC_BATCH_CFG,
- mdata->mdp_base + map->ctrl_reg);
- } else {
- writel_relaxed(config,
- mdata->mdp_base + map->ctrl_reg);
- config = readl_relaxed(mdata->mdp_base + map->ctrl_reg);
- pr_debug("MISR_CTRL = 0x%x", config);
+ memset(map->crc_ping, 0, sizeof(map->crc_ping));
+ memset(map->crc_pong, 0, sizeof(map->crc_pong));
+ map->crc_index = 0;
+ map->use_ping = true;
+ map->is_ping_full = false;
+ map->is_pong_full = false;
+
+ if (MISR_OP_BM != map->crc_op_mode) {
+
+ writel_relaxed(config,
+ mdata->mdp_base + map->ctrl_reg);
+ pr_debug("MISR_CTRL = 0x%x",
+ readl_relaxed(mdata->mdp_base + map->ctrl_reg));
}
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
return 0;
}
-int mdss_misr_crc_get(struct mdss_data_type *mdata, struct mdp_misr *resp)
+int mdss_misr_get(struct mdss_data_type *mdata,
+ struct mdp_misr *resp,
+ struct mdss_mdp_ctl *ctl)
{
struct mdss_mdp_misr_map *map;
u32 status;
- int ret = 0;
+ int ret = -1;
int i;
map = mdss_misr_get_map(resp->block_id);
@@ -501,35 +573,60 @@
pr_err("Invalid MISR Block=%d\n", resp->block_id);
return -EINVAL;
}
-
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
switch (map->crc_op_mode) {
case MISR_OP_SFM:
case MISR_OP_MFM:
ret = readl_poll_timeout(mdata->mdp_base + map->ctrl_reg,
status, status & MDSS_MDP_LP_MISR_CTRL_STATUS,
MISR_POLL_SLEEP, MISR_POLL_TIMEOUT);
-
- pr_debug("Status of Get MISR_CTRL = 0x%x", status);
if (ret == 0) {
- resp->crc_value[0] =
- readl_relaxed(mdata->mdp_base + map->value_reg);
+ resp->crc_value[0] = readl_relaxed(mdata->mdp_base +
+ map->value_reg);
pr_debug("CRC %d=0x%x\n", resp->block_id,
- resp->crc_value[0]);
+ resp->crc_value[0]);
+ writel_relaxed(0, mdata->mdp_base + map->ctrl_reg);
} else {
- pr_warn("MISR %d busy with status 0x%x\n",
- resp->block_id, status);
+ mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_START, 1);
+ ret = readl_poll_timeout(mdata->mdp_base +
+ map->ctrl_reg, status,
+ status & MDSS_MDP_LP_MISR_CTRL_STATUS,
+ MISR_POLL_SLEEP, MISR_POLL_TIMEOUT);
+ if (ret == 0) {
+ resp->crc_value[0] =
+ readl_relaxed(mdata->mdp_base +
+ map->value_reg);
+ }
+ writel_relaxed(0, mdata->mdp_base + map->ctrl_reg);
}
break;
case MISR_OP_BM:
- for (i = 0; i < MISR_CRC_BATCH_SIZE; i++)
- resp->crc_value[i] = map->crc_value[i];
- map->crc_index = 0;
+ if (map->is_ping_full) {
+ for (i = 0; i < MISR_CRC_BATCH_SIZE; i++)
+ resp->crc_value[i] = map->crc_ping[i];
+ memset(map->crc_ping, 0, sizeof(map->crc_ping));
+ map->is_ping_full = false;
+ ret = 0;
+ } else if (map->is_pong_full) {
+ for (i = 0; i < MISR_CRC_BATCH_SIZE; i++)
+ resp->crc_value[i] = map->crc_pong[i];
+ memset(map->crc_pong, 0, sizeof(map->crc_pong));
+ map->is_pong_full = false;
+ ret = 0;
+ } else {
+ pr_debug("mdss_mdp_misr_crc_get PING BUF %s\n",
+ map->is_ping_full ? "FULL" : "EMPTRY");
+ pr_debug("mdss_mdp_misr_crc_get PONG BUF %s\n",
+ map->is_pong_full ? "FULL" : "EMPTRY");
+ }
+ resp->crc_op_mode = map->crc_op_mode;
break;
default:
ret = -ENOSYS;
break;
}
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
return ret;
}
@@ -537,22 +634,71 @@
void mdss_misr_crc_collect(struct mdss_data_type *mdata, int block_id)
{
struct mdss_mdp_misr_map *map;
- u32 status, config;
+ u32 status = 0;
+ u32 crc = 0x0BAD0BAD;
+ bool crc_stored = false;
map = mdss_misr_get_map(block_id);
if (!map || (map->crc_op_mode != MISR_OP_BM))
return;
- config = MISR_CRC_BATCH_CFG;
-
status = readl_relaxed(mdata->mdp_base + map->ctrl_reg);
- if (status & MDSS_MDP_LP_MISR_CTRL_STATUS) {
- map->crc_value[map->crc_index] =
- readl_relaxed(mdata->mdp_base + map->value_reg);
- map->crc_index++;
- if (map->crc_index == MISR_CRC_BATCH_SIZE)
- map->crc_index = 0;
- config |= MDSS_MDP_LP_MISR_CTRL_STATUS_CLEAR;
+ if (MDSS_MDP_LP_MISR_CTRL_STATUS & status) {
+ crc = readl_relaxed(mdata->mdp_base + map->value_reg);
+ if (map->use_ping) {
+ if (map->is_ping_full) {
+ pr_err("PING Buffer FULL\n");
+ } else {
+ map->crc_ping[map->crc_index] = crc;
+ crc_stored = true;
+ }
+ } else {
+ if (map->is_pong_full) {
+ pr_err("PONG Buffer FULL\n");
+ } else {
+ map->crc_pong[map->crc_index] = crc;
+ crc_stored = true;
+ }
+ }
+
+ if (crc_stored) {
+ map->crc_index = (map->crc_index + 1);
+ if (map->crc_index == MISR_CRC_BATCH_SIZE) {
+ map->crc_index = 0;
+ if (true == map->use_ping) {
+ map->is_ping_full = true;
+ map->use_ping = false;
+ } else {
+ map->is_pong_full = true;
+ map->use_ping = true;
+ }
+ pr_debug("USE BUFF %s\n", map->use_ping ?
+ "PING" : "PONG");
+ pr_debug("mdss_misr_crc_collect PING BUF %s\n",
+ map->is_ping_full ? "FULL" : "EMPTRY");
+ pr_debug("mdss_misr_crc_collect PONG BUF %s\n",
+ map->is_pong_full ? "FULL" : "EMPTRY");
+ }
+ } else {
+ pr_err("CRC(%d) Not saved\n", crc);
+ }
+
+ writel_relaxed(MDSS_MDP_LP_MISR_CTRL_STATUS_CLEAR,
+ mdata->mdp_base + map->ctrl_reg);
+ writel_relaxed(MISR_CRC_BATCH_CFG,
+ mdata->mdp_base + map->ctrl_reg);
+ } else if (0 == status) {
+ writel_relaxed(MISR_CRC_BATCH_CFG,
+ mdata->mdp_base + map->ctrl_reg);
+ pr_debug("$$ Batch CRC Start $$\n");
}
- writel_relaxed(config, mdata->mdp_base + map->ctrl_reg);
+ pr_debug("$$ Vsync Count = %d, CRC=0x%x Indx = %d$$\n",
+ vsync_count, crc, map->crc_index);
+
+ if (MAX_VSYNC_COUNT == vsync_count) {
+ pr_err("RESET vsync_count(%d)\n", vsync_count);
+ vsync_count = 0;
+ } else {
+ vsync_count += 1;
+ }
}
diff --git a/drivers/video/msm/mdss/mdss_debug.h b/drivers/video/msm/mdss/mdss_debug.h
index 29eb16c..984caab 100644
--- a/drivers/video/msm/mdss/mdss_debug.h
+++ b/drivers/video/msm/mdss/mdss_debug.h
@@ -16,30 +16,35 @@
#include "mdss.h"
-#define MISR_POLL_SLEEP 2000
-#define MISR_POLL_TIMEOUT 32000
-#define MISR_CRC_BATCH_SIZE 32
-#define MISR_CRC_BATCH_CFG 0x101
+#define MISR_POLL_SLEEP 2000
+#define MISR_POLL_TIMEOUT 32000
+#define MISR_CRC_BATCH_CFG 0x101
#ifdef CONFIG_DEBUG_FS
int mdss_debugfs_init(struct mdss_data_type *mdata);
int mdss_debugfs_remove(struct mdss_data_type *mdata);
int mdss_debug_register_base(const char *name, void __iomem *base,
size_t max_offset);
-int mdss_misr_crc_set(struct mdss_data_type *mdata, struct mdp_misr *req);
-int mdss_misr_crc_get(struct mdss_data_type *mdata, struct mdp_misr *resp);
+int mdss_misr_set(struct mdss_data_type *mdata, struct mdp_misr *req,
+ struct mdss_mdp_ctl *ctl);
+int mdss_misr_get(struct mdss_data_type *mdata, struct mdp_misr *resp,
+ struct mdss_mdp_ctl *ctl);
void mdss_misr_crc_collect(struct mdss_data_type *mdata, int block_id);
#else
static inline int mdss_debugfs_init(struct mdss_data_type *mdata) { return 0; }
static inline int mdss_debugfs_remove(struct mdss_data_type *mdata)
{ return 0; }
static inline int mdss_debug_register_base(const char *name, void __iomem *base,
- size_t max_offset) { return 0; }
-static inline int mdss_misr_crc_set(struct mdss_data_type *mdata,
- struct mdp_misr *reg) { return 0; }
-static inline int mdss_misr_crc_get(struct mdss_data_type *mdata,
- struct mdp_misr *resp) { return 0; }
+ size_t max_offset) { return 0; }
+static inline int mdss_misr_set(struct mdss_data_type *mdata,
+ struct mdp_misr *req,
+ struct mdss_mdp_ctl *ctl)
+{ return 0; }
+static inline int mdss_misr_get(struct mdss_data_type *mdata,
+ struct mdp_misr *resp,
+ struct mdss_mdp_ctl *ctl)
+{ return 0; }
static inline void mdss_misr_crc_collect(struct mdss_data_type *mdata,
- int block_id) { }
+ int block_id) { }
#endif
#endif /* MDSS_DEBUG_H */
diff --git a/drivers/video/msm/mdss/mdss_dsi.h b/drivers/video/msm/mdss/mdss_dsi.h
index 7202c62..855ec6c 100644
--- a/drivers/video/msm/mdss/mdss_dsi.h
+++ b/drivers/video/msm/mdss/mdss_dsi.h
@@ -19,6 +19,7 @@
#include "mdss_panel.h"
#include "mdss_io_util.h"
+#include "mdss_dsi_cmd.h"
#define MMSS_SERDES_BASE_PHY 0x04f01000 /* mmss (De)Serializer CFG */
@@ -89,6 +90,17 @@
DSI_HS_MODE,
};
+enum dsi_lane_map_type {
+ DSI_LANE_MAP_0123,
+ DSI_LANE_MAP_3012,
+ DSI_LANE_MAP_2301,
+ DSI_LANE_MAP_1230,
+ DSI_LANE_MAP_0321,
+ DSI_LANE_MAP_1032,
+ DSI_LANE_MAP_2103,
+ DSI_LANE_MAP_3210,
+};
+
#define CTRL_STATE_UNKNOWN 0x00
#define CTRL_STATE_PANEL_INIT BIT(0)
#define CTRL_STATE_MDP_ACTIVE BIT(1)
@@ -183,81 +195,6 @@
u32 pre_div_func;
};
-#define DSI_HOST_HDR_SIZE 4
-#define DSI_HDR_LAST BIT(31)
-#define DSI_HDR_LONG_PKT BIT(30)
-#define DSI_HDR_BTA BIT(29)
-#define DSI_HDR_VC(vc) (((vc) & 0x03) << 22)
-#define DSI_HDR_DTYPE(dtype) (((dtype) & 0x03f) << 16)
-#define DSI_HDR_DATA2(data) (((data) & 0x0ff) << 8)
-#define DSI_HDR_DATA1(data) ((data) & 0x0ff)
-#define DSI_HDR_WC(wc) ((wc) & 0x0ffff)
-
-#define MDSS_DSI_MRPS 0x04 /* Maximum Return Packet Size */
-
-#define MDSS_DSI_LEN 8 /* 4 x 4 - 6 - 2, bytes dcs header+crc-align */
-
-struct dsi_buf {
- u32 *hdr; /* dsi host header */
- char *start; /* buffer start addr */
- char *end; /* buffer end addr */
- int size; /* size of buffer */
- char *data; /* buffer */
- int len; /* data length */
- dma_addr_t dmap; /* mapped dma addr */
-};
-
-/* dcs read/write */
-#define DTYPE_DCS_WRITE 0x05 /* short write, 0 parameter */
-#define DTYPE_DCS_WRITE1 0x15 /* short write, 1 parameter */
-#define DTYPE_DCS_READ 0x06 /* read */
-#define DTYPE_DCS_LWRITE 0x39 /* long write */
-
-/* generic read/write */
-#define DTYPE_GEN_WRITE 0x03 /* short write, 0 parameter */
-#define DTYPE_GEN_WRITE1 0x13 /* short write, 1 parameter */
-#define DTYPE_GEN_WRITE2 0x23 /* short write, 2 parameter */
-#define DTYPE_GEN_LWRITE 0x29 /* long write */
-#define DTYPE_GEN_READ 0x04 /* long read, 0 parameter */
-#define DTYPE_GEN_READ1 0x14 /* long read, 1 parameter */
-#define DTYPE_GEN_READ2 0x24 /* long read, 2 parameter */
-
-#define DTYPE_TEAR_ON 0x35 /* set tear on */
-#define DTYPE_MAX_PKTSIZE 0x37 /* set max packet size */
-#define DTYPE_NULL_PKT 0x09 /* null packet, no data */
-#define DTYPE_BLANK_PKT 0x19 /* blankiing packet, no data */
-
-#define DTYPE_CM_ON 0x02 /* color mode off */
-#define DTYPE_CM_OFF 0x12 /* color mode on */
-#define DTYPE_PERIPHERAL_OFF 0x22
-#define DTYPE_PERIPHERAL_ON 0x32
-
-/*
- * dcs response
- */
-#define DTYPE_ACK_ERR_RESP 0x02
-#define DTYPE_EOT_RESP 0x08 /* end of tx */
-#define DTYPE_GEN_READ1_RESP 0x11 /* 1 parameter, short */
-#define DTYPE_GEN_READ2_RESP 0x12 /* 2 parameter, short */
-#define DTYPE_GEN_LREAD_RESP 0x1a
-#define DTYPE_DCS_LREAD_RESP 0x1c
-#define DTYPE_DCS_READ1_RESP 0x21 /* 1 parameter, short */
-#define DTYPE_DCS_READ2_RESP 0x22 /* 2 parameter, short */
-
-
-struct dsi_ctrl_hdr {
- char dtype; /* data type */
- char last; /* last in chain */
- char vc; /* virtual chan */
- char ack; /* ask ACK from peripheral */
- char wait; /* ms */
- short dlen; /* 16 bits */
-} __packed;
-
-struct dsi_cmd_desc {
- struct dsi_ctrl_hdr dchdr;
- char *payload;
-};
struct dsi_panel_cmds {
char *buf;
@@ -267,29 +204,6 @@
int link_state;
};
-#define CMD_REQ_MAX 4
-
-#define CMD_REQ_RX 0x0001
-#define CMD_REQ_COMMIT 0x0002
-#define CMD_CLK_CTRL 0x0004
-#define CMD_REQ_NO_MAX_PKT_SIZE 0x0008
-
-struct dcs_cmd_req {
- struct dsi_cmd_desc *cmds;
- int cmds_cnt;
- u32 flags;
- int rlen; /* rx length */
- char *rbuf; /* rx buf */
- void (*cb)(int data);
-};
-
-struct dcs_cmd_list {
- int put;
- int get;
- int tot;
- struct dcs_cmd_req list[CMD_REQ_MAX];
-};
-
struct dsi_kickoff_action {
struct list_head act_entry;
void (*action) (void *);
@@ -319,6 +233,7 @@
int (*off) (struct mdss_panel_data *pdata);
int (*partial_update_fnc) (struct mdss_panel_data *pdata);
int (*check_status) (struct mdss_dsi_ctrl_pdata *pdata);
+ int (*cmdlist_commit)(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp);
struct mdss_panel_data panel_data;
unsigned char *ctrl_base;
int reg_size;
@@ -378,11 +293,6 @@
int dsi_panel_device_register(struct device_node *pan_node,
struct mdss_dsi_ctrl_pdata *ctrl_pdata);
-char *mdss_dsi_buf_reserve_hdr(struct dsi_buf *dp, int hlen);
-char *mdss_dsi_buf_init(struct dsi_buf *dp);
-void mdss_dsi_init(void);
-int mdss_dsi_buf_alloc(struct dsi_buf *, int size);
-int mdss_dsi_cmd_dma_add(struct dsi_buf *dp, struct dsi_cmd_desc *cm);
int mdss_dsi_cmds_tx(struct mdss_dsi_ctrl_pdata *ctrl,
struct dsi_cmd_desc *cmds, int cnt);
@@ -391,8 +301,6 @@
void mdss_dsi_host_init(struct mipi_panel_info *pinfo,
struct mdss_panel_data *pdata);
-void mdss_dsi_set_tear_on(struct mdss_dsi_ctrl_pdata *ctrl);
-void mdss_dsi_set_tear_off(struct mdss_dsi_ctrl_pdata *ctrl);
void mdss_dsi_op_mode_config(int mode,
struct mdss_panel_data *pdata);
void mdss_dsi_cmd_mode_ctrl(int enable);
@@ -428,10 +336,7 @@
void mdss_dsi_ctrl_init(struct mdss_dsi_ctrl_pdata *ctrl);
void mdss_dsi_cmd_mdp_busy(struct mdss_dsi_ctrl_pdata *ctrl);
void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl);
-void mdss_dsi_cmdlist_commit(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp);
-int mdss_dsi_cmdlist_put(struct mdss_dsi_ctrl_pdata *ctrl,
- struct dcs_cmd_req *cmdreq);
-struct dcs_cmd_req *mdss_dsi_cmdlist_get(struct mdss_dsi_ctrl_pdata *ctrl);
+int mdss_dsi_cmdlist_commit(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp);
void mdss_dsi_cmdlist_kickoff(int intf);
int mdss_dsi_bta_status_check(struct mdss_dsi_ctrl_pdata *ctrl);
diff --git a/drivers/video/msm/mdss/mdss_dsi_cmd.c b/drivers/video/msm/mdss/mdss_dsi_cmd.c
new file mode 100644
index 0000000..8fc1115c0
--- /dev/null
+++ b/drivers/video/msm/mdss/mdss_dsi_cmd.c
@@ -0,0 +1,688 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/iopoll.h>
+#include <linux/kthread.h>
+
+#include <mach/iommu_domains.h>
+
+#include "mdss_dsi_cmd.h"
+#include "mdss_dsi.h"
+
+/*
+ * mipi dsi buf mechanism
+ */
+char *mdss_dsi_buf_reserve(struct dsi_buf *dp, int len)
+{
+ dp->data += len;
+ return dp->data;
+}
+
+char *mdss_dsi_buf_unreserve(struct dsi_buf *dp, int len)
+{
+ dp->data -= len;
+ return dp->data;
+}
+
+char *mdss_dsi_buf_push(struct dsi_buf *dp, int len)
+{
+ dp->data -= len;
+ dp->len += len;
+ return dp->data;
+}
+
+char *mdss_dsi_buf_reserve_hdr(struct dsi_buf *dp, int hlen)
+{
+ dp->hdr = (u32 *)dp->data;
+ return mdss_dsi_buf_reserve(dp, hlen);
+}
+
+char *mdss_dsi_buf_init(struct dsi_buf *dp)
+{
+ int off;
+
+ dp->data = dp->start;
+ off = (int)dp->data;
+ /* 8 byte align */
+ off &= 0x07;
+ if (off)
+ off = 8 - off;
+ dp->data += off;
+ dp->len = 0;
+ return dp->data;
+}
+
+int mdss_dsi_buf_alloc(struct dsi_buf *dp, int size)
+{
+
+ dp->start = dma_alloc_writecombine(NULL, size, &dp->dmap, GFP_KERNEL);
+ if (dp->start == NULL) {
+ pr_err("%s:%u\n", __func__, __LINE__);
+ return -ENOMEM;
+ }
+
+ dp->end = dp->start + size;
+ dp->size = size;
+
+ if ((int)dp->start & 0x07)
+ pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
+
+ dp->data = dp->start;
+ dp->len = 0;
+ return size;
+}
+
+/*
+ * mipi dsi generic long write
+ */
+static int mdss_dsi_generic_lwrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ char *bp;
+ u32 *hp;
+ int i, len = 0;
+
+ dchdr = &cm->dchdr;
+ bp = mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+
+ /* fill up payload */
+ if (cm->payload) {
+ len = dchdr->dlen;
+ len += 3;
+ len &= ~0x03; /* multipled by 4 */
+ for (i = 0; i < dchdr->dlen; i++)
+ *bp++ = cm->payload[i];
+
+ /* append 0xff to the end */
+ for (; i < len; i++)
+ *bp++ = 0xff;
+
+ dp->len += len;
+ }
+
+ /* fill up header */
+ hp = dp->hdr;
+ *hp = 0;
+ *hp = DSI_HDR_WC(dchdr->dlen);
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_LONG_PKT;
+ *hp |= DSI_HDR_DTYPE(DTYPE_GEN_LWRITE);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ len += DSI_HOST_HDR_SIZE;
+
+ return len;
+}
+
+/*
+ * mipi dsi generic short write with 0, 1 2 parameters
+ */
+static int mdss_dsi_generic_swrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+ int len;
+
+ dchdr = &cm->dchdr;
+ if (dchdr->dlen && cm->payload == 0) {
+ pr_err("%s: NO payload error\n", __func__);
+ return 0;
+ }
+
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+
+ len = (dchdr->dlen > 2) ? 2 : dchdr->dlen;
+
+ if (len == 1) {
+ *hp |= DSI_HDR_DTYPE(DTYPE_GEN_WRITE1);
+ *hp |= DSI_HDR_DATA1(cm->payload[0]);
+ *hp |= DSI_HDR_DATA2(0);
+ } else if (len == 2) {
+ *hp |= DSI_HDR_DTYPE(DTYPE_GEN_WRITE2);
+ *hp |= DSI_HDR_DATA1(cm->payload[0]);
+ *hp |= DSI_HDR_DATA2(cm->payload[1]);
+ } else {
+ *hp |= DSI_HDR_DTYPE(DTYPE_GEN_WRITE);
+ *hp |= DSI_HDR_DATA1(0);
+ *hp |= DSI_HDR_DATA2(0);
+ }
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+/*
+ * mipi dsi gerneric read with 0, 1 2 parameters
+ */
+static int mdss_dsi_generic_read(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+ int len;
+
+ dchdr = &cm->dchdr;
+ if (dchdr->dlen && cm->payload == 0) {
+ pr_err("%s: NO payload error\n", __func__);
+ return 0;
+ }
+
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_BTA;
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ len = (dchdr->dlen > 2) ? 2 : dchdr->dlen;
+
+ if (len == 1) {
+ *hp |= DSI_HDR_DTYPE(DTYPE_GEN_READ1);
+ *hp |= DSI_HDR_DATA1(cm->payload[0]);
+ *hp |= DSI_HDR_DATA2(0);
+ } else if (len == 2) {
+ *hp |= DSI_HDR_DTYPE(DTYPE_GEN_READ2);
+ *hp |= DSI_HDR_DATA1(cm->payload[0]);
+ *hp |= DSI_HDR_DATA2(cm->payload[1]);
+ } else {
+ *hp |= DSI_HDR_DTYPE(DTYPE_GEN_READ);
+ *hp |= DSI_HDR_DATA1(0);
+ *hp |= DSI_HDR_DATA2(0);
+ }
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+/*
+ * mipi dsi dcs long write
+ */
+static int mdss_dsi_dcs_lwrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ char *bp;
+ u32 *hp;
+ int i, len = 0;
+
+ dchdr = &cm->dchdr;
+ bp = mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+
+ /*
+ * fill up payload
+ * dcs command byte (first byte) followed by payload
+ */
+ if (cm->payload) {
+ len = dchdr->dlen;
+ len += 3;
+ len &= ~0x03; /* multipled by 4 */
+ for (i = 0; i < dchdr->dlen; i++)
+ *bp++ = cm->payload[i];
+
+ /* append 0xff to the end */
+ for (; i < len; i++)
+ *bp++ = 0xff;
+
+ dp->len += len;
+ }
+
+ /* fill up header */
+ hp = dp->hdr;
+ *hp = 0;
+ *hp = DSI_HDR_WC(dchdr->dlen);
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_LONG_PKT;
+ *hp |= DSI_HDR_DTYPE(DTYPE_DCS_LWRITE);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+
+ len += DSI_HOST_HDR_SIZE;
+ return len;
+}
+
+/*
+ * mipi dsi dcs short write with 0 parameters
+ */
+static int mdss_dsi_dcs_swrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+ int len;
+
+ dchdr = &cm->dchdr;
+ if (cm->payload == 0) {
+ pr_err("%s: NO payload error\n", __func__);
+ return -EINVAL;
+ }
+
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ if (dchdr->ack) /* ask ACK trigger msg from peripeheral */
+ *hp |= DSI_HDR_BTA;
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ len = (dchdr->dlen > 1) ? 1 : dchdr->dlen;
+
+ *hp |= DSI_HDR_DTYPE(DTYPE_DCS_WRITE);
+ *hp |= DSI_HDR_DATA1(cm->payload[0]); /* dcs command byte */
+ *hp |= DSI_HDR_DATA2(0);
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+/*
+ * mipi dsi dcs short write with 1 parameters
+ */
+static int mdss_dsi_dcs_swrite1(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+
+ dchdr = &cm->dchdr;
+ if (dchdr->dlen < 2 || cm->payload == 0) {
+ pr_err("%s: NO payload error\n", __func__);
+ return -EINVAL;
+ }
+
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ if (dchdr->ack) /* ask ACK trigger msg from peripeheral */
+ *hp |= DSI_HDR_BTA;
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ *hp |= DSI_HDR_DTYPE(DTYPE_DCS_WRITE1);
+ *hp |= DSI_HDR_DATA1(cm->payload[0]); /* dcs comamnd byte */
+ *hp |= DSI_HDR_DATA2(cm->payload[1]); /* parameter */
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+/*
+ * mipi dsi dcs read with 0 parameters
+ */
+
+static int mdss_dsi_dcs_read(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+
+ dchdr = &cm->dchdr;
+ if (cm->payload == 0) {
+ pr_err("%s: NO payload error\n", __func__);
+ return -EINVAL;
+ }
+
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_BTA;
+ *hp |= DSI_HDR_DTYPE(DTYPE_DCS_READ);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ *hp |= DSI_HDR_DATA1(cm->payload[0]); /* dcs command byte */
+ *hp |= DSI_HDR_DATA2(0);
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+static int mdss_dsi_cm_on(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+
+ dchdr = &cm->dchdr;
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_DTYPE(DTYPE_CM_ON);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+static int mdss_dsi_cm_off(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+
+ dchdr = &cm->dchdr;
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_DTYPE(DTYPE_CM_OFF);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+static int mdss_dsi_peripheral_on(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+
+ dchdr = &cm->dchdr;
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_DTYPE(DTYPE_PERIPHERAL_ON);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+static int mdss_dsi_peripheral_off(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+
+ dchdr = &cm->dchdr;
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_DTYPE(DTYPE_PERIPHERAL_OFF);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+static int mdss_dsi_set_max_pktsize(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+
+ dchdr = &cm->dchdr;
+ if (cm->payload == 0) {
+ pr_err("%s: NO payload error\n", __func__);
+ return 0;
+ }
+
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_DTYPE(DTYPE_MAX_PKTSIZE);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ *hp |= DSI_HDR_DATA1(cm->payload[0]);
+ *hp |= DSI_HDR_DATA2(cm->payload[1]);
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+static int mdss_dsi_null_pkt(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+
+ dchdr = &cm->dchdr;
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp = DSI_HDR_WC(dchdr->dlen);
+ *hp |= DSI_HDR_LONG_PKT;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_DTYPE(DTYPE_NULL_PKT);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+static int mdss_dsi_blank_pkt(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ u32 *hp;
+
+ dchdr = &cm->dchdr;
+ mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
+ hp = dp->hdr;
+ *hp = 0;
+ *hp = DSI_HDR_WC(dchdr->dlen);
+ *hp |= DSI_HDR_LONG_PKT;
+ *hp |= DSI_HDR_VC(dchdr->vc);
+ *hp |= DSI_HDR_DTYPE(DTYPE_BLANK_PKT);
+ if (dchdr->last)
+ *hp |= DSI_HDR_LAST;
+
+ mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
+ return DSI_HOST_HDR_SIZE; /* 4 bytes */
+}
+
+/*
+ * prepare cmd buffer to be txed
+ */
+int mdss_dsi_cmd_dma_add(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
+{
+ struct dsi_ctrl_hdr *dchdr;
+ int len = 0;
+
+ dchdr = &cm->dchdr;
+
+ switch (dchdr->dtype) {
+ case DTYPE_GEN_WRITE:
+ case DTYPE_GEN_WRITE1:
+ case DTYPE_GEN_WRITE2:
+ len = mdss_dsi_generic_swrite(dp, cm);
+ break;
+ case DTYPE_GEN_LWRITE:
+ len = mdss_dsi_generic_lwrite(dp, cm);
+ break;
+ case DTYPE_GEN_READ:
+ case DTYPE_GEN_READ1:
+ case DTYPE_GEN_READ2:
+ len = mdss_dsi_generic_read(dp, cm);
+ break;
+ case DTYPE_DCS_LWRITE:
+ len = mdss_dsi_dcs_lwrite(dp, cm);
+ break;
+ case DTYPE_DCS_WRITE:
+ len = mdss_dsi_dcs_swrite(dp, cm);
+ break;
+ case DTYPE_DCS_WRITE1:
+ len = mdss_dsi_dcs_swrite1(dp, cm);
+ break;
+ case DTYPE_DCS_READ:
+ len = mdss_dsi_dcs_read(dp, cm);
+ break;
+ case DTYPE_MAX_PKTSIZE:
+ len = mdss_dsi_set_max_pktsize(dp, cm);
+ break;
+ case DTYPE_NULL_PKT:
+ len = mdss_dsi_null_pkt(dp, cm);
+ break;
+ case DTYPE_BLANK_PKT:
+ len = mdss_dsi_blank_pkt(dp, cm);
+ break;
+ case DTYPE_CM_ON:
+ len = mdss_dsi_cm_on(dp, cm);
+ break;
+ case DTYPE_CM_OFF:
+ len = mdss_dsi_cm_off(dp, cm);
+ break;
+ case DTYPE_PERIPHERAL_ON:
+ len = mdss_dsi_peripheral_on(dp, cm);
+ break;
+ case DTYPE_PERIPHERAL_OFF:
+ len = mdss_dsi_peripheral_off(dp, cm);
+ break;
+ default:
+ pr_debug("%s: dtype=%x NOT supported\n",
+ __func__, dchdr->dtype);
+ break;
+
+ }
+
+ return len;
+}
+
+/*
+ * mdss_dsi_short_read1_resp: 1 parameter
+ */
+int mdss_dsi_short_read1_resp(struct dsi_buf *rp)
+{
+ /* strip out dcs type */
+ rp->data++;
+ rp->len = 1;
+ return rp->len;
+}
+
+/*
+ * mdss_dsi_short_read2_resp: 2 parameter
+ */
+int mdss_dsi_short_read2_resp(struct dsi_buf *rp)
+{
+ /* strip out dcs type */
+ rp->data++;
+ rp->len = 2;
+ return rp->len;
+}
+
+int mdss_dsi_long_read_resp(struct dsi_buf *rp)
+{
+ /* strip out dcs header */
+ rp->data += 4;
+ rp->len -= 4;
+ return rp->len;
+}
+
+static char set_tear_on[2] = {0x35, 0x00};
+static struct dsi_cmd_desc dsi_tear_on_cmd = {
+ {DTYPE_DCS_WRITE1, 1, 0, 0, 0, sizeof(set_tear_on)}, set_tear_on};
+
+static char set_tear_off[2] = {0x34, 0x00};
+static struct dsi_cmd_desc dsi_tear_off_cmd = {
+ {DTYPE_DCS_WRITE, 1, 0, 0, 0, sizeof(set_tear_off)}, set_tear_off};
+
+void mdss_dsi_set_tear_on(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ struct dcs_cmd_req cmdreq;
+
+ cmdreq.cmds = &dsi_tear_on_cmd;
+ cmdreq.cmds_cnt = 1;
+ cmdreq.flags = CMD_REQ_COMMIT;
+ cmdreq.rlen = 0;
+ cmdreq.cb = NULL;
+
+ mdss_dsi_cmdlist_put(ctrl, &cmdreq);
+}
+
+void mdss_dsi_set_tear_off(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ struct dcs_cmd_req cmdreq;
+
+ cmdreq.cmds = &dsi_tear_off_cmd;
+ cmdreq.cmds_cnt = 1;
+ cmdreq.flags = CMD_REQ_COMMIT;
+ cmdreq.rlen = 0;
+ cmdreq.cb = NULL;
+
+ mdss_dsi_cmdlist_put(ctrl, &cmdreq);
+}
+
+/*
+ * mdss_dsi_cmd_get: ctrl->cmd_mutex acquired by caller
+ */
+struct dcs_cmd_req *mdss_dsi_cmdlist_get(struct mdss_dsi_ctrl_pdata *ctrl)
+{
+ struct dcs_cmd_list *clist;
+ struct dcs_cmd_req *req = NULL;
+
+ clist = &ctrl->cmdlist;
+ if (clist->get != clist->put) {
+ req = &clist->list[clist->get];
+ clist->get++;
+ clist->get %= CMD_REQ_MAX;
+ clist->tot--;
+ pr_debug("%s: tot=%d put=%d get=%d\n", __func__,
+ clist->tot, clist->put, clist->get);
+ }
+ return req;
+}
+
+int mdss_dsi_cmdlist_put(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dcs_cmd_req *cmdreq)
+{
+ struct dcs_cmd_req *req;
+ struct dcs_cmd_list *clist;
+ int ret = -EINVAL;
+
+ mutex_lock(&ctrl->cmd_mutex);
+ clist = &ctrl->cmdlist;
+ req = &clist->list[clist->put];
+ *req = *cmdreq;
+ clist->put++;
+ clist->put %= CMD_REQ_MAX;
+ clist->tot++;
+ if (clist->put == clist->get) {
+ /* drop the oldest one */
+ pr_debug("%s: DROP, tot=%d put=%d get=%d\n", __func__,
+ clist->tot, clist->put, clist->get);
+ clist->get++;
+ clist->get %= CMD_REQ_MAX;
+ clist->tot--;
+ }
+ mutex_unlock(&ctrl->cmd_mutex);
+
+ pr_debug("%s: tot=%d put=%d get=%d\n", __func__,
+ clist->tot, clist->put, clist->get);
+
+ if (req->flags & CMD_REQ_COMMIT) {
+ if (!ctrl->cmdlist_commit)
+ pr_err("cmdlist_commit not implemented!\n");
+ else
+ ret = ctrl->cmdlist_commit(ctrl, 0);
+ }
+ return ret;
+}
+
diff --git a/drivers/video/msm/mdss/mdss_dsi_cmd.h b/drivers/video/msm/mdss/mdss_dsi_cmd.h
new file mode 100644
index 0000000..c480756
--- /dev/null
+++ b/drivers/video/msm/mdss/mdss_dsi_cmd.h
@@ -0,0 +1,133 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef MDSS_DSI_CMD_H
+#define MDSS_DSI_CMD_H
+
+#include "mdss.h"
+
+struct mdss_dsi_ctrl_pdata;
+
+#define DSI_HOST_HDR_SIZE 4
+#define DSI_HDR_LAST BIT(31)
+#define DSI_HDR_LONG_PKT BIT(30)
+#define DSI_HDR_BTA BIT(29)
+#define DSI_HDR_VC(vc) (((vc) & 0x03) << 22)
+#define DSI_HDR_DTYPE(dtype) (((dtype) & 0x03f) << 16)
+#define DSI_HDR_DATA2(data) (((data) & 0x0ff) << 8)
+#define DSI_HDR_DATA1(data) ((data) & 0x0ff)
+#define DSI_HDR_WC(wc) ((wc) & 0x0ffff)
+
+#define MDSS_DSI_MRPS 0x04 /* Maximum Return Packet Size */
+
+#define MDSS_DSI_LEN 8 /* 4 x 4 - 6 - 2, bytes dcs header+crc-align */
+
+struct dsi_buf {
+ u32 *hdr; /* dsi host header */
+ char *start; /* buffer start addr */
+ char *end; /* buffer end addr */
+ int size; /* size of buffer */
+ char *data; /* buffer */
+ int len; /* data length */
+ dma_addr_t dmap; /* mapped dma addr */
+};
+
+/* dcs read/write */
+#define DTYPE_DCS_WRITE 0x05 /* short write, 0 parameter */
+#define DTYPE_DCS_WRITE1 0x15 /* short write, 1 parameter */
+#define DTYPE_DCS_READ 0x06 /* read */
+#define DTYPE_DCS_LWRITE 0x39 /* long write */
+
+/* generic read/write */
+#define DTYPE_GEN_WRITE 0x03 /* short write, 0 parameter */
+#define DTYPE_GEN_WRITE1 0x13 /* short write, 1 parameter */
+#define DTYPE_GEN_WRITE2 0x23 /* short write, 2 parameter */
+#define DTYPE_GEN_LWRITE 0x29 /* long write */
+#define DTYPE_GEN_READ 0x04 /* long read, 0 parameter */
+#define DTYPE_GEN_READ1 0x14 /* long read, 1 parameter */
+#define DTYPE_GEN_READ2 0x24 /* long read, 2 parameter */
+
+#define DTYPE_TEAR_ON 0x35 /* set tear on */
+#define DTYPE_MAX_PKTSIZE 0x37 /* set max packet size */
+#define DTYPE_NULL_PKT 0x09 /* null packet, no data */
+#define DTYPE_BLANK_PKT 0x19 /* blankiing packet, no data */
+
+#define DTYPE_CM_ON 0x02 /* color mode off */
+#define DTYPE_CM_OFF 0x12 /* color mode on */
+#define DTYPE_PERIPHERAL_OFF 0x22
+#define DTYPE_PERIPHERAL_ON 0x32
+
+/*
+ * dcs response
+ */
+#define DTYPE_ACK_ERR_RESP 0x02
+#define DTYPE_EOT_RESP 0x08 /* end of tx */
+#define DTYPE_GEN_READ1_RESP 0x11 /* 1 parameter, short */
+#define DTYPE_GEN_READ2_RESP 0x12 /* 2 parameter, short */
+#define DTYPE_GEN_LREAD_RESP 0x1a
+#define DTYPE_DCS_LREAD_RESP 0x1c
+#define DTYPE_DCS_READ1_RESP 0x21 /* 1 parameter, short */
+#define DTYPE_DCS_READ2_RESP 0x22 /* 2 parameter, short */
+
+struct dsi_ctrl_hdr {
+ char dtype; /* data type */
+ char last; /* last in chain */
+ char vc; /* virtual chan */
+ char ack; /* ask ACK from peripheral */
+ char wait; /* ms */
+ short dlen; /* 16 bits */
+} __packed;
+
+struct dsi_cmd_desc {
+ struct dsi_ctrl_hdr dchdr;
+ char *payload;
+};
+
+#define CMD_REQ_MAX 4
+#define CMD_REQ_RX 0x0001
+#define CMD_REQ_COMMIT 0x0002
+#define CMD_CLK_CTRL 0x0004
+#define CMD_REQ_NO_MAX_PKT_SIZE 0x0008
+
+struct dcs_cmd_req {
+ struct dsi_cmd_desc *cmds;
+ int cmds_cnt;
+ u32 flags;
+ int rlen; /* rx length */
+ char *rbuf; /* rx buf */
+ void (*cb)(int data);
+};
+
+struct dcs_cmd_list {
+ int put;
+ int get;
+ int tot;
+ struct dcs_cmd_req list[CMD_REQ_MAX];
+};
+
+char *mdss_dsi_buf_reserve(struct dsi_buf *dp, int len);
+char *mdss_dsi_buf_unreserve(struct dsi_buf *dp, int len);
+char *mdss_dsi_buf_push(struct dsi_buf *dp, int len);
+char *mdss_dsi_buf_reserve_hdr(struct dsi_buf *dp, int hlen);
+char *mdss_dsi_buf_init(struct dsi_buf *dp);
+int mdss_dsi_buf_alloc(struct dsi_buf *dp, int size);
+int mdss_dsi_cmd_dma_add(struct dsi_buf *dp, struct dsi_cmd_desc *cm);
+int mdss_dsi_short_read1_resp(struct dsi_buf *rp);
+int mdss_dsi_short_read2_resp(struct dsi_buf *rp);
+int mdss_dsi_long_read_resp(struct dsi_buf *rp);
+void mdss_dsi_set_tear_on(struct mdss_dsi_ctrl_pdata *ctrl);
+void mdss_dsi_set_tear_off(struct mdss_dsi_ctrl_pdata *ctrl);
+struct dcs_cmd_req *mdss_dsi_cmdlist_get(struct mdss_dsi_ctrl_pdata *ctrl);
+int mdss_dsi_cmdlist_put(struct mdss_dsi_ctrl_pdata *ctrl,
+ struct dcs_cmd_req *cmdreq);
+#endif
diff --git a/drivers/video/msm/mdss/mdss_dsi_host.c b/drivers/video/msm/mdss/mdss_dsi_host.c
index 750fbf3..65e6214 100644
--- a/drivers/video/msm/mdss/mdss_dsi_host.c
+++ b/drivers/video/msm/mdss/mdss_dsi_host.c
@@ -107,6 +107,7 @@
mutex_init(&ctrl->cmd_mutex);
mdss_dsi_buf_alloc(&ctrl->tx_buf, SZ_4K);
mdss_dsi_buf_alloc(&ctrl->rx_buf, SZ_4K);
+ ctrl->cmdlist_commit = mdss_dsi_cmdlist_commit;
if (dsi_event.inited == 0) {
@@ -199,576 +200,6 @@
spin_unlock(&ctrl->irq_lock);
}
-/*
- * mipi dsi buf mechanism
- */
-char *mdss_dsi_buf_reserve(struct dsi_buf *dp, int len)
-{
- dp->data += len;
- return dp->data;
-}
-
-char *mdss_dsi_buf_unreserve(struct dsi_buf *dp, int len)
-{
- dp->data -= len;
- return dp->data;
-}
-
-char *mdss_dsi_buf_push(struct dsi_buf *dp, int len)
-{
- dp->data -= len;
- dp->len += len;
- return dp->data;
-}
-
-char *mdss_dsi_buf_reserve_hdr(struct dsi_buf *dp, int hlen)
-{
- dp->hdr = (u32 *)dp->data;
- return mdss_dsi_buf_reserve(dp, hlen);
-}
-
-char *mdss_dsi_buf_init(struct dsi_buf *dp)
-{
- int off;
-
- dp->data = dp->start;
- off = (int)dp->data;
- /* 8 byte align */
- off &= 0x07;
- if (off)
- off = 8 - off;
- dp->data += off;
- dp->len = 0;
- return dp->data;
-}
-
-int mdss_dsi_buf_alloc(struct dsi_buf *dp, int size)
-{
-
- dp->start = dma_alloc_writecombine(NULL, size, &dp->dmap, GFP_KERNEL);
- if (dp->start == NULL) {
- pr_err("%s:%u\n", __func__, __LINE__);
- return -ENOMEM;
- }
-
- dp->end = dp->start + size;
- dp->size = size;
-
- if ((int)dp->start & 0x07)
- pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
-
- dp->data = dp->start;
- dp->len = 0;
- return size;
-}
-
-/*
- * mipi dsi generic long write
- */
-static int mdss_dsi_generic_lwrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- char *bp;
- u32 *hp;
- int i, len = 0;
-
- dchdr = &cm->dchdr;
- bp = mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
-
- /* fill up payload */
- if (cm->payload) {
- len = dchdr->dlen;
- len += 3;
- len &= ~0x03; /* multipled by 4 */
- for (i = 0; i < dchdr->dlen; i++)
- *bp++ = cm->payload[i];
-
- /* append 0xff to the end */
- for (; i < len; i++)
- *bp++ = 0xff;
-
- dp->len += len;
- }
-
- /* fill up header */
- hp = dp->hdr;
- *hp = 0;
- *hp = DSI_HDR_WC(dchdr->dlen);
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_LONG_PKT;
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_LWRITE);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- len += DSI_HOST_HDR_SIZE;
-
- return len;
-}
-
-/*
- * mipi dsi generic short write with 0, 1 2 parameters
- */
-static int mdss_dsi_generic_swrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
- int len;
-
- dchdr = &cm->dchdr;
- if (dchdr->dlen && cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return 0;
- }
-
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
-
- len = (dchdr->dlen > 2) ? 2 : dchdr->dlen;
-
- if (len == 1) {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_WRITE1);
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(0);
- } else if (len == 2) {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_WRITE2);
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(cm->payload[1]);
- } else {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_WRITE);
- *hp |= DSI_HDR_DATA1(0);
- *hp |= DSI_HDR_DATA2(0);
- }
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-/*
- * mipi dsi gerneric read with 0, 1 2 parameters
- */
-static int mdss_dsi_generic_read(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
- int len;
-
- dchdr = &cm->dchdr;
- if (dchdr->dlen && cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return 0;
- }
-
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_BTA;
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- len = (dchdr->dlen > 2) ? 2 : dchdr->dlen;
-
- if (len == 1) {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_READ1);
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(0);
- } else if (len == 2) {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_READ2);
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(cm->payload[1]);
- } else {
- *hp |= DSI_HDR_DTYPE(DTYPE_GEN_READ);
- *hp |= DSI_HDR_DATA1(0);
- *hp |= DSI_HDR_DATA2(0);
- }
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-/*
- * mipi dsi dcs long write
- */
-static int mdss_dsi_dcs_lwrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- char *bp;
- u32 *hp;
- int i, len = 0;
-
- dchdr = &cm->dchdr;
- bp = mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
-
- /*
- * fill up payload
- * dcs command byte (first byte) followed by payload
- */
- if (cm->payload) {
- len = dchdr->dlen;
- len += 3;
- len &= ~0x03; /* multipled by 4 */
- for (i = 0; i < dchdr->dlen; i++)
- *bp++ = cm->payload[i];
-
- /* append 0xff to the end */
- for (; i < len; i++)
- *bp++ = 0xff;
-
- dp->len += len;
- }
-
- /* fill up header */
- hp = dp->hdr;
- *hp = 0;
- *hp = DSI_HDR_WC(dchdr->dlen);
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_LONG_PKT;
- *hp |= DSI_HDR_DTYPE(DTYPE_DCS_LWRITE);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
-
- len += DSI_HOST_HDR_SIZE;
- return len;
-}
-
-/*
- * mipi dsi dcs short write with 0 parameters
- */
-static int mdss_dsi_dcs_swrite(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
- int len;
-
- dchdr = &cm->dchdr;
- if (cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return -EINVAL;
- }
-
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- if (dchdr->ack) /* ask ACK trigger msg from peripeheral */
- *hp |= DSI_HDR_BTA;
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- len = (dchdr->dlen > 1) ? 1 : dchdr->dlen;
-
- *hp |= DSI_HDR_DTYPE(DTYPE_DCS_WRITE);
- *hp |= DSI_HDR_DATA1(cm->payload[0]); /* dcs command byte */
- *hp |= DSI_HDR_DATA2(0);
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-/*
- * mipi dsi dcs short write with 1 parameters
- */
-static int mdss_dsi_dcs_swrite1(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
-
- dchdr = &cm->dchdr;
- if (dchdr->dlen < 2 || cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return -EINVAL;
- }
-
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- if (dchdr->ack) /* ask ACK trigger msg from peripeheral */
- *hp |= DSI_HDR_BTA;
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- *hp |= DSI_HDR_DTYPE(DTYPE_DCS_WRITE1);
- *hp |= DSI_HDR_DATA1(cm->payload[0]); /* dcs comamnd byte */
- *hp |= DSI_HDR_DATA2(cm->payload[1]); /* parameter */
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-/*
- * mipi dsi dcs read with 0 parameters
- */
-
-static int mdss_dsi_dcs_read(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
-
- dchdr = &cm->dchdr;
- if (cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return -EINVAL;
- }
-
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_BTA;
- *hp |= DSI_HDR_DTYPE(DTYPE_DCS_READ);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- *hp |= DSI_HDR_DATA1(cm->payload[0]); /* dcs command byte */
- *hp |= DSI_HDR_DATA2(0);
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-static int mdss_dsi_cm_on(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
-
- dchdr = &cm->dchdr;
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_CM_ON);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-static int mdss_dsi_cm_off(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
-
- dchdr = &cm->dchdr;
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_CM_OFF);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-static int mdss_dsi_peripheral_on(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
-
- dchdr = &cm->dchdr;
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_PERIPHERAL_ON);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-static int mdss_dsi_peripheral_off(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
-
- dchdr = &cm->dchdr;
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_PERIPHERAL_OFF);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-static int mdss_dsi_set_max_pktsize(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
-
- dchdr = &cm->dchdr;
- if (cm->payload == 0) {
- pr_err("%s: NO payload error\n", __func__);
- return 0;
- }
-
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_MAX_PKTSIZE);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- *hp |= DSI_HDR_DATA1(cm->payload[0]);
- *hp |= DSI_HDR_DATA2(cm->payload[1]);
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-static int mdss_dsi_null_pkt(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
-
- dchdr = &cm->dchdr;
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp = DSI_HDR_WC(dchdr->dlen);
- *hp |= DSI_HDR_LONG_PKT;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_NULL_PKT);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-static int mdss_dsi_blank_pkt(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- u32 *hp;
-
- dchdr = &cm->dchdr;
- mdss_dsi_buf_reserve_hdr(dp, DSI_HOST_HDR_SIZE);
- hp = dp->hdr;
- *hp = 0;
- *hp = DSI_HDR_WC(dchdr->dlen);
- *hp |= DSI_HDR_LONG_PKT;
- *hp |= DSI_HDR_VC(dchdr->vc);
- *hp |= DSI_HDR_DTYPE(DTYPE_BLANK_PKT);
- if (dchdr->last)
- *hp |= DSI_HDR_LAST;
-
- mdss_dsi_buf_push(dp, DSI_HOST_HDR_SIZE);
- return DSI_HOST_HDR_SIZE; /* 4 bytes */
-}
-
-/*
- * prepare cmd buffer to be txed
- */
-int mdss_dsi_cmd_dma_add(struct dsi_buf *dp, struct dsi_cmd_desc *cm)
-{
- struct dsi_ctrl_hdr *dchdr;
- int len = 0;
-
- dchdr = &cm->dchdr;
-
- switch (dchdr->dtype) {
- case DTYPE_GEN_WRITE:
- case DTYPE_GEN_WRITE1:
- case DTYPE_GEN_WRITE2:
- len = mdss_dsi_generic_swrite(dp, cm);
- break;
- case DTYPE_GEN_LWRITE:
- len = mdss_dsi_generic_lwrite(dp, cm);
- break;
- case DTYPE_GEN_READ:
- case DTYPE_GEN_READ1:
- case DTYPE_GEN_READ2:
- len = mdss_dsi_generic_read(dp, cm);
- break;
- case DTYPE_DCS_LWRITE:
- len = mdss_dsi_dcs_lwrite(dp, cm);
- break;
- case DTYPE_DCS_WRITE:
- len = mdss_dsi_dcs_swrite(dp, cm);
- break;
- case DTYPE_DCS_WRITE1:
- len = mdss_dsi_dcs_swrite1(dp, cm);
- break;
- case DTYPE_DCS_READ:
- len = mdss_dsi_dcs_read(dp, cm);
- break;
- case DTYPE_MAX_PKTSIZE:
- len = mdss_dsi_set_max_pktsize(dp, cm);
- break;
- case DTYPE_NULL_PKT:
- len = mdss_dsi_null_pkt(dp, cm);
- break;
- case DTYPE_BLANK_PKT:
- len = mdss_dsi_blank_pkt(dp, cm);
- break;
- case DTYPE_CM_ON:
- len = mdss_dsi_cm_on(dp, cm);
- break;
- case DTYPE_CM_OFF:
- len = mdss_dsi_cm_off(dp, cm);
- break;
- case DTYPE_PERIPHERAL_ON:
- len = mdss_dsi_peripheral_on(dp, cm);
- break;
- case DTYPE_PERIPHERAL_OFF:
- len = mdss_dsi_peripheral_off(dp, cm);
- break;
- default:
- pr_debug("%s: dtype=%x NOT supported\n",
- __func__, dchdr->dtype);
- break;
-
- }
-
- return len;
-}
-
-/*
- * mdss_dsi_short_read1_resp: 1 parameter
- */
-static int mdss_dsi_short_read1_resp(struct dsi_buf *rp)
-{
- /* strip out dcs type */
- rp->data++;
- rp->len = 1;
- return rp->len;
-}
-
-/*
- * mdss_dsi_short_read2_resp: 2 parameter
- */
-static int mdss_dsi_short_read2_resp(struct dsi_buf *rp)
-{
- /* strip out dcs type */
- rp->data++;
- rp->len = 2;
- return rp->len;
-}
-
-static int mdss_dsi_long_read_resp(struct dsi_buf *rp)
-{
- /* strip out dcs header */
- rp->data += 4;
- rp->len -= 4;
- return rp->len;
-}
-
void mdss_dsi_cmd_test_pattern(struct mdss_panel_data *pdata)
{
struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
@@ -1202,40 +633,6 @@
return ret;
}
-static char set_tear_on[2] = {0x35, 0x00};
-static struct dsi_cmd_desc dsi_tear_on_cmd = {
- {DTYPE_DCS_WRITE1, 1, 0, 0, 0, sizeof(set_tear_on)}, set_tear_on};
-
-static char set_tear_off[2] = {0x34, 0x00};
-static struct dsi_cmd_desc dsi_tear_off_cmd = {
- {DTYPE_DCS_WRITE, 1, 0, 0, 0, sizeof(set_tear_off)}, set_tear_off};
-
-void mdss_dsi_set_tear_on(struct mdss_dsi_ctrl_pdata *ctrl)
-{
- struct dcs_cmd_req cmdreq;
-
- cmdreq.cmds = &dsi_tear_on_cmd;
- cmdreq.cmds_cnt = 1;
- cmdreq.flags = CMD_REQ_COMMIT;
- cmdreq.rlen = 0;
- cmdreq.cb = NULL;
-
- mdss_dsi_cmdlist_put(ctrl, &cmdreq);
-}
-
-void mdss_dsi_set_tear_off(struct mdss_dsi_ctrl_pdata *ctrl)
-{
- struct dcs_cmd_req cmdreq;
-
- cmdreq.cmds = &dsi_tear_off_cmd;
- cmdreq.cmds_cnt = 1;
- cmdreq.flags = CMD_REQ_COMMIT;
- cmdreq.rlen = 0;
- cmdreq.cb = NULL;
-
- mdss_dsi_cmdlist_put(ctrl, &cmdreq);
-}
-
int mdss_dsi_cmd_reg_tx(u32 data,
unsigned char *ctrl_base)
{
@@ -1750,45 +1147,63 @@
/* wait until DMA finishes the current job */
pr_debug("%s: pending pid=%d\n",
__func__, current->pid);
- wait_for_completion(&ctrl->mdp_comp);
+ if (!wait_for_completion_timeout(&ctrl->mdp_comp,
+ msecs_to_jiffies(DMA_TX_TIMEOUT)))
+ pr_err("%s: timeout error\n", __func__);
}
pr_debug("%s: done pid=%d\n",
__func__, current->pid);
}
-void mdss_dsi_cmdlist_tx(struct mdss_dsi_ctrl_pdata *ctrl,
+int mdss_dsi_cmdlist_tx(struct mdss_dsi_ctrl_pdata *ctrl,
struct dcs_cmd_req *req)
{
- int ret;
+ int ret, ret_val = -EINVAL;
ret = mdss_dsi_cmds_tx(ctrl, req->cmds, req->cmds_cnt);
+ if (!IS_ERR_VALUE(ret))
+ ret_val = 0;
+
if (req->cb)
req->cb(ret);
+ return ret_val;
}
-void mdss_dsi_cmdlist_rx(struct mdss_dsi_ctrl_pdata *ctrl,
+int mdss_dsi_cmdlist_rx(struct mdss_dsi_ctrl_pdata *ctrl,
struct dcs_cmd_req *req)
{
struct dsi_buf *rp;
- int len = 0;
+ int len = 0, ret = -EINVAL;
if (req->rbuf) {
rp = &ctrl->rx_buf;
len = mdss_dsi_cmds_rx(ctrl, req->cmds, req->rlen);
memcpy(req->rbuf, rp->data, rp->len);
+ /*
+ * For dual DSI cases, early return of controller - 0
+ * is valid. Hence, for those cases the return value
+ * is zero even though we don't send any commands.
+ *
+ */
+ if ((ctrl->shared_pdata.broadcast_enable &&
+ ctrl->ndx == DSI_CTRL_0) || (len != 0))
+ ret = 0;
} else {
pr_err("%s: No rx buffer provided\n", __func__);
}
if (req->cb)
req->cb(len);
+
+ return ret;
}
-void mdss_dsi_cmdlist_commit(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp)
+int mdss_dsi_cmdlist_commit(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp)
{
struct dcs_cmd_req *req;
+ int ret = -EINVAL;
mutex_lock(&ctrl->cmd_mutex);
req = mdss_dsi_cmdlist_get(ctrl);
@@ -1813,9 +1228,9 @@
mdss_dsi_clk_ctrl(ctrl, 1);
if (req->flags & CMD_REQ_RX)
- mdss_dsi_cmdlist_rx(ctrl, req);
+ ret = mdss_dsi_cmdlist_rx(ctrl, req);
else
- mdss_dsi_cmdlist_tx(ctrl, req);
+ ret = mdss_dsi_cmdlist_tx(ctrl, req);
mdss_dsi_clk_ctrl(ctrl, 0);
mdss_bus_bandwidth_ctrl(0);
@@ -1826,63 +1241,9 @@
mdss_dsi_cmd_mdp_start(ctrl);
mutex_unlock(&ctrl->cmd_mutex);
-}
-
-/*
- * mdss_dsi_cmd_get: ctrl->cmd_mutex acquired by caller
- */
-struct dcs_cmd_req *mdss_dsi_cmdlist_get(struct mdss_dsi_ctrl_pdata *ctrl)
-{
- struct dcs_cmd_list *clist;
- struct dcs_cmd_req *req = NULL;
-
- clist = &ctrl->cmdlist;
- if (clist->get != clist->put) {
- req = &clist->list[clist->get];
- clist->get++;
- clist->get %= CMD_REQ_MAX;
- clist->tot--;
- pr_debug("%s: tot=%d put=%d get=%d\n", __func__,
- clist->tot, clist->put, clist->get);
- }
- return req;
-}
-
-int mdss_dsi_cmdlist_put(struct mdss_dsi_ctrl_pdata *ctrl,
- struct dcs_cmd_req *cmdreq)
-{
- struct dcs_cmd_req *req;
- struct dcs_cmd_list *clist;
- int ret = 0;
-
- mutex_lock(&ctrl->cmd_mutex);
- clist = &ctrl->cmdlist;
- req = &clist->list[clist->put];
- *req = *cmdreq;
- clist->put++;
- clist->put %= CMD_REQ_MAX;
- clist->tot++;
- if (clist->put == clist->get) {
- /* drop the oldest one */
- pr_debug("%s: DROP, tot=%d put=%d get=%d\n", __func__,
- clist->tot, clist->put, clist->get);
- clist->get++;
- clist->get %= CMD_REQ_MAX;
- clist->tot--;
- }
- mutex_unlock(&ctrl->cmd_mutex);
-
- ret++;
- pr_debug("%s: tot=%d put=%d get=%d\n", __func__,
- clist->tot, clist->put, clist->get);
-
- if (req->flags & CMD_REQ_COMMIT)
- mdss_dsi_cmdlist_commit(ctrl, 0);
-
return ret;
}
-
static void dsi_send_events(struct mdss_dsi_ctrl_pdata *ctrl, u32 events)
{
struct dsi_event_q *evq;
@@ -1970,6 +1331,8 @@
if (status) {
MIPI_OUTP(base + 0x0068, status);
+ /* Writing of an extra 0 needed to clear error bits */
+ MIPI_OUTP(base + 0x0068, 0);
pr_err("%s: status=%x\n", __func__, status);
}
}
diff --git a/drivers/video/msm/mdss/mdss_dsi_panel.c b/drivers/video/msm/mdss/mdss_dsi_panel.c
index 8c04940..06f6959 100644
--- a/drivers/video/msm/mdss/mdss_dsi_panel.c
+++ b/drivers/video/msm/mdss/mdss_dsi_panel.c
@@ -30,29 +30,10 @@
void mdss_dsi_panel_pwm_cfg(struct mdss_dsi_ctrl_pdata *ctrl)
{
- int ret;
-
- if (!gpio_is_valid(ctrl->pwm_pmic_gpio)) {
- pr_err("%s: pwm_pmic_gpio=%d Invalid\n", __func__,
- ctrl->pwm_pmic_gpio);
- ctrl->pwm_pmic_gpio = -1;
- return;
- }
-
- ret = gpio_request(ctrl->pwm_pmic_gpio, "disp_pwm");
- if (ret) {
- pr_err("%s: pwm_pmic_gpio=%d request failed\n", __func__,
- ctrl->pwm_pmic_gpio);
- ctrl->pwm_pmic_gpio = -1;
- return;
- }
-
ctrl->pwm_bl = pwm_request(ctrl->pwm_lpg_chan, "lcd-bklt");
if (ctrl->pwm_bl == NULL || IS_ERR(ctrl->pwm_bl)) {
- pr_err("%s: lpg_chan=%d pwm request failed", __func__,
- ctrl->pwm_lpg_chan);
- gpio_free(ctrl->pwm_pmic_gpio);
- ctrl->pwm_pmic_gpio = -1;
+ pr_err("%s: Error: lpg_chan=%d pwm request failed",
+ __func__, ctrl->pwm_lpg_chan);
}
}
@@ -366,6 +347,49 @@
return 0;
}
+static void mdss_dsi_parse_lane_swap(struct device_node *np, char *dlane_swap)
+{
+ const char *data;
+
+ *dlane_swap = DSI_LANE_MAP_0123;
+ data = of_get_property(np, "qcom,mdss-dsi-lane-map", NULL);
+ if (data) {
+ if (!strcmp(data, "lane_map_3012"))
+ *dlane_swap = DSI_LANE_MAP_3012;
+ else if (!strcmp(data, "lane_map_2301"))
+ *dlane_swap = DSI_LANE_MAP_2301;
+ else if (!strcmp(data, "lane_map_1230"))
+ *dlane_swap = DSI_LANE_MAP_1230;
+ else if (!strcmp(data, "lane_map_0321"))
+ *dlane_swap = DSI_LANE_MAP_0321;
+ else if (!strcmp(data, "lane_map_1032"))
+ *dlane_swap = DSI_LANE_MAP_1032;
+ else if (!strcmp(data, "lane_map_2103"))
+ *dlane_swap = DSI_LANE_MAP_2103;
+ else if (!strcmp(data, "lane_map_3210"))
+ *dlane_swap = DSI_LANE_MAP_3210;
+ }
+}
+
+static void mdss_dsi_parse_trigger(struct device_node *np, char *trigger,
+ char *trigger_key)
+{
+ const char *data;
+
+ *trigger = DSI_CMD_TRIGGER_SW;
+ data = of_get_property(np, trigger_key, NULL);
+ if (data) {
+ if (!strcmp(data, "none"))
+ *trigger = DSI_CMD_TRIGGER_NONE;
+ else if (!strcmp(data, "trigger_te"))
+ *trigger = DSI_CMD_TRIGGER_TE;
+ else if (!strcmp(data, "trigger_sw_seof"))
+ *trigger = DSI_CMD_TRIGGER_SW_SEOF;
+ else if (!strcmp(data, "trigger_sw_te"))
+ *trigger = DSI_CMD_TRIGGER_SW_TE;
+ }
+}
+
static int mdss_dsi_parse_dcs_cmds(struct device_node *np,
struct dsi_panel_cmds *pcmds, char *cmd_key, char *link_key)
@@ -398,7 +422,7 @@
if (dchdr->dlen > len) {
pr_err("%s: dtsi cmd=%x error, len=%d",
__func__, dchdr->dtype, dchdr->dlen);
- return -ENOMEM;
+ goto exit_free;
}
bp += sizeof(*dchdr);
len -= sizeof(*dchdr);
@@ -410,14 +434,13 @@
if (len != 0) {
pr_err("%s: dcs_cmd=%x len=%d error!",
__func__, buf[0], blen);
- kfree(buf);
- return -ENOMEM;
+ goto exit_free;
}
pcmds->cmds = kzalloc(cnt * sizeof(struct dsi_cmd_desc),
GFP_KERNEL);
if (!pcmds->cmds)
- return -ENOMEM;
+ goto exit_free;
pcmds->cmd_cnt = cnt;
pcmds->buf = buf;
@@ -445,6 +468,10 @@
pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt, pcmds->link_state);
return 0;
+
+exit_free:
+ kfree(buf);
+ return -ENOMEM;
}
@@ -652,8 +679,10 @@
data = of_get_property(np, "qcom,mdss-dsi-panel-type", NULL);
if (data && !strncmp(data, "dsi_cmd_mode", 12))
pinfo->mipi.mode = DSI_CMD_MODE;
- rc = of_property_read_u32(np, "qcom,mdss-dsi-pixel-packing", &tmp);
- tmp = (!rc ? tmp : 0);
+ tmp = 0;
+ data = of_get_property(np, "qcom,mdss-dsi-pixel-packing", NULL);
+ if (data && !strcmp(data, "loose"))
+ tmp = 1;
rc = mdss_panel_dt_get_dst_fmt(pinfo->bpp,
pinfo->mipi.mode, tmp,
&(pinfo->mipi.dst_format));
@@ -761,10 +790,14 @@
"qcom,mdss-dsi-bllp-power-mode");
pinfo->mipi.eof_bllp_power_stop = of_property_read_bool(
np, "qcom,mdss-dsi-bllp-eof-power-mode");
- rc = of_property_read_u32(np,
- "qcom,mdss-dsi-traffic-mode", &tmp);
- pinfo->mipi.traffic_mode =
- (!rc ? tmp : DSI_NON_BURST_SYNCH_PULSE);
+ pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_PULSE;
+ data = of_get_property(np, "qcom,mdss-dsi-traffic-mode", NULL);
+ if (data) {
+ if (!strcmp(data, "non_burst_sync_event"))
+ pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
+ else if (!strcmp(data, "burst_mode"))
+ pinfo->mipi.traffic_mode = DSI_BURST_MODE;
+ }
rc = of_property_read_u32(np,
"qcom,mdss-dsi-te-dcs-command", &tmp);
pinfo->mipi.insert_dcs_cmd =
@@ -783,8 +816,20 @@
(!rc ? tmp : 1);
rc = of_property_read_u32(np, "qcom,mdss-dsi-virtual-channel-id", &tmp);
pinfo->mipi.vc = (!rc ? tmp : 0);
- rc = of_property_read_u32(np, "qcom,mdss-dsi-color-order", &tmp);
- pinfo->mipi.rgb_swap = (!rc ? tmp : DSI_RGB_SWAP_RGB);
+ pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
+ data = of_get_property(np, "mdss-dsi-color-order", NULL);
+ if (data) {
+ if (!strcmp(data, "rgb_swap_rbg"))
+ pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RBG;
+ else if (!strcmp(data, "rgb_swap_bgr"))
+ pinfo->mipi.rgb_swap = DSI_RGB_SWAP_BGR;
+ else if (!strcmp(data, "rgb_swap_brg"))
+ pinfo->mipi.rgb_swap = DSI_RGB_SWAP_BRG;
+ else if (!strcmp(data, "rgb_swap_grb"))
+ pinfo->mipi.rgb_swap = DSI_RGB_SWAP_GRB;
+ else if (!strcmp(data, "rgb_swap_gbr"))
+ pinfo->mipi.rgb_swap = DSI_RGB_SWAP_GBR;
+ }
pinfo->mipi.data_lane0 = of_property_read_bool(np,
"qcom,mdss-dsi-lane-0-state");
pinfo->mipi.data_lane1 = of_property_read_bool(np,
@@ -794,9 +839,6 @@
pinfo->mipi.data_lane3 = of_property_read_bool(np,
"qcom,mdss-dsi-lane-3-state");
- rc = of_property_read_u32(np, "qcom,mdss-dsi-lane-map", &tmp);
- pinfo->mipi.dlane_swap = (!rc ? tmp : 0);
-
rc = of_property_read_u32(np, "qcom,mdss-dsi-t-clk-pre", &tmp);
pinfo->mipi.t_clk_pre = (!rc ? tmp : 0x24);
rc = of_property_read_u32(np, "qcom,mdss-dsi-t-clk-post", &tmp);
@@ -805,26 +847,7 @@
rc = of_property_read_u32(np, "qcom,mdss-dsi-stream", &tmp);
pinfo->mipi.stream = (!rc ? tmp : 0);
- rc = of_property_read_u32(np, "qcom,mdss-dsi-mdp-trigger", &tmp);
- pinfo->mipi.mdp_trigger =
- (!rc ? tmp : DSI_CMD_TRIGGER_SW);
- if (pinfo->mipi.mdp_trigger > 6) {
- pr_err("%s:%d, Invalid mdp trigger. Forcing to sw trigger",
- __func__, __LINE__);
- pinfo->mipi.mdp_trigger =
- DSI_CMD_TRIGGER_SW;
- }
-
- rc = of_property_read_u32(np, "qcom,mdss-dsi-dma-trigger", &tmp);
- pinfo->mipi.dma_trigger =
- (!rc ? tmp : DSI_CMD_TRIGGER_SW);
- if (pinfo->mipi.dma_trigger > 6) {
- pr_err("%s:%d, Invalid dma trigger. Forcing to sw trigger",
- __func__, __LINE__);
- pinfo->mipi.dma_trigger =
- DSI_CMD_TRIGGER_SW;
- }
- data = of_get_property(np, "qcom,mdss-dsi-panel-mode-gpio-state", &tmp);
+ data = of_get_property(np, "qcom,mdss-dsi-panel-mode-gpio-state", NULL);
if (data) {
if (!strcmp(data, "high"))
pinfo->mode_gpio_state = MODE_GPIO_HIGH;
@@ -834,9 +857,9 @@
pinfo->mode_gpio_state = MODE_GPIO_NOT_VALID;
}
- rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-frame-rate", &tmp);
+ rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-framerate", &tmp);
pinfo->mipi.frame_rate = (!rc ? tmp : 60);
- rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-clock-rate", &tmp);
+ rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-clockrate", &tmp);
pinfo->clk_rate = (!rc ? tmp : 0);
data = of_get_property(np, "qcom,mdss-dsi-panel-timings", &len);
if ((!data) || (len != 12)) {
@@ -854,6 +877,14 @@
mdss_dsi_parse_fbc_params(np, pinfo);
+ mdss_dsi_parse_trigger(np, &(pinfo->mipi.mdp_trigger),
+ "qcom,mdss-dsi-mdp-trigger");
+
+ mdss_dsi_parse_trigger(np, &(pinfo->mipi.dma_trigger),
+ "qcom,mdss-dsi-dma-trigger");
+
+ mdss_dsi_parse_lane_swap(np, &(pinfo->mipi.dlane_swap));
+
mdss_dsi_parse_reset_seq(np, pinfo->rst_seq, &(pinfo->rst_seq_len),
"qcom,mdss-dsi-reset-sequence");
diff --git a/drivers/video/msm/mdss/mdss_edp.c b/drivers/video/msm/mdss/mdss_edp.c
index 042491d..bb27e6b 100644
--- a/drivers/video/msm/mdss/mdss_edp.c
+++ b/drivers/video/msm/mdss/mdss_edp.c
@@ -228,38 +228,273 @@
}
}
-void mdss_edp_config_sync(unsigned char *base)
+int mdss_edp_mainlink_ready(struct mdss_edp_drv_pdata *ep, u32 which)
+{
+ u32 data;
+ int cnt = 10;
+
+ while (--cnt) {
+ data = edp_read(ep->base + 0x84); /* EDP_MAINLINK_READY */
+ if (data & which) {
+ pr_debug("%s: which=%x ready\n", __func__, which);
+ return 1;
+ }
+ usleep(1000);
+ }
+ pr_err("%s: which=%x NOT ready\n", __func__, which);
+
+ return 0;
+}
+
+void mdss_edp_mainlink_reset(struct mdss_edp_drv_pdata *ep)
+{
+ edp_write(ep->base + 0x04, 0x02); /* EDP_MAINLINK_CTRL */
+ usleep(1000);
+ edp_write(ep->base + 0x04, 0); /* EDP_MAINLINK_CTRL */
+}
+
+void mdss_edp_mainlink_ctrl(struct mdss_edp_drv_pdata *ep, int enable)
+{
+ u32 data;
+
+ data = edp_read(ep->base + 0x04);
+ data &= ~BIT(0);
+
+ if (enable)
+ data |= 0x1;
+
+ edp_write(ep->base + 0x04, data);
+}
+
+void mdss_edp_state_ctrl(struct mdss_edp_drv_pdata *ep, u32 state)
+{
+ edp_write(ep->base + EDP_STATE_CTRL, state);
+}
+
+void mdss_edp_aux_reset(struct mdss_edp_drv_pdata *ep)
+{
+ /* reset AUX */
+ edp_write(ep->base + 0x300, BIT(1)); /* EDP_AUX_CTRL */
+ usleep(1000);
+ edp_write(ep->base + 0x300, 0); /* EDP_AUX_CTRL */
+}
+
+void mdss_edp_aux_ctrl(struct mdss_edp_drv_pdata *ep, int enable)
+{
+ u32 data;
+
+ data = edp_read(ep->base + 0x300);
+ if (enable)
+ data |= 0x01;
+ else
+ data |= ~0x01;
+ edp_write(ep->base + 0x300, data); /* EDP_AUX_CTRL */
+}
+
+void mdss_edp_phy_pll_reset(struct mdss_edp_drv_pdata *ep)
+{
+ /* EDP_PHY_CTRL */
+ edp_write(ep->base + 0x74, 0x005); /* bit 0, 2 */
+ usleep(1000);
+ edp_write(ep->base + 0x74, 0x000); /* EDP_PHY_CTRL */
+}
+
+int mdss_edp_phy_pll_ready(struct mdss_edp_drv_pdata *ep)
+{
+ int cnt;
+ u32 status = 0;
+
+ cnt = 100;
+ while (--cnt) {
+ status = edp_read(ep->base + 0x6c0);
+ if (status & 0x01)
+ break;
+ usleep(100);
+ }
+
+ pr_debug("%s: PLL cnt=%d status=%x\n", __func__, cnt, (int)status);
+
+ if (cnt <= 0) {
+ pr_err("%s: PLL NOT ready\n", __func__);
+ return 0;
+ } else
+ return 1;
+}
+
+int mdss_edp_phy_ready(struct mdss_edp_drv_pdata *ep)
+{
+ u32 status;
+
+ status = edp_read(ep->base + 0x598);
+ status &= 0x01;
+
+ return status;
+}
+
+void mdss_edp_phy_power_ctrl(struct mdss_edp_drv_pdata *ep, int enable)
+{
+ if (enable) {
+ /* EDP_PHY_EDPPHY_GLB_PD_CTL */
+ edp_write(ep->base + 0x52c, 0x3f);
+ /* EDP_PHY_EDPPHY_GLB_CFG */
+ edp_write(ep->base + 0x528, 0x1);
+ /* EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG */
+ edp_write(ep->base + 0x620, 0xf);
+ } else {
+ /* EDP_PHY_EDPPHY_GLB_PD_CTL */
+ edp_write(ep->base + 0x52c, 0xc0);
+ }
+}
+
+void mdss_edp_lane_power_ctrl(struct mdss_edp_drv_pdata *ep, int up)
+{
+ int i, off, max_lane;
+ u32 data;
+
+ max_lane = ep->lane_cnt;
+
+ if (up)
+ data = 0; /* power up */
+ else
+ data = 0x7; /* power down */
+
+ /* EDP_PHY_EDPPHY_LNn_PD_CTL */
+ for (i = 0; i < max_lane; i++) {
+ off = 0x40 * i;
+ edp_write(ep->base + 0x404 + off , data);
+ }
+
+ /* power down un used lane */
+ data = 0x7; /* power down */
+ for (i = max_lane; i < EDP_MAX_LANE; i++) {
+ off = 0x40 * i;
+ edp_write(ep->base + 0x404 + off , data);
+ }
+}
+
+void mdss_edp_clock_synchrous(struct mdss_edp_drv_pdata *ep, int sync)
+{
+ u32 data;
+
+ /* EDP_MISC1_MISC0 */
+ data = edp_read(ep->base + 0x02c);
+
+ if (sync)
+ data |= 0x01;
+ else
+ data &= ~0x01;
+
+ /* EDP_MISC1_MISC0 */
+ edp_write(ep->base + 0x2c, data);
+}
+
+/* voltage mode and pre emphasis cfg */
+void mdss_edp_phy_vm_pe_init(struct mdss_edp_drv_pdata *ep)
+{
+ /* EDP_PHY_EDPPHY_GLB_VM_CFG0 */
+ edp_write(ep->base + 0x510, 0x3); /* vm only */
+ /* EDP_PHY_EDPPHY_GLB_VM_CFG1 */
+ edp_write(ep->base + 0x514, 0x64);
+ /* EDP_PHY_EDPPHY_GLB_MISC9 */
+ edp_write(ep->base + 0x518, 0x6c);
+}
+
+void mdss_edp_config_ctrl(struct mdss_edp_drv_pdata *ep)
+{
+ struct dpcd_cap *cap;
+ struct display_timing_desc *dp;
+ u32 data = 0;
+
+ dp = &ep->edid.timing[0];
+
+ cap = &ep->dpcd;
+
+ data = ep->lane_cnt - 1;
+ data <<= 4;
+
+ if (cap->enhanced_frame)
+ data |= 0x40;
+
+ if (ep->edid.color_depth == 8) {
+ /* 0 == 6 bits, 1 == 8 bits */
+ data |= 0x100; /* bit 8 */
+ }
+
+ if (!dp->interlaced) /* progressive */
+ data |= 0x04;
+
+ data |= 0x03; /* sycn clock & static Mvid */
+
+ edp_write(ep->base + 0xc, data); /* EDP_CONFIGURATION_CTRL */
+}
+
+static void mdss_edp_sw_mvid_nvid(struct mdss_edp_drv_pdata *ep)
+{
+ edp_write(ep->base + 0x14, 0x13b); /* EDP_SOFTWARE_MVID */
+ edp_write(ep->base + 0x18, 0x266); /* EDP_SOFTWARE_NVID */
+}
+
+static void mdss_edp_timing_cfg(struct mdss_edp_drv_pdata *ep)
+{
+ struct mdss_panel_info *pinfo;
+ u32 total_ver, total_hor;
+ u32 data;
+
+ pinfo = &ep->panel_data.panel_info;
+
+ pr_debug("%s: width=%d hporch= %d %d %d\n", __func__,
+ pinfo->xres, pinfo->lcdc.h_back_porch,
+ pinfo->lcdc.h_front_porch, pinfo->lcdc.h_pulse_width);
+
+ pr_debug("%s: height=%d vporch= %d %d %d\n", __func__,
+ pinfo->yres, pinfo->lcdc.v_back_porch,
+ pinfo->lcdc.v_front_porch, pinfo->lcdc.v_pulse_width);
+
+ total_hor = pinfo->xres + pinfo->lcdc.h_back_porch +
+ pinfo->lcdc.h_front_porch + pinfo->lcdc.h_pulse_width;
+
+ total_ver = pinfo->yres + pinfo->lcdc.v_back_porch +
+ pinfo->lcdc.v_front_porch + pinfo->lcdc.v_pulse_width;
+
+ data = total_ver;
+ data <<= 16;
+ data |= total_hor;
+ edp_write(ep->base + 0x1c, data); /* EDP_TOTAL_HOR_VER */
+
+ data = (pinfo->lcdc.v_back_porch + pinfo->lcdc.v_pulse_width);
+ data <<= 16;
+ data |= (pinfo->lcdc.h_back_porch + pinfo->lcdc.h_pulse_width);
+ edp_write(ep->base + 0x20, data); /* EDP_START_HOR_VER_FROM_SYNC */
+
+ data = pinfo->lcdc.v_pulse_width;
+ data <<= 16;
+ data |= pinfo->lcdc.h_pulse_width;
+ edp_write(ep->base + 0x24, data); /* EDP_HSYNC_VSYNC_WIDTH_POLARITY */
+
+ data = pinfo->yres;
+ data <<= 16;
+ data |= pinfo->xres;
+ edp_write(ep->base + 0x28, data); /* EDP_ACTIVE_HOR_VER */
+}
+
+int mdss_edp_wait4train(struct mdss_edp_drv_pdata *edp_drv)
{
int ret = 0;
- ret = edp_read(base + 0xc); /* EDP_CONFIGURATION_CTRL */
- ret &= ~0x733;
- ret |= (0x55 & 0x733);
- edp_write(base + 0xc, ret);
- edp_write(base + 0xc, 0x55); /* EDP_CONFIGURATION_CTRL */
-}
+ if (edp_drv->cont_splash)
+ return ret;
-static void mdss_edp_config_sw_div(unsigned char *base)
-{
- edp_write(base + 0x14, 0x13b); /* EDP_SOFTWARE_MVID */
- edp_write(base + 0x18, 0x266); /* EDP_SOFTWARE_NVID */
-}
+ ret = wait_for_completion_timeout(&edp_drv->video_comp, 30);
+ if (ret <= 0) {
+ pr_err("%s: Link Train timedout\n", __func__);
+ ret = -EINVAL;
+ } else {
+ ret = 0;
+ }
-static void mdss_edp_config_static_mdiv(unsigned char *base)
-{
- int ret = 0;
+ pr_debug("%s:\n", __func__);
- ret = edp_read(base + 0xc); /* EDP_CONFIGURATION_CTRL */
- edp_write(base + 0xc, ret | 0x2); /* EDP_CONFIGURATION_CTRL */
- edp_write(base + 0xc, 0x57); /* EDP_CONFIGURATION_CTRL */
-}
-
-static void mdss_edp_enable(unsigned char *base, int enable)
-{
- edp_write(base + 0x8, 0x0); /* EDP_STATE_CTRL */
- edp_write(base + 0x8, 0x40); /* EDP_STATE_CTRL */
- edp_write(base + 0x94, enable); /* EDP_TIMING_ENGINE_EN */
- edp_write(base + 0x4, enable); /* EDP_MAINLINK_CTRL */
+ return ret;
}
static void mdss_edp_irq_enable(struct mdss_edp_drv_pdata *edp_drv);
@@ -278,73 +513,53 @@
edp_drv = container_of(pdata, struct mdss_edp_drv_pdata,
panel_data);
- pr_debug("%s:+\n", __func__);
- if (edp_drv->train_start == 0)
- edp_drv->train_start++;
+ pr_debug("%s:+, cont_splash=%d\n", __func__, edp_drv->cont_splash);
- mdss_edp_phy_pll_reset(edp_drv->base);
- mdss_edp_aux_reset(edp_drv->base);
- mdss_edp_mainlink_reset(edp_drv->base);
-
- ret = mdss_edp_prepare_clocks(edp_drv);
- if (ret)
- return ret;
- mdss_edp_phy_powerup(edp_drv->base, 1);
-
- mdss_edp_pll_configure(edp_drv->base, edp_drv->edid.timing[0].pclk);
- mdss_edp_phy_pll_ready(edp_drv->base);
-
- ret = mdss_edp_clk_enable(edp_drv);
- if (ret) {
- mdss_edp_unprepare_clocks(edp_drv);
- return ret;
- }
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- mdss_edp_aux_ctrl(edp_drv->base, 1);
+ if (!edp_drv->cont_splash) { /* vote for clocks */
+ mdss_edp_phy_pll_reset(edp_drv);
+ mdss_edp_aux_reset(edp_drv);
+ mdss_edp_mainlink_reset(edp_drv);
+ mdss_edp_aux_ctrl(edp_drv, 1);
- mdss_edp_lane_power_ctrl(edp_drv->base,
- edp_drv->dpcd.max_lane_count, 1);
- mdss_edp_enable_mainlink(edp_drv->base, 1);
- mdss_edp_config_clk(edp_drv->base, edp_drv->mmss_cc_base);
+ ret = mdss_edp_prepare_clocks(edp_drv);
+ if (ret)
+ return ret;
- mdss_edp_clock_synchrous(edp_drv->base, 1);
- mdss_edp_phy_vm_pe_init(edp_drv->base);
- mdss_edp_config_sync(edp_drv->base);
- mdss_edp_config_sw_div(edp_drv->base);
- mdss_edp_config_static_mdiv(edp_drv->base);
- gpio_set_value(edp_drv->gpio_panel_en, 1);
+ mdss_edp_phy_power_ctrl(edp_drv, 1);
+
+ ret = mdss_edp_clk_enable(edp_drv);
+ if (ret) {
+ mdss_edp_unprepare_clocks(edp_drv);
+ return ret;
+ }
+
+ mdss_edp_phy_pll_ready(edp_drv);
+
+ mdss_edp_lane_power_ctrl(edp_drv, 1);
+
+ mdss_edp_clock_synchrous(edp_drv, 1);
+ mdss_edp_phy_vm_pe_init(edp_drv);
+ mdss_edp_config_ctrl(edp_drv);
+ mdss_edp_sw_mvid_nvid(edp_drv);
+ mdss_edp_timing_cfg(edp_drv);
+
+ gpio_set_value(edp_drv->gpio_panel_en, 1);
+
+ INIT_COMPLETION(edp_drv->idle_comp);
+ mdss_edp_mainlink_ctrl(edp_drv, 1);
+ } else {
+ mdss_edp_aux_ctrl(edp_drv, 1);
+ }
+
mdss_edp_irq_enable(edp_drv);
+ mdss_edp_wait4train(edp_drv);
+
+ edp_drv->cont_splash = 0;
+
pr_debug("%s:-\n", __func__);
- return 0;
-}
-
-int mdss_edp_wait4train(struct mdss_panel_data *pdata)
-{
- struct mdss_edp_drv_pdata *edp_drv = NULL;
- int ret = 0;
-
- if (!pdata) {
- pr_err("%s: Invalid input data\n", __func__);
- return -EINVAL;
- }
-
- edp_drv = container_of(pdata, struct mdss_edp_drv_pdata,
- panel_data);
-
- ret = wait_for_completion_timeout(&edp_drv->train_comp, 100);
- if (ret <= 0) {
- pr_err("%s: Link Train timedout\n", __func__);
- ret = -EINVAL;
- } else {
- ret = 0;
- }
-
- mdss_edp_enable(edp_drv->base, 1);
-
- pr_debug("%s:\n", __func__);
-
return ret;
}
@@ -359,28 +574,44 @@
pr_err("%s: Invalid input data\n", __func__);
return -EINVAL;
}
- pr_debug("%s:+\n", __func__);
+ pr_debug("%s:+, cont_splash=%d\n", __func__, edp_drv->cont_splash);
+
+
+ INIT_COMPLETION(edp_drv->idle_comp);
+ mdss_edp_state_ctrl(edp_drv, ST_PUSH_IDLE);
+
+ ret = wait_for_completion_timeout(&edp_drv->idle_comp,
+ msecs_to_jiffies(100));
+ if (ret == 0)
+ pr_err("%s: idle pattern timedout\n", __func__);
+
+ mdss_edp_state_ctrl(edp_drv, 0);
+
+ mdss_edp_sink_power_state(edp_drv, SINK_POWER_OFF);
mdss_edp_irq_disable(edp_drv);
gpio_set_value(edp_drv->gpio_panel_en, 0);
+
if (edp_drv->bl_pwm != NULL)
pwm_disable(edp_drv->bl_pwm);
- mdss_edp_enable(edp_drv->base, 0);
- mdss_edp_unconfig_clk(edp_drv->base, edp_drv->mmss_cc_base);
- mdss_edp_enable_mainlink(edp_drv->base, 0);
- mdss_edp_lane_power_ctrl(edp_drv->base,
- edp_drv->dpcd.max_lane_count, 0);
+ mdss_edp_mainlink_reset(edp_drv);
+ mdss_edp_mainlink_ctrl(edp_drv, 0);
+
+ mdss_edp_lane_power_ctrl(edp_drv, 0);
+ mdss_edp_phy_power_ctrl(edp_drv, 0);
+
mdss_edp_clk_disable(edp_drv);
- mdss_edp_phy_powerup(edp_drv->base, 0);
mdss_edp_unprepare_clocks(edp_drv);
+
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
- mdss_edp_aux_ctrl(edp_drv->base, 0);
+ mdss_edp_aux_ctrl(edp_drv, 0);
- pr_debug("%s:-\n", __func__);
- return ret;
+ pr_debug("%s-: state_ctrl=%x\n", __func__,
+ edp_read(edp_drv->base + 0x8));
+ return 0;
}
static int mdss_edp_event_handler(struct mdss_panel_data *pdata,
@@ -393,9 +624,6 @@
case MDSS_EVENT_UNBLANK:
rc = mdss_edp_on(pdata);
break;
- case MDSS_EVENT_PANEL_ON:
- rc = mdss_edp_wait4train(pdata);
- break;
case MDSS_EVENT_PANEL_OFF:
rc = mdss_edp_off(pdata);
break;
@@ -477,6 +705,9 @@
edp_drv->panel_data.event_handler = mdss_edp_event_handler;
edp_drv->panel_data.set_backlight = mdss_edp_set_backlight;
+ edp_drv->panel_data.panel_info.cont_splash_enabled =
+ edp_drv->cont_splash;
+
ret = mdss_register_panel(edp_drv->pdev, &edp_drv->panel_data);
if (ret) {
dev_err(&(edp_drv->pdev->dev), "unable to register eDP\n");
@@ -539,10 +770,25 @@
return 0;
}
-static void mdss_edp_video_ready(struct mdss_edp_drv_pdata *edp_drv)
+static void mdss_edp_video_ready(struct mdss_edp_drv_pdata *ep)
{
pr_debug("%s: edp_video_ready\n", __func__);
+ complete(&ep->video_comp);
+}
+static void mdss_edp_idle_patterns_sent(struct mdss_edp_drv_pdata *ep)
+{
+ pr_debug("%s: idle_patterns_sent\n", __func__);
+ complete(&ep->idle_comp);
+}
+
+static void mdss_edp_do_link_train(struct mdss_edp_drv_pdata *ep)
+{
+ if (ep->cont_splash)
+ return;
+
+ INIT_COMPLETION(ep->train_comp);
+ mdss_edp_link_train(ep);
}
static int edp_event_thread(void *data)
@@ -579,13 +825,14 @@
if (todo & EV_DPCD_STATUS_READ)
mdss_edp_dpcd_status_read(ep);
- if (todo & EV_LINK_TRAIN) {
- INIT_COMPLETION(ep->train_comp);
- mdss_edp_link_train(ep);
- }
+ if (todo & EV_LINK_TRAIN)
+ mdss_edp_do_link_train(ep);
if (todo & EV_VIDEO_READY)
mdss_edp_video_ready(ep);
+
+ if (todo & EV_IDLE_PATTERNS_SENT)
+ mdss_edp_idle_patterns_sent(ep);
}
return 0;
@@ -607,11 +854,12 @@
u32 isr1, isr2, mask1, mask2;
u32 ack;
+ spin_lock(&ep->lock);
isr1 = edp_read(base + 0x308);
isr2 = edp_read(base + 0x30c);
- mask1 = isr1 & EDP_INTR_MASK1;
- mask2 = isr2 & EDP_INTR_MASK2;
+ mask1 = isr1 & ep->mask1;
+ mask2 = isr2 & ep->mask2;
isr1 &= ~mask1; /* remove masks bit */
isr2 &= ~mask2;
@@ -628,16 +876,19 @@
ack <<= 1; /* ack bits */
ack |= mask2;
edp_write(base + 0x30c, ack);
+ spin_unlock(&ep->lock);
if (isr1 & EDP_INTR_HPD) {
isr1 &= ~EDP_INTR_HPD; /* clear */
- if (ep->train_start)
- edp_send_events(ep, EV_LINK_TRAIN);
+ edp_send_events(ep, EV_LINK_TRAIN);
}
if (isr2 & EDP_INTR_READY_FOR_VIDEO)
edp_send_events(ep, EV_VIDEO_READY);
+ if (isr2 & EDP_INTR_IDLE_PATTERNs_SENT)
+ edp_send_events(ep, EV_IDLE_PATTERNS_SENT);
+
if (isr1 && ep->aux_cmd_busy) {
/* clear EDP_AUX_TRANS_CTRL */
edp_write(base + 0x318, 0);
@@ -661,16 +912,24 @@
static void mdss_edp_irq_enable(struct mdss_edp_drv_pdata *edp_drv)
{
- edp_write(edp_drv->base + 0x308, EDP_INTR_MASK1);
- edp_write(edp_drv->base + 0x30c, EDP_INTR_MASK2);
+ unsigned long flags;
+
+ spin_lock_irqsave(&edp_drv->lock, flags);
+ edp_write(edp_drv->base + 0x308, edp_drv->mask1);
+ edp_write(edp_drv->base + 0x30c, edp_drv->mask2);
+ spin_unlock_irqrestore(&edp_drv->lock, flags);
mdss_enable_irq(&mdss_edp_hw);
}
static void mdss_edp_irq_disable(struct mdss_edp_drv_pdata *edp_drv)
{
+ unsigned long flags;
+
+ spin_lock_irqsave(&edp_drv->lock, flags);
edp_write(edp_drv->base + 0x308, 0x0);
edp_write(edp_drv->base + 0x30c, 0x0);
+ spin_unlock_irqrestore(&edp_drv->lock, flags);
mdss_disable_irq(&mdss_edp_hw);
}
@@ -679,7 +938,6 @@
{
int ret = 0;
-
edp_drv->gpio_panel_hpd = of_get_named_gpio_flags(
edp_drv->pdev->dev.of_node, "gpio-panel-hpd", 0,
&edp_drv->hpd_flags);
@@ -769,7 +1027,11 @@
edp_drv->pdev = pdev;
edp_drv->pdev->id = 1;
edp_drv->clk_on = 0;
- edp_drv->train_start = 0; /* no link train yet */
+ edp_drv->aux_rate = 19200000;
+ edp_drv->mask1 = EDP_INTR_MASK1;
+ edp_drv->mask2 = EDP_INTR_MASK2;
+ mutex_init(&edp_drv->emutex);
+ spin_lock_init(&edp_drv->lock);
ret = mdss_edp_get_base_address(edp_drv);
if (ret)
@@ -801,34 +1063,55 @@
mdss_edp_event_setup(edp_drv);
+ edp_drv->cont_splash = of_property_read_bool(pdev->dev.of_node,
+ "qcom,cont-splash-enabled");
+
+ pr_debug("%s:cont_splash=%d\n", __func__, edp_drv->cont_splash);
+
/* need mdss clock to receive irq */
- mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+ if (!edp_drv->cont_splash)
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
/* only need aux and ahb clock for aux channel */
mdss_edp_prepare_aux_clocks(edp_drv);
mdss_edp_aux_clk_enable(edp_drv);
- mdss_edp_phy_pll_reset(edp_drv->base);
- mdss_edp_aux_reset(edp_drv->base);
- mdss_edp_mainlink_reset(edp_drv->base);
- mdss_edp_phy_powerup(edp_drv->base, 1);
- mdss_edp_aux_ctrl(edp_drv->base, 1);
+
+ if (!edp_drv->cont_splash) {
+ mdss_edp_phy_pll_reset(edp_drv);
+ mdss_edp_aux_reset(edp_drv);
+ mdss_edp_mainlink_reset(edp_drv);
+ mdss_edp_phy_power_ctrl(edp_drv, 1);
+ mdss_edp_aux_ctrl(edp_drv, 1);
+ }
mdss_edp_irq_enable(edp_drv);
mdss_edp_edid_read(edp_drv, 0);
mdss_edp_dpcd_cap_read(edp_drv);
+ mdss_edp_fill_link_cfg(edp_drv);
mdss_edp_irq_disable(edp_drv);
- mdss_edp_aux_ctrl(edp_drv->base, 0);
+ if (!edp_drv->cont_splash) {
+ mdss_edp_aux_ctrl(edp_drv, 0);
+ mdss_edp_phy_power_ctrl(edp_drv, 0);
+ }
+
mdss_edp_aux_clk_disable(edp_drv);
- mdss_edp_phy_powerup(edp_drv->base, 0);
mdss_edp_unprepare_aux_clocks(edp_drv);
- mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
+ if (!edp_drv->cont_splash)
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
+
+ if (edp_drv->cont_splash) { /* vote for clocks */
+ mdss_edp_prepare_clocks(edp_drv);
+ mdss_edp_clk_enable(edp_drv);
+ }
mdss_edp_device_register(edp_drv);
+ pr_info("%s: done\n", __func__);
+
return 0;
diff --git a/drivers/video/msm/mdss/mdss_edp.h b/drivers/video/msm/mdss/mdss_edp.h
index 33b899f..0c0200d 100644
--- a/drivers/video/msm/mdss/mdss_edp.h
+++ b/drivers/video/msm/mdss/mdss_edp.h
@@ -57,6 +57,8 @@
#define EDP_INTR_ACK_SHIFT 1
#define EDP_INTR_MASK_SHIFT 2
+#define EDP_MAX_LANE 4
+
/* isr */
#define EDP_INTR_HPD BIT(0)
#define EDP_INTR_AUX_I2C_DONE BIT(3)
@@ -137,8 +139,27 @@
#define EV_DPCD_CAP_READ BIT(2)
#define EV_DPCD_STATUS_READ BIT(3)
#define EV_LINK_TRAIN BIT(4)
+#define EV_IDLE_PATTERNS_SENT BIT(30)
#define EV_VIDEO_READY BIT(31)
+/* edp state ctrl */
+#define ST_TRAIN_PATTERN_1 BIT(0)
+#define ST_TRAIN_PATTERN_2 BIT(1)
+#define ST_TRAIN_PATTERN_3 BIT(2)
+#define ST_SYMBOL_ERR_RATE_MEASUREMENT BIT(3)
+#define ST_PRBS7 BIT(4)
+#define ST_CUSTOM_80_BIT_PATTERN BIT(5)
+#define ST_SEND_VIDEO BIT(6)
+#define ST_PUSH_IDLE BIT(7)
+
+/* sink power state */
+#define SINK_POWER_ON 1
+#define SINK_POWER_OFF 2
+
+#define EDP_LINK_RATE_162 6 /* 1.62G = 270M * 6 */
+#define EDP_LINK_RATE_270 10 /* 2.70G = 270M * 10 */
+#define EDP_LINK_RATE_MAX EDP_LINK_RATE_270
+
struct dpcd_cap {
char major;
char minor;
@@ -238,16 +259,31 @@
int (*off) (struct mdss_panel_data *pdata);
struct platform_device *pdev;
+ struct mutex emutex;
+ int clk_cnt;
+ int cont_splash;
+
/* edp specific */
unsigned char *base;
int base_size;
unsigned char *mmss_cc_base;
+ u32 mask1;
+ u32 mask2;
struct mdss_panel_data panel_data;
+ int edp_on_cnt;
+ int edp_off_cnt;
+
+ u32 pixel_rate;
+ u32 aux_rate;
+ char link_rate; /* X 27000000 for real rate */
+ char lane_cnt;
+ char train_link_rate; /* X 27000000 for real rate */
+ char train_lane_cnt;
+
struct edp_edid edid;
struct dpcd_cap dpcd;
- int train_start;
/* regulators */
struct regulator *vdda_vreg;
@@ -275,6 +311,8 @@
/* aux */
struct completion aux_comp;
struct completion train_comp;
+ struct completion idle_comp;
+ struct completion video_comp;
struct mutex aux_mutex;
u32 aux_cmd_busy;
u32 aux_cmd_i2c;
@@ -286,8 +324,6 @@
char txbuf[256];
char rxbuf[256];
struct dpcd_link_status link_status;
- char link_rate;
- char lane_cnt;
char v_level;
char p_level;
/* transfer unit */
@@ -303,12 +339,9 @@
u32 event_gndx;
u32 event_todo_list[HPD_EVENT_MAX];
spinlock_t event_lock;
+ spinlock_t lock;
};
-void mdss_edp_phy_sw_reset(unsigned char *base);
-void mdss_edp_pll_configure(unsigned char *base, int rate);
-void mdss_edp_enable_mainlink(unsigned char *base, int enable);
-void mdss_edp_phy_powerup(unsigned char *base, int enable);
int mdss_edp_aux_clk_enable(struct mdss_edp_drv_pdata *edp_drv);
void mdss_edp_aux_clk_disable(struct mdss_edp_drv_pdata *edp_drv);
int mdss_edp_clk_enable(struct mdss_edp_drv_pdata *edp_drv);
@@ -319,29 +352,22 @@
void mdss_edp_unprepare_aux_clocks(struct mdss_edp_drv_pdata *edp_drv);
int mdss_edp_prepare_clocks(struct mdss_edp_drv_pdata *edp_drv);
void mdss_edp_unprepare_clocks(struct mdss_edp_drv_pdata *edp_drv);
-void mdss_edp_config_clk(unsigned char *base, unsigned char *mmss_cc_base);
-void mdss_edp_unconfig_clk(unsigned char *base,
- unsigned char *mmss_cc_base);
void mdss_edp_dpcd_cap_read(struct mdss_edp_drv_pdata *edp);
-void mdss_edp_dpcd_status_read(struct mdss_edp_drv_pdata *edp);
+int mdss_edp_dpcd_status_read(struct mdss_edp_drv_pdata *edp);
void mdss_edp_edid_read(struct mdss_edp_drv_pdata *edp, int block);
int mdss_edp_link_train(struct mdss_edp_drv_pdata *edp);
void edp_aux_i2c_handler(struct mdss_edp_drv_pdata *edp, u32 isr);
void edp_aux_native_handler(struct mdss_edp_drv_pdata *edp, u32 isr);
void mdss_edp_aux_init(struct mdss_edp_drv_pdata *ep);
-void mdss_edp_enable_aux(unsigned char *edp_base, int enable);
-void mdss_edp_timing_engine_ctrl(unsigned char *edp_base, int enable);
-void mdss_edp_mainlink_ctrl(unsigned char *edp_base, int enable);
-void mdss_edp_mainlink_reset(unsigned char *edp_base);
-void mdss_edp_aux_reset(unsigned char *edp_base);
-void mdss_edp_aux_ctrl(unsigned char *edp_base, int enable);
-void mdss_edp_phy_pll_reset(unsigned char *edp_base);
-int mdss_edp_phy_pll_ready(unsigned char *edp_base);
-int mdss_edp_phy_ready(unsigned char *edp_base);
-void mdss_edp_lane_power_ctrl(unsigned char *edp_base, int max_lane, int up);
-void mdss_edp_phy_vm_pe_init(unsigned char *edp_base);
-void mdss_edp_clock_synchrous(unsigned char *edp_base, int sync);
+void mdss_edp_fill_link_cfg(struct mdss_edp_drv_pdata *ep);
+void mdss_edp_sink_power_down(struct mdss_edp_drv_pdata *ep);
+void mdss_edp_state_ctrl(struct mdss_edp_drv_pdata *ep, u32 state);
+int mdss_edp_sink_power_state(struct mdss_edp_drv_pdata *ep, char state);
+void mdss_edp_lane_power_ctrl(struct mdss_edp_drv_pdata *ep, int up);
+void mdss_edp_config_ctrl(struct mdss_edp_drv_pdata *ep);
+
+void mdss_edp_clk_debug(unsigned char *edp_base, unsigned char *mmss_cc_base);
#endif /* MDSS_EDP_H */
diff --git a/drivers/video/msm/mdss/mdss_edp_aux.c b/drivers/video/msm/mdss/mdss_edp_aux.c
index 6d8e2c2..bbcee19 100644
--- a/drivers/video/msm/mdss/mdss_edp_aux.c
+++ b/drivers/video/msm/mdss/mdss_edp_aux.c
@@ -368,7 +368,6 @@
char *bp;
int i;
char csum = 0;
- int ret = 0;
bp = buf;
if (len < 128) {
@@ -389,7 +388,7 @@
return -EINVAL;
}
- return ret;
+ return 0;
}
@@ -411,7 +410,7 @@
edid->id_name[2] = 'A' + data - 1;
edid->id_name[3] = 0;
- pr_debug("%s: edid manufacturer = %s", __func__, edid->id_name);
+ pr_debug("%s: edid manufacturer = %s\n", __func__, edid->id_name);
}
void edp_extract_edid_product(struct edp_edid *edid, char *buf)
@@ -427,21 +426,21 @@
data <<= 8;
edid->id_product |= data;
- pr_debug("%s: edid product = 0x%x", __func__, edid->id_product);
+ pr_debug("%s: edid product = 0x%x\n", __func__, edid->id_product);
};
void edp_extract_edid_version(struct edp_edid *edid, char *buf)
{
edid->version = buf[0x12];
edid->revision = buf[0x13];
- pr_debug("%s: edid version = %d.%d", __func__, edid->version,
+ pr_debug("%s: edid version = %d.%d\n", __func__, edid->version,
edid->revision);
};
void edp_extract_edid_ext_block_cnt(struct edp_edid *edid, char *buf)
{
edid->ext_block_cnt = buf[0x7e];
- pr_debug("%s: edid extension = %d", __func__,
+ pr_debug("%s: edid extension = %d\n", __func__,
edid->ext_block_cnt);
};
@@ -461,7 +460,7 @@
pr_debug("%s: Digital Video intf=%d color_depth=%d\n",
__func__, edid->video_intf, edid->color_depth);
} else {
- pr_err("%s: Error, Analog video interface", __func__);
+ pr_err("%s: Error, Analog video interface\n", __func__);
}
};
@@ -485,7 +484,7 @@
}
}
- pr_debug("%s: edid dpm=%d color_format=%d", __func__,
+ pr_debug("%s: edid dpm=%d color_format=%d\n", __func__,
edid->dpm, edid->color_format);
};
@@ -567,6 +566,7 @@
dp->h_border = *bp++; /* byte 0x45 */
dp->v_border = *bp++; /* byte 0x46 */
+ /* progressive or interlaved */
dp->interlaced = *bp & 0x80; /* byte 0x47 */
dp->stereo = *bp & 0x60;
@@ -642,12 +642,13 @@
pr_debug("%s: ret=%d\n", __func__, ret);
if (ret >= 0)
break;
- pr_debug("%s: failed in write\n", __func__);
msleep(100);
}
- if (cnt == 0)
+ if (cnt <= 0) {
+ pr_err("%s: aux chan NOT ready\n", __func__);
return 0;
+ }
return 1;
}
@@ -718,14 +719,15 @@
data = *bp++; /* byte 1 */
/* 162, 270 and 540 MB, symbol rate, NOT bit rate */
- cap->max_link_rate = data * 27;
+ cap->max_link_rate = data;
if (--rlen <= 0)
return;
pr_debug("%s: link_rate=%d\n", __func__, cap->max_link_rate);
data = *bp++; /* byte 2 */
if (data & BIT(7))
- cap->flags |= DPCD_ENHANCED_FRAME;
+ cap->enhanced_frame++;
+
if (data & 0x40)
cap->flags |= DPCD_TPS3;
data &= 0x0f;
@@ -789,7 +791,9 @@
pr_debug("%s: scrambler_reset=%d\n", __func__,
cap->scrambler_reset);
- cap->enhanced_frame = data & BIT(1);
+ if (data & BIT(1))
+ cap->enhanced_frame++;
+
pr_debug("%s: enhanced_framing=%d\n", __func__,
cap->enhanced_frame);
if (--rlen <= 0)
@@ -804,7 +808,7 @@
cap->training_read_interval);
}
-static void edp_link_status_read(struct mdss_edp_drv_pdata *ep, int len)
+static int edp_link_status_read(struct mdss_edp_drv_pdata *ep, int len)
{
char *bp;
char data;
@@ -815,9 +819,9 @@
pr_debug("%s: len=%d", __func__, len);
/* skip byte 0x200 and 0x201 */
rlen = edp_aux_read_buf(ep, 0x202, len, 0);
- if (rlen <= 0) {
+ if (rlen < len) {
pr_err("%s: edp aux read failed\n", __func__);
- return;
+ return 0;
}
rp = &ep->rxp;
bp = rp->data;
@@ -825,26 +829,18 @@
data = *bp++; /* byte 0x202 */
sp->lane_01_status = data; /* lane 0, 1 */
- if (--rlen <= 0)
- return;
data = *bp++; /* byte 0x203 */
sp->lane_23_status = data; /* lane 2, 3 */
- if (--rlen <= 0)
- return;
data = *bp++; /* byte 0x204 */
sp->interlane_align_done = (data & BIT(0));
sp->downstream_port_status_changed = (data & BIT(6));
sp->link_status_updated = (data & BIT(7));
- if (--rlen <= 0)
- return;
data = *bp++; /* byte 0x205 */
sp->port_0_in_sync = (data & BIT(0));
sp->port_1_in_sync = (data & BIT(1));
- if (--rlen <= 0)
- return;
data = *bp++; /* byte 0x206 */
sp->req_voltage_swing[0] = data & 0x03;
@@ -854,8 +850,6 @@
sp->req_voltage_swing[1] = data & 0x03;
data >>= 2;
sp->req_pre_emphasis[1] = data & 0x03;
- if (--rlen <= 0)
- return;
data = *bp++; /* byte 0x207 */
sp->req_voltage_swing[2] = data & 0x03;
@@ -865,16 +859,23 @@
sp->req_voltage_swing[3] = data & 0x03;
data >>= 2;
sp->req_pre_emphasis[3] = data & 0x03;
+
+ return len;
}
static int edp_cap_lane_rate_set(struct mdss_edp_drv_pdata *ep)
{
char buf[4];
int len = 0;
+ struct dpcd_cap *cap;
+
+ cap = &ep->dpcd;
pr_debug("%s: bw=%x lane=%d\n", __func__, ep->link_rate, ep->lane_cnt);
buf[0] = ep->link_rate;
buf[1] = ep->lane_cnt;
+ if (cap->enhanced_frame)
+ buf[1] |= 0x80;
len = edp_aux_write_buf(ep, 0x100, buf, 2, 0);
return len;
@@ -901,13 +902,6 @@
return edp_aux_write_buf(ep, 0x103, buf, 4, 0);
}
-static int edp_powerstate_write(struct mdss_edp_drv_pdata *ep,
- char powerstate)
-{
- pr_debug("%s: state=%d\n", __func__, powerstate);
- return edp_aux_write_buf(ep, 0x600, &powerstate, 1, 0);
-}
-
static int edp_train_pattern_set_write(struct mdss_edp_drv_pdata *ep,
int pattern)
{
@@ -923,8 +917,6 @@
u32 mask;
u32 data;
- pr_debug("%s:\n", __func__);
-
if (ep->lane_cnt == 1) {
mask = 0x01; /* lane 0 */
data = ep->link_status.lane_01_status;
@@ -953,8 +945,10 @@
pr_debug("%s:\n", __func__);
- if (!ep->link_status.interlane_align_done) /* not align */
+ if (!ep->link_status.interlane_align_done) { /* not align */
+ pr_err("%s: interlane align failed\n", __func__);
return 0;
+ }
if (ep->lane_cnt == 1) {
mask = 0x7;
@@ -1154,8 +1148,47 @@
return ret;
}
-static int edp_link_rate_shift(struct mdss_edp_drv_pdata *ep)
+static int edp_link_rate_down_shift(struct mdss_edp_drv_pdata *ep)
{
+ u32 prate, lrate;
+ int rate, lane, max_lane;
+ int changed = 0;
+
+ rate = ep->link_rate;
+ lane = ep->lane_cnt;
+ max_lane = ep->dpcd.max_lane_count;
+
+ prate = ep->pixel_rate;
+ prate /= 1000; /* avoid using 64 biits */
+ prate *= ep->bpp;
+ prate /= 8; /* byte */
+
+ if (rate > EDP_LINK_RATE_162 && rate <= EDP_LINK_RATE_MAX) {
+ rate -= 4; /* reduce rate */
+ changed++;
+ }
+
+ if (changed) {
+ if (lane >= 1 && lane < max_lane)
+ lane <<= 1; /* increase lane */
+
+ lrate = 270000000; /* 270M */
+ lrate /= 1000; /* avoid using 64 bits */
+ lrate *= rate;
+ lrate /= 10; /* byte, 10 bits --> 8 bits */
+ lrate *= lane;
+
+ pr_debug("%s: new lrate=%u prate=%u rate=%d lane=%d p=%d b=%d\n",
+ __func__, lrate, prate, rate, lane, ep->pixel_rate, ep->bpp);
+
+ if (lrate > prate) {
+ ep->link_rate = rate;
+ ep->lane_cnt = lane;
+ pr_debug("%s: new rate=%d %d\n", __func__, rate, lane);
+ return 0;
+ }
+ }
+
/* add calculation later */
return -EINVAL;
}
@@ -1180,23 +1213,23 @@
return ret;
}
- /* start with max rate and lane */
- ep->lane_cnt = ep->dpcd.max_lane_count;
- ep->link_rate = ep->dpcd.max_link_rate;
edp_write(ep->base + EDP_MAINLINK_CTRL, 0x1);
+ mdss_edp_sink_power_state(ep, SINK_POWER_ON);
+
train_start:
ep->v_level = 0; /* start from default level */
ep->p_level = 0;
edp_cap_lane_rate_set(ep);
+ mdss_edp_config_ctrl(ep);
+ mdss_edp_lane_power_ctrl(ep, 1);
edp_clear_training_pattern(ep);
usleep(ep->dpcd.training_read_interval);
- edp_powerstate_write(ep, 1);
ret = edp_start_link_train_1(ep);
if (ret < 0) {
- if (edp_link_rate_shift(ep) == 0) {
+ if (edp_link_rate_down_shift(ep) == 0) {
goto train_start;
} else {
pr_err("%s: Training 1 failed", __func__);
@@ -1210,7 +1243,7 @@
edp_clear_training_pattern(ep);
ret = edp_start_link_train_2(ep);
if (ret < 0) {
- if (edp_link_rate_shift(ep) == 0) {
+ if (edp_link_rate_down_shift(ep) == 0) {
goto train_start;
} else {
pr_err("%s: Training 2 failed", __func__);
@@ -1221,6 +1254,7 @@
pr_debug("%s: Training 2 completed successfully", __func__);
+ mdss_edp_state_ctrl(ep, ST_SEND_VIDEO);
clear:
edp_clear_training_pattern(ep);
@@ -1233,9 +1267,33 @@
edp_sink_capability_read(ep, 16);
}
-void mdss_edp_dpcd_status_read(struct mdss_edp_drv_pdata *ep)
+int mdss_edp_dpcd_status_read(struct mdss_edp_drv_pdata *ep)
{
- edp_link_status_read(ep, 6);
+ struct dpcd_link_status *sp;
+ int ret = 0; /* not sync */
+
+ ret = edp_link_status_read(ep, 6);
+
+ if (ret) {
+ sp = &ep->link_status;
+ ret = sp->port_0_in_sync; /* 1 == sync */
+ }
+
+ return ret;
+}
+
+void mdss_edp_fill_link_cfg(struct mdss_edp_drv_pdata *ep)
+{
+ struct display_timing_desc *dp;
+
+ dp = &ep->edid.timing[0];
+ ep->pixel_rate = dp->pclk;
+ ep->lane_cnt = ep->dpcd.max_lane_count;
+ ep->link_rate = ep->dpcd.max_link_rate;
+
+ pr_debug("%s: pclk=%d rate=%d lane=%d\n", __func__,
+ ep->pixel_rate, ep->link_rate, ep->lane_cnt);
+
}
void mdss_edp_edid_read(struct mdss_edp_drv_pdata *ep, int block)
@@ -1243,6 +1301,15 @@
edp_sink_edid_read(ep, block);
}
+int mdss_edp_sink_power_state(struct mdss_edp_drv_pdata *ep, char state)
+{
+ int ret;
+
+ ret = edp_aux_write_buf(ep, 0x600, &state, 1, 0);
+ pr_debug("%s: state=%d ret=%d\n", __func__, state, ret);
+ return ret;
+}
+
int mdss_edp_link_train(struct mdss_edp_drv_pdata *ep)
{
return edp_aux_link_train(ep);
@@ -1253,7 +1320,10 @@
mutex_init(&ep->aux_mutex);
init_completion(&ep->aux_comp);
init_completion(&ep->train_comp);
+ init_completion(&ep->idle_comp);
+ init_completion(&ep->video_comp);
complete(&ep->train_comp); /* make non block at first time */
+ complete(&ep->video_comp); /* make non block at first time */
edp_buf_init(&ep->txp, ep->txbuf, sizeof(ep->txbuf));
edp_buf_init(&ep->rxp, ep->rxbuf, sizeof(ep->rxbuf));
diff --git a/drivers/video/msm/mdss/mdss_fb.c b/drivers/video/msm/mdss/mdss_fb.c
index 81473db..c15c02b 100644
--- a/drivers/video/msm/mdss/mdss_fb.c
+++ b/drivers/video/msm/mdss/mdss_fb.c
@@ -92,7 +92,7 @@
unsigned long val, void *data);
static int __mdss_fb_display_thread(void *data);
-static void mdss_fb_pan_idle(struct msm_fb_data_type *mfd);
+static int mdss_fb_pan_idle(struct msm_fb_data_type *mfd);
static int mdss_fb_send_panel_event(struct msm_fb_data_type *mfd,
int event, void *arg);
void mdss_fb_no_update_notify_timer_cb(unsigned long data)
@@ -297,6 +297,7 @@
{
struct msm_fb_data_type *mfd = platform_get_drvdata(pdev);
+ mfd->shutdown_pending = true;
lock_fb_info(mfd->fbi);
mdss_fb_release_all(mfd->fbi, true);
unlock_fb_info(mfd->fbi);
@@ -779,13 +780,18 @@
u32 len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.smem_len);
unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
+ int ret = 0;
if (!start) {
pr_warn("No framebuffer memory is allocated.\n");
return -ENOMEM;
}
- mdss_fb_pan_idle(mfd);
+ ret = mdss_fb_pan_idle(mfd);
+ if (ret) {
+ pr_err("Shutdown pending. Aborting operation\n");
+ return ret;
+ }
/* Set VM flags. */
start &= PAGE_MASK;
@@ -1120,8 +1126,6 @@
mfd->index, fbi->var.xres, fbi->var.yres,
fbi->fix.smem_len);
- kthread_run(__mdss_fb_display_thread, mfd, "mdss_fb%d", mfd->index);
-
return 0;
}
@@ -1132,6 +1136,11 @@
int result;
int pid = current->tgid;
+ if (mfd->shutdown_pending) {
+ pr_err("Shutdown pending. Aborting operation\n");
+ return -EPERM;
+ }
+
list_for_each_entry(pinfo, &mfd->proc_list, list) {
if (pinfo->pid == pid)
break;
@@ -1151,23 +1160,49 @@
result = pm_runtime_get_sync(info->dev);
- if (result < 0)
+ if (result < 0) {
pr_err("pm_runtime: fail to wake up\n");
+ goto pm_error;
+ }
if (!mfd->ref_cnt) {
+ mfd->disp_thread = kthread_run(__mdss_fb_display_thread, mfd,
+ "mdss_fb%d", mfd->index);
+ if (IS_ERR(mfd->disp_thread)) {
+ pr_err("unable to start display thread %d\n",
+ mfd->index);
+ result = PTR_ERR(mfd->disp_thread);
+ mfd->disp_thread = NULL;
+ goto thread_error;
+ }
+
result = mdss_fb_blank_sub(FB_BLANK_UNBLANK, info,
mfd->op_enable);
if (result) {
- pm_runtime_put(info->dev);
pr_err("can't turn on fb%d! rc=%d\n", mfd->index,
result);
- return result;
+ goto blank_error;
}
}
pinfo->ref_cnt++;
mfd->ref_cnt++;
+
return 0;
+
+blank_error:
+ kthread_stop(mfd->disp_thread);
+ mfd->disp_thread = NULL;
+
+thread_error:
+ if (pinfo && !pinfo->ref_cnt) {
+ list_del(&pinfo->list);
+ kfree(pinfo);
+ }
+ pm_runtime_put(info->dev);
+
+pm_error:
+ return result;
}
static int mdss_fb_release_all(struct fb_info *info, bool release_all)
@@ -1176,9 +1211,12 @@
struct mdss_fb_proc_info *pinfo = NULL, *temp_pinfo = NULL;
int ret = 0;
int pid = current->tgid;
+ bool unknown_pid = true, release_needed = false;
+ struct task_struct *task = current->group_leader;
if (!mfd->ref_cnt) {
- pr_info("try to close unopened fb %d!\n", mfd->index);
+ pr_info("try to close unopened fb %d! from %s\n", mfd->index,
+ task->comm);
return -EINVAL;
}
@@ -1190,12 +1228,15 @@
if (!release_all && (pinfo->pid != pid))
continue;
- pr_debug("found process entry pid=%d ref=%d\n", pinfo->pid,
- pinfo->ref_cnt);
+ unknown_pid = false;
+
+ pr_debug("found process %s pid=%d mfd->ref=%d pinfo->ref=%d\n",
+ task->comm, mfd->ref_cnt, pinfo->pid, pinfo->ref_cnt);
do {
if (mfd->ref_cnt < pinfo->ref_cnt)
- pr_warn("WARN:mfd->ref_cnt < pinfo->ref_cnt\n");
+ pr_warn("WARN:mfd->ref=%d < pinfo->ref=%d\n",
+ mfd->ref_cnt, pinfo->ref_cnt);
else
mfd->ref_cnt--;
@@ -1203,24 +1244,57 @@
pm_runtime_put(info->dev);
} while (release_all && pinfo->ref_cnt);
+ if (release_all && mfd->disp_thread) {
+ kthread_stop(mfd->disp_thread);
+ mfd->disp_thread = NULL;
+ }
+
if (pinfo->ref_cnt == 0) {
- if (mfd->mdp.release_fnc) {
- ret = mfd->mdp.release_fnc(mfd);
- if (ret)
- pr_err("error releasing fb%d pid=%d\n",
- mfd->index, pinfo->pid);
- }
list_del(&pinfo->list);
kfree(pinfo);
+ release_needed = !release_all;
+ }
+
+ if (!release_all)
+ break;
+ }
+
+ if (release_needed) {
+ pr_debug("known process %s pid=%d mfd->ref=%d\n",
+ task->comm, pid, mfd->ref_cnt);
+
+ if (mfd->mdp.release_fnc) {
+ ret = mfd->mdp.release_fnc(mfd, false);
+ if (ret)
+ pr_err("error releasing fb%d pid=%d\n",
+ mfd->index, pid);
+ }
+ } else if (unknown_pid || release_all) {
+ pr_warn("unknown process %s pid=%d mfd->ref=%d\n",
+ task->comm, pid, mfd->ref_cnt);
+
+ if (mfd->ref_cnt)
+ mfd->ref_cnt--;
+
+ if (mfd->mdp.release_fnc) {
+ ret = mfd->mdp.release_fnc(mfd, true);
+ if (ret)
+ pr_err("error fb%d release process %s pid=%d\n",
+ mfd->index, task->comm, pid);
}
}
if (!mfd->ref_cnt) {
+ if (mfd->disp_thread) {
+ kthread_stop(mfd->disp_thread);
+ mfd->disp_thread = NULL;
+ }
+
ret = mdss_fb_blank_sub(FB_BLANK_POWERDOWN, info,
mfd->op_enable);
if (ret) {
- pr_err("can't turn off fb%d! rc=%d\n",
- mfd->index, ret);
+ pr_err("can't turn off fb%d! rc=%d process %s pid=%d\n",
+ mfd->index, ret, task->comm, pid);
return ret;
}
}
@@ -1392,21 +1466,28 @@
* hardware configuration. After this function returns it is safe to perform
* software updates for next frame.
*/
-static void mdss_fb_pan_idle(struct msm_fb_data_type *mfd)
+static int mdss_fb_pan_idle(struct msm_fb_data_type *mfd)
{
- int ret;
+ int ret = 0;
ret = wait_event_timeout(mfd->idle_wait_q,
- !atomic_read(&mfd->commits_pending),
+ (!atomic_read(&mfd->commits_pending) ||
+ mfd->shutdown_pending),
msecs_to_jiffies(WAIT_DISP_OP_TIMEOUT));
if (!ret) {
pr_err("wait for idle timeout %d pending=%d\n",
ret, atomic_read(&mfd->commits_pending));
mdss_fb_signal_timeline(&mfd->mdp_sync_pt_data);
+ } else if (mfd->shutdown_pending) {
+ pr_debug("Shutdown signalled\n");
+ return -EPERM;
}
+
+ return 0;
}
+
static int mdss_fb_pan_display_ex(struct fb_info *info,
struct mdp_display_commit *disp_commit)
{
@@ -1424,7 +1505,11 @@
if (var->yoffset > (info->var.yres_virtual - info->var.yres))
return -EINVAL;
- mdss_fb_pan_idle(mfd);
+ ret = mdss_fb_pan_idle(mfd);
+ if (ret) {
+ pr_err("Shutdown pending. Aborting operation\n");
+ return ret;
+ }
mutex_lock(&mfd->mdp_sync_pt_data.sync_mutex);
if (info->fix.xpanstep)
@@ -1556,14 +1641,20 @@
while (1) {
wait_event(mfd->commit_wait_q,
- atomic_read(&mfd->commits_pending));
+ (atomic_read(&mfd->commits_pending) ||
+ kthread_should_stop()));
+
+ if (kthread_should_stop())
+ break;
ret = __mdss_fb_perform_commit(mfd);
-
atomic_dec(&mfd->commits_pending);
wake_up_all(&mfd->idle_wait_q);
}
+ atomic_set(&mfd->commits_pending, 0);
+ wake_up_all(&mfd->idle_wait_q);
+
return ret;
}
@@ -1686,8 +1777,14 @@
struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
struct fb_var_screeninfo *var = &info->var;
int old_imgType;
+ int ret = 0;
- mdss_fb_pan_idle(mfd);
+ ret = mdss_fb_pan_idle(mfd);
+ if (ret) {
+ pr_err("Shutdown pending. Aborting operation\n");
+ return ret;
+ }
+
old_imgType = mfd->fb_imgType;
switch (var->bits_per_pixel) {
case 16:
@@ -1734,7 +1831,7 @@
mfd->panel_reconfig = false;
}
- return 0;
+ return ret;
}
int mdss_fb_dcm(struct msm_fb_data_type *mfd, int req_state)
@@ -1975,8 +2072,15 @@
mfd = (struct msm_fb_data_type *)info->par;
mdss_fb_power_setting_idle(mfd);
if ((cmd != MSMFB_VSYNC_CTRL) && (cmd != MSMFB_OVERLAY_VSYNC_CTRL) &&
- (cmd != MSMFB_ASYNC_BLIT) && (cmd != MSMFB_BLIT))
- mdss_fb_pan_idle(mfd);
+ (cmd != MSMFB_ASYNC_BLIT) && (cmd != MSMFB_BLIT) &&
+ (cmd != MSMFB_NOTIFY_UPDATE)) {
+ ret = mdss_fb_pan_idle(mfd);
+ if (ret) {
+ pr_debug("Shutdown pending. Aborting operation %x\n",
+ cmd);
+ return ret;
+ }
+ }
switch (cmd) {
case MSMFB_CURSOR:
diff --git a/drivers/video/msm/mdss/mdss_fb.h b/drivers/video/msm/mdss/mdss_fb.h
index 8213dbe..e245dd3 100644
--- a/drivers/video/msm/mdss/mdss_fb.h
+++ b/drivers/video/msm/mdss/mdss_fb.h
@@ -106,7 +106,7 @@
int (*on_fnc)(struct msm_fb_data_type *mfd);
int (*off_fnc)(struct msm_fb_data_type *mfd);
/* called to release resources associated to the process */
- int (*release_fnc)(struct msm_fb_data_type *mfd);
+ int (*release_fnc)(struct msm_fb_data_type *mfd, bool release_all);
int (*kickoff_fnc)(struct msm_fb_data_type *mfd,
struct mdp_display_commit *data);
int (*ioctl_handler)(struct msm_fb_data_type *mfd, u32 cmd, void *arg);
@@ -195,9 +195,11 @@
struct msm_sync_pt_data mdp_sync_pt_data;
/* for non-blocking */
+ struct task_struct *disp_thread;
atomic_t commits_pending;
wait_queue_head_t commit_wait_q;
wait_queue_head_t idle_wait_q;
+ bool shutdown_pending;
struct msm_fb_backup_type msm_fb_backup;
struct completion power_set_comp;
diff --git a/drivers/video/msm/mdss/mdss_hdmi_hdcp.c b/drivers/video/msm/mdss/mdss_hdmi_hdcp.c
index ca21b51..8ff9059 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_hdcp.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_hdcp.c
@@ -31,6 +31,8 @@
#define HDCP_KEYS_STATE_PROD_AKSV 6
#define HDCP_KEYS_STATE_RESERVED 7
+#define HDCP_INT_CLR (BIT(1) | BIT(5) | BIT(7) | BIT(9) | BIT(13))
+
struct hdmi_hdcp_ctrl {
u32 auth_retries;
u32 tp_msgid;
@@ -1139,16 +1141,15 @@
}
/*
- * Need to set the state to inactive here so that any ongoing
- * reauth works will know that the HDCP session has been turned off
+ * Disable HDCP interrupts.
+ * Also, need to set the state to inactive here so that any ongoing
+ * reauth works will know that the HDCP session has been turned off.
*/
mutex_lock(hdcp_ctrl->init_data.mutex);
+ DSS_REG_W(io, HDMI_HDCP_INT_CTRL, 0);
hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE;
mutex_unlock(hdcp_ctrl->init_data.mutex);
- /* Disable HDCP interrupts */
- DSS_REG_W(io, HDMI_HDCP_INT_CTRL, 0);
-
/*
* Cancel any pending auth/reauth attempts.
* If one is ongoing, this will wait for it to finish.
@@ -1193,7 +1194,7 @@
if (HDCP_STATE_INACTIVE == hdcp_ctrl->hdcp_state) {
DEV_ERR("%s: HDCP inactive. Just clear int and return.\n",
__func__);
- DSS_REG_W(io, HDMI_HDCP_INT_CTRL, hdcp_int_val);
+ DSS_REG_W(io, HDMI_HDCP_INT_CTRL, HDCP_INT_CLR);
return 0;
}
diff --git a/drivers/video/msm/mdss/mdss_hdmi_tx.c b/drivers/video/msm/mdss/mdss_hdmi_tx.c
index 87b7526..b45a446 100644
--- a/drivers/video/msm/mdss/mdss_hdmi_tx.c
+++ b/drivers/video/msm/mdss/mdss_hdmi_tx.c
@@ -63,8 +63,11 @@
/* Supported HDMI Audio channels */
#define MSM_HDMI_AUDIO_CHANNEL_2 2
+#define MSM_HDMI_AUDIO_CHANNEL_3 3
#define MSM_HDMI_AUDIO_CHANNEL_4 4
+#define MSM_HDMI_AUDIO_CHANNEL_5 5
#define MSM_HDMI_AUDIO_CHANNEL_6 6
+#define MSM_HDMI_AUDIO_CHANNEL_7 7
#define MSM_HDMI_AUDIO_CHANNEL_8 8
enum msm_hdmi_supported_audio_sample_rates {
@@ -1718,8 +1721,6 @@
} else {
msm_dss_enable_clk(power_data->clk_config,
power_data->num_clk, 0);
- msm_dss_clk_set_rate(power_data->clk_config,
- power_data->num_clk);
msm_dss_enable_gpio(power_data->gpio_config,
power_data->num_gpio, 0);
msm_dss_enable_vreg(power_data->vreg_config,
@@ -2051,12 +2052,15 @@
switch (num_of_channels) {
case MSM_HDMI_AUDIO_CHANNEL_2:
break;
+ case MSM_HDMI_AUDIO_CHANNEL_3:
case MSM_HDMI_AUDIO_CHANNEL_4:
channel_count = 3;
break;
+ case MSM_HDMI_AUDIO_CHANNEL_5:
case MSM_HDMI_AUDIO_CHANNEL_6:
channel_count = 5;
break;
+ case MSM_HDMI_AUDIO_CHANNEL_7:
case MSM_HDMI_AUDIO_CHANNEL_8:
channel_count = 7;
break;
@@ -2473,12 +2477,6 @@
hdmi_tx_powerdown_phy(hdmi_ctrl);
- /*
- * this is needed to avoid pll lock failure due to
- * clk framework's rate caching.
- */
- hdmi_ctrl->pdata.power_data[HDMI_TX_CORE_PM].clk_config[0].rate = 0;
-
hdmi_cec_deconfig(hdmi_ctrl->feature_data[HDMI_TX_FEAT_CEC]);
hdmi_tx_core_off(hdmi_ctrl);
diff --git a/drivers/video/msm/mdss/mdss_mdp.c b/drivers/video/msm/mdss/mdss_mdp.c
index bac01fc..b218b1e 100644
--- a/drivers/video/msm/mdss/mdss_mdp.c
+++ b/drivers/video/msm/mdss/mdss_mdp.c
@@ -646,6 +646,7 @@
if (!enable) {
msm_bus_scale_client_update_request(
mdata->bus_hdl, 0);
+ mdss_iommu_dettach(mdata);
pm_runtime_put(&mdata->pdev->dev);
} else {
pm_runtime_get_sync(&mdata->pdev->dev);
@@ -994,6 +995,9 @@
/* swap */
writel_relaxed(1, offset + 16);
}
+
+ mdata->nmax_concurrent_ad_hw = (mdata->mdp_rev <= MDSS_MDP_HW_REV_102) ?
+ 1 : 2;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
pr_debug("MDP hw init done\n");
@@ -1018,6 +1022,11 @@
if (rc)
return rc;
+ mdata->hist_intr.req = 0;
+ mdata->hist_intr.curr = 0;
+ mdata->hist_intr.state = 0;
+ spin_lock_init(&mdata->hist_intr.lock);
+
mdata->iclient = msm_ion_client_create(-1, mdata->pdev->name);
if (IS_ERR_OR_NULL(mdata->iclient)) {
pr_err("msm_ion_client_create() return error (%p)\n",
@@ -1057,15 +1066,20 @@
#define SPRINT(fmt, ...) \
(cnt += scnprintf(buf + cnt, len - cnt, fmt, ##__VA_ARGS__))
- SPRINT("mdp_version=5 hw_rev=%d\n", mdata->mdp_rev);
+ SPRINT("mdp_version=5\n");
+ SPRINT("hw_rev=%d\n", mdata->mdp_rev);
SPRINT("rgb_pipes=%d\n", mdata->nrgb_pipes);
SPRINT("vig_pipes=%d\n", mdata->nvig_pipes);
SPRINT("dma_pipes=%d\n", mdata->ndma_pipes);
SPRINT("smp_count=%d\n", mdata->smp_mb_cnt);
SPRINT("smp_size=%d\n", mdata->smp_mb_size);
- SPRINT("max downscale ratio=%d\n", MAX_DOWNSCALE_RATIO);
- SPRINT("max upscale ratio=%d\n", MAX_UPSCALE_RATIO);
- SPRINT("features:");
+ SPRINT("max_downscale_ratio=%d\n", MAX_DOWNSCALE_RATIO);
+ SPRINT("max_upscale_ratio=%d\n", MAX_UPSCALE_RATIO);
+ if (mdata->max_bw_low)
+ SPRINT("max_bandwidth_low=%u\n", mdata->max_bw_low);
+ if (mdata->max_bw_high)
+ SPRINT("max_bandwidth_high=%u\n", mdata->max_bw_high);
+ SPRINT("features=");
if (mdata->has_bwc)
SPRINT(" bwc");
if (mdata->has_decimation)
@@ -1962,6 +1976,16 @@
prop = of_find_property(pdev->dev.of_node, "batfet-supply", NULL);
mdata->batfet_required = prop ? true : false;
+ rc = of_property_read_u32(pdev->dev.of_node,
+ "qcom,max-bandwidth-low-kbps", &mdata->max_bw_low);
+ if (rc)
+ pr_debug("max bandwidth (low) property not specified\n");
+
+ rc = of_property_read_u32(pdev->dev.of_node,
+ "qcom,max-bandwidth-high-kbps", &mdata->max_bw_high);
+ if (rc)
+ pr_debug("max bandwidth (high) property not specified\n");
+
return 0;
}
@@ -1977,9 +2001,11 @@
mdata->ad_cfgs = NULL;
return 0;
}
+
if (mdata->nad_cfgs > mdata->nmixers_intf)
return -EINVAL;
+
mdata->has_wb_ad = of_property_read_bool(pdev->dev.of_node,
"qcom,mdss-has-wb-ad");
diff --git a/drivers/video/msm/mdss/mdss_mdp.h b/drivers/video/msm/mdss/mdss_mdp.h
index d140ea0..769f9b2 100644
--- a/drivers/video/msm/mdss/mdss_mdp.h
+++ b/drivers/video/msm/mdss/mdss_mdp.h
@@ -117,6 +117,12 @@
MDSS_MDP_MAX_CSC
};
+struct splash_pipe_cfg {
+ int width;
+ int height;
+ int mixer;
+};
+
struct mdss_mdp_ctl;
typedef void (*mdp_vsync_handler_t)(struct mdss_mdp_ctl *, ktime_t);
@@ -275,10 +281,16 @@
spinlock_t hist_lock;
};
-struct mdss_ad_info {
+struct mdss_mdp_ad {
char __iomem *base;
u8 num;
+};
+
+struct mdss_ad_info {
+ u8 num;
+ u8 calc_hw_num;
u32 sts;
+ u32 reg_sts;
u32 state;
u32 ad_data;
u32 ad_data_mode;
@@ -292,6 +304,7 @@
struct completion comp;
u32 last_str;
u32 last_bl;
+ u32 bl_data;
u32 calc_itr;
uint32_t bl_bright_shift;
uint32_t bl_lin[AD_BL_LIN_LEN];
@@ -354,6 +367,8 @@
u8 blend_op;
u8 overfetch_disable;
u32 transp;
+ u32 bg_color;
+ u8 has_buf;
struct msm_fb_data_type *mfd;
struct mdss_mdp_mixer *mixer;
@@ -451,6 +466,8 @@
irqreturn_t mdss_mdp_isr(int irq, void *ptr);
int mdss_iommu_attach(struct mdss_data_type *mdata);
+int mdss_iommu_dettach(struct mdss_data_type *mdata);
+int mdss_mdp_scan_cont_splash(void);
void mdss_mdp_irq_clear(struct mdss_data_type *mdata,
u32 intr_type, u32 intf_num);
int mdss_mdp_irq_enable(u32 intr_type, u32 intf_num);
@@ -512,6 +529,8 @@
int mdss_mdp_mixer_handoff(struct mdss_mdp_ctl *ctl, u32 num,
struct mdss_mdp_pipe *pipe);
+int mdss_mdp_scan_pipes(void);
+
struct mdss_mdp_mixer *mdss_mdp_wb_mixer_alloc(int rotator);
int mdss_mdp_wb_mixer_destroy(struct mdss_mdp_mixer *mixer);
struct mdss_mdp_mixer *mdss_mdp_mixer_get(struct mdss_mdp_ctl *ctl, int mux);
@@ -544,6 +563,7 @@
int mdss_hw_init(struct mdss_data_type *mdata);
int mdss_mdp_pa_config(struct mdp_pa_cfg_data *config, u32 *copyback);
+int mdss_mdp_pa_v2_config(struct mdp_pa_v2_cfg_data *config, u32 *copyback);
int mdss_mdp_pcc_config(struct mdp_pcc_cfg_data *cfg_ptr, u32 *copyback);
int mdss_mdp_igc_lut_config(struct mdp_igc_lut_data *config, u32 *copyback,
u32 copy_from_kernel);
@@ -552,8 +572,10 @@
int mdss_mdp_dither_config(struct mdp_dither_cfg_data *config, u32 *copyback);
int mdss_mdp_gamut_config(struct mdp_gamut_cfg_data *config, u32 *copyback);
-int mdss_mdp_histogram_start(struct mdp_histogram_start_req *req);
-int mdss_mdp_histogram_stop(u32 block);
+int mdss_mdp_hist_intr_req(struct mdss_intr *intr, u32 bits, bool en);
+int mdss_mdp_hist_intr_setup(struct mdss_intr *intr, int state);
+int mdss_mdp_hist_start(struct mdp_histogram_start_req *req);
+int mdss_mdp_hist_stop(u32 block);
int mdss_mdp_hist_collect(struct mdp_histogram_data *hist);
void mdss_mdp_hist_intr_done(u32 isr);
@@ -561,7 +583,7 @@
struct mdss_ad_init_cfg *init_cfg);
int mdss_mdp_ad_input(struct msm_fb_data_type *mfd,
struct mdss_ad_input *input, int wait);
-int mdss_mdp_ad_addr_setup(struct mdss_data_type *mdata, u32 *ad_off);
+int mdss_mdp_ad_addr_setup(struct mdss_data_type *mdata, u32 *ad_offsets);
int mdss_mdp_calib_mode(struct msm_fb_data_type *mfd,
struct mdss_calib_cfg *cfg);
diff --git a/drivers/video/msm/mdss/mdss_mdp_ctl.c b/drivers/video/msm/mdss/mdss_mdp_ctl.c
index aa7c4dd..bad4d06 100644
--- a/drivers/video/msm/mdss/mdss_mdp_ctl.c
+++ b/drivers/video/msm/mdss/mdss_mdp_ctl.c
@@ -615,6 +615,7 @@
{
switch (ctl->panel_data->panel_info.type) {
case MIPI_VIDEO_PANEL:
+ case EDP_PANEL:
return mdss_mdp_video_reconfigure_splash_done(ctl, handoff);
case MIPI_CMD_PANEL:
return mdss_mdp_cmd_reconfigure_splash_done(ctl, handoff);
@@ -974,6 +975,8 @@
mixer->width = sctl->width;
mixer->height = sctl->height;
+ mixer->roi = (struct mdss_mdp_img_rect)
+ {0, 0, mixer->width, mixer->height};
sctl->mixer_left = mixer;
return mdss_mdp_set_split_ctl(ctl, sctl);
@@ -1108,6 +1111,7 @@
int mdss_mdp_ctl_start(struct mdss_mdp_ctl *ctl)
{
struct mdss_mdp_ctl *sctl;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
int ret = 0;
if (ctl->power_on) {
@@ -1155,6 +1159,7 @@
mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_PACK_3D, 0);
}
}
+ mdss_mdp_hist_intr_setup(&mdata->hist_intr, MDSS_IRQ_RESUME);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
error:
@@ -1167,6 +1172,7 @@
{
struct mdss_mdp_ctl *sctl;
int ret = 0;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
u32 off;
if (!ctl->power_on) {
@@ -1182,6 +1188,8 @@
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+ mdss_mdp_hist_intr_setup(&mdata->hist_intr, MDSS_IRQ_SUSPEND);
+
if (ctl->stop_fnc)
ret = ctl->stop_fnc(ctl);
else
@@ -1782,6 +1790,11 @@
{
int ret;
+ if (!ctl) {
+ pr_err("invalid ctl\n");
+ return -ENODEV;
+ }
+
ret = mutex_lock_interruptible(&ctl->lock);
if (ret)
return ret;
diff --git a/drivers/video/msm/mdss/mdss_mdp_hwio.h b/drivers/video/msm/mdss/mdss_mdp_hwio.h
index 52ca42c..b6f94d0 100644
--- a/drivers/video/msm/mdss/mdss_mdp_hwio.h
+++ b/drivers/video/msm/mdss/mdss_mdp_hwio.h
@@ -20,6 +20,7 @@
#define GC_LUT_SEGMENTS 16
#define ENHIST_LUT_ENTRIES 256
#define HIST_V_SIZE 256
+#define SIX_ZONE_LUT_ENTRIES 384
#define MDSS_MDP_HW_REV_100 0x10000000
#define MDSS_MDP_HW_REV_102 0x10020000
@@ -216,8 +217,20 @@
#define MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEX 0x228
#define MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEY 0x22C
#define MDSS_MDP_REG_VIG_QSEED2_SHARP 0x230
+#define MDSS_MDP_REG_VIG_MEM_COL_BASE 0x288
#define MDSS_MDP_REG_VIG_PA_BASE 0x310
+#define MDSS_MDP_VIG_OP_PA_SAT_ZERO_EXP_EN BIT(2)
+#define MDSS_MDP_VIG_OP_PA_MEM_PROTECT_EN BIT(3)
+#define MDSS_MDP_VIG_OP_PA_EN BIT(4)
+#define MDSS_MDP_VIG_OP_PA_MEM_COL_SKIN_MASK BIT(5)
+#define MDSS_MDP_VIG_OP_PA_MEM_COL_FOL_MASK BIT(6)
+#define MDSS_MDP_VIG_OP_PA_MEM_COL_SKY_MASK BIT(7)
+#define MDSS_MDP_VIG_OP_PA_HUE_MASK BIT(25)
+#define MDSS_MDP_VIG_OP_PA_SAT_MASK BIT(26)
+#define MDSS_MDP_VIG_OP_PA_VAL_MASK BIT(27)
+#define MDSS_MDP_VIG_OP_PA_CONT_MASK BIT(28)
+
#define MDSS_MDP_REG_SCALE_CONFIG 0x204
#define MDSS_MDP_REG_SCALE_PHASE_STEP_X 0x210
#define MDSS_MDP_REG_SCALE_PHASE_STEP_Y 0x214
@@ -359,6 +372,8 @@
#define MDSS_MDP_REG_WB_CSC_BASE 0x260
#define MDSS_MDP_REG_WB_DST_ADDR_SW_STATUS 0x2B0
+#define MDSS_MDP_MAX_AD_AL 65535
+#define MDSS_MDP_MAX_AD_STR 255
#define MDSS_MDP_REG_AD_BYPASS 0x000
#define MDSS_MDP_REG_AD_CTRL_0 0x004
@@ -394,6 +409,11 @@
#define MDSS_MDP_REG_AD_STR_OUT 0x14C
#define MDSS_MDP_REG_AD_BL_OUT 0x154
#define MDSS_MDP_REG_AD_CALC_DONE 0x158
+#define MDSS_MDP_REG_AD_FRAME_END 0x15C
+#define MDSS_MDP_REG_AD_PROCS_END 0x160
+#define MDSS_MDP_REG_AD_FRAME_START 0x164
+#define MDSS_MDP_REG_AD_PROCS_START 0x168
+#define MDSS_MDP_REG_AD_TILE_CTRL 0x16C
enum mdss_mdp_dspp_index {
MDSS_MDP_DSPP0,
@@ -413,6 +433,28 @@
#define MDSS_MDP_REG_DSPP_GAMUT_BASE 0x2DC
#define MDSS_MDP_REG_DSPP_GC_BASE 0x2B0
+#define MDSS_MDP_DSPP_OP_IGC_LUT_EN BIT(0)
+#define MDSS_MDP_DSPP_OP_PA_SAT_ZERO_EXP_EN BIT(1)
+#define MDSS_MDP_DSPP_OP_PA_MEM_PROTECT_EN BIT(2)
+#define MDSS_MDP_DSPP_OP_PCC_EN BIT(4)
+#define MDSS_MDP_DSPP_OP_PA_MEM_COL_SKIN_MASK BIT(5)
+#define MDSS_MDP_DSPP_OP_PA_MEM_COL_FOL_MASK BIT(6)
+#define MDSS_MDP_DSPP_OP_PA_MEM_COL_SKY_MASK BIT(7)
+#define MDSS_MDP_DSPP_OP_DST_DITHER_EN BIT(8)
+#define MDSS_MDP_DSPP_OP_HIST_EN BIT(16)
+#define MDSS_MDP_DSPP_OP_HIST_LUTV_EN BIT(19)
+#define MDSS_MDP_DSPP_OP_PA_EN BIT(20)
+#define MDSS_MDP_DSPP_OP_ARGC_LUT_EN BIT(22)
+#define MDSS_MDP_DSPP_OP_GAMUT_EN BIT(23)
+#define MDSS_MDP_DSPP_OP_GAMUT_PCC_ORDER BIT(24)
+#define MDSS_MDP_DSPP_OP_PA_HUE_MASK BIT(25)
+#define MDSS_MDP_DSPP_OP_PA_SAT_MASK BIT(26)
+#define MDSS_MDP_DSPP_OP_PA_VAL_MASK BIT(27)
+#define MDSS_MDP_DSPP_OP_PA_CONT_MASK BIT(28)
+#define MDSS_MDP_DSPP_OP_PA_SIX_ZONE_HUE_MASK BIT(29)
+#define MDSS_MDP_DSPP_OP_PA_SIX_ZONE_SAT_MASK BIT(30)
+#define MDSS_MDP_DSPP_OP_PA_SIX_ZONE_VAL_MASK BIT(31)
+
enum mdss_mpd_intf_index {
MDSS_MDP_NO_INTF,
MDSS_MDP_INTF0,
diff --git a/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c b/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c
index d3e18ac..c4a0645 100644
--- a/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c
+++ b/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c
@@ -196,12 +196,14 @@
static inline void mdss_mdp_cmd_clk_on(struct mdss_mdp_cmd_ctx *ctx)
{
unsigned long flags;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
mutex_lock(&ctx->clk_mtx);
if (!ctx->clk_enabled) {
ctx->clk_enabled = 1;
mdss_mdp_ctl_intf_event
(ctx->ctl, MDSS_EVENT_PANEL_CLK_CTRL, (void *)1);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+ mdss_mdp_hist_intr_setup(&mdata->hist_intr, MDSS_IRQ_RESUME);
}
spin_lock_irqsave(&ctx->clk_lock, flags);
if (!ctx->rdptr_enabled)
@@ -214,6 +216,7 @@
static inline void mdss_mdp_cmd_clk_off(struct mdss_mdp_cmd_ctx *ctx)
{
unsigned long flags;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
int set_clk_off = 0;
mutex_lock(&ctx->clk_mtx);
@@ -224,6 +227,7 @@
if (ctx->clk_enabled && set_clk_off) {
ctx->clk_enabled = 0;
+ mdss_mdp_hist_intr_setup(&mdata->hist_intr, MDSS_IRQ_SUSPEND);
mdss_mdp_ctl_intf_event
(ctx->ctl, MDSS_EVENT_PANEL_CLK_CTRL, (void *)0);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
@@ -510,14 +514,14 @@
mdss_mdp_cmd_set_partial_roi(ctl);
+ mdss_mdp_cmd_clk_on(ctx);
+
/*
* tx dcs command if had any
*/
mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_DSI_CMDLIST_KOFF,
(void *)&ctx->recovery);
- mdss_mdp_cmd_clk_on(ctx);
-
INIT_COMPLETION(ctx->pp_comp);
mdss_mdp_irq_enable(MDSS_MDP_IRQ_PING_PONG_COMP, ctx->pp_num);
mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_START, 1);
diff --git a/drivers/video/msm/mdss/mdss_mdp_overlay.c b/drivers/video/msm/mdss/mdss_mdp_overlay.c
index 0fb01ad..14b486a 100644
--- a/drivers/video/msm/mdss/mdss_mdp_overlay.c
+++ b/drivers/video/msm/mdss/mdss_mdp_overlay.c
@@ -504,6 +504,7 @@
} else {
pipe->overfetch_disable = 0;
}
+ pipe->bg_color = req->bg_color;
req->id = pipe->ndx;
pipe->req_data = *req;
@@ -539,11 +540,10 @@
pipe->pp_cfg.hist_cfg.frame_cnt;
hist.bit_mask = pipe->pp_cfg.hist_cfg.bit_mask;
hist.num_bins = pipe->pp_cfg.hist_cfg.num_bins;
- mdss_mdp_histogram_start(&hist);
+ mdss_mdp_hist_start(&hist);
} else if (pipe->pp_cfg.hist_cfg.ops &
MDP_PP_OPS_DISABLE) {
- mdss_mdp_histogram_stop(
- pipe->pp_cfg.hist_cfg.block);
+ mdss_mdp_hist_stop(pipe->pp_cfg.hist_cfg.block);
}
}
len = pipe->pp_cfg.hist_lut_cfg.len;
@@ -562,10 +562,14 @@
if ((pipe->flags & MDP_DEINTERLACE) && !pipe->scale.enable_pxl_ext) {
if (pipe->flags & MDP_SOURCE_ROTATED_90) {
+ pipe->src.x = DIV_ROUND_UP(pipe->src.x, 2);
+ pipe->src.x &= ~1;
pipe->src.w /= 2;
pipe->img_width /= 2;
} else {
pipe->src.h /= 2;
+ pipe->src.y = DIV_ROUND_UP(pipe->src.y, 2);
+ pipe->src.y &= ~1;
}
}
@@ -596,6 +600,7 @@
}
pipe->params_changed++;
+ pipe->has_buf = 0;
req->vert_deci = pipe->vert_deci;
@@ -826,6 +831,9 @@
if (ctl->power_on) {
if (!mdp5_data->mdata->batfet)
mdss_mdp_batfet_ctrl(mdp5_data->mdata, true);
+ if (!is_mdss_iommu_attached() &&
+ !mfd->panel_info->cont_splash_enabled)
+ mdss_iommu_attach(mdp5_data->mdata);
return 0;
}
@@ -944,6 +952,9 @@
int ret = 0;
int sd_in_pipe = 0;
+ if (!is_mdss_iommu_attached() && !mfd->panel_info->cont_splash_enabled)
+ mdss_iommu_attach(mdp5_data->mdata);
+
if (ctl->shared_lock)
mutex_lock(ctl->shared_lock);
@@ -1027,8 +1038,9 @@
} else if (pipe->front_buf.num_planes) {
buf = &pipe->front_buf;
} else {
- pr_warn("pipe queue w/o buffer\n");
- continue;
+ pr_debug("no buf detected pnum=%d use solid fill\n",
+ pipe->num);
+ buf = NULL;
}
ret = mdss_mdp_pipe_queue_data(pipe, buf);
@@ -1153,11 +1165,13 @@
/**
* mdss_mdp_overlay_release_all() - release any overlays associated with fb dev
* @mfd: Msm frame buffer structure associated with fb device
+ * @release_all: ignore pid and release all the pipes
*
* Release any resources allocated by calling process, this can be called
* on fb_release to release any overlays/rotator sessions left open.
*/
-static int __mdss_mdp_overlay_release_all(struct msm_fb_data_type *mfd)
+static int __mdss_mdp_overlay_release_all(struct msm_fb_data_type *mfd,
+ bool release_all)
{
struct mdss_mdp_pipe *pipe;
struct mdss_mdp_rotator_session *rot, *tmp;
@@ -1171,7 +1185,7 @@
mutex_lock(&mdp5_data->ov_lock);
mutex_lock(&mfd->lock);
list_for_each_entry(pipe, &mdp5_data->pipes_used, used_list) {
- if (!mfd->ref_cnt || (pipe->pid == pid)) {
+ if (release_all || (pipe->pid == pid)) {
unset_ndx |= pipe->ndx;
cnt++;
}
@@ -1183,6 +1197,9 @@
cnt++;
}
+ pr_debug("release_all=%d mfd->ref_cnt=%d unset_ndx=0x%x cnt=%d\n",
+ release_all, mfd->ref_cnt, unset_ndx, cnt);
+
mutex_unlock(&mfd->lock);
if (unset_ndx) {
@@ -1251,6 +1268,7 @@
if (IS_ERR_VALUE(ret)) {
pr_err("src_data pmem error\n");
}
+ pipe->has_buf = 1;
mdss_mdp_pipe_unmap(pipe);
return ret;
@@ -1493,6 +1511,7 @@
buf->p[0].addr += offset;
buf->p[0].len = fbi->fix.smem_len - offset;
buf->num_planes = 1;
+ pipe->has_buf = 1;
mdss_mdp_pipe_unmap(pipe);
if (fbi->var.xres > MAX_MIXER_WIDTH || mfd->split_display) {
@@ -1507,6 +1526,7 @@
goto pan_display_error;
}
pipe->back_buf = *buf;
+ pipe->has_buf = 1;
mdss_mdp_pipe_unmap(pipe);
}
mutex_unlock(&mdp5_data->ov_lock);
@@ -1942,6 +1962,11 @@
©back);
break;
+ case mdp_op_pa_v2_cfg:
+ ret = mdss_mdp_pa_v2_config(&mdp_pp.data.pa_v2_cfg_data,
+ ©back);
+ break;
+
case mdp_op_pcc_cfg:
ret = mdss_mdp_pcc_config(&mdp_pp.data.pcc_cfg_data,
©back);
@@ -2048,7 +2073,7 @@
if (ret)
return ret;
- ret = mdss_mdp_histogram_start(&hist_req);
+ ret = mdss_mdp_hist_start(&hist_req);
break;
case MSMFB_HISTOGRAM_STOP:
@@ -2056,7 +2081,7 @@
if (ret)
return ret;
- ret = mdss_mdp_histogram_stop(block);
+ ret = mdss_mdp_hist_stop(block);
if (ret)
return ret;
@@ -2092,7 +2117,10 @@
struct msmfb_metadata *metadata)
{
struct mdss_data_type *mdata = mfd_to_mdata(mfd);
+ struct mdss_mdp_ctl *ctl = mfd_to_ctl(mfd);
int ret = 0;
+ if (!ctl)
+ return -EPERM;
switch (metadata->op) {
case metadata_op_vic:
if (mfd->panel_info)
@@ -2104,7 +2132,7 @@
case metadata_op_crc:
if (!mfd->panel_power_on)
return -EPERM;
- ret = mdss_misr_crc_set(mdata, &metadata->data.misr_request);
+ ret = mdss_misr_set(mdata, &metadata->data.misr_request, ctl);
break;
case metadata_op_wb_format:
ret = mdss_mdp_wb_set_format(mfd,
@@ -2140,7 +2168,10 @@
struct msmfb_metadata *metadata)
{
struct mdss_data_type *mdata = mfd_to_mdata(mfd);
+ struct mdss_mdp_ctl *ctl = mfd_to_ctl(mfd);
int ret = 0;
+ if (!ctl)
+ return -EPERM;
switch (metadata->op) {
case metadata_op_frame_rate:
metadata->data.panel_frame_rate =
@@ -2152,7 +2183,7 @@
case metadata_op_crc:
if (!mfd->panel_power_on)
return -EPERM;
- ret = mdss_misr_crc_get(mdata, &metadata->data.misr_request);
+ ret = mdss_misr_get(mdata, &metadata->data.misr_request, ctl);
break;
case metadata_op_wb_format:
ret = mdss_mdp_wb_get_format(mfd, &metadata->data.mixer_cfg);
diff --git a/drivers/video/msm/mdss/mdss_mdp_pipe.c b/drivers/video/msm/mdss/mdss_mdp_pipe.c
index 25cb9dd..0abd4d5 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pipe.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pipe.c
@@ -166,7 +166,7 @@
struct mdss_mdp_plane_sizes ps;
int i;
int rc = 0, rot_mode = 0;
- u32 nlines;
+ u32 nlines, format;
u16 width;
width = pipe->src.w >> pipe->horz_deci;
@@ -179,8 +179,25 @@
pr_debug("BWC SMP strides ystride0=%x ystride1=%x\n",
ps.ystride[0], ps.ystride[1]);
} else {
- rc = mdss_mdp_get_plane_sizes(pipe->src_fmt->format,
- width, pipe->src.h, &ps, 0);
+ format = pipe->src_fmt->format;
+ /*
+ * when decimation block is present, all chroma planes
+ * are fetched on a single SMP plane for chroma pixels
+ */
+ if (mdata->has_decimation) {
+ switch (pipe->src_fmt->chroma_sample) {
+ case MDSS_MDP_CHROMA_H2V1:
+ format = MDP_Y_CRCB_H2V1;
+ break;
+ case MDSS_MDP_CHROMA_420:
+ format = MDP_Y_CBCR_H2V2;
+ break;
+ default:
+ break;
+ }
+ }
+ rc = mdss_mdp_get_plane_sizes(format, width, pipe->src.h,
+ &ps, 0);
if (rc)
return rc;
@@ -191,15 +208,6 @@
max(pipe->mixer->width, width);
} else if (mdata->has_decimation) {
/*
- * when decimation block is used, all chroma planes
- * are fetched on a single SMP plane for chroma pixels
- */
- if (ps.num_planes == 3) {
- ps.num_planes = 2;
- ps.ystride[1] += ps.ystride[2];
- }
-
- /*
* To avoid quailty loss, MDP does one less decimation
* on chroma components if they are subsampled.
* Account for this to have enough SMPs for latency
@@ -924,6 +932,8 @@
secure = (pipe->flags & MDP_SECURE_OVERLAY_SESSION ? 0xF : 0x0);
mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC_FORMAT, format);
+ mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC_CONSTANT_COLOR,
+ pipe->bg_color);
mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC_ADDR_SW_STATUS, secure);
return 0;
@@ -962,7 +972,8 @@
(pipe->mixer->type == MDSS_MDP_MIXER_TYPE_WRITEBACK)
&& (ctl->mdata->mixer_switched)) ||
ctl->roi_changed;
- if (src_data == NULL) {
+ if (src_data == NULL || !pipe->has_buf) {
+ pipe->params_changed = 0;
mdss_mdp_pipe_solidfill_setup(pipe);
goto update_nobuf;
}
diff --git a/drivers/video/msm/mdss/mdss_mdp_pp.c b/drivers/video/msm/mdss/mdss_mdp_pp.c
index dc7b8b3..dd46f0e 100644
--- a/drivers/video/msm/mdss/mdss_mdp_pp.c
+++ b/drivers/video/msm/mdss/mdss_mdp_pp.c
@@ -184,9 +184,27 @@
#define PP_FLAGS_DIRTY_PGC 0x100
#define PP_FLAGS_DIRTY_SHARP 0x200
+#define PP_SSPP 0
+#define PP_DSPP 1
+
#define PP_STS_ENABLE 0x1
#define PP_STS_GAMUT_FIRST 0x2
+#define PP_STS_PA_HUE_MASK 0x2
+#define PP_STS_PA_SAT_MASK 0x4
+#define PP_STS_PA_VAL_MASK 0x8
+#define PP_STS_PA_CONT_MASK 0x10
+#define PP_STS_PA_MEM_PROTECT_EN 0x20
+#define PP_STS_PA_MEM_COL_SKIN_MASK 0x40
+#define PP_STS_PA_MEM_COL_FOL_MASK 0x80
+#define PP_STS_PA_MEM_COL_SKY_MASK 0x100
+#define PP_STS_PA_SIX_ZONE_HUE_MASK 0x200
+#define PP_STS_PA_SIX_ZONE_SAT_MASK 0x400
+#define PP_STS_PA_SIX_ZONE_VAL_MASK 0x800
+#define PP_STS_PA_SAT_ZERO_EXP_EN 0x1000
+
+#define PP_AD_BAD_HW_NUM 255
+
#define PP_AD_STATE_INIT 0x2
#define PP_AD_STATE_CFG 0x4
#define PP_AD_STATE_DATA 0x8
@@ -205,6 +223,7 @@
#define PP_AD_STS_DIRTY_CFG 0x4
#define PP_AD_STS_DIRTY_DATA 0x8
#define PP_AD_STS_DIRTY_VSYNC 0x10
+#define PP_AD_STS_DIRTY_ENABLE 0x20
#define PP_AD_STS_IS_DIRTY(sts) (((sts) & PP_AD_STS_DIRTY_INIT) ||\
((sts) & PP_AD_STS_DIRTY_CFG))
@@ -262,6 +281,9 @@
gc_lut_b[MDSS_BLOCK_DISP_NUM][GC_LUT_SEGMENTS];
u32 enhist_lut[MDSS_BLOCK_DISP_NUM][ENHIST_LUT_ENTRIES];
struct mdp_pa_cfg pa_disp_cfg[MDSS_BLOCK_DISP_NUM];
+ struct mdp_pa_v2_data pa_v2_disp_cfg[MDSS_BLOCK_DISP_NUM];
+ u32 six_zone_lut_curve_p0[MDSS_BLOCK_DISP_NUM][SIX_ZONE_LUT_ENTRIES];
+ u32 six_zone_lut_curve_p1[MDSS_BLOCK_DISP_NUM][SIX_ZONE_LUT_ENTRIES];
struct mdp_pcc_cfg_data pcc_disp_cfg[MDSS_BLOCK_DISP_NUM];
struct mdp_igc_lut_data igc_disp_cfg[MDSS_BLOCK_DISP_NUM];
struct mdp_pgc_lut_data argc_disp_cfg[MDSS_BLOCK_DISP_NUM];
@@ -279,51 +301,85 @@
static DEFINE_MUTEX(mdss_pp_mutex);
static struct mdss_pp_res_type *mdss_pp_res;
-static void pp_hist_read(char __iomem *v_base,
+static u32 pp_hist_read(char __iomem *v_addr,
struct pp_hist_col_info *hist_info);
static int pp_histogram_setup(u32 *op, u32 block, struct mdss_mdp_mixer *mix);
static int pp_histogram_disable(struct pp_hist_col_info *hist_info,
u32 done_bit, char __iomem *ctl_base);
-static void pp_update_pcc_regs(u32 offset,
+static void pp_update_pcc_regs(char __iomem *addr,
struct mdp_pcc_cfg_data *cfg_ptr);
static void pp_update_igc_lut(struct mdp_igc_lut_data *cfg,
- u32 offset, u32 blk_idx);
-static void pp_update_gc_one_lut(u32 offset,
+ char __iomem *addr, u32 blk_idx);
+static void pp_update_gc_one_lut(char __iomem *addr,
struct mdp_ar_gc_lut_data *lut_data,
uint8_t num_stages);
-static void pp_update_argc_lut(u32 offset,
+static void pp_update_argc_lut(char __iomem *addr,
struct mdp_pgc_lut_data *config);
static void pp_update_hist_lut(char __iomem *base,
struct mdp_hist_lut_data *cfg);
static int pp_gm_has_invalid_lut_size(struct mdp_gamut_cfg_data *config);
static void pp_gamut_config(struct mdp_gamut_cfg_data *gamut_cfg,
- u32 base, struct pp_sts_type *pp_sts);
-static void pp_pa_config(unsigned long flags, u32 base,
+ char __iomem *base, struct pp_sts_type *pp_sts);
+static void pp_pa_config(unsigned long flags, char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_pa_cfg *pa_config);
-static void pp_pcc_config(unsigned long flags, u32 base,
+static void pp_pa_v2_config(unsigned long flags, char __iomem *addr,
+ struct pp_sts_type *pp_sts,
+ struct mdp_pa_v2_data *pa_v2_config,
+ int mdp_location);
+static void pp_pcc_config(unsigned long flags, char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_pcc_cfg_data *pcc_config);
-static void pp_igc_config(unsigned long flags, u32 base,
+static void pp_igc_config(unsigned long flags, char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_igc_lut_data *igc_config,
u32 pipe_num);
-static void pp_enhist_config(unsigned long flags, char __iomem *base,
+static void pp_enhist_config(unsigned long flags, char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_hist_lut_data *enhist_cfg);
-static void pp_sharp_config(char __iomem *offset,
+static void pp_dither_config(char __iomem *addr,
+ struct pp_sts_type *pp_sts,
+ struct mdp_dither_cfg_data *dither_cfg);
+static void pp_dspp_opmode_config(struct pp_sts_type *pp_sts, u32 *opmode,
+ int mdp_rev);
+static void pp_sharp_config(char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_sharp_cfg *sharp_config);
+static void pp_update_pa_v2_vig_opmode(struct pp_sts_type *pp_sts,
+ u32 *opmode);
+static int pp_copy_pa_six_zone_lut(struct mdp_pa_v2_cfg_data *pa_v2_config,
+ u32 disp_num);
+static void pp_update_pa_v2_global_adj_regs(char __iomem *addr,
+ struct mdp_pa_v2_data *pa_config);
+static void pp_update_pa_v2_mem_col(char __iomem *addr,
+ struct mdp_pa_v2_data *pa_v2_config);
+static void pp_update_pa_v2_mem_col_regs(char __iomem *addr,
+ struct mdp_pa_mem_col_cfg *cfg);
+static void pp_update_pa_v2_six_zone_regs(char __iomem *addr,
+ struct mdp_pa_v2_data *pa_v2_config);
+static void pp_update_pa_v2_sts(struct pp_sts_type *pp_sts,
+ struct mdp_pa_v2_data *pa_v2_config);
+static int pp_read_pa_v2_regs(char __iomem *addr,
+ struct mdp_pa_v2_data *pa_v2_config,
+ u32 disp_num);
+static void pp_read_pa_mem_col_regs(char __iomem *addr,
+ struct mdp_pa_mem_col_cfg *mem_col_cfg);
static int mdss_ad_init_checks(struct msm_fb_data_type *mfd);
static int mdss_mdp_get_ad(struct msm_fb_data_type *mfd,
struct mdss_ad_info **ad);
static int pp_update_ad_input(struct msm_fb_data_type *mfd);
static void pp_ad_vsync_handler(struct mdss_mdp_ctl *ctl, ktime_t t);
-static void pp_ad_cfg_write(struct mdss_ad_info *ad);
-static void pp_ad_init_write(struct mdss_ad_info *ad);
-static void pp_ad_input_write(struct mdss_ad_info *ad, u32 bl_lvl);
+static void pp_ad_cfg_write(struct mdss_mdp_ad *ad_hw,
+ struct mdss_ad_info *ad);
+static void pp_ad_init_write(struct mdss_mdp_ad *ad_hw,
+ struct mdss_ad_info *ad, struct mdss_mdp_ctl *ctl);
+static void pp_ad_input_write(struct mdss_mdp_ad *ad_hw,
+ struct mdss_ad_info *ad);
+static void pp_ad_bypass_config(struct mdss_ad_info *ad, u32 *opmode);
+static int pp_ad_setup_hw_nums(struct msm_fb_data_type *mfd,
+ struct mdss_ad_info *ad);
static int mdss_mdp_ad_setup(struct msm_fb_data_type *mfd);
-static void pp_ad_cfg_lut(char __iomem *offset, u32 *data);
+static void pp_ad_cfg_lut(char __iomem *addr, u32 *data);
static u32 last_sts, last_state;
@@ -331,7 +387,7 @@
struct mdp_csc_cfg *data)
{
int i, ret = 0;
- char __iomem *base, *off;
+ char __iomem *base, *addr;
u32 val = 0;
struct mdss_data_type *mdata;
struct mdss_mdp_pipe *pipe;
@@ -374,33 +430,33 @@
return ret;
}
- off = base + CSC_MV_OFF;
+ addr = base + CSC_MV_OFF;
for (i = 0; i < 9; i++) {
if (i & 0x1) {
val |= data->csc_mv[i] << 16;
- writel_relaxed(val, off);
- off += sizeof(u32 *);
+ writel_relaxed(val, addr);
+ addr += sizeof(u32 *);
} else {
val = data->csc_mv[i];
}
}
- writel_relaxed(val, off); /* COEFF_33 */
+ writel_relaxed(val, addr); /* COEFF_33 */
- off = base + CSC_BV_OFF;
+ addr = base + CSC_BV_OFF;
for (i = 0; i < 3; i++) {
- writel_relaxed(data->csc_pre_bv[i], off);
- writel_relaxed(data->csc_post_bv[i], off + CSC_POST_OFF);
- off += sizeof(u32 *);
+ writel_relaxed(data->csc_pre_bv[i], addr);
+ writel_relaxed(data->csc_post_bv[i], addr + CSC_POST_OFF);
+ addr += sizeof(u32 *);
}
- off = base + CSC_LV_OFF;
+ addr = base + CSC_LV_OFF;
for (i = 0; i < 6; i += 2) {
val = (data->csc_pre_lv[i] << 8) | data->csc_pre_lv[i+1];
- writel_relaxed(val, off);
+ writel_relaxed(val, addr);
val = (data->csc_post_lv[i] << 8) | data->csc_post_lv[i+1];
- writel_relaxed(val, off + CSC_POST_OFF);
- off += sizeof(u32 *);
+ writel_relaxed(val, addr + CSC_POST_OFF);
+ addr += sizeof(u32 *);
}
return ret;
@@ -423,29 +479,29 @@
}
static void pp_gamut_config(struct mdp_gamut_cfg_data *gamut_cfg,
- u32 base, struct pp_sts_type *pp_sts)
+ char __iomem *base, struct pp_sts_type *pp_sts)
{
- u32 offset;
+ char __iomem *addr;
int i, j;
if (gamut_cfg->flags & MDP_PP_OPS_WRITE) {
- offset = base + MDSS_MDP_REG_DSPP_GAMUT_BASE;
+ addr = base + MDSS_MDP_REG_DSPP_GAMUT_BASE;
for (i = 0; i < MDP_GAMUT_TABLE_NUM; i++) {
for (j = 0; j < gamut_cfg->tbl_size[i]; j++)
- MDSS_MDP_REG_WRITE(offset,
- (u32)gamut_cfg->r_tbl[i][j]);
- offset += 4;
+ writel_relaxed((u32)gamut_cfg->r_tbl[i][j],
+ addr);
+ addr += 4;
}
for (i = 0; i < MDP_GAMUT_TABLE_NUM; i++) {
for (j = 0; j < gamut_cfg->tbl_size[i]; j++)
- MDSS_MDP_REG_WRITE(offset,
- (u32)gamut_cfg->g_tbl[i][j]);
- offset += 4;
+ writel_relaxed((u32)gamut_cfg->g_tbl[i][j],
+ addr);
+ addr += 4;
}
for (i = 0; i < MDP_GAMUT_TABLE_NUM; i++) {
for (j = 0; j < gamut_cfg->tbl_size[i]; j++)
- MDSS_MDP_REG_WRITE(offset,
- (u32)gamut_cfg->b_tbl[i][j]);
- offset += 4;
+ writel_relaxed((u32)gamut_cfg->b_tbl[i][j],
+ addr);
+ addr += 4;
}
if (gamut_cfg->gamut_first)
pp_sts->gamut_sts |= PP_STS_GAMUT_FIRST;
@@ -457,19 +513,19 @@
pp_sts->gamut_sts |= PP_STS_ENABLE;
}
-static void pp_pa_config(unsigned long flags, u32 base,
+static void pp_pa_config(unsigned long flags, char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_pa_cfg *pa_config)
{
if (flags & PP_FLAGS_DIRTY_PA) {
if (pa_config->flags & MDP_PP_OPS_WRITE) {
- MDSS_MDP_REG_WRITE(base, pa_config->hue_adj);
- base += 4;
- MDSS_MDP_REG_WRITE(base, pa_config->sat_adj);
- base += 4;
- MDSS_MDP_REG_WRITE(base, pa_config->val_adj);
- base += 4;
- MDSS_MDP_REG_WRITE(base, pa_config->cont_adj);
+ writel_relaxed(pa_config->hue_adj, addr);
+ addr += 4;
+ writel_relaxed(pa_config->sat_adj, addr);
+ addr += 4;
+ writel_relaxed(pa_config->val_adj, addr);
+ addr += 4;
+ writel_relaxed(pa_config->cont_adj, addr);
}
if (pa_config->flags & MDP_PP_OPS_DISABLE)
pp_sts->pa_sts &= ~PP_STS_ENABLE;
@@ -478,13 +534,160 @@
}
}
-static void pp_pcc_config(unsigned long flags, u32 base,
+static void pp_pa_v2_config(unsigned long flags, char __iomem *addr,
+ struct pp_sts_type *pp_sts,
+ struct mdp_pa_v2_data *pa_v2_config,
+ int mdp_location)
+{
+ if ((flags & PP_FLAGS_DIRTY_PA) &&
+ (pa_v2_config->flags & MDP_PP_OPS_WRITE)) {
+ pp_update_pa_v2_global_adj_regs(addr,
+ pa_v2_config);
+ /* Update PA DSPP Regs */
+ if (mdp_location == PP_DSPP) {
+ addr += 0x10;
+ pp_update_pa_v2_six_zone_regs(addr, pa_v2_config);
+ addr += 0xC;
+ pp_update_pa_v2_mem_col(addr, pa_v2_config);
+ } else if (mdp_location == PP_SSPP) { /* Update PA SSPP Regs */
+ addr -= MDSS_MDP_REG_VIG_PA_BASE;
+ addr += MDSS_MDP_REG_VIG_MEM_COL_BASE;
+ pp_update_pa_v2_mem_col(addr, pa_v2_config);
+ }
+ pp_update_pa_v2_sts(pp_sts, pa_v2_config);
+ }
+}
+
+static void pp_update_pa_v2_global_adj_regs(char __iomem *addr,
+ struct mdp_pa_v2_data *pa_v2_config)
+{
+ if (pa_v2_config->flags & MDP_PP_PA_HUE_ENABLE)
+ writel_relaxed(pa_v2_config->global_hue_adj, addr);
+ addr += 4;
+ if (pa_v2_config->flags & MDP_PP_PA_SAT_ENABLE)
+ /* Sat Global Adjust reg includes Sat Threshold */
+ writel_relaxed(pa_v2_config->global_sat_adj, addr);
+ addr += 4;
+ if (pa_v2_config->flags & MDP_PP_PA_VAL_ENABLE)
+ writel_relaxed(pa_v2_config->global_val_adj, addr);
+ addr += 4;
+ if (pa_v2_config->flags & MDP_PP_PA_CONT_ENABLE)
+ writel_relaxed(pa_v2_config->global_cont_adj, addr);
+}
+
+static void pp_update_pa_v2_mem_col(char __iomem *addr,
+ struct mdp_pa_v2_data *pa_v2_config)
+{
+ /* Update skin zone memory color registers */
+ if (pa_v2_config->flags & MDP_PP_PA_SKIN_ENABLE)
+ pp_update_pa_v2_mem_col_regs(addr, &pa_v2_config->skin_cfg);
+ addr += 0x14;
+ /* Update sky zone memory color registers */
+ if (pa_v2_config->flags & MDP_PP_PA_SKY_ENABLE)
+ pp_update_pa_v2_mem_col_regs(addr, &pa_v2_config->sky_cfg);
+ addr += 0x14;
+ /* Update foliage zone memory color registers */
+ if (pa_v2_config->flags & MDP_PP_PA_FOL_ENABLE)
+ pp_update_pa_v2_mem_col_regs(addr, &pa_v2_config->fol_cfg);
+}
+
+static void pp_update_pa_v2_mem_col_regs(char __iomem *addr,
+ struct mdp_pa_mem_col_cfg *cfg)
+{
+ pr_debug("ADDR: 0x%x, P0: 0x%x\n", (u32)addr, cfg->color_adjust_p0);
+ writel_relaxed(cfg->color_adjust_p0, addr);
+ addr += 4;
+ pr_debug("ADDR: 0x%x, P1: 0x%x\n", (u32)addr, cfg->color_adjust_p1);
+ writel_relaxed(cfg->color_adjust_p1, addr);
+ addr += 4;
+ pr_debug("ADDR: 0x%x, HUE REGION: 0x%x\n", (u32)addr, cfg->hue_region);
+ writel_relaxed(cfg->hue_region, addr);
+ addr += 4;
+ pr_debug("ADDR: 0x%x, SAT REGION: 0x%x\n", (u32)addr, cfg->sat_region);
+ writel_relaxed(cfg->sat_region, addr);
+ addr += 4;
+ pr_debug("ADDR: 0x%x, VAL REGION: 0x%x\n", (u32)addr, cfg->val_region);
+ writel_relaxed(cfg->val_region, addr);
+}
+
+static void pp_update_pa_v2_six_zone_regs(char __iomem *addr,
+ struct mdp_pa_v2_data *pa_v2_config)
+{
+ int i;
+ u32 data;
+ /* Update six zone memory color registers */
+ if (pa_v2_config->flags & MDP_PP_PA_SIX_ZONE_ENABLE) {
+ addr += 4;
+ writel_relaxed(pa_v2_config->six_zone_curve_p1[0], addr);
+ addr -= 4;
+ /* Index Update to trigger auto-incrementing LUT accesses */
+ data = (1 << 26);
+ writel_relaxed((pa_v2_config->six_zone_curve_p0[0] & 0xFFF) |
+ data, addr);
+
+ /* Remove Index Update */
+ for (i = 1; i < SIX_ZONE_LUT_ENTRIES; i++) {
+ addr += 4;
+ writel_relaxed(pa_v2_config->six_zone_curve_p1[i],
+ addr);
+ addr -= 4;
+ writel_relaxed(pa_v2_config->six_zone_curve_p0[i] &
+ 0xFFF, addr);
+ }
+ addr += 8;
+ writel_relaxed(pa_v2_config->six_zone_thresh, addr);
+ }
+}
+
+static void pp_update_pa_v2_sts(struct pp_sts_type *pp_sts,
+ struct mdp_pa_v2_data *pa_v2_config)
+{
+ pp_sts->pa_sts = 0;
+ /* PA STS update */
+ if (pa_v2_config->flags & MDP_PP_OPS_ENABLE)
+ pp_sts->pa_sts |= PP_STS_ENABLE;
+ else
+ pp_sts->pa_sts &= ~PP_STS_ENABLE;
+
+ /* Global HSV STS update */
+ if (pa_v2_config->flags & MDP_PP_PA_HUE_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_HUE_MASK;
+ if (pa_v2_config->flags & MDP_PP_PA_SAT_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_SAT_MASK;
+ if (pa_v2_config->flags & MDP_PP_PA_VAL_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_VAL_MASK;
+ if (pa_v2_config->flags & MDP_PP_PA_CONT_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_CONT_MASK;
+ if (pa_v2_config->flags & MDP_PP_PA_MEM_PROTECT_EN)
+ pp_sts->pa_sts |= PP_STS_PA_MEM_PROTECT_EN;
+ if (pa_v2_config->flags & MDP_PP_PA_SAT_ZERO_EXP_EN)
+ pp_sts->pa_sts |= PP_STS_PA_SAT_ZERO_EXP_EN;
+
+ /* Memory Color STS update */
+ if (pa_v2_config->flags & MDP_PP_PA_MEM_COL_SKIN_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_MEM_COL_SKIN_MASK;
+ if (pa_v2_config->flags & MDP_PP_PA_MEM_COL_SKY_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_MEM_COL_SKY_MASK;
+ if (pa_v2_config->flags & MDP_PP_PA_MEM_COL_FOL_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_MEM_COL_FOL_MASK;
+
+ /* Six Zone STS update */
+ if (pa_v2_config->flags & MDP_PP_PA_SIX_ZONE_HUE_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_SIX_ZONE_HUE_MASK;
+ if (pa_v2_config->flags & MDP_PP_PA_SIX_ZONE_SAT_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_SIX_ZONE_SAT_MASK;
+ if (pa_v2_config->flags & MDP_PP_PA_SIX_ZONE_VAL_MASK)
+ pp_sts->pa_sts |= PP_STS_PA_SIX_ZONE_VAL_MASK;
+
+}
+
+static void pp_pcc_config(unsigned long flags, char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_pcc_cfg_data *pcc_config)
{
if (flags & PP_FLAGS_DIRTY_PCC) {
if (pcc_config->ops & MDP_PP_OPS_WRITE)
- pp_update_pcc_regs(base, pcc_config);
+ pp_update_pcc_regs(addr, pcc_config);
if (pcc_config->ops & MDP_PP_OPS_DISABLE)
pp_sts->pcc_sts &= ~PP_STS_ENABLE;
@@ -493,7 +696,7 @@
}
}
-static void pp_igc_config(unsigned long flags, u32 base,
+static void pp_igc_config(unsigned long flags, char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_igc_lut_data *igc_config,
u32 pipe_num)
@@ -501,7 +704,7 @@
u32 tbl_idx;
if (flags & PP_FLAGS_DIRTY_IGC) {
if (igc_config->ops & MDP_PP_OPS_WRITE)
- pp_update_igc_lut(igc_config, base, pipe_num);
+ pp_update_igc_lut(igc_config, addr, pipe_num);
if (igc_config->ops & MDP_PP_IGC_FLAG_ROM0) {
pp_sts->pcc_sts |= PP_STS_ENABLE;
@@ -520,13 +723,13 @@
}
}
-static void pp_enhist_config(unsigned long flags, char __iomem *base,
+static void pp_enhist_config(unsigned long flags, char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_hist_lut_data *enhist_cfg)
{
if (flags & PP_FLAGS_DIRTY_ENHIST) {
if (enhist_cfg->ops & MDP_PP_OPS_WRITE)
- pp_update_hist_lut(base, enhist_cfg);
+ pp_update_hist_lut(addr, enhist_cfg);
if (enhist_cfg->ops & MDP_PP_OPS_DISABLE)
pp_sts->enhist_sts &= ~PP_STS_ENABLE;
@@ -536,18 +739,18 @@
}
/*the below function doesn't do error checking on the input params*/
-static void pp_sharp_config(char __iomem *base,
+static void pp_sharp_config(char __iomem *addr,
struct pp_sts_type *pp_sts,
struct mdp_sharp_cfg *sharp_config)
{
if (sharp_config->flags & MDP_PP_OPS_WRITE) {
- writel_relaxed(sharp_config->strength, base);
- base += 4;
- writel_relaxed(sharp_config->edge_thr, base);
- base += 4;
- writel_relaxed(sharp_config->smooth_thr, base);
- base += 4;
- writel_relaxed(sharp_config->noise_thr, base);
+ writel_relaxed(sharp_config->strength, addr);
+ addr += 4;
+ writel_relaxed(sharp_config->edge_thr, addr);
+ addr += 4;
+ writel_relaxed(sharp_config->smooth_thr, addr);
+ addr += 4;
+ writel_relaxed(sharp_config->noise_thr, addr);
}
if (sharp_config->flags & MDP_PP_OPS_DISABLE)
pp_sts->sharp_sts &= ~PP_STS_ENABLE;
@@ -558,12 +761,14 @@
static int pp_vig_pipe_setup(struct mdss_mdp_pipe *pipe, u32 *op)
{
- u32 opmode = 0, base = 0;
+ u32 opmode = 0;
unsigned long flags = 0;
char __iomem *offset;
+ struct mdss_data_type *mdata;
pr_debug("pnum=%x\n", pipe->num);
+ mdata = mdss_mdp_get_mdata();
if ((pipe->flags & MDP_OVERLAY_PP_CFG_EN) &&
(pipe->pp_cfg.config_ops & MDP_OVERLAY_PP_CSC_CFG)) {
opmode |= !!(pipe->pp_cfg.csc_cfg.flags &
@@ -597,15 +802,30 @@
pp_histogram_setup(&opmode, MDSS_PP_SSPP_CFG | pipe->num, pipe->mixer);
if (pipe->flags & MDP_OVERLAY_PP_CFG_EN) {
- if (pipe->pp_cfg.config_ops & MDP_OVERLAY_PP_PA_CFG) {
+ if ((pipe->pp_cfg.config_ops & MDP_OVERLAY_PP_PA_CFG) &&
+ (mdata->mdp_rev < MDSS_MDP_HW_REV_103)) {
flags = PP_FLAGS_DIRTY_PA;
- base = MDSS_MDP_REG_SSPP_OFFSET(pipe->num) +
- MDSS_MDP_REG_VIG_PA_BASE;
- pp_pa_config(flags, base, &pipe->pp_res.pp_sts,
- &pipe->pp_cfg.pa_cfg);
+ pp_pa_config(flags,
+ pipe->base + MDSS_MDP_REG_VIG_PA_BASE,
+ &pipe->pp_res.pp_sts,
+ &pipe->pp_cfg.pa_cfg);
if (pipe->pp_res.pp_sts.pa_sts & PP_STS_ENABLE)
- opmode |= (1 << 4); /* PA_EN */
+ opmode |= MDSS_MDP_VIG_OP_PA_EN;
+ }
+ if ((pipe->pp_cfg.config_ops & MDP_OVERLAY_PP_PA_V2_CFG) &&
+ (mdata->mdp_rev >= MDSS_MDP_HW_REV_103)) {
+ flags = PP_FLAGS_DIRTY_PA;
+ pp_pa_v2_config(flags,
+ pipe->base + MDSS_MDP_REG_VIG_PA_BASE,
+ &pipe->pp_res.pp_sts,
+ &pipe->pp_cfg.pa_v2_cfg,
+ PP_SSPP);
+ pp_update_pa_v2_vig_opmode(&pipe->pp_res.pp_sts,
+ &opmode);
+
+ if (pipe->pp_res.pp_sts.pa_sts & PP_STS_ENABLE)
+ opmode |= MDSS_MDP_VIG_OP_PA_EN;
}
if (pipe->pp_cfg.config_ops & MDP_OVERLAY_PP_HIST_LUT_CFG) {
@@ -634,6 +854,29 @@
return 0;
}
+static void pp_update_pa_v2_vig_opmode(struct pp_sts_type *pp_sts,
+ u32 *opmode)
+{
+ if (pp_sts->pa_sts & PP_STS_PA_HUE_MASK)
+ *opmode |= MDSS_MDP_VIG_OP_PA_HUE_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_SAT_MASK)
+ *opmode |= MDSS_MDP_VIG_OP_PA_SAT_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_VAL_MASK)
+ *opmode |= MDSS_MDP_VIG_OP_PA_VAL_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_CONT_MASK)
+ *opmode |= MDSS_MDP_VIG_OP_PA_CONT_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_MEM_PROTECT_EN)
+ *opmode |= MDSS_MDP_VIG_OP_PA_MEM_PROTECT_EN;
+ if (pp_sts->pa_sts & PP_STS_PA_SAT_ZERO_EXP_EN)
+ *opmode |= MDSS_MDP_VIG_OP_PA_SAT_ZERO_EXP_EN;
+ if (pp_sts->pa_sts & PP_STS_PA_MEM_COL_SKIN_MASK)
+ *opmode |= MDSS_MDP_VIG_OP_PA_MEM_COL_SKIN_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_MEM_COL_SKY_MASK)
+ *opmode |= MDSS_MDP_VIG_OP_PA_MEM_COL_SKY_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_MEM_COL_FOL_MASK)
+ *opmode |= MDSS_MDP_VIG_OP_PA_MEM_COL_FOL_MASK;
+}
+
static int mdss_mdp_scale_setup(struct mdss_mdp_pipe *pipe)
{
u32 scale_config = 0;
@@ -880,8 +1123,9 @@
{
int ret = 0;
unsigned long flags = 0;
- u32 pipe_base;
+ char __iomem *pipe_base;
u32 pipe_num;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
if (pipe == NULL)
return -EINVAL;
@@ -893,15 +1137,15 @@
*/
switch (pipe->type) {
case MDSS_MDP_PIPE_TYPE_VIG:
- pipe_base = MDSS_MDP_REG_IGC_VIG_BASE;
+ pipe_base = mdata->mdp_base + MDSS_MDP_REG_IGC_VIG_BASE;
pipe_num = pipe->num - MDSS_MDP_SSPP_VIG0;
break;
case MDSS_MDP_PIPE_TYPE_RGB:
- pipe_base = MDSS_MDP_REG_IGC_RGB_BASE;
+ pipe_base = mdata->mdp_base + MDSS_MDP_REG_IGC_RGB_BASE;
pipe_num = pipe->num - MDSS_MDP_SSPP_RGB0;
break;
case MDSS_MDP_PIPE_TYPE_DMA:
- pipe_base = MDSS_MDP_REG_IGC_DMA_BASE;
+ pipe_base = mdata->mdp_base + MDSS_MDP_REG_IGC_DMA_BASE;
pipe_num = pipe->num - MDSS_MDP_SSPP_DMA0;
break;
default:
@@ -923,10 +1167,11 @@
static int pp_mixer_setup(u32 disp_num,
struct mdss_mdp_mixer *mixer)
{
- u32 flags, offset, dspp_num, opmode = 0;
+ u32 flags, dspp_num, opmode = 0;
struct mdp_pgc_lut_data *pgc_config;
struct pp_sts_type *pp_sts;
struct mdss_mdp_ctl *ctl;
+ char __iomem *addr;
dspp_num = mixer->num;
if (!mixer || !mixer->ctl)
@@ -947,9 +1192,9 @@
if (flags & PP_FLAGS_DIRTY_ARGC) {
pgc_config = &mdss_pp_res->argc_disp_cfg[disp_num];
if (pgc_config->flags & MDP_PP_OPS_WRITE) {
- offset = MDSS_MDP_REG_LM_OFFSET(disp_num) +
+ addr = mixer->base +
MDSS_MDP_REG_LM_GC_LUT_BASE;
- pp_update_argc_lut(offset, pgc_config);
+ pp_update_argc_lut(addr, pgc_config);
}
if (pgc_config->flags & MDP_PP_OPS_DISABLE)
pp_sts->argc_sts &= ~PP_STS_ENABLE;
@@ -960,15 +1205,28 @@
/* update LM opmode if LM needs flush */
if ((pp_sts->argc_sts & PP_STS_ENABLE) &&
(ctl->flush_bits & (BIT(6) << dspp_num))) {
- offset = MDSS_MDP_REG_LM_OFFSET(dspp_num) +
- MDSS_MDP_REG_LM_OP_MODE;
- opmode = MDSS_MDP_REG_READ(offset);
+ addr = mixer->base + MDSS_MDP_REG_LM_OP_MODE;
+ opmode = readl_relaxed(addr);
opmode |= (1 << 0); /* GC_LUT_EN */
- MDSS_MDP_REG_WRITE(offset, opmode);
+ writel_relaxed(opmode, addr);
}
return 0;
}
+static char __iomem *mdss_mdp_get_mixer_addr_off(u32 dspp_num)
+{
+ struct mdss_data_type *mdata;
+ struct mdss_mdp_mixer *mixer;
+
+ mdata = mdss_mdp_get_mdata();
+ if (mdata->nmixers_intf <= dspp_num) {
+ pr_err("Invalid dspp_num=%d", dspp_num);
+ return ERR_PTR(-EINVAL);
+ }
+ mixer = mdata->mixer_intf + dspp_num;
+ return mixer->base;
+}
+
static char __iomem *mdss_mdp_get_dspp_addr_off(u32 dspp_num)
{
struct mdss_data_type *mdata;
@@ -1040,16 +1298,97 @@
return ret;
}
+static void pp_dither_config(char __iomem *addr,
+ struct pp_sts_type *pp_sts,
+ struct mdp_dither_cfg_data *dither_cfg)
+{
+ u32 data;
+ int i;
+
+ if (dither_cfg->flags & MDP_PP_OPS_WRITE) {
+ data = dither_depth_map[dither_cfg->g_y_depth];
+ data |= dither_depth_map[dither_cfg->b_cb_depth] << 2;
+ data |= dither_depth_map[dither_cfg->r_cr_depth] << 4;
+ writel_relaxed(data, addr);
+ addr += 0x14;
+ for (i = 0; i < 16; i += 4) {
+ data = dither_matrix[i] |
+ (dither_matrix[i + 1] << 4) |
+ (dither_matrix[i + 2] << 8) |
+ (dither_matrix[i + 3] << 12);
+ writel_relaxed(data, addr);
+ addr += 4;
+ }
+ }
+ if (dither_cfg->flags & MDP_PP_OPS_DISABLE)
+ pp_sts->dither_sts &= ~PP_STS_ENABLE;
+ else if (dither_cfg->flags & MDP_PP_OPS_ENABLE)
+ pp_sts->dither_sts |= PP_STS_ENABLE;
+}
+
+static void pp_dspp_opmode_config(struct pp_sts_type *pp_sts, u32 *opmode,
+ int mdp_rev)
+{
+ if (pp_sts->pa_sts & PP_STS_ENABLE)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_EN; /* PA_EN */
+ if (mdp_rev >= MDSS_MDP_HW_REV_103) {
+ if (pp_sts->pa_sts & PP_STS_PA_HUE_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_HUE_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_SAT_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_SAT_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_VAL_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_VAL_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_CONT_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_CONT_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_MEM_PROTECT_EN)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_MEM_PROTECT_EN;
+ if (pp_sts->pa_sts & PP_STS_PA_SAT_ZERO_EXP_EN)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_SAT_ZERO_EXP_EN;
+ if (pp_sts->pa_sts & PP_STS_PA_MEM_COL_SKIN_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_MEM_COL_SKIN_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_MEM_COL_FOL_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_MEM_COL_FOL_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_MEM_COL_SKY_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_MEM_COL_SKY_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_SIX_ZONE_HUE_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_SIX_ZONE_HUE_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_SIX_ZONE_SAT_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_SIX_ZONE_SAT_MASK;
+ if (pp_sts->pa_sts & PP_STS_PA_SIX_ZONE_VAL_MASK)
+ *opmode |= MDSS_MDP_DSPP_OP_PA_SIX_ZONE_VAL_MASK;
+ }
+ if (pp_sts->pcc_sts & PP_STS_ENABLE)
+ *opmode |= MDSS_MDP_DSPP_OP_PCC_EN; /* PCC_EN */
+
+ if (pp_sts->igc_sts & PP_STS_ENABLE) {
+ *opmode |= MDSS_MDP_DSPP_OP_IGC_LUT_EN | /* IGC_LUT_EN */
+ (pp_sts->igc_tbl_idx << 1);
+ }
+ if (pp_sts->enhist_sts & PP_STS_ENABLE) {
+ *opmode |= MDSS_MDP_DSPP_OP_HIST_LUTV_EN | /* HIST_LUT_EN */
+ MDSS_MDP_DSPP_OP_PA_EN; /* PA_EN */
+ }
+ if (pp_sts->dither_sts & PP_STS_ENABLE)
+ *opmode |= MDSS_MDP_DSPP_OP_DST_DITHER_EN; /* DITHER_EN */
+ if (pp_sts->gamut_sts & PP_STS_ENABLE) {
+ *opmode |= MDSS_MDP_DSPP_OP_GAMUT_EN; /* GAMUT_EN */
+ if (pp_sts->gamut_sts & PP_STS_GAMUT_FIRST)
+ *opmode |= MDSS_MDP_DSPP_OP_GAMUT_PCC_ORDER;
+ }
+ if (pp_sts->pgc_sts & PP_STS_ENABLE)
+ *opmode |= MDSS_MDP_DSPP_OP_ARGC_LUT_EN;
+}
+
static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
{
- u32 flags, base, offset, dspp_num, opmode = 0;
- struct mdp_dither_cfg_data *dither_cfg;
+ u32 ad_flags, flags, dspp_num, opmode = 0, ad_bypass;
struct mdp_pgc_lut_data *pgc_config;
struct pp_sts_type *pp_sts;
- u32 data;
- char __iomem *basel;
- int i, ret = 0;
+ char __iomem *base, *addr;
+ int ret = 0;
struct mdss_data_type *mdata;
+ struct mdss_ad_info *ad = NULL;
+ struct mdss_mdp_ad *ad_hw = NULL;
struct mdss_mdp_ctl *ctl;
u32 mixer_cnt;
u32 mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];
@@ -1063,8 +1402,7 @@
if ((mixer->type != MDSS_MDP_MIXER_TYPE_INTF) ||
(dspp_num >= MDSS_MDP_MAX_DSPP))
return -EINVAL;
- base = MDSS_MDP_REG_DSPP_OFFSET(dspp_num);
- basel = mdss_mdp_get_dspp_addr_off(dspp_num);
+ base = mdss_mdp_get_dspp_addr_off(dspp_num);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
@@ -1078,107 +1416,90 @@
flags = 0;
mixer_cnt = mdss_mdp_get_ctl_mixers(disp_num, mixer_id);
- if (dspp_num < mdata->nad_cfgs && (mixer_cnt != 2)) {
- ret = mdss_mdp_ad_setup(ctl->mfd);
- if (ret < 0)
- pr_warn("ad_setup(dspp%d) returns %d", dspp_num, ret);
+ if (dspp_num < mdata->nad_cfgs && disp_num < mdata->nad_cfgs &&
+ (mixer_cnt <= mdata->nmax_concurrent_ad_hw)) {
+ ad = &mdata->ad_cfgs[disp_num];
+ ad_flags = ad->reg_sts;
+ ad_hw = &mdata->ad_off[dspp_num];
+ } else {
+ ad_flags = 0;
}
+
/* call calibration specific processing here */
if (ctl->mfd->calib_mode)
goto flush_exit;
/* nothing to update */
- if ((!flags) && (!(opmode)) && (ret <= 0))
+ if ((!flags) && (!(opmode)) && (!ad_flags))
goto dspp_exit;
- ret = 0;
pp_sts = &mdss_pp_res->pp_disp_sts[disp_num];
- pp_pa_config(flags, base + MDSS_MDP_REG_DSPP_PA_BASE, pp_sts,
- &mdss_pp_res->pa_disp_cfg[disp_num]);
+ if (mdata->mdp_rev >= MDSS_MDP_HW_REV_103) {
+ pp_pa_v2_config(flags, base + MDSS_MDP_REG_DSPP_PA_BASE, pp_sts,
+ &mdss_pp_res->pa_v2_disp_cfg[disp_num],
+ PP_DSPP);
+ } else
+ pp_pa_config(flags, base + MDSS_MDP_REG_DSPP_PA_BASE, pp_sts,
+ &mdss_pp_res->pa_disp_cfg[disp_num]);
pp_pcc_config(flags, base + MDSS_MDP_REG_DSPP_PCC_BASE, pp_sts,
&mdss_pp_res->pcc_disp_cfg[disp_num]);
- pp_igc_config(flags, MDSS_MDP_REG_IGC_DSPP_BASE, pp_sts,
- &mdss_pp_res->igc_disp_cfg[disp_num], dspp_num);
+ pp_igc_config(flags, mdata->mdp_base + MDSS_MDP_REG_IGC_DSPP_BASE,
+ pp_sts, &mdss_pp_res->igc_disp_cfg[disp_num],
+ dspp_num);
- pp_enhist_config(flags, basel + MDSS_MDP_REG_DSPP_HIST_LUT_BASE,
+ pp_enhist_config(flags, base + MDSS_MDP_REG_DSPP_HIST_LUT_BASE,
pp_sts, &mdss_pp_res->enhist_disp_cfg[disp_num]);
- if (pp_sts->pa_sts & PP_STS_ENABLE)
- opmode |= (1 << 20); /* PA_EN */
-
- if (pp_sts->pcc_sts & PP_STS_ENABLE)
- opmode |= (1 << 4); /* PCC_EN */
-
- if (pp_sts->igc_sts & PP_STS_ENABLE) {
- opmode |= (1 << 0) | /* IGC_LUT_EN */
- (pp_sts->igc_tbl_idx << 1);
- }
-
- if (pp_sts->enhist_sts & PP_STS_ENABLE) {
- opmode |= (1 << 19) | /* HIST_LUT_EN */
- (1 << 20); /* PA_EN */
- if (!(pp_sts->pa_sts & PP_STS_ENABLE)) {
- /* Program default value */
- offset = base + MDSS_MDP_REG_DSPP_PA_BASE;
- MDSS_MDP_REG_WRITE(offset, 0);
- MDSS_MDP_REG_WRITE(offset + 4, 0);
- MDSS_MDP_REG_WRITE(offset + 8, 0);
- MDSS_MDP_REG_WRITE(offset + 12, 0);
- }
+ if (pp_sts->enhist_sts & PP_STS_ENABLE &&
+ !(pp_sts->pa_sts & PP_STS_ENABLE)) {
+ /* Program default value */
+ addr = base + MDSS_MDP_REG_DSPP_PA_BASE;
+ writel_relaxed(0, addr);
+ writel_relaxed(0, addr + 4);
+ writel_relaxed(0, addr + 8);
+ writel_relaxed(0, addr + 12);
}
if (flags & PP_FLAGS_DIRTY_DITHER) {
- dither_cfg = &mdss_pp_res->dither_disp_cfg[disp_num];
- if (dither_cfg->flags & MDP_PP_OPS_WRITE) {
- offset = base + MDSS_MDP_REG_DSPP_DITHER_DEPTH;
- MDSS_MDP_REG_WRITE(offset,
- dither_depth_map[dither_cfg->g_y_depth] |
- (dither_depth_map[dither_cfg->b_cb_depth] << 2) |
- (dither_depth_map[dither_cfg->r_cr_depth] << 4));
- offset += 0x14;
- for (i = 0; i << 16; i += 4) {
- data = dither_matrix[i] |
- (dither_matrix[i + 1] << 4) |
- (dither_matrix[i + 2] << 8) |
- (dither_matrix[i + 3] << 12);
- MDSS_MDP_REG_WRITE(offset, data);
- offset += 4;
- }
- }
- if (dither_cfg->flags & MDP_PP_OPS_DISABLE)
- pp_sts->dither_sts &= ~PP_STS_ENABLE;
- else if (dither_cfg->flags & MDP_PP_OPS_ENABLE)
- pp_sts->dither_sts |= PP_STS_ENABLE;
+ addr = base + MDSS_MDP_REG_DSPP_DITHER_DEPTH;
+ pp_dither_config(addr, pp_sts,
+ &mdss_pp_res->dither_disp_cfg[disp_num]);
}
- if (pp_sts->dither_sts & PP_STS_ENABLE)
- opmode |= (1 << 8); /* DITHER_EN */
if (flags & PP_FLAGS_DIRTY_GAMUT)
pp_gamut_config(&mdss_pp_res->gamut_disp_cfg[disp_num], base,
pp_sts);
- if (pp_sts->gamut_sts & PP_STS_ENABLE) {
- opmode |= (1 << 23); /* GAMUT_EN */
- if (pp_sts->gamut_sts & PP_STS_GAMUT_FIRST)
- opmode |= (1 << 24); /* GAMUT_ORDER */
- }
if (flags & PP_FLAGS_DIRTY_PGC) {
pgc_config = &mdss_pp_res->pgc_disp_cfg[disp_num];
if (pgc_config->flags & MDP_PP_OPS_WRITE) {
- offset = base + MDSS_MDP_REG_DSPP_GC_BASE;
- pp_update_argc_lut(offset, pgc_config);
+ addr = base + MDSS_MDP_REG_DSPP_GC_BASE;
+ pp_update_argc_lut(addr, pgc_config);
}
if (pgc_config->flags & MDP_PP_OPS_DISABLE)
pp_sts->pgc_sts &= ~PP_STS_ENABLE;
else if (pgc_config->flags & MDP_PP_OPS_ENABLE)
pp_sts->pgc_sts |= PP_STS_ENABLE;
}
- if (pp_sts->pgc_sts & PP_STS_ENABLE)
- opmode |= (1 << 22);
+ if (ad_hw) {
+ mutex_lock(&ad->lock);
+ ad_flags = ad->reg_sts;
+ if (ad_flags & PP_AD_STS_DIRTY_DATA)
+ pp_ad_input_write(ad_hw, ad);
+ if (ad_flags & PP_AD_STS_DIRTY_INIT)
+ pp_ad_init_write(ad_hw, ad, ctl);
+ if (ad_flags & PP_AD_STS_DIRTY_CFG)
+ pp_ad_cfg_write(ad_hw, ad);
+ pp_ad_bypass_config(ad, &ad_bypass);
+ writel_relaxed(ad_bypass, ad_hw->base);
+ mutex_unlock(&ad->lock);
+ }
+
+ pp_dspp_opmode_config(pp_sts, &opmode, mdata->mdp_rev);
flush_exit:
- writel_relaxed(opmode, basel + MDSS_MDP_REG_DSPP_OP_MODE);
+ writel_relaxed(opmode, base + MDSS_MDP_REG_DSPP_OP_MODE);
ctl->flush_bits |= BIT(13 + dspp_num);
wmb();
dspp_exit:
@@ -1209,13 +1530,39 @@
/* call only when holding and mfd->lock */
int mdss_mdp_pp_setup_locked(struct mdss_mdp_ctl *ctl)
{
+ struct mdss_data_type *mdata = ctl->mdata;
+ int ret = 0;
+ u32 mixer_cnt;
+ u32 mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];
u32 disp_num;
+ int i;
+ bool valid_mixers = true;
if ((!ctl->mfd) || (!mdss_pp_res))
return -EINVAL;
/* treat fb_num the same as block logical id*/
disp_num = ctl->mfd->index;
+ mixer_cnt = mdss_mdp_get_ctl_mixers(disp_num, mixer_id);
+ if (!mixer_cnt) {
+ valid_mixers = false;
+ ret = -EINVAL;
+ pr_warn("Configuring post processing without mixers, err = %d",
+ ret);
+ goto exit;
+ }
+ if (mdata->nad_cfgs == 0)
+ valid_mixers = false;
+ for (i = 0; i < mixer_cnt && valid_mixers; i++) {
+ if (mixer_id[i] > mdata->nad_cfgs)
+ valid_mixers = false;
+ }
+ if (valid_mixers && (mixer_cnt <= mdata->nmax_concurrent_ad_hw)) {
+ ret = mdss_mdp_ad_setup(ctl->mfd);
+ if (ret < 0)
+ pr_warn("ad_setup(disp%d) returns %d", disp_num, ret);
+ }
+
mutex_lock(&mdss_pp_mutex);
if (ctl->mixer_left) {
pp_mixer_setup(disp_num, ctl->mixer_left);
@@ -1226,11 +1573,14 @@
pp_dspp_setup(disp_num, ctl->mixer_right);
}
/* clear dirty flag */
- if (disp_num < MDSS_BLOCK_DISP_NUM)
+ if (disp_num < MDSS_BLOCK_DISP_NUM) {
mdss_pp_res->pp_disp_flags[disp_num] = 0;
+ if (disp_num < mdata->nad_cfgs)
+ mdata->ad_cfgs[disp_num].reg_sts = 0;
+ }
mutex_unlock(&mdss_pp_mutex);
-
- return 0;
+exit:
+ return ret;
}
/*
@@ -1253,17 +1603,19 @@
ad = &mdata->ad_cfgs[dspp_num];
if (PP_AD_STATE_CFG & ad->state)
- pp_ad_cfg_write(ad);
+ pp_ad_cfg_write(&mdata->ad_off[dspp_num], ad);
if (PP_AD_STATE_INIT & ad->state)
- pp_ad_init_write(ad);
- if ((PP_AD_STATE_DATA & ad->state) && (ad->sts & PP_STS_ENABLE)) {
+ pp_ad_init_write(&mdata->ad_off[dspp_num], ad, ctl);
+ if ((PP_AD_STATE_DATA & ad->state) &&
+ (ad->sts & PP_STS_ENABLE)) {
bl = ad->bl_mfd->bl_level;
ad->last_bl = bl;
if (ad->state & PP_AD_STATE_BL_LIN) {
bl = ad->bl_lin[bl >> ad->bl_bright_shift];
bl = bl << ad->bl_bright_shift;
}
- pp_ad_input_write(ad, bl);
+ ad->bl_data = bl;
+ pp_ad_input_write(&mdata->ad_off[dspp_num], ad);
}
if ((PP_AD_STATE_VSYNC & ad->state) && ad->calc_itr)
ctl->add_vsync_handler(ctl, &ad->handle);
@@ -1273,10 +1625,17 @@
if (pp_sts.pa_sts & PP_STS_ENABLE) {
flags |= PP_FLAGS_DIRTY_PA;
- if (!(mdss_pp_res->pa_disp_cfg[disp_num].flags
- & MDP_PP_OPS_DISABLE))
- mdss_pp_res->pa_disp_cfg[disp_num].flags |=
- MDP_PP_OPS_WRITE;
+ if (mdata->mdp_rev >= MDSS_MDP_HW_REV_103) {
+ if (!(mdss_pp_res->pa_v2_disp_cfg[disp_num].flags
+ & MDP_PP_OPS_DISABLE))
+ mdss_pp_res->pa_v2_disp_cfg[disp_num].flags |=
+ MDP_PP_OPS_WRITE;
+ } else {
+ if (!(mdss_pp_res->pa_disp_cfg[disp_num].flags
+ & MDP_PP_OPS_DISABLE))
+ mdss_pp_res->pa_disp_cfg[disp_num].flags |=
+ MDP_PP_OPS_WRITE;
+ }
}
if (pp_sts.pcc_sts & PP_STS_ENABLE) {
flags |= PP_FLAGS_DIRTY_PCC;
@@ -1419,10 +1778,15 @@
u32 *copyback)
{
int ret = 0;
- u32 pa_offset, disp_num, dspp_num = 0;
+ u32 disp_num, dspp_num = 0;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
+ char __iomem *pa_addr;
+
+ if (mdata->mdp_rev >= MDSS_MDP_HW_REV_103)
+ return -EINVAL;
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
- (config->block >= MDP_BLOCK_MAX))
+ (config->block >= MDP_BLOCK_MAX))
return -EINVAL;
mutex_lock(&mdss_pp_mutex);
@@ -1431,20 +1795,20 @@
if (config->pa_data.flags & MDP_PP_OPS_READ) {
ret = pp_get_dspp_num(disp_num, &dspp_num);
if (ret) {
- pr_err("%s, no dspp connects to disp %d",
- __func__, disp_num);
+ pr_err("no dspp connects to disp %d",
+ disp_num);
goto pa_config_exit;
}
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- pa_offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
- MDSS_MDP_REG_DSPP_PA_BASE;
- config->pa_data.hue_adj = MDSS_MDP_REG_READ(pa_offset);
- pa_offset += 4;
- config->pa_data.sat_adj = MDSS_MDP_REG_READ(pa_offset);
- pa_offset += 4;
- config->pa_data.val_adj = MDSS_MDP_REG_READ(pa_offset);
- pa_offset += 4;
- config->pa_data.cont_adj = MDSS_MDP_REG_READ(pa_offset);
+ pa_addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
+ MDSS_MDP_REG_DSPP_PA_BASE;
+ config->pa_data.hue_adj = readl_relaxed(pa_addr);
+ pa_addr += 4;
+ config->pa_data.sat_adj = readl_relaxed(pa_addr);
+ pa_addr += 4;
+ config->pa_data.val_adj = readl_relaxed(pa_addr);
+ pa_addr += 4;
+ config->pa_data.cont_adj = readl_relaxed(pa_addr);
*copyback = 1;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
} else {
@@ -1457,137 +1821,299 @@
return ret;
}
-static void pp_read_pcc_regs(u32 offset,
- struct mdp_pcc_cfg_data *cfg_ptr)
+int mdss_mdp_pa_v2_config(struct mdp_pa_v2_cfg_data *config,
+ u32 *copyback)
{
- cfg_ptr->r.c = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.c = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.c = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
+ int ret = 0;
+ u32 disp_num, dspp_num = 0;
+ char __iomem *pa_addr;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
- cfg_ptr->r.r = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.r = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.r = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
+ if (mdata->mdp_rev < MDSS_MDP_HW_REV_103)
+ return -EINVAL;
- cfg_ptr->r.g = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.g = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.g = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
+ if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
+ (config->block >= MDP_BLOCK_MAX))
+ return -EINVAL;
- cfg_ptr->r.b = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.b = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.b = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
+ mutex_lock(&mdss_pp_mutex);
+ disp_num = config->block - MDP_LOGICAL_BLOCK_DISP_0;
- cfg_ptr->r.rr = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.rr = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.rr = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
+ if (config->pa_v2_data.flags & MDP_PP_OPS_READ) {
+ ret = pp_get_dspp_num(disp_num, &dspp_num);
+ if (ret) {
+ pr_err("no dspp connects to disp %d",
+ disp_num);
+ goto pa_config_exit;
+ }
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+ pa_addr = mdss_mdp_get_dspp_addr_off(dspp_num);
+ if (IS_ERR(pa_addr)) {
+ ret = PTR_ERR(pa_addr);
+ goto pa_config_exit;
+ } else
+ pa_addr += MDSS_MDP_REG_DSPP_PA_BASE;
+ ret = pp_read_pa_v2_regs(pa_addr,
+ &config->pa_v2_data,
+ disp_num);
+ if (ret)
+ goto pa_config_exit;
+ *copyback = 1;
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
+ } else {
+ if (config->pa_v2_data.flags & MDP_PP_PA_SIX_ZONE_ENABLE) {
+ ret = pp_copy_pa_six_zone_lut(config, disp_num);
+ if (ret)
+ goto pa_config_exit;
+ }
+ mdss_pp_res->pa_v2_disp_cfg[disp_num] =
+ config->pa_v2_data;
+ mdss_pp_res->pa_v2_disp_cfg[disp_num].six_zone_curve_p0 =
+ &mdss_pp_res->six_zone_lut_curve_p0[disp_num][0];
+ mdss_pp_res->pa_v2_disp_cfg[disp_num].six_zone_curve_p1 =
+ &mdss_pp_res->six_zone_lut_curve_p1[disp_num][0];
+ mdss_pp_res->pp_disp_flags[disp_num] |= PP_FLAGS_DIRTY_PA;
+ }
- cfg_ptr->r.rg = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.rg = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.rg = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
-
- cfg_ptr->r.rb = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.rb = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.rb = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
-
- cfg_ptr->r.gg = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.gg = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.gg = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
-
- cfg_ptr->r.gb = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.gb = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.gb = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
-
- cfg_ptr->r.bb = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.bb = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.bb = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
-
- cfg_ptr->r.rgb_0 = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.rgb_0 = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.rgb_0 = MDSS_MDP_REG_READ(offset + 8);
- offset += 0x10;
-
- cfg_ptr->r.rgb_1 = MDSS_MDP_REG_READ(offset);
- cfg_ptr->g.rgb_1 = MDSS_MDP_REG_READ(offset + 4);
- cfg_ptr->b.rgb_1 = MDSS_MDP_REG_READ(offset + 8);
+pa_config_exit:
+ mutex_unlock(&mdss_pp_mutex);
+ return ret;
}
-static void pp_update_pcc_regs(u32 offset,
+
+static int pp_read_pa_v2_regs(char __iomem *addr,
+ struct mdp_pa_v2_data *pa_v2_config,
+ u32 disp_num)
+{
+ int i;
+ u32 data;
+
+ if (pa_v2_config->flags & MDP_PP_PA_HUE_ENABLE)
+ pa_v2_config->global_hue_adj = readl_relaxed(addr);
+ addr += 4;
+ if (pa_v2_config->flags & MDP_PP_PA_SAT_ENABLE)
+ pa_v2_config->global_sat_adj = readl_relaxed(addr);
+ addr += 4;
+ if (pa_v2_config->flags & MDP_PP_PA_VAL_ENABLE)
+ pa_v2_config->global_val_adj = readl_relaxed(addr);
+ addr += 4;
+ if (pa_v2_config->flags & MDP_PP_PA_CONT_ENABLE)
+ pa_v2_config->global_cont_adj = readl_relaxed(addr);
+ addr += 4;
+
+ /* Six zone LUT and thresh data */
+ if (pa_v2_config->flags & MDP_PP_PA_SIX_ZONE_ENABLE) {
+ data = (3 << 25);
+ writel_relaxed(data, addr);
+
+ for (i = 0; i < SIX_ZONE_LUT_ENTRIES; i++) {
+ addr += 4;
+ mdss_pp_res->six_zone_lut_curve_p1[disp_num][i] =
+ readl_relaxed(addr);
+ addr -= 4;
+ mdss_pp_res->six_zone_lut_curve_p0[disp_num][i] =
+ readl_relaxed(addr) & 0xFFF;
+ }
+
+ if (copy_to_user(pa_v2_config->six_zone_curve_p0,
+ &mdss_pp_res->six_zone_lut_curve_p0[disp_num][0],
+ SIX_ZONE_LUT_ENTRIES * sizeof(u32))) {
+ return -EFAULT;
+ }
+
+ if (copy_to_user(pa_v2_config->six_zone_curve_p1,
+ &mdss_pp_res->six_zone_lut_curve_p1[disp_num][0],
+ SIX_ZONE_LUT_ENTRIES * sizeof(u32))) {
+ return -EFAULT;
+ }
+
+ addr += 8;
+ pa_v2_config->six_zone_thresh = readl_relaxed(addr);
+ addr += 4;
+ } else {
+ addr += 12;
+ }
+
+ /* Skin memory color config registers */
+ if (pa_v2_config->flags & MDP_PP_PA_SKIN_ENABLE)
+ pp_read_pa_mem_col_regs(addr, &pa_v2_config->skin_cfg);
+
+ addr += 0x14;
+ /* Sky memory color config registers */
+ if (pa_v2_config->flags & MDP_PP_PA_SKY_ENABLE)
+ pp_read_pa_mem_col_regs(addr, &pa_v2_config->sky_cfg);
+
+ addr += 0x14;
+ /* Foliage memory color config registers */
+ if (pa_v2_config->flags & MDP_PP_PA_FOL_ENABLE)
+ pp_read_pa_mem_col_regs(addr, &pa_v2_config->fol_cfg);
+
+ return 0;
+}
+
+static void pp_read_pa_mem_col_regs(char __iomem *addr,
+ struct mdp_pa_mem_col_cfg *mem_col_cfg)
+{
+ mem_col_cfg->color_adjust_p0 = readl_relaxed(addr);
+ addr += 4;
+ mem_col_cfg->color_adjust_p1 = readl_relaxed(addr);
+ addr += 4;
+ mem_col_cfg->hue_region = readl_relaxed(addr);
+ addr += 4;
+ mem_col_cfg->sat_region = readl_relaxed(addr);
+ addr += 4;
+ mem_col_cfg->val_region = readl_relaxed(addr);
+}
+
+static int pp_copy_pa_six_zone_lut(struct mdp_pa_v2_cfg_data *pa_v2_config,
+ u32 disp_num)
+{
+ if (copy_from_user(&mdss_pp_res->six_zone_lut_curve_p0[disp_num][0],
+ pa_v2_config->pa_v2_data.six_zone_curve_p0,
+ SIX_ZONE_LUT_ENTRIES * sizeof(u32))) {
+ return -EFAULT;
+ }
+ if (copy_from_user(&mdss_pp_res->six_zone_lut_curve_p1[disp_num][0],
+ pa_v2_config->pa_v2_data.six_zone_curve_p1,
+ SIX_ZONE_LUT_ENTRIES * sizeof(u32))) {
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static void pp_read_pcc_regs(char __iomem *addr,
struct mdp_pcc_cfg_data *cfg_ptr)
{
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.c);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.c);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.c);
- offset += 0x10;
+ cfg_ptr->r.c = readl_relaxed(addr);
+ cfg_ptr->g.c = readl_relaxed(addr + 4);
+ cfg_ptr->b.c = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.r);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.r);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.r);
- offset += 0x10;
+ cfg_ptr->r.r = readl_relaxed(addr);
+ cfg_ptr->g.r = readl_relaxed(addr + 4);
+ cfg_ptr->b.r = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.g);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.g);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.g);
- offset += 0x10;
+ cfg_ptr->r.g = readl_relaxed(addr);
+ cfg_ptr->g.g = readl_relaxed(addr + 4);
+ cfg_ptr->b.g = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.b);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.b);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.b);
- offset += 0x10;
+ cfg_ptr->r.b = readl_relaxed(addr);
+ cfg_ptr->g.b = readl_relaxed(addr + 4);
+ cfg_ptr->b.b = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rr);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rr);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rr);
- offset += 0x10;
+ cfg_ptr->r.rr = readl_relaxed(addr);
+ cfg_ptr->g.rr = readl_relaxed(addr + 4);
+ cfg_ptr->b.rr = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rg);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rg);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rg);
- offset += 0x10;
+ cfg_ptr->r.rg = readl_relaxed(addr);
+ cfg_ptr->g.rg = readl_relaxed(addr + 4);
+ cfg_ptr->b.rg = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rb);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rb);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rb);
- offset += 0x10;
+ cfg_ptr->r.rb = readl_relaxed(addr);
+ cfg_ptr->g.rb = readl_relaxed(addr + 4);
+ cfg_ptr->b.rb = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.gg);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.gg);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.gg);
- offset += 0x10;
+ cfg_ptr->r.gg = readl_relaxed(addr);
+ cfg_ptr->g.gg = readl_relaxed(addr + 4);
+ cfg_ptr->b.gg = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.gb);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.gb);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.gb);
- offset += 0x10;
+ cfg_ptr->r.gb = readl_relaxed(addr);
+ cfg_ptr->g.gb = readl_relaxed(addr + 4);
+ cfg_ptr->b.gb = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.bb);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.bb);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.bb);
- offset += 0x10;
+ cfg_ptr->r.bb = readl_relaxed(addr);
+ cfg_ptr->g.bb = readl_relaxed(addr + 4);
+ cfg_ptr->b.bb = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rgb_0);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rgb_0);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rgb_0);
- offset += 0x10;
+ cfg_ptr->r.rgb_0 = readl_relaxed(addr);
+ cfg_ptr->g.rgb_0 = readl_relaxed(addr + 4);
+ cfg_ptr->b.rgb_0 = readl_relaxed(addr + 8);
+ addr += 0x10;
- MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rgb_1);
- MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rgb_1);
- MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rgb_1);
+ cfg_ptr->r.rgb_1 = readl_relaxed(addr);
+ cfg_ptr->g.rgb_1 = readl_relaxed(addr + 4);
+ cfg_ptr->b.rgb_1 = readl_relaxed(addr + 8);
+}
+
+static void pp_update_pcc_regs(char __iomem *addr,
+ struct mdp_pcc_cfg_data *cfg_ptr)
+{
+ writel_relaxed(cfg_ptr->r.c, addr);
+ writel_relaxed(cfg_ptr->g.c, addr + 4);
+ writel_relaxed(cfg_ptr->b.c, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.r, addr);
+ writel_relaxed(cfg_ptr->g.r, addr + 4);
+ writel_relaxed(cfg_ptr->b.r, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.g, addr);
+ writel_relaxed(cfg_ptr->g.g, addr + 4);
+ writel_relaxed(cfg_ptr->b.g, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.b, addr);
+ writel_relaxed(cfg_ptr->g.b, addr + 4);
+ writel_relaxed(cfg_ptr->b.b, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.rr, addr);
+ writel_relaxed(cfg_ptr->g.rr, addr + 4);
+ writel_relaxed(cfg_ptr->b.rr, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.rg, addr);
+ writel_relaxed(cfg_ptr->g.rg, addr + 4);
+ writel_relaxed(cfg_ptr->b.rg, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.rb, addr);
+ writel_relaxed(cfg_ptr->g.rb, addr + 4);
+ writel_relaxed(cfg_ptr->b.rb, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.gg, addr);
+ writel_relaxed(cfg_ptr->g.gg, addr + 4);
+ writel_relaxed(cfg_ptr->b.gg, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.gb, addr);
+ writel_relaxed(cfg_ptr->g.gb, addr + 4);
+ writel_relaxed(cfg_ptr->b.gb, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.bb, addr);
+ writel_relaxed(cfg_ptr->g.bb, addr + 4);
+ writel_relaxed(cfg_ptr->b.bb, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.rgb_0, addr);
+ writel_relaxed(cfg_ptr->g.rgb_0, addr + 4);
+ writel_relaxed(cfg_ptr->b.rgb_0, addr + 8);
+ addr += 0x10;
+
+ writel_relaxed(cfg_ptr->r.rgb_1, addr);
+ writel_relaxed(cfg_ptr->g.rgb_1, addr + 4);
+ writel_relaxed(cfg_ptr->b.rgb_1, addr + 8);
}
int mdss_mdp_pcc_config(struct mdp_pcc_cfg_data *config,
u32 *copyback)
{
int ret = 0;
- u32 base, disp_num, dspp_num = 0;
+ u32 disp_num, dspp_num = 0;
+ char __iomem *addr;
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
@@ -1606,9 +2132,9 @@
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- base = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
+ addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
MDSS_MDP_REG_DSPP_PCC_BASE;
- pp_read_pcc_regs(base, config);
+ pp_read_pcc_regs(addr, config);
*copyback = 1;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
} else {
@@ -1622,57 +2148,57 @@
}
static void pp_read_igc_lut(struct mdp_igc_lut_data *cfg,
- u32 offset, u32 blk_idx)
+ char __iomem *addr, u32 blk_idx)
{
int i;
u32 data;
/* INDEX_UPDATE & VALUE_UPDATEN */
data = (3 << 24) | (((~(1 << blk_idx)) & 0x7) << 28);
- MDSS_MDP_REG_WRITE(offset, data);
+ writel_relaxed(data, addr);
for (i = 0; i < cfg->len; i++)
- cfg->c0_c1_data[i] = MDSS_MDP_REG_READ(offset) & 0xFFF;
+ cfg->c0_c1_data[i] = readl_relaxed(addr) & 0xFFF;
- offset += 0x4;
- MDSS_MDP_REG_WRITE(offset, data);
+ addr += 0x4;
+ writel_relaxed(data, addr);
for (i = 0; i < cfg->len; i++)
- cfg->c0_c1_data[i] |= (MDSS_MDP_REG_READ(offset) & 0xFFF) << 16;
+ cfg->c0_c1_data[i] |= (readl_relaxed(addr) & 0xFFF) << 16;
- offset += 0x4;
- MDSS_MDP_REG_WRITE(offset, data);
+ addr += 0x4;
+ writel_relaxed(data, addr);
for (i = 0; i < cfg->len; i++)
- cfg->c2_data[i] = MDSS_MDP_REG_READ(offset) & 0xFFF;
+ cfg->c2_data[i] = readl_relaxed(addr) & 0xFFF;
}
static void pp_update_igc_lut(struct mdp_igc_lut_data *cfg,
- u32 offset, u32 blk_idx)
+ char __iomem *addr, u32 blk_idx)
{
int i;
u32 data;
/* INDEX_UPDATE */
data = (1 << 25) | (((~(1 << blk_idx)) & 0x7) << 28);
- MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
+ writel_relaxed((cfg->c0_c1_data[0] & 0xFFF) | data, addr);
/* disable index update */
data &= ~(1 << 25);
for (i = 1; i < cfg->len; i++)
- MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[i] & 0xFFF) | data);
+ writel_relaxed((cfg->c0_c1_data[i] & 0xFFF) | data, addr);
- offset += 0x4;
+ addr += 0x4;
data |= (1 << 25);
- MDSS_MDP_REG_WRITE(offset, ((cfg->c0_c1_data[0] >> 16) & 0xFFF) | data);
+ writel_relaxed(((cfg->c0_c1_data[0] >> 16) & 0xFFF) | data, addr);
data &= ~(1 << 25);
for (i = 1; i < cfg->len; i++)
- MDSS_MDP_REG_WRITE(offset,
- ((cfg->c0_c1_data[i] >> 16) & 0xFFF) | data);
+ writel_relaxed(((cfg->c0_c1_data[i] >> 16) & 0xFFF) | data,
+ addr);
- offset += 0x4;
+ addr += 0x4;
data |= (1 << 25);
- MDSS_MDP_REG_WRITE(offset, (cfg->c2_data[0] & 0xFFF) | data);
+ writel_relaxed((cfg->c2_data[0] & 0xFFF) | data, addr);
data &= ~(1 << 25);
for (i = 1; i < cfg->len; i++)
- MDSS_MDP_REG_WRITE(offset, (cfg->c2_data[i] & 0xFFF) | data);
+ writel_relaxed((cfg->c2_data[i] & 0xFFF) | data, addr);
}
int mdss_mdp_limited_lut_igc_config(struct mdss_mdp_ctl *ctl)
@@ -1700,8 +2226,10 @@
u32 *copyback, u32 copy_from_kernel)
{
int ret = 0;
- u32 tbl_idx, igc_offset, disp_num, dspp_num = 0;
+ u32 tbl_idx, disp_num, dspp_num = 0;
struct mdp_igc_lut_data local_cfg;
+ char __iomem *igc_addr;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
@@ -1727,13 +2255,14 @@
tbl_idx = 2;
else
tbl_idx = 0;
- igc_offset = MDSS_MDP_REG_IGC_DSPP_BASE + (0x10 * tbl_idx);
+ igc_addr = mdata->mdp_base + MDSS_MDP_REG_IGC_DSPP_BASE +
+ (0x10 * tbl_idx);
local_cfg = *config;
local_cfg.c0_c1_data =
&mdss_pp_res->igc_lut_c0c1[disp_num][0];
local_cfg.c2_data =
&mdss_pp_res->igc_lut_c2[disp_num][0];
- pp_read_igc_lut(&local_cfg, igc_offset, dspp_num);
+ pp_read_igc_lut(&local_cfg, igc_addr, dspp_num);
if (copy_to_user(config->c0_c1_data, local_cfg.c2_data,
config->len * sizeof(u32))) {
ret = -EFAULT;
@@ -1781,126 +2310,128 @@
mutex_unlock(&mdss_pp_mutex);
return ret;
}
-static void pp_update_gc_one_lut(u32 offset,
+static void pp_update_gc_one_lut(char __iomem *addr,
struct mdp_ar_gc_lut_data *lut_data,
uint8_t num_stages)
{
int i, start_idx, idx;
- start_idx = (MDSS_MDP_REG_READ(offset) >> 16) & 0xF;
+ start_idx = (readl_relaxed(addr) >> 16) & 0xF;
for (i = start_idx; i < GC_LUT_SEGMENTS; i++) {
idx = min((uint8_t)i, (uint8_t)(num_stages-1));
- MDSS_MDP_REG_WRITE(offset, lut_data[idx].x_start);
+ writel_relaxed(lut_data[idx].x_start, addr);
}
for (i = 0; i < start_idx; i++) {
idx = min((uint8_t)i, (uint8_t)(num_stages-1));
- MDSS_MDP_REG_WRITE(offset, lut_data[idx].x_start);
+ writel_relaxed(lut_data[idx].x_start, addr);
}
- offset += 4;
- start_idx = (MDSS_MDP_REG_READ(offset) >> 16) & 0xF;
+ addr += 4;
+ start_idx = (readl_relaxed(addr) >> 16) & 0xF;
for (i = start_idx; i < GC_LUT_SEGMENTS; i++) {
idx = min((uint8_t)i, (uint8_t)(num_stages-1));
- MDSS_MDP_REG_WRITE(offset, lut_data[idx].slope);
+ writel_relaxed(lut_data[idx].slope, addr);
}
for (i = 0; i < start_idx; i++) {
idx = min((uint8_t)i, (uint8_t)(num_stages-1));
- MDSS_MDP_REG_WRITE(offset, lut_data[idx].slope);
+ writel_relaxed(lut_data[idx].slope, addr);
}
- offset += 4;
- start_idx = (MDSS_MDP_REG_READ(offset) >> 16) & 0xF;
+ addr += 4;
+ start_idx = (readl_relaxed(addr) >> 16) & 0xF;
for (i = start_idx; i < GC_LUT_SEGMENTS; i++) {
idx = min((uint8_t)i, (uint8_t)(num_stages-1));
- MDSS_MDP_REG_WRITE(offset, lut_data[idx].offset);
+ writel_relaxed(lut_data[idx].offset, addr);
}
for (i = 0; i < start_idx; i++) {
idx = min((uint8_t)i, (uint8_t)(num_stages-1));
- MDSS_MDP_REG_WRITE(offset, lut_data[idx].offset);
+ writel_relaxed(lut_data[idx].offset, addr);
}
}
-static void pp_update_argc_lut(u32 offset, struct mdp_pgc_lut_data *config)
+static void pp_update_argc_lut(char __iomem *addr,
+ struct mdp_pgc_lut_data *config)
{
- pp_update_gc_one_lut(offset, config->r_data, config->num_r_stages);
- offset += 0x10;
- pp_update_gc_one_lut(offset, config->g_data, config->num_g_stages);
- offset += 0x10;
- pp_update_gc_one_lut(offset, config->b_data, config->num_b_stages);
+ pp_update_gc_one_lut(addr, config->r_data, config->num_r_stages);
+ addr += 0x10;
+ pp_update_gc_one_lut(addr, config->g_data, config->num_g_stages);
+ addr += 0x10;
+ pp_update_gc_one_lut(addr, config->b_data, config->num_b_stages);
}
-static void pp_read_gc_one_lut(u32 offset,
+static void pp_read_gc_one_lut(char __iomem *addr,
struct mdp_ar_gc_lut_data *gc_data)
{
int i, start_idx, data;
- data = MDSS_MDP_REG_READ(offset);
+ data = readl_relaxed(addr);
start_idx = (data >> 16) & 0xF;
gc_data[start_idx].x_start = data & 0xFFF;
for (i = start_idx + 1; i < GC_LUT_SEGMENTS; i++) {
- data = MDSS_MDP_REG_READ(offset);
+ data = readl_relaxed(addr);
gc_data[i].x_start = data & 0xFFF;
}
for (i = 0; i < start_idx; i++) {
- data = MDSS_MDP_REG_READ(offset);
+ data = readl_relaxed(addr);
gc_data[i].x_start = data & 0xFFF;
}
- offset += 4;
- data = MDSS_MDP_REG_READ(offset);
+ addr += 4;
+ data = readl_relaxed(addr);
start_idx = (data >> 16) & 0xF;
gc_data[start_idx].slope = data & 0x7FFF;
for (i = start_idx + 1; i < GC_LUT_SEGMENTS; i++) {
- data = MDSS_MDP_REG_READ(offset);
+ data = readl_relaxed(addr);
gc_data[i].slope = data & 0x7FFF;
}
for (i = 0; i < start_idx; i++) {
- data = MDSS_MDP_REG_READ(offset);
+ data = readl_relaxed(addr);
gc_data[i].slope = data & 0x7FFF;
}
- offset += 4;
- data = MDSS_MDP_REG_READ(offset);
+ addr += 4;
+ data = readl_relaxed(addr);
start_idx = (data >> 16) & 0xF;
gc_data[start_idx].offset = data & 0x7FFF;
for (i = start_idx + 1; i < GC_LUT_SEGMENTS; i++) {
- data = MDSS_MDP_REG_READ(offset);
+ data = readl_relaxed(addr);
gc_data[i].offset = data & 0x7FFF;
}
for (i = 0; i < start_idx; i++) {
- data = MDSS_MDP_REG_READ(offset);
+ data = readl_relaxed(addr);
gc_data[i].offset = data & 0x7FFF;
}
}
-static int pp_read_argc_lut(struct mdp_pgc_lut_data *config, u32 offset)
+static int pp_read_argc_lut(struct mdp_pgc_lut_data *config, char __iomem *addr)
{
int ret = 0;
- pp_read_gc_one_lut(offset, config->r_data);
- offset += 0x10;
- pp_read_gc_one_lut(offset, config->g_data);
- offset += 0x10;
- pp_read_gc_one_lut(offset, config->b_data);
+ pp_read_gc_one_lut(addr, config->r_data);
+ addr += 0x10;
+ pp_read_gc_one_lut(addr, config->g_data);
+ addr += 0x10;
+ pp_read_gc_one_lut(addr, config->b_data);
return ret;
}
/* Note: Assumes that its inputs have been checked by calling function */
-static void pp_update_hist_lut(char __iomem *offset,
+static void pp_update_hist_lut(char __iomem *addr,
struct mdp_hist_lut_data *cfg)
{
int i;
for (i = 0; i < ENHIST_LUT_ENTRIES; i++)
- writel_relaxed(cfg->data[i], offset);
+ writel_relaxed(cfg->data[i], addr);
/* swap */
if (PP_LOCAT(cfg->block) == MDSS_PP_DSPP_CFG)
- writel_relaxed(1, offset + 4);
+ writel_relaxed(1, addr + 4);
else
- writel_relaxed(1, offset + 16);
+ writel_relaxed(1, addr + 16);
}
int mdss_mdp_argc_config(struct mdp_pgc_lut_data *config,
u32 *copyback)
{
int ret = 0;
- u32 argc_offset = 0, disp_num, dspp_num = 0;
+ u32 disp_num, dspp_num = 0;
struct mdp_pgc_lut_data local_cfg;
struct mdp_pgc_lut_data *pgc_ptr;
u32 tbl_size, r_size, g_size, b_size;
+ char __iomem *argc_addr = 0;
if ((PP_BLOCK(config->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(config->block) >= MDP_BLOCK_MAX))
@@ -1911,14 +2442,14 @@
disp_num = PP_BLOCK(config->block) - MDP_LOGICAL_BLOCK_DISP_0;
switch (PP_LOCAT(config->block)) {
case MDSS_PP_LM_CFG:
- argc_offset = MDSS_MDP_REG_LM_OFFSET(dspp_num) +
+ argc_addr = mdss_mdp_get_mixer_addr_off(dspp_num) +
MDSS_MDP_REG_LM_GC_LUT_BASE;
pgc_ptr = &mdss_pp_res->argc_disp_cfg[disp_num];
mdss_pp_res->pp_disp_flags[disp_num] |=
PP_FLAGS_DIRTY_ARGC;
break;
case MDSS_PP_DSPP_CFG:
- argc_offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
+ argc_addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
MDSS_MDP_REG_DSPP_GC_BASE;
pgc_ptr = &mdss_pp_res->pgc_disp_cfg[disp_num];
mdss_pp_res->pp_disp_flags[disp_num] |=
@@ -1946,7 +2477,7 @@
&mdss_pp_res->gc_lut_g[disp_num][0];
local_cfg.b_data =
&mdss_pp_res->gc_lut_b[disp_num][0];
- pp_read_argc_lut(&local_cfg, argc_offset);
+ pp_read_argc_lut(&local_cfg, argc_addr);
if (copy_to_user(config->r_data,
&mdss_pp_res->gc_lut_r[disp_num][0], tbl_size)) {
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
@@ -2017,7 +2548,8 @@
u32 *copyback)
{
int i, ret = 0;
- u32 hist_offset, disp_num, dspp_num = 0;
+ u32 disp_num, dspp_num = 0;
+ char __iomem *hist_addr;
if ((PP_BLOCK(config->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(config->block) >= MDP_BLOCK_MAX))
@@ -2035,11 +2567,11 @@
}
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- hist_offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
+ hist_addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
MDSS_MDP_REG_DSPP_HIST_LUT_BASE;
for (i = 0; i < ENHIST_LUT_ENTRIES; i++)
mdss_pp_res->enhist_lut[disp_num][i] =
- MDSS_MDP_REG_READ(hist_offset);
+ readl_relaxed(hist_addr);
if (copy_to_user(config->data,
&mdss_pp_res->enhist_lut[disp_num][0],
ENHIST_LUT_ENTRIES * sizeof(u32))) {
@@ -2110,13 +2642,13 @@
u32 *copyback)
{
int i, j, ret = 0;
- u32 offset, disp_num, dspp_num = 0;
+ u32 disp_num, dspp_num = 0;
uint16_t *tbl_off;
struct mdp_gamut_cfg_data local_cfg;
uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM];
uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM];
uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
-
+ char __iomem *addr;
if ((config->block < MDP_LOGICAL_BLOCK_DISP_0) ||
(config->block >= MDP_BLOCK_MAX))
@@ -2137,7 +2669,7 @@
}
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
+ addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
MDSS_MDP_REG_DSPP_GAMUT_BASE;
for (i = 0; i < MDP_GAMUT_TABLE_NUM; i++) {
r_tbl[i] = kzalloc(
@@ -2149,8 +2681,8 @@
}
for (j = 0; j < config->tbl_size[i]; j++)
r_tbl[i][j] =
- (u16)MDSS_MDP_REG_READ(offset);
- offset += 4;
+ (u16)readl_relaxed(addr);
+ addr += 4;
ret = copy_to_user(config->r_tbl[i], r_tbl[i],
sizeof(uint16_t) * config->tbl_size[i]);
kfree(r_tbl[i]);
@@ -2170,8 +2702,8 @@
}
for (j = 0; j < config->tbl_size[i]; j++)
g_tbl[i][j] =
- (u16)MDSS_MDP_REG_READ(offset);
- offset += 4;
+ (u16)readl_relaxed(addr);
+ addr += 4;
ret = copy_to_user(config->g_tbl[i], g_tbl[i],
sizeof(uint16_t) * config->tbl_size[i]);
kfree(g_tbl[i]);
@@ -2191,8 +2723,8 @@
}
for (j = 0; j < config->tbl_size[i]; j++)
b_tbl[i][j] =
- (u16)MDSS_MDP_REG_READ(offset);
- offset += 4;
+ (u16)readl_relaxed(addr);
+ addr += 4;
ret = copy_to_user(config->b_tbl[i], b_tbl[i],
sizeof(uint16_t) * config->tbl_size[i]);
kfree(b_tbl[i]);
@@ -2241,19 +2773,27 @@
mutex_unlock(&mdss_pp_mutex);
return ret;
}
-static void pp_hist_read(char __iomem *v_base,
+
+static u32 pp_hist_read(char __iomem *v_addr,
struct pp_hist_col_info *hist_info)
{
int i, i_start;
+ u32 sum = 0;
u32 data;
- data = readl_relaxed(v_base);
+ data = readl_relaxed(v_addr);
i_start = data >> 24;
hist_info->data[i_start] = data & 0xFFFFFF;
- for (i = i_start + 1; i < HIST_V_SIZE; i++)
- hist_info->data[i] = readl_relaxed(v_base) & 0xFFFFFF;
- for (i = 0; i < i_start - 1; i++)
- hist_info->data[i] = readl_relaxed(v_base) & 0xFFFFFF;
+ sum += hist_info->data[i_start];
+ for (i = i_start + 1; i < HIST_V_SIZE; i++) {
+ hist_info->data[i] = readl_relaxed(v_addr) & 0xFFFFFF;
+ sum += hist_info->data[i];
+ }
+ for (i = 0; i < i_start; i++) {
+ hist_info->data[i] = readl_relaxed(v_addr) & 0xFFFFFF;
+ sum += hist_info->data[i];
+ }
hist_info->hist_cnt_read++;
+ return sum;
}
/* Assumes that relevant clocks are enabled */
@@ -2263,6 +2803,8 @@
{
unsigned long flag;
int ret = 0;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
+
mutex_lock(&hist_info->hist_mutex);
/* check if it is idle */
if (hist_info->col_en) {
@@ -2282,7 +2824,7 @@
hist_info->col_en = true;
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
hist_info->is_kick_ready = true;
- mdss_mdp_hist_irq_enable(3 << shift_bit);
+ mdss_mdp_hist_intr_req(&mdata->hist_intr, 3 << shift_bit, true);
writel_relaxed(req->frame_cnt, ctl_base + 8);
/* Kick out reset start */
writel_relaxed(1, ctl_base + 4);
@@ -2291,7 +2833,8 @@
return ret;
}
-int mdss_mdp_histogram_start(struct mdp_histogram_start_req *req)
+#define MDSS_MAX_HIST_BIN_SIZE 16777215
+int mdss_mdp_hist_start(struct mdp_histogram_start_req *req)
{
u32 done_shift_bit;
char __iomem *ctl_base;
@@ -2299,9 +2842,13 @@
int i, ret = 0;
u32 disp_num, dspp_num = 0;
u32 mixer_cnt, mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];
+ u32 frame_size;
struct mdss_mdp_pipe *pipe;
struct mdss_data_type *mdata = mdss_mdp_get_mdata();
+ if (!mdss_is_ready())
+ return -EPROBE_DEFER;
+
if ((PP_BLOCK(req->block) < MDP_LOGICAL_BLOCK_DISP_0) ||
(PP_BLOCK(req->block) >= MDP_BLOCK_MAX))
return -EINVAL;
@@ -2321,6 +2868,16 @@
ret = -EPERM;
goto hist_exit;
}
+
+ frame_size = (mdata->ctl_off[mixer_id[0]].width *
+ mdata->ctl_off[mixer_id[0]].height);
+ if (!frame_size ||
+ ((MDSS_MAX_HIST_BIN_SIZE / frame_size) < req->frame_cnt)) {
+ pr_err("%s, too many frames for given display size, %d",
+ __func__, req->frame_cnt);
+ ret = -EINVAL;
+ goto hist_exit;
+ }
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
if (PP_LOCAT(req->block) == MDSS_PP_SSPP_CFG) {
@@ -2328,7 +2885,7 @@
if (!i) {
ret = -EINVAL;
pr_warn("Must pass pipe arguments, %d", i);
- goto hist_exit;
+ goto hist_stop_clk;
}
for (i = 0; i < MDSS_PP_ARG_NUM; i++) {
@@ -2338,10 +2895,9 @@
if (IS_ERR_OR_NULL(pipe))
continue;
if (!pipe || pipe->num > MDSS_MDP_SSPP_VIG2) {
- mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
ret = -EINVAL;
pr_warn("Invalid Hist pipe (%d)", i);
- goto hist_exit;
+ goto hist_stop_clk;
}
done_shift_bit = (pipe->num * 4);
hist_info = &pipe->pp_res.hist;
@@ -2364,8 +2920,8 @@
PP_FLAGS_DIRTY_HIST_COL;
}
}
+hist_stop_clk:
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
-
hist_exit:
return ret;
}
@@ -2375,6 +2931,8 @@
{
int ret = 0;
unsigned long flag;
+ struct mdss_data_type *mdata = mdss_mdp_get_mdata();
+
mutex_lock(&hist_info->hist_mutex);
if (hist_info->col_en == false) {
pr_debug("Histogram already disabled (%d)", (u32) ctl_base);
@@ -2387,7 +2945,7 @@
hist_info->col_state = HIST_UNKNOWN;
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
hist_info->is_kick_ready = false;
- mdss_mdp_hist_irq_disable(done_bit);
+ mdss_mdp_hist_intr_req(&mdata->hist_intr, done_bit, false);
writel_relaxed(BIT(1), ctl_base);/* cancel */
ret = 0;
exit:
@@ -2395,7 +2953,7 @@
return ret;
}
-int mdss_mdp_histogram_stop(u32 block)
+int mdss_mdp_hist_stop(u32 block)
{
int i, ret = 0;
char __iomem *ctl_base;
@@ -2472,12 +3030,156 @@
return ret;
}
+/**
+ * mdss_mdp_hist_intr_req() - Request changes the histogram interupts
+ * @intr: structure containting state of interrupt register
+ * @bits: the bits on interrupt register that should be changed
+ * @en: true if bits should be set, false if bits should be cleared
+ *
+ * Adds or removes the bits from the interrupt request.
+ *
+ * Does not store reference count for each bit. I.e. a bit with multiple
+ * enable requests can be disabled with a single disable request.
+ *
+ * Return: 0 if uneventful, errno on invalid input
+ */
+int mdss_mdp_hist_intr_req(struct mdss_intr *intr, u32 bits, bool en)
+{
+ unsigned long flag;
+ int ret = 0;
+ if (!intr) {
+ pr_err("NULL addr passed, %p", intr);
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&intr->lock, flag);
+ if (en)
+ intr->req |= bits;
+ else
+ intr->req &= ~bits;
+ spin_unlock_irqrestore(&intr->lock, flag);
+
+ mdss_mdp_hist_intr_setup(intr, MDSS_IRQ_REQ);
+
+ return ret;
+}
+
+
+#define MDSS_INTR_STATE_ACTIVE 1
+#define MDSS_INTR_STATE_NULL 0
+#define MDSS_INTR_STATE_SUSPEND -1
+
+/**
+ * mdss_mdp_hist_intr_setup() - Manage intr and clk depending on requests.
+ * @intr: structure containting state of intr reg
+ * @state: MDSS_IRQ_SUSPEND if suspend is needed,
+ * MDSS_IRQ_RESUME if resume is needed,
+ * MDSS_IRQ_REQ if neither (i.e. requesting an interrupt)
+ *
+ * This function acts as a gatekeeper for the interrupt, making sure that the
+ * MDP clocks are enabled while the interrupts are enabled to prevent
+ * unclocked accesses.
+ *
+ * To reduce code repetition, 4 state transitions have been encoded here. Each
+ * transition updates the interrupt's state structure (mdss_intr) to reflect
+ * the which bits have been requested (intr->req), are currently enabled
+ * (intr->curr), as well as defines which interrupt bits need to be enabled or
+ * disabled ('en' and 'dis' respectively). The 4th state is not explicity
+ * coded in the if/else chain, but is for MDSS_IRQ_REQ's when the interrupt
+ * is in suspend, in which case, the only change required (intr->req being
+ * updated) has already occured in the calling function.
+ *
+ * To control the clock, which can't be requested while holding the spinlock,
+ * the inital state is compared with the exit state to detect when the
+ * interrupt needs a clock.
+ *
+ * The clock requests surrounding the majority of this function serve to
+ * enable the register writes to change the interrupt register, as well as to
+ * prevent a race condition that could keep the clocks on (due to mdp_clk_cnt
+ * never being decremented below 0) when a enable/disable occurs but the
+ * disable requests the clocks disabled before the enable is able to request
+ * the clocks enabled.
+ *
+ * Return: 0 if uneventful, errno on repeated action or invalid input
+ */
+int mdss_mdp_hist_intr_setup(struct mdss_intr *intr, int type)
+{
+ unsigned long flag;
+ int ret = 0, req_clk = 0;
+ u32 en = 0, dis = 0;
+ u32 diff, init_curr;
+ int init_state;
+ if (!intr) {
+ WARN(1, "NULL intr pointer");
+ return -EINVAL;
+ }
+
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+ spin_lock_irqsave(&intr->lock, flag);
+
+ init_state = intr->state;
+ init_curr = intr->curr;
+
+ if (type == MDSS_IRQ_RESUME) {
+ /* resume intrs */
+ if (intr->state == MDSS_INTR_STATE_ACTIVE) {
+ ret = -EPERM;
+ goto exit;
+ }
+ en = intr->req;
+ dis = 0;
+ intr->curr = intr->req;
+ intr->state = intr->curr ?
+ MDSS_INTR_STATE_ACTIVE : MDSS_INTR_STATE_NULL;
+ } else if (type == MDSS_IRQ_SUSPEND) {
+ /* suspend intrs */
+ if (intr->state == MDSS_INTR_STATE_SUSPEND) {
+ ret = -EPERM;
+ goto exit;
+ }
+ en = 0;
+ dis = intr->curr;
+ intr->curr = 0;
+ intr->state = MDSS_INTR_STATE_SUSPEND;
+ } else if (intr->state != MDSS_IRQ_SUSPEND) {
+ /* Not resuming/suspending or in suspend state */
+ diff = intr->req ^ intr->curr;
+ en = diff & ~intr->curr;
+ dis = diff & ~intr->req;
+ intr->curr = intr->req;
+ intr->state = intr->curr ?
+ MDSS_INTR_STATE_ACTIVE : MDSS_INTR_STATE_NULL;
+ }
+
+ if (en)
+ mdss_mdp_hist_irq_enable(en);
+ if (dis)
+ mdss_mdp_hist_irq_disable(dis);
+
+ if ((init_state != MDSS_INTR_STATE_ACTIVE) &&
+ (intr->state == MDSS_INTR_STATE_ACTIVE))
+ req_clk = 1;
+ else if ((init_state == MDSS_INTR_STATE_ACTIVE) &&
+ (intr->state != MDSS_INTR_STATE_ACTIVE))
+ req_clk = -1;
+
+exit:
+ spin_unlock_irqrestore(&intr->lock, flag);
+ if (req_clk < 0)
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
+ else if (req_clk > 0)
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
+
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
+ return ret;
+}
+
static int pp_hist_collect(struct mdp_histogram_data *hist,
struct pp_hist_col_info *hist_info,
- char __iomem *ctl_base)
+ char __iomem *ctl_base, u32 expect_sum)
{
int wait_ret, ret = 0;
- u32 timeout;
+ u32 timeout, sum;
char __iomem *v_base;
unsigned long flag;
struct mdss_pipe_pp_res *res;
@@ -2544,10 +3246,13 @@
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
v_base = ctl_base + 0x1C;
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
- pp_hist_read(v_base, hist_info);
+ sum = pp_hist_read(v_base, hist_info);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
spin_lock_irqsave(&hist_info->hist_lock, flag);
- hist_info->read_request = false;
+ if (!expect_sum || sum == expect_sum)
+ hist_info->read_request = false;
+ else
+ ret = -ENODATA;
hist_info->col_state = HIST_IDLE;
}
spin_unlock_irqrestore(&hist_info->hist_lock, flag);
@@ -2567,6 +3272,7 @@
u32 *hist_data_addr;
u32 pipe_cnt = 0;
u32 pipe_num = MDSS_MDP_SSPP_VIG0;
+ u32 exp_sum = 0;
struct mdss_mdp_pipe *pipe;
struct mdss_data_type *mdata = mdss_mdp_get_mdata();
@@ -2596,7 +3302,10 @@
hist_info = &mdss_pp_res->dspp_hist[dspp_num];
ctl_base = mdss_mdp_get_dspp_addr_off(dspp_num) +
MDSS_MDP_REG_DSPP_HIST_CTL_BASE;
- ret = pp_hist_collect(hist, hist_info, ctl_base);
+ exp_sum = (mdata->mixer_intf[dspp_num].width *
+ mdata->mixer_intf[dspp_num].height);
+ ret = pp_hist_collect(hist, hist_info, ctl_base,
+ exp_sum);
if (ret)
goto hist_collect_exit;
}
@@ -2665,7 +3374,8 @@
hist_info = &pipe->pp_res.hist;
ctl_base = pipe->base +
MDSS_MDP_REG_VIG_HIST_CTL_BASE;
- ret = pp_hist_collect(hist, hist_info, ctl_base);
+ ret = pp_hist_collect(hist, hist_info, ctl_base,
+ exp_sum);
mdss_mdp_pipe_unmap(pipe);
if (ret)
goto hist_collect_exit;
@@ -2796,7 +3506,6 @@
return out;
}
-#define MDSS_AD_MAX_MIXERS 1
static int mdss_ad_init_checks(struct msm_fb_data_type *mfd)
{
u32 mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];
@@ -2822,8 +3531,9 @@
pr_debug("no mixers connected, %d", mixer_num);
return -EHOSTDOWN;
}
- if (mixer_num > MDSS_AD_MAX_MIXERS) {
- pr_debug("too many mixers, not supported, %d", mixer_num);
+ if (mixer_num > mdata->nmax_concurrent_ad_hw) {
+ pr_debug("too many mixers, not supported, %d > %d", mixer_num,
+ mdata->nmax_concurrent_ad_hw);
return ret;
}
@@ -2987,6 +3697,11 @@
ret = -EINVAL;
goto error;
}
+ if (input->in.amb_light > MDSS_MDP_MAX_AD_AL) {
+ pr_warn("invalid input ambient light");
+ ret = -EINVAL;
+ goto error;
+ }
ad->ad_data_mode = MDSS_AD_INPUT_AMBIENT;
pr_debug("ambient = %d", input->in.amb_light);
ad->ad_data = input->in.amb_light;
@@ -3001,6 +3716,11 @@
ret = -EINVAL;
goto error;
}
+ if (input->in.strength > MDSS_MDP_MAX_AD_STR) {
+ pr_warn("invalid input strength");
+ ret = -EINVAL;
+ goto error;
+ }
ad->ad_data_mode = MDSS_AD_INPUT_STRENGTH;
pr_debug("strength = %d", input->in.strength);
ad->ad_data = input->in.strength;
@@ -3052,23 +3772,26 @@
return ret;
}
-static void pp_ad_input_write(struct mdss_ad_info *ad, u32 bl_lvl)
+static void pp_ad_input_write(struct mdss_mdp_ad *ad_hw,
+ struct mdss_ad_info *ad)
{
- char __iomem *base = ad->base;
+ char __iomem *base;
+
+ base = ad_hw->base;
switch (ad->cfg.mode) {
case MDSS_AD_MODE_AUTO_BL:
writel_relaxed(ad->ad_data, base + MDSS_MDP_REG_AD_AL);
break;
case MDSS_AD_MODE_AUTO_STR:
- writel_relaxed(bl_lvl, base + MDSS_MDP_REG_AD_BL);
+ writel_relaxed(ad->bl_data, base + MDSS_MDP_REG_AD_BL);
writel_relaxed(ad->ad_data, base + MDSS_MDP_REG_AD_AL);
break;
case MDSS_AD_MODE_TARG_STR:
- writel_relaxed(bl_lvl, base + MDSS_MDP_REG_AD_BL);
+ writel_relaxed(ad->bl_data, base + MDSS_MDP_REG_AD_BL);
writel_relaxed(ad->ad_data, base + MDSS_MDP_REG_AD_TARG_STR);
break;
case MDSS_AD_MODE_MAN_STR:
- writel_relaxed(bl_lvl, base + MDSS_MDP_REG_AD_BL);
+ writel_relaxed(ad->bl_data, base + MDSS_MDP_REG_AD_BL);
writel_relaxed(ad->ad_data, base + MDSS_MDP_REG_AD_STR_MAN);
break;
default:
@@ -3077,10 +3800,27 @@
}
}
-static void pp_ad_init_write(struct mdss_ad_info *ad)
+#define MDSS_AD_MERGED_WIDTH 4
+static void pp_ad_init_write(struct mdss_mdp_ad *ad_hw, struct mdss_ad_info *ad,
+ struct mdss_mdp_ctl *ctl)
{
+ struct mdss_data_type *mdata = ctl->mdata;
u32 temp;
- char __iomem *base = ad->base;
+ u32 frame_start, frame_end, procs_start, procs_end, tile_ctrl;
+ u32 num;
+ char __iomem *base;
+ bool is_calc, is_dual_pipe;
+ u32 mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];
+ u32 mixer_num;
+ mixer_num = mdss_mdp_get_ctl_mixers(ctl->mfd->index, mixer_id);
+ if (mixer_num > 1)
+ is_dual_pipe = true;
+ else
+ is_dual_pipe = false;
+
+ base = ad_hw->base;
+ is_calc = ad->calc_hw_num == ad_hw->num;
+
writel_relaxed(ad->init.i_control[0] & 0x1F,
base + MDSS_MDP_REG_AD_CON_CTRL_0);
writel_relaxed(ad->init.i_control[1] << 8,
@@ -3115,13 +3855,50 @@
pp_ad_cfg_lut(base + MDSS_MDP_REG_AD_LUT_FI, ad->init.asym_lut);
pp_ad_cfg_lut(base + MDSS_MDP_REG_AD_LUT_CC, ad->init.color_corr_lut);
+
+ if (mdata->mdp_rev >= MDSS_MDP_HW_REV_103) {
+ if (is_dual_pipe) {
+ num = ad_hw->num;
+ tile_ctrl = 0x5;
+ if (is_calc) {
+ frame_start = 0;
+ procs_start = 0;
+ frame_end = mdata->mixer_intf[num].width +
+ MDSS_AD_MERGED_WIDTH;
+ procs_end = mdata->mixer_intf[num].width;
+ } else {
+ tile_ctrl |= 0x10;
+ procs_start = ad->init.frame_w -
+ (mdata->mixer_intf[num].width);
+ procs_end = ad->init.frame_w;
+ frame_start = procs_start -
+ MDSS_AD_MERGED_WIDTH;
+ frame_end = procs_end;
+ }
+ procs_end -= 1;
+ frame_end -= 1;
+ } else {
+ frame_start = 0x0;
+ frame_end = 0xFFFF;
+ procs_start = 0x0;
+ procs_end = 0xFFFF;
+ tile_ctrl = 0x1;
+ }
+ writel_relaxed(frame_start, base + MDSS_MDP_REG_AD_FRAME_START);
+ writel_relaxed(frame_end, base + MDSS_MDP_REG_AD_FRAME_END);
+ writel_relaxed(procs_start, base + MDSS_MDP_REG_AD_PROCS_START);
+ writel_relaxed(procs_end, base + MDSS_MDP_REG_AD_PROCS_END);
+ writel_relaxed(tile_ctrl, base + MDSS_MDP_REG_AD_TILE_CTRL);
+ }
}
#define MDSS_PP_AD_DEF_CALIB 0x6E
-static void pp_ad_cfg_write(struct mdss_ad_info *ad)
+static void pp_ad_cfg_write(struct mdss_mdp_ad *ad_hw, struct mdss_ad_info *ad)
{
- char __iomem *base = ad->base;
+ char __iomem *base;
u32 temp, temp_calib = MDSS_PP_AD_DEF_CALIB;
+
+ base = ad_hw->base;
switch (ad->cfg.mode) {
case MDSS_AD_MODE_AUTO_BL:
temp = ad->cfg.backlight_max << 16;
@@ -3170,29 +3947,57 @@
}
#define MDSS_PP_AD_BYPASS_DEF 0x101
+static void pp_ad_bypass_config(struct mdss_ad_info *ad, u32 *opmode)
+{
+ if (ad->reg_sts & PP_STS_ENABLE)
+ *opmode = 0;
+ else
+ *opmode = MDSS_PP_AD_BYPASS_DEF;
+}
+
+static int pp_ad_setup_hw_nums(struct msm_fb_data_type *mfd,
+ struct mdss_ad_info *ad)
+{
+ u32 mixer_id[MDSS_MDP_INTF_MAX_LAYERMIXER];
+ u32 mixer_num;
+
+ mixer_num = mdss_mdp_get_ctl_mixers(mfd->index, mixer_id);
+ if (!mixer_num)
+ return -EINVAL;
+
+ /* default to left mixer */
+ ad->calc_hw_num = mixer_id[0];
+ return 0;
+}
+
static int mdss_mdp_ad_setup(struct msm_fb_data_type *mfd)
{
int ret = 0;
struct mdss_ad_info *ad;
struct mdss_mdp_ctl *ctl = mfd_to_ctl(mfd);
struct msm_fb_data_type *bl_mfd;
- char __iomem *base;
- u32 temp;
+ struct mdss_data_type *mdata;
u32 bypass = MDSS_PP_AD_BYPASS_DEF, bl;
ret = mdss_mdp_get_ad(mfd, &ad);
- if (ret)
- return ret;
+ if (ret) {
+ ret = -EINVAL;
+ pr_debug("failed to get ad_info, err = %d", ret);
+ goto exit;
+ }
if (mfd->panel_info->type == WRITEBACK_PANEL) {
bl_mfd = mdss_get_mfd_from_index(0);
- if (!bl_mfd)
- return ret;
+ if (!bl_mfd) {
+ ret = -EINVAL;
+ pr_warn("failed to get primary FB bl handle, err = %d",
+ ret);
+ goto exit;
+ }
} else {
bl_mfd = mfd;
}
-
- base = ad->base;
+ mdata = mfd_to_mdata(mfd);
mutex_lock(&ad->lock);
if (ad->sts != last_sts || ad->state != last_state) {
@@ -3222,17 +4027,17 @@
bl = ad->bl_lin[bl >> ad->bl_bright_shift];
bl = bl << ad->bl_bright_shift;
}
- mutex_unlock(&bl_mfd->bl_lock);
+ ad->bl_data = bl;
}
- mutex_unlock(&mfd->bl_lock);
- pp_ad_input_write(ad, bl);
+ mutex_unlock(&bl_mfd->bl_lock);
+ ad->reg_sts |= PP_AD_STS_DIRTY_DATA;
}
if (ad->sts & PP_AD_STS_DIRTY_CFG) {
ad->sts &= ~PP_AD_STS_DIRTY_CFG;
ad->state |= PP_AD_STATE_CFG;
- pp_ad_cfg_write(ad);
+ ad->reg_sts |= PP_AD_STS_DIRTY_CFG;
if (!MDSS_AD_MODE_DATA_MATCH(ad->cfg.mode, ad->ad_data_mode)) {
ad->sts &= ~PP_AD_STS_DIRTY_DATA;
@@ -3242,8 +4047,13 @@
}
if (ad->sts & PP_AD_STS_DIRTY_INIT) {
ad->sts &= ~PP_AD_STS_DIRTY_INIT;
- ad->state |= PP_AD_STATE_INIT;
- pp_ad_init_write(ad);
+ if (pp_ad_setup_hw_nums(mfd, ad)) {
+ pr_warn("failed to setup ad master");
+ ad->calc_hw_num = PP_AD_BAD_HW_NUM;
+ } else {
+ ad->state |= PP_AD_STATE_INIT;
+ ad->reg_sts |= PP_AD_STS_DIRTY_INIT;
+ }
}
/* update ad screen size if it has changed since last configuration */
@@ -3256,14 +4066,12 @@
ctl->height);
ad->init.frame_w = ctl->width;
ad->init.frame_h = ctl->height;
- temp = ad->init.frame_w << 16;
- temp |= ad->init.frame_h & 0xFFFF;
- writel_relaxed(temp, base + MDSS_MDP_REG_AD_FRAME_SIZE);
+ ad->reg_sts |= PP_AD_STS_DIRTY_INIT;
}
if ((ad->sts & PP_STS_ENABLE) && PP_AD_STATE_IS_READY(ad->state)) {
bypass = 0;
- ret = 1;
+ ad->reg_sts |= PP_AD_STS_DIRTY_ENABLE;
ad->state |= PP_AD_STATE_RUN;
mutex_lock(&bl_mfd->bl_lock);
if (bl_mfd != mfd)
@@ -3274,7 +4082,7 @@
} else {
if (ad->state & PP_AD_STATE_RUN) {
- ret = 1;
+ ad->reg_sts = PP_AD_STS_DIRTY_ENABLE;
/* Clear state and regs when going to off state*/
ad->sts = 0;
ad->sts |= PP_AD_STS_DIRTY_VSYNC;
@@ -3287,6 +4095,7 @@
ad->ad_data_mode = 0;
ad->last_bl = 0;
ad->calc_itr = 0;
+ ad->calc_hw_num = PP_AD_BAD_HW_NUM;
memset(&ad->bl_lin, 0, sizeof(uint32_t) *
AD_BL_LIN_LEN);
memset(&ad->bl_lin_inv, 0, sizeof(uint32_t) *
@@ -3301,7 +4110,10 @@
}
ad->state &= ~PP_AD_STATE_RUN;
}
- writel_relaxed(bypass, base);
+ if (!bypass)
+ ad->reg_sts |= PP_STS_ENABLE;
+ else
+ ad->reg_sts &= ~PP_STS_ENABLE;
if (PP_AD_STS_DIRTY_VSYNC & ad->sts) {
pr_debug("dirty vsync, calc_itr = %d", ad->calc_itr);
@@ -3324,6 +4136,7 @@
ad->state);
}
mutex_unlock(&ad->lock);
+exit:
return ret;
}
@@ -3333,6 +4146,8 @@
struct mdss_ad_info *ad;
struct mdss_mdp_ctl *ctl;
struct msm_fb_data_type *mfd, *bl_mfd;
+ struct mdss_data_type *mdata;
+ char __iomem *base;
u32 bl, calc_done = 0;
ad = container_of(work, struct mdss_ad_info, calc_work);
@@ -3344,29 +4159,39 @@
mfd = ad->mfd;
bl_mfd = ad->bl_mfd;
ctl = mfd_to_ctl(ad->mfd);
+ mdata = mfd_to_mdata(ad->mfd);
+
+ if (!mdata || ad->calc_hw_num > mdata->nad_cfgs) {
+ mutex_unlock(&ad->lock);
+ return;
+ }
+
+
+ base = mdata->ad_off[ad->calc_hw_num].base;
if ((ad->cfg.mode == MDSS_AD_MODE_AUTO_STR) && (ad->last_bl == 0)) {
mutex_unlock(&ad->lock);
return;
}
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
if (PP_AD_STATE_RUN & ad->state) {
/* Kick off calculation */
ad->calc_itr--;
- writel_relaxed(1, ad->base + MDSS_MDP_REG_AD_START_CALC);
+ writel_relaxed(1, base + MDSS_MDP_REG_AD_START_CALC);
}
if (ad->state & PP_AD_STATE_RUN) {
do {
- calc_done = readl_relaxed(ad->base +
+ calc_done = readl_relaxed(base +
MDSS_MDP_REG_AD_CALC_DONE);
if (!calc_done)
usleep(MDSS_PP_AD_SLEEP);
} while (!calc_done && (ad->state & PP_AD_STATE_RUN));
if (calc_done) {
- ad->last_str = 0xFF & readl_relaxed(ad->base +
+ ad->last_str = 0xFF & readl_relaxed(base +
MDSS_MDP_REG_AD_STR_OUT);
if (MDSS_AD_RUNNING_AUTO_BL(ad)) {
- bl = 0xFFFF & readl_relaxed(ad->base +
+ bl = 0xFFFF & readl_relaxed(base +
MDSS_MDP_REG_AD_BL_OUT);
if (ad->state & PP_AD_STATE_BL_LIN) {
bl = bl >> ad->bl_bright_shift;
@@ -3389,6 +4214,7 @@
ad->last_str = 0xFFFFFFFF;
}
}
+ mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
complete(&ad->comp);
if (!ad->calc_itr) {
@@ -3405,7 +4231,7 @@
}
#define PP_AD_LUT_LEN 33
-static void pp_ad_cfg_lut(char __iomem *offset, u32 *data)
+static void pp_ad_cfg_lut(char __iomem *addr, u32 *data)
{
int i;
u32 temp;
@@ -3413,30 +4239,42 @@
for (i = 0; i < PP_AD_LUT_LEN - 1; i += 2) {
temp = data[i+1] << 16;
temp |= (data[i] & 0xFFFF);
- writel_relaxed(temp, offset + (i*2));
+ writel_relaxed(temp, addr + (i*2));
}
writel_relaxed(data[PP_AD_LUT_LEN - 1] << 16,
- offset + ((PP_AD_LUT_LEN - 1) * 2));
+ addr + ((PP_AD_LUT_LEN - 1) * 2));
}
-int mdss_mdp_ad_addr_setup(struct mdss_data_type *mdata, u32 *ad_off)
+int mdss_mdp_ad_addr_setup(struct mdss_data_type *mdata, u32 *ad_offsets)
{
u32 i;
int rc = 0;
- mdata->ad_cfgs = devm_kzalloc(&mdata->pdev->dev,
- sizeof(struct mdss_ad_info) * mdata->nad_cfgs,
+ mdata->ad_off = devm_kzalloc(&mdata->pdev->dev,
+ sizeof(struct mdss_mdp_ad) * mdata->nad_cfgs,
GFP_KERNEL);
+ if (!mdata->ad_off) {
+ pr_err("unable to setup assertive display hw:devm_kzalloc fail\n");
+ return -ENOMEM;
+ }
+
+ mdata->ad_cfgs = devm_kzalloc(&mdata->pdev->dev,
+ sizeof(struct mdss_ad_info) * mdata->nad_cfgs,
+ GFP_KERNEL);
+
if (!mdata->ad_cfgs) {
pr_err("unable to setup assertive display:devm_kzalloc fail\n");
+ devm_kfree(&mdata->pdev->dev, mdata->ad_off);
return -ENOMEM;
}
mdata->ad_calc_wq = create_singlethread_workqueue("ad_calc_wq");
for (i = 0; i < mdata->nad_cfgs; i++) {
- mdata->ad_cfgs[i].base = mdata->mdp_base + ad_off[i];
+ mdata->ad_off[i].base = mdata->mdp_base + ad_offsets[i];
+ mdata->ad_off[i].num = i;
mdata->ad_cfgs[i].num = i;
+ mdata->ad_cfgs[i].reg_sts = 0;
mdata->ad_cfgs[i].calc_itr = 0;
mdata->ad_cfgs[i].last_str = 0xFFFFFFFF;
mdata->ad_cfgs[i].last_bl = 0;
@@ -3563,8 +4401,8 @@
return ret;
}
- if (cfg->size == 0) {
- pr_err("Invalid buffer size");
+ if (cfg->size == 0 || cfg->size > PAGE_SIZE) {
+ pr_err("Invalid buffer size %d", cfg->size);
return ret;
}
diff --git a/drivers/video/msm/mdss/mdss_mdp_rotator.c b/drivers/video/msm/mdss/mdss_mdp_rotator.c
index 057914b..e2e41bb 100644
--- a/drivers/video/msm/mdss/mdss_mdp_rotator.c
+++ b/drivers/video/msm/mdss/mdss_mdp_rotator.c
@@ -437,6 +437,7 @@
rot->flags |= MDP_DEINTERLACE;
rot->src_rect.h /= 2;
rot->src_rect.y = DIV_ROUND_UP(rot->src_rect.y, 2);
+ rot->src_rect.y &= ~1;
}
rot->dst = rot->src_rect;
diff --git a/drivers/video/msm/mdss/mdss_mdp_util.c b/drivers/video/msm/mdss/mdss_mdp_util.c
index b680823..c3e1916 100644
--- a/drivers/video/msm/mdss/mdss_mdp_util.c
+++ b/drivers/video/msm/mdss/mdss_mdp_util.c
@@ -200,14 +200,20 @@
mdss_misr_crc_collect(mdata, DISPLAY_MISR_HDMI);
}
- if (isr & MDSS_MDP_INTR_WB_0_DONE)
+ if (isr & MDSS_MDP_INTR_WB_0_DONE) {
mdss_mdp_intr_done(MDP_INTR_WB_0);
+ mdss_misr_crc_collect(mdata, DISPLAY_MISR_MDP);
+ }
- if (isr & MDSS_MDP_INTR_WB_1_DONE)
+ if (isr & MDSS_MDP_INTR_WB_1_DONE) {
mdss_mdp_intr_done(MDP_INTR_WB_1);
+ mdss_misr_crc_collect(mdata, DISPLAY_MISR_MDP);
+ }
- if (isr & MDSS_MDP_INTR_WB_2_DONE)
+ if (isr & MDSS_MDP_INTR_WB_2_DONE) {
mdss_mdp_intr_done(MDP_INTR_WB_2);
+ mdss_misr_crc_collect(mdata, DISPLAY_MISR_MDP);
+ }
mdp_isr_done:
hist_isr = MDSS_MDP_REG_READ(MDSS_MDP_REG_HIST_INTR_STATUS);
diff --git a/drivers/video/msm/mdss/msm_mdss_io_8974.c b/drivers/video/msm/mdss/msm_mdss_io_8974.c
index 62704a9..a63275b 100644
--- a/drivers/video/msm/mdss/msm_mdss_io_8974.c
+++ b/drivers/video/msm/mdss/msm_mdss_io_8974.c
@@ -665,215 +665,6 @@
}
-void mdss_edp_timing_engine_ctrl(unsigned char *edp_base, int enable)
-{
- /* should eb last reg to program */
- edp_write(edp_base + 0x94, enable); /* EDP_TIMING_ENGINE_EN */
-}
-
-void mdss_edp_mainlink_ctrl(unsigned char *edp_base, int enable)
-{
- edp_write(edp_base + 0x04, enable); /* EDP_MAINLINK_CTRL */
-}
-
-void mdss_edp_mainlink_reset(unsigned char *edp_base)
-{
- edp_write(edp_base + 0x04, 0x02); /* EDP_MAINLINK_CTRL */
- usleep(1000);
- edp_write(edp_base + 0x04, 0); /* EDP_MAINLINK_CTRL */
-}
-
-void mdss_edp_aux_reset(unsigned char *edp_base)
-{
- /*reset AUX */
- edp_write(edp_base + 0x300, BIT(1)); /* EDP_AUX_CTRL */
- usleep(1000);
- edp_write(edp_base + 0x300, 0); /* EDP_AUX_CTRL */
-}
-
-void mdss_edp_aux_ctrl(unsigned char *edp_base, int enable)
-{
- u32 data;
-
- data = edp_read(edp_base + 0x300);
- if (enable)
- data |= 0x01;
- else
- data |= ~0x01;
- edp_write(edp_base + 0x300, data); /* EDP_AUX_CTRL */
-}
-
-void mdss_edp_phy_pll_reset(unsigned char *edp_base)
-{
- /* EDP_PHY_CTRL */
- edp_write(edp_base + 0x74, 0x005); /* bit 0, 2 */
- usleep(1000);
- edp_write(edp_base + 0x74, 0x000); /* EDP_PHY_CTRL */
-}
-
-int mdss_edp_phy_pll_ready(unsigned char *edp_base)
-{
- int cnt;
- u32 status;
-
- cnt = 10;
- while (cnt--) {
- status = edp_read(edp_base + 0x6c0);
- if (status & 0x01)
- break;
- usleep(100);
- }
-
- if (cnt == 0) {
- pr_err("%s: PLL NOT ready\n", __func__);
- return 0;
- } else
- return 1;
-}
-
-int mdss_edp_phy_ready(unsigned char *edp_base)
-{
- u32 status;
-
- status = edp_read(edp_base + 0x598);
- status &= 0x01;
-
- return status;
-}
-
-void mdss_edp_phy_powerup(unsigned char *edp_base, int enable)
-{
- if (enable) {
- /* EDP_PHY_EDPPHY_GLB_PD_CTL */
- edp_write(edp_base + 0x52c, 0x3f);
- /* EDP_PHY_EDPPHY_GLB_CFG */
- edp_write(edp_base + 0x528, 0x1);
- /* EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG */
- edp_write(edp_base + 0x620, 0xf);
- } else {
- /* EDP_PHY_EDPPHY_GLB_PD_CTL */
- edp_write(edp_base + 0x52c, 0xc0);
- }
-}
-
-void mdss_edp_pll_configure(unsigned char *edp_base, int rate)
-{
- if (rate == 810000000) {
- edp_write(edp_base + 0x60c, 0x18);
- edp_write(edp_base + 0x664, 0x5);
- edp_write(edp_base + 0x600, 0x0);
- edp_write(edp_base + 0x638, 0x36);
- edp_write(edp_base + 0x63c, 0x69);
- edp_write(edp_base + 0x640, 0xff);
- edp_write(edp_base + 0x644, 0x2f);
- edp_write(edp_base + 0x648, 0x0);
- edp_write(edp_base + 0x66c, 0x0a);
- edp_write(edp_base + 0x674, 0x01);
- edp_write(edp_base + 0x684, 0x5a);
- edp_write(edp_base + 0x688, 0x0);
- edp_write(edp_base + 0x68c, 0x60);
- edp_write(edp_base + 0x690, 0x0);
- edp_write(edp_base + 0x694, 0x2a);
- edp_write(edp_base + 0x698, 0x3);
- edp_write(edp_base + 0x65c, 0x10);
- edp_write(edp_base + 0x660, 0x1a);
- edp_write(edp_base + 0x604, 0x0);
- edp_write(edp_base + 0x624, 0x0);
- edp_write(edp_base + 0x628, 0x0);
-
- edp_write(edp_base + 0x620, 0x1);
- edp_write(edp_base + 0x620, 0x5);
- edp_write(edp_base + 0x620, 0x7);
- edp_write(edp_base + 0x620, 0xf);
-
- } else if (rate == 138530000) {
- edp_write(edp_base + 0x664, 0x5); /* UNIPHY_PLL_LKDET_CFG2 */
- edp_write(edp_base + 0x600, 0x1); /* UNIPHY_PLL_REFCLK_CFG */
- edp_write(edp_base + 0x638, 0x36); /* UNIPHY_PLL_SDM_CFG0 */
- edp_write(edp_base + 0x63c, 0x62); /* UNIPHY_PLL_SDM_CFG1 */
- edp_write(edp_base + 0x640, 0x0); /* UNIPHY_PLL_SDM_CFG2 */
- edp_write(edp_base + 0x644, 0x28); /* UNIPHY_PLL_SDM_CFG3 */
- edp_write(edp_base + 0x648, 0x0); /* UNIPHY_PLL_SDM_CFG4 */
- edp_write(edp_base + 0x64c, 0x80); /* UNIPHY_PLL_SSC_CFG0 */
- edp_write(edp_base + 0x650, 0x0); /* UNIPHY_PLL_SSC_CFG1 */
- edp_write(edp_base + 0x654, 0x0); /* UNIPHY_PLL_SSC_CFG2 */
- edp_write(edp_base + 0x658, 0x0); /* UNIPHY_PLL_SSC_CFG3 */
- edp_write(edp_base + 0x66c, 0xa); /* UNIPHY_PLL_CAL_CFG0 */
- edp_write(edp_base + 0x674, 0x1); /* UNIPHY_PLL_CAL_CFG2 */
- edp_write(edp_base + 0x684, 0x5a); /* UNIPHY_PLL_CAL_CFG6 */
- edp_write(edp_base + 0x688, 0x0); /* UNIPHY_PLL_CAL_CFG7 */
- edp_write(edp_base + 0x68c, 0x60); /* UNIPHY_PLL_CAL_CFG8 */
- edp_write(edp_base + 0x690, 0x0); /* UNIPHY_PLL_CAL_CFG9 */
- edp_write(edp_base + 0x694, 0x46); /* UNIPHY_PLL_CAL_CFG10 */
- edp_write(edp_base + 0x698, 0x5); /* UNIPHY_PLL_CAL_CFG11 */
- edp_write(edp_base + 0x65c, 0x10); /* UNIPHY_PLL_LKDET_CFG0 */
- edp_write(edp_base + 0x660, 0x1a); /* UNIPHY_PLL_LKDET_CFG1 */
- edp_write(edp_base + 0x604, 0x0); /* UNIPHY_PLL_POSTDIV1_CFG */
- edp_write(edp_base + 0x624, 0x0); /* UNIPHY_PLL_POSTDIV2_CFG */
- edp_write(edp_base + 0x628, 0x0); /* UNIPHY_PLL_POSTDIV3_CFG */
-
- edp_write(edp_base + 0x620, 0x1); /* UNIPHY_PLL_GLB_CFG */
- edp_write(edp_base + 0x620, 0x5); /* UNIPHY_PLL_GLB_CFG */
- edp_write(edp_base + 0x620, 0x7); /* UNIPHY_PLL_GLB_CFG */
- edp_write(edp_base + 0x620, 0xf); /* UNIPHY_PLL_GLB_CFG */
- } else {
- pr_err("%s: rate=%d is NOT supported\n", __func__, rate);
- }
-}
-
-void mdss_edp_enable_aux(unsigned char *edp_base, int enable)
-{
- if (!enable) {
- edp_write(edp_base + 0x300, 0); /* EDP_AUX_CTRL */
- return;
- }
-
- /*reset AUX */
- edp_write(edp_base + 0x300, BIT(1)); /* EDP_AUX_CTRL */
- edp_write(edp_base + 0x300, 0); /* EDP_AUX_CTRL */
-
- /* Enable AUX */
- edp_write(edp_base + 0x300, BIT(0)); /* EDP_AUX_CTRL */
-
- edp_write(edp_base + 0x550, 0x2c); /* AUX_CFG0 */
- edp_write(edp_base + 0x308, 0xffffffff); /* INTR_STATUS */
- edp_write(edp_base + 0x568, 0xff); /* INTR_MASK */
-}
-
-void mdss_edp_enable_mainlink(unsigned char *edp_base, int enable)
-{
- u32 data;
-
- data = edp_read(edp_base + 0x004);
- data &= ~BIT(0);
-
- if (enable) {
- data |= 0x1;
- edp_write(edp_base + 0x004, data);
- edp_write(edp_base + 0x004, 0x1);
- } else {
- data |= 0x0;
- edp_write(edp_base + 0x004, data);
- }
-}
-
-void mdss_edp_lane_power_ctrl(unsigned char *edp_base, int max_lane, int up)
-{
- int i, off;
- u32 data;
-
- if (up)
- data = 0; /* power up */
- else
- data = 0x7; /* power down */
-
- /* EDP_PHY_EDPPHY_LNn_PD_CTL */
- for (i = 0; i < max_lane; i++) {
- off = 0x40 * i;
- edp_write(edp_base + 0x404 + off , data);
- }
-}
-
void mdss_edp_clk_deinit(struct mdss_edp_drv_pdata *edp_drv)
{
if (edp_drv->aux_clk)
@@ -968,18 +759,18 @@
return 0;
}
- if (clk_set_rate(edp_drv->aux_clk, 19200000) < 0)
+ if (clk_set_rate(edp_drv->link_clk, edp_drv->link_rate * 27000000) < 0)
+ pr_err("%s: link_clk - clk_set_rate failed\n",
+ __func__);
+
+ if (clk_set_rate(edp_drv->aux_clk, edp_drv->aux_rate) < 0)
pr_err("%s: aux_clk - clk_set_rate failed\n",
__func__);
- if (clk_set_rate(edp_drv->pixel_clk, 138500000) < 0)
+ if (clk_set_rate(edp_drv->pixel_clk, edp_drv->pixel_rate) < 0)
pr_err("%s: pixel_clk - clk_set_rate failed\n",
__func__);
- if (clk_set_rate(edp_drv->link_clk, 270000000) < 0)
- pr_err("%s: link_clk - clk_set_rate failed\n",
- __func__);
-
ret = clk_enable(edp_drv->aux_clk);
if (ret) {
pr_err("%s: Failed to enable aux clk\n", __func__);
@@ -1034,20 +825,20 @@
{
int ret;
- ret = clk_prepare(edp_drv->aux_clk);
- if (ret) {
- pr_err("%s: Failed to prepare aux clk\n", __func__);
- goto c2;
- }
ret = clk_prepare(edp_drv->ahb_clk);
if (ret) {
pr_err("%s: Failed to prepare ahb clk\n", __func__);
goto c1;
}
+ ret = clk_prepare(edp_drv->aux_clk);
+ if (ret) {
+ pr_err("%s: Failed to prepare aux clk\n", __func__);
+ goto c2;
+ }
return 0;
c1:
- clk_unprepare(edp_drv->aux_clk);
+ clk_unprepare(edp_drv->ahb_clk);
c2:
return ret;
@@ -1063,19 +854,20 @@
{
int ret;
+ /* ahb clock should be first one to enable */
+ ret = clk_prepare(edp_drv->ahb_clk);
+ if (ret) {
+ pr_err("%s: Failed to prepare ahb clk\n", __func__);
+ goto c4;
+ }
ret = clk_prepare(edp_drv->aux_clk);
if (ret) {
pr_err("%s: Failed to prepare aux clk\n", __func__);
- goto c4;
+ goto c3;
}
ret = clk_prepare(edp_drv->pixel_clk);
if (ret) {
pr_err("%s: Failed to prepare pixel clk\n", __func__);
- goto c3;
- }
- ret = clk_prepare(edp_drv->ahb_clk);
- if (ret) {
- pr_err("%s: Failed to prepare ahb clk\n", __func__);
goto c2;
}
ret = clk_prepare(edp_drv->link_clk);
@@ -1086,11 +878,11 @@
return 0;
c1:
- clk_unprepare(edp_drv->ahb_clk);
-c2:
clk_unprepare(edp_drv->pixel_clk);
-c3:
+c2:
clk_unprepare(edp_drv->aux_clk);
+c3:
+ clk_unprepare(edp_drv->ahb_clk);
c4:
return ret;
}
@@ -1099,81 +891,27 @@
{
clk_unprepare(edp_drv->aux_clk);
clk_unprepare(edp_drv->pixel_clk);
- clk_unprepare(edp_drv->ahb_clk);
clk_unprepare(edp_drv->link_clk);
+ /* ahb clock should be last one to disable */
+ clk_unprepare(edp_drv->ahb_clk);
}
-void mdss_edp_enable_pixel_clk(unsigned char *edp_base,
- unsigned char *mmss_cc_base, int enable)
+void mdss_edp_clk_debug(unsigned char *edp_base, unsigned char *mmss_cc_base)
{
- if (!enable) {
- edp_write(mmss_cc_base + 0x032c, 0); /* CBCR */
- return;
- }
+ u32 da4, da0, d32c;
+ u32 dc4, dc0, d330;
- edp_write(edp_base + 0x624, 0x1); /* PostDiv2 */
+ /* pixel clk */
+ da0 = edp_read(mmss_cc_base + 0x0a0);
+ da4 = edp_read(mmss_cc_base + 0x0a4);
+ d32c = edp_read(mmss_cc_base + 0x32c);
- /* Configuring MND for Pixel */
- edp_write(mmss_cc_base + 0x00a8, 0x3f); /* M value */
- edp_write(mmss_cc_base + 0x00ac, 0xb); /* N value */
- edp_write(mmss_cc_base + 0x00b0, 0x0); /* D value */
+ /* main link clk */
+ dc0 = edp_read(mmss_cc_base + 0x0c0);
+ dc4 = edp_read(mmss_cc_base + 0x0c4);
+ d330 = edp_read(mmss_cc_base + 0x330);
- /* CFG RCGR */
- edp_write(mmss_cc_base + 0x00a4, (5 << 8) | (2 << 12));
- edp_write(mmss_cc_base + 0x00a0, 3); /* CMD RCGR */
+ pr_err("%s: da0=%x da4=%x d32c=%x dc0=%x dc4=%x d330=%x\n", __func__,
+ (int)da0, (int)da4, (int)d32c, (int)dc0, (int)dc4, (int)d330);
- edp_write(mmss_cc_base + 0x032c, 1); /* CBCR */
-}
-
-void mdss_edp_enable_link_clk(unsigned char *mmss_cc_base, int enable)
-{
- if (!enable) {
- edp_write(mmss_cc_base + 0x0330, 0); /* CBCR */
- return;
- }
-
- edp_write(mmss_cc_base + 0x00c4, (4 << 8)); /* CFG RCGR */
- edp_write(mmss_cc_base + 0x00c0, 3); /* CMD RCGR */
-
- edp_write(mmss_cc_base + 0x0330, 1); /* CBCR */
-}
-
-void mdss_edp_config_clk(unsigned char *edp_base, unsigned char *mmss_cc_base)
-{
- mdss_edp_enable_link_clk(mmss_cc_base, 1);
- mdss_edp_enable_pixel_clk(edp_base, mmss_cc_base, 1);
-}
-
-void mdss_edp_unconfig_clk(unsigned char *edp_base,
- unsigned char *mmss_cc_base)
-{
- mdss_edp_enable_link_clk(mmss_cc_base, 0);
- mdss_edp_enable_pixel_clk(edp_base, mmss_cc_base, 0);
-}
-
-void mdss_edp_clock_synchrous(unsigned char *edp_base, int sync)
-{
- u32 data;
-
- /* EDP_MISC1_MISC0 */
- data = edp_read(edp_base + 0x02c);
-
- if (sync)
- data |= 0x01;
- else
- data &= ~0x01;
-
- /* EDP_MISC1_MISC0 */
- edp_write(edp_base + 0x2c, data);
-}
-
-/* voltage mode and pre emphasis cfg */
-void mdss_edp_phy_vm_pe_init(unsigned char *edp_base)
-{
- /* EDP_PHY_EDPPHY_GLB_VM_CFG0 */
- edp_write(edp_base + 0x510, 0x3); /* vm only */
- /* EDP_PHY_EDPPHY_GLB_VM_CFG1 */
- edp_write(edp_base + 0x514, 0x64);
- /* EDP_PHY_EDPPHY_GLB_MISC9 */
- edp_write(edp_base + 0x518, 0x6c);
}
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
old mode 100644
new mode 100755
index f66a034..329b58e
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -325,6 +325,7 @@
header-y += ptrace.h
header-y += qnx4_fs.h
header-y += qnxtypes.h
+header-y += qrng.h
header-y += quota.h
header-y += radeonfb.h
header-y += random.h
@@ -453,3 +454,4 @@
header-y += msm_audio_amrwbplus.h
header-y += avtimer.h
header-y += msm_ipa.h
+header-y += msm_thermal_ioctl.h
diff --git a/include/linux/clockchips.h b/include/linux/clockchips.h
index 81e803e..20b8446 100644
--- a/include/linux/clockchips.h
+++ b/include/linux/clockchips.h
@@ -55,6 +55,11 @@
#define CLOCK_EVT_FEAT_C3STOP 0x000008
#define CLOCK_EVT_FEAT_DUMMY 0x000010
+/*
+ * Core shall set the interrupt affinity dynamically in broadcast mode
+ */
+#define CLOCK_EVT_FEAT_DYNIRQ 0x000020
+
/**
* struct clock_event_device - clock event device descriptor
* @event_handler: Assigned by the framework to be called by the low
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 5ab7183..6b76dfd7 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -147,7 +147,9 @@
extern void cpuidle_unregister_driver(struct cpuidle_driver *drv);
extern int cpuidle_register_device(struct cpuidle_device *dev);
extern void cpuidle_unregister_device(struct cpuidle_device *dev);
-
+extern int cpuidle_register(struct cpuidle_driver *drv,
+ const struct cpumask *const coupled_cpus);
+extern void cpuidle_unregister(struct cpuidle_driver *drv);
extern void cpuidle_pause_and_lock(void);
extern void cpuidle_resume_and_unlock(void);
extern int cpuidle_enable_device(struct cpuidle_device *dev);
@@ -168,7 +170,10 @@
static inline int cpuidle_register_device(struct cpuidle_device *dev)
{return -ENODEV; }
static inline void cpuidle_unregister_device(struct cpuidle_device *dev) { }
-
+static inline int cpuidle_register(struct cpuidle_driver *drv,
+ const struct cpumask *const coupled_cpus)
+{return -ENODEV; }
+static inline void cpuidle_unregister(struct cpuidle_driver *drv) { }
static inline void cpuidle_pause_and_lock(void) { }
static inline void cpuidle_resume_and_unlock(void) { }
static inline int cpuidle_enable_device(struct cpuidle_device *dev)
diff --git a/include/linux/dma-contiguous.h b/include/linux/dma-contiguous.h
index 8a1b3a1..78e57cd 100644
--- a/include/linux/dma-contiguous.h
+++ b/include/linux/dma-contiguous.h
@@ -65,6 +65,9 @@
*/
#define MAX_CMA_AREAS (1 + CONFIG_CMA_AREAS)
+
+phys_addr_t cma_get_base(struct device *dev);
+
extern struct cma *dma_contiguous_def_area;
void dma_contiguous_reserve(phys_addr_t addr_limit);
@@ -129,6 +132,12 @@
return false;
}
+
+static inline phys_addr_t cma_get_base(struct device *dev)
+{
+ return 0;
+}
+
#endif
#endif
diff --git a/include/linux/input.h b/include/linux/input.h
index d4cdb02..558178b 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -167,6 +167,7 @@
#define INPUT_PROP_DIRECT 0x01 /* direct input devices */
#define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */
#define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */
+#define INPUT_PROP_NO_DUMMY_RELEASE 0x04 /* no dummy event */
#define INPUT_PROP_MAX 0x1f
#define INPUT_PROP_CNT (INPUT_PROP_MAX + 1)
diff --git a/include/linux/kref.h b/include/linux/kref.h
index aa5acc26..6f515f2 100644
--- a/include/linux/kref.h
+++ b/include/linux/kref.h
@@ -18,6 +18,7 @@
#include <linux/bug.h>
#include <linux/atomic.h>
#include <linux/kernel.h>
+#include <linux/mutex.h>
struct kref {
atomic_t refcount;
@@ -94,6 +95,23 @@
return kref_sub(kref, 1, release);
}
+static inline int kref_put_mutex(struct kref *kref,
+ void (*release)(struct kref *kref),
+ struct mutex *lock)
+{
+ WARN_ON(release == NULL);
+ if (unlikely(!atomic_add_unless(&kref->refcount, -1, 1))) {
+ mutex_lock(lock);
+ if (unlikely(!atomic_dec_and_test(&kref->refcount))) {
+ mutex_unlock(lock);
+ return 0;
+ }
+ release(kref);
+ return 1;
+ }
+ return 0;
+}
+
/**
* kref_get_unless_zero - Increment refcount for object unless it is zero.
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index 1bcfd28..43aebb5 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -392,7 +392,7 @@
unsigned int idle_timeout;
struct notifier_block reboot_notify;
bool issue_long_pon;
- u8 cached_ext_csd;
+ u8 *cached_ext_csd;
};
/*
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index e1dbd21..bff056d 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -300,6 +300,7 @@
#define MMC_CAP2_HS400_1_8V (1 << 21) /* can support */
#define MMC_CAP2_HS400_1_2V (1 << 22) /* can support */
+#define MMC_CAP2_CORE_PM (1 << 23) /* use PM framework */
#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \
MMC_CAP2_HS400_1_2V)
mmc_pm_flag_t pm_caps; /* supported pm features */
@@ -572,4 +573,9 @@
return host->caps2 & MMC_CAP2_CORE_RUNTIME_PM;
}
+static inline int mmc_use_core_pm(struct mmc_host *host)
+{
+ return host->caps2 & MMC_CAP2_CORE_PM;
+}
+
#endif /* LINUX_MMC_HOST_H */
diff --git a/include/linux/msm_adreno_devfreq.h b/include/linux/msm_adreno_devfreq.h
index a84d14c..53d7085 100644
--- a/include/linux/msm_adreno_devfreq.h
+++ b/include/linux/msm_adreno_devfreq.h
@@ -16,12 +16,31 @@
/* same as KGSL_MAX_PWRLEVELS */
#define MSM_ADRENO_MAX_PWRLEVELS 10
+struct xstats {
+ u64 ram_time;
+ u64 ram_wait;
+ int mod;
+};
+
struct devfreq_msm_adreno_tz_data {
struct notifier_block nb;
struct {
s64 total_time;
s64 busy_time;
} bin;
+ struct {
+ u64 total_time;
+ u64 ram_time;
+ u64 gpu_time;
+ u32 num;
+ u32 max;
+ u32 up[MSM_ADRENO_MAX_PWRLEVELS];
+ u32 down[MSM_ADRENO_MAX_PWRLEVELS];
+ u32 p_up[MSM_ADRENO_MAX_PWRLEVELS];
+ u32 p_down[MSM_ADRENO_MAX_PWRLEVELS];
+ unsigned int *index;
+ uint64_t *ib;
+ } bus;
unsigned int device_id;
};
diff --git a/include/linux/msm_audio_acdb.h b/include/linux/msm_audio_acdb.h
index 853899e..8912dc9 100644
--- a/include/linux/msm_audio_acdb.h
+++ b/include/linux/msm_audio_acdb.h
@@ -126,6 +126,8 @@
(AUDIO_MAX_ACDB_IOCTL+9), unsigned)
#define AUDIO_SET_RTAC_CVP_CAL _IOWR(AUDIO_IOCTL_MAGIC, \
(AUDIO_MAX_ACDB_IOCTL+10), unsigned)
+#define AUDIO_GET_RTAC_ADM_INFO_V2 _IOWR(AUDIO_IOCTL_MAGIC, \
+ (AUDIO_MAX_ACDB_IOCTL+11), unsigned)
#define AUDIO_MAX_RTAC_IOCTL (AUDIO_MAX_ACDB_IOCTL+20)
diff --git a/include/linux/msm_ion.h b/include/linux/msm_ion.h
index 3976699..0127edc 100644
--- a/include/linux/msm_ion.h
+++ b/include/linux/msm_ion.h
@@ -197,6 +197,14 @@
enum ion_memory_types memory_type;
};
+/*
+ * struct ion_cma_pdata - extra data for CMA regions
+ * @default_prefetch_size - default size to use for prefetching
+ */
+struct ion_cma_pdata {
+ unsigned long default_prefetch_size;
+};
+
#ifdef CONFIG_ION
/**
* msm_ion_client_create - allocate a client using the ion_device specified in
@@ -504,6 +512,11 @@
unsigned int length;
};
+struct ion_prefetch_data {
+ int heap_id;
+ unsigned long len;
+};
+
#define ION_IOC_MSM_MAGIC 'M'
/**
@@ -528,4 +541,10 @@
#define ION_IOC_CLEAN_INV_CACHES _IOWR(ION_IOC_MSM_MAGIC, 2, \
struct ion_flush_data)
+#define ION_IOC_PREFETCH _IOWR(ION_IOC_MSM_MAGIC, 3, \
+ struct ion_prefetch_data)
+
+#define ION_IOC_DRAIN _IOWR(ION_IOC_MSM_MAGIC, 4, \
+ struct ion_prefetch_data)
+
#endif
diff --git a/include/linux/msm_mdp.h b/include/linux/msm_mdp.h
index 3425386..724e573 100644
--- a/include/linux/msm_mdp.h
+++ b/include/linux/msm_mdp.h
@@ -320,6 +320,27 @@
#define MDP_PP_IGC_FLAG_ROM0 0x10
#define MDP_PP_IGC_FLAG_ROM1 0x20
+#define MDP_PP_PA_HUE_ENABLE 0x10
+#define MDP_PP_PA_SAT_ENABLE 0x20
+#define MDP_PP_PA_VAL_ENABLE 0x40
+#define MDP_PP_PA_CONT_ENABLE 0x80
+#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100
+#define MDP_PP_PA_SKIN_ENABLE 0x200
+#define MDP_PP_PA_SKY_ENABLE 0x400
+#define MDP_PP_PA_FOL_ENABLE 0x800
+#define MDP_PP_PA_HUE_MASK 0x1000
+#define MDP_PP_PA_SAT_MASK 0x2000
+#define MDP_PP_PA_VAL_MASK 0x4000
+#define MDP_PP_PA_CONT_MASK 0x8000
+#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000
+#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000
+#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000
+#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000
+#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000
+#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000
+#define MDP_PP_PA_MEM_PROTECT_EN 0x400000
+#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000
+
#define MDSS_PP_DSPP_CFG 0x000
#define MDSS_PP_SSPP_CFG 0x100
#define MDSS_PP_LM_CFG 0x200
@@ -364,6 +385,7 @@
#define MDP_OVERLAY_PP_SHARP_CFG 0x10
#define MDP_OVERLAY_PP_HIST_CFG 0x20
#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40
+#define MDP_OVERLAY_PP_PA_V2_CFG 0x80
#define MDP_CSC_FLAG_ENABLE 0x1
#define MDP_CSC_FLAG_YUV_IN 0x2
@@ -392,6 +414,31 @@
uint32_t cont_adj;
};
+struct mdp_pa_mem_col_cfg {
+ uint32_t color_adjust_p0;
+ uint32_t color_adjust_p1;
+ uint32_t hue_region;
+ uint32_t sat_region;
+ uint32_t val_region;
+};
+
+#define MDP_SIX_ZONE_TABLE_NUM 384
+
+struct mdp_pa_v2_data {
+ /* Mask bits for PA features */
+ uint32_t flags;
+ uint32_t global_hue_adj;
+ uint32_t global_sat_adj;
+ uint32_t global_val_adj;
+ uint32_t global_cont_adj;
+ uint32_t *six_zone_curve_p0;
+ uint32_t *six_zone_curve_p1;
+ uint32_t six_zone_thresh;
+ struct mdp_pa_mem_col_cfg skin_cfg;
+ struct mdp_pa_mem_col_cfg sky_cfg;
+ struct mdp_pa_mem_col_cfg fol_cfg;
+};
+
struct mdp_igc_lut_data {
uint32_t block;
uint32_t len, ops;
@@ -419,6 +466,7 @@
struct mdp_csc_cfg csc_cfg;
struct mdp_qseed_cfg qseed_cfg[2];
struct mdp_pa_cfg pa_cfg;
+ struct mdp_pa_v2_data pa_v2_cfg;
struct mdp_igc_lut_data igc_cfg;
struct mdp_sharp_cfg sharp_cfg;
struct mdp_histogram_cfg hist_cfg;
@@ -479,6 +527,50 @@
uint32_t roi_w[MAX_PLANES];
};
+/**
+ * struct mdp_overlay - overlay surface structure
+ * @src: Source image information (width, height, format).
+ * @src_rect: Source crop rectangle, portion of image that will be fetched.
+ * This should always be within boundaries of source image.
+ * @dst_rect: Destination rectangle, the position and size of image on screen.
+ * This should always be within panel boundaries.
+ * @z_order: Blending stage to occupy in display, if multiple layers are
+ * present, highest z_order usually means the top most visible
+ * layer. The range acceptable is from 0-3 to support blending
+ * up to 4 layers.
+ * @is_fg: This flag is used to disable blending of any layers with z_order
+ * less than this overlay. It means that any layers with z_order
+ * less than this layer will not be blended and will be replaced
+ * by the background border color.
+ * @alpha: Used to set plane opacity. The range can be from 0-255, where
+ * 0 means completely transparent and 255 means fully opaque.
+ * @transp_mask: Color used as color key for transparency. Any pixel in fetched
+ * image matching this color will be transparent when blending.
+ * The color should be in same format as the source image format.
+ * @flags: This is used to customize operation of overlay. See MDP flags
+ * for more information.
+ * @user_data: DEPRECATED* Used to store user application specific information.
+ * @bg_color: Solid color used to fill the overlay surface when no source
+ * buffer is provided.
+ * @horz_deci: Horizontal decimation value, this indicates the amount of pixels
+ * dropped for each pixel that is fetched from a line. The value
+ * given should be power of two of decimation amount.
+ * 0: no decimation
+ * 1: decimate by 2 (drop 1 pixel for each pixel fetched)
+ * 2: decimate by 4 (drop 3 pixels for each pixel fetched)
+ * 3: decimate by 8 (drop 7 pixels for each pixel fetched)
+ * 4: decimate by 16 (drop 15 pixels for each pixel fetched)
+ * @vert_deci: Vertical decimation value, this indicates the amount of lines
+ * dropped for each line that is fetched from overlay. The value
+ * given should be power of two of decimation amount.
+ * 0: no decimation
+ * 1: decimation by 2 (drop 1 line for each line fetched)
+ * 2: decimation by 4 (drop 3 lines for each line fetched)
+ * 3: decimation by 8 (drop 7 lines for each line fetched)
+ * 4: decimation by 16 (drop 15 lines for each line fetched)
+ * @overlay_pp_cfg: Overlay post processing configuration, for more information
+ * see struct mdp_overlay_pp_params.
+ */
struct mdp_overlay {
struct msmfb_img src;
struct mdp_rect src_rect;
@@ -490,7 +582,8 @@
uint32_t transp_mask;
uint32_t flags;
uint32_t id;
- uint32_t user_data[7];
+ uint32_t user_data[6];
+ uint32_t bg_color;
uint8_t horz_deci;
uint8_t vert_deci;
struct mdp_overlay_pp_params overlay_pp_cfg;
@@ -520,19 +613,21 @@
uint32_t *b;
};
+#define MISR_CRC_BATCH_SIZE 32
enum {
- DISPLAY_MISR_EDP,
+ DISPLAY_MISR_EDP = 0,
DISPLAY_MISR_DSI0,
DISPLAY_MISR_DSI1,
DISPLAY_MISR_HDMI,
DISPLAY_MISR_LCDC,
+ DISPLAY_MISR_MDP,
DISPLAY_MISR_ATV,
DISPLAY_MISR_DSI_CMD,
DISPLAY_MISR_MAX
};
enum {
- MISR_OP_NONE,
+ MISR_OP_NONE = 0,
MISR_OP_SFM,
MISR_OP_MFM,
MISR_OP_BM,
@@ -543,7 +638,7 @@
uint32_t block_id;
uint32_t frame_count;
uint32_t crc_op_mode;
- uint32_t crc_value[32];
+ uint32_t crc_value[MISR_CRC_BATCH_SIZE];
};
/*
@@ -659,6 +754,11 @@
struct mdp_pa_cfg pa_data;
};
+struct mdp_pa_v2_cfg_data {
+ uint32_t block;
+ struct mdp_pa_v2_data pa_v2_data;
+};
+
struct mdp_dither_cfg_data {
uint32_t block;
uint32_t flags;
@@ -703,7 +803,7 @@
};
#define MDSS_MAX_BL_BRIGHTNESS 255
-#define AD_BL_LIN_LEN (MDSS_MAX_BL_BRIGHTNESS + 1)
+#define AD_BL_LIN_LEN 256
#define MDSS_AD_MODE_AUTO_BL 0x0
#define MDSS_AD_MODE_AUTO_STR 0x1
@@ -787,6 +887,7 @@
mdp_op_qseed_cfg,
mdp_bl_scale_cfg,
mdp_op_pa_cfg,
+ mdp_op_pa_v2_cfg,
mdp_op_dither_cfg,
mdp_op_gamut_cfg,
mdp_op_calib_cfg,
@@ -818,6 +919,7 @@
struct mdp_qseed_cfg_data qseed_cfg_data;
struct mdp_bl_scale_data bl_scale_data;
struct mdp_pa_cfg_data pa_cfg_data;
+ struct mdp_pa_v2_cfg_data pa_v2_cfg_data;
struct mdp_dither_cfg_data dither_cfg_data;
struct mdp_gamut_cfg_data gamut_cfg_data;
struct mdp_calib_config_data calib_cfg;
diff --git a/include/linux/msm_thermal.h b/include/linux/msm_thermal.h
index 2ca9900..25b5363 100644
--- a/include/linux/msm_thermal.h
+++ b/include/linux/msm_thermal.h
@@ -19,22 +19,30 @@
uint32_t poll_ms;
int32_t limit_temp_degC;
int32_t temp_hysteresis_degC;
- uint32_t freq_step;
- uint32_t freq_control_mask;
+ uint32_t bootup_freq_step;
+ uint32_t bootup_freq_control_mask;
int32_t core_limit_temp_degC;
int32_t core_temp_hysteresis_degC;
int32_t hotplug_temp_degC;
int32_t hotplug_temp_hysteresis_degC;
uint32_t core_control_mask;
+ uint32_t freq_mitig_temp_degc;
+ uint32_t freq_mitig_temp_hysteresis_degc;
+ uint32_t freq_mitig_control_mask;
+ uint32_t freq_limit;
int32_t vdd_rstr_temp_degC;
int32_t vdd_rstr_temp_hyst_degC;
int32_t psm_temp_degC;
int32_t psm_temp_hyst_degC;
+ int32_t ocr_temp_degC;
+ int32_t ocr_temp_hyst_degC;
};
#ifdef CONFIG_THERMAL_MONITOR
extern int msm_thermal_init(struct msm_thermal_data *pdata);
extern int msm_thermal_device_init(void);
+extern int msm_thermal_set_frequency(uint32_t cpu, uint32_t freq,
+ bool is_max);
#else
static inline int msm_thermal_init(struct msm_thermal_data *pdata)
{
@@ -44,6 +52,11 @@
{
return -ENOSYS;
}
+static inline int msm_thermal_set_frequency(uint32_t cpu, uint32_t freq,
+ bool is_max)
+{
+ return -ENOSYS;
+}
#endif
#endif /*__MSM_THERMAL_H*/
diff --git a/include/linux/msm_thermal_ioctl.h b/include/linux/msm_thermal_ioctl.h
new file mode 100644
index 0000000..7b36493
--- /dev/null
+++ b/include/linux/msm_thermal_ioctl.h
@@ -0,0 +1,41 @@
+#ifndef _MSM_THERMAL_IOCTL_H
+#define _MSM_THERMAL_IOCTL_H
+
+#include <linux/ioctl.h>
+
+#define MSM_THERMAL_IOCTL_NAME "msm_thermal_query"
+
+struct __attribute__((__packed__)) cpu_freq_arg {
+ uint32_t cpu_num;
+ uint32_t freq_req;
+};
+
+struct __attribute__((__packed__)) msm_thermal_ioctl {
+ uint32_t size;
+ union {
+ struct cpu_freq_arg cpu_freq;
+ };
+};
+
+enum {
+ /*Set CPU Frequency*/
+ MSM_SET_CPU_MAX_FREQ = 0x00,
+ MSM_SET_CPU_MIN_FREQ = 0x01,
+
+ MSM_CMD_MAX_NR,
+};
+
+#define MSM_THERMAL_MAGIC_NUM 0xCA /*Unique magic number*/
+
+#define MSM_THERMAL_SET_CPU_MAX_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\
+ MSM_SET_CPU_MAX_FREQ, struct msm_thermal_ioctl)
+
+#define MSM_THERMAL_SET_CPU_MIN_FREQUENCY _IOW(MSM_THERMAL_MAGIC_NUM,\
+ MSM_SET_CPU_MIN_FREQ, struct msm_thermal_ioctl)
+
+#ifdef __KERNEL__
+extern int msm_thermal_ioctl_init(void);
+extern void msm_thermal_ioctl_cleanup(void);
+#endif
+
+#endif
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index 22b004e..0065203 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -105,6 +105,7 @@
POWER_SUPPLY_PROP_CURRENT_MAX,
POWER_SUPPLY_PROP_INPUT_CURRENT_MAX,
POWER_SUPPLY_PROP_INPUT_CURRENT_TRIM,
+ POWER_SUPPLY_PROP_INPUT_CURRENT_SETTLED,
POWER_SUPPLY_PROP_CURRENT_NOW,
POWER_SUPPLY_PROP_CURRENT_AVG,
POWER_SUPPLY_PROP_POWER_NOW,
diff --git a/include/linux/qrng.h b/include/linux/qrng.h
new file mode 100644
index 0000000..35708e3
--- /dev/null
+++ b/include/linux/qrng.h
@@ -0,0 +1,12 @@
+#ifndef __QRNG_H_
+#define __QRNG_H_
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define QRNG_IOC_MAGIC 0x100
+
+#define QRNG_IOCTL_RESET_BUS_BANDWIDTH\
+ _IO(QRNG_IOC_MAGIC, 1)
+
+#endif /* __QRNG_H_ */
diff --git a/include/linux/qseecom.h b/include/linux/qseecom.h
index 6d2db8f3..a45c34c 100644
--- a/include/linux/qseecom.h
+++ b/include/linux/qseecom.h
@@ -163,6 +163,13 @@
QSEOS_UNPROTECT_PROTECTED_BUFFER,
};
+enum qseecom_bandwidth_request_mode {
+ INACTIVE = 0,
+ LOW,
+ MEDIUM,
+ HIGH,
+};
+
/*
* struct qseecom_send_modfd_resp - for send command ioctl request
* @req_len - command buffer length
@@ -177,7 +184,6 @@
enum qseecom_buffer_protection protection_mode; /* in */
};
-
#define QSEECOM_IOC_MAGIC 0x97
@@ -246,4 +252,8 @@
#define QSEECOM_IOCTL_UNPROTECT_BUF \
_IOWR(QSEECOM_IOC_MAGIC, 22, int)
+
+#define QSEECOM_IOCTL_SET_BUS_SCALING_REQ \
+ _IOWR(QSEECOM_IOC_MAGIC, 23, int)
+
#endif /* __QSEECOM_H_ */
diff --git a/include/linux/regulator/cpr-regulator.h b/include/linux/regulator/cpr-regulator.h
index 6387913..624860e 100644
--- a/include/linux/regulator/cpr-regulator.h
+++ b/include/linux/regulator/cpr-regulator.h
@@ -16,7 +16,7 @@
#include <linux/regulator/machine.h>
-#define CPR_REGULATOR_DRIVER_NAME "qcom,cpr-regulator"
+#define CPR_REGULATOR_DRIVER_NAME "qti,cpr-regulator"
#define CPR_PVS_EFUSE_BITS_MAX 5
#define CPR_PVS_EFUSE_BINS_MAX (1 << CPR_PVS_EFUSE_BITS_MAX)
diff --git a/include/linux/sensors.h b/include/linux/sensors.h
new file mode 100644
index 0000000..3520034
--- /dev/null
+++ b/include/linux/sensors.h
@@ -0,0 +1,70 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_SENSORS_H_INCLUDED
+#define __LINUX_SENSORS_H_INCLUDED
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/rwsem.h>
+
+#define SENSORS_ACCELERATION_HANDLE 0
+#define SENSORS_MAGNETIC_FIELD_HANDLE 1
+#define SENSORS_ORIENTATION_HANDLE 2
+#define SENSORS_LIGHT_HANDLE 3
+#define SENSORS_PROXIMITY_HANDLE 4
+#define SENSORS_GYROSCOPE_HANDLE 5
+#define SENSORS_PRESSURE_HANDLE 6
+
+#define SENSOR_TYPE_ACCELEROMETER 1
+#define SENSOR_TYPE_GEOMAGNETIC_FIELD 2
+#define SENSOR_TYPE_MAGNETIC_FIELD SENSOR_TYPE_GEOMAGNETIC_FIELD
+#define SENSOR_TYPE_ORIENTATION 3
+#define SENSOR_TYPE_GYROSCOPE 4
+#define SENSOR_TYPE_LIGHT 5
+#define SENSOR_TYPE_PRESSURE 6
+#define SENSOR_TYPE_TEMPERATURE 7
+#define SENSOR_TYPE_PROXIMITY 8
+#define SENSOR_TYPE_GRAVITY 9
+#define SENSOR_TYPE_LINEAR_ACCELERATION 10
+#define SENSOR_TYPE_ROTATION_VECTOR 11
+#define SENSOR_TYPE_RELATIVE_HUMIDITY 12
+#define SENSOR_TYPE_AMBIENT_TEMPERATURE 13
+#define SENSOR_TYPE_MAGNETIC_FIELD_UNCALIBRATED 14
+#define SENSOR_TYPE_GAME_ROTATION_VECTOR 15
+#define SENSOR_TYPE_GYROSCOPE_UNCALIBRATED 16
+#define SENSOR_TYPE_SIGNIFICANT_MOTION 17
+#define SENSOR_TYPE_STEP_DETECTOR 18
+#define SENSOR_TYPE_STEP_COUNTER 19
+#define SENSOR_TYPE_GEOMAGNETIC_ROTATION_VECTOR 20
+
+struct sensors_classdev {
+ struct device *dev;
+ struct list_head node;
+ const char *name;
+ const char *vendor;
+ int version;
+ int handle;
+ int type;
+ const char *max_range;
+ const char *resolution;
+ const char *sensor_power;
+ int min_delay;
+ int fifo_reserved_event_count;
+ int fifo_max_event_count;
+};
+
+extern int sensors_classdev_register(struct device *parent,
+ struct sensors_classdev *sensors_cdev);
+extern void sensors_classdev_unregister(struct sensors_classdev *sensors_cdev);
+
+#endif /* __LINUX_SENSORS_H_INCLUDED */
diff --git a/include/linux/slimbus/slimbus.h b/include/linux/slimbus/slimbus.h
index cba4394..c940091 100644
--- a/include/linux/slimbus/slimbus.h
+++ b/include/linux/slimbus/slimbus.h
@@ -1077,7 +1077,7 @@
extern int slim_register_board_info(struct slim_boardinfo const *info,
unsigned n);
#else
-int slim_register_board_info(struct slim_boardinfo const *info,
+static inline int slim_register_board_info(struct slim_boardinfo const *info,
unsigned n)
{
return 0;
diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index ed6d41b..faf98fe 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -102,6 +102,7 @@
enum thermal_trip_type trip;
int (*notify)(enum thermal_trip_type type, int temp, void *data);
void *data;
+ uint8_t active;
struct list_head list;
};
@@ -189,6 +190,8 @@
int sensor_get_id(char *name);
int sensor_set_trip(uint32_t sensor_id, struct sensor_threshold *threshold);
int sensor_cancel_trip(uint32_t sensor_id, struct sensor_threshold *threshold);
+int sensor_activate_trip(uint32_t sensor_id, struct sensor_threshold *threshold,
+ bool enable);
int thermal_sensor_trip(struct thermal_zone_device *tz,
enum thermal_trip_type trip, long temp);
diff --git a/include/linux/tick.h b/include/linux/tick.h
index 494a314..dc15221 100644
--- a/include/linux/tick.h
+++ b/include/linux/tick.h
@@ -8,6 +8,7 @@
#include <linux/clockchips.h>
#include <linux/irqflags.h>
+#include <linux/hrtimer.h>
#ifdef CONFIG_GENERIC_CLOCKEVENTS
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 9eb9cd8..045a58b 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -232,6 +232,8 @@
* connected on data lines or not.
* @enable_ahb2ahb_bypass: Indicates whether enable AHB2AHB BYPASS
* mode with controller in device mode.
+ * @disable_retention_with_vdd_min: Indicates whether to enable allowing
+ * VDD min without putting PHY into retention
*/
struct msm_otg_platform_data {
int *phy_init_seq;
@@ -261,6 +263,7 @@
bool l1_supported;
bool dpdm_pulldown_added;
bool enable_ahb2ahb_bypass;
+ bool disable_retention_with_vdd_min;
};
/* phy related flags */
@@ -427,6 +430,11 @@
* voltage regulator(VDDCX) during host mode.
*/
#define ALLOW_HOST_PHY_RETENTION BIT(4)
+ /*
+ * Allow VDD minimization without putting PHY into retention
+ * for fixing PHY current leakage issue when LDOs are turned off.
+ */
+#define ALLOW_VDD_MIN_WITH_RETENTION_DISABLED BIT(5)
unsigned long lpm_flags;
#define PHY_PWR_COLLAPSED BIT(0)
#define PHY_RETENTIONED BIT(1)
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 560accb..bfafe00 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -1904,6 +1904,9 @@
V4L2_CID_MPEG_VIDC_VIDEO_STREAM_OUTPUT_SECONDARY = 1,
};
+#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MIN_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 36)
+#define V4L2_CID_MPEG_VIDC_VIDEO_VP8_MAX_QP (V4L2_CID_MPEG_MSM_VIDC_BASE + 37)
+
/* Camera class control IDs */
#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900)
#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1)
diff --git a/include/media/msm_cam_sensor.h b/include/media/msm_cam_sensor.h
index cccf851..c48586e 100644
--- a/include/media/msm_cam_sensor.h
+++ b/include/media/msm_cam_sensor.h
@@ -571,6 +571,7 @@
struct msm_camera_led_cfg_t {
enum msm_camera_led_config_t cfgtype;
+ uint32_t led_current;
};
#define VIDIOC_MSM_SENSOR_CFG \
diff --git a/include/media/msm_jpeg.h b/include/media/msm_jpeg.h
index 56829f1..99f0de0 100644
--- a/include/media/msm_jpeg.h
+++ b/include/media/msm_jpeg.h
@@ -55,6 +55,9 @@
#define MSM_JPEG_IOCTL_TEST_DUMP_REGION \
_IOW(MSM_JPEG_IOCTL_MAGIC, 15, unsigned long)
+#define MSM_JPEG_IOCTL_SET_CLK_RATE \
+ _IOW(MSM_JPEG_IOCTL_MAGIC, 16, unsigned long)
+
#define MSM_JPEG_MODE_REALTIME_ENCODE 0
#define MSM_JPEG_MODE_OFFLINE_ENCODE 1
#define MSM_JPEG_MODE_REALTIME_ROTATION 2
diff --git a/include/media/msm_vidc.h b/include/media/msm_vidc.h
index 868be9f..bc85ebb 100644
--- a/include/media/msm_vidc.h
+++ b/include/media/msm_vidc.h
@@ -18,6 +18,41 @@
MSM_VIDC_MAX_DEVICES,
};
+/* NOTE: if you change this enum you MUST update the
+ * "buffer-type-tz-usage-table" for any affected target
+ * in arch/arm/boot/dts/<arch>.dtsi
+ */
+enum hal_buffer {
+ HAL_BUFFER_INPUT = 0x1,
+ HAL_BUFFER_OUTPUT = 0x2,
+ HAL_BUFFER_OUTPUT2 = 0x4,
+ HAL_BUFFER_EXTRADATA_INPUT = 0x8,
+ HAL_BUFFER_EXTRADATA_OUTPUT = 0x10,
+ HAL_BUFFER_EXTRADATA_OUTPUT2 = 0x20,
+ HAL_BUFFER_INTERNAL_SCRATCH = 0x40,
+ HAL_BUFFER_INTERNAL_SCRATCH_1 = 0x80,
+ HAL_BUFFER_INTERNAL_SCRATCH_2 = 0x100,
+ HAL_BUFFER_INTERNAL_PERSIST = 0x200,
+ HAL_BUFFER_INTERNAL_PERSIST_1 = 0x400,
+ HAL_BUFFER_INTERNAL_CMD_QUEUE = 0x800,
+};
+
+struct msm_smem {
+ int mem_type;
+ size_t size;
+ void *kvaddr;
+ unsigned long device_addr;
+ u32 flags;
+ void *smem_priv;
+ enum hal_buffer buffer_type;
+};
+
+enum smem_cache_ops {
+ SMEM_CACHE_CLEAN,
+ SMEM_CACHE_INVALIDATE,
+ SMEM_CACHE_CLEAN_INVALIDATE,
+};
+
void *msm_vidc_open(int core_id, int session_type);
int msm_vidc_close(void *instance);
int msm_vidc_querycap(void *instance, struct v4l2_capability *cap);
@@ -47,6 +82,18 @@
int msm_vidc_wait(void *instance);
int msm_vidc_s_parm(void *instance, struct v4l2_streamparm *a);
int msm_vidc_enum_framesizes(void *instance, struct v4l2_frmsizeenum *fsize);
+struct msm_smem *msm_vidc_smem_alloc(void *instance,
+ size_t size, u32 align, u32 flags,
+ enum hal_buffer buffer_type, int map_kernel);
+void msm_vidc_smem_free(void *instance, struct msm_smem *mem);
+int msm_vidc_smem_cache_operations(void *instance,
+ struct msm_smem *mem, enum smem_cache_ops);
+struct msm_smem *msm_vidc_smem_user_to_kernel(void *instance,
+ int fd, u32 offset, enum hal_buffer buffer_type);
+int msm_vidc_smem_get_domain_partition(void *instance,
+ u32 flags, enum hal_buffer buffer_type,
+ int *domain_num, int *partition_num);
+void *msm_vidc_smem_get_client(void *instance);
#endif
struct msm_vidc_interlace_payload {
unsigned int format;
@@ -93,6 +140,27 @@
unsigned int num_panscan_windows;
struct msm_vidc_panscan_window wnd[1];
};
+struct msm_vidc_s3d_frame_packing_payload {
+ unsigned int fpa_id;
+ unsigned int cancel_flag;
+ unsigned int fpa_type;
+ unsigned int quin_cunx_flag;
+ unsigned int content_interprtation_type;
+ unsigned int spatial_flipping_flag;
+ unsigned int frame0_flipped_flag;
+ unsigned int field_views_flag;
+ unsigned int current_frame_is_frame0_flag;
+ unsigned int frame0_self_contained_flag;
+ unsigned int frame1_self_contained_flag;
+ unsigned int frame0_graid_pos_x;
+ unsigned int frame0_graid_pos_y;
+ unsigned int frame1_graid_pos_x;
+ unsigned int frame1_graid_pos_y;
+ unsigned int fpa_reserved_byte;
+ unsigned int fpa_repetition_period;
+ unsigned int fpa_extension_flag;
+};
+
enum msm_vidc_extradata_type {
EXTRADATA_NONE = 0x00000000,
EXTRADATA_MB_QUANTIZATION = 0x00000001,
diff --git a/include/media/msmb_isp.h b/include/media/msmb_isp.h
index 7b0ad14..568a3fa 100644
--- a/include/media/msmb_isp.h
+++ b/include/media/msmb_isp.h
@@ -152,6 +152,7 @@
enum msm_vfe_axi_stream_cmd {
STOP_STREAM,
START_STREAM,
+ STOP_IMMEDIATELY,
};
struct msm_vfe_axi_stream_cfg_cmd {
diff --git a/include/sound/apr_audio-v2.h b/include/sound/apr_audio-v2.h
index b62a759..2c969cd 100644
--- a/include/sound/apr_audio-v2.h
+++ b/include/sound/apr_audio-v2.h
@@ -6279,6 +6279,206 @@
#define VOICE_CMD_GET_PARAM 0x0001133E
#define VOICE_EVT_GET_PARAM_ACK 0x00011008
+
+/** ID of the Bass Boost module.
+ This module supports the following parameter IDs:
+ - #AUDPROC_PARAM_ID_BASS_BOOST_ENABLE
+ - #AUDPROC_PARAM_ID_BASS_BOOST_MODE
+ - #AUDPROC_PARAM_ID_BASS_BOOST_STRENGTH
+*/
+#define AUDPROC_MODULE_ID_BASS_BOOST 0x000108A1
+/** ID of the Bass Boost enable parameter used by
+ AUDPROC_MODULE_ID_BASS_BOOST.
+*/
+#define AUDPROC_PARAM_ID_BASS_BOOST_ENABLE 0x000108A2
+/** ID of the Bass Boost mode parameter used by
+ AUDPROC_MODULE_ID_BASS_BOOST.
+*/
+#define AUDPROC_PARAM_ID_BASS_BOOST_MODE 0x000108A3
+/** ID of the Bass Boost strength parameter used by
+ AUDPROC_MODULE_ID_BASS_BOOST.
+*/
+#define AUDPROC_PARAM_ID_BASS_BOOST_STRENGTH 0x000108A4
+
+/** ID of the Virtualizer module. This module supports the
+ following parameter IDs:
+ - #AUDPROC_PARAM_ID_VIRTUALIZER_ENABLE
+ - #AUDPROC_PARAM_ID_VIRTUALIZER_STRENGTH
+ - #AUDPROC_PARAM_ID_VIRTUALIZER_OUT_TYPE
+ - #AUDPROC_PARAM_ID_VIRTUALIZER_GAIN_ADJUST
+*/
+#define AUDPROC_MODULE_ID_VIRTUALIZER 0x000108A5
+/** ID of the Virtualizer enable parameter used by
+ AUDPROC_MODULE_ID_VIRTUALIZER.
+*/
+#define AUDPROC_PARAM_ID_VIRTUALIZER_ENABLE 0x000108A6
+/** ID of the Virtualizer strength parameter used by
+ AUDPROC_MODULE_ID_VIRTUALIZER.
+*/
+#define AUDPROC_PARAM_ID_VIRTUALIZER_STRENGTH 0x000108A7
+/** ID of the Virtualizer out type parameter used by
+ AUDPROC_MODULE_ID_VIRTUALIZER.
+*/
+#define AUDPROC_PARAM_ID_VIRTUALIZER_OUT_TYPE 0x000108A8
+/** ID of the Virtualizer out type parameter used by
+ AUDPROC_MODULE_ID_VIRTUALIZER.
+*/
+#define AUDPROC_PARAM_ID_VIRTUALIZER_GAIN_ADJUST 0x000108A9
+
+/** ID of the Reverb module. This module supports the following
+ parameter IDs:
+ - #AUDPROC_PARAM_ID_REVERB_ENABLE
+ - #AUDPROC_PARAM_ID_REVERB_MODE
+ - #AUDPROC_PARAM_ID_REVERB_PRESET
+ - #AUDPROC_PARAM_ID_REVERB_WET_MIX
+ - #AUDPROC_PARAM_ID_REVERB_GAIN_ADJUST
+ - #AUDPROC_PARAM_ID_REVERB_ROOM_LEVEL
+ - #AUDPROC_PARAM_ID_REVERB_ROOM_HF_LEVEL
+ - #AUDPROC_PARAM_ID_REVERB_DECAY_TIME
+ - #AUDPROC_PARAM_ID_REVERB_DECAY_HF_RATIO
+ - #AUDPROC_PARAM_ID_REVERB_REFLECTIONS_LEVEL
+ - #AUDPROC_PARAM_ID_REVERB_REFLECTIONS_DELAY
+ - #AUDPROC_PARAM_ID_REVERB_LEVEL
+ - #AUDPROC_PARAM_ID_REVERB_DELAY
+ - #AUDPROC_PARAM_ID_REVERB_DIFFUSION
+ - #AUDPROC_PARAM_ID_REVERB_DENSITY
+*/
+#define AUDPROC_MODULE_ID_REVERB 0x000108AA
+/** ID of the Reverb enable parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_ENABLE 0x000108AB
+/** ID of the Reverb mode parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_MODE 0x000108AC
+/** ID of the Reverb preset parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_PRESET 0x000108AD
+/** ID of the Reverb wet mix parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_WET_MIX 0x000108AE
+/** ID of the Reverb gain adjust parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_GAIN_ADJUST 0x000108AF
+/** ID of the Reverb room level parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_ROOM_LEVEL 0x000108B0
+/** ID of the Reverb room hf level parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_ROOM_HF_LEVEL 0x000108B1
+/** ID of the Reverb decay time parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_DECAY_TIME 0x000108B2
+/** ID of the Reverb decay hf ratio parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_DECAY_HF_RATIO 0x000108B3
+/** ID of the Reverb reflections level parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_REFLECTIONS_LEVEL 0x000108B4
+/** ID of the Reverb reflections delay parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_REFLECTIONS_DELAY 0x000108B5
+/** ID of the Reverb level parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_LEVEL 0x000108B6
+/** ID of the Reverb delay parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_DELAY 0x000108B7
+/** ID of the Reverb diffusion parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_DIFFUSION 0x000108B8
+/** ID of the Reverb density parameter used by
+ AUDPROC_MODULE_ID_REVERB.
+*/
+#define AUDPROC_PARAM_ID_REVERB_DENSITY 0x000108B9
+
+/** ID of the Popless Equalizer module. This module supports the
+ following parameter IDs:
+ - #AUDPROC_PARAM_ID_EQ_ENABLE
+ - #AUDPROC_PARAM_ID_EQ_CONFIG
+ - #AUDPROC_PARAM_ID_EQ_NUM_BANDS
+ - #AUDPROC_PARAM_ID_EQ_BAND_LEVELS
+ - #AUDPROC_PARAM_ID_EQ_BAND_LEVEL_RANGE
+ - #AUDPROC_PARAM_ID_EQ_BAND_FREQS
+ - #AUDPROC_PARAM_ID_EQ_SINGLE_BAND_FREQ_RANGE
+ - #AUDPROC_PARAM_ID_EQ_SINGLE_BAND_FREQ
+ - #AUDPROC_PARAM_ID_EQ_BAND_INDEX
+ - #AUDPROC_PARAM_ID_EQ_PRESET_ID
+ - #AUDPROC_PARAM_ID_EQ_NUM_PRESETS
+ - #AUDPROC_PARAM_ID_EQ_GET_PRESET_NAME
+*/
+#define AUDPROC_MODULE_ID_POPLESS_EQUALIZER 0x000108BA
+/** ID of the Popless Equalizer enable parameter used by
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER.
+*/
+#define AUDPROC_PARAM_ID_EQ_ENABLE 0x000108BB
+/** ID of the Popless Equalizer config parameter used by
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER.
+*/
+#define AUDPROC_PARAM_ID_EQ_CONFIG 0x000108BC
+/** ID of the Popless Equalizer number of bands parameter used
+ by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is
+ used for get param only.
+*/
+#define AUDPROC_PARAM_ID_EQ_NUM_BANDS 0x000108BD
+/** ID of the Popless Equalizer band levels parameter used by
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is
+ used for get param only.
+*/
+#define AUDPROC_PARAM_ID_EQ_BAND_LEVELS 0x000108BE
+/** ID of the Popless Equalizer band level range parameter used
+ by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is
+ used for get param only.
+*/
+#define AUDPROC_PARAM_ID_EQ_BAND_LEVEL_RANGE 0x000108BF
+/** ID of the Popless Equalizer band frequencies parameter used
+ by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is
+ used for get param only.
+*/
+#define AUDPROC_PARAM_ID_EQ_BAND_FREQS 0x000108C0
+/** ID of the Popless Equalizer single band frequency range
+ parameter used by AUDPROC_MODULE_ID_POPLESS_EQUALIZER.
+ This param ID is used for get param only.
+*/
+#define AUDPROC_PARAM_ID_EQ_SINGLE_BAND_FREQ_RANGE 0x000108C1
+/** ID of the Popless Equalizer single band frequency parameter
+ used by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID
+ is used for set param only.
+*/
+#define AUDPROC_PARAM_ID_EQ_SINGLE_BAND_FREQ 0x000108C2
+/** ID of the Popless Equalizer band index parameter used by
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER.
+*/
+#define AUDPROC_PARAM_ID_EQ_BAND_INDEX 0x000108C3
+/** ID of the Popless Equalizer preset id parameter used by
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is used
+ for get param only.
+*/
+#define AUDPROC_PARAM_ID_EQ_PRESET_ID 0x000108C4
+/** ID of the Popless Equalizer number of presets parameter used
+ by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is used
+ for get param only.
+*/
+#define AUDPROC_PARAM_ID_EQ_NUM_PRESETS 0x000108C5
+/** ID of the Popless Equalizer preset name parameter used by
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is used
+ for get param only.
+*/
+#define AUDPROC_PARAM_ID_EQ_PRESET_NAME 0x000108C6
+
/* Set Q6 topologies */
#define ASM_CMD_ADD_TOPOLOGIES 0x00010DBE
#define ADM_CMD_ADD_TOPOLOGIES 0x00010335
@@ -6972,5 +7172,7 @@
#define US_POINT_EPOS_FORMAT_V2 0x0001272D
#define US_RAW_FORMAT_V2 0x0001272C
#define US_PROX_FORMAT_V2 0x0001272E
+#define US_RAW_SYNC_FORMAT 0x0001272F
+#define US_GES_SYNC_FORMAT 0x00012730
#endif /*_APR_AUDIO_V2_H_ */
diff --git a/include/sound/audio_effects.h b/include/sound/audio_effects.h
new file mode 100644
index 0000000..3444477
--- /dev/null
+++ b/include/sound/audio_effects.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _AUDIO_EFFECTS_H
+#define _AUDIO_EFFECTS_H
+
+/** AUDIO EFFECTS **/
+
+
+/* CONFIG GET/SET */
+#define CONFIG_CACHE 0
+#define CONFIG_SET 1
+#define CONFIG_GET 2
+
+/* CONFIG HEADER */
+/*
+
+ MODULE_ID,
+ DEVICE,
+ NUM_COMMANDS,
+ COMMAND_ID_1,
+ CONFIG_CACHE/SET/GET,
+ OFFSET_1,
+ LENGTH_1,
+ VALUES_1,
+ ...,
+ ...,
+ COMMAND_ID_2,
+ CONFIG_CACHE/SET/GET,
+ OFFSET_2,
+ LENGTH_2,
+ VALUES_2,
+ ...,
+ ...,
+ COMMAND_ID_3,
+ ...
+*/
+
+
+/* CONFIG PARAM IDs */
+#define VIRTUALIZER_MODULE 0x00001000
+#define VIRTUALIZER_ENABLE 0x00001001
+#define VIRTUALIZER_STRENGTH 0x00001002
+#define VIRTUALIZER_OUT_TYPE 0x00001003
+#define VIRTUALIZER_GAIN_ADJUST 0x00001004
+#define VIRTUALIZER_ENABLE_PARAM_LEN 1
+#define VIRTUALIZER_STRENGTH_PARAM_LEN 1
+#define VIRTUALIZER_OUT_TYPE_PARAM_LEN 1
+#define VIRTUALIZER_GAIN_ADJUST_PARAM_LEN 1
+
+#define REVERB_MODULE 0x00002000
+#define REVERB_ENABLE 0x00002001
+#define REVERB_MODE 0x00002002
+#define REVERB_PRESET 0x00002003
+#define REVERB_WET_MIX 0x00002004
+#define REVERB_GAIN_ADJUST 0x00002005
+#define REVERB_ROOM_LEVEL 0x00002006
+#define REVERB_ROOM_HF_LEVEL 0x00002007
+#define REVERB_DECAY_TIME 0x00002008
+#define REVERB_DECAY_HF_RATIO 0x00002009
+#define REVERB_REFLECTIONS_LEVEL 0x0000200a
+#define REVERB_REFLECTIONS_DELAY 0x0000200b
+#define REVERB_LEVEL 0x0000200c
+#define REVERB_DELAY 0x0000200d
+#define REVERB_DIFFUSION 0x0000200e
+#define REVERB_DENSITY 0x0000200f
+#define REVERB_ENABLE_PARAM_LEN 1
+#define REVERB_MODE_PARAM_LEN 1
+#define REVERB_PRESET_PARAM_LEN 1
+#define REVERB_WET_MIX_PARAM_LEN 1
+#define REVERB_GAIN_ADJUST_PARAM_LEN 1
+#define REVERB_ROOM_LEVEL_PARAM_LEN 1
+#define REVERB_ROOM_HF_LEVEL_PARAM_LEN 1
+#define REVERB_DECAY_TIME_PARAM_LEN 1
+#define REVERB_DECAY_HF_RATIO_PARAM_LEN 1
+#define REVERB_REFLECTIONS_LEVEL_PARAM_LEN 1
+#define REVERB_REFLECTIONS_DELAY_PARAM_LEN 1
+#define REVERB_LEVEL_PARAM_LEN 1
+#define REVERB_DELAY_PARAM_LEN 1
+#define REVERB_DIFFUSION_PARAM_LEN 1
+#define REVERB_DENSITY_PARAM_LEN 1
+
+#define BASS_BOOST_MODULE 0x00003000
+#define BASS_BOOST_ENABLE 0x00003001
+#define BASS_BOOST_MODE 0x00003002
+#define BASS_BOOST_STRENGTH 0x00003003
+#define BASS_BOOST_ENABLE_PARAM_LEN 1
+#define BASS_BOOST_MODE_PARAM_LEN 1
+#define BASS_BOOST_STRENGTH_PARAM_LEN 1
+
+#define EQ_MODULE 0x00004000
+#define EQ_ENABLE 0x00004001
+#define EQ_CONFIG 0x00004002
+#define EQ_NUM_BANDS 0x00004003
+#define EQ_BAND_LEVELS 0x00004004
+#define EQ_BAND_LEVEL_RANGE 0x00004005
+#define EQ_BAND_FREQS 0x00004006
+#define EQ_SINGLE_BAND_FREQ_RANGE 0x00004007
+#define EQ_SINGLE_BAND_FREQ 0x00004008
+#define EQ_BAND_INDEX 0x00004009
+#define EQ_PRESET_ID 0x0000400a
+#define EQ_NUM_PRESETS 0x0000400b
+#define EQ_PRESET_NAME 0x0000400c
+#define EQ_ENABLE_PARAM_LEN 1
+#define EQ_CONFIG_PARAM_LEN 3
+#define EQ_CONFIG_PER_BAND_PARAM_LEN 5
+#define EQ_NUM_BANDS_PARAM_LEN 1
+#define EQ_BAND_LEVELS_PARAM_LEN 13
+#define EQ_BAND_LEVEL_RANGE_PARAM_LEN 2
+#define EQ_BAND_FREQS_PARAM_LEN 13
+#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN 2
+#define EQ_SINGLE_BAND_FREQ_PARAM_LEN 1
+#define EQ_BAND_INDEX_PARAM_LEN 1
+#define EQ_PRESET_ID_PARAM_LEN 1
+#define EQ_NUM_PRESETS_PARAM_LEN 1
+#define EQ_PRESET_NAME_PARAM_LEN 32
+
+#define EQ_TYPE_NONE 0
+#define EQ_BASS_BOOST 1
+#define EQ_BASS_CUT 2
+#define EQ_TREBLE_BOOST 3
+#define EQ_TREBLE_CUT 4
+#define EQ_BAND_BOOST 5
+#define EQ_BAND_CUT 6
+
+
+
+#define COMMAND_PAYLOAD_LEN 3
+#define COMMAND_PAYLOAD_SZ (COMMAND_PAYLOAD_LEN * sizeof(uint32_t))
+#define MAX_INBAND_PARAM_SZ 4096
+#define Q27_UNITY (1 << 27)
+#define Q8_UNITY (1 << 8)
+#define CUSTOM_OPENSL_PRESET 18
+
+#define VIRTUALIZER_ENABLE_PARAM_SZ \
+ (VIRTUALIZER_ENABLE_PARAM_LEN*sizeof(uint32_t))
+#define VIRTUALIZER_STRENGTH_PARAM_SZ \
+ (VIRTUALIZER_STRENGTH_PARAM_LEN*sizeof(uint32_t))
+#define VIRTUALIZER_OUT_TYPE_PARAM_SZ \
+ (VIRTUALIZER_OUT_TYPE_PARAM_LEN*sizeof(uint32_t))
+#define VIRTUALIZER_GAIN_ADJUST_PARAM_SZ \
+ (VIRTUALIZER_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t))
+struct virtualizer_params {
+ uint32_t device;
+ uint32_t enable_flag;
+ uint32_t strength;
+ uint32_t out_type;
+ int32_t gain_adjust;
+};
+
+#define NUM_OSL_REVERB_PRESETS_SUPPORTED 6
+#define REVERB_ENABLE_PARAM_SZ \
+ (REVERB_ENABLE_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_MODE_PARAM_SZ \
+ (REVERB_MODE_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_PRESET_PARAM_SZ \
+ (REVERB_PRESET_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_WET_MIX_PARAM_SZ \
+ (REVERB_WET_MIX_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_GAIN_ADJUST_PARAM_SZ \
+ (REVERB_GAIN_ADJUST_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_ROOM_LEVEL_PARAM_SZ \
+ (REVERB_ROOM_LEVEL_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_ROOM_HF_LEVEL_PARAM_SZ \
+ (REVERB_ROOM_HF_LEVEL_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_DECAY_TIME_PARAM_SZ \
+ (REVERB_DECAY_TIME_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_DECAY_HF_RATIO_PARAM_SZ \
+ (REVERB_DECAY_HF_RATIO_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_REFLECTIONS_LEVEL_PARAM_SZ \
+ (REVERB_REFLECTIONS_LEVEL_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_REFLECTIONS_DELAY_PARAM_SZ \
+ (REVERB_REFLECTIONS_DELAY_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_LEVEL_PARAM_SZ \
+ (REVERB_LEVEL_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_DELAY_PARAM_SZ \
+ (REVERB_DELAY_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_DIFFUSION_PARAM_SZ \
+ (REVERB_DIFFUSION_PARAM_LEN*sizeof(uint32_t))
+#define REVERB_DENSITY_PARAM_SZ \
+ (REVERB_DENSITY_PARAM_LEN*sizeof(uint32_t))
+struct reverb_params {
+ uint32_t device;
+ uint32_t enable_flag;
+ uint32_t mode;
+ uint32_t preset;
+ uint32_t wet_mix;
+ int32_t gain_adjust;
+ int32_t room_level;
+ int32_t room_hf_level;
+ uint32_t decay_time;
+ uint32_t decay_hf_ratio;
+ int32_t reflections_level;
+ uint32_t reflections_delay;
+ int32_t level;
+ uint32_t delay;
+ uint32_t diffusion;
+ uint32_t density;
+};
+
+#define BASS_BOOST_ENABLE_PARAM_SZ \
+ (BASS_BOOST_ENABLE_PARAM_LEN*sizeof(uint32_t))
+#define BASS_BOOST_MODE_PARAM_SZ \
+ (BASS_BOOST_MODE_PARAM_LEN*sizeof(uint32_t))
+#define BASS_BOOST_STRENGTH_PARAM_SZ \
+ (BASS_BOOST_STRENGTH_PARAM_LEN*sizeof(uint32_t))
+struct bass_boost_params {
+ uint32_t device;
+ uint32_t enable_flag;
+ uint32_t mode;
+ uint32_t strength;
+};
+
+
+#define MAX_EQ_BANDS 12
+#define MAX_OSL_EQ_BANDS 5
+#define EQ_ENABLE_PARAM_SZ \
+ (EQ_ENABLE_PARAM_LEN*sizeof(uint32_t))
+#define EQ_CONFIG_PARAM_SZ \
+ (EQ_CONFIG_PARAM_LEN*sizeof(uint32_t))
+#define EQ_CONFIG_PER_BAND_PARAM_SZ \
+ (EQ_CONFIG_PER_BAND_PARAM_LEN*sizeof(uint32_t))
+#define EQ_CONFIG_PARAM_MAX_LEN (EQ_CONFIG_PARAM_LEN+\
+ MAX_EQ_BANDS*EQ_CONFIG_PER_BAND_PARAM_LEN)
+#define EQ_CONFIG_PARAM_MAX_SZ \
+ (EQ_CONFIG_PARAM_MAX_LEN*sizeof(uint32_t))
+#define EQ_NUM_BANDS_PARAM_SZ \
+ (EQ_NUM_BANDS_PARAM_LEN*sizeof(uint32_t))
+#define EQ_BAND_LEVELS_PARAM_SZ \
+ (EQ_BAND_LEVELS_PARAM_LEN*sizeof(uint32_t))
+#define EQ_BAND_LEVEL_RANGE_PARAM_SZ \
+ (EQ_BAND_LEVEL_RANGE_PARAM_LEN*sizeof(uint32_t))
+#define EQ_BAND_FREQS_PARAM_SZ \
+ (EQ_BAND_FREQS_PARAM_LEN*sizeof(uint32_t))
+#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_SZ \
+ (EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN*sizeof(uint32_t))
+#define EQ_SINGLE_BAND_FREQ_PARAM_SZ \
+ (EQ_SINGLE_BAND_FREQ_PARAM_LEN*sizeof(uint32_t))
+#define EQ_BAND_INDEX_PARAM_SZ \
+ (EQ_BAND_INDEX_PARAM_LEN*sizeof(uint32_t))
+#define EQ_PRESET_ID_PARAM_SZ \
+ (EQ_PRESET_ID_PARAM_LEN*sizeof(uint32_t))
+#define EQ_NUM_PRESETS_PARAM_SZ \
+ (EQ_NUM_PRESETS_PARAM_LEN*sizeof(uint8_t))
+struct eq_config_t {
+ int32_t eq_pregain;
+ int32_t preset_id;
+ uint32_t num_bands;
+};
+struct eq_per_band_config_t {
+ int32_t band_idx;
+ uint32_t filter_type;
+ uint32_t freq_millihertz;
+ int32_t gain_millibels;
+ uint32_t quality_factor;
+};
+struct eq_per_band_freq_range_t {
+ uint32_t band_index;
+ uint32_t min_freq_millihertz;
+ uint32_t max_freq_millihertz;
+};
+
+struct eq_params {
+ uint32_t device;
+ uint32_t enable_flag;
+ struct eq_config_t config;
+ struct eq_per_band_config_t per_band_cfg[MAX_EQ_BANDS];
+ struct eq_per_band_freq_range_t per_band_freq_range[MAX_EQ_BANDS];
+ uint32_t band_index;
+ uint32_t freq_millihertz;
+};
+
+#endif /*_MSM_AUDIO_EFFECTS_H*/
diff --git a/include/sound/q6asm-v2.h b/include/sound/q6asm-v2.h
index eb3b41a..b00cfc9 100644
--- a/include/sound/q6asm-v2.h
+++ b/include/sound/q6asm-v2.h
@@ -67,6 +67,8 @@
/* Enable Sample_Rate/Channel_Mode notification event from Decoder */
#define SR_CM_NOTIFY_ENABLE 0x0004
+#define TUN_WRITE_IO_MODE 0x0008 /* tunnel read write mode */
+#define TUN_READ_IO_MODE 0x0004 /* tunnel read write mode */
#define SYNC_IO_MODE 0x0001
#define ASYNC_IO_MODE 0x0002
#define COMPRESSED_IO 0x0040
@@ -218,6 +220,9 @@
uint32_t rd_format,
uint32_t wr_format);
+int q6asm_open_loopback_v2(struct audio_client *ac,
+ uint16_t bits_per_sample);
+
int q6asm_write(struct audio_client *ac, uint32_t len, uint32_t msw_ts,
uint32_t lsw_ts, uint32_t flags);
int q6asm_write_nolock(struct audio_client *ac, uint32_t len, uint32_t msw_ts,
@@ -377,6 +382,9 @@
int q6asm_get_session_time(struct audio_client *ac, uint64_t *tstamp);
+int q6asm_send_audio_effects_params(struct audio_client *ac, char *params,
+ uint32_t params_length);
+
/* Client can set the IO mode to either AIO/SIO mode */
int q6asm_set_io_mode(struct audio_client *ac, uint32_t mode);
diff --git a/include/sound/soc.h b/include/sound/soc.h
index ecfba67..278ada3 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -563,6 +563,7 @@
#endif
struct snd_soc_jack {
+ struct mutex mutex;
struct snd_jack *jack;
struct snd_soc_codec *codec;
struct list_head pins;
diff --git a/kernel/cpu.c b/kernel/cpu.c
index d5ab2e6..2db91f9 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -77,6 +77,10 @@
if (cpu_hotplug.active_writer == current)
return;
mutex_lock(&cpu_hotplug.lock);
+
+ if (WARN_ON(!cpu_hotplug.refcount))
+ cpu_hotplug.refcount++; /* try to fix things up */
+
if (!--cpu_hotplug.refcount && unlikely(cpu_hotplug.active_writer))
wake_up_process(cpu_hotplug.active_writer);
mutex_unlock(&cpu_hotplug.lock);
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 89a5395..954a8c4 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -4931,7 +4931,7 @@
touch_all_softlockup_watchdogs();
-#ifdef CONFIG_SCHED_DEBUG
+#ifdef CONFIG_SYSRQ_SCHED_DEBUG
sysrq_sched_debug_show();
#endif
rcu_read_unlock();
diff --git a/kernel/sched/debug.c b/kernel/sched/debug.c
index 09acaa1..c00829e 100644
--- a/kernel/sched/debug.c
+++ b/kernel/sched/debug.c
@@ -374,10 +374,12 @@
return 0;
}
+#ifdef CONFIG_SYSRQ_SCHED_DEBUG
void sysrq_sched_debug_show(void)
{
sched_debug_show(NULL, NULL);
}
+#endif
static int sched_debug_open(struct inode *inode, struct file *filp)
{
diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h
index 55f6d9c..c0288a6 100644
--- a/kernel/sched/sched.h
+++ b/kernel/sched/sched.h
@@ -872,7 +872,9 @@
#endif
+#ifdef CONFIG_SYSRQ_SCHED_DEBUG
extern void sysrq_sched_debug_show(void);
+#endif
extern void sched_init_granularity(void);
extern void update_max_interval(void);
extern void update_group_power(struct sched_domain *sd, int cpu);
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index d16a59ec..c35fe53 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -102,6 +102,7 @@
extern unsigned int core_pipe_limit;
extern int pid_max;
extern int min_free_kbytes;
+extern int extra_free_kbytes;
extern int min_free_order_shift;
extern int pid_max_min, pid_max_max;
extern int sysctl_drop_caches;
@@ -1228,6 +1229,14 @@
.extra1 = &zero,
},
{
+ .procname = "extra_free_kbytes",
+ .data = &extra_free_kbytes,
+ .maxlen = sizeof(extra_free_kbytes),
+ .mode = 0644,
+ .proc_handler = min_free_kbytes_sysctl_handler,
+ .extra1 = &zero,
+ },
+ {
.procname = "min_free_order_shift",
.data = &min_free_order_shift,
.maxlen = sizeof(min_free_order_shift),
diff --git a/kernel/time/tick-broadcast.c b/kernel/time/tick-broadcast.c
index f113755..d6d0d41 100644
--- a/kernel/time/tick-broadcast.c
+++ b/kernel/time/tick-broadcast.c
@@ -370,14 +370,34 @@
return to_cpumask(tick_broadcast_oneshot_mask);
}
-static int tick_broadcast_set_event(ktime_t expires, int force)
+/*
+ * Set broadcast interrupt affinity
+ */
+static void tick_broadcast_set_affinity(struct clock_event_device *bc,
+ const struct cpumask *cpumask)
{
- struct clock_event_device *bc = tick_broadcast_device.evtdev;
+ if (!(bc->features & CLOCK_EVT_FEAT_DYNIRQ))
+ return;
+
+ if (cpumask_equal(bc->cpumask, cpumask))
+ return;
+
+ bc->cpumask = cpumask;
+ irq_set_affinity(bc->irq, bc->cpumask);
+}
+
+static int tick_broadcast_set_event(struct clock_event_device *bc, int cpu,
+ ktime_t expires, int force)
+{
+ int ret;
if (bc->mode != CLOCK_EVT_MODE_ONESHOT)
clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT);
- return clockevents_program_event(bc, expires, force);
+ ret = clockevents_program_event(bc, expires, force);
+ if (!ret)
+ tick_broadcast_set_affinity(bc, cpumask_of(cpu));
+ return ret;
}
int tick_resume_broadcast_oneshot(struct clock_event_device *bc)
@@ -406,7 +426,7 @@
{
struct tick_device *td;
ktime_t now, next_event;
- int cpu;
+ int cpu, next_cpu = 0;
raw_spin_lock(&tick_broadcast_lock);
again:
@@ -417,10 +437,12 @@
/* Find all expired events */
for_each_cpu(cpu, tick_get_broadcast_oneshot_mask()) {
td = &per_cpu(tick_cpu_device, cpu);
- if (td->evtdev->next_event.tv64 <= now.tv64)
+ if (td->evtdev->next_event.tv64 <= now.tv64) {
cpumask_set_cpu(cpu, to_cpumask(tmpmask));
- else if (td->evtdev->next_event.tv64 < next_event.tv64)
+ } else if (td->evtdev->next_event.tv64 < next_event.tv64) {
next_event.tv64 = td->evtdev->next_event.tv64;
+ next_cpu = cpu;
+ }
}
/*
@@ -443,7 +465,7 @@
* Rearm the broadcast device. If event expired,
* repeat the above
*/
- if (tick_broadcast_set_event(next_event, 0))
+ if (tick_broadcast_set_event(dev, next_cpu, next_event, 0))
goto again;
}
raw_spin_unlock(&tick_broadcast_lock);
@@ -486,7 +508,7 @@
cpumask_set_cpu(cpu, tick_get_broadcast_oneshot_mask());
clockevents_set_mode(dev, CLOCK_EVT_MODE_SHUTDOWN);
if (dev->next_event.tv64 < bc->next_event.tv64)
- tick_broadcast_set_event(dev->next_event, 1);
+ tick_broadcast_set_event(bc, cpu, dev->next_event, 1);
}
} else {
if (cpumask_test_cpu(cpu, tick_get_broadcast_oneshot_mask())) {
@@ -555,7 +577,7 @@
clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT);
tick_broadcast_init_next_event(to_cpumask(tmpmask),
tick_next_period);
- tick_broadcast_set_event(tick_next_period, 1);
+ tick_broadcast_set_event(bc, cpu, tick_next_period, 1);
} else
bc->next_event.tv64 = KTIME_MAX;
} else {
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index b9060a1..5160a45 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -291,6 +291,15 @@
that can help debug the scheduler. The runtime overhead of this
option is minimal.
+config SYSRQ_SCHED_DEBUG
+ bool "Print scheduling debugging info from sysrq-trigger"
+ depends on SCHED_DEBUG
+ default y
+ help
+ If you say Y here, the "show-task-states(T)" and
+ "show-blocked-tasks(W)" sysrq-triggers will print additional
+ scheduling statistics.
+
config SCHEDSTATS
bool "Collect scheduler statistics"
depends on DEBUG_KERNEL && PROC_FS
diff --git a/lib/idr.c b/lib/idr.c
index 4046e29..e90d2d0 100644
--- a/lib/idr.c
+++ b/lib/idr.c
@@ -625,7 +625,14 @@
return p;
}
- id += 1 << n;
+ /*
+ * Proceed to the next layer at the current level. Unlike
+ * idr_for_each(), @id isn't guaranteed to be aligned to
+ * layer boundary at this point and adding 1 << n may
+ * incorrectly skip IDs. Make sure we jump to the
+ * beginning of the next layer using round_up().
+ */
+ id = round_up(id + 1, 1 << n);
while (n < fls(id)) {
n += IDR_BITS;
p = *--paa;
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index a1e4f77..d4c0534 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -199,9 +199,21 @@
"Movable",
};
+/*
+ * Try to keep at least this much lowmem free. Do not allow normal
+ * allocations below this point, only high priority ones. Automatically
+ * tuned according to the amount of memory in the system.
+ */
int min_free_kbytes = 1024;
int min_free_order_shift = 1;
+/*
+ * Extra memory for the system to try freeing. Used to temporarily
+ * free memory, to make space for new workloads. Anyone can allocate
+ * down to the min watermarks controlled by min_free_kbytes above.
+ */
+int extra_free_kbytes = 0;
+
static unsigned long __meminitdata nr_kernel_pages;
static unsigned long __meminitdata nr_all_pages;
static unsigned long __meminitdata dma_reserve;
@@ -1451,10 +1463,11 @@
zone = page_zone(page);
mt = get_pageblock_migratetype(page);
- if (mt != MIGRATE_ISOLATE && !is_migrate_cma(mt)) {
+ if (mt != MIGRATE_ISOLATE) {
/* Obey watermarks as if the page was being allocated */
watermark = low_wmark_pages(zone) + (1 << order);
- if (!zone_watermark_ok(zone, 0, watermark, 0, 0))
+ if (!is_migrate_cma(mt) &&
+ !zone_watermark_ok(zone, 0, watermark, 0, 0))
return 0;
__mod_zone_freepage_state(zone, -(1UL << order), mt);
@@ -5177,6 +5190,7 @@
static void __setup_per_zone_wmarks(void)
{
unsigned long pages_min = min_free_kbytes >> (PAGE_SHIFT - 10);
+ unsigned long pages_low = extra_free_kbytes >> (PAGE_SHIFT - 10);
unsigned long lowmem_pages = 0;
struct zone *zone;
unsigned long flags;
@@ -5188,11 +5202,14 @@
}
for_each_zone(zone) {
- u64 tmp;
+ u64 min, low;
spin_lock_irqsave(&zone->lock, flags);
- tmp = (u64)pages_min * zone->present_pages;
- do_div(tmp, lowmem_pages);
+ min = (u64)pages_min * zone->present_pages;
+ do_div(min, lowmem_pages);
+ low = (u64)pages_low * zone->present_pages;
+ do_div(low, vm_total_pages);
+
if (is_highmem(zone)) {
/*
* __GFP_HIGH and PF_MEMALLOC allocations usually don't
@@ -5216,11 +5233,13 @@
* If it's a lowmem zone, reserve a number of pages
* proportionate to the zone's size.
*/
- zone->watermark[WMARK_MIN] = tmp;
+ zone->watermark[WMARK_MIN] = min;
}
- zone->watermark[WMARK_LOW] = min_wmark_pages(zone) + (tmp >> 2);
- zone->watermark[WMARK_HIGH] = min_wmark_pages(zone) + (tmp >> 1);
+ zone->watermark[WMARK_LOW] = min_wmark_pages(zone) +
+ low + (min >> 2);
+ zone->watermark[WMARK_HIGH] = min_wmark_pages(zone) +
+ low + (min >> 1);
setup_zone_migrate_reserve(zone);
spin_unlock_irqrestore(&zone->lock, flags);
@@ -5333,7 +5352,7 @@
/*
* min_free_kbytes_sysctl_handler - just a wrapper around proc_dointvec() so
* that we can call two helper functions whenever min_free_kbytes
- * changes.
+ * or extra_free_kbytes changes.
*/
int min_free_kbytes_sysctl_handler(ctl_table *table, int write,
void __user *buffer, size_t *length, loff_t *ppos)
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index e174693..fa8a793 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -184,36 +184,6 @@
return ret;
}
-#ifdef ENABLE_VMALLOC_SAVING
-int is_vmalloc_addr(const void *x)
-{
- struct rb_node *n;
- struct vmap_area *va;
- int ret = 0;
-
- spin_lock(&vmap_area_lock);
-
- for (n = rb_first(vmap_area_root); n; rb_next(n)) {
- va = rb_entry(n, struct vmap_area, rb_node);
- if (x >= va->va_start && x < va->va_end) {
- ret = 1;
- break;
- }
- }
-
- spin_unlock(&vmap_area_lock);
- return ret;
-}
-#else
-int is_vmalloc_addr(const void *x)
-{
- unsigned long addr = (unsigned long)x;
-
- return addr >= VMALLOC_START && addr < VMALLOC_END;
-}
-#endif
-EXPORT_SYMBOL(is_vmalloc_addr);
-
int is_vmalloc_or_module_addr(const void *x)
{
/*
@@ -302,6 +272,47 @@
static unsigned long vmap_area_pcpu_hole;
+#ifdef CONFIG_ENABLE_VMALLOC_SAVING
+int is_vmalloc_addr(const void *x)
+{
+ struct vmap_area *va;
+ int ret = 0;
+
+ spin_lock(&vmap_area_lock);
+ list_for_each_entry(va, &vmap_area_list, list) {
+ if (va->flags & (VM_LAZY_FREE | VM_LAZY_FREEING))
+ continue;
+
+ if (!(va->flags & VM_VM_AREA))
+ continue;
+
+ if (va->vm == NULL)
+ continue;
+
+ if (va->vm->flags & VM_LOWMEM)
+ continue;
+
+ if ((unsigned long)x >= va->va_start &&
+ (unsigned long)x < va->va_end) {
+ ret = 1;
+ break;
+ }
+ }
+ spin_unlock(&vmap_area_lock);
+ return ret;
+}
+#else
+int is_vmalloc_addr(const void *x)
+{
+ unsigned long addr = (unsigned long)x;
+
+ return addr >= VMALLOC_START && addr < VMALLOC_END;
+}
+#endif
+EXPORT_SYMBOL(is_vmalloc_addr);
+
+
+
static struct vmap_area *__find_vmap_area(unsigned long addr)
{
struct rb_node *n = vmap_area_root.rb_node;
diff --git a/net/core/skbuff.c b/net/core/skbuff.c
index e598400..04cfc69 100644
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
@@ -191,7 +191,7 @@
size = SKB_DATA_ALIGN(size);
size += SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
data = kmalloc_node_track_caller(size, gfp_mask, node);
- if (!data)
+ if (unlikely(ZERO_OR_NULL_PTR(data)))
goto nodata;
/* kmalloc(size) might give us more room than requested.
* Put skb_shared_info exactly at the end of allocated zone,
diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
index b2b0e99..2628937 100644
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -3443,7 +3443,10 @@
tcp_done(sk);
bh_unlock_sock(sk);
local_bh_enable();
- sock_put(sk);
+ if (!sock_flag(sk, SOCK_DEAD)) {
+ sock_orphan(sk);
+ sock_put(sk);
+ }
goto restart;
}
diff --git a/sound/core/compress_offload.c b/sound/core/compress_offload.c
index 8daa015..f8e9d7a 100644
--- a/sound/core/compress_offload.c
+++ b/sound/core/compress_offload.c
@@ -612,9 +612,10 @@
static inline int
snd_compr_tstamp(struct snd_compr_stream *stream, unsigned long arg)
{
- struct snd_compr_tstamp tstamp = {0};
+ struct snd_compr_tstamp tstamp;
int ret;
+ memset(&tstamp, 0, sizeof(tstamp));
ret = snd_compr_update_tstamp(stream, &tstamp);
if (ret == 0)
ret = copy_to_user((struct snd_compr_tstamp __user *)arg,
diff --git a/sound/soc/codecs/msm8x10-wcd.c b/sound/soc/codecs/msm8x10-wcd.c
index 52af21c..1962ff0 100644
--- a/sound/soc/codecs/msm8x10-wcd.c
+++ b/sound/soc/codecs/msm8x10-wcd.c
@@ -1396,7 +1396,10 @@
switch (decimator) {
case 1:
case 2:
- adc_dmic_sel = 0x0;
+ if ((dec_mux == 3) || (dec_mux == 4))
+ adc_dmic_sel = 0x1;
+ else
+ adc_dmic_sel = 0x0;
break;
default:
dev_err(codec->dev, "%s: Invalid Decimator = %u\n",
@@ -2582,6 +2585,8 @@
*/
{MSM8X10_WCD_A_RX_HPH_OCP_CTL, 0xE1, 0x61},
{MSM8X10_WCD_A_RX_COM_OCP_COUNT, 0xFF, 0xFF},
+ {MSM8X10_WCD_A_RX_HPH_L_TEST, 0x01, 0x01},
+ {MSM8X10_WCD_A_RX_HPH_R_TEST, 0x01, 0x01},
/* Initialize gain registers to use register gain */
{MSM8X10_WCD_A_RX_HPH_L_GAIN, 0x20, 0x20},
diff --git a/sound/soc/codecs/msm_hdmi_codec_rx.c b/sound/soc/codecs/msm_hdmi_codec_rx.c
index e5d5c32..73c9547e 100644
--- a/sound/soc/codecs/msm_hdmi_codec_rx.c
+++ b/sound/soc/codecs/msm_hdmi_codec_rx.c
@@ -21,6 +21,8 @@
#define MSM_HDMI_PCM_RATES SNDRV_PCM_RATE_48000
+static int msm_hdmi_audio_codec_return_value;
+
struct msm_hdmi_audio_codec_rx_data {
struct platform_device *hdmi_core_pdev;
struct msm_hdmi_audio_codec_ops hdmi_ops;
@@ -54,8 +56,8 @@
int rc;
codec_data = snd_soc_codec_get_drvdata(codec);
- rc = codec_data->hdmi_ops.get_audio_edid_blk(codec_data->hdmi_core_pdev,
- &edid_blk);
+ rc = codec_data->hdmi_ops.get_audio_edid_blk(
+ codec_data->hdmi_core_pdev, &edid_blk);
if (!IS_ERR_VALUE(rc)) {
memcpy(ucontrol->value.bytes.data, edid_blk.audio_data_blk,
@@ -80,6 +82,24 @@
},
};
+static int msm_hdmi_audio_codec_rx_dai_startup(
+ struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct msm_hdmi_audio_codec_rx_data *codec_data =
+ dev_get_drvdata(dai->codec->dev);
+
+ msm_hdmi_audio_codec_return_value =
+ codec_data->hdmi_ops.hdmi_cable_status(
+ codec_data->hdmi_core_pdev, 1);
+ if (IS_ERR_VALUE(msm_hdmi_audio_codec_return_value)) {
+ dev_err(dai->dev,
+ "%s() HDMI core is not ready\n", __func__);
+ }
+
+ return msm_hdmi_audio_codec_return_value;
+}
+
static int msm_hdmi_audio_codec_rx_dai_hw_params(
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
@@ -89,17 +109,37 @@
u32 level_shift = 0; /* 0dB */
bool down_mix = 0;
u32 num_channels = params_channels(params);
+ int rc = 0;
struct msm_hdmi_audio_codec_rx_data *codec_data =
dev_get_drvdata(dai->codec->dev);
+ /*refer to HDMI spec CEA-861-E: Table 28 Audio InfoFrame Data Byte 4*/
+ if (IS_ERR_VALUE(msm_hdmi_audio_codec_return_value)) {
+ dev_err(dai->dev,
+ "%s() HDMI core is not ready\n", __func__);
+ return msm_hdmi_audio_codec_return_value;
+ }
+
switch (num_channels) {
case 2:
channel_allocation = 0;
break;
+ case 3:
+ channel_allocation = 0x02;//default to FL/FR/FC
+ break;
+ case 4:
+ channel_allocation = 0x06;//default to FL/FR/FC/RC
+ break;
+ case 5:
+ channel_allocation = 0x0A;//default to FL/FR/FC/RR/RL
+ break;
case 6:
channel_allocation = 0x0B;
break;
+ case 7:
+ channel_allocation = 0x12;//default to FL/FR/FC/RL/RR/RRC/RLC
+ break;
case 8:
channel_allocation = 0x13;
break;
@@ -108,19 +148,47 @@
return -EINVAL;
}
- dev_dbg(dai->dev, "%s() num_ch %u samplerate %u channel_allocation = %u\n",
+ dev_dbg(dai->dev,
+ "%s() num_ch %u samplerate %u channel_allocation = %u\n",
__func__, num_channels, params_rate(params),
channel_allocation);
- codec_data->hdmi_ops.audio_info_setup(codec_data->hdmi_core_pdev,
- params_rate(params), num_channels, channel_allocation,
- level_shift, down_mix);
+ rc = codec_data->hdmi_ops.audio_info_setup(
+ codec_data->hdmi_core_pdev,
+ params_rate(params), num_channels,
+ channel_allocation, level_shift, down_mix);
+ if (IS_ERR_VALUE(rc)) {
+ dev_err(dai->dev,
+ "%s() HDMI core is not ready\n", __func__);
+ }
- return 0;
+ return rc;
+}
+
+static void msm_hdmi_audio_codec_rx_dai_shutdown(
+ struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ int rc;
+
+ struct msm_hdmi_audio_codec_rx_data *codec_data =
+ dev_get_drvdata(dai->codec->dev);
+
+ rc = codec_data->hdmi_ops.hdmi_cable_status(
+ codec_data->hdmi_core_pdev, 0);
+ if (IS_ERR_VALUE(rc)) {
+ dev_err(dai->dev,
+ "%s() HDMI core had problems releasing HDMI audio flag\n",
+ __func__);
+ }
+
+ return;
}
static struct snd_soc_dai_ops msm_hdmi_audio_codec_rx_dai_ops = {
+ .startup = msm_hdmi_audio_codec_rx_dai_startup,
.hw_params = msm_hdmi_audio_codec_rx_dai_hw_params,
+ .shutdown = msm_hdmi_audio_codec_rx_dai_shutdown
};
static int msm_hdmi_audio_codec_rx_probe(struct snd_soc_codec *codec)
diff --git a/sound/soc/codecs/wcd9306.c b/sound/soc/codecs/wcd9306.c
index aaa132e..4912cf04a 100644
--- a/sound/soc/codecs/wcd9306.c
+++ b/sound/soc/codecs/wcd9306.c
@@ -42,6 +42,8 @@
#define TAPAN_HPH_PA_SETTLE_COMP_ON 3000
#define TAPAN_HPH_PA_SETTLE_COMP_OFF 13000
+#define DAPM_MICBIAS2_EXTERNAL_STANDALONE "MIC BIAS2 External Standalone"
+
#define TAPAN_VDD_CX_OPTIMAL_UA 10000
#define TAPAN_VDD_CX_SLEEP_UA 2000
@@ -281,6 +283,8 @@
s32 dmic_1_2_clk_cnt;
s32 dmic_3_4_clk_cnt;
s32 dmic_5_6_clk_cnt;
+ s32 ldo_h_users;
+ s32 micb_2_users;
u32 anc_slot;
bool anc_func;
@@ -1323,6 +1327,9 @@
static const struct soc_enum rx4_mix1_inp2_chain_enum =
SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX4_B1_CTL, 4, 13, rx_3_4_mix1_text);
+static const struct soc_enum rx4_mix1_inp3_chain_enum =
+ SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX4_B2_CTL, 0, 13, rx_3_4_mix1_text);
+
static const struct soc_enum rx1_mix2_inp1_chain_enum =
SOC_ENUM_SINGLE(TAPAN_A_CDC_CONN_RX1_B3_CTL, 0, 5, rx_mix2_text);
@@ -1418,6 +1425,9 @@
static const struct snd_kcontrol_new rx4_mix1_inp2_mux =
SOC_DAPM_ENUM("RX4 MIX1 INP2 Mux", rx4_mix1_inp2_chain_enum);
+static const struct snd_kcontrol_new rx4_mix1_inp3_mux =
+ SOC_DAPM_ENUM("RX4 MIX1 INP3 Mux", rx4_mix1_inp3_chain_enum);
+
static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx1_mix2_inp1_chain_enum);
@@ -1829,6 +1839,7 @@
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
u16 adc_reg;
u8 init_bit_shift;
@@ -1856,6 +1867,9 @@
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
+ if (w->reg == TAPAN_A_TX_3_EN)
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr,
+ WCD9XXX_EVENT_PRE_TX_3_ON);
snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift,
1 << init_bit_shift);
break;
@@ -1864,6 +1878,11 @@
snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00);
break;
+ case SND_SOC_DAPM_POST_PMD:
+ if (w->reg == TAPAN_A_TX_3_EN)
+ wcd9xxx_resmgr_notifier_call(&tapan->resmgr,
+ WCD9XXX_EVENT_POST_TX_3_OFF);
+ break;
}
return 0;
}
@@ -2137,38 +2156,37 @@
{
struct snd_soc_codec *codec = w->codec;
struct tapan_priv *tapan = snd_soc_codec_get_drvdata(codec);
- u16 micb_int_reg;
+ u16 micb_int_reg = 0, micb_ctl_reg = 0;
u8 cfilt_sel_val = 0;
char *internal1_text = "Internal1";
char *internal2_text = "Internal2";
char *internal3_text = "Internal3";
enum wcd9xxx_notify_event e_post_off, e_pre_on, e_post_on;
- dev_dbg(codec->dev, "%s %d\n", __func__, event);
- switch (w->reg) {
- case TAPAN_A_MICB_1_CTL:
+ pr_debug("%s: w->name %s event %d\n", __func__, w->name, event);
+ if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) {
+ micb_ctl_reg = TAPAN_A_MICB_1_CTL;
micb_int_reg = TAPAN_A_MICB_1_INT_RBIAS;
cfilt_sel_val = tapan->resmgr.pdata->micbias.bias1_cfilt_sel;
e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_1_ON;
e_post_on = WCD9XXX_EVENT_POST_MICBIAS_1_ON;
e_post_off = WCD9XXX_EVENT_POST_MICBIAS_1_OFF;
- break;
- case TAPAN_A_MICB_2_CTL:
+ } else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) {
+ micb_ctl_reg = TAPAN_A_MICB_2_CTL;
micb_int_reg = TAPAN_A_MICB_2_INT_RBIAS;
cfilt_sel_val = tapan->resmgr.pdata->micbias.bias2_cfilt_sel;
e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_2_ON;
e_post_on = WCD9XXX_EVENT_POST_MICBIAS_2_ON;
e_post_off = WCD9XXX_EVENT_POST_MICBIAS_2_OFF;
- break;
- case TAPAN_A_MICB_3_CTL:
+ } else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) {
+ micb_ctl_reg = TAPAN_A_MICB_3_CTL;
micb_int_reg = TAPAN_A_MICB_3_INT_RBIAS;
cfilt_sel_val = tapan->resmgr.pdata->micbias.bias3_cfilt_sel;
e_pre_on = WCD9XXX_EVENT_PRE_MICBIAS_3_ON;
e_post_on = WCD9XXX_EVENT_POST_MICBIAS_3_ON;
e_post_off = WCD9XXX_EVENT_POST_MICBIAS_3_OFF;
- break;
- default:
- pr_err("%s: Error, invalid micbias register\n", __func__);
+ } else {
+ pr_err("%s: Error, invalid micbias %s\n", __func__, w->name);
return -EINVAL;
}
@@ -2187,6 +2205,20 @@
else if (strnstr(w->name, internal3_text, 30))
snd_soc_update_bits(codec, micb_int_reg, 0x3, 0x3);
+ if (micb_ctl_reg == TAPAN_A_MICB_2_CTL) {
+ if (++tapan->micb_2_users == 1)
+ wcd9xxx_resmgr_add_cond_update_bits(
+ &tapan->resmgr,
+ WCD9XXX_COND_HPH_MIC,
+ micb_ctl_reg, w->shift,
+ false);
+ pr_debug("%s: micb_2_users %d\n", __func__,
+ tapan->micb_2_users);
+ } else
+ snd_soc_update_bits(codec, micb_ctl_reg, 1 << w->shift,
+ 1 << w->shift);
+
+
break;
case SND_SOC_DAPM_POST_PMU:
usleep_range(20000, 20000);
@@ -2194,6 +2226,22 @@
wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_post_on);
break;
case SND_SOC_DAPM_POST_PMD:
+ if (micb_ctl_reg == TAPAN_A_MICB_2_CTL) {
+ if (--tapan->micb_2_users == 0)
+ wcd9xxx_resmgr_rm_cond_update_bits(
+ &tapan->resmgr,
+ WCD9XXX_COND_HPH_MIC,
+ micb_ctl_reg, 7,
+ false);
+ pr_debug("%s: micb_2_users %d\n", __func__,
+ tapan->micb_2_users);
+ WARN(tapan->micb_2_users < 0,
+ "Unexpected micbias users %d\n",
+ tapan->micb_2_users);
+ } else
+ snd_soc_update_bits(codec, micb_ctl_reg, 1 << w->shift,
+ 0);
+
/* Let MBHC module know so micbias switch to be off */
wcd9xxx_resmgr_notifier_call(&tapan->resmgr, e_post_off);
@@ -2212,6 +2260,23 @@
return 0;
}
+/* called under codec_resource_lock acquisition */
+static int tapan_enable_mbhc_micbias(struct snd_soc_codec *codec, bool enable)
+{
+ int rc;
+
+ if (enable)
+ rc = snd_soc_dapm_force_enable_pin(&codec->dapm,
+ DAPM_MICBIAS2_EXTERNAL_STANDALONE);
+ else
+ rc = snd_soc_dapm_disable_pin(&codec->dapm,
+ DAPM_MICBIAS2_EXTERNAL_STANDALONE);
+ if (!rc)
+ snd_soc_dapm_sync(&codec->dapm);
+ pr_debug("%s: leave ret %d\n", __func__, rc);
+ return rc;
+}
+
static void tx_hpf_corner_freq_callback(struct work_struct *work)
{
struct delayed_work *hpf_delayed_work;
@@ -2426,16 +2491,66 @@
return 0;
}
+/* called under codec_resource_lock acquisition */
+static int __tapan_codec_enable_ldo_h(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = w->codec;
+ struct tapan_priv *priv = snd_soc_codec_get_drvdata(codec);
+
+ pr_debug("%s: enter\n", __func__);
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ /*
+ * ldo_h_users is protected by codec->mutex, don't need
+ * additional mutex
+ */
+ if (++priv->ldo_h_users == 1) {
+ WCD9XXX_BG_CLK_LOCK(&priv->resmgr);
+ wcd9xxx_resmgr_get_bandgap(&priv->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ wcd9xxx_resmgr_get_clk_block(&priv->resmgr,
+ WCD9XXX_CLK_RCO);
+ snd_soc_update_bits(codec, TAPAN_A_LDO_H_MODE_1, 1 << 7,
+ 1 << 7);
+ wcd9xxx_resmgr_put_clk_block(&priv->resmgr,
+ WCD9XXX_CLK_RCO);
+ WCD9XXX_BG_CLK_UNLOCK(&priv->resmgr);
+ pr_debug("%s: ldo_h_users %d\n", __func__,
+ priv->ldo_h_users);
+ /* LDO enable requires 1ms to settle down */
+ usleep_range(1000, 1010);
+ }
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ if (--priv->ldo_h_users == 0) {
+ WCD9XXX_BG_CLK_LOCK(&priv->resmgr);
+ wcd9xxx_resmgr_get_clk_block(&priv->resmgr,
+ WCD9XXX_CLK_RCO);
+ snd_soc_update_bits(codec, TAPAN_A_LDO_H_MODE_1, 1 << 7,
+ 0);
+ wcd9xxx_resmgr_put_clk_block(&priv->resmgr,
+ WCD9XXX_CLK_RCO);
+ wcd9xxx_resmgr_put_bandgap(&priv->resmgr,
+ WCD9XXX_BANDGAP_AUDIO_MODE);
+ WCD9XXX_BG_CLK_UNLOCK(&priv->resmgr);
+ pr_debug("%s: ldo_h_users %d\n", __func__,
+ priv->ldo_h_users);
+ }
+ WARN(priv->ldo_h_users < 0, "Unexpected ldo_h users %d\n",
+ priv->ldo_h_users);
+ break;
+ }
+ pr_debug("%s: leave\n", __func__);
+ return 0;
+}
+
static int tapan_codec_enable_ldo_h(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
- switch (event) {
- case SND_SOC_DAPM_POST_PMU:
- case SND_SOC_DAPM_POST_PMD:
- usleep_range(1000, 1000);
- break;
- }
- return 0;
+ int rc;
+ rc = __tapan_codec_enable_ldo_h(w, kcontrol, event);
+ return rc;
}
static int tapan_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
@@ -2847,7 +2962,7 @@
{"DAC1", "Switch", "CLASS_H_DSM MUX"},
{"HPHL DAC", "Switch", "CLASS_H_DSM MUX"},
- {"HPHR DAC", NULL, "RX2 CHAIN"},
+ {"HPHR DAC", NULL, "RDAC3 MUX"},
{"LINEOUT1", NULL, "LINEOUT1 PA"},
{"LINEOUT2", NULL, "LINEOUT2 PA"},
@@ -2858,11 +2973,14 @@
{"LINEOUT2 PA", NULL, "LINEOUT2_PA_MIXER"},
{"LINEOUT2_PA_MIXER", NULL, "LINEOUT2 DAC"},
- {"LINEOUT1 DAC", NULL, "RX3 MIX1"},
{"RDAC5 MUX", "DEM3_INV", "RX3 MIX1"},
{"LINEOUT2 DAC", NULL, "RDAC5 MUX"},
+ {"RDAC4 MUX", "DEM3", "RX3 MIX1"},
+ {"RDAC4 MUX", "DEM2", "RX2 CHAIN"},
+ {"LINEOUT1 DAC", NULL, "RDAC4 MUX"},
+
{"SPK PA", NULL, "SPK DAC"},
{"SPK DAC", NULL, "VDD_SPKDRV"},
@@ -2875,7 +2993,7 @@
{"LINEOUT1 DAC", NULL, "CDC_CP_VDD"},
{"LINEOUT2 DAC", NULL, "CDC_CP_VDD"},
- {"RDAC3 MUX", "DEM2", "RX2 MIX1"},
+ {"RDAC3 MUX", "DEM2", "RX2 CHAIN"},
{"RDAC3 MUX", "DEM1", "RX1 CHAIN"},
{"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
@@ -3005,14 +3123,12 @@
{"MIC BIAS2 Internal2", NULL, "LDO_H"},
{"MIC BIAS2 Internal3", NULL, "LDO_H"},
{"MIC BIAS2 External", NULL, "LDO_H"},
+ {DAPM_MICBIAS2_EXTERNAL_STANDALONE, NULL, "LDO_H Standalone"},
};
static const struct snd_soc_dapm_route wcd9302_map[] = {
{"SPK DAC", "Switch", "RX3 MIX1"},
- {"RDAC4 MUX", "DEM3", "RX3 MIX1"},
- {"RDAC4 MUX", "DEM2", "RX2 CHAIN"},
- {"LINEOUT1 DAC", NULL, "RDAC4 MUX"},
{"RDAC5 MUX", "DEM4", "RX3 MIX1"},
{"RDAC5 MUX", "DEM3_INV", "RDAC4 MUX"},
@@ -4167,7 +4283,7 @@
SND_SOC_DAPM_MUX("RX4 MIX1 INP2", SND_SOC_NOPM, 0, 0,
&rx4_mix1_inp2_mux),
SND_SOC_DAPM_MUX("RX4 MIX1 INP3", SND_SOC_NOPM, 0, 0,
- &rx4_mix1_inp2_mux),
+ &rx4_mix1_inp3_mux),
/* RX4 MIX2 mux inputs */
SND_SOC_DAPM_MUX("RX4 MIX2 INP1", SND_SOC_NOPM, 0, 0,
@@ -4224,13 +4340,13 @@
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("ANC1 FB MUX", SND_SOC_NOPM, 0, 0, &anc1_fb_mux),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 External", TAPAN_A_MICB_3_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 External", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal1", TAPAN_A_MICB_3_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal1", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal2", TAPAN_A_MICB_3_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS3 Internal2", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
@@ -4453,17 +4569,27 @@
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
- SND_SOC_DAPM_SUPPLY("LDO_H", TAPAN_A_LDO_H_MODE_1, 7, 0,
- tapan_codec_enable_ldo_h, SND_SOC_DAPM_POST_PMU),
+ SND_SOC_DAPM_SUPPLY("LDO_H", SND_SOC_NOPM, 7, 0,
+ tapan_codec_enable_ldo_h,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+ /*
+ * DAPM 'LDO_H Standalone' is to be powered by mbhc driver after
+ * acquring codec_resource lock.
+ * So call __tapan_codec_enable_ldo_h instead and avoid deadlock.
+ */
+ SND_SOC_DAPM_SUPPLY("LDO_H Standalone", SND_SOC_NOPM, 7, 0,
+ __tapan_codec_enable_ldo_h,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("AMIC1"),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 External", TAPAN_A_MICB_1_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 External", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal1", TAPAN_A_MICB_1_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal1", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal2", TAPAN_A_MICB_1_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS1 Internal2", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
@@ -4485,19 +4611,24 @@
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_INPUT("AMIC2"),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 External", TAPAN_A_MICB_2_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 External", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal1", TAPAN_A_MICB_2_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal1", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal2", TAPAN_A_MICB_2_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal2", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
- SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal3", TAPAN_A_MICB_2_CTL, 7, 0,
+ SND_SOC_DAPM_MICBIAS_E("MIC BIAS2 Internal3", SND_SOC_NOPM, 7, 0,
tapan_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_MICBIAS_E(DAPM_MICBIAS2_EXTERNAL_STANDALONE, SND_SOC_NOPM,
+ 7, 0, tapan_codec_enable_micbias,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+ SND_SOC_DAPM_POST_PMD),
+
SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
AIF1_CAP, 0, tapan_codec_enable_slimtx,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
@@ -5495,7 +5626,8 @@
else
rco_clk_rate = TAPAN_MCLK_CLK_9P6MHZ;
- ret = wcd9xxx_mbhc_init(&tapan->mbhc, &tapan->resmgr, codec, NULL,
+ ret = wcd9xxx_mbhc_init(&tapan->mbhc, &tapan->resmgr, codec,
+ tapan_enable_mbhc_micbias,
&mbhc_cb, &cdc_intr_ids, rco_clk_rate,
TAPAN_CDC_ZDET_SUPPORTED);
if (ret)
@@ -5702,7 +5834,8 @@
else
rco_clk_rate = TAPAN_MCLK_CLK_9P6MHZ;
- ret = wcd9xxx_mbhc_init(&tapan->mbhc, &tapan->resmgr, codec, NULL,
+ ret = wcd9xxx_mbhc_init(&tapan->mbhc, &tapan->resmgr, codec,
+ tapan_enable_mbhc_micbias,
&mbhc_cb, &cdc_intr_ids, rco_clk_rate,
TAPAN_CDC_ZDET_SUPPORTED);
@@ -5720,6 +5853,8 @@
tapan->aux_pga_cnt = 0;
tapan->aux_l_gain = 0x1F;
tapan->aux_r_gain = 0x1F;
+ tapan->ldo_h_users = 0;
+ tapan->micb_2_users = 0;
tapan_update_reg_defaults(codec);
tapan_update_reg_mclk_rate(wcd9xxx);
tapan_codec_init_reg(codec);
diff --git a/sound/soc/codecs/wcd9320.c b/sound/soc/codecs/wcd9320.c
index 6dc2ec0..c62f875 100644
--- a/sound/soc/codecs/wcd9320.c
+++ b/sound/soc/codecs/wcd9320.c
@@ -260,6 +260,8 @@
#define TAIKO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
+#define TAIKO_SLIM_PGD_PORT_INT_TX_EN0 (TAIKO_SLIM_PGD_PORT_INT_EN0 + 2)
+
enum {
AIF1_PB = 0,
AIF1_CAP,
@@ -4884,6 +4886,46 @@
return ret;
}
+static void taiko_codec_enable_int_port(struct wcd9xxx_codec_dai_data *dai,
+ struct snd_soc_codec *codec)
+{
+ struct wcd9xxx_ch *ch;
+ int port_num = 0;
+ unsigned short reg = 0;
+ u8 val = 0;
+ if (!dai || !codec) {
+ pr_err("%s: Invalid params\n", __func__);
+ return;
+ }
+ list_for_each_entry(ch, &dai->wcd9xxx_ch_list, list) {
+ if (ch->port >= TAIKO_RX_PORT_START_NUMBER) {
+ port_num = ch->port - TAIKO_RX_PORT_START_NUMBER;
+ reg = TAIKO_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
+ val = wcd9xxx_interface_reg_read(codec->control_data,
+ reg);
+ if (!(val & (1 << (port_num % 8)))) {
+ val |= (1 << (port_num % 8));
+ wcd9xxx_interface_reg_write(
+ codec->control_data, reg, val);
+ val = wcd9xxx_interface_reg_read(
+ codec->control_data, reg);
+ }
+ } else {
+ port_num = ch->port;
+ reg = TAIKO_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
+ val = wcd9xxx_interface_reg_read(codec->control_data,
+ reg);
+ if (!(val & (1 << (port_num % 8)))) {
+ val |= (1 << (port_num % 8));
+ wcd9xxx_interface_reg_write(codec->control_data,
+ reg, val);
+ val = wcd9xxx_interface_reg_read(
+ codec->control_data, reg);
+ }
+ }
+ }
+}
+
static int taiko_codec_enable_slimrx(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol,
int event)
@@ -4910,6 +4952,7 @@
switch (event) {
case SND_SOC_DAPM_POST_PMU:
+ taiko_codec_enable_int_port(dai, codec);
(void) taiko_codec_enable_slim_chmask(dai, true);
ret = wcd9xxx_cfg_slim_sch_rx(core, &dai->wcd9xxx_ch_list,
dai->rate, dai->bit_width,
@@ -4974,6 +5017,7 @@
/*Enable spkr VI clocks*/
snd_soc_update_bits(codec,
TAIKO_A_CDC_CLK_TX_CLK_EN_B2_CTL, 0xC, 0xC);
+ taiko_codec_enable_int_port(dai, codec);
(void) taiko_codec_enable_slim_chmask(dai, true);
ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
dai->rate, dai->bit_width,
@@ -5021,6 +5065,7 @@
dai = &taiko_p->dai[w->shift];
switch (event) {
case SND_SOC_DAPM_POST_PMU:
+ taiko_codec_enable_int_port(dai, codec);
(void) taiko_codec_enable_slim_chmask(dai, true);
ret = wcd9xxx_cfg_slim_sch_tx(core, &dai->wcd9xxx_ch_list,
dai->rate, dai->bit_width,
@@ -5629,8 +5674,9 @@
unsigned long status = 0;
int i, j, port_id, k;
u32 bit;
- u8 val;
+ u8 val, int_val = 0;
bool tx, cleared;
+ unsigned short reg = 0;
for (i = TAIKO_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
i <= TAIKO_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
@@ -5645,12 +5691,28 @@
TAIKO_SLIM_PGD_PORT_INT_RX_SOURCE0 + j);
if (val & TAIKO_SLIM_IRQ_OVERFLOW)
pr_err_ratelimited(
- "%s: overflow error on %s port %d, value %x\n",
- __func__, (tx ? "TX" : "RX"), port_id, val);
+ "%s: overflow error on %s port %d, value %x\n",
+ __func__, (tx ? "TX" : "RX"), port_id, val);
if (val & TAIKO_SLIM_IRQ_UNDERFLOW)
pr_err_ratelimited(
- "%s: underflow error on %s port %d, value %x\n",
- __func__, (tx ? "TX" : "RX"), port_id, val);
+ "%s: underflow error on %s port %d, value %x\n",
+ __func__, (tx ? "TX" : "RX"), port_id, val);
+ if ((val & TAIKO_SLIM_IRQ_OVERFLOW) ||
+ (val & TAIKO_SLIM_IRQ_UNDERFLOW)) {
+ if (!tx)
+ reg = TAIKO_SLIM_PGD_PORT_INT_EN0 +
+ (port_id / 8);
+ else
+ reg = TAIKO_SLIM_PGD_PORT_INT_TX_EN0 +
+ (port_id / 8);
+ int_val = wcd9xxx_interface_reg_read(
+ codec->control_data, reg);
+ if (int_val & (1 << (port_id % 8))) {
+ int_val = int_val ^ (1 << (port_id % 8));
+ wcd9xxx_interface_reg_write(codec->control_data,
+ reg, int_val);
+ }
+ }
if (val & TAIKO_SLIM_IRQ_PORT_CLOSED) {
/*
* INT SOURCE register starts from RX to TX
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.c b/sound/soc/codecs/wcd9xxx-mbhc.c
index ec99c5f..14218d8 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.c
+++ b/sound/soc/codecs/wcd9xxx-mbhc.c
@@ -90,7 +90,7 @@
#define WCD9XXX_HPHL_STATUS_READY_WAIT_US 1000
#define WCD9XXX_MUX_SWITCH_READY_WAIT_MS 50
-#define WCD9XXX_MEAS_DELTA_MAX_MV 50
+#define WCD9XXX_MEAS_DELTA_MAX_MV 120
#define WCD9XXX_MEAS_INVALD_RANGE_LOW_MV 20
#define WCD9XXX_MEAS_INVALD_RANGE_HIGH_MV 80
@@ -128,7 +128,7 @@
S_IRUGO | S_IWUSR | S_IWGRP);
MODULE_PARM_DESC(impedance_detect_en, "enable/disable impedance detect");
-static bool detect_use_vddio_switch = true;
+static bool detect_use_vddio_switch;
struct wcd9xxx_mbhc_detect {
u16 dce;
@@ -213,7 +213,6 @@
/* called under codec_resource_lock acquisition */
static void wcd9xxx_start_hs_polling(struct wcd9xxx_mbhc *mbhc)
{
- s16 v_brh, v_b1_hu;
struct snd_soc_codec *codec = mbhc->codec;
int mbhc_state = mbhc->mbhc_state;
@@ -227,7 +226,7 @@
* setup internal micbias if codec uses internal micbias for
* headset detection
*/
- if (mbhc->mbhc_cfg->use_int_rbias && !mbhc->int_rbias_on) {
+ if (mbhc->mbhc_cfg->use_int_rbias) {
if (mbhc->mbhc_cb && mbhc->mbhc_cb->setup_int_rbias)
mbhc->mbhc_cb->setup_int_rbias(codec, true);
else
@@ -254,17 +253,6 @@
/* set to max */
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL, 0x7F);
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL, 0xFF);
-
- v_brh = wcd9xxx_get_current_v(mbhc, WCD9XXX_CURRENT_V_BR_H);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL,
- (v_brh >> 8) & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL,
- v_brh & 0xFF);
- v_b1_hu = wcd9xxx_get_current_v(mbhc, WCD9XXX_CURRENT_V_B1_HU);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL,
- v_b1_hu & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL,
- (v_b1_hu >> 8) & 0xFF);
}
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_EN_CTL, 0x1);
@@ -325,22 +313,32 @@
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL,
(d->v_ins_hu[MBHC_V_IDX_VDDIO] >> 8) &
0xFF);
- /* Threshods for button press */
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL,
- d->v_b1_hu[MBHC_V_IDX_VDDIO] & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL,
- (d->v_b1_hu[MBHC_V_IDX_VDDIO] >> 8) &
- 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL,
- d->v_b1_h[MBHC_V_IDX_VDDIO] & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL,
- (d->v_b1_h[MBHC_V_IDX_VDDIO] >> 8) &
- 0xFF);
- /* Threshods for button release */
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL,
- d->v_brh[MBHC_V_IDX_VDDIO] & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL,
- (d->v_brh[MBHC_V_IDX_VDDIO] >> 8) & 0xFF);
+
+ if (mbhc->mbhc_state != MBHC_STATE_POTENTIAL_RECOVERY) {
+ /* Threshods for button press */
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL,
+ d->v_b1_hu[MBHC_V_IDX_VDDIO] & 0xFF);
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL,
+ (d->v_b1_hu[MBHC_V_IDX_VDDIO] >> 8) &
+ 0xFF);
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL,
+ d->v_b1_h[MBHC_V_IDX_VDDIO] & 0xFF);
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL,
+ (d->v_b1_h[MBHC_V_IDX_VDDIO] >> 8) &
+ 0xFF);
+ /* Threshods for button release */
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL,
+ d->v_brh[MBHC_V_IDX_VDDIO] & 0xFF);
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL,
+ (d->v_brh[MBHC_V_IDX_VDDIO] >> 8) &
+ 0xFF);
+ }
pr_debug("%s: Programmed MBHC thresholds to VDDIO\n",
__func__);
}
@@ -376,22 +374,31 @@
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL,
(d->v_ins_hu[MBHC_V_IDX_CFILT] >> 8) &
0xFF);
- /* Revert threshods for button press */
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL,
- d->v_b1_hu[MBHC_V_IDX_CFILT] & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL,
- (d->v_b1_hu[MBHC_V_IDX_CFILT] >> 8) &
- 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL,
- d->v_b1_h[MBHC_V_IDX_CFILT] & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL,
- (d->v_b1_h[MBHC_V_IDX_CFILT] >> 8) &
- 0xFF);
- /* Revert threshods for button release */
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL,
- d->v_brh[MBHC_V_IDX_CFILT] & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL,
- (d->v_brh[MBHC_V_IDX_CFILT] >> 8) & 0xFF);
+ if (mbhc->mbhc_state != MBHC_STATE_POTENTIAL_RECOVERY) {
+ /* Revert threshods for button press */
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL,
+ d->v_b1_hu[MBHC_V_IDX_CFILT] & 0xFF);
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL,
+ (d->v_b1_hu[MBHC_V_IDX_CFILT] >> 8) &
+ 0xFF);
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL,
+ d->v_b1_h[MBHC_V_IDX_CFILT] & 0xFF);
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL,
+ (d->v_b1_h[MBHC_V_IDX_CFILT] >> 8) &
+ 0xFF);
+ /* Revert threshods for button release */
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL,
+ d->v_brh[MBHC_V_IDX_CFILT] & 0xFF);
+ snd_soc_write(codec,
+ WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL,
+ (d->v_brh[MBHC_V_IDX_CFILT] >> 8) &
+ 0xFF);
+ }
pr_debug("%s: Programmed MBHC thresholds to MICBIAS\n",
__func__);
}
@@ -489,19 +496,25 @@
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL, v_ins_hu & 0xFF);
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL,
(v_ins_hu >> 8) & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL, v_b1_hu & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL,
- (v_b1_hu >> 8) & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL, v_b1_h & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL,
- (v_b1_h >> 8) & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL, v_brh & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL,
- (v_brh >> 8) & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL,
- mbhc->mbhc_data.v_brl & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL,
- (mbhc->mbhc_data.v_brl >> 8) & 0xFF);
+
+ if (mbhc->mbhc_state != MBHC_STATE_POTENTIAL_RECOVERY) {
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL, v_b1_hu &
+ 0xFF);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL,
+ (v_b1_hu >> 8) & 0xFF);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL, v_b1_h &
+ 0xFF);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL,
+ (v_b1_h >> 8) & 0xFF);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL, v_brh &
+ 0xFF);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL,
+ (v_brh >> 8) & 0xFF);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL,
+ mbhc->mbhc_data.v_brl & 0xFF);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL,
+ (mbhc->mbhc_data.v_brl >> 8) & 0xFF);
+ }
}
static void wcd9xxx_codec_switch_cfilt_mode(struct wcd9xxx_mbhc *mbhc,
@@ -841,7 +854,8 @@
mbhc->zl = mbhc->zr = 0;
wcd9xxx_jack_report(mbhc, &mbhc->headset_jack,
0, WCD9XXX_JACK_MASK);
- mbhc->hph_status = 0;
+ mbhc->hph_status &= ~(SND_JACK_HEADSET |
+ SND_JACK_LINEOUT);
}
/* Report insertion */
mbhc->hph_status |= jack_type;
@@ -972,7 +986,9 @@
if (noreldetection)
wcd9xxx_turn_onoff_rel_detection(codec, false);
- snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL, 0x2, 0x0);
+ if (mbhc->mbhc_cfg->do_recalibration)
+ snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL, 0x2,
+ 0x0);
/* Turn on the override */
if (!override_bypass)
snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_B1_CTL, 0x4, 0x4);
@@ -982,8 +998,9 @@
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_EN_CTL, 0x4);
snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL, 0x8,
0x0);
- snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL, 0x2,
- 0x2);
+ if (mbhc->mbhc_cfg->do_recalibration)
+ snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL,
+ 0x2, 0x2);
usleep_range(mbhc->mbhc_data.t_sta_dce,
mbhc->mbhc_data.t_sta_dce);
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_EN_CTL, 0x4);
@@ -995,8 +1012,9 @@
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_EN_CTL, 0x2);
snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL, 0x8,
0x0);
- snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL, 0x2,
- 0x2);
+ if (mbhc->mbhc_cfg->do_recalibration)
+ snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL,
+ 0x2, 0x2);
usleep_range(mbhc->mbhc_data.t_sta_dce,
mbhc->mbhc_data.t_sta_dce);
snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_EN_CTL, 0x2);
@@ -1103,7 +1121,7 @@
* setup internal micbias if codec uses internal micbias for
* headset detection
*/
- if (mbhc->mbhc_cfg->use_int_rbias && !mbhc->int_rbias_on) {
+ if (mbhc->mbhc_cfg->use_int_rbias) {
if (mbhc->mbhc_cb && mbhc->mbhc_cb->setup_int_rbias)
mbhc->mbhc_cb->setup_int_rbias(codec, true);
else
@@ -1140,48 +1158,59 @@
snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_B1_CTL, 0x2, 0x2);
snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_CLK_CTL, 0x8, 0x8);
+ if (!mbhc->mbhc_cfg->do_recalibration) {
+ if (!is_cs_enable)
+ wcd9xxx_calibrate_hs_polling(mbhc);
+ }
+
/* don't flip override */
bias_value = __wcd9xxx_codec_sta_dce(mbhc, 1, true, true);
snd_soc_write(codec, mbhc->mbhc_bias_regs.cfilt_ctl, cfilt_mode);
snd_soc_update_bits(codec, WCD9XXX_A_MBHC_HPH, 0x13, 0x00);
- /* recalibrate dce_z and sta_z */
- reg = snd_soc_read(codec, WCD9XXX_A_CDC_MBHC_B1_CTL);
- change = snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_B1_CTL, 0x78,
- btn_det->mbhc_nsc << 3);
- wcd9xxx_get_z(mbhc, &dce_z, &sta_z);
- if (change)
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_B1_CTL, reg);
- if (dce_z && sta_z) {
- pr_debug("%s: sta_z 0x%x -> 0x%x, dce_z 0x%x -> 0x%x\n",
- __func__,
- mbhc->mbhc_data.sta_z, sta_z & 0xffff,
- mbhc->mbhc_data.dce_z, dce_z & 0xffff);
- mbhc->mbhc_data.dce_z = dce_z;
- mbhc->mbhc_data.sta_z = sta_z;
- wcd9xxx_mbhc_calc_thres(mbhc);
- wcd9xxx_calibrate_hs_polling(mbhc);
- } else {
- pr_warn("%s: failed get new dce_z/sta_z 0x%x/0x%x\n", __func__,
- dce_z, sta_z);
- }
-
- if (is_cs_enable) {
- /* recalibrate dce_nsc_cs_z */
- reg = snd_soc_read(mbhc->codec, WCD9XXX_A_CDC_MBHC_B1_CTL);
- snd_soc_update_bits(mbhc->codec, WCD9XXX_A_CDC_MBHC_B1_CTL,
- 0x78, WCD9XXX_MBHC_NSC_CS << 3);
- wcd9xxx_get_z(mbhc, &dce_z, NULL);
- snd_soc_write(mbhc->codec, WCD9XXX_A_CDC_MBHC_B1_CTL, reg);
- if (dce_z) {
- pr_debug("%s: dce_nsc_cs_z 0x%x -> 0x%x\n", __func__,
- mbhc->mbhc_data.dce_nsc_cs_z, dce_z & 0xffff);
- mbhc->mbhc_data.dce_nsc_cs_z = dce_z;
+ if (mbhc->mbhc_cfg->do_recalibration) {
+ /* recalibrate dce_z and sta_z */
+ reg = snd_soc_read(codec, WCD9XXX_A_CDC_MBHC_B1_CTL);
+ change = snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_B1_CTL,
+ 0x78, btn_det->mbhc_nsc << 3);
+ wcd9xxx_get_z(mbhc, &dce_z, &sta_z);
+ if (change)
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_B1_CTL, reg);
+ if (dce_z && sta_z) {
+ pr_debug("%s: sta_z 0x%x -> 0x%x, dce_z 0x%x -> 0x%x\n",
+ __func__,
+ mbhc->mbhc_data.sta_z, sta_z & 0xffff,
+ mbhc->mbhc_data.dce_z, dce_z & 0xffff);
+ mbhc->mbhc_data.dce_z = dce_z;
+ mbhc->mbhc_data.sta_z = sta_z;
+ wcd9xxx_mbhc_calc_thres(mbhc);
+ wcd9xxx_calibrate_hs_polling(mbhc);
} else {
- pr_debug("%s: failed get new dce_nsc_cs_z\n", __func__);
+ pr_warn("%s: failed get new dce_z/sta_z 0x%x/0x%x\n",
+ __func__, dce_z, sta_z);
+ }
+
+ if (is_cs_enable) {
+ /* recalibrate dce_nsc_cs_z */
+ reg = snd_soc_read(mbhc->codec,
+ WCD9XXX_A_CDC_MBHC_B1_CTL);
+ snd_soc_update_bits(mbhc->codec,
+ WCD9XXX_A_CDC_MBHC_B1_CTL,
+ 0x78, WCD9XXX_MBHC_NSC_CS << 3);
+ wcd9xxx_get_z(mbhc, &dce_z, NULL);
+ snd_soc_write(mbhc->codec, WCD9XXX_A_CDC_MBHC_B1_CTL,
+ reg);
+ if (dce_z) {
+ pr_debug("%s: dce_nsc_cs_z 0x%x -> 0x%x\n",
+ __func__, mbhc->mbhc_data.dce_nsc_cs_z,
+ dce_z & 0xffff);
+ mbhc->mbhc_data.dce_nsc_cs_z = dce_z;
+ } else {
+ pr_debug("%s: failed get new dce_nsc_cs_z\n",
+ __func__);
+ }
}
}
-
return bias_value;
}
@@ -1751,6 +1780,7 @@
/* GND and MIC swap detection requires at least 2 rounds of DCE */
BUG_ON(NUM_DCE_PLUG_INS_DETECT < 2);
+ detect_use_vddio_switch = mbhc->mbhc_cfg->use_vddio_meas;
/*
* There are chances vddio switch is on and cfilt voltage is adjusted
@@ -2048,8 +2078,11 @@
pr_debug("%s: enter\n", __func__);
WCD9XXX_BCL_ASSERT_LOCKED(mbhc->resmgr);
- current_source_enable = ((mbhc->mbhc_cfg->cs_enable_flags &
- (1 << MBHC_CS_ENABLE_INSERTION)) != 0);
+
+ current_source_enable = (((mbhc->mbhc_cfg->cs_enable_flags &
+ (1 << MBHC_CS_ENABLE_INSERTION)) != 0) &&
+ (!(snd_soc_read(mbhc->codec,
+ mbhc->mbhc_bias_regs.ctl_reg) & 0x80)));
if (current_source_enable) {
wcd9xxx_turn_onoff_current_source(mbhc, true, false);
@@ -2174,9 +2207,10 @@
unsigned long retry = 0, timeout;
bool cs_enable;
- cs_enable = ((mbhc->mbhc_cfg->cs_enable_flags &
- (1 << MBHC_CS_ENABLE_REMOVAL)) != 0);
-
+ cs_enable = (((mbhc->mbhc_cfg->cs_enable_flags &
+ (1 << MBHC_CS_ENABLE_REMOVAL)) != 0) &&
+ (!(snd_soc_read(mbhc->codec,
+ mbhc->mbhc_bias_regs.ctl_reg) & 0x80)));
if (cs_enable)
wcd9xxx_turn_onoff_current_source(mbhc, true, false);
@@ -2688,8 +2722,11 @@
mbhc = container_of(work, struct wcd9xxx_mbhc, correct_plug_swch);
codec = mbhc->codec;
- current_source_enable = ((mbhc->mbhc_cfg->cs_enable_flags &
- (1 << MBHC_CS_ENABLE_POLLING)) != 0);
+
+ current_source_enable = (((mbhc->mbhc_cfg->cs_enable_flags &
+ (1 << MBHC_CS_ENABLE_POLLING)) != 0) &&
+ (!(snd_soc_read(codec,
+ mbhc->mbhc_bias_regs.ctl_reg) & 0x80)));
wcd9xxx_onoff_ext_mclk(mbhc, true);
@@ -3124,15 +3161,22 @@
mv = ceilmv + btn_det->v_btn_press_delta_cic;
pr_debug("%s: reprogram vb1hu/vbrh to %dmv\n", __func__, mv);
- /* update LSB first so mbhc hardware block doesn't see too low value */
- v_b1_hu = wcd9xxx_codec_v_sta_dce(mbhc, STA, mv, false);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL, v_b1_hu & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL,
- (v_b1_hu >> 8) & 0xFF);
- v_brh = wcd9xxx_codec_v_sta_dce(mbhc, DCE, mv, false);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL, v_brh & 0xFF);
- snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL,
- (v_brh >> 8) & 0xFF);
+ if (mbhc->mbhc_state != MBHC_STATE_POTENTIAL_RECOVERY) {
+ /*
+ * update LSB first so mbhc hardware block
+ * doesn't see too low value.
+ */
+ v_b1_hu = wcd9xxx_codec_v_sta_dce(mbhc, STA, mv, false);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL, v_b1_hu &
+ 0xFF);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL,
+ (v_b1_hu >> 8) & 0xFF);
+ v_brh = wcd9xxx_codec_v_sta_dce(mbhc, DCE, mv, false);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL, v_brh &
+ 0xFF);
+ snd_soc_write(codec, WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL,
+ (v_brh >> 8) & 0xFF);
+ }
return 0;
}
@@ -3188,7 +3232,7 @@
* setup internal micbias if codec uses internal micbias for
* headset detection
*/
- if (mbhc->mbhc_cfg->use_int_rbias && !mbhc->int_rbias_on) {
+ if (mbhc->mbhc_cfg->use_int_rbias) {
if (mbhc->mbhc_cb && mbhc->mbhc_cb->setup_int_rbias)
mbhc->mbhc_cb->setup_int_rbias(codec, true);
else
@@ -3218,7 +3262,9 @@
__func__);
if (mbhc->update_z) {
wcd9xxx_update_z(mbhc);
- mbhc->update_z = false;
+ dce_z = mbhc->mbhc_data.dce_z;
+ sta_z = mbhc->mbhc_data.sta_z;
+ mbhc->update_z = true;
}
stamv = __wcd9xxx_codec_sta_dce_v(mbhc, 0, sta, sta_z,
mbhc->mbhc_data.micb_mv);
@@ -3244,7 +3290,9 @@
if (mbhc->update_z) {
wcd9xxx_update_z(mbhc);
- mbhc->update_z = false;
+ dce_z = mbhc->mbhc_data.dce_z;
+ sta_z = mbhc->mbhc_data.sta_z;
+ mbhc->update_z = true;
}
stamv = __wcd9xxx_codec_sta_dce_v(mbhc, 0, sta, sta_z,
@@ -3718,6 +3766,7 @@
gain = wcd9xxx_mbhc_cal_btn_det_mp(btn_det, MBHC_BTN_DET_GAIN);
snd_soc_update_bits(codec, WCD9XXX_A_CDC_MBHC_B2_CTL, 0x78,
gain[idx] << 3);
+ snd_soc_update_bits(codec, WCD9XXX_A_MICB_2_MBHC, 0x04, 0x04);
pr_debug("%s: leave\n", __func__);
}
@@ -4019,7 +4068,6 @@
if (mbhc->mbhc_cfg->use_int_rbias) {
if (mbhc->mbhc_cb && mbhc->mbhc_cb->setup_int_rbias) {
mbhc->mbhc_cb->setup_int_rbias(codec, true);
- mbhc->int_rbias_on = true;
} else {
pr_info("%s: internal bias requested but codec did not provide callback\n",
__func__);
@@ -4178,7 +4226,6 @@
case WCD9XXX_EVENT_PRE_MICBIAS_2_ON:
case WCD9XXX_EVENT_PRE_MICBIAS_3_ON:
case WCD9XXX_EVENT_PRE_MICBIAS_4_ON:
- mbhc->int_rbias_on = true;
if (mbhc->mbhc_cfg && mbhc->mbhc_cfg->micbias ==
wcd9xxx_event_to_micbias(event)) {
wcd9xxx_switch_micbias(mbhc, 0);
@@ -4206,7 +4253,6 @@
case WCD9XXX_EVENT_POST_MICBIAS_2_OFF:
case WCD9XXX_EVENT_POST_MICBIAS_3_OFF:
case WCD9XXX_EVENT_POST_MICBIAS_4_OFF:
- mbhc->int_rbias_on = false;
if (mbhc->mbhc_cfg && mbhc->mbhc_cfg->micbias ==
wcd9xxx_event_to_micbias(event)) {
if (mbhc->event_state &
@@ -4238,7 +4284,8 @@
if (mbhc->hph_status & SND_JACK_OC_HPHL)
hphlocp_off_report(mbhc, SND_JACK_OC_HPHL);
if (!(mbhc->event_state &
- (1 << MBHC_EVENT_PA_HPHL | 1 << MBHC_EVENT_PA_HPHR)))
+ (1 << MBHC_EVENT_PA_HPHL | 1 << MBHC_EVENT_PA_HPHR |
+ 1 << MBHC_EVENT_PRE_TX_3_ON)))
wcd9xxx_switch_micbias(mbhc, 0);
break;
case WCD9XXX_EVENT_POST_HPHR_PA_OFF:
@@ -4249,7 +4296,8 @@
if (mbhc->hph_status & SND_JACK_OC_HPHR)
hphrocp_off_report(mbhc, SND_JACK_OC_HPHL);
if (!(mbhc->event_state &
- (1 << MBHC_EVENT_PA_HPHL | 1 << MBHC_EVENT_PA_HPHR)))
+ (1 << MBHC_EVENT_PA_HPHL | 1 << MBHC_EVENT_PA_HPHR |
+ 1 << MBHC_EVENT_PRE_TX_3_ON)))
wcd9xxx_switch_micbias(mbhc, 0);
break;
/* Clock usage change */
@@ -4331,6 +4379,28 @@
case WCD9XXX_EVENT_POST_BG_MBHC_ON:
/* Not used for now */
break;
+ case WCD9XXX_EVENT_PRE_TX_3_ON:
+ /*
+ * if polling is ON, mbhc micbias not enabled
+ * switch micbias source to VDDIO
+ */
+ set_bit(MBHC_EVENT_PRE_TX_3_ON, &mbhc->event_state);
+ if (!(snd_soc_read(codec, mbhc->mbhc_bias_regs.ctl_reg)
+ & 0x80) &&
+ mbhc->polling_active && !mbhc->mbhc_micbias_switched)
+ wcd9xxx_switch_micbias(mbhc, 1);
+ break;
+ case WCD9XXX_EVENT_POST_TX_3_OFF:
+ /*
+ * Switch back to micbias if HPH PA or TX3 path
+ * is disabled
+ */
+ clear_bit(MBHC_EVENT_PRE_TX_3_ON, &mbhc->event_state);
+ if (mbhc->polling_active && mbhc->mbhc_micbias_switched &&
+ !(mbhc->event_state & (1 << MBHC_EVENT_PA_HPHL |
+ 1 << MBHC_EVENT_PA_HPHR)))
+ wcd9xxx_switch_micbias(mbhc, 0);
+ break;
default:
WARN(1, "Unknown event %d\n", event);
ret = -EINVAL;
@@ -4502,7 +4572,6 @@
mbhc->mbhc_cb = mbhc_cb;
mbhc->intr_ids = mbhc_cdc_intr_ids;
mbhc->impedance_detect = impedance_det_en;
- mbhc->int_rbias_on = false;
if (mbhc->intr_ids == NULL) {
pr_err("%s: Interrupt mapping not provided\n", __func__);
diff --git a/sound/soc/codecs/wcd9xxx-mbhc.h b/sound/soc/codecs/wcd9xxx-mbhc.h
index 7fe9538..98f73fc 100644
--- a/sound/soc/codecs/wcd9xxx-mbhc.h
+++ b/sound/soc/codecs/wcd9xxx-mbhc.h
@@ -123,6 +123,8 @@
enum wcd9xxx_mbhc_event_state {
MBHC_EVENT_PA_HPHL,
MBHC_EVENT_PA_HPHR,
+ MBHC_EVENT_PRE_TX_3_ON,
+ MBHC_EVENT_POST_TX_3_OFF,
};
struct wcd9xxx_mbhc_general_cfg {
@@ -228,6 +230,8 @@
bool (*swap_gnd_mic) (struct snd_soc_codec *);
unsigned long cs_enable_flags;
bool use_int_rbias;
+ bool do_recalibration;
+ bool use_vddio_meas;
};
struct wcd9xxx_cfilt_mode {
@@ -336,7 +340,6 @@
u32 rco_clk_rate;
bool update_z;
- bool int_rbias_on;
/* Holds codec specific interrupt mapping */
const struct wcd9xxx_mbhc_intr *intr_ids;
diff --git a/sound/soc/codecs/wcd9xxx-resmgr.c b/sound/soc/codecs/wcd9xxx-resmgr.c
index 5d74469..e56b182 100644
--- a/sound/soc/codecs/wcd9xxx-resmgr.c
+++ b/sound/soc/codecs/wcd9xxx-resmgr.c
@@ -92,6 +92,9 @@
"WCD9XXX_EVENT_POST_RESUME",
+ "WCD9XXX_EVENT_PRE_TX_3_ON",
+ "WCD9XXX_EVENT_POST_TX_3_OFF",
+
"WCD9XXX_EVENT_LAST",
};
@@ -561,8 +564,15 @@
if (--resmgr->clk_rco_users == 0 &&
resmgr->clk_type == WCD9XXX_CLK_RCO) {
wcd9xxx_disable_clock_block(resmgr);
- snd_soc_update_bits(resmgr->codec,
- WCD9XXX_A_RC_OSC_FREQ, 0x80, 0x00);
+ /* if RCO is enabled, switch from it */
+ if (snd_soc_read(resmgr->codec, WCD9XXX_A_RC_OSC_FREQ)
+ & 0x80) {
+ if (resmgr->codec_type !=
+ WCD9XXX_CDC_TYPE_HELICON)
+ snd_soc_write(resmgr->codec,
+ WCD9XXX_A_CLK_BUFF_EN2, 0x02);
+ wcd9xxx_resmgr_enable_config_mode(resmgr, 0);
+ }
resmgr->clk_type = WCD9XXX_CLK_OFF;
}
break;
diff --git a/sound/soc/codecs/wcd9xxx-resmgr.h b/sound/soc/codecs/wcd9xxx-resmgr.h
index 603bd1e..9f383b6 100644
--- a/sound/soc/codecs/wcd9xxx-resmgr.h
+++ b/sound/soc/codecs/wcd9xxx-resmgr.h
@@ -105,6 +105,9 @@
WCD9XXX_EVENT_POST_RESUME,
+ WCD9XXX_EVENT_PRE_TX_3_ON,
+ WCD9XXX_EVENT_POST_TX_3_OFF,
+
WCD9XXX_EVENT_LAST,
};
diff --git a/sound/soc/msm/apq8074.c b/sound/soc/msm/apq8074.c
index 3a055e2..5b12b9c 100644
--- a/sound/soc/msm/apq8074.c
+++ b/sound/soc/msm/apq8074.c
@@ -19,18 +19,22 @@
#include <linux/mfd/pm8xxx/pm8921.h>
#include <linux/qpnp/clkdiv.h>
#include <linux/regulator/consumer.h>
+#include <linux/io.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/pcm.h>
#include <sound/jack.h>
#include <sound/q6afe-v2.h>
-#include <asm/mach-types.h>
-#include <mach/socinfo.h>
#include <sound/pcm_params.h>
+#include <asm/mach-types.h>
+#include <mach/subsystem_notif.h>
+#include <mach/socinfo.h>
+
#include "qdsp6v2/msm-pcm-routing-v2.h"
+#include "qdsp6v2/q6core.h"
+#include "../codecs/wcd9xxx-common.h"
#include "../codecs/wcd9320.h"
-#include <linux/io.h>
#define DRV_NAME "apq8074-asoc-taiko"
@@ -82,6 +86,10 @@
#define NUM_OF_AUXPCM_GPIOS 4
+static void *adsp_state_notifier;
+
+#define ADSP_STATE_READY_TIMEOUT_MS 3000
+
static inline int param_is_mask(int p)
{
return ((p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
@@ -1230,6 +1238,101 @@
return true;
}
+static int msm_afe_set_config(struct snd_soc_codec *codec)
+{
+ int rc;
+ void *config_data;
+
+ pr_debug("%s: enter\n", __func__);
+ config_data = taiko_get_afe_config(codec, AFE_CDC_REGISTERS_CONFIG);
+ rc = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
+ if (rc) {
+ pr_err("%s: Failed to set codec registers config %d\n",
+ __func__, rc);
+ return rc;
+ }
+
+ config_data = taiko_get_afe_config(codec, AFE_SLIMBUS_SLAVE_CONFIG);
+ rc = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
+ if (rc) {
+ pr_err("%s: Failed to set slimbus slave config %d\n", __func__,
+ rc);
+ return rc;
+ }
+
+ return 0;
+}
+
+static void msm_afe_clear_config(void)
+{
+ afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
+ afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
+}
+
+static int msm8974_adsp_state_callback(struct notifier_block *nb,
+ unsigned long value, void *priv)
+{
+ if (value == SUBSYS_BEFORE_SHUTDOWN) {
+ pr_debug("%s: ADSP is about to shutdown. Clearing AFE config\n",
+ __func__);
+ msm_afe_clear_config();
+ } else if (value == SUBSYS_AFTER_POWERUP) {
+ pr_debug("%s: ADSP is up\n", __func__);
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block adsp_state_notifier_block = {
+ .notifier_call = msm8974_adsp_state_callback,
+ .priority = -INT_MAX,
+};
+
+static int msm8974_taiko_codec_up(struct snd_soc_codec *codec)
+{
+ int err;
+ unsigned long timeout;
+ int adsp_ready = 0;
+
+ timeout = jiffies +
+ msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
+
+ do {
+ if (!q6core_is_adsp_ready()) {
+ pr_err("%s: ADSP Audio isn't ready\n", __func__);
+ } else {
+ pr_debug("%s: ADSP Audio is ready\n", __func__);
+ adsp_ready = 1;
+ break;
+ }
+ } while (time_after(timeout, jiffies));
+
+ if (!adsp_ready) {
+ pr_err("%s: timed out waiting for ADSP Audio\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ err = msm_afe_set_config(codec);
+ if (err)
+ pr_err("%s: Failed to set AFE config. err %d\n",
+ __func__, err);
+ return err;
+}
+
+static int apq8074_taiko_event_cb(struct snd_soc_codec *codec,
+ enum wcd9xxx_codec_event codec_event)
+{
+ switch (codec_event) {
+ case WCD9XXX_CODEC_EVENT_CODEC_UP:
+ return msm8974_taiko_codec_up(codec);
+ break;
+ default:
+ pr_err("%s: UnSupported codec event %d\n",
+ __func__, codec_event);
+ return -EINVAL;
+ }
+}
+
static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
{
int err;
@@ -1291,19 +1394,9 @@
tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
- config_data = taiko_get_afe_config(codec, AFE_CDC_REGISTERS_CONFIG);
- err = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
+ err = msm_afe_set_config(codec);
if (err) {
- pr_err("%s: Failed to set codec registers config %d\n",
- __func__, err);
- goto out;
- }
-
- config_data = taiko_get_afe_config(codec, AFE_SLIMBUS_SLAVE_CONFIG);
- err = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
- if (err) {
- pr_err("%s: Failed to set slimbus slave config %d\n", __func__,
- err);
+ pr_err("%s: Failed to set AFE config %d\n", __func__, err);
goto out;
}
@@ -1340,12 +1433,23 @@
err = taiko_hs_detect(codec, &mbhc_cfg);
if (err)
goto out;
- else
- return err;
} else {
err = -ENOMEM;
goto out;
}
+ adsp_state_notifier =
+ subsys_notif_register_notifier("adsp",
+ &adsp_state_notifier_block);
+ if (!adsp_state_notifier) {
+ pr_err("%s: Failed to register adsp state notifier\n",
+ __func__);
+ err = -EFAULT;
+ taiko_hs_detect_exit(codec);
+ goto out;
+ }
+
+ taiko_event_register(apq8074_taiko_event_cb, rtd->codec);
+ return 0;
out:
clk_put(codec_clk);
return err;
diff --git a/sound/soc/msm/msm-dai-fe.c b/sound/soc/msm/msm-dai-fe.c
index 39cb470..6f94d99 100644
--- a/sound/soc/msm/msm-dai-fe.c
+++ b/sound/soc/msm/msm-dai-fe.c
@@ -422,6 +422,30 @@
},
{
.playback = {
+ .stream_name = "INT_HFP_BT Hostless Playback",
+ .aif_name = "INTHFP_DL_HL",
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 16000,
+ },
+ .capture = {
+ .stream_name = "INT_HFP_BT Hostless Capture",
+ .aif_name = "INTHFP_UL_HL",
+ .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
+ .channels_min = 1,
+ .channels_max = 2,
+ .rate_min = 8000,
+ .rate_max = 16000,
+ },
+ .ops = &msm_fe_dai_ops,
+ .name = "INT_HFP_BT_HOSTLESS",
+ },
+ {
+ .playback = {
.stream_name = "AFE-PROXY Playback",
.aif_name = "PCM_RX",
.rates = (SNDRV_PCM_RATE_8000 |
diff --git a/sound/soc/msm/msm8226.c b/sound/soc/msm/msm8226.c
index c25a460..b4ae0a4 100644
--- a/sound/soc/msm/msm8226.c
+++ b/sound/soc/msm/msm8226.c
@@ -94,6 +94,8 @@
.cs_enable_flags = (1 << MBHC_CS_ENABLE_POLLING |
1 << MBHC_CS_ENABLE_INSERTION |
1 << MBHC_CS_ENABLE_REMOVAL),
+ .do_recalibration = true,
+ .use_vddio_meas = true,
};
struct msm_auxpcm_gpio {
@@ -1418,6 +1420,21 @@
.codec_name = "snd-soc-dummy",
.be_id = MSM_FRONTEND_DAI_LSM1,
},
+ {
+ .name = "MSM8226 Compr8",
+ .stream_name = "COMPR8",
+ .cpu_dai_name = "MultiMedia8",
+ .platform_name = "msm-compr-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1,
+ /* this dainlink has playback support */
+ .be_id = MSM_FRONTEND_DAI_MULTIMEDIA8,
+ },
/* Backend BT/FM DAI Links */
{
.name = LPASS_BE_INT_BT_SCO_RX,
diff --git a/sound/soc/msm/msm8974.c b/sound/soc/msm/msm8974.c
index b34750a..69a6671 100644
--- a/sound/soc/msm/msm8974.c
+++ b/sound/soc/msm/msm8974.c
@@ -129,6 +129,8 @@
.cs_enable_flags = (1 << MBHC_CS_ENABLE_POLLING |
1 << MBHC_CS_ENABLE_INSERTION |
1 << MBHC_CS_ENABLE_REMOVAL),
+ .do_recalibration = true,
+ .use_vddio_meas = true,
};
struct msm_auxpcm_gpio {
@@ -2201,6 +2203,37 @@
.codec_name = "snd-soc-dummy",
},
{
+ .name = "INT_HFP_BT Hostless",
+ .stream_name = "INT_HFP_BT Hostless",
+ .cpu_dai_name = "INT_HFP_BT_HOSTLESS",
+ .platform_name = "msm-pcm-hostless",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ /* this dai link has playback support */
+ .ignore_pmdown_time = 1,
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ },
+ {
+ .name = "MSM8974 HFP TX",
+ .stream_name = "MultiMedia6",
+ .cpu_dai_name = "MultiMedia6",
+ .platform_name = "msm-pcm-loopback",
+ .dynamic = 1,
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .ignore_suspend = 1,
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ /* this dainlink has playback support */
+ .ignore_pmdown_time = 1,
+ .be_id = MSM_FRONTEND_DAI_MULTIMEDIA6,
+ },
+ {
.name = LPASS_BE_SLIMBUS_4_TX,
.stream_name = "Slimbus4 Capture",
.cpu_dai_name = "msm-dai-q6-dev.16393",
diff --git a/sound/soc/msm/msm8x10.c b/sound/soc/msm/msm8x10.c
index d9af6f3..c1ba26a 100644
--- a/sound/soc/msm/msm8x10.c
+++ b/sound/soc/msm/msm8x10.c
@@ -102,6 +102,8 @@
.cs_enable_flags = (1 << MBHC_CS_ENABLE_POLLING |
1 << MBHC_CS_ENABLE_INSERTION |
1 << MBHC_CS_ENABLE_REMOVAL),
+ .do_recalibration = false,
+ .use_vddio_meas = false,
};
/*
@@ -161,6 +163,8 @@
SND_SOC_DAPM_MIC("Handset Mic", NULL),
SND_SOC_DAPM_MIC("Headset Mic", NULL),
SND_SOC_DAPM_MIC("Secondary Mic", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic1", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic2", NULL),
};
static int msm8x10_ext_spk_power_amp_init(void)
{
diff --git a/sound/soc/msm/qdsp6v2/Makefile b/sound/soc/msm/qdsp6v2/Makefile
index 5aa84a0..f0f5db6 100644
--- a/sound/soc/msm/qdsp6v2/Makefile
+++ b/sound/soc/msm/qdsp6v2/Makefile
@@ -3,7 +3,8 @@
msm-multi-ch-pcm-q6-v2.o msm-pcm-lpa-v2.o \
msm-pcm-afe-v2.o msm-pcm-voip-v2.o \
msm-pcm-voice-v2.o msm-dai-q6-hdmi-v2.o \
- msm-lsm-client.o
+ msm-lsm-client.o msm-audio-effects-q6-v2.o \
+ msm-pcm-loopback-v2.o
obj-$(CONFIG_SND_SOC_QDSP6V2) += snd-soc-qdsp6v2.o msm-pcm-dtmf-v2.o \
msm-dai-stub-v2.o
obj-$(CONFIG_DOLBY_DAP) += msm-dolby-dap-config.o
diff --git a/sound/soc/msm/qdsp6v2/audio_acdb.c b/sound/soc/msm/qdsp6v2/audio_acdb.c
index 8187616..4e04bef 100644
--- a/sound/soc/msm/qdsp6v2/audio_acdb.c
+++ b/sound/soc/msm/qdsp6v2/audio_acdb.c
@@ -405,9 +405,9 @@
done:
mutex_unlock(&acdb_data.acdb_mutex);
-ret:
pr_debug("ACDB=> %s: Path = %d samplerate = %u usec = %u status %d\n",
__func__, path, entry->sample_rate, entry->delay_usec, result);
+ret:
return result;
}
@@ -718,11 +718,22 @@
int result = 0;
pr_debug("%s,\n", __func__);
+ if (cal_block == NULL) {
+ pr_err("ACDB=> NULL pointer sent to %s\n", __func__);
+ result = -EINVAL;
+ goto done;
+ }
if (cal_size > MAX_COL_SIZE) {
pr_err("%s: col size is to big %d\n", __func__, cal_size);
result = -EINVAL;
goto done;
}
+ if (acdb_data.col_data[vocproc_type] == NULL) {
+ pr_err("%s: vocproc_type %d data not allocated!\n",
+ __func__, vocproc_type);
+ result = -EINVAL;
+ goto done;
+ }
if (copy_from_user(acdb_data.col_data[vocproc_type],
(void *)((uint8_t *)cal_block + sizeof(cal_size)),
cal_size)) {
@@ -746,6 +757,12 @@
result = -EINVAL;
goto done;
}
+ if (acdb_data.col_data[vocproc_type] == NULL) {
+ pr_err("%s: vocproc_type %d data not allocated!\n",
+ __func__, vocproc_type);
+ result = -EINVAL;
+ goto done;
+ }
cal_block->cal_size = acdb_data.
vocproc_col_cal[vocproc_type].cal_size;
@@ -1042,8 +1059,19 @@
return result;
}
-static void allocate_hw_delay_entries(void)
+static void deallocate_hw_delay_entries(void)
{
+ kfree(acdb_data.hw_delay_rx.delay_info);
+ kfree(acdb_data.hw_delay_tx.delay_info);
+
+ acdb_data.hw_delay_rx.delay_info = NULL;
+ acdb_data.hw_delay_tx.delay_info = NULL;
+}
+
+static int allocate_hw_delay_entries(void)
+{
+ int result = 0;
+
/* Allocate memory for hw delay entries */
acdb_data.hw_delay_rx.num_entries = 0;
acdb_data.hw_delay_tx.num_entries = 0;
@@ -1054,6 +1082,8 @@
if (acdb_data.hw_delay_rx.delay_info == NULL) {
pr_err("%s : Failed to allocate av sync delay entries rx\n",
__func__);
+ result = -ENOMEM;
+ goto done;
}
acdb_data.hw_delay_tx.delay_info =
kmalloc(sizeof(struct hw_delay_entry)*
@@ -1062,7 +1092,44 @@
if (acdb_data.hw_delay_tx.delay_info == NULL) {
pr_err("%s : Failed to allocate av sync delay entries tx\n",
__func__);
+ deallocate_hw_delay_entries();
+ result = -ENOMEM;
+ goto done;
}
+done:
+ return result;
+}
+
+static void deallocate_col_data(void)
+{
+ int i;
+
+ for (i = 0; i < MAX_VOCPROC_TYPES; i++) {
+ kfree(acdb_data.col_data[i]);
+ acdb_data.col_data[i] = NULL;
+ }
+}
+
+static int allocate_col_data(void)
+{
+ int result = 0;
+ int i;
+
+ for (i = 0; i < MAX_VOCPROC_TYPES; i++) {
+ acdb_data.col_data[i] = kmalloc(MAX_COL_SIZE, GFP_KERNEL);
+ if (acdb_data.col_data[i] == NULL) {
+ pr_err("%s: kmalloc column data failed, type = %d\n",
+ __func__, i);
+ deallocate_col_data();
+ result = -ENOMEM;
+ goto done;
+ }
+ acdb_data.vocproc_col_cal[i].cal_kvaddr =
+ (uint32_t)acdb_data.col_data[i];
+ }
+
+done:
+ return result;
}
static int unmap_cal_tables(void)
@@ -1111,7 +1178,6 @@
static int deregister_memory(void)
{
int result = 0;
- int i;
pr_debug("%s\n", __func__);
if (acdb_data.mem_len == 0)
@@ -1130,13 +1196,8 @@
acdb_data.ion_client = NULL;
acdb_data.ion_handle = NULL;
- for (i = 0; i < MAX_VOCPROC_TYPES; i++) {
- kfree(acdb_data.col_data[i]);
- acdb_data.col_data[i] = NULL;
- }
-
- kfree(acdb_data.hw_delay_tx.delay_info);
- kfree(acdb_data.hw_delay_rx.delay_info);
+ deallocate_col_data();
+ deallocate_hw_delay_entries();
done:
return result;
}
@@ -1144,13 +1205,26 @@
static int register_memory(void)
{
int result;
- int i;
ion_phys_addr_t paddr;
void *kvptr;
unsigned long kvaddr;
unsigned long mem_len;
pr_debug("%s\n", __func__);
+ result = allocate_col_data();
+ if (result) {
+ pr_err("%s: allocate_col_data failed, rc = %d\n",
+ __func__, result);
+ goto err_done;
+ }
+
+ result = allocate_hw_delay_entries();
+ if (result) {
+ pr_err("%s: allocate_hw_delay_entries failed, rc = %d\n",
+ __func__, result);
+ goto err_col;
+ }
+
result = msm_audio_ion_import("audio_acdb_client",
&acdb_data.ion_client,
&acdb_data.ion_handle,
@@ -1160,15 +1234,7 @@
if (result) {
pr_err("%s: audio ION alloc failed, rc = %d\n",
__func__, result);
- goto err_ion_handle;
- }
-
- allocate_hw_delay_entries();
-
- for (i = 0; i < MAX_VOCPROC_TYPES; i++) {
- acdb_data.col_data[i] = kmalloc(MAX_COL_SIZE, GFP_KERNEL);
- acdb_data.vocproc_col_cal[i].cal_kvaddr =
- (uint32_t)acdb_data.col_data[i];
+ goto err_hw_delay;
}
kvaddr = (unsigned long)kvptr;
@@ -1181,7 +1247,11 @@
acdb_data.mem_len);
return result;
-err_ion_handle:
+err_hw_delay:
+ deallocate_hw_delay_entries();
+err_col:
+ deallocate_col_data();
+err_done:
acdb_data.mem_len = 0;
return result;
}
diff --git a/sound/soc/msm/qdsp6v2/msm-audio-effects-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-audio-effects-q6-v2.c
new file mode 100644
index 0000000..5e4d9d3
--- /dev/null
+++ b/sound/soc/msm/qdsp6v2/msm-audio-effects-q6-v2.c
@@ -0,0 +1,721 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <sound/apr_audio-v2.h>
+#include <sound/q6asm-v2.h>
+#include <sound/compress_params.h>
+#include "msm-audio-effects-q6-v2.h"
+
+int msm_audio_effects_virtualizer_handler(struct audio_client *ac,
+ struct virtualizer_params *virtualizer,
+ long *values)
+{
+ int devices = *values++;
+ int num_commands = *values++;
+ char *params;
+ int *updt_params, i, prev_enable_flag;
+ uint32_t params_length = (MAX_INBAND_PARAM_SZ);
+ int rc = 0;
+
+ pr_debug("%s\n", __func__);
+ if (!ac) {
+ pr_err("%s: cannot set audio effects\n", __func__);
+ return -EINVAL;
+ }
+ params = kzalloc(params_length, GFP_KERNEL);
+ if (!params) {
+ pr_err("%s, params memory alloc failed\n", __func__);
+ return -ENOMEM;
+ }
+ pr_debug("%s: device: %d\n", __func__, devices);
+ updt_params = (int *)params;
+ params_length = 0;
+ for (i = 0; i < num_commands; i++) {
+ uint32_t command_id = *values++;
+ uint32_t command_config_state = *values++;
+ uint32_t index_offset = *values++;
+ uint32_t length = *values++;
+ switch (command_id) {
+ case VIRTUALIZER_ENABLE:
+ pr_debug("%s: VIRTUALIZER_ENABLE\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ prev_enable_flag = virtualizer->enable_flag;
+ virtualizer->enable_flag = *values++;
+ if (prev_enable_flag != virtualizer->enable_flag) {
+ *updt_params++ = AUDPROC_MODULE_ID_VIRTUALIZER;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_VIRTUALIZER_ENABLE;
+ *updt_params++ = VIRTUALIZER_ENABLE_PARAM_SZ;
+ *updt_params++ = virtualizer->enable_flag;
+ params_length += COMMAND_PAYLOAD_SZ +
+ VIRTUALIZER_ENABLE_PARAM_SZ;
+ }
+ break;
+ case VIRTUALIZER_STRENGTH:
+ pr_debug("%s: VIRTUALIZER_STRENGTH\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ virtualizer->strength = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_VIRTUALIZER;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_VIRTUALIZER_STRENGTH;
+ *updt_params++ = VIRTUALIZER_STRENGTH_PARAM_SZ;
+ *updt_params++ = virtualizer->strength;
+ params_length += COMMAND_PAYLOAD_SZ +
+ VIRTUALIZER_STRENGTH_PARAM_SZ;
+ }
+ break;
+ case VIRTUALIZER_OUT_TYPE:
+ pr_debug("%s: VIRTUALIZER_OUT_TYPE\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ virtualizer->out_type = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_VIRTUALIZER;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_VIRTUALIZER_OUT_TYPE;
+ *updt_params++ = VIRTUALIZER_OUT_TYPE_PARAM_SZ;
+ *updt_params++ = virtualizer->out_type;
+ params_length += COMMAND_PAYLOAD_SZ +
+ VIRTUALIZER_OUT_TYPE_PARAM_SZ;
+ }
+ break;
+ case VIRTUALIZER_GAIN_ADJUST:
+ pr_debug("%s: VIRTUALIZER_GAIN_ADJUST\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ virtualizer->gain_adjust = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_VIRTUALIZER;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_VIRTUALIZER_GAIN_ADJUST;
+ *updt_params++ =
+ VIRTUALIZER_GAIN_ADJUST_PARAM_SZ;
+ *updt_params++ = virtualizer->gain_adjust;
+ params_length += COMMAND_PAYLOAD_SZ +
+ VIRTUALIZER_GAIN_ADJUST_PARAM_SZ;
+ }
+ break;
+ default:
+ pr_err("%s: Invalid command to set config\n", __func__);
+ break;
+ }
+ }
+ if (params_length)
+ q6asm_send_audio_effects_params(ac, params,
+ params_length);
+invalid_config:
+ kfree(params);
+ return rc;
+}
+
+int msm_audio_effects_reverb_handler(struct audio_client *ac,
+ struct reverb_params *reverb,
+ long *values)
+{
+ int devices = *values++;
+ int num_commands = *values++;
+ char *params;
+ int *updt_params, i, prev_enable_flag;
+ uint32_t params_length = (MAX_INBAND_PARAM_SZ);
+ int rc = 0;
+
+ pr_debug("%s\n", __func__);
+ if (!ac) {
+ pr_err("%s: cannot set audio effects\n", __func__);
+ return -EINVAL;
+ }
+ params = kzalloc(params_length, GFP_KERNEL);
+ if (!params) {
+ pr_err("%s, params memory alloc failed\n", __func__);
+ return -ENOMEM;
+ }
+ pr_debug("%s: device: %d\n", __func__, devices);
+ updt_params = (int *)params;
+ params_length = 0;
+ for (i = 0; i < num_commands; i++) {
+ uint32_t command_id = *values++;
+ uint32_t command_config_state = *values++;
+ uint32_t index_offset = *values++;
+ uint32_t length = *values++;
+ switch (command_id) {
+ case REVERB_ENABLE:
+ pr_debug("%s: REVERB_ENABLE\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ prev_enable_flag = reverb->enable_flag;
+ reverb->enable_flag = *values++;
+ if (prev_enable_flag != reverb->enable_flag) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ = AUDPROC_PARAM_ID_REVERB_ENABLE;
+ *updt_params++ = REVERB_ENABLE_PARAM_SZ;
+ *updt_params++ = reverb->enable_flag;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_ENABLE_PARAM_SZ;
+ }
+ break;
+ case REVERB_MODE:
+ pr_debug("%s: REVERB_MODE\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->mode = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ = AUDPROC_PARAM_ID_REVERB_MODE;
+ *updt_params++ = REVERB_MODE_PARAM_SZ;
+ *updt_params++ = reverb->mode;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_MODE_PARAM_SZ;
+ }
+ break;
+ case REVERB_PRESET:
+ pr_debug("%s: REVERB_PRESET\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->preset = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ = AUDPROC_PARAM_ID_REVERB_PRESET;
+ *updt_params++ = REVERB_PRESET_PARAM_SZ;
+ *updt_params++ = reverb->preset;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_PRESET_PARAM_SZ;
+ }
+ break;
+ case REVERB_WET_MIX:
+ pr_debug("%s: REVERB_WET_MIX\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->wet_mix = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_WET_MIX;
+ *updt_params++ = REVERB_WET_MIX_PARAM_SZ;
+ *updt_params++ = reverb->wet_mix;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_WET_MIX_PARAM_SZ;
+ }
+ break;
+ case REVERB_GAIN_ADJUST:
+ pr_debug("%s: REVERB_GAIN_ADJUST\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->gain_adjust = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_GAIN_ADJUST;
+ *updt_params++ = REVERB_GAIN_ADJUST_PARAM_SZ;
+ *updt_params++ = reverb->gain_adjust;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_GAIN_ADJUST_PARAM_SZ;
+ }
+ break;
+ case REVERB_ROOM_LEVEL:
+ pr_debug("%s: REVERB_ROOM_LEVEL\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->room_level = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_ROOM_LEVEL;
+ *updt_params++ = REVERB_ROOM_LEVEL_PARAM_SZ;
+ *updt_params++ = reverb->room_level;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_ROOM_LEVEL_PARAM_SZ;
+ }
+ break;
+ case REVERB_ROOM_HF_LEVEL:
+ pr_debug("%s: REVERB_ROOM_HF_LEVEL\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->room_hf_level = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_ROOM_HF_LEVEL;
+ *updt_params++ = REVERB_ROOM_HF_LEVEL_PARAM_SZ;
+ *updt_params++ = reverb->room_hf_level;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_ROOM_HF_LEVEL_PARAM_SZ;
+ }
+ break;
+ case REVERB_DECAY_TIME:
+ pr_debug("%s: REVERB_DECAY_TIME\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->decay_time = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_DECAY_TIME;
+ *updt_params++ = REVERB_DECAY_TIME_PARAM_SZ;
+ *updt_params++ = reverb->decay_time;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_DECAY_TIME_PARAM_SZ;
+ }
+ break;
+ case REVERB_DECAY_HF_RATIO:
+ pr_debug("%s: REVERB_DECAY_HF_RATIO\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->decay_hf_ratio = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_DECAY_HF_RATIO;
+ *updt_params++ = REVERB_DECAY_HF_RATIO_PARAM_SZ;
+ *updt_params++ = reverb->decay_hf_ratio;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_DECAY_HF_RATIO_PARAM_SZ;
+ }
+ break;
+ case REVERB_REFLECTIONS_LEVEL:
+ pr_debug("%s: REVERB_REFLECTIONS_LEVEL\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->reflections_level = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_REFLECTIONS_LEVEL;
+ *updt_params++ =
+ REVERB_REFLECTIONS_LEVEL_PARAM_SZ;
+ *updt_params++ = reverb->reflections_level;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_REFLECTIONS_LEVEL_PARAM_SZ;
+ }
+ break;
+ case REVERB_REFLECTIONS_DELAY:
+ pr_debug("%s: REVERB_REFLECTIONS_DELAY\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->reflections_delay = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_REFLECTIONS_DELAY;
+ *updt_params++ =
+ REVERB_REFLECTIONS_DELAY_PARAM_SZ;
+ *updt_params++ = reverb->reflections_delay;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_REFLECTIONS_DELAY_PARAM_SZ;
+ }
+ break;
+ case REVERB_LEVEL:
+ pr_debug("%s: REVERB_LEVEL\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->level = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ = AUDPROC_PARAM_ID_REVERB_LEVEL;
+ *updt_params++ = REVERB_LEVEL_PARAM_SZ;
+ *updt_params++ = reverb->level;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_LEVEL_PARAM_SZ;
+ }
+ break;
+ case REVERB_DELAY:
+ pr_debug("%s: REVERB_DELAY\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->delay = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ = AUDPROC_PARAM_ID_REVERB_DELAY;
+ *updt_params++ = REVERB_DELAY_PARAM_SZ;
+ *updt_params++ = reverb->delay;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_DELAY_PARAM_SZ;
+ }
+ break;
+ case REVERB_DIFFUSION:
+ pr_debug("%s: REVERB_DIFFUSION\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->diffusion = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_DIFFUSION;
+ *updt_params++ = REVERB_DIFFUSION_PARAM_SZ;
+ *updt_params++ = reverb->diffusion;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_DIFFUSION_PARAM_SZ;
+ }
+ break;
+ case REVERB_DENSITY:
+ pr_debug("%s: REVERB_DENSITY\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ reverb->density = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_REVERB;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_REVERB_DENSITY;
+ *updt_params++ = REVERB_DENSITY_PARAM_SZ;
+ *updt_params++ = reverb->density;
+ params_length += COMMAND_PAYLOAD_SZ +
+ REVERB_DENSITY_PARAM_SZ;
+ }
+ break;
+ default:
+ pr_err("%s: Invalid command to set config\n", __func__);
+ break;
+ }
+ }
+ if (params_length)
+ q6asm_send_audio_effects_params(ac, params,
+ params_length);
+invalid_config:
+ kfree(params);
+ return rc;
+}
+
+int msm_audio_effects_bass_boost_handler(struct audio_client *ac,
+ struct bass_boost_params *bass_boost,
+ long *values)
+{
+ int devices = *values++;
+ int num_commands = *values++;
+ char *params;
+ int *updt_params, i, prev_enable_flag;
+ uint32_t params_length = (MAX_INBAND_PARAM_SZ);
+ int rc = 0;
+
+ pr_debug("%s\n", __func__);
+ if (!ac) {
+ pr_err("%s: cannot set audio effects\n", __func__);
+ return -EINVAL;
+ }
+ params = kzalloc(params_length, GFP_KERNEL);
+ if (!params) {
+ pr_err("%s, params memory alloc failed\n", __func__);
+ return -ENOMEM;
+ }
+ pr_debug("%s: device: %d\n", __func__, devices);
+ updt_params = (int *)params;
+ params_length = 0;
+ for (i = 0; i < num_commands; i++) {
+ uint32_t command_id = *values++;
+ uint32_t command_config_state = *values++;
+ uint32_t index_offset = *values++;
+ uint32_t length = *values++;
+ switch (command_id) {
+ case BASS_BOOST_ENABLE:
+ pr_debug("%s: BASS_BOOST_ENABLE\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ prev_enable_flag = bass_boost->enable_flag;
+ bass_boost->enable_flag = *values++;
+ if (prev_enable_flag != bass_boost->enable_flag) {
+ *updt_params++ = AUDPROC_MODULE_ID_BASS_BOOST;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_BASS_BOOST_ENABLE;
+ *updt_params++ = BASS_BOOST_ENABLE_PARAM_SZ;
+ *updt_params++ = bass_boost->enable_flag;
+ params_length += COMMAND_PAYLOAD_SZ +
+ BASS_BOOST_ENABLE_PARAM_SZ;
+ }
+ break;
+ case BASS_BOOST_MODE:
+ pr_debug("%s: BASS_BOOST_MODE\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ bass_boost->mode = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_BASS_BOOST;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_BASS_BOOST_MODE;
+ *updt_params++ = BASS_BOOST_MODE_PARAM_SZ;
+ *updt_params++ = bass_boost->mode;
+ params_length += COMMAND_PAYLOAD_SZ +
+ BASS_BOOST_MODE_PARAM_SZ;
+ }
+ break;
+ case BASS_BOOST_STRENGTH:
+ pr_debug("%s: BASS_BOOST_STRENGTH\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ bass_boost->strength = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ = AUDPROC_MODULE_ID_BASS_BOOST;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_BASS_BOOST_STRENGTH;
+ *updt_params++ = BASS_BOOST_STRENGTH_PARAM_SZ;
+ *updt_params++ = bass_boost->strength;
+ params_length += COMMAND_PAYLOAD_SZ +
+ BASS_BOOST_STRENGTH_PARAM_SZ;
+ }
+ break;
+ default:
+ pr_err("%s: Invalid command to set config\n", __func__);
+ break;
+ }
+ }
+ if (params_length)
+ q6asm_send_audio_effects_params(ac, params,
+ params_length);
+invalid_config:
+ kfree(params);
+ return rc;
+}
+
+int msm_audio_effects_popless_eq_handler(struct audio_client *ac,
+ struct eq_params *eq,
+ long *values)
+{
+ int devices = *values++;
+ int num_commands = *values++;
+ char *params;
+ int *updt_params, i, prev_enable_flag;
+ uint32_t params_length = (MAX_INBAND_PARAM_SZ);
+ int rc = 0;
+
+ pr_debug("%s\n", __func__);
+ if (!ac) {
+ pr_err("%s: cannot set audio effects\n", __func__);
+ return -EINVAL;
+ }
+ params = kzalloc(params_length, GFP_KERNEL);
+ if (!params) {
+ pr_err("%s, params memory alloc failed\n", __func__);
+ return -ENOMEM;
+ }
+ pr_debug("%s: device: %d\n", __func__, devices);
+ updt_params = (int *)params;
+ params_length = 0;
+ for (i = 0; i < num_commands; i++) {
+ uint32_t command_id = *values++;
+ uint32_t command_config_state = *values++;
+ uint32_t index_offset = *values++;
+ uint32_t length = *values++;
+ int idx, j;
+ switch (command_id) {
+ case EQ_ENABLE:
+ pr_debug("%s: EQ_ENABLE\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ prev_enable_flag = eq->enable_flag;
+ eq->enable_flag = *values++;
+ pr_debug("%s: prev_enable_flag : %d, eq.enable_flag : %d",
+ __func__, prev_enable_flag, eq->enable_flag);
+ if (prev_enable_flag != eq->enable_flag) {
+ *updt_params++ =
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER;
+ *updt_params++ = AUDPROC_PARAM_ID_EQ_ENABLE;
+ *updt_params++ = EQ_ENABLE_PARAM_SZ;
+ *updt_params++ = eq->enable_flag;
+ params_length += COMMAND_PAYLOAD_SZ +
+ EQ_ENABLE_PARAM_SZ;
+ }
+ break;
+ case EQ_CONFIG:
+ pr_debug("%s: EQ_CONFIG\n", __func__);
+ if (length < EQ_CONFIG_PARAM_LEN || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ for (idx = 0; idx < MAX_EQ_BANDS; idx++)
+ eq->per_band_cfg[idx].band_idx = -1;
+ eq->config.eq_pregain = *values++;
+ eq->config.preset_id = *values++;
+ eq->config.num_bands = *values++;
+ if (eq->config.num_bands > MAX_EQ_BANDS) {
+ pr_err("invalid num of bands\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ if (eq->config.num_bands &&
+ (((length - EQ_CONFIG_PARAM_LEN)/
+ EQ_CONFIG_PER_BAND_PARAM_LEN)
+ != eq->config.num_bands)) {
+ pr_err("invalid length to set config per band\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ for (j = 0; j < eq->config.num_bands; j++) {
+ idx = *values++;
+ eq->per_band_cfg[idx].band_idx = idx;
+ eq->per_band_cfg[idx].filter_type = *values++;
+ eq->per_band_cfg[idx].freq_millihertz =
+ *values++;
+ eq->per_band_cfg[idx].gain_millibels =
+ *values++;
+ eq->per_band_cfg[idx].quality_factor =
+ *values++;
+ }
+ if (command_config_state == CONFIG_SET) {
+ int config_param_length = EQ_CONFIG_PARAM_SZ +
+ (EQ_CONFIG_PER_BAND_PARAM_SZ*
+ eq->config.num_bands);
+ *updt_params++ =
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER;
+ *updt_params++ = AUDPROC_PARAM_ID_EQ_CONFIG;
+ *updt_params++ = config_param_length;
+ *updt_params++ = eq->config.eq_pregain;
+ *updt_params++ = eq->config.preset_id;
+ *updt_params++ = eq->config.num_bands;
+ for (idx = 0; idx < MAX_EQ_BANDS; idx++) {
+ if (eq->per_band_cfg[idx].band_idx < 0)
+ continue;
+ *updt_params++ =
+ eq->per_band_cfg[idx].filter_type;
+ *updt_params++ =
+ eq->per_band_cfg[idx].freq_millihertz;
+ *updt_params++ =
+ eq->per_band_cfg[idx].gain_millibels;
+ *updt_params++ =
+ eq->per_band_cfg[idx].quality_factor;
+ *updt_params++ =
+ eq->per_band_cfg[idx].band_idx;
+ }
+ params_length += COMMAND_PAYLOAD_SZ +
+ config_param_length;
+ }
+ break;
+ case EQ_BAND_INDEX:
+ pr_debug("%s: EQ_BAND_INDEX\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ idx = *values++;
+ if (idx > MAX_EQ_BANDS) {
+ pr_err("invalid band index\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ eq->band_index = idx;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ =
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_EQ_BAND_INDEX;
+ *updt_params++ = EQ_BAND_INDEX_PARAM_SZ;
+ *updt_params++ = eq->band_index;
+ params_length += COMMAND_PAYLOAD_SZ +
+ EQ_BAND_INDEX_PARAM_SZ;
+ }
+ break;
+ case EQ_SINGLE_BAND_FREQ:
+ pr_debug("%s: EQ_SINGLE_BAND_FREQ\n", __func__);
+ if (length != 1 || index_offset != 0) {
+ pr_err("no valid params\n");
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+ if (eq->band_index > MAX_EQ_BANDS) {
+ pr_err("invalid band index to set frequency\n");
+ break;
+ }
+ eq->freq_millihertz = *values++;
+ if (command_config_state == CONFIG_SET) {
+ *updt_params++ =
+ AUDPROC_MODULE_ID_POPLESS_EQUALIZER;
+ *updt_params++ =
+ AUDPROC_PARAM_ID_EQ_SINGLE_BAND_FREQ;
+ *updt_params++ = EQ_SINGLE_BAND_FREQ_PARAM_SZ;
+ *updt_params++ = eq->freq_millihertz;
+ params_length += COMMAND_PAYLOAD_SZ +
+ EQ_SINGLE_BAND_FREQ_PARAM_SZ;
+ }
+ break;
+ default:
+ pr_err("%s: Invalid command to set config\n", __func__);
+ break;
+ }
+ }
+ if (params_length)
+ q6asm_send_audio_effects_params(ac, params,
+ params_length);
+invalid_config:
+ kfree(params);
+ return rc;
+}
diff --git a/sound/soc/msm/qdsp6v2/msm-audio-effects-q6-v2.h b/sound/soc/msm/qdsp6v2/msm-audio-effects-q6-v2.h
new file mode 100644
index 0000000..3d2e6d4
--- /dev/null
+++ b/sound/soc/msm/qdsp6v2/msm-audio-effects-q6-v2.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MSM_AUDIO_EFFECTS_H
+#define _MSM_AUDIO_EFFECTS_H
+
+#include <sound/audio_effects.h>
+
+int msm_audio_effects_reverb_handler(struct audio_client *ac,
+ struct reverb_params *reverb,
+ long *values);
+
+int msm_audio_effects_bass_boost_handler(struct audio_client *ac,
+ struct bass_boost_params *bass_boost,
+ long *values);
+int msm_audio_effects_virtualizer_handler(struct audio_client *ac,
+ struct virtualizer_params *virtualizer,
+ long *values);
+
+int msm_audio_effects_popless_eq_handler(struct audio_client *ac,
+ struct eq_params *eq,
+ long *values);
+#endif /*_MSM_AUDIO_EFFECTS_H*/
diff --git a/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c
index 55d50ed..7935100 100644
--- a/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-compress-q6-v2.c
@@ -43,6 +43,7 @@
#include "msm-pcm-routing-v2.h"
#include "audio_ocmem.h"
+#include "msm-audio-effects-q6-v2.h"
#define DSP_PP_BUFFERING_IN_MSEC 25
#define PARTIAL_DRAIN_ACK_EARLY_BY_MSEC 150
@@ -71,6 +72,7 @@
atomic_t audio_ocmem_req;
struct snd_compr_stream *cstream[MSM_FRONTEND_DAI_MAX];
uint32_t volume[MSM_FRONTEND_DAI_MAX][2]; /* For both L & R */
+ struct msm_compr_audio_effects *audio_effects[MSM_FRONTEND_DAI_MAX];
};
struct msm_compr_audio {
@@ -109,6 +111,7 @@
atomic_t xrun;
atomic_t close;
atomic_t wait_on_close;
+ atomic_t error;
wait_queue_head_t eos_wait;
wait_queue_head_t drain_wait;
@@ -118,6 +121,13 @@
spinlock_t lock;
};
+struct msm_compr_audio_effects {
+ struct bass_boost_params bass_boost;
+ struct virtualizer_params virtualizer;
+ struct reverb_params reverb;
+ struct eq_params equalizer;
+};
+
static int msm_compr_set_volume(struct snd_compr_stream *cstream,
uint32_t volume_l, uint32_t volume_r)
{
@@ -164,17 +174,11 @@
pr_debug("%s: bytes_received = %d copied_total = %d\n",
__func__, prtd->bytes_received, prtd->copied_total);
- /*
- * FIXME: Initial and trailing silence removal API call to DSP results
- * to a glitch during the stream transition for gapless playback.
- * Add this when the issue is fixed from DSP.
- */
-/*
if (prtd->first_buffer)
q6asm_send_meta_data(prtd->audio_client,
prtd->gapless_state.initial_samples_drop,
prtd->gapless_state.trailing_samples_drop);
-*/
+
buffer_length = prtd->codec_param.buffer.fragment_size;
bytes_available = prtd->bytes_received - prtd->copied_total;
if (bytes_available < prtd->codec_param.buffer.fragment_size)
@@ -354,6 +358,14 @@
case ASM_SESSION_CMDRSP_GET_SESSIONTIME_V3:
pr_debug("ASM_SESSION_CMDRSP_GET_SESSIONTIME_V3\n");
break;
+ case RESET_EVENTS:
+ pr_err("Received reset events CB, move to error state");
+ spin_lock(&prtd->lock);
+ snd_compr_fragment_elapsed(cstream);
+ prtd->copied_total = prtd->bytes_received;
+ atomic_set(&prtd->error, 1);
+ spin_unlock(&prtd->lock);
+ break;
default:
pr_debug("Not Supported Event opcode[0x%x]\n", opcode);
break;
@@ -514,10 +526,18 @@
prtd->cstream = cstream;
pdata->cstream[rtd->dai_link->be_id] = cstream;
+ pdata->audio_effects[rtd->dai_link->be_id] =
+ kzalloc(sizeof(struct msm_compr_audio_effects), GFP_KERNEL);
+ if (!pdata->audio_effects[rtd->dai_link->be_id]) {
+ pr_err("%s: Could not allocate memory for effects\n", __func__);
+ kfree(prtd);
+ return -ENOMEM;
+ }
prtd->audio_client = q6asm_audio_client_alloc(
(app_cb)compr_event_handler, prtd);
if (!prtd->audio_client) {
- pr_err("%s: Could not allocate memory\n", __func__);
+ pr_err("%s: Could not allocate memory for client\n", __func__);
+ kfree(pdata->audio_effects[rtd->dai_link->be_id]);
kfree(prtd);
return -ENOMEM;
}
@@ -545,6 +565,7 @@
atomic_set(&prtd->xrun, 0);
atomic_set(&prtd->close, 0);
atomic_set(&prtd->wait_on_close, 0);
+ atomic_set(&prtd->error, 0);
init_waitqueue_head(&prtd->eos_wait);
init_waitqueue_head(&prtd->drain_wait);
@@ -629,6 +650,7 @@
q6asm_audio_client_free(ac);
+ kfree(pdata->audio_effects[soc_prtd->dai_link->be_id]);
kfree(prtd);
return 0;
@@ -759,6 +781,14 @@
return -EINVAL;
}
+ spin_lock_irqsave(&prtd->lock, flags);
+ if (atomic_read(&prtd->error)) {
+ pr_err("%s Got RESET EVENTS notification, return immediately", __func__);
+ spin_unlock_irqrestore(&prtd->lock, flags);
+ return 0;
+ }
+ spin_unlock_irqrestore(&prtd->lock, flags);
+
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
pr_debug("%s: SNDRV_PCM_TRIGGER_START\n", __func__);
@@ -1072,6 +1102,15 @@
tstamp.byte_offset = prtd->byte_offset;
tstamp.copied_total = prtd->copied_total;
first_buffer = prtd->first_buffer;
+
+ if (atomic_read(&prtd->error)) {
+ pr_err("%s Got RESET EVENTS notification, return error", __func__);
+ tstamp.pcm_io_frames = 0;
+ memcpy(arg, &tstamp, sizeof(struct snd_compr_tstamp));
+ spin_unlock_irqrestore(&prtd->lock, flags);
+ return -EINVAL;
+ }
+
spin_unlock_irqrestore(&prtd->lock, flags);
/*
@@ -1160,6 +1199,14 @@
return 0;
}
+ spin_lock_irqsave(&prtd->lock, flags);
+ if (atomic_read(&prtd->error)) {
+ pr_err("%s Got RESET EVENTS notification", __func__);
+ spin_unlock_irqrestore(&prtd->lock, flags);
+ return -EINVAL;
+ }
+ spin_unlock_irqrestore(&prtd->lock, flags);
+
dstn = prtd->buffer + prtd->app_pointer;
if (count < prtd->buffer_size - prtd->app_pointer) {
if (copy_from_user(dstn, buf, count))
@@ -1282,50 +1329,125 @@
}
static int msm_compr_volume_put(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
+ struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_platform *platform = snd_kcontrol_chip(kcontrol);
- struct soc_mixer_control *mc =
- (struct soc_mixer_control *)kcontrol->private_value;
+ unsigned long fe_id = kcontrol->private_value;
struct msm_compr_pdata *pdata = (struct msm_compr_pdata *)
snd_soc_platform_get_drvdata(platform);
- struct snd_compr_stream *cstream = pdata->cstream[mc->reg];
- uint32_t *volume = pdata->volume[mc->reg];
+ struct snd_compr_stream *cstream = NULL;
+ uint32_t *volume = NULL;
+
+ if (fe_id >= MSM_FRONTEND_DAI_MAX) {
+ pr_err("%s Received out of bounds fe_id %lu\n",
+ __func__, fe_id);
+ return -EINVAL;
+ }
+
+ cstream = pdata->cstream[fe_id];
+ volume = pdata->volume[fe_id];
volume[0] = ucontrol->value.integer.value[0];
volume[1] = ucontrol->value.integer.value[1];
- pr_debug("%s: mc->reg %d left_vol %d right_vol %d\n",
- __func__, mc->reg, volume[0], volume[1]);
+ pr_debug("%s: fe_id %lu left_vol %d right_vol %d\n",
+ __func__, fe_id, volume[0], volume[1]);
if (cstream)
msm_compr_set_volume(cstream, volume[0], volume[1]);
return 0;
}
static int msm_compr_volume_get(struct snd_kcontrol *kcontrol,
- struct snd_ctl_elem_value *ucontrol)
+ struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_platform *platform = snd_kcontrol_chip(kcontrol);
- struct soc_mixer_control *mc =
- (struct soc_mixer_control *)kcontrol->private_value;
+ unsigned long fe_id = kcontrol->private_value;
+
struct msm_compr_pdata *pdata =
snd_soc_platform_get_drvdata(platform);
- uint32_t *volume = pdata->volume[mc->reg];
- pr_debug("%s: mc->reg %d\n", __func__, mc->reg);
+ uint32_t *volume = NULL;
+
+ if (fe_id >= MSM_FRONTEND_DAI_MAX) {
+ pr_err("%s Received out of bound fe_id %lu\n", __func__, fe_id);
+ return -EINVAL;
+ }
+
+ volume = pdata->volume[fe_id];
+ pr_debug("%s: fe_id %lu\n", __func__, fe_id);
ucontrol->value.integer.value[0] = volume[0];
ucontrol->value.integer.value[1] = volume[1];
return 0;
}
-/* System Pin has no volume control */
-static const struct snd_kcontrol_new msm_compr_volume_controls[] = {
- SOC_DOUBLE_EXT_TLV("Compress Playback Volume",
- MSM_FRONTEND_DAI_MULTIMEDIA4,
- 0, 8, COMPRESSED_LR_VOL_MAX_STEPS, 0,
- msm_compr_volume_get,
- msm_compr_volume_put,
- msm_compr_vol_gain),
-};
+static int msm_compr_audio_effects_config_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_platform *platform = snd_kcontrol_chip(kcontrol);
+ unsigned long fe_id = kcontrol->private_value;
+ struct msm_compr_pdata *pdata = (struct msm_compr_pdata *)
+ snd_soc_platform_get_drvdata(platform);
+ struct msm_compr_audio_effects *audio_effects = NULL;
+ struct snd_compr_stream *cstream = NULL;
+ struct msm_compr_audio *prtd = NULL;
+ long *values = &(ucontrol->value.integer.value[0]);
+ int effects_module;
+
+ pr_debug("%s\n", __func__);
+ if (fe_id >= MSM_FRONTEND_DAI_MAX) {
+ pr_err("%s Received out of bounds fe_id %lu\n",
+ __func__, fe_id);
+ return -EINVAL;
+ }
+ cstream = pdata->cstream[fe_id];
+ audio_effects = pdata->audio_effects[fe_id];
+ if (!cstream || !audio_effects) {
+ pr_err("%s: stream or effects inactive\n", __func__);
+ return -EINVAL;
+ }
+ prtd = cstream->runtime->private_data;
+ if (!prtd) {
+ pr_err("%s: cannot set audio effects\n", __func__);
+ return -EINVAL;
+ }
+ effects_module = *values++;
+ switch (effects_module) {
+ case VIRTUALIZER_MODULE:
+ pr_debug("%s: VIRTUALIZER_MODULE\n", __func__);
+ msm_audio_effects_virtualizer_handler(prtd->audio_client,
+ &(audio_effects->virtualizer),
+ values);
+ break;
+ case REVERB_MODULE:
+ pr_debug("%s: REVERB_MODULE\n", __func__);
+ msm_audio_effects_reverb_handler(prtd->audio_client,
+ &(audio_effects->reverb),
+ values);
+ break;
+ case BASS_BOOST_MODULE:
+ pr_debug("%s: BASS_BOOST_MODULE\n", __func__);
+ msm_audio_effects_bass_boost_handler(prtd->audio_client,
+ &(audio_effects->bass_boost),
+ values);
+ break;
+ case EQ_MODULE:
+ pr_debug("%s: EQ_MODULE\n", __func__);
+ msm_audio_effects_popless_eq_handler(prtd->audio_client,
+ &(audio_effects->equalizer),
+ values);
+ break;
+ default:
+ pr_err("%s Invalid effects config module\n", __func__);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int msm_compr_audio_effects_config_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ /* dummy function */
+ return 0;
+}
static int msm_compr_probe(struct snd_soc_platform *platform)
{
@@ -1345,12 +1467,141 @@
for (i = 0; i < MSM_FRONTEND_DAI_MAX; i++) {
pdata->volume[i][0] = COMPRESSED_LR_VOL_MAX_STEPS;
pdata->volume[i][1] = COMPRESSED_LR_VOL_MAX_STEPS;
+ pdata->audio_effects[i] = NULL;
pdata->cstream[i] = NULL;
}
return 0;
}
+static int msm_compr_volume_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 2;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = COMPRESSED_LR_VOL_MAX_STEPS;
+ return 0;
+}
+
+static int msm_compr_audio_effects_config_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+ uinfo->count = 128;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 0xFFFFFFFF;
+ return 0;
+}
+
+static int msm_compr_add_volume_control(struct snd_soc_pcm_runtime *rtd)
+{
+ const char *mixer_ctl_name = "Compress Playback";
+ const char *deviceNo = "NN";
+ const char *suffix = "Volume";
+ char *mixer_str = NULL;
+ int ctl_len;
+ struct snd_kcontrol_new fe_volume_control[1] = {
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "?",
+ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
+ SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = msm_compr_volume_info,
+ .tlv.p = msm_compr_vol_gain,
+ .get = msm_compr_volume_get,
+ .put = msm_compr_volume_put,
+ .private_value = 0,
+ }
+ };
+
+ if (!rtd) {
+ pr_err("%s NULL rtd\n", __func__);
+ return 0;
+ }
+ pr_debug("%s: added new compr FE with name %s, id %d, cpu dai %s, device no %d\n",
+ __func__, rtd->dai_link->name, rtd->dai_link->be_id,
+ rtd->dai_link->cpu_dai_name, rtd->pcm->device);
+ ctl_len = strlen(mixer_ctl_name) + 1 + strlen(deviceNo) + 1 +
+ strlen(suffix) + 1;
+ mixer_str = kzalloc(ctl_len, GFP_KERNEL);
+ if (!mixer_str) {
+ pr_err("failed to allocate mixer ctrl str of len %d", ctl_len);
+ return 0;
+ }
+ snprintf(mixer_str, ctl_len, "%s %d %s", mixer_ctl_name,
+ rtd->pcm->device, suffix);
+ fe_volume_control[0].name = mixer_str;
+ fe_volume_control[0].private_value = rtd->dai_link->be_id;
+ pr_debug("Registering new mixer ctl %s", mixer_str);
+ snd_soc_add_platform_controls(rtd->platform, fe_volume_control,
+ ARRAY_SIZE(fe_volume_control));
+ kfree(mixer_str);
+ return 0;
+}
+
+static int msm_compr_add_audio_effects_control(struct snd_soc_pcm_runtime *rtd)
+{
+ const char *mixer_ctl_name = "Audio Effects Config";
+ const char *deviceNo = "NN";
+ char *mixer_str = NULL;
+ int ctl_len;
+ struct snd_kcontrol_new fe_audio_effects_config_control[1] = {
+ {
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "?",
+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = msm_compr_audio_effects_config_info,
+ .get = msm_compr_audio_effects_config_get,
+ .put = msm_compr_audio_effects_config_put,
+ .private_value = 0,
+ }
+ };
+
+
+ if (!rtd) {
+ pr_err("%s NULL rtd\n", __func__);
+ return 0;
+ }
+
+ pr_debug("%s: added new compr FE with name %s, id %d, cpu dai %s, device no %d\n",
+ __func__, rtd->dai_link->name, rtd->dai_link->be_id,
+ rtd->dai_link->cpu_dai_name, rtd->pcm->device);
+
+ ctl_len = strlen(mixer_ctl_name) + 1 + strlen(deviceNo) + 1;
+ mixer_str = kzalloc(ctl_len, GFP_KERNEL);
+
+ if (!mixer_str) {
+ pr_err("failed to allocate mixer ctrl str of len %d", ctl_len);
+ return 0;
+ }
+
+ snprintf(mixer_str, ctl_len, "%s %d", mixer_ctl_name, rtd->pcm->device);
+
+ fe_audio_effects_config_control[0].name = mixer_str;
+ fe_audio_effects_config_control[0].private_value = rtd->dai_link->be_id;
+ pr_debug("Registering new mixer ctl %s", mixer_str);
+ snd_soc_add_platform_controls(rtd->platform,
+ fe_audio_effects_config_control,
+ ARRAY_SIZE(fe_audio_effects_config_control));
+ kfree(mixer_str);
+ return 0;
+}
+
+static int msm_compr_new(struct snd_soc_pcm_runtime *rtd)
+{
+ int rc;
+
+ rc = msm_compr_add_volume_control(rtd);
+ if (rc)
+ pr_err("%s: Could not add Compr Volume Control\n", __func__);
+ rc = msm_compr_add_audio_effects_control(rtd);
+ if (rc)
+ pr_err("%s: Could not add Compr Audio Effects Control\n",
+ __func__);
+ return 0;
+}
+
static struct snd_compr_ops msm_compr_ops = {
.open = msm_compr_open,
.free = msm_compr_free,
@@ -1367,8 +1618,7 @@
static struct snd_soc_platform_driver msm_soc_platform = {
.probe = msm_compr_probe,
.compr_ops = &msm_compr_ops,
- .controls = msm_compr_volume_controls,
- .num_controls = ARRAY_SIZE(msm_compr_volume_controls),
+ .pcm_new = msm_compr_new,
};
static __devinit int msm_compr_dev_probe(struct platform_device *pdev)
diff --git a/sound/soc/msm/qdsp6v2/msm-dai-q6-hdmi-v2.c b/sound/soc/msm/qdsp6v2/msm-dai-q6-hdmi-v2.c
index 0cf044c..9de15d9 100644
--- a/sound/soc/msm/qdsp6v2/msm-dai-q6-hdmi-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-dai-q6-hdmi-v2.c
@@ -129,13 +129,26 @@
break;
}
+ /*refer to HDMI spec CEA-861-E: Table 28 Audio InfoFrame Data Byte 4*/
switch (dai_data->channels) {
case 2:
dai_data->port_config.hdmi_multi_ch.channel_allocation = 0;
break;
+ case 3:
+ dai_data->port_config.hdmi_multi_ch.channel_allocation = 0x02;
+ break;
+ case 4:
+ dai_data->port_config.hdmi_multi_ch.channel_allocation = 0x06;
+ break;
+ case 5:
+ dai_data->port_config.hdmi_multi_ch.channel_allocation = 0x0A;
+ break;
case 6:
dai_data->port_config.hdmi_multi_ch.channel_allocation = 0x0B;
break;
+ case 7:
+ dai_data->port_config.hdmi_multi_ch.channel_allocation = 0x12;
+ break;
case 8:
dai_data->port_config.hdmi_multi_ch.channel_allocation = 0x13;
break;
diff --git a/sound/soc/msm/qdsp6v2/msm-dolby-dap-config.c b/sound/soc/msm/qdsp6v2/msm-dolby-dap-config.c
index 307d63e..63ac5d3 100644
--- a/sound/soc/msm/qdsp6v2/msm-dolby-dap-config.c
+++ b/sound/soc/msm/qdsp6v2/msm-dolby-dap-config.c
@@ -179,13 +179,13 @@
DOLBY_ENDDEP_PARAM_VMB_OFFSET},
{-320, -320, 144}
},
- {REMOTE_SUBMIX, 2, DOLBY_ENDP_EXT_SPEAKERS,
+ {REMOTE_SUBMIX, 2, DOLBY_ENDP_HDMI,
{DOLBY_PARAM_ID_DVLO, DOLBY_PARAM_ID_DVLI, DOLBY_PARAM_ID_VMB},
{DOLBY_ENDDEP_PARAM_DVLO_LENGTH, DOLBY_ENDDEP_PARAM_DVLI_LENGTH,
DOLBY_ENDDEP_PARAM_VMB_LENGTH},
{DOLBY_ENDDEP_PARAM_DVLO_OFFSET, DOLBY_ENDDEP_PARAM_DVLI_OFFSET,
DOLBY_ENDDEP_PARAM_VMB_OFFSET},
- {-320, -320, 144}
+ {-496, -496, 0}
},
{ANC_HEADSET, 2, DOLBY_ENDP_HEADPHONES,
{DOLBY_PARAM_ID_DVLO, DOLBY_PARAM_ID_DVLI, DOLBY_PARAM_ID_VMB},
@@ -211,13 +211,13 @@
DOLBY_ENDDEP_PARAM_VMB_OFFSET},
{-320, -320, 144}
},
- {FM, 2, DOLBY_ENDP_EXT_SPEAKERS,
+ {FM, 2, DOLBY_ENDP_HDMI,
{DOLBY_PARAM_ID_DVLO, DOLBY_PARAM_ID_DVLI, DOLBY_PARAM_ID_VMB},
{DOLBY_ENDDEP_PARAM_DVLO_LENGTH, DOLBY_ENDDEP_PARAM_DVLI_LENGTH,
DOLBY_ENDDEP_PARAM_VMB_LENGTH},
{DOLBY_ENDDEP_PARAM_DVLO_OFFSET, DOLBY_ENDDEP_PARAM_DVLI_OFFSET,
DOLBY_ENDDEP_PARAM_VMB_OFFSET},
- {-320, -320, 144}
+ {-496, -496, 0}
},
{FM_TX, 2, DOLBY_ENDP_EXT_SPEAKERS,
{DOLBY_PARAM_ID_DVLO, DOLBY_PARAM_ID_DVLI, DOLBY_PARAM_ID_VMB},
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-loopback-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-loopback-v2.c
new file mode 100644
index 0000000..57fc268
--- /dev/null
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-loopback-v2.c
@@ -0,0 +1,441 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 and
+* only version 2 as published by the Free Software Foundation.
+
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*/
+
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <sound/apr_audio-v2.h>
+#include <sound/core.h>
+#include <sound/soc.h>
+#include <sound/q6asm-v2.h>
+#include <sound/pcm.h>
+#include <sound/initval.h>
+#include <sound/control.h>
+#include <sound/tlv.h>
+#include <asm/dma.h>
+
+#include "msm-pcm-routing-v2.h"
+
+#define LOOPBACK_VOL_MAX_STEPS 0x2000
+
+static const DECLARE_TLV_DB_LINEAR(loopback_rx_vol_gain, 0,
+ LOOPBACK_VOL_MAX_STEPS);
+
+struct msm_pcm_loopback {
+ struct snd_pcm_substream *playback_substream;
+ struct snd_pcm_substream *capture_substream;
+
+ int instance;
+
+ struct mutex lock;
+
+ uint32_t samp_rate;
+ uint32_t channel_mode;
+
+ int playback_start;
+ int capture_start;
+ int session_id;
+ struct audio_client *audio_client;
+ int volume;
+};
+
+static void stop_pcm(struct msm_pcm_loopback *pcm);
+
+static const struct snd_pcm_hardware dummy_pcm_hardware = {
+ .formats = 0xffffffff,
+ .channels_min = 1,
+ .channels_max = UINT_MAX,
+
+ /* Random values to keep userspace happy when checking constraints */
+ .info = SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_BLOCK_TRANSFER,
+ .buffer_bytes_max = 128*1024,
+ .period_bytes_min = 1024,
+ .period_bytes_max = 1024*2,
+ .periods_min = 2,
+ .periods_max = 128,
+};
+
+static void msm_pcm_route_event_handler(enum msm_pcm_routing_event event,
+ void *priv_data)
+{
+ struct msm_pcm_loopback *pcm = priv_data;
+
+ BUG_ON(!pcm);
+
+ pr_debug("%s: event %x\n", __func__, event);
+
+ switch (event) {
+ case MSM_PCM_RT_EVT_DEVSWITCH:
+ q6asm_cmd(pcm->audio_client, CMD_PAUSE);
+ q6asm_cmd(pcm->audio_client, CMD_FLUSH);
+ q6asm_run(pcm->audio_client, 0, 0, 0);
+ default:
+ break;
+ }
+}
+
+static void msm_pcm_loopback_event_handler(uint32_t opcode, uint32_t token,
+ uint32_t *payload, void *priv)
+{
+ pr_debug("%s\n", __func__);
+ switch (opcode) {
+ case APR_BASIC_RSP_RESULT: {
+ switch (payload[0]) {
+ break;
+ default:
+ break;
+ }
+ }
+ break;
+ default:
+ pr_err("Not Supported Event opcode[0x%x]\n", opcode);
+ break;
+ }
+}
+
+static int pcm_loopback_set_volume(struct msm_pcm_loopback *prtd, int volume)
+{
+ int rc = -EINVAL;
+
+ pr_debug("%s Setting volume 0x%x\n", __func__, volume);
+
+ if (prtd && prtd->audio_client) {
+ rc = q6asm_set_volume(prtd->audio_client, volume);
+ if (rc < 0) {
+ pr_err("%s: Send Volume command failed rc = %d\n",
+ __func__, rc);
+ return rc;
+ }
+ prtd->volume = volume;
+ }
+ return rc;
+}
+
+static int msm_pcm_open(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
+ struct msm_pcm_loopback *pcm;
+ int ret = 0;
+ uint16_t bits_per_sample = 16;
+ struct msm_pcm_routing_evt event;
+
+ pcm = dev_get_drvdata(rtd->platform->dev);
+ mutex_lock(&pcm->lock);
+
+ snd_soc_set_runtime_hwparams(substream, &dummy_pcm_hardware);
+ pcm->volume = 0x2000;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ pcm->playback_substream = substream;
+ else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+ pcm->capture_substream = substream;
+
+ pcm->instance++;
+ dev_dbg(rtd->platform->dev, "%s: pcm out open: %d,%d\n", __func__,
+ pcm->instance, substream->stream);
+ if (pcm->instance == 2) {
+ struct snd_soc_pcm_runtime *soc_pcm_rx =
+ pcm->playback_substream->private_data;
+ struct snd_soc_pcm_runtime *soc_pcm_tx =
+ pcm->capture_substream->private_data;
+ if (pcm->audio_client != NULL)
+ stop_pcm(pcm);
+
+ pcm->audio_client = q6asm_audio_client_alloc(
+ (app_cb)msm_pcm_loopback_event_handler, pcm);
+ if (!pcm->audio_client) {
+ dev_err(rtd->platform->dev,
+ "%s: Could not allocate memory\n", __func__);
+ mutex_unlock(&pcm->lock);
+ return -ENOMEM;
+ }
+ pcm->session_id = pcm->audio_client->session;
+ pcm->audio_client->perf_mode = false;
+ ret = q6asm_open_loopback_v2(pcm->audio_client,
+ bits_per_sample);
+ if (ret < 0) {
+ dev_err(rtd->platform->dev,
+ "%s: pcm out open failed\n", __func__);
+ q6asm_audio_client_free(pcm->audio_client);
+ mutex_unlock(&pcm->lock);
+ return -ENOMEM;
+ }
+ event.event_func = msm_pcm_route_event_handler;
+ event.priv_data = (void *) pcm;
+ msm_pcm_routing_reg_phy_stream(soc_pcm_tx->dai_link->be_id,
+ pcm->audio_client->perf_mode,
+ pcm->session_id, pcm->capture_substream->stream);
+ msm_pcm_routing_reg_phy_stream_v2(soc_pcm_rx->dai_link->be_id,
+ pcm->audio_client->perf_mode,
+ pcm->session_id, pcm->playback_substream->stream,
+ event);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ pcm->playback_substream = substream;
+ ret = pcm_loopback_set_volume(pcm, pcm->volume);
+ if (ret < 0)
+ dev_err(rtd->platform->dev,
+ "Error %d setting volume", ret);
+ }
+ }
+ dev_info(rtd->platform->dev, "%s: Instance = %d, Stream ID = %s\n",
+ __func__ , pcm->instance, substream->pcm->id);
+ runtime->private_data = pcm;
+
+ mutex_unlock(&pcm->lock);
+
+ return 0;
+}
+
+static void stop_pcm(struct msm_pcm_loopback *pcm)
+{
+ struct snd_soc_pcm_runtime *soc_pcm_rx =
+ pcm->playback_substream->private_data;
+ struct snd_soc_pcm_runtime *soc_pcm_tx =
+ pcm->capture_substream->private_data;
+
+ if (pcm->audio_client == NULL)
+ return;
+ q6asm_cmd(pcm->audio_client, CMD_CLOSE);
+
+ msm_pcm_routing_dereg_phy_stream(soc_pcm_rx->dai_link->be_id,
+ SNDRV_PCM_STREAM_PLAYBACK);
+ msm_pcm_routing_dereg_phy_stream(soc_pcm_tx->dai_link->be_id,
+ SNDRV_PCM_STREAM_CAPTURE);
+ q6asm_audio_client_free(pcm->audio_client);
+ pcm->audio_client = NULL;
+}
+
+static int msm_pcm_close(struct snd_pcm_substream *substream)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct msm_pcm_loopback *pcm = runtime->private_data;
+ struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
+ int ret = 0;
+
+ mutex_lock(&pcm->lock);
+
+ dev_dbg(rtd->platform->dev, "%s: end pcm call:%d\n",
+ __func__, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ pcm->playback_start = 0;
+ else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+ pcm->capture_start = 0;
+
+ pcm->instance--;
+ if (!pcm->playback_start || !pcm->capture_start) {
+ dev_dbg(rtd->platform->dev, "%s: end pcm call\n", __func__);
+ stop_pcm(pcm);
+ }
+
+ mutex_unlock(&pcm->lock);
+ return ret;
+}
+
+static int msm_pcm_prepare(struct snd_pcm_substream *substream)
+{
+ int ret = 0;
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct msm_pcm_loopback *pcm = runtime->private_data;
+ struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
+
+ mutex_lock(&pcm->lock);
+
+ dev_dbg(rtd->platform->dev, "%s: ASM loopback stream:%d\n",
+ __func__, substream->stream);
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ if (!pcm->playback_start)
+ pcm->playback_start = 1;
+ } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ if (!pcm->capture_start)
+ pcm->capture_start = 1;
+ }
+ mutex_unlock(&pcm->lock);
+
+ return ret;
+}
+
+static int msm_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+ struct snd_pcm_runtime *runtime = substream->runtime;
+ struct msm_pcm_loopback *pcm = runtime->private_data;
+ struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ dev_dbg(rtd->platform->dev,
+ "%s: playback_start:%d,capture_start:%d\n", __func__,
+ pcm->playback_start, pcm->capture_start);
+ if (pcm->playback_start && pcm->capture_start)
+ q6asm_run_nowait(pcm->audio_client, 0, 0, 0);
+ break;
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ case SNDRV_PCM_TRIGGER_STOP:
+ dev_dbg(rtd->platform->dev,
+ "%s:Pause/Stop - playback_start:%d,capture_start:%d\n",
+ __func__, pcm->playback_start, pcm->capture_start);
+ if (pcm->playback_start && pcm->capture_start)
+ q6asm_cmd_nowait(pcm->audio_client, CMD_PAUSE);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int msm_pcm_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
+
+ dev_dbg(rtd->platform->dev, "%s: ASM loopback\n", __func__);
+
+ return snd_pcm_lib_alloc_vmalloc_buffer(substream,
+ params_buffer_bytes(params));
+}
+
+static int msm_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+ return snd_pcm_lib_free_vmalloc_buffer(substream);
+}
+
+static struct snd_pcm_ops msm_pcm_ops = {
+ .open = msm_pcm_open,
+ .hw_params = msm_pcm_hw_params,
+ .hw_free = msm_pcm_hw_free,
+ .close = msm_pcm_close,
+ .prepare = msm_pcm_prepare,
+ .trigger = msm_pcm_trigger,
+};
+
+static int msm_pcm_volume_ctl_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int rc = 0;
+ struct snd_pcm_volume *vol = kcontrol->private_data;
+ struct snd_pcm_substream *substream = vol->pcm->streams[0].substream;
+ struct msm_pcm_loopback *prtd = substream->runtime->private_data;
+ int volume = ucontrol->value.integer.value[0];
+
+ rc = pcm_loopback_set_volume(prtd, volume);
+ return rc;
+}
+
+static int msm_pcm_add_controls(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_pcm *pcm = rtd->pcm->streams[0].pcm;
+ struct snd_pcm_volume *volume_info;
+ struct snd_kcontrol *kctl;
+ int ret = 0;
+
+ dev_dbg(rtd->dev, "%s, Volume cntrl add\n", __func__);
+ ret = snd_pcm_add_volume_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
+ NULL, 1,
+ rtd->dai_link->be_id,
+ &volume_info);
+ if (ret < 0)
+ return ret;
+ kctl = volume_info->kctl;
+ kctl->put = msm_pcm_volume_ctl_put;
+ kctl->tlv.p = loopback_rx_vol_gain;
+ return 0;
+}
+
+static int msm_asoc_pcm_new(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_card *card = rtd->card->snd_card;
+ int ret = 0;
+
+ if (!card->dev->coherent_dma_mask)
+ card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
+
+ ret = msm_pcm_add_controls(rtd);
+ if (ret)
+ dev_err(rtd->dev, "%s, kctl add failed\n", __func__);
+ return ret;
+}
+
+static struct snd_soc_platform_driver msm_soc_platform = {
+ .ops = &msm_pcm_ops,
+ .pcm_new = msm_asoc_pcm_new,
+};
+
+static __devinit int msm_pcm_probe(struct platform_device *pdev)
+{
+ struct msm_pcm_loopback *pcm;
+
+ dev_set_name(&pdev->dev, "%s", "msm-pcm-loopback");
+ dev_dbg(&pdev->dev, "%s: dev name %s\n",
+ __func__, dev_name(&pdev->dev));
+
+ pcm = kzalloc(sizeof(struct msm_pcm_loopback), GFP_KERNEL);
+ if (!pcm) {
+ dev_err(&pdev->dev, "%s Failed to allocate memory for pcm\n",
+ __func__);
+ return -ENOMEM;
+ } else {
+ mutex_init(&pcm->lock);
+ dev_set_drvdata(&pdev->dev, pcm);
+ }
+ return snd_soc_register_platform(&pdev->dev,
+ &msm_soc_platform);
+}
+
+static int msm_pcm_remove(struct platform_device *pdev)
+{
+ struct msm_pcm_loopback *pcm;
+
+ pcm = dev_get_drvdata(&pdev->dev);
+ mutex_destroy(&pcm->lock);
+ kfree(pcm);
+
+ snd_soc_unregister_platform(&pdev->dev);
+ return 0;
+}
+
+static const struct of_device_id msm_pcm_loopback_dt_match[] = {
+ {.compatible = "qti,msm-pcm-loopback"},
+ {}
+};
+
+static struct platform_driver msm_pcm_driver = {
+ .driver = {
+ .name = "msm-pcm-loopback",
+ .owner = THIS_MODULE,
+ .of_match_table = msm_pcm_loopback_dt_match,
+ },
+ .probe = msm_pcm_probe,
+ .remove = __devexit_p(msm_pcm_remove),
+};
+
+static int __init msm_soc_platform_init(void)
+{
+ return platform_driver_register(&msm_pcm_driver);
+}
+module_init(msm_soc_platform_init);
+
+static void __exit msm_soc_platform_exit(void)
+{
+ platform_driver_unregister(&msm_pcm_driver);
+}
+module_exit(msm_soc_platform_exit);
+
+MODULE_DESCRIPTION("PCM loopback platform driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c
index dc41948..f25f746 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c
@@ -109,6 +109,25 @@
.mask = 0,
};
+static void msm_pcm_route_event_handler(enum msm_pcm_routing_event event,
+ void *priv_data)
+{
+ struct msm_audio *prtd = priv_data;
+
+ BUG_ON(!prtd);
+
+ pr_debug("%s: event %x\n", __func__, event);
+
+ switch (event) {
+ case MSM_PCM_RT_EVT_BUF_RECFG:
+ q6asm_cmd(prtd->audio_client, CMD_PAUSE);
+ q6asm_cmd(prtd->audio_client, CMD_FLUSH);
+ q6asm_run(prtd->audio_client, 0, 0, 0);
+ default:
+ break;
+ }
+}
+
static void event_handler(uint32_t opcode,
uint32_t token, uint32_t *payload, void *priv)
{
@@ -151,18 +170,31 @@
pr_debug("token = 0x%08x\n", token);
in_frame_info[token][0] = payload[4];
in_frame_info[token][1] = payload[5];
- prtd->pcm_irq_pos += in_frame_info[token][0];
- pr_debug("pcm_irq_pos=%d\n", prtd->pcm_irq_pos);
- if (atomic_read(&prtd->start))
- snd_pcm_period_elapsed(substream);
- if (atomic_read(&prtd->in_count) <= prtd->periods)
- atomic_inc(&prtd->in_count);
- wake_up(&the_locks.read_wait);
- if (prtd->mmap_flag
- && q6asm_is_cpu_buf_avail_nolock(OUT,
+ /* assume data size = 0 during flushing */
+ if (in_frame_info[token][0]) {
+ prtd->pcm_irq_pos += in_frame_info[token][0];
+ pr_debug("pcm_irq_pos=%d\n", prtd->pcm_irq_pos);
+ if (atomic_read(&prtd->start))
+ snd_pcm_period_elapsed(substream);
+ if (atomic_read(&prtd->in_count) <= prtd->periods)
+ atomic_inc(&prtd->in_count);
+ wake_up(&the_locks.read_wait);
+ if (prtd->mmap_flag &&
+ q6asm_is_cpu_buf_avail_nolock(OUT,
prtd->audio_client,
&size, &idx))
- q6asm_read_nolock(prtd->audio_client);
+ q6asm_read_nolock(prtd->audio_client);
+ } else {
+ pr_debug("%s: reclaim flushed buf in_count %x\n",
+ __func__, atomic_read(&prtd->in_count));
+ atomic_inc(&prtd->in_count);
+ if (atomic_read(&prtd->in_count) == prtd->periods) {
+ pr_info("%s: reclaimed all bufs\n", __func__);
+ if (atomic_read(&prtd->start))
+ snd_pcm_period_elapsed(substream);
+ wake_up(&the_locks.read_wait);
+ }
+ }
break;
}
case APR_BASIC_RSP_RESULT: {
@@ -681,6 +713,7 @@
int dir, ret;
struct msm_plat_data *pdata;
uint16_t bits_per_sample = 16;
+ struct msm_pcm_routing_evt event;
pdata = (struct msm_plat_data *)
dev_get_drvdata(soc_prtd->platform->dev);
@@ -737,9 +770,12 @@
pr_debug("%s: session ID %d\n",
__func__, prtd->audio_client->session);
prtd->session_id = prtd->audio_client->session;
- msm_pcm_routing_reg_phy_stream(soc_prtd->dai_link->be_id,
+ event.event_func = msm_pcm_route_event_handler;
+ event.priv_data = (void *) prtd;
+ msm_pcm_routing_reg_phy_stream_v2(soc_prtd->dai_link->be_id,
prtd->audio_client->perf_mode,
- prtd->session_id, substream->stream);
+ prtd->session_id, substream->stream,
+ event);
}
ret = q6asm_audio_client_buf_alloc_contiguous(dir,
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
index 121c2ea..711291da 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c
@@ -50,10 +50,21 @@
unsigned int format;
};
+struct msm_pcm_routing_fdai_data {
+ u16 be_srate; /* track prior backend sample rate for flushing purpose */
+ int strm_id; /* ASM stream ID */
+ struct msm_pcm_routing_evt event_info;
+};
+
#define INVALID_SESSION -1
#define SESSION_TYPE_RX 0
#define SESSION_TYPE_TX 1
+#define EC_PORT_ID_PRIMARY_MI2S_TX 1
+#define EC_PORT_ID_SECONDARY_MI2S_TX 2
+#define EC_PORT_ID_TERTIARY_MI2S_TX 3
+#define EC_PORT_ID_QUATERNARY_MI2S_TX 4
+
static struct mutex routing_lock;
static int fm_switch_enable;
@@ -63,6 +74,7 @@
static int slim0_rx_aanc_fb_port;
static int msm_route_ec_ref_rx = 3; /* NONE */
static uint32_t voc_session_id = ALL_SESSION_VSID;
+static int msm_route_ext_ec_ref = AFE_PORT_INVALID;
enum {
MADNONE,
@@ -244,25 +256,35 @@
/* Track ASM playback & capture sessions of DAI */
-static int fe_dai_map[MSM_FRONTEND_DAI_MM_SIZE][2] = {
+static struct msm_pcm_routing_fdai_data
+ fe_dai_map[MSM_FRONTEND_DAI_MM_SIZE][2] = {
/* MULTIMEDIA1 */
- {INVALID_SESSION, INVALID_SESSION},
+ {{0, INVALID_SESSION, {NULL, NULL} },
+ {0, INVALID_SESSION, {NULL, NULL} } },
/* MULTIMEDIA2 */
- {INVALID_SESSION, INVALID_SESSION},
+ {{0, INVALID_SESSION, {NULL, NULL} },
+ {0, INVALID_SESSION, {NULL, NULL} } },
/* MULTIMEDIA3 */
- {INVALID_SESSION, INVALID_SESSION},
+ {{0, INVALID_SESSION, {NULL, NULL} },
+ {0, INVALID_SESSION, {NULL, NULL} } },
/* MULTIMEDIA4 */
- {INVALID_SESSION, INVALID_SESSION},
+ {{0, INVALID_SESSION, {NULL, NULL} },
+ {0, INVALID_SESSION, {NULL, NULL} } },
/* MULTIMEDIA5 */
- {INVALID_SESSION, INVALID_SESSION},
+ {{0, INVALID_SESSION, {NULL, NULL} },
+ {0, INVALID_SESSION, {NULL, NULL} } },
/* MULTIMEDIA6 */
- {INVALID_SESSION, INVALID_SESSION},
- /* MULTIMEDIA7 */
- {INVALID_SESSION, INVALID_SESSION},
+ {{0, INVALID_SESSION, {NULL, NULL} },
+ {0, INVALID_SESSION, {NULL, NULL} } },
+ /* MULTIMEDIA7*/
+ {{0, INVALID_SESSION, {NULL, NULL} },
+ {0, INVALID_SESSION, {NULL, NULL} } },
/* MULTIMEDIA8 */
- {INVALID_SESSION, INVALID_SESSION},
+ {{0, INVALID_SESSION, {NULL, NULL} },
+ {0, INVALID_SESSION, {NULL, NULL} } },
/* MULTIMEDIA9 */
- {INVALID_SESSION, INVALID_SESSION},
+ {{0, INVALID_SESSION, {NULL, NULL} },
+ {0, INVALID_SESSION, {NULL, NULL} } },
};
/* Track performance mode of all front-end multimedia sessions.
@@ -328,7 +350,7 @@
mutex_lock(&routing_lock);
- fe_dai_map[fedai_id][session_type] = dspst_id;
+ fe_dai_map[fedai_id][session_type].strm_id = dspst_id;
for (i = 0; i < MSM_BACKEND_DAI_MAX; i++) {
if (!is_be_dai_extproc(i) &&
(afe_get_port_type(msm_bedais[i].port_id) == port_type) &&
@@ -370,7 +392,7 @@
mutex_lock(&routing_lock);
payload.num_copps = 0; /* only RX needs to use payload */
- fe_dai_map[fedai_id][session_type] = dspst_id;
+ fe_dai_map[fedai_id][session_type].strm_id = dspst_id;
fe_dai_perf_mode[fedai_id][session_type] = perf_mode;
/* re-enable EQ if active */
@@ -429,6 +451,19 @@
mutex_unlock(&routing_lock);
}
+void msm_pcm_routing_reg_phy_stream_v2(int fedai_id, bool perf_mode,
+ int dspst_id, int stream_type,
+ struct msm_pcm_routing_evt event_info)
+{
+ msm_pcm_routing_reg_phy_stream(fedai_id, perf_mode, dspst_id,
+ stream_type);
+
+ if (stream_type == SNDRV_PCM_STREAM_PLAYBACK)
+ fe_dai_map[fedai_id][SESSION_TYPE_RX].event_info = event_info;
+ else
+ fe_dai_map[fedai_id][SESSION_TYPE_TX].event_info = event_info;
+}
+
void msm_pcm_routing_dereg_phy_stream(int fedai_id, int stream_type)
{
int i, port_type, session_type, path_type, topology;
@@ -464,8 +499,8 @@
}
}
- fe_dai_map[fedai_id][session_type] = INVALID_SESSION;
-
+ fe_dai_map[fedai_id][session_type].strm_id = INVALID_SESSION;
+ fe_dai_map[fedai_id][session_type].be_srate = 0;
mutex_unlock(&routing_lock);
}
@@ -491,6 +526,7 @@
int session_type, path_type, port_id, topology;
u32 channels;
uint16_t bits_per_sample = 16;
+ struct msm_pcm_routing_fdai_data *fdai;
pr_debug("%s: reg %x val %x set %x\n", __func__, reg, val, set);
@@ -517,10 +553,23 @@
(msm_bedais[reg].port_id == VOICE2_PLAYBACK_TX)))
voc_start_playback(set, msm_bedais[reg].port_id);
set_bit(val, &msm_bedais[reg].fe_sessions);
- if (msm_bedais[reg].active && fe_dai_map[val][session_type] !=
+ fdai = &fe_dai_map[val][session_type];
+ if (msm_bedais[reg].active && fdai->strm_id !=
INVALID_SESSION) {
channels = msm_bedais[reg].channel;
+ if (session_type == SESSION_TYPE_TX &&
+ fdai->be_srate &&
+ (fdai->be_srate != msm_bedais[reg].sample_rate)) {
+ pr_debug("%s: flush strm %d diff BE rates\n",
+ __func__, fdai->strm_id);
+
+ if (fdai->event_info.event_func)
+ fdai->event_info.event_func(
+ MSM_PCM_RT_EVT_BUF_RECFG,
+ fdai->event_info.priv_data);
+ fdai->be_srate = 0; /* might not need it */
+ }
if (msm_bedais[reg].format == SNDRV_PCM_FORMAT_S24_LE)
bits_per_sample = 24;
@@ -543,8 +592,14 @@
msm_bedais[reg].sample_rate, channels,
topology, false, bits_per_sample);
+ if (session_type == SESSION_TYPE_RX &&
+ fdai->event_info.event_func)
+ fdai->event_info.event_func(
+ MSM_PCM_RT_EVT_DEVSWITCH,
+ fdai->event_info.priv_data);
+
msm_pcm_routing_build_matrix(val,
- fe_dai_map[val][session_type], path_type,
+ fdai->strm_id, path_type,
fe_dai_perf_mode[val][session_type]);
port_id = srs_port_id = msm_bedais[reg].port_id;
srs_send_params(srs_port_id, 1, 0);
@@ -560,7 +615,8 @@
(msm_bedais[reg].port_id == VOICE2_PLAYBACK_TX)))
voc_start_playback(set, msm_bedais[reg].port_id);
clear_bit(val, &msm_bedais[reg].fe_sessions);
- if (msm_bedais[reg].active && fe_dai_map[val][session_type] !=
+ fdai = &fe_dai_map[val][session_type];
+ if (msm_bedais[reg].active && fdai->strm_id !=
INVALID_SESSION) {
adm_close(msm_bedais[reg].port_id,
fe_dai_perf_mode[val][session_type]);
@@ -568,7 +624,7 @@
(fe_dai_perf_mode[val][session_type] == false))
dolby_dap_deinit(msm_bedais[reg].port_id);
msm_pcm_routing_build_matrix(val,
- fe_dai_map[val][session_type], path_type,
+ fdai->strm_id, path_type,
fe_dai_perf_mode[val][session_type]);
}
}
@@ -1197,12 +1253,12 @@
static void msm_send_eq_values(int eq_idx)
{
int result;
- struct audio_client *ac =
- q6asm_get_audio_client(fe_dai_map[eq_idx][SESSION_TYPE_RX]);
+ struct audio_client *ac = q6asm_get_audio_client(
+ fe_dai_map[eq_idx][SESSION_TYPE_RX].strm_id);
if (ac == NULL) {
pr_err("%s: Could not get audio client for session: %d\n",
- __func__, fe_dai_map[eq_idx][SESSION_TYPE_RX]);
+ __func__, fe_dai_map[eq_idx][SESSION_TYPE_RX].strm_id);
goto done;
}
@@ -1369,6 +1425,76 @@
msm_routing_ec_ref_rx_get, msm_routing_ec_ref_rx_put),
};
+static int msm_routing_ext_ec_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ pr_debug("%s: ext_ec_ref_rx = %x\n", __func__, msm_route_ext_ec_ref);
+
+ mutex_lock(&routing_lock);
+ ucontrol->value.integer.value[0] = msm_route_ext_ec_ref;
+ mutex_unlock(&routing_lock);
+ return 0;
+}
+
+static int msm_routing_ext_ec_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
+ struct snd_soc_dapm_widget *widget = wlist->widgets[0];
+ int mux = ucontrol->value.enumerated.item[0];
+ struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+ int ret = 0;
+ bool state = false;
+
+ pr_debug("%s: msm_route_ec_ref_rx = %d value = %ld\n",
+ __func__, msm_route_ext_ec_ref,
+ ucontrol->value.integer.value[0]);
+
+ mutex_lock(&routing_lock);
+ switch (ucontrol->value.integer.value[0]) {
+ case EC_PORT_ID_PRIMARY_MI2S_TX:
+ msm_route_ext_ec_ref = AFE_PORT_ID_PRIMARY_MI2S_TX;
+ state = true;
+ break;
+ case EC_PORT_ID_SECONDARY_MI2S_TX:
+ msm_route_ext_ec_ref = AFE_PORT_ID_SECONDARY_MI2S_TX;
+ state = true;
+ break;
+ case EC_PORT_ID_TERTIARY_MI2S_TX:
+ msm_route_ext_ec_ref = AFE_PORT_ID_TERTIARY_MI2S_TX;
+ state = true;
+ break;
+ case EC_PORT_ID_QUATERNARY_MI2S_TX:
+ msm_route_ext_ec_ref = AFE_PORT_ID_QUATERNARY_MI2S_TX;
+ state = true;
+ break;
+ default:
+ msm_route_ext_ec_ref = AFE_PORT_INVALID;
+ break;
+ }
+ if (voc_set_ext_ec_ref(msm_route_ext_ec_ref, state)) {
+ mutex_unlock(&routing_lock);
+ snd_soc_dapm_mux_update_power(widget, kcontrol, 1, mux, e);
+ } else {
+ ret = -EINVAL;
+ mutex_unlock(&routing_lock);
+ }
+ return ret;
+}
+
+static const char * const ext_ec_ref_rx[] = {"NONE", "PRI_MI2S_TX",
+ "SEC_MI2S_TX", "TERT_MI2S_TX",
+ "QUAT_MI2S_TX"};
+
+static const struct soc_enum msm_route_ext_ec_ref_rx_enum[] = {
+ SOC_ENUM_SINGLE_EXT(5, ext_ec_ref_rx),
+};
+
+static const struct snd_kcontrol_new voc_ext_ec_mux =
+ SOC_DAPM_ENUM_EXT("VOC_EXT_EC MUX Mux", msm_route_ext_ec_ref_rx_enum[0],
+ msm_routing_ext_ec_get, msm_routing_ext_ec_put);
+
+
static const struct snd_kcontrol_new pri_i2s_rx_mixer_controls[] = {
SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_PRI_I2S_RX ,
MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer,
@@ -1958,6 +2084,15 @@
};
+static const struct snd_kcontrol_new mmul6_mixer_controls[] = {
+ SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX,
+ MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+ SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX,
+ MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer,
+ msm_routing_put_audio_mixer),
+};
+
static const struct snd_kcontrol_new pri_rx_voice_mixer_controls[] = {
SOC_SINGLE_EXT("CSVoice", MSM_BACKEND_DAI_PRI_I2S_RX,
MSM_FRONTEND_DAI_CS_VOICE, 1, 0, msm_routing_get_voice_mixer,
@@ -2964,6 +3099,7 @@
SND_SOC_DAPM_AIF_OUT("MM_UL4", "MultiMedia4 Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL5", "MultiMedia5 Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL8", "MultiMedia8 Capture", 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("MM_UL6", "MultiMedia6 Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("MM_UL9", "MultiMedia9 Capture", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("CS-VOICE_DL1", "CS-VOICE Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("CS-VOICE_UL1", "CS-VOICE Capture", 0, 0, 0, 0),
@@ -2992,6 +3128,10 @@
0, 0, 0, 0),
SND_SOC_DAPM_AIF_OUT("INTFM_UL_HL", "INT_FM_HOSTLESS Capture",
0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_IN("INTHFP_DL_HL", "INT_HFP_BT_HOSTLESS Playback",
+ 0, 0, 0, 0),
+ SND_SOC_DAPM_AIF_OUT("INTHFP_UL_HL", "INT_HFP_BT_HOSTLESS Capture",
+ 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("HDMI_DL_HL", "HDMI_HOSTLESS Playback", 0, 0, 0, 0),
SND_SOC_DAPM_AIF_IN("SEC_I2S_DL_HL", "SEC_I2S_RX_HOSTLESS Playback",
0, 0, 0, 0),
@@ -3142,6 +3282,8 @@
mmul5_mixer_controls, ARRAY_SIZE(mmul5_mixer_controls)),
SND_SOC_DAPM_MIXER("MultiMedia8 Mixer", SND_SOC_NOPM, 0, 0,
mmul8_mixer_controls, ARRAY_SIZE(mmul8_mixer_controls)),
+ SND_SOC_DAPM_MIXER("MultiMedia6 Mixer", SND_SOC_NOPM, 0, 0,
+ mmul6_mixer_controls, ARRAY_SIZE(mmul6_mixer_controls)),
SND_SOC_DAPM_MIXER("AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
auxpcm_rx_mixer_controls, ARRAY_SIZE(auxpcm_rx_mixer_controls)),
SND_SOC_DAPM_MIXER("SEC_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0,
@@ -3263,6 +3405,8 @@
SND_SOC_DAPM_MUX("SLIM0_RX_VI_FB_LCH_MUX", SND_SOC_NOPM, 0, 0,
&slim0_rx_vi_fb_lch_mux),
+ SND_SOC_DAPM_MUX("VOC_EXT_EC MUX", SND_SOC_NOPM, 0, 0,
+ &voc_ext_ec_mux),
};
@@ -3354,6 +3498,9 @@
{"QUAT_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"},
{"QUAT_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"},
{"QUAT_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"},
+ {"QUAT_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"},
+ {"QUAT_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
+ {"QUAT_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
{"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX Audio Mixer"},
{"TERT_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
@@ -3393,6 +3540,7 @@
{"MultiMedia2 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"},
{"MultiMedia1 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"},
{"MultiMedia1 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"},
+ {"MultiMedia6 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"},
{"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
{"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
@@ -3403,6 +3551,7 @@
{"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia7", "MM_DL7"},
{"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia8", "MM_DL8"},
{"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia9", "MM_DL9"},
+ {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia6", "MM_UL6"},
{"INT_BT_SCO_RX", NULL, "INTERNAL_BT_SCO_RX Audio Mixer"},
{"INTERNAL_FM_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
@@ -3435,6 +3584,7 @@
{"MultiMedia4 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"},
{"MultiMedia5 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"},
{"MultiMedia8 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"},
+ {"MultiMedia6 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"},
{"MultiMedia1 Mixer", "AFE_PCM_TX", "PCM_TX"},
{"MultiMedia4 Mixer", "AFE_PCM_TX", "PCM_TX"},
@@ -3446,6 +3596,7 @@
{"MM_UL4", NULL, "MultiMedia4 Mixer"},
{"MM_UL5", NULL, "MultiMedia5 Mixer"},
{"MM_UL8", NULL, "MultiMedia8 Mixer"},
+ {"MM_UL6", NULL, "MultiMedia6 Mixer"},
{"AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"},
{"AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"},
@@ -3560,6 +3711,12 @@
{"MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"},
{"MI2S_RX", NULL, "MI2S_RX_Voice Mixer"},
+ {"VOC_EXT_EC MUX", "PRI_MI2S_TX" , "PRI_MI2S_TX"},
+ {"VOC_EXT_EC MUX", "SEC_MI2S_TX" , "SEC_MI2S_TX"},
+ {"VOC_EXT_EC MUX", "TERT_MI2S_TX" , "TERT_MI2S_TX"},
+ {"VOC_EXT_EC MUX", "QUAT_MI2S_TX" , "QUAT_MI2S_TX"},
+ {"CS-VOICE_UL1", NULL, "VOC_EXT_EC MUX"},
+
{"Voice_Tx Mixer", "PRI_TX_Voice", "PRI_I2S_TX"},
{"Voice_Tx Mixer", "PRI_MI2S_TX_Voice", "PRI_MI2S_TX"},
{"Voice_Tx Mixer", "MI2S_TX_Voice", "MI2S_TX"},
@@ -3629,6 +3786,8 @@
{"INT_FM_RX", NULL, "INTFM_DL_HL"},
{"INTFM_UL_HL", NULL, "INT_FM_TX"},
+ {"INTHFP_UL_HL", NULL, "INT_BT_SCO_TX"},
+ {"INT_BT_SCO_RX", NULL, "MM_DL6"},
{"AUX_PCM_RX", NULL, "AUXPCM_DL_HL"},
{"AUXPCM_UL_HL", NULL, "AUX_PCM_TX"},
{"MI2S_RX", NULL, "MI2S_DL_HL"},
@@ -3794,7 +3953,9 @@
mutex_lock(&routing_lock);
topology = get_topology(path_type);
for_each_set_bit(i, &bedai->fe_sessions, MSM_FRONTEND_DAI_MM_SIZE) {
- if (fe_dai_map[i][session_type] != INVALID_SESSION) {
+ if (fe_dai_map[i][session_type].strm_id != INVALID_SESSION) {
+ fe_dai_map[i][session_type].be_srate =
+ bedai->sample_rate;
adm_close(bedai->port_id,
fe_dai_perf_mode[i][session_type]);
srs_port_id = -1;
@@ -3821,6 +3982,7 @@
u32 channels;
bool playback, capture;
uint16_t bits_per_sample = 16;
+ struct msm_pcm_routing_fdai_data *fdai;
if (be_id >= MSM_BACKEND_DAI_MAX) {
pr_err("%s: unexpected be_id %d\n", __func__, be_id);
@@ -3852,8 +4014,21 @@
capture = substream->stream == SNDRV_PCM_STREAM_CAPTURE;
for_each_set_bit(i, &bedai->fe_sessions, MSM_FRONTEND_DAI_MM_SIZE) {
- if (fe_dai_map[i][session_type] != INVALID_SESSION) {
+ fdai = &fe_dai_map[i][session_type];
+ if (fdai->strm_id != INVALID_SESSION) {
+ if (session_type == SESSION_TYPE_TX &&
+ fdai->be_srate &&
+ (fdai->be_srate != bedai->sample_rate)) {
+ pr_debug("%s: flush strm %d diff BE rates\n",
+ __func__,
+ fdai->strm_id);
+ if (fdai->event_info.event_func)
+ fdai->event_info.event_func(
+ MSM_PCM_RT_EVT_BUF_RECFG,
+ fdai->event_info.priv_data);
+ fdai->be_srate = 0; /* might not need it */
+ }
channels = bedai->channel;
if (bedai->format == SNDRV_PCM_FORMAT_S24_LE)
bits_per_sample = 24;
@@ -3880,7 +4055,7 @@
}
msm_pcm_routing_build_matrix(i,
- fe_dai_map[i][session_type], path_type,
+ fdai->strm_id, path_type,
fe_dai_perf_mode[i][session_type]);
port_id = srs_port_id = bedai->port_id;
srs_send_params(srs_port_id, 1, 0);
diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h
index 10be150..4f7c4e3 100644
--- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h
+++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.h
@@ -133,6 +133,12 @@
MSM_BACKEND_DAI_MAX,
};
+enum msm_pcm_routing_event {
+ MSM_PCM_RT_EVT_BUF_RECFG,
+ MSM_PCM_RT_EVT_DEVSWITCH,
+ MSM_PCM_RT_EVT_MAX,
+};
+
/* dai_id: front-end ID,
* dspst_id: DSP audio stream ID
* stream_type: playback or capture
@@ -142,6 +148,15 @@
void msm_pcm_routing_reg_psthr_stream(int fedai_id, int dspst_id,
int stream_type);
+struct msm_pcm_routing_evt {
+ void (*event_func)(enum msm_pcm_routing_event, void *);
+ void *priv_data;
+};
+
+void msm_pcm_routing_reg_phy_stream_v2(int fedai_id, bool perf_mode,
+ int dspst_id, int stream_type,
+ struct msm_pcm_routing_evt event_info);
+
void msm_pcm_routing_dereg_phy_stream(int fedai_id, int stream_type);
int msm_routing_check_backend_enabled(int fedai_id);
diff --git a/sound/soc/msm/qdsp6v2/q6adm.c b/sound/soc/msm/qdsp6v2/q6adm.c
index 3ee6f6e..6cb7ce1 100644
--- a/sound/soc/msm/qdsp6v2/q6adm.c
+++ b/sound/soc/msm/qdsp6v2/q6adm.c
@@ -1160,10 +1160,10 @@
} else if (channel_mode == 6) {
open.dev_channel_mapping[0] = PCM_CHANNEL_FL;
open.dev_channel_mapping[1] = PCM_CHANNEL_FR;
- open.dev_channel_mapping[2] = PCM_CHANNEL_FC;
- open.dev_channel_mapping[3] = PCM_CHANNEL_LFE;
- open.dev_channel_mapping[4] = PCM_CHANNEL_LB;
- open.dev_channel_mapping[5] = PCM_CHANNEL_RB;
+ open.dev_channel_mapping[2] = PCM_CHANNEL_LFE;
+ open.dev_channel_mapping[3] = PCM_CHANNEL_FC;
+ open.dev_channel_mapping[4] = PCM_CHANNEL_LS;
+ open.dev_channel_mapping[5] = PCM_CHANNEL_RS;
} else if (channel_mode == 8) {
open.dev_channel_mapping[0] = PCM_CHANNEL_FL;
open.dev_channel_mapping[1] = PCM_CHANNEL_FR;
@@ -1171,8 +1171,8 @@
open.dev_channel_mapping[3] = PCM_CHANNEL_FC;
open.dev_channel_mapping[4] = PCM_CHANNEL_LB;
open.dev_channel_mapping[5] = PCM_CHANNEL_RB;
- open.dev_channel_mapping[6] = PCM_CHANNEL_RLC;
- open.dev_channel_mapping[7] = PCM_CHANNEL_RRC;
+ open.dev_channel_mapping[6] = PCM_CHANNEL_FLC;
+ open.dev_channel_mapping[7] = PCM_CHANNEL_FRC;
} else {
pr_err("%s invalid num_chan %d\n", __func__,
channel_mode);
diff --git a/sound/soc/msm/qdsp6v2/q6asm.c b/sound/soc/msm/qdsp6v2/q6asm.c
index 2804c6a..631e9bd 100644
--- a/sound/soc/msm/qdsp6v2/q6asm.c
+++ b/sound/soc/msm/qdsp6v2/q6asm.c
@@ -62,10 +62,13 @@
uint32_t buf_addr_lsw;
uint32_t mmap_hdl;
};
-static int32_t q6asm_mmapcallback(struct apr_client_data *data, void *priv);
+static int32_t q6asm_srvc_callback(struct apr_client_data *data, void *priv);
static int32_t q6asm_callback(struct apr_client_data *data, void *priv);
static void q6asm_add_hdr(struct audio_client *ac, struct apr_hdr *hdr,
uint32_t pkt_size, uint32_t cmd_flg);
+static void q6asm_add_hdr_custom_topology(struct audio_client *ac,
+ struct apr_hdr *hdr,
+ uint32_t pkt_size, uint32_t cmd_flg);
static void q6asm_add_hdr_async(struct audio_client *ac, struct apr_hdr *hdr,
uint32_t pkt_size, uint32_t cmd_flg);
static int q6asm_memory_map_regions(struct audio_client *ac, int dir,
@@ -364,7 +367,6 @@
struct list_head *ptr, *next;
int result;
int size = 4096;
-
get_asm_custom_topology(&cal_block);
if (cal_block.cal_size == 0) {
pr_debug("%s: no cal to send addr= 0x%x\n",
@@ -422,8 +424,9 @@
}
}
- q6asm_add_hdr(ac, &asm_top.hdr, APR_PKT_SIZE(APR_HDR_SIZE,
- sizeof(asm_top)), TRUE);
+ q6asm_add_hdr_custom_topology(ac, &asm_top.hdr,
+ APR_PKT_SIZE(APR_HDR_SIZE,
+ sizeof(asm_top)), TRUE);
asm_top.hdr.opcode = ASM_CMD_ADD_TOPOLOGIES;
asm_top.payload_addr_lsw = cal_block.cal_paddr;
@@ -445,7 +448,7 @@
result = wait_event_timeout(ac->cmd_wait,
(atomic_read(&ac->cmd_state) == 0), 5*HZ);
if (!result) {
- pr_err("%s: Set topologies failed payload = 0x%x\n",
+ pr_err("%s: Set topologies failed after timedout payload = 0x%x\n",
__func__, cal_block.cal_paddr);
goto done;
}
@@ -731,6 +734,8 @@
}
}
+ apr_deregister(ac->apr2);
+ ac->apr2 = NULL;
apr_deregister(ac->apr);
ac->apr = NULL;
ac->mmap_apr = NULL;
@@ -775,7 +780,7 @@
if ((atomic_read(&this_mmap.ref_cnt) == 0) ||
(this_mmap.apr == NULL)) {
this_mmap.apr = apr_register("ADSP", "ASM", \
- (apr_fn)q6asm_mmapcallback,\
+ (apr_fn)q6asm_srvc_callback,\
0x0FFFFFFFF, &this_mmap);
if (this_mmap.apr == NULL) {
pr_debug("%s Unable to register APR ASM common port\n",
@@ -811,13 +816,18 @@
(apr_fn)q6asm_callback,\
((ac->session) << 8 | 0x0001),\
ac);
+
+ if (ac->apr == NULL) {
+ pr_err("%s Registration with APR failed\n", __func__);
+ goto fail;
+ }
ac->apr2 = apr_register("ADSP", "ASM", \
(apr_fn)q6asm_callback,\
((ac->session) << 8 | 0x0002),\
ac);
- if (ac->apr == NULL) {
- pr_err("%s Registration with APR failed\n", __func__);
+ if (ac->apr2 == NULL) {
+ pr_err("%s Registration with APR-2 failed\n", __func__);
goto fail;
}
rtac_set_asm_handle(n, ac->apr);
@@ -869,7 +879,6 @@
pr_err("%s: session not active: %d\n", __func__, session_id);
goto err;
}
-
return session[session_id];
err:
return NULL;
@@ -1042,7 +1051,7 @@
return -EINVAL;
}
-static int32_t q6asm_mmapcallback(struct apr_client_data *data, void *priv)
+static int32_t q6asm_srvc_callback(struct apr_client_data *data, void *priv)
{
uint32_t sid = 0;
uint32_t dir = 0;
@@ -1089,6 +1098,7 @@
switch (payload[0]) {
case ASM_CMD_SHARED_MEM_MAP_REGIONS:
case ASM_CMD_SHARED_MEM_UNMAP_REGIONS:
+ case ASM_CMD_ADD_TOPOLOGIES:
if (payload[1] != 0) {
pr_err("%s: cmd = 0x%x returned error = 0x%x sid:%d\n",
__func__, payload[0], payload[1], sid);
@@ -1246,6 +1256,7 @@
case ASM_STREAM_CMD_OPEN_READ_V3:
case ASM_STREAM_CMD_OPEN_WRITE_V3:
case ASM_STREAM_CMD_OPEN_READWRITE_V2:
+ case ASM_STREAM_CMD_OPEN_LOOPBACK_V2:
case ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2:
case ASM_STREAM_CMD_SET_ENCDEC_PARAM:
case ASM_CMD_ADD_TOPOLOGIES:
@@ -1614,6 +1625,36 @@
return;
}
+static void q6asm_add_hdr_custom_topology(struct audio_client *ac,
+ struct apr_hdr *hdr,
+ uint32_t pkt_size, uint32_t cmd_flg)
+{
+ pr_debug("%s:pkt_size=%d cmd_flg=%d session=%d\n", __func__, pkt_size,
+ cmd_flg, ac->session);
+ if (ac->apr == NULL) {
+ pr_err("%s: ac->apr is NULL", __func__);
+ return;
+ }
+
+ mutex_lock(&ac->cmd_lock);
+ hdr->hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, \
+ APR_HDR_LEN(sizeof(struct apr_hdr)),\
+ APR_PKT_VER);
+ hdr->src_svc = ((struct apr_svc *)ac->apr)->id;
+ hdr->src_domain = APR_DOMAIN_APPS;
+ hdr->dest_svc = APR_SVC_ASM;
+ hdr->dest_domain = APR_DOMAIN_ADSP;
+ hdr->src_port = ((ac->session << 8) & 0xFF00) | 0x01;
+ hdr->dest_port = 0;
+ if (cmd_flg) {
+ hdr->token = ((ac->session << 8) | 0x0001) ;
+ atomic_set(&ac->cmd_state, 1);
+ }
+ hdr->pkt_size = pkt_size;
+ mutex_unlock(&ac->cmd_lock);
+ return;
+}
+
static void q6asm_add_mmaphdr(struct audio_client *ac, struct apr_hdr *hdr,
u32 pkt_size, u32 cmd_flg, u32 token)
{
@@ -1704,6 +1745,7 @@
rc);
goto fail_cmd;
}
+ ac->io_mode |= TUN_READ_IO_MODE;
return 0;
fail_cmd:
return -EINVAL;
@@ -1797,6 +1839,7 @@
rc);
goto fail_cmd;
}
+ ac->io_mode |= TUN_WRITE_IO_MODE;
return 0;
fail_cmd:
return -EINVAL;
@@ -1937,6 +1980,49 @@
return -EINVAL;
}
+int q6asm_open_loopback_v2(struct audio_client *ac, uint16_t bits_per_sample)
+{
+ int rc = 0x00;
+ struct asm_stream_cmd_open_loopback_v2 open;
+
+ if ((ac == NULL) || (ac->apr == NULL)) {
+ pr_err("%s APR handle NULL\n", __func__);
+ return -EINVAL;
+ }
+ pr_debug("%s: session[%d]", __func__, ac->session);
+
+ q6asm_add_hdr(ac, &open.hdr, sizeof(open), TRUE);
+ open.hdr.opcode = ASM_STREAM_CMD_OPEN_LOOPBACK_V2;
+
+ open.mode_flags = 0;
+ open.src_endpointype = 0;
+ open.sink_endpointype = 0;
+ /* source endpoint : matrix */
+ open.postprocopo_id = get_asm_topology();
+ if (open.postprocopo_id == 0)
+ open.postprocopo_id = DEFAULT_POPP_TOPOLOGY;
+ open.bits_per_sample = bits_per_sample;
+ open.reserved = 0;
+
+ rc = apr_send_pkt(ac->apr, (uint32_t *) &open);
+ if (rc < 0) {
+ pr_err("%s open failed op[0x%x]rc[%d]\n", __func__,
+ open.hdr.opcode, rc);
+ goto fail_cmd;
+ }
+
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 5*HZ);
+ if (!rc) {
+ pr_err("%s timeout. waited for open_loopback rc[%d]\n",
+ __func__, rc);
+ goto fail_cmd;
+ }
+ return 0;
+fail_cmd:
+ return -EINVAL;
+}
+
int q6asm_run(struct audio_client *ac, uint32_t flags,
uint32_t msw_ts, uint32_t lsw_ts)
{
@@ -2236,21 +2322,21 @@
lchannel_mapping[3] = PCM_CHANNEL_LB;
lchannel_mapping[4] = PCM_CHANNEL_RB;
} else if (channels == 6) {
- lchannel_mapping[0] = PCM_CHANNEL_FC;
- lchannel_mapping[1] = PCM_CHANNEL_FL;
- lchannel_mapping[2] = PCM_CHANNEL_FR;
- lchannel_mapping[3] = PCM_CHANNEL_LB;
- lchannel_mapping[4] = PCM_CHANNEL_RB;
- lchannel_mapping[5] = PCM_CHANNEL_LFE;
+ lchannel_mapping[0] = PCM_CHANNEL_FL;
+ lchannel_mapping[1] = PCM_CHANNEL_FR;
+ lchannel_mapping[2] = PCM_CHANNEL_FC;
+ lchannel_mapping[3] = PCM_CHANNEL_LFE;
+ lchannel_mapping[4] = PCM_CHANNEL_LS;
+ lchannel_mapping[5] = PCM_CHANNEL_RS;
} else if (channels == 8) {
lchannel_mapping[0] = PCM_CHANNEL_FL;
lchannel_mapping[1] = PCM_CHANNEL_FR;
- lchannel_mapping[2] = PCM_CHANNEL_LFE;
- lchannel_mapping[3] = PCM_CHANNEL_FC;
+ lchannel_mapping[2] = PCM_CHANNEL_FC;
+ lchannel_mapping[3] = PCM_CHANNEL_LFE;
lchannel_mapping[4] = PCM_CHANNEL_LB;
lchannel_mapping[5] = PCM_CHANNEL_RB;
- lchannel_mapping[6] = PCM_CHANNEL_RLC;
- lchannel_mapping[7] = PCM_CHANNEL_RRC;
+ lchannel_mapping[6] = PCM_CHANNEL_FLC;
+ lchannel_mapping[7] = PCM_CHANNEL_FRC;
} else {
pr_err("%s: ERROR.unsupported num_ch = %u\n",
__func__, channels);
@@ -3930,6 +4016,58 @@
return -EINVAL;
}
+int q6asm_send_audio_effects_params(struct audio_client *ac, char *params,
+ uint32_t params_length)
+{
+ char *asm_params = NULL;
+ struct apr_hdr hdr;
+ struct asm_stream_cmd_set_pp_params_v2 payload_params;
+ int sz, rc;
+
+ pr_debug("%s\n", __func__);
+ if (!ac || ac->apr == NULL || params == NULL) {
+ pr_err("APR handle NULL or params NULL\n");
+ return -EINVAL;
+ }
+ sz = sizeof(struct apr_hdr) +
+ sizeof(struct asm_stream_cmd_set_pp_params_v2) +
+ params_length;
+ asm_params = kzalloc(sz, GFP_KERNEL);
+ if (!asm_params) {
+ pr_err("%s, adm params memory alloc failed", __func__);
+ return -ENOMEM;
+ }
+ q6asm_add_hdr_async(ac, &hdr, (sizeof(struct apr_hdr) +
+ sizeof(struct asm_stream_cmd_set_pp_params_v2) +
+ params_length), TRUE);
+ hdr.opcode = ASM_STREAM_CMD_SET_PP_PARAMS_V2;
+ payload_params.data_payload_addr_lsw = 0;
+ payload_params.data_payload_addr_msw = 0;
+ payload_params.mem_map_handle = 0;
+ payload_params.data_payload_size = params_length;
+ memcpy(((u8 *)asm_params), &hdr, sizeof(struct apr_hdr));
+ memcpy(((u8 *)asm_params + sizeof(struct apr_hdr)), &payload_params,
+ sizeof(struct asm_stream_cmd_set_pp_params_v2));
+ memcpy(((u8 *)asm_params + sizeof(struct apr_hdr) +
+ sizeof(struct asm_stream_cmd_set_pp_params_v2)),
+ params, params_length);
+ rc = apr_send_pkt(ac->apr, (uint32_t *) asm_params);
+ if (rc < 0) {
+ pr_err("%s: audio effects set-params send failed\n", __func__);
+ goto fail_send_param;
+ }
+ rc = wait_event_timeout(ac->cmd_wait,
+ (atomic_read(&ac->cmd_state) == 0), 1*HZ);
+ if (!rc) {
+ pr_err("%s: timeout, audio effects set-params\n", __func__);
+ goto fail_send_param;
+ }
+ rc = 0;
+fail_send_param:
+ kfree(asm_params);
+ return rc;
+}
+
static int __q6asm_cmd(struct audio_client *ac, int cmd, uint32_t stream_id)
{
struct apr_hdr hdr;
@@ -4125,9 +4263,11 @@
{
int cnt = 0;
int loopcnt = 0;
+ int used;
struct audio_port_data *port = NULL;
if (ac->io_mode & SYNC_IO_MODE) {
+ used = (ac->io_mode & TUN_WRITE_IO_MODE ? 1 : 0);
mutex_lock(&ac->cmd_lock);
for (loopcnt = 0; loopcnt <= OUT; loopcnt++) {
port = &ac->port[loopcnt];
@@ -4137,7 +4277,7 @@
while (cnt >= 0) {
if (!port->buf)
continue;
- port->buf[cnt].used = 1;
+ port->buf[cnt].used = used;
cnt--;
}
}
diff --git a/sound/soc/msm/qdsp6v2/q6voice.c b/sound/soc/msm/qdsp6v2/q6voice.c
index 673ecff..c4395c2 100644
--- a/sound/soc/msm/qdsp6v2/q6voice.c
+++ b/sound/soc/msm/qdsp6v2/q6voice.c
@@ -350,6 +350,11 @@
NULL : &common.voice[idx]);
}
+static bool is_voice_session(u32 session_id)
+{
+ return (session_id == common.voice[VOC_PATH_PASSIVE].session_id);
+}
+
static bool is_voip_session(u32 session_id)
{
return (session_id == common.voice[VOC_PATH_FULL].session_id);
@@ -1861,10 +1866,18 @@
cvp_setdev_cmd.cvp_set_device_v2.tx_port_id = v->dev_tx.port_id;
cvp_setdev_cmd.cvp_set_device_v2.rx_port_id = v->dev_rx.port_id;
- cvp_setdev_cmd.cvp_set_device_v2.vocproc_mode =
+
+ if (common.ec_ref_ext) {
+ cvp_setdev_cmd.cvp_set_device_v2.vocproc_mode =
+ VSS_IVOCPROC_VOCPROC_MODE_EC_EXT_MIXING;
+ cvp_setdev_cmd.cvp_set_device_v2.ec_ref_port_id =
+ common.ec_port_id;
+ } else {
+ cvp_setdev_cmd.cvp_set_device_v2.vocproc_mode =
VSS_IVOCPROC_VOCPROC_MODE_EC_INT_MIXING;
- cvp_setdev_cmd.cvp_set_device_v2.ec_ref_port_id =
+ cvp_setdev_cmd.cvp_set_device_v2.ec_ref_port_id =
VSS_IVOCPROC_PORT_ID_NONE;
+ }
pr_debug("topology=%d , tx_port_id=%d, rx_port_id=%d\n",
cvp_setdev_cmd.cvp_set_device_v2.tx_topology_id,
cvp_setdev_cmd.cvp_set_device_v2.tx_port_id,
@@ -3026,10 +3039,17 @@
cvp_session_cmd.cvp_session.rx_port_id = v->dev_rx.port_id;
cvp_session_cmd.cvp_session.profile_id =
VSS_ICOMMON_CAL_NETWORK_ID_NONE;
- cvp_session_cmd.cvp_session.vocproc_mode =
+ if (common.ec_ref_ext) {
+ cvp_session_cmd.cvp_session.vocproc_mode =
+ VSS_IVOCPROC_VOCPROC_MODE_EC_EXT_MIXING;
+ cvp_session_cmd.cvp_session.ec_ref_port_id =
+ common.ec_port_id;
+ } else {
+ cvp_session_cmd.cvp_session.vocproc_mode =
VSS_IVOCPROC_VOCPROC_MODE_EC_INT_MIXING;
- cvp_session_cmd.cvp_session.ec_ref_port_id =
+ cvp_session_cmd.cvp_session.ec_ref_port_id =
VSS_IVOCPROC_PORT_ID_NONE;
+ }
pr_debug("tx_topology: %d tx_port_id=%d, rx_port_id=%d, mode: 0x%x\n",
cvp_session_cmd.cvp_session.tx_topology_id,
@@ -4257,8 +4277,10 @@
v = voice_get_session(voc_get_session_id(VOICE_SESSION_NAME));
else if (port_id == VOICE2_PLAYBACK_TX)
v = voice_get_session(voc_get_session_id(VOICE2_SESSION_NAME));
+ else
+ pr_err("%s: Invalid port_id 0x%x", __func__, port_id);
- if (v != NULL) {
+ while (v != NULL) {
mutex_lock(&v->lock);
v->music_info.port_id = port_id;
v->music_info.play_enable = set;
@@ -4278,8 +4300,17 @@
}
mutex_unlock(&v->lock);
- } else {
- pr_err("%s: Invalid port_id 0x%x", __func__, port_id);
+
+ /* Voice and VoLTE call use the same pseudo port and hence
+ * use the same mixer control. So enable incall delivery
+ * for VoLTE as well with Voice.
+ */
+ if (is_voice_session(v->session_id)) {
+ v = voice_get_session(voc_get_session_id(
+ VOLTE_SESSION_NAME));
+ } else {
+ break;
+ }
}
return ret;
@@ -4313,7 +4344,8 @@
v->voc_state = VOC_CHANGE;
}
-
+ if (common.ec_ref_ext)
+ voc_set_ext_ec_ref(AFE_PORT_INVALID, false);
fail: mutex_unlock(&v->lock);
return ret;
@@ -4756,6 +4788,8 @@
ret = -EINVAL;
}
+ if (common.ec_ref_ext)
+ voc_set_ext_ec_ref(AFE_PORT_INVALID, false);
mutex_unlock(&v->lock);
return ret;
@@ -4973,6 +5007,28 @@
return ret;
}
+int voc_set_ext_ec_ref(uint16_t port_id, bool state)
+{
+ int ret = 0;
+
+ mutex_lock(&common.common_lock);
+ if (state == true) {
+ if (port_id == AFE_PORT_INVALID) {
+ pr_err("%s: Invalid port id", __func__);
+ ret = -EINVAL;
+ goto exit;
+ }
+ common.ec_port_id = port_id;
+ common.ec_ref_ext = true;
+ } else {
+ common.ec_ref_ext = false;
+ common.ec_port_id = port_id;
+ }
+exit:
+ mutex_unlock(&common.common_lock);
+ return ret;
+}
+
void voc_register_mvs_cb(ul_cb_fn ul_cb,
dl_cb_fn dl_cb,
void *private_data)
@@ -5807,7 +5863,7 @@
common.default_vol_step_val = 0;
common.default_vol_ramp_duration_ms = DEFAULT_VOLUME_RAMP_DURATION;
common.default_mute_ramp_duration_ms = DEFAULT_MUTE_RAMP_DURATION;
-
+ common.ec_ref_ext = false;
/* Initialize MVS info. */
common.mvs_info.network_type = VSS_NETWORK_ID_DEFAULT;
diff --git a/sound/soc/msm/qdsp6v2/q6voice.h b/sound/soc/msm/qdsp6v2/q6voice.h
index 39f0986..5c0cf21 100644
--- a/sound/soc/msm/qdsp6v2/q6voice.h
+++ b/sound/soc/msm/qdsp6v2/q6voice.h
@@ -1328,6 +1328,8 @@
uint32_t default_vol_step_val;
uint32_t default_vol_ramp_duration_ms;
uint32_t default_mute_ramp_duration_ms;
+ bool ec_ref_ext;
+ uint16_t ec_port_id;
/* APR to MVM in the Q6 */
void *apr_q6_mvm;
@@ -1462,5 +1464,6 @@
int voc_start_playback(uint32_t set, uint16_t port_id);
int voc_start_record(uint32_t port_id, uint32_t set, uint32_t session_id);
int voice_get_idx_for_session(u32 session_id);
+int voc_set_ext_ec_ref(uint16_t port_id, bool state);
#endif
diff --git a/sound/soc/msm/qdsp6v2/rtac.c b/sound/soc/msm/qdsp6v2/rtac.c
index ee21112..f74dbe2 100644
--- a/sound/soc/msm/qdsp6v2/rtac.c
+++ b/sound/soc/msm/qdsp6v2/rtac.c
@@ -100,6 +100,28 @@
struct rtac_adm_data device[RTAC_MAX_ACTIVE_DEVICES];
};
static struct rtac_adm rtac_adm_data;
+
+
+/* ADM V2 data */
+struct rtac_popp_data {
+ uint32_t popp;
+ uint32_t popp_topology;
+};
+
+struct rtac_adm_data_v2 {
+ uint32_t topology_id;
+ uint32_t afe_port;
+ uint32_t copp;
+ uint32_t num_of_popp;
+ struct rtac_popp_data popp[RTAC_MAX_ACTIVE_POPP];
+};
+
+struct rtac_adm_v2 {
+ uint32_t num_of_dev;
+ struct rtac_adm_data_v2 device[RTAC_MAX_ACTIVE_DEVICES];
+};
+
+static struct rtac_adm_v2 rtac_adm_data_v2;
static u32 *rtac_adm_buffer;
@@ -356,6 +378,147 @@
return result;
}
+
+/* ADM Info V2 */
+static void add_popp_v2(u32 dev_idx, u32 port_id, u32 popp_id)
+{
+ u32 i = 0;
+
+ for (; i < rtac_adm_data_v2.device[dev_idx].num_of_popp; i++)
+ if (rtac_adm_data_v2.device[dev_idx].popp[i].popp == popp_id)
+ goto done;
+
+ if (rtac_adm_data_v2.device[dev_idx].num_of_popp ==
+ RTAC_MAX_ACTIVE_POPP) {
+ pr_err("%s, Max POPP!\n", __func__);
+ goto done;
+ }
+ rtac_adm_data_v2.device[dev_idx].popp[
+ rtac_adm_data_v2.device[dev_idx].num_of_popp].popp = popp_id;
+ rtac_adm_data_v2.device[dev_idx].popp[
+ rtac_adm_data_v2.device[dev_idx].num_of_popp++].popp_topology =
+ get_asm_topology();
+done:
+ return;
+}
+
+static void rtac_add_adm_device_v2(u32 port_id, u32 copp_id, u32 path_id,
+ u32 popp_id)
+{
+ u32 i = 0;
+ pr_debug("%s: port_id = %d, popp_id = %d\n", __func__, port_id,
+ popp_id);
+
+ if (rtac_adm_data_v2.num_of_dev == RTAC_MAX_ACTIVE_DEVICES) {
+ pr_err("%s, Can't add anymore RTAC devices!\n", __func__);
+ goto done;
+ }
+
+ /* Check if device already added */
+ if (rtac_adm_data_v2.num_of_dev != 0) {
+ for (; i < rtac_adm_data_v2.num_of_dev; i++) {
+ if (rtac_adm_data_v2.device[i].afe_port == port_id) {
+ add_popp_v2(i, port_id, popp_id);
+ goto done;
+ }
+ if (rtac_adm_data_v2.device[i].num_of_popp ==
+ RTAC_MAX_ACTIVE_POPP) {
+ pr_err("%s, Max POPP!\n", __func__);
+ goto done;
+ }
+ }
+ }
+
+ /* Add device */
+ rtac_adm_data_v2.num_of_dev++;
+
+ if (path_id == ADM_PATH_PLAYBACK)
+ rtac_adm_data_v2.device[i].topology_id =
+ get_adm_rx_topology();
+ else
+ rtac_adm_data_v2.device[i].topology_id =
+ get_adm_tx_topology();
+ rtac_adm_data_v2.device[i].afe_port = port_id;
+ rtac_adm_data_v2.device[i].copp = copp_id;
+ rtac_adm_data_v2.device[i].popp[
+ rtac_adm_data_v2.device[i].num_of_popp].popp = popp_id;
+ rtac_adm_data_v2.device[i].popp[
+ rtac_adm_data_v2.device[i].num_of_popp++].popp_topology =
+ get_asm_topology();
+done:
+ return;
+}
+
+static void shift_adm_devices_v2(u32 dev_idx)
+{
+ for (; dev_idx < rtac_adm_data_v2.num_of_dev; dev_idx++) {
+ memcpy(&rtac_adm_data_v2.device[dev_idx],
+ &rtac_adm_data_v2.device[dev_idx + 1],
+ sizeof(rtac_adm_data_v2.device[dev_idx]));
+ memset(&rtac_adm_data_v2.device[dev_idx + 1], 0,
+ sizeof(rtac_adm_data_v2.device[dev_idx]));
+ }
+}
+
+static void shift_popp_v2(u32 copp_idx, u32 popp_idx)
+{
+ for (; popp_idx < rtac_adm_data_v2.device[copp_idx].num_of_popp;
+ popp_idx++) {
+ memcpy(&rtac_adm_data_v2.device[copp_idx].popp[popp_idx].popp,
+ &rtac_adm_data_v2.device[copp_idx].popp[popp_idx + 1].
+ popp, sizeof(uint32_t));
+ memcpy(&rtac_adm_data_v2.device[copp_idx].popp[popp_idx].
+ popp_topology,
+ &rtac_adm_data_v2.device[copp_idx].popp[popp_idx + 1].
+ popp_topology,
+ sizeof(uint32_t));
+ memset(&rtac_adm_data_v2.device[copp_idx].popp[popp_idx + 1].
+ popp, 0, sizeof(uint32_t));
+ memset(&rtac_adm_data_v2.device[copp_idx].popp[popp_idx + 1].
+ popp_topology, 0, sizeof(uint32_t));
+ }
+}
+
+static void rtac_remove_adm_device_v2(u32 port_id)
+{
+ s32 i;
+ pr_debug("%s: port_id = %d\n", __func__, port_id);
+
+ /* look for device */
+ for (i = 0; i < rtac_adm_data_v2.num_of_dev; i++) {
+ if (rtac_adm_data_v2.device[i].afe_port == port_id) {
+ memset(&rtac_adm_data_v2.device[i], 0,
+ sizeof(rtac_adm_data_v2.device[i]));
+ rtac_adm_data_v2.num_of_dev--;
+
+ if (rtac_adm_data_v2.num_of_dev >= 1) {
+ shift_adm_devices_v2(i);
+ break;
+ }
+ }
+ }
+ return;
+}
+
+static void rtac_remove_popp_from_adm_devices_v2(u32 popp_id)
+{
+ s32 i, j;
+ pr_debug("%s: popp_id = %d\n", __func__, popp_id);
+
+ for (i = 0; i < rtac_adm_data_v2.num_of_dev; i++) {
+ for (j = 0; j < rtac_adm_data_v2.device[i].num_of_popp; j++) {
+ if (rtac_adm_data_v2.device[i].popp[j].popp ==
+ popp_id) {
+ rtac_adm_data_v2.device[i].popp[j].popp = 0;
+ rtac_adm_data_v2.device[i].popp[j].
+ popp_topology = 0;
+ rtac_adm_data_v2.device[i].num_of_popp--;
+ shift_popp_v2(i, j);
+ }
+ }
+ }
+}
+
/* ADM Info */
void add_popp(u32 dev_idx, u32 port_id, u32 popp_id)
{
@@ -383,6 +546,8 @@
popp_id);
mutex_lock(&rtac_adm_mutex);
+ rtac_add_adm_device_v2(port_id, copp_id, path_id, popp_id);
+
if (rtac_adm_data.num_of_dev == RTAC_MAX_ACTIVE_DEVICES) {
pr_err("%s, Can't add anymore RTAC devices!\n", __func__);
goto done;
@@ -440,7 +605,7 @@
&rtac_adm_data.device[copp_idx].popp[popp_idx + 1],
sizeof(uint32_t));
memset(&rtac_adm_data.device[copp_idx].popp[popp_idx + 1], 0,
- sizeof(uint32_t));
+ sizeof(uint32_t));
}
}
@@ -450,6 +615,8 @@
pr_debug("%s: port_id = %d\n", __func__, port_id);
mutex_lock(&rtac_adm_mutex);
+ rtac_remove_adm_device_v2(port_id);
+
/* look for device */
for (i = 0; i < rtac_adm_data.num_of_dev; i++) {
if (rtac_adm_data.device[i].afe_port == port_id) {
@@ -474,6 +641,7 @@
pr_debug("%s: popp_id = %d\n", __func__, popp_id);
mutex_lock(&rtac_adm_mutex);
+ rtac_remove_popp_from_adm_devices_v2(popp_id);
for (i = 0; i < rtac_adm_data.num_of_dev; i++) {
for (j = 0; j < rtac_adm_data.device[i].num_of_popp; j++) {
@@ -1269,6 +1437,13 @@
else
result = sizeof(rtac_adm_data);
break;
+ case AUDIO_GET_RTAC_ADM_INFO_V2:
+ if (copy_to_user((void *)arg, &rtac_adm_data_v2,
+ sizeof(rtac_adm_data_v2)))
+ pr_err("%s: Could not copy to userspace!\n", __func__);
+ else
+ result = sizeof(rtac_adm_data_v2);
+ break;
case AUDIO_GET_RTAC_VOICE_INFO:
if (copy_to_user((void *)arg, &rtac_voice_data,
sizeof(rtac_voice_data)))
@@ -1339,6 +1514,7 @@
/* ADM */
memset(&rtac_adm_data, 0, sizeof(rtac_adm_data));
+ memset(&rtac_adm_data_v2, 0, sizeof(rtac_adm_data_v2));
rtac_adm_apr_data.apr_handle = NULL;
atomic_set(&rtac_adm_apr_data.cmd_state, 0);
init_waitqueue_head(&rtac_adm_apr_data.cmd_wait);
diff --git a/sound/soc/soc-compress.c b/sound/soc/soc-compress.c
index 58b8399..b9af9b6 100644
--- a/sound/soc/soc-compress.c
+++ b/sound/soc/soc-compress.c
@@ -756,6 +756,14 @@
rtd->compr = compr;
compr->private_data = rtd;
+ if (platform->driver->pcm_new) {
+ ret = platform->driver->pcm_new(rtd);
+ if (ret < 0) {
+ pr_err("asoc: compress pcm constructor failed\n");
+ goto compr_err;
+ }
+ }
+
printk(KERN_INFO "compress asoc: %s <-> %s mapping ok\n", codec_dai->name,
cpu_dai->name);
return ret;
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index bc3f6a7..63bbbdd 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -1922,7 +1922,7 @@
{
struct snd_soc_card *card = widget->dapm->card;
int ret;
- mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME);
+ mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_PCM);
ret = soc_dapm_mux_update_power(widget, kcontrol, change, mux, e);
mutex_unlock(&card->dapm_mutex);
return ret;
@@ -1970,7 +1970,7 @@
{
struct snd_soc_card *card = widget->dapm->card;
int ret;
- mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME);
+ mutex_lock_nested(&card->dapm_mutex, SND_SOC_DAPM_CLASS_PCM);
ret = soc_dapm_mixer_update_power(widget, kcontrol, connect);
mutex_unlock(&card->dapm_mutex);
return ret;
diff --git a/sound/soc/soc-jack.c b/sound/soc/soc-jack.c
index 9eb96e5..60a401a 100644
--- a/sound/soc/soc-jack.c
+++ b/sound/soc/soc-jack.c
@@ -36,6 +36,7 @@
int snd_soc_jack_new(struct snd_soc_codec *codec, const char *id, int type,
struct snd_soc_jack *jack)
{
+ mutex_init(&jack->mutex);
jack->codec = codec;
INIT_LIST_HEAD(&jack->pins);
INIT_LIST_HEAD(&jack->jack_zones);
@@ -75,7 +76,7 @@
codec = jack->codec;
dapm = &codec->dapm;
- mutex_lock(&codec->mutex);
+ mutex_lock(&jack->mutex);
oldstatus = jack->status;
@@ -109,7 +110,7 @@
snd_jack_report(jack->jack, jack->status);
out:
- mutex_unlock(&codec->mutex);
+ mutex_unlock(&jack->mutex);
}
EXPORT_SYMBOL_GPL(snd_soc_jack_report);