| /* |
| * Copyright (C) 2008 Google, Inc. |
| * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved. |
| * |
| * This software is licensed under the terms of the GNU General Public |
| * License version 2, as published by the Free Software Foundation, and |
| * may be copied, distributed, and modified under those terms. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| */ |
| |
| #include <linux/kernel.h> |
| #include <linux/platform_device.h> |
| #include <linux/msm_rotator.h> |
| #include <linux/dma-mapping.h> |
| #include <linux/msm_kgsl.h> |
| #include <linux/android_pmem.h> |
| #include <linux/regulator/machine.h> |
| #include <mach/irqs.h> |
| #include <mach/msm_iomap.h> |
| #include <mach/dma.h> |
| #include <mach/board.h> |
| #include <asm/clkdev.h> |
| |
| #include "devices.h" |
| #include "gpio_hw.h" |
| #include "footswitch.h" |
| |
| #include <asm/mach/flash.h> |
| |
| #include <asm/mach/mmc.h> |
| #include <mach/msm_hsusb.h> |
| #ifdef CONFIG_PMIC8058 |
| #include <linux/mfd/pmic8058.h> |
| #endif |
| #include <mach/dal_axi.h> |
| #include <mach/msm_memtypes.h> |
| |
| /* EBI THERMAL DRIVER */ |
| static struct resource msm_ebi0_thermal_resources[] = { |
| { |
| .start = 0xA8600000, |
| .end = 0xA86005FF, |
| .name = "physbase", |
| .flags = IORESOURCE_MEM |
| } |
| }; |
| |
| struct platform_device msm_ebi0_thermal = { |
| .name = "msm_popmem-tm", |
| .id = 0, |
| .num_resources = 1, |
| .resource = msm_ebi0_thermal_resources |
| }; |
| |
| static struct resource msm_ebi1_thermal_resources[] = { |
| { |
| .start = 0xA8700000, |
| .end = 0xA87005FF, |
| .name = "physbase", |
| .flags = IORESOURCE_MEM |
| } |
| }; |
| |
| struct platform_device msm_ebi1_thermal = { |
| .name = "msm_popmem-tm", |
| .id = 1, |
| .num_resources = 1, |
| .resource = msm_ebi1_thermal_resources |
| }; |
| |
| |
| static struct resource resources_uart1[] = { |
| { |
| .start = INT_UART1, |
| .end = INT_UART1, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .start = MSM_UART1_PHYS, |
| .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| }; |
| |
| static struct resource resources_uart2[] = { |
| { |
| .start = INT_UART2, |
| .end = INT_UART2, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .start = MSM_UART2_PHYS, |
| .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| .name = "uart_resource" |
| }, |
| }; |
| |
| static struct resource resources_uart3[] = { |
| { |
| .start = INT_UART3, |
| .end = INT_UART3, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .start = MSM_UART3_PHYS, |
| .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| }; |
| |
| struct platform_device msm_device_uart1 = { |
| .name = "msm_serial", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(resources_uart1), |
| .resource = resources_uart1, |
| }; |
| |
| struct platform_device msm_device_uart2 = { |
| .name = "msm_serial", |
| .id = 1, |
| .num_resources = ARRAY_SIZE(resources_uart2), |
| .resource = resources_uart2, |
| }; |
| |
| struct platform_device msm_device_uart3 = { |
| .name = "msm_serial", |
| .id = 2, |
| .num_resources = ARRAY_SIZE(resources_uart3), |
| .resource = resources_uart3, |
| }; |
| |
| #define MSM_UART1DM_PHYS 0xA3300000 |
| #define MSM_UART2DM_PHYS 0xA3200000 |
| static struct resource msm_uart1_dm_resources[] = { |
| { |
| .start = MSM_UART1DM_PHYS, |
| .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_UART1DM_IRQ, |
| .end = INT_UART1DM_IRQ, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .start = INT_UART1DM_RX, |
| .end = INT_UART1DM_RX, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .start = DMOV_HSUART1_TX_CHAN, |
| .end = DMOV_HSUART1_RX_CHAN, |
| .name = "uartdm_channels", |
| .flags = IORESOURCE_DMA, |
| }, |
| { |
| .start = DMOV_HSUART1_TX_CRCI, |
| .end = DMOV_HSUART1_RX_CRCI, |
| .name = "uartdm_crci", |
| .flags = IORESOURCE_DMA, |
| }, |
| }; |
| |
| static u64 msm_uart_dm1_dma_mask = DMA_BIT_MASK(32); |
| |
| struct platform_device msm_device_uart_dm1 = { |
| .name = "msm_serial_hs", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(msm_uart1_dm_resources), |
| .resource = msm_uart1_dm_resources, |
| .dev = { |
| .dma_mask = &msm_uart_dm1_dma_mask, |
| .coherent_dma_mask = DMA_BIT_MASK(32), |
| }, |
| }; |
| |
| static struct resource msm_uart2_dm_resources[] = { |
| { |
| .start = MSM_UART2DM_PHYS, |
| .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_UART2DM_IRQ, |
| .end = INT_UART2DM_IRQ, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .start = INT_UART2DM_RX, |
| .end = INT_UART2DM_RX, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .start = DMOV_HSUART2_TX_CHAN, |
| .end = DMOV_HSUART2_RX_CHAN, |
| .name = "uartdm_channels", |
| .flags = IORESOURCE_DMA, |
| }, |
| { |
| .start = DMOV_HSUART2_TX_CRCI, |
| .end = DMOV_HSUART2_RX_CRCI, |
| .name = "uartdm_crci", |
| .flags = IORESOURCE_DMA, |
| }, |
| }; |
| |
| static u64 msm_uart_dm2_dma_mask = DMA_BIT_MASK(32); |
| |
| struct platform_device msm_device_uart_dm2 = { |
| .name = "msm_serial_hs", |
| .id = 1, |
| .num_resources = ARRAY_SIZE(msm_uart2_dm_resources), |
| .resource = msm_uart2_dm_resources, |
| .dev = { |
| .dma_mask = &msm_uart_dm2_dma_mask, |
| .coherent_dma_mask = DMA_BIT_MASK(32), |
| }, |
| }; |
| |
| #define MSM_I2C_SIZE SZ_4K |
| #define MSM_I2C_PHYS 0xACD00000 |
| #define MSM_I2C_2_PHYS 0xACF00000 |
| static struct resource resources_i2c_2[] = { |
| { |
| .start = MSM_I2C_2_PHYS, |
| .end = MSM_I2C_2_PHYS + MSM_I2C_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_PWB_I2C_2, |
| .end = INT_PWB_I2C_2, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| struct platform_device msm_device_i2c_2 = { |
| .name = "msm_i2c", |
| .id = 2, |
| .num_resources = ARRAY_SIZE(resources_i2c_2), |
| .resource = resources_i2c_2, |
| }; |
| |
| static struct resource resources_i2c[] = { |
| { |
| .start = MSM_I2C_PHYS, |
| .end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_PWB_I2C, |
| .end = INT_PWB_I2C, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| struct platform_device msm_device_i2c = { |
| .name = "msm_i2c", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(resources_i2c), |
| .resource = resources_i2c, |
| }; |
| |
| #define MSM_QUP_PHYS 0xA8301000 |
| #define MSM_GSBI_QUP_I2C_PHYS 0xA8300000 |
| #define MSM_QUP_SIZE SZ_4K |
| static struct resource resources_qup[] = { |
| { |
| .name = "qup_phys_addr", |
| .start = MSM_QUP_PHYS, |
| .end = MSM_QUP_PHYS + MSM_QUP_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .name = "gsbi_qup_i2c_addr", |
| .start = MSM_GSBI_QUP_I2C_PHYS, |
| .end = MSM_GSBI_QUP_I2C_PHYS + 4 - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .name = "qup_in_intr", |
| .start = INT_PWB_QUP_IN, |
| .end = INT_PWB_QUP_IN, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .name = "qup_out_intr", |
| .start = INT_PWB_QUP_OUT, |
| .end = INT_PWB_QUP_OUT, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .name = "qup_err_intr", |
| .start = INT_PWB_QUP_ERR, |
| .end = INT_PWB_QUP_ERR, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| struct platform_device qup_device_i2c = { |
| .name = "qup_i2c", |
| .id = 4, |
| .num_resources = ARRAY_SIZE(resources_qup), |
| .resource = resources_qup, |
| }; |
| |
| #ifdef CONFIG_MSM_SSBI |
| #define MSM_SSBI_PMIC1_PHYS 0xAD900000 |
| static struct resource msm_ssbi_pmic1_resources[] = { |
| { |
| .start = MSM_SSBI_PMIC1_PHYS, |
| .end = MSM_SSBI_PMIC1_PHYS + SZ_4K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| }; |
| |
| struct platform_device msm_device_ssbi_pmic1 = { |
| .name = "msm_ssbi", |
| .id = 0, |
| .resource = msm_ssbi_pmic1_resources, |
| .num_resources = ARRAY_SIZE(msm_ssbi_pmic1_resources), |
| }; |
| #endif |
| |
| #ifdef CONFIG_I2C_SSBI |
| #define MSM_SSBI7_PHYS 0xAC800000 |
| static struct resource msm_ssbi7_resources[] = { |
| { |
| .name = "ssbi_base", |
| .start = MSM_SSBI7_PHYS, |
| .end = MSM_SSBI7_PHYS + SZ_4K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| }; |
| |
| struct platform_device msm_device_ssbi7 = { |
| .name = "i2c_ssbi", |
| .id = 7, |
| .num_resources = ARRAY_SIZE(msm_ssbi7_resources), |
| .resource = msm_ssbi7_resources, |
| }; |
| #endif /* CONFIG_I2C_SSBI */ |
| |
| #define MSM_HSUSB_PHYS 0xA3600000 |
| static struct resource resources_hsusb_otg[] = { |
| { |
| .start = MSM_HSUSB_PHYS, |
| .end = MSM_HSUSB_PHYS + SZ_1K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_USB_HS, |
| .end = INT_USB_HS, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| static u64 dma_mask = 0xffffffffULL; |
| struct platform_device msm_device_hsusb_otg = { |
| .name = "msm_hsusb_otg", |
| .id = -1, |
| .num_resources = ARRAY_SIZE(resources_hsusb_otg), |
| .resource = resources_hsusb_otg, |
| .dev = { |
| .dma_mask = &dma_mask, |
| .coherent_dma_mask = 0xffffffffULL, |
| }, |
| }; |
| |
| static struct resource resources_hsusb_peripheral[] = { |
| { |
| .start = MSM_HSUSB_PHYS, |
| .end = MSM_HSUSB_PHYS + SZ_1K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_USB_HS, |
| .end = INT_USB_HS, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| static struct resource resources_gadget_peripheral[] = { |
| { |
| .start = MSM_HSUSB_PHYS, |
| .end = MSM_HSUSB_PHYS + SZ_1K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_USB_HS, |
| .end = INT_USB_HS, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| struct platform_device msm_device_hsusb_peripheral = { |
| .name = "msm_hsusb_peripheral", |
| .id = -1, |
| .num_resources = ARRAY_SIZE(resources_hsusb_peripheral), |
| .resource = resources_hsusb_peripheral, |
| .dev = { |
| .dma_mask = &dma_mask, |
| .coherent_dma_mask = 0xffffffffULL, |
| }, |
| }; |
| |
| struct platform_device msm_device_gadget_peripheral = { |
| .name = "msm_hsusb", |
| .id = -1, |
| .num_resources = ARRAY_SIZE(resources_gadget_peripheral), |
| .resource = resources_gadget_peripheral, |
| .dev = { |
| .dma_mask = &dma_mask, |
| .coherent_dma_mask = 0xffffffffULL, |
| }, |
| }; |
| |
| static struct resource resources_hsusb_host[] = { |
| { |
| .start = MSM_HSUSB_PHYS, |
| .end = MSM_HSUSB_PHYS + SZ_1K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_USB_HS, |
| .end = INT_USB_HS, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| struct platform_device msm_device_hsusb_host = { |
| .name = "msm_hsusb_host", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(resources_hsusb_host), |
| .resource = resources_hsusb_host, |
| .dev = { |
| .dma_mask = &dma_mask, |
| .coherent_dma_mask = 0xffffffffULL, |
| }, |
| }; |
| |
| static struct platform_device *msm_host_devices[] = { |
| &msm_device_hsusb_host, |
| }; |
| |
| int msm_add_host(unsigned int host, struct msm_usb_host_platform_data *plat) |
| { |
| struct platform_device *pdev; |
| |
| pdev = msm_host_devices[host]; |
| if (!pdev) |
| return -ENODEV; |
| pdev->dev.platform_data = plat; |
| return platform_device_register(pdev); |
| } |
| |
| struct platform_device asoc_msm_pcm = { |
| .name = "msm-dsp-audio", |
| .id = 0, |
| }; |
| |
| struct platform_device asoc_msm_dai0 = { |
| .name = "msm-codec-dai", |
| .id = 0, |
| }; |
| |
| struct platform_device asoc_msm_dai1 = { |
| .name = "msm-cpu-dai", |
| .id = 0, |
| }; |
| |
| #if defined (CONFIG_SND_MSM_MVS_DAI_SOC) |
| struct platform_device asoc_msm_mvs = { |
| .name = "msm-mvs-audio", |
| .id = 0, |
| }; |
| |
| struct platform_device asoc_mvs_dai0 = { |
| .name = "mvs-codec-dai", |
| .id = 0, |
| }; |
| |
| struct platform_device asoc_mvs_dai1 = { |
| .name = "mvs-cpu-dai", |
| .id = 0, |
| }; |
| #endif |
| |
| #define MSM_NAND_PHYS 0xA0200000 |
| #define MSM_NANDC01_PHYS 0xA0240000 |
| #define MSM_NANDC10_PHYS 0xA0280000 |
| #define MSM_NANDC11_PHYS 0xA02C0000 |
| #define EBI2_REG_BASE 0xA0000000 |
| static struct resource resources_nand[] = { |
| [0] = { |
| .name = "msm_nand_dmac", |
| .start = DMOV_NAND_CHAN, |
| .end = DMOV_NAND_CHAN, |
| .flags = IORESOURCE_DMA, |
| }, |
| [1] = { |
| .name = "msm_nand_phys", |
| .start = MSM_NAND_PHYS, |
| .end = MSM_NAND_PHYS + 0x7FF, |
| .flags = IORESOURCE_MEM, |
| }, |
| [2] = { |
| .name = "msm_nandc01_phys", |
| .start = MSM_NANDC01_PHYS, |
| .end = MSM_NANDC01_PHYS + 0x7FF, |
| .flags = IORESOURCE_MEM, |
| }, |
| [3] = { |
| .name = "msm_nandc10_phys", |
| .start = MSM_NANDC10_PHYS, |
| .end = MSM_NANDC10_PHYS + 0x7FF, |
| .flags = IORESOURCE_MEM, |
| }, |
| [4] = { |
| .name = "msm_nandc11_phys", |
| .start = MSM_NANDC11_PHYS, |
| .end = MSM_NANDC11_PHYS + 0x7FF, |
| .flags = IORESOURCE_MEM, |
| }, |
| [5] = { |
| .name = "ebi2_reg_base", |
| .start = EBI2_REG_BASE, |
| .end = EBI2_REG_BASE + 0x60, |
| .flags = IORESOURCE_MEM, |
| }, |
| }; |
| |
| static struct resource resources_otg[] = { |
| { |
| .start = MSM_HSUSB_PHYS, |
| .end = MSM_HSUSB_PHYS + SZ_1K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_USB_HS, |
| .end = INT_USB_HS, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .name = "vbus_on", |
| .start = PMIC8058_IRQ_BASE + PM8058_CHGVAL_IRQ, |
| .end = PMIC8058_IRQ_BASE + PM8058_CHGVAL_IRQ, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| struct platform_device msm_device_otg = { |
| .name = "msm_otg", |
| .id = -1, |
| .num_resources = ARRAY_SIZE(resources_otg), |
| .resource = resources_otg, |
| .dev = { |
| .coherent_dma_mask = 0xffffffffULL, |
| }, |
| }; |
| |
| struct flash_platform_data msm_nand_data = { |
| .parts = NULL, |
| .nr_parts = 0, |
| .interleave = 0, |
| }; |
| |
| struct platform_device msm_device_nand = { |
| .name = "msm_nand", |
| .id = -1, |
| .num_resources = ARRAY_SIZE(resources_nand), |
| .resource = resources_nand, |
| .dev = { |
| .platform_data = &msm_nand_data, |
| }, |
| }; |
| |
| struct platform_device msm_device_smd = { |
| .name = "msm_smd", |
| .id = -1, |
| }; |
| |
| static struct resource msm_dmov_resource[] = { |
| { |
| .start = INT_ADM_AARM, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .start = 0xAC400000, |
| .end = 0xAC400000 + SZ_4K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| }; |
| |
| static struct msm_dmov_pdata msm_dmov_pdata = { |
| .sd = 2, |
| .sd_size = 0x400, |
| }; |
| |
| struct platform_device msm_device_dmov = { |
| .name = "msm_dmov", |
| .id = -1, |
| .resource = msm_dmov_resource, |
| .num_resources = ARRAY_SIZE(msm_dmov_resource), |
| .dev = { |
| .platform_data = &msm_dmov_pdata, |
| }, |
| }; |
| |
| #define MSM_SDC1_BASE 0xA0400000 |
| #define MSM_SDC2_BASE 0xA0500000 |
| #define MSM_SDC3_BASE 0xA3000000 |
| #define MSM_SDC4_BASE 0xA3100000 |
| static struct resource resources_sdc1[] = { |
| { |
| .start = MSM_SDC1_BASE, |
| .end = MSM_SDC1_BASE + SZ_4K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_SDC1_0, |
| .end = INT_SDC1_1, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .name = "sdcc_dma_chnl", |
| .start = DMOV_SDC1_CHAN, |
| .end = DMOV_SDC1_CHAN, |
| .flags = IORESOURCE_DMA, |
| }, |
| { |
| .name = "sdcc_dma_crci", |
| .start = DMOV_SDC1_CRCI, |
| .end = DMOV_SDC1_CRCI, |
| .flags = IORESOURCE_DMA, |
| } |
| }; |
| |
| static struct resource resources_sdc2[] = { |
| { |
| .start = MSM_SDC2_BASE, |
| .end = MSM_SDC2_BASE + SZ_4K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_SDC2_0, |
| .end = INT_SDC2_1, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .name = "sdcc_dma_chnl", |
| .start = DMOV_SDC2_CHAN, |
| .end = DMOV_SDC2_CHAN, |
| .flags = IORESOURCE_DMA, |
| }, |
| { |
| .name = "sdcc_dma_crci", |
| .start = DMOV_SDC2_CRCI, |
| .end = DMOV_SDC2_CRCI, |
| .flags = IORESOURCE_DMA, |
| } |
| }; |
| |
| static struct resource resources_sdc3[] = { |
| { |
| .start = MSM_SDC3_BASE, |
| .end = MSM_SDC3_BASE + SZ_4K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_SDC3_0, |
| .end = INT_SDC3_1, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .name = "sdcc_dma_chnl", |
| .start = DMOV_SDC3_CHAN, |
| .end = DMOV_SDC3_CHAN, |
| .flags = IORESOURCE_DMA, |
| }, |
| { |
| .name = "sdcc_dma_crci", |
| .start = DMOV_SDC3_CRCI, |
| .end = DMOV_SDC3_CRCI, |
| .flags = IORESOURCE_DMA, |
| }, |
| }; |
| |
| static struct resource resources_sdc4[] = { |
| { |
| .start = MSM_SDC4_BASE, |
| .end = MSM_SDC4_BASE + SZ_4K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_SDC4_0, |
| .end = INT_SDC4_1, |
| .flags = IORESOURCE_IRQ, |
| }, |
| { |
| .name = "sdcc_dma_chnl", |
| .start = DMOV_SDC4_CHAN, |
| .end = DMOV_SDC4_CHAN, |
| .flags = IORESOURCE_DMA, |
| }, |
| { |
| .name = "sdcc_dma_crci", |
| .start = DMOV_SDC4_CRCI, |
| .end = DMOV_SDC4_CRCI, |
| .flags = IORESOURCE_DMA, |
| }, |
| }; |
| |
| struct platform_device msm_device_sdc1 = { |
| .name = "msm_sdcc", |
| .id = 1, |
| .num_resources = ARRAY_SIZE(resources_sdc1), |
| .resource = resources_sdc1, |
| .dev = { |
| .coherent_dma_mask = 0xffffffff, |
| }, |
| }; |
| |
| struct platform_device msm_device_sdc2 = { |
| .name = "msm_sdcc", |
| .id = 2, |
| .num_resources = ARRAY_SIZE(resources_sdc2), |
| .resource = resources_sdc2, |
| .dev = { |
| .coherent_dma_mask = 0xffffffff, |
| }, |
| }; |
| |
| struct platform_device msm_device_sdc3 = { |
| .name = "msm_sdcc", |
| .id = 3, |
| .num_resources = ARRAY_SIZE(resources_sdc3), |
| .resource = resources_sdc3, |
| .dev = { |
| .coherent_dma_mask = 0xffffffff, |
| }, |
| }; |
| |
| struct platform_device msm_device_sdc4 = { |
| .name = "msm_sdcc", |
| .id = 4, |
| .num_resources = ARRAY_SIZE(resources_sdc4), |
| .resource = resources_sdc4, |
| .dev = { |
| .coherent_dma_mask = 0xffffffff, |
| }, |
| }; |
| |
| static struct platform_device *msm_sdcc_devices[] __initdata = { |
| &msm_device_sdc1, |
| &msm_device_sdc2, |
| &msm_device_sdc3, |
| &msm_device_sdc4, |
| }; |
| |
| int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat) |
| { |
| struct platform_device *pdev; |
| |
| if (controller < 1 || controller > 4) |
| return -EINVAL; |
| |
| pdev = msm_sdcc_devices[controller-1]; |
| pdev->dev.platform_data = plat; |
| return platform_device_register(pdev); |
| } |
| |
| static struct resource msm_vidc_720p_resources[] = { |
| { |
| .start = 0xA3B00000, |
| .end = 0xA3B00000 + SZ_4K - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_MFC720, |
| .end = INT_MFC720, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| struct msm_vidc_platform_data vidc_platform_data = { |
| .memtype = MEMTYPE_EBI0, |
| .enable_ion = 0 |
| }; |
| |
| struct platform_device msm_device_vidc_720p = { |
| .name = "msm_vidc", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(msm_vidc_720p_resources), |
| .resource = msm_vidc_720p_resources, |
| .dev = { |
| .platform_data = &vidc_platform_data, |
| }, |
| }; |
| |
| #if defined(CONFIG_FB_MSM_MDP40) |
| #define MDP_BASE 0xA3F00000 |
| #define PMDH_BASE 0xAD600000 |
| #define EMDH_BASE 0xAD700000 |
| #define TVENC_BASE 0xAD400000 |
| #else |
| #define MDP_BASE 0xAA200000 |
| #define PMDH_BASE 0xAA600000 |
| #define EMDH_BASE 0xAA700000 |
| #define TVENC_BASE 0xAA400000 |
| #endif |
| |
| static struct resource msm_mdp_resources[] = { |
| { |
| .name = "mdp", |
| .start = MDP_BASE, |
| .end = MDP_BASE + 0x000F0000 - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_MDP, |
| .end = INT_MDP, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| static struct resource msm_mddi_resources[] = { |
| { |
| .name = "pmdh", |
| .start = PMDH_BASE, |
| .end = PMDH_BASE + PAGE_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| } |
| }; |
| |
| static struct resource msm_mddi_ext_resources[] = { |
| { |
| .name = "emdh", |
| .start = EMDH_BASE, |
| .end = EMDH_BASE + PAGE_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| } |
| }; |
| |
| static struct resource msm_ebi2_lcd_resources[] = { |
| { |
| .name = "base", |
| .start = 0xa0d00000, |
| .end = 0xa0d00000 + PAGE_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .name = "lcd01", |
| .start = 0x98000000, |
| .end = 0x98000000 + 0x80000 - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .name = "lcd02", |
| .start = 0x9c000000, |
| .end = 0x9c000000 + 0x80000 - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| }; |
| |
| static struct resource msm_tvenc_resources[] = { |
| { |
| .name = "tvenc", |
| .start = TVENC_BASE, |
| .end = TVENC_BASE + PAGE_SIZE - 1, |
| .flags = IORESOURCE_MEM, |
| } |
| }; |
| |
| #ifdef CONFIG_FB_MSM_TVOUT |
| static struct resource tvout_device_resources[] = { |
| { |
| .name = "tvout_device_irq", |
| .start = INT_TV_ENC, |
| .end = INT_TV_ENC, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| #endif |
| |
| static struct platform_device msm_mdp_device = { |
| .name = "mdp", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(msm_mdp_resources), |
| .resource = msm_mdp_resources, |
| }; |
| |
| static struct platform_device msm_mddi_device = { |
| .name = "mddi", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(msm_mddi_resources), |
| .resource = msm_mddi_resources, |
| }; |
| |
| static struct platform_device msm_mddi_ext_device = { |
| .name = "mddi_ext", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(msm_mddi_ext_resources), |
| .resource = msm_mddi_ext_resources, |
| }; |
| |
| static struct platform_device msm_ebi2_lcd_device = { |
| .name = "ebi2_lcd", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(msm_ebi2_lcd_resources), |
| .resource = msm_ebi2_lcd_resources, |
| }; |
| |
| static struct platform_device msm_lcdc_device = { |
| .name = "lcdc", |
| .id = 0, |
| }; |
| |
| static struct platform_device msm_dtv_device = { |
| .name = "dtv", |
| .id = 0, |
| }; |
| |
| static struct platform_device msm_tvenc_device = { |
| .name = "tvenc", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(msm_tvenc_resources), |
| .resource = msm_tvenc_resources, |
| }; |
| |
| #ifdef CONFIG_FB_MSM_TVOUT |
| static struct platform_device tvout_msm_device = { |
| .name = "tvout_device", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(tvout_device_resources), |
| .resource = tvout_device_resources, |
| }; |
| #endif |
| |
| /* TSIF begin */ |
| #if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) |
| |
| #define MSM_TSIF_PHYS (0xa3400000) |
| #define MSM_TSIF_SIZE (0x200) |
| |
| static struct resource tsif_resources[] = { |
| [0] = { |
| .flags = IORESOURCE_IRQ, |
| .start = INT_TSIF, |
| .end = INT_TSIF, |
| }, |
| [1] = { |
| .flags = IORESOURCE_MEM, |
| .start = MSM_TSIF_PHYS, |
| .end = MSM_TSIF_PHYS + MSM_TSIF_SIZE - 1, |
| }, |
| [2] = { |
| .flags = IORESOURCE_DMA, |
| .start = DMOV_TSIF_CHAN, |
| .end = DMOV_TSIF_CRCI, |
| }, |
| }; |
| |
| static void tsif_release(struct device *dev) |
| { |
| dev_info(dev, "release\n"); |
| } |
| |
| struct platform_device msm_device_tsif = { |
| .name = "msm_tsif", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(tsif_resources), |
| .resource = tsif_resources, |
| .dev = { |
| .release = tsif_release, |
| }, |
| }; |
| #endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */ |
| /* TSIF end */ |
| |
| |
| |
| #ifdef CONFIG_MSM_ROTATOR |
| static struct resource resources_msm_rotator[] = { |
| { |
| .start = 0xA3E00000, |
| .end = 0xA3F00000 - 1, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .start = INT_ROTATOR, |
| .end = INT_ROTATOR, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| static struct msm_rot_clocks rotator_clocks[] = { |
| { |
| .clk_name = "core_clk", |
| .clk_type = ROTATOR_CORE_CLK, |
| .clk_rate = 0, |
| }, |
| { |
| .clk_name = "iface_clk", |
| .clk_type = ROTATOR_PCLK, |
| .clk_rate = 0, |
| }, |
| { |
| .clk_name = "mem_clk", |
| .clk_type = ROTATOR_IMEM_CLK, |
| .clk_rate = 0, |
| }, |
| }; |
| |
| static struct msm_rotator_platform_data rotator_pdata = { |
| .number_of_clocks = ARRAY_SIZE(rotator_clocks), |
| .hardware_version_number = 0x1000303, |
| .rotator_clks = rotator_clocks, |
| .regulator_name = "fs_rot", |
| }; |
| |
| struct platform_device msm_rotator_device = { |
| .name = "msm_rotator", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(resources_msm_rotator), |
| .resource = resources_msm_rotator, |
| .dev = { |
| .platform_data = &rotator_pdata, |
| }, |
| }; |
| #endif |
| |
| static void __init msm_register_device(struct platform_device *pdev, void *data) |
| { |
| int ret; |
| |
| pdev->dev.platform_data = data; |
| |
| ret = platform_device_register(pdev); |
| if (ret) |
| dev_err(&pdev->dev, |
| "%s: platform_device_register() failed = %d\n", |
| __func__, ret); |
| } |
| |
| void __init msm_fb_register_device(char *name, void *data) |
| { |
| if (!strncmp(name, "mdp", 3)) |
| msm_register_device(&msm_mdp_device, data); |
| else if (!strncmp(name, "pmdh", 4)) |
| msm_register_device(&msm_mddi_device, data); |
| else if (!strncmp(name, "emdh", 4)) |
| msm_register_device(&msm_mddi_ext_device, data); |
| else if (!strncmp(name, "ebi2", 4)) |
| msm_register_device(&msm_ebi2_lcd_device, data); |
| else if (!strncmp(name, "tvenc", 5)) |
| msm_register_device(&msm_tvenc_device, data); |
| else if (!strncmp(name, "lcdc", 4)) |
| msm_register_device(&msm_lcdc_device, data); |
| else if (!strncmp(name, "dtv", 3)) |
| msm_register_device(&msm_dtv_device, data); |
| #ifdef CONFIG_FB_MSM_TVOUT |
| else if (!strncmp(name, "tvout_device", 12)) |
| msm_register_device(&tvout_msm_device, data); |
| #endif |
| else |
| printk(KERN_ERR "%s: unknown device! %s\n", __func__, name); |
| } |
| |
| static struct platform_device msm_camera_device = { |
| .name = "msm_camera", |
| .id = 0, |
| }; |
| |
| void __init msm_camera_register_device(void *res, uint32_t num, |
| void *data) |
| { |
| msm_camera_device.num_resources = num; |
| msm_camera_device.resource = res; |
| |
| msm_register_device(&msm_camera_device, data); |
| } |
| |
| struct resource kgsl_3d0_resources[] = { |
| { |
| .name = KGSL_3D0_REG_MEMORY, |
| .start = 0xA3500000, /* 3D GRP address */ |
| .end = 0xA351ffff, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .name = KGSL_3D0_IRQ, |
| .start = INT_GRP_3D, |
| .end = INT_GRP_3D, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| static struct kgsl_device_platform_data kgsl_3d0_pdata = { |
| .pwr_data = { |
| .pwrlevel = { |
| { |
| .gpu_freq = 245760000, |
| .bus_freq = 192000000, |
| }, |
| { |
| .gpu_freq = 192000000, |
| .bus_freq = 152000000, |
| }, |
| { |
| .gpu_freq = 192000000, |
| .bus_freq = 0, |
| }, |
| }, |
| .init_level = 0, |
| .num_levels = 3, |
| .set_grp_async = set_grp3d_async, |
| .idle_timeout = HZ/20, |
| .nap_allowed = true, |
| }, |
| .clk = { |
| .name = { |
| .clk = "core_clk", |
| .pclk = "iface_clk", |
| }, |
| }, |
| .imem_clk_name = { |
| .clk = "mem_clk", |
| .pclk = NULL, |
| }, |
| }; |
| |
| struct platform_device msm_kgsl_3d0 = { |
| .name = "kgsl-3d0", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(kgsl_3d0_resources), |
| .resource = kgsl_3d0_resources, |
| .dev = { |
| .platform_data = &kgsl_3d0_pdata, |
| }, |
| }; |
| |
| static struct resource kgsl_2d0_resources[] = { |
| { |
| .name = KGSL_2D0_REG_MEMORY, |
| .start = 0xA3900000, /* Z180 base address */ |
| .end = 0xA3900FFF, |
| .flags = IORESOURCE_MEM, |
| }, |
| { |
| .name = KGSL_2D0_IRQ, |
| .start = INT_GRP_2D, |
| .end = INT_GRP_2D, |
| .flags = IORESOURCE_IRQ, |
| }, |
| }; |
| |
| static struct kgsl_device_platform_data kgsl_2d0_pdata = { |
| .pwr_data = { |
| .pwrlevel = { |
| { |
| .gpu_freq = 0, |
| .bus_freq = 192000000, |
| }, |
| }, |
| .init_level = 0, |
| .num_levels = 1, |
| /* HW workaround, run Z180 SYNC @ 192 MHZ */ |
| .set_grp_async = NULL, |
| .idle_timeout = HZ/10, |
| .nap_allowed = true, |
| }, |
| .clk = { |
| .name = { |
| .clk = "core_clk", |
| .pclk = "iface_clk", |
| }, |
| }, |
| }; |
| |
| struct platform_device msm_kgsl_2d0 = { |
| .name = "kgsl-2d0", |
| .id = 0, |
| .num_resources = ARRAY_SIZE(kgsl_2d0_resources), |
| .resource = kgsl_2d0_resources, |
| .dev = { |
| .platform_data = &kgsl_2d0_pdata, |
| }, |
| }; |
| |
| struct platform_device *msm_footswitch_devices[] = { |
| FS_PCOM(FS_GFX2D0, "fs_gfx2d0"), |
| FS_PCOM(FS_GFX3D, "fs_gfx3d"), |
| FS_PCOM(FS_MDP, "fs_mdp"), |
| FS_PCOM(FS_MFC, "fs_mfc"), |
| FS_PCOM(FS_ROT, "fs_rot"), |
| FS_PCOM(FS_VFE, "fs_vfe"), |
| FS_PCOM(FS_VPE, "fs_vpe"), |
| }; |
| unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices); |