H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_MCE_H |
| 2 | #define _ASM_X86_MCE_H |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 3 | |
Jaswinder Singh Rajput | 999b697 | 2009-01-30 22:47:27 +0530 | [diff] [blame] | 4 | #include <linux/types.h> |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 5 | #include <asm/ioctls.h> |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 6 | |
| 7 | /* |
| 8 | * Machine Check support for x86 |
| 9 | */ |
| 10 | |
Thomas Gleixner | 01c6680 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 11 | #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ |
| 12 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
| 13 | #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ |
| 14 | #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ |
| 15 | #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ |
| 16 | #define MCG_EXT_CNT_SHIFT 16 |
| 17 | #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 18 | |
Ingo Molnar | 06b851d | 2009-04-08 12:31:25 +0200 | [diff] [blame] | 19 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
| 20 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ |
| 21 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 22 | |
Ingo Molnar | 06b851d | 2009-04-08 12:31:25 +0200 | [diff] [blame] | 23 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
| 24 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ |
| 25 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ |
| 26 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
| 27 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ |
| 28 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ |
| 29 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 30 | |
| 31 | /* Fields are zero when not available */ |
| 32 | struct mce { |
| 33 | __u64 status; |
| 34 | __u64 misc; |
| 35 | __u64 addr; |
| 36 | __u64 mcgstatus; |
H. Peter Anvin | 65ea5b0 | 2008-01-30 13:30:56 +0100 | [diff] [blame] | 37 | __u64 ip; |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 38 | __u64 tsc; /* cpu time stamp counter */ |
| 39 | __u64 res1; /* for future extension */ |
| 40 | __u64 res2; /* dito. */ |
| 41 | __u8 cs; /* code segment */ |
| 42 | __u8 bank; /* machine check bank */ |
| 43 | __u8 cpu; /* cpu that raised the error */ |
| 44 | __u8 finished; /* entry is valid */ |
| 45 | __u32 pad; |
| 46 | }; |
| 47 | |
| 48 | /* |
| 49 | * This structure contains all data related to the MCE log. Also |
| 50 | * carries a signature to make it easier to find from external |
| 51 | * debugging tools. Each entry is only valid when its finished flag |
| 52 | * is set. |
| 53 | */ |
| 54 | |
| 55 | #define MCE_LOG_LEN 32 |
| 56 | |
| 57 | struct mce_log { |
| 58 | char signature[12]; /* "MACHINECHECK" */ |
| 59 | unsigned len; /* = MCE_LOG_LEN */ |
| 60 | unsigned next; |
| 61 | unsigned flags; |
| 62 | unsigned pad0; |
| 63 | struct mce entry[MCE_LOG_LEN]; |
| 64 | }; |
| 65 | |
| 66 | #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ |
| 67 | |
| 68 | #define MCE_LOG_SIGNATURE "MACHINECHECK" |
| 69 | |
| 70 | #define MCE_GET_RECORD_LEN _IOR('M', 1, int) |
| 71 | #define MCE_GET_LOG_LEN _IOR('M', 2, int) |
| 72 | #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) |
| 73 | |
| 74 | /* Software defined banks */ |
| 75 | #define MCE_EXTENDED_BANK 128 |
| 76 | #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 |
| 77 | |
| 78 | #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */ |
| 79 | #define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9) |
| 80 | #define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9) |
| 81 | #define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9) |
| 82 | #define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9) |
| 83 | #define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9) |
| 84 | #define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9) |
| 85 | #define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0) |
| 86 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 87 | #ifdef __KERNEL__ |
| 88 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 89 | extern int mce_disabled; |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 90 | |
| 91 | #include <asm/atomic.h> |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame^] | 92 | #include <linux/percpu.h> |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 93 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 94 | void mce_setup(struct mce *m); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 95 | void mce_log(struct mce *m); |
Ingo Molnar | cb491fc | 2009-04-08 12:31:17 +0200 | [diff] [blame] | 96 | DECLARE_PER_CPU(struct sys_device, mce_dev); |
Rafael J. Wysocki | 8735728 | 2008-08-22 22:23:09 +0200 | [diff] [blame] | 97 | extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 98 | |
Andi Kleen | 41fdff3 | 2009-02-12 13:49:30 +0100 | [diff] [blame] | 99 | /* |
| 100 | * To support more than 128 would need to escape the predefined |
| 101 | * Linux defined extended banks first. |
| 102 | */ |
| 103 | #define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1) |
| 104 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 105 | #ifdef CONFIG_X86_MCE_INTEL |
| 106 | void mce_intel_feature_init(struct cpuinfo_x86 *c); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 107 | void cmci_clear(void); |
| 108 | void cmci_reenable(void); |
| 109 | void cmci_rediscover(int dying); |
| 110 | void cmci_recheck(void); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 111 | #else |
| 112 | static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 113 | static inline void cmci_clear(void) {} |
| 114 | static inline void cmci_reenable(void) {} |
| 115 | static inline void cmci_rediscover(int dying) {} |
| 116 | static inline void cmci_recheck(void) {} |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 117 | #endif |
| 118 | |
| 119 | #ifdef CONFIG_X86_MCE_AMD |
| 120 | void mce_amd_feature_init(struct cpuinfo_x86 *c); |
| 121 | #else |
| 122 | static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } |
| 123 | #endif |
| 124 | |
H. Peter Anvin | 3873607 | 2009-05-28 10:05:33 -0700 | [diff] [blame] | 125 | int mce_available(struct cpuinfo_x86 *c); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 126 | |
Andi Kleen | 01ca79f | 2009-05-27 21:56:52 +0200 | [diff] [blame^] | 127 | DECLARE_PER_CPU(unsigned, mce_exception_count); |
| 128 | |
Andi Kleen | b5f2fa4 | 2009-02-12 13:43:22 +0100 | [diff] [blame] | 129 | void mce_log_therm_throt_event(__u64 status); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 130 | |
| 131 | extern atomic_t mce_entry; |
| 132 | |
H. Peter Anvin | 3873607 | 2009-05-28 10:05:33 -0700 | [diff] [blame] | 133 | void do_machine_check(struct pt_regs *, long); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 134 | |
Andi Kleen | ee031c3 | 2009-02-12 13:49:34 +0100 | [diff] [blame] | 135 | typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); |
| 136 | DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); |
| 137 | |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 138 | enum mcp_flags { |
| 139 | MCP_TIMESTAMP = (1 << 0), /* log time stamp */ |
| 140 | MCP_UC = (1 << 1), /* log uncorrected errors */ |
Andi Kleen | 5679af4 | 2009-04-07 17:06:55 +0200 | [diff] [blame] | 141 | MCP_DONTLOG = (1 << 2), /* only clear, don't log */ |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 142 | }; |
H. Peter Anvin | 3873607 | 2009-05-28 10:05:33 -0700 | [diff] [blame] | 143 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); |
Andi Kleen | b79109c | 2009-02-12 13:43:23 +0100 | [diff] [blame] | 144 | |
H. Peter Anvin | 3873607 | 2009-05-28 10:05:33 -0700 | [diff] [blame] | 145 | int mce_notify_user(void); |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 146 | |
Andi Kleen | ea149b3 | 2009-04-29 19:31:00 +0200 | [diff] [blame] | 147 | DECLARE_PER_CPU(struct mce, injectm); |
| 148 | extern struct file_operations mce_chrdev_ops; |
| 149 | |
Thomas Gleixner | af7a78e | 2008-01-30 13:30:17 +0100 | [diff] [blame] | 150 | #ifdef CONFIG_X86_MCE |
H. Peter Anvin | 3873607 | 2009-05-28 10:05:33 -0700 | [diff] [blame] | 151 | void mcheck_init(struct cpuinfo_x86 *c); |
Thomas Gleixner | af7a78e | 2008-01-30 13:30:17 +0100 | [diff] [blame] | 152 | #else |
| 153 | #define mcheck_init(c) do { } while (0) |
| 154 | #endif |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 155 | |
Andi Kleen | b276268 | 2009-02-12 13:49:31 +0100 | [diff] [blame] | 156 | extern void (*mce_threshold_vector)(void); |
| 157 | |
Thomas Gleixner | e2f4302 | 2007-10-17 18:04:40 +0200 | [diff] [blame] | 158 | #endif /* __KERNEL__ */ |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 159 | #endif /* _ASM_X86_MCE_H */ |