Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1 | /* |
Gertjan van Wingerde | 9c9a0d1 | 2009-11-08 16:39:55 +0100 | [diff] [blame] | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 3 | <http://rt2x00.serialmonkey.com> |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 2 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the |
| 17 | Free Software Foundation, Inc., |
| 18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | Module: rt2400pci |
| 23 | Abstract: rt2400pci device specific routines. |
| 24 | Supported chipsets: RT2460. |
| 25 | */ |
| 26 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 27 | #include <linux/delay.h> |
| 28 | #include <linux/etherdevice.h> |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/kernel.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/pci.h> |
| 33 | #include <linux/eeprom_93cx6.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 35 | |
| 36 | #include "rt2x00.h" |
| 37 | #include "rt2x00pci.h" |
| 38 | #include "rt2400pci.h" |
| 39 | |
| 40 | /* |
| 41 | * Register access. |
| 42 | * All access to the CSR registers will go through the methods |
| 43 | * rt2x00pci_register_read and rt2x00pci_register_write. |
| 44 | * BBP and RF register require indirect register access, |
| 45 | * and use the CSR registers BBPCSR and RFCSR to achieve this. |
| 46 | * These indirect registers work with busy bits, |
| 47 | * and we will try maximal REGISTER_BUSY_COUNT times to access |
| 48 | * the register while taking a REGISTER_BUSY_DELAY us delay |
| 49 | * between each attampt. When the busy bit is still set at that time, |
| 50 | * the access attempt is considered to have failed, |
| 51 | * and we will print an error. |
| 52 | */ |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 53 | #define WAIT_FOR_BBP(__dev, __reg) \ |
| 54 | rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg)) |
| 55 | #define WAIT_FOR_RF(__dev, __reg) \ |
| 56 | rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg)) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 57 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 58 | static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 59 | const unsigned int word, const u8 value) |
| 60 | { |
| 61 | u32 reg; |
| 62 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 63 | mutex_lock(&rt2x00dev->csr_mutex); |
| 64 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 65 | /* |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 66 | * Wait until the BBP becomes available, afterwards we |
| 67 | * can safely write the new data into the register. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 68 | */ |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 69 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 70 | reg = 0; |
| 71 | rt2x00_set_field32(®, BBPCSR_VALUE, value); |
| 72 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); |
| 73 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); |
| 74 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 75 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 76 | rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); |
| 77 | } |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 78 | |
| 79 | mutex_unlock(&rt2x00dev->csr_mutex); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 80 | } |
| 81 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 82 | static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 83 | const unsigned int word, u8 *value) |
| 84 | { |
| 85 | u32 reg; |
| 86 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 87 | mutex_lock(&rt2x00dev->csr_mutex); |
| 88 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 89 | /* |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 90 | * Wait until the BBP becomes available, afterwards we |
| 91 | * can safely write the read request into the register. |
| 92 | * After the data has been written, we wait until hardware |
| 93 | * returns the correct value, if at any time the register |
| 94 | * doesn't become available in time, reg will be 0xffffffff |
| 95 | * which means we return 0xff to the caller. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 96 | */ |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 97 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 98 | reg = 0; |
| 99 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); |
| 100 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); |
| 101 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 102 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 103 | rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 104 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 105 | WAIT_FOR_BBP(rt2x00dev, ®); |
| 106 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 107 | |
| 108 | *value = rt2x00_get_field32(reg, BBPCSR_VALUE); |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 109 | |
| 110 | mutex_unlock(&rt2x00dev->csr_mutex); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 111 | } |
| 112 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 113 | static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 114 | const unsigned int word, const u32 value) |
| 115 | { |
| 116 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 117 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 118 | mutex_lock(&rt2x00dev->csr_mutex); |
| 119 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 120 | /* |
| 121 | * Wait until the RF becomes available, afterwards we |
| 122 | * can safely write the new data into the register. |
| 123 | */ |
| 124 | if (WAIT_FOR_RF(rt2x00dev, ®)) { |
| 125 | reg = 0; |
| 126 | rt2x00_set_field32(®, RFCSR_VALUE, value); |
| 127 | rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); |
| 128 | rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); |
| 129 | rt2x00_set_field32(®, RFCSR_BUSY, 1); |
| 130 | |
| 131 | rt2x00pci_register_write(rt2x00dev, RFCSR, reg); |
| 132 | rt2x00_rf_write(rt2x00dev, word, value); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 133 | } |
| 134 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 135 | mutex_unlock(&rt2x00dev->csr_mutex); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom) |
| 139 | { |
| 140 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 141 | u32 reg; |
| 142 | |
| 143 | rt2x00pci_register_read(rt2x00dev, CSR21, ®); |
| 144 | |
| 145 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); |
| 146 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); |
| 147 | eeprom->reg_data_clock = |
| 148 | !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); |
| 149 | eeprom->reg_chip_select = |
| 150 | !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); |
| 151 | } |
| 152 | |
| 153 | static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom) |
| 154 | { |
| 155 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 156 | u32 reg = 0; |
| 157 | |
| 158 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); |
| 159 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); |
| 160 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, |
| 161 | !!eeprom->reg_data_clock); |
| 162 | rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, |
| 163 | !!eeprom->reg_chip_select); |
| 164 | |
| 165 | rt2x00pci_register_write(rt2x00dev, CSR21, reg); |
| 166 | } |
| 167 | |
| 168 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 169 | static const struct rt2x00debug rt2400pci_rt2x00debug = { |
| 170 | .owner = THIS_MODULE, |
| 171 | .csr = { |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 172 | .read = rt2x00pci_register_read, |
| 173 | .write = rt2x00pci_register_write, |
| 174 | .flags = RT2X00DEBUGFS_OFFSET, |
| 175 | .word_base = CSR_REG_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 176 | .word_size = sizeof(u32), |
| 177 | .word_count = CSR_REG_SIZE / sizeof(u32), |
| 178 | }, |
| 179 | .eeprom = { |
| 180 | .read = rt2x00_eeprom_read, |
| 181 | .write = rt2x00_eeprom_write, |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 182 | .word_base = EEPROM_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 183 | .word_size = sizeof(u16), |
| 184 | .word_count = EEPROM_SIZE / sizeof(u16), |
| 185 | }, |
| 186 | .bbp = { |
| 187 | .read = rt2400pci_bbp_read, |
| 188 | .write = rt2400pci_bbp_write, |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 189 | .word_base = BBP_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 190 | .word_size = sizeof(u8), |
| 191 | .word_count = BBP_SIZE / sizeof(u8), |
| 192 | }, |
| 193 | .rf = { |
| 194 | .read = rt2x00_rf_read, |
| 195 | .write = rt2400pci_rf_write, |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 196 | .word_base = RF_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 197 | .word_size = sizeof(u32), |
| 198 | .word_count = RF_SIZE / sizeof(u32), |
| 199 | }, |
| 200 | }; |
| 201 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 202 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 203 | static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
| 204 | { |
| 205 | u32 reg; |
| 206 | |
| 207 | rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®); |
| 208 | return rt2x00_get_field32(reg, GPIOCSR_BIT0); |
| 209 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 210 | |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 211 | #ifdef CONFIG_RT2X00_LIB_LEDS |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 212 | static void rt2400pci_brightness_set(struct led_classdev *led_cdev, |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 213 | enum led_brightness brightness) |
| 214 | { |
| 215 | struct rt2x00_led *led = |
| 216 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 217 | unsigned int enabled = brightness != LED_OFF; |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 218 | u32 reg; |
| 219 | |
| 220 | rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®); |
| 221 | |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 222 | if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 223 | rt2x00_set_field32(®, LEDCSR_LINK, enabled); |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 224 | else if (led->type == LED_TYPE_ACTIVITY) |
| 225 | rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 226 | |
| 227 | rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); |
| 228 | } |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 229 | |
| 230 | static int rt2400pci_blink_set(struct led_classdev *led_cdev, |
| 231 | unsigned long *delay_on, |
| 232 | unsigned long *delay_off) |
| 233 | { |
| 234 | struct rt2x00_led *led = |
| 235 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 236 | u32 reg; |
| 237 | |
| 238 | rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®); |
| 239 | rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); |
| 240 | rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); |
| 241 | rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); |
| 242 | |
| 243 | return 0; |
| 244 | } |
Ivo van Doorn | 475433b | 2008-06-03 20:30:01 +0200 | [diff] [blame] | 245 | |
| 246 | static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev, |
| 247 | struct rt2x00_led *led, |
| 248 | enum led_type type) |
| 249 | { |
| 250 | led->rt2x00dev = rt2x00dev; |
| 251 | led->type = type; |
| 252 | led->led_dev.brightness_set = rt2400pci_brightness_set; |
| 253 | led->led_dev.blink_set = rt2400pci_blink_set; |
| 254 | led->flags = LED_INITIALIZED; |
| 255 | } |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 256 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 257 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 258 | /* |
| 259 | * Configuration handlers. |
| 260 | */ |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 261 | static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev, |
| 262 | const unsigned int filter_flags) |
| 263 | { |
| 264 | u32 reg; |
| 265 | |
| 266 | /* |
| 267 | * Start configuration steps. |
| 268 | * Note that the version error will always be dropped |
| 269 | * since there is no filter for it at this time. |
| 270 | */ |
| 271 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); |
| 272 | rt2x00_set_field32(®, RXCSR0_DROP_CRC, |
| 273 | !(filter_flags & FIF_FCSFAIL)); |
| 274 | rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, |
| 275 | !(filter_flags & FIF_PLCPFAIL)); |
| 276 | rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, |
| 277 | !(filter_flags & FIF_CONTROL)); |
| 278 | rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, |
| 279 | !(filter_flags & FIF_PROMISC_IN_BSS)); |
| 280 | rt2x00_set_field32(®, RXCSR0_DROP_TODS, |
Ivo van Doorn | e0b005f | 2008-03-31 15:24:53 +0200 | [diff] [blame] | 281 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
| 282 | !rt2x00dev->intf_ap_count); |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 283 | rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); |
| 284 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); |
| 285 | } |
| 286 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 287 | static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev, |
| 288 | struct rt2x00_intf *intf, |
| 289 | struct rt2x00intf_conf *conf, |
| 290 | const unsigned int flags) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 291 | { |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 292 | unsigned int bcn_preload; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 293 | u32 reg; |
| 294 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 295 | if (flags & CONFIG_UPDATE_TYPE) { |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 296 | /* |
| 297 | * Enable beacon config |
| 298 | */ |
Ivo van Doorn | bad1363 | 2008-11-09 20:47:00 +0100 | [diff] [blame] | 299 | bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 300 | rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®); |
| 301 | rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); |
| 302 | rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 303 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 304 | /* |
| 305 | * Enable synchronisation. |
| 306 | */ |
| 307 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
Ivo van Doorn | fd3c91c | 2008-03-09 22:47:43 +0100 | [diff] [blame] | 308 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 309 | rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); |
Ivo van Doorn | fd3c91c | 2008-03-09 22:47:43 +0100 | [diff] [blame] | 310 | rt2x00_set_field32(®, CSR14_TBCN, 1); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 311 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
| 312 | } |
| 313 | |
| 314 | if (flags & CONFIG_UPDATE_MAC) |
| 315 | rt2x00pci_register_multiwrite(rt2x00dev, CSR3, |
| 316 | conf->mac, sizeof(conf->mac)); |
| 317 | |
| 318 | if (flags & CONFIG_UPDATE_BSSID) |
| 319 | rt2x00pci_register_multiwrite(rt2x00dev, CSR5, |
| 320 | conf->bssid, sizeof(conf->bssid)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 321 | } |
| 322 | |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 323 | static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev, |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 324 | struct rt2x00lib_erp *erp, |
| 325 | u32 changed) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 326 | { |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 327 | int preamble_mask; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 328 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 329 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 330 | /* |
| 331 | * When short preamble is enabled, we should set bit 0x08 |
| 332 | */ |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 333 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
| 334 | preamble_mask = erp->short_preamble << 3; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 335 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 336 | rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); |
| 337 | rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff); |
| 338 | rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a); |
| 339 | rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); |
| 340 | rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); |
| 341 | rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 342 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 343 | rt2x00pci_register_read(rt2x00dev, ARCSR2, ®); |
| 344 | rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); |
| 345 | rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); |
| 346 | rt2x00_set_field32(®, ARCSR2_LENGTH, |
| 347 | GET_DURATION(ACK_SIZE, 10)); |
| 348 | rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 349 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 350 | rt2x00pci_register_read(rt2x00dev, ARCSR3, ®); |
| 351 | rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); |
| 352 | rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); |
| 353 | rt2x00_set_field32(®, ARCSR2_LENGTH, |
| 354 | GET_DURATION(ACK_SIZE, 20)); |
| 355 | rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 356 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 357 | rt2x00pci_register_read(rt2x00dev, ARCSR4, ®); |
| 358 | rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); |
| 359 | rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); |
| 360 | rt2x00_set_field32(®, ARCSR2_LENGTH, |
| 361 | GET_DURATION(ACK_SIZE, 55)); |
| 362 | rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 363 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 364 | rt2x00pci_register_read(rt2x00dev, ARCSR5, ®); |
| 365 | rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); |
| 366 | rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); |
| 367 | rt2x00_set_field32(®, ARCSR2_LENGTH, |
| 368 | GET_DURATION(ACK_SIZE, 110)); |
| 369 | rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); |
| 370 | } |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 371 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 372 | if (changed & BSS_CHANGED_BASIC_RATES) |
| 373 | rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 374 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 375 | if (changed & BSS_CHANGED_ERP_SLOT) { |
| 376 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); |
| 377 | rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); |
| 378 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 379 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 380 | rt2x00pci_register_read(rt2x00dev, CSR18, ®); |
| 381 | rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); |
| 382 | rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); |
| 383 | rt2x00pci_register_write(rt2x00dev, CSR18, reg); |
Ivo van Doorn | 8a566af | 2009-05-21 19:16:46 +0200 | [diff] [blame] | 384 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 385 | rt2x00pci_register_read(rt2x00dev, CSR19, ®); |
| 386 | rt2x00_set_field32(®, CSR19_DIFS, erp->difs); |
| 387 | rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); |
| 388 | rt2x00pci_register_write(rt2x00dev, CSR19, reg); |
| 389 | } |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 390 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 391 | if (changed & BSS_CHANGED_BEACON_INT) { |
| 392 | rt2x00pci_register_read(rt2x00dev, CSR12, ®); |
| 393 | rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, |
| 394 | erp->beacon_int * 16); |
| 395 | rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, |
| 396 | erp->beacon_int * 16); |
| 397 | rt2x00pci_register_write(rt2x00dev, CSR12, reg); |
| 398 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 399 | } |
| 400 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 401 | static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev, |
| 402 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 403 | { |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 404 | u8 r1; |
| 405 | u8 r4; |
| 406 | |
| 407 | /* |
| 408 | * We should never come here because rt2x00lib is supposed |
| 409 | * to catch this and send us the correct antenna explicitely. |
| 410 | */ |
| 411 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || |
| 412 | ant->tx == ANTENNA_SW_DIVERSITY); |
| 413 | |
| 414 | rt2400pci_bbp_read(rt2x00dev, 4, &r4); |
| 415 | rt2400pci_bbp_read(rt2x00dev, 1, &r1); |
| 416 | |
| 417 | /* |
| 418 | * Configure the TX antenna. |
| 419 | */ |
| 420 | switch (ant->tx) { |
| 421 | case ANTENNA_HW_DIVERSITY: |
| 422 | rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1); |
| 423 | break; |
| 424 | case ANTENNA_A: |
| 425 | rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0); |
| 426 | break; |
| 427 | case ANTENNA_B: |
| 428 | default: |
| 429 | rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2); |
| 430 | break; |
| 431 | } |
| 432 | |
| 433 | /* |
| 434 | * Configure the RX antenna. |
| 435 | */ |
| 436 | switch (ant->rx) { |
| 437 | case ANTENNA_HW_DIVERSITY: |
| 438 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1); |
| 439 | break; |
| 440 | case ANTENNA_A: |
| 441 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0); |
| 442 | break; |
| 443 | case ANTENNA_B: |
| 444 | default: |
| 445 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2); |
| 446 | break; |
| 447 | } |
| 448 | |
| 449 | rt2400pci_bbp_write(rt2x00dev, 4, r4); |
| 450 | rt2400pci_bbp_write(rt2x00dev, 1, r1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 451 | } |
| 452 | |
| 453 | static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 454 | struct rf_channel *rf) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 455 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 456 | /* |
| 457 | * Switch on tuning bits. |
| 458 | */ |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 459 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); |
| 460 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 461 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 462 | rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 463 | rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); |
| 464 | rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 465 | |
| 466 | /* |
| 467 | * RF2420 chipset don't need any additional actions. |
| 468 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 469 | if (rt2x00_rf(rt2x00dev, RF2420)) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 470 | return; |
| 471 | |
| 472 | /* |
| 473 | * For the RT2421 chipsets we need to write an invalid |
| 474 | * reference clock rate to activate auto_tune. |
| 475 | * After that we set the value back to the correct channel. |
| 476 | */ |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 477 | rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 478 | rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32); |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 479 | rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 480 | |
| 481 | msleep(1); |
| 482 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 483 | rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 484 | rt2400pci_rf_write(rt2x00dev, 2, rf->rf2); |
| 485 | rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 486 | |
| 487 | msleep(1); |
| 488 | |
| 489 | /* |
| 490 | * Switch off tuning bits. |
| 491 | */ |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 492 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); |
| 493 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 494 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 495 | rt2400pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 496 | rt2400pci_rf_write(rt2x00dev, 3, rf->rf3); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 497 | |
| 498 | /* |
| 499 | * Clear false CRC during channel switch. |
| 500 | */ |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 501 | rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 502 | } |
| 503 | |
| 504 | static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower) |
| 505 | { |
| 506 | rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower)); |
| 507 | } |
| 508 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 509 | static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
| 510 | struct rt2x00lib_conf *libconf) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 511 | { |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 512 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 513 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 514 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); |
| 515 | rt2x00_set_field32(®, CSR11_LONG_RETRY, |
| 516 | libconf->conf->long_frame_max_tx_count); |
| 517 | rt2x00_set_field32(®, CSR11_SHORT_RETRY, |
| 518 | libconf->conf->short_frame_max_tx_count); |
| 519 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 520 | } |
| 521 | |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 522 | static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev, |
| 523 | struct rt2x00lib_conf *libconf) |
| 524 | { |
| 525 | enum dev_state state = |
| 526 | (libconf->conf->flags & IEEE80211_CONF_PS) ? |
| 527 | STATE_SLEEP : STATE_AWAKE; |
| 528 | u32 reg; |
| 529 | |
| 530 | if (state == STATE_SLEEP) { |
| 531 | rt2x00pci_register_read(rt2x00dev, CSR20, ®); |
| 532 | rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, |
Ivo van Doorn | 6b347bf | 2009-05-23 21:09:28 +0200 | [diff] [blame] | 533 | (rt2x00dev->beacon_int - 20) * 16); |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 534 | rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, |
| 535 | libconf->conf->listen_interval - 1); |
| 536 | |
| 537 | /* We must first disable autowake before it can be enabled */ |
| 538 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); |
| 539 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); |
| 540 | |
| 541 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); |
| 542 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); |
Gertjan van Wingerde | 5731858 | 2010-03-30 23:50:23 +0200 | [diff] [blame] | 543 | } else { |
| 544 | rt2x00pci_register_read(rt2x00dev, CSR20, ®); |
| 545 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); |
| 546 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 547 | } |
| 548 | |
| 549 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); |
| 550 | } |
| 551 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 552 | static void rt2400pci_config(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 553 | struct rt2x00lib_conf *libconf, |
| 554 | const unsigned int flags) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 555 | { |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 556 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 557 | rt2400pci_config_channel(rt2x00dev, &libconf->rf); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 558 | if (flags & IEEE80211_CONF_CHANGE_POWER) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 559 | rt2400pci_config_txpower(rt2x00dev, |
| 560 | libconf->conf->power_level); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 561 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
| 562 | rt2400pci_config_retry_limit(rt2x00dev, libconf); |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 563 | if (flags & IEEE80211_CONF_CHANGE_PS) |
| 564 | rt2400pci_config_ps(rt2x00dev, libconf); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 565 | } |
| 566 | |
| 567 | static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 568 | const int cw_min, const int cw_max) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 569 | { |
| 570 | u32 reg; |
| 571 | |
| 572 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 573 | rt2x00_set_field32(®, CSR11_CWMIN, cw_min); |
| 574 | rt2x00_set_field32(®, CSR11_CWMAX, cw_max); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 575 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); |
| 576 | } |
| 577 | |
| 578 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 579 | * Link tuning |
| 580 | */ |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 581 | static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev, |
| 582 | struct link_qual *qual) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 583 | { |
| 584 | u32 reg; |
| 585 | u8 bbp; |
| 586 | |
| 587 | /* |
| 588 | * Update FCS error count from register. |
| 589 | */ |
| 590 | rt2x00pci_register_read(rt2x00dev, CNT0, ®); |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 591 | qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 592 | |
| 593 | /* |
| 594 | * Update False CCA count from register. |
| 595 | */ |
| 596 | rt2400pci_bbp_read(rt2x00dev, 39, &bbp); |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 597 | qual->false_cca = bbp; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 598 | } |
| 599 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 600 | static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev, |
| 601 | struct link_qual *qual, u8 vgc_level) |
Ivo van Doorn | eb20b4e | 2008-12-20 10:54:22 +0100 | [diff] [blame] | 602 | { |
Ivo van Doorn | 223dcc2 | 2010-07-11 12:25:17 +0200 | [diff] [blame] | 603 | if (qual->vgc_level_reg != vgc_level) { |
| 604 | rt2400pci_bbp_write(rt2x00dev, 13, vgc_level); |
| 605 | qual->vgc_level = vgc_level; |
| 606 | qual->vgc_level_reg = vgc_level; |
| 607 | } |
Ivo van Doorn | eb20b4e | 2008-12-20 10:54:22 +0100 | [diff] [blame] | 608 | } |
| 609 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 610 | static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev, |
| 611 | struct link_qual *qual) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 612 | { |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 613 | rt2400pci_set_vgc(rt2x00dev, qual, 0x08); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 614 | } |
| 615 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 616 | static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev, |
| 617 | struct link_qual *qual, const u32 count) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 618 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 619 | /* |
| 620 | * The link tuner should not run longer then 60 seconds, |
| 621 | * and should run once every 2 seconds. |
| 622 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 623 | if (count > 60 || !(count & 1)) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 624 | return; |
| 625 | |
| 626 | /* |
| 627 | * Base r13 link tuning on the false cca count. |
| 628 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 629 | if ((qual->false_cca > 512) && (qual->vgc_level < 0x20)) |
| 630 | rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); |
| 631 | else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08)) |
| 632 | rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 633 | } |
| 634 | |
| 635 | /* |
| 636 | * Initialization functions. |
| 637 | */ |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 638 | static bool rt2400pci_get_entry_state(struct queue_entry *entry) |
| 639 | { |
| 640 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
| 641 | u32 word; |
| 642 | |
| 643 | if (entry->queue->qid == QID_RX) { |
| 644 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 645 | |
| 646 | return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); |
| 647 | } else { |
| 648 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 649 | |
| 650 | return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
| 651 | rt2x00_get_field32(word, TXD_W0_VALID)); |
| 652 | } |
| 653 | } |
| 654 | |
| 655 | static void rt2400pci_clear_entry(struct queue_entry *entry) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 656 | { |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 657 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 658 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 659 | u32 word; |
| 660 | |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 661 | if (entry->queue->qid == QID_RX) { |
| 662 | rt2x00_desc_read(entry_priv->desc, 2, &word); |
| 663 | rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len); |
| 664 | rt2x00_desc_write(entry_priv->desc, 2, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 665 | |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 666 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 667 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); |
| 668 | rt2x00_desc_write(entry_priv->desc, 1, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 669 | |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 670 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 671 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); |
| 672 | rt2x00_desc_write(entry_priv->desc, 0, word); |
| 673 | } else { |
| 674 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 675 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); |
| 676 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); |
| 677 | rt2x00_desc_write(entry_priv->desc, 0, word); |
| 678 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 679 | } |
| 680 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 681 | static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 682 | { |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 683 | struct queue_entry_priv_pci *entry_priv; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 684 | u32 reg; |
| 685 | |
| 686 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 687 | * Initialize registers. |
| 688 | */ |
| 689 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 690 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); |
| 691 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); |
| 692 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); |
| 693 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 694 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); |
| 695 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 696 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 697 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 698 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 699 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 700 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); |
| 701 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 702 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 703 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 704 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 705 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 706 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); |
| 707 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 708 | entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 709 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 710 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 711 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 712 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); |
| 713 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 714 | entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 715 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 716 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 717 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 718 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); |
| 719 | |
| 720 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); |
| 721 | rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 722 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 723 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); |
| 724 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 725 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 726 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 727 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, |
| 728 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 729 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); |
| 730 | |
| 731 | return 0; |
| 732 | } |
| 733 | |
| 734 | static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) |
| 735 | { |
| 736 | u32 reg; |
| 737 | |
| 738 | rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002); |
| 739 | rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002); |
| 740 | rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20); |
| 741 | rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002); |
| 742 | |
| 743 | rt2x00pci_register_read(rt2x00dev, TIMECSR, ®); |
| 744 | rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); |
| 745 | rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); |
| 746 | rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); |
| 747 | rt2x00pci_register_write(rt2x00dev, TIMECSR, reg); |
| 748 | |
| 749 | rt2x00pci_register_read(rt2x00dev, CSR9, ®); |
| 750 | rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, |
| 751 | (rt2x00dev->rx->data_size / 128)); |
| 752 | rt2x00pci_register_write(rt2x00dev, CSR9, reg); |
| 753 | |
Ivo van Doorn | 1f90916 | 2008-07-08 13:45:20 +0200 | [diff] [blame] | 754 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
| 755 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); |
| 756 | rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); |
| 757 | rt2x00_set_field32(®, CSR14_TBCN, 0); |
| 758 | rt2x00_set_field32(®, CSR14_TCFP, 0); |
| 759 | rt2x00_set_field32(®, CSR14_TATIMW, 0); |
| 760 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); |
| 761 | rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); |
| 762 | rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); |
| 763 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
| 764 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 765 | rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000); |
| 766 | |
| 767 | rt2x00pci_register_read(rt2x00dev, ARCSR0, ®); |
| 768 | rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133); |
| 769 | rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134); |
| 770 | rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136); |
| 771 | rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135); |
| 772 | rt2x00pci_register_write(rt2x00dev, ARCSR0, reg); |
| 773 | |
| 774 | rt2x00pci_register_read(rt2x00dev, RXCSR3, ®); |
| 775 | rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/ |
| 776 | rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); |
| 777 | rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */ |
| 778 | rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); |
| 779 | rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */ |
| 780 | rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); |
| 781 | rt2x00pci_register_write(rt2x00dev, RXCSR3, reg); |
| 782 | |
| 783 | rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); |
| 784 | |
| 785 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) |
| 786 | return -EBUSY; |
| 787 | |
| 788 | rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223); |
| 789 | rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518); |
| 790 | |
| 791 | rt2x00pci_register_read(rt2x00dev, MACCSR2, ®); |
| 792 | rt2x00_set_field32(®, MACCSR2_DELAY, 64); |
| 793 | rt2x00pci_register_write(rt2x00dev, MACCSR2, reg); |
| 794 | |
| 795 | rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®); |
| 796 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); |
| 797 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154); |
| 798 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); |
| 799 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154); |
| 800 | rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg); |
| 801 | |
| 802 | rt2x00pci_register_read(rt2x00dev, CSR1, ®); |
| 803 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); |
| 804 | rt2x00_set_field32(®, CSR1_BBP_RESET, 0); |
| 805 | rt2x00_set_field32(®, CSR1_HOST_READY, 0); |
| 806 | rt2x00pci_register_write(rt2x00dev, CSR1, reg); |
| 807 | |
| 808 | rt2x00pci_register_read(rt2x00dev, CSR1, ®); |
| 809 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); |
| 810 | rt2x00_set_field32(®, CSR1_HOST_READY, 1); |
| 811 | rt2x00pci_register_write(rt2x00dev, CSR1, reg); |
| 812 | |
| 813 | /* |
| 814 | * We must clear the FCS and FIFO error count. |
| 815 | * These registers are cleared on read, |
| 816 | * so we may pass a useless variable to store the value. |
| 817 | */ |
| 818 | rt2x00pci_register_read(rt2x00dev, CNT0, ®); |
| 819 | rt2x00pci_register_read(rt2x00dev, CNT4, ®); |
| 820 | |
| 821 | return 0; |
| 822 | } |
| 823 | |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 824 | static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
| 825 | { |
| 826 | unsigned int i; |
| 827 | u8 value; |
| 828 | |
| 829 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 830 | rt2400pci_bbp_read(rt2x00dev, 0, &value); |
| 831 | if ((value != 0xff) && (value != 0x00)) |
| 832 | return 0; |
| 833 | udelay(REGISTER_BUSY_DELAY); |
| 834 | } |
| 835 | |
| 836 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); |
| 837 | return -EACCES; |
| 838 | } |
| 839 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 840 | static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev) |
| 841 | { |
| 842 | unsigned int i; |
| 843 | u16 eeprom; |
| 844 | u8 reg_id; |
| 845 | u8 value; |
| 846 | |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 847 | if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev))) |
| 848 | return -EACCES; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 849 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 850 | rt2400pci_bbp_write(rt2x00dev, 1, 0x00); |
| 851 | rt2400pci_bbp_write(rt2x00dev, 3, 0x27); |
| 852 | rt2400pci_bbp_write(rt2x00dev, 4, 0x08); |
| 853 | rt2400pci_bbp_write(rt2x00dev, 10, 0x0f); |
| 854 | rt2400pci_bbp_write(rt2x00dev, 15, 0x72); |
| 855 | rt2400pci_bbp_write(rt2x00dev, 16, 0x74); |
| 856 | rt2400pci_bbp_write(rt2x00dev, 17, 0x20); |
| 857 | rt2400pci_bbp_write(rt2x00dev, 18, 0x72); |
| 858 | rt2400pci_bbp_write(rt2x00dev, 19, 0x0b); |
| 859 | rt2400pci_bbp_write(rt2x00dev, 20, 0x00); |
| 860 | rt2400pci_bbp_write(rt2x00dev, 28, 0x11); |
| 861 | rt2400pci_bbp_write(rt2x00dev, 29, 0x04); |
| 862 | rt2400pci_bbp_write(rt2x00dev, 30, 0x21); |
| 863 | rt2400pci_bbp_write(rt2x00dev, 31, 0x00); |
| 864 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 865 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
| 866 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); |
| 867 | |
| 868 | if (eeprom != 0xffff && eeprom != 0x0000) { |
| 869 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); |
| 870 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 871 | rt2400pci_bbp_write(rt2x00dev, reg_id, value); |
| 872 | } |
| 873 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 874 | |
| 875 | return 0; |
| 876 | } |
| 877 | |
| 878 | /* |
| 879 | * Device state switch handlers. |
| 880 | */ |
| 881 | static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev, |
| 882 | enum dev_state state) |
| 883 | { |
| 884 | u32 reg; |
| 885 | |
| 886 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); |
| 887 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 888 | (state == STATE_RADIO_RX_OFF) || |
| 889 | (state == STATE_RADIO_RX_OFF_LINK)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 890 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); |
| 891 | } |
| 892 | |
| 893 | static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
| 894 | enum dev_state state) |
| 895 | { |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 896 | int mask = (state == STATE_RADIO_IRQ_OFF) || |
| 897 | (state == STATE_RADIO_IRQ_OFF_ISR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 898 | u32 reg; |
| 899 | |
| 900 | /* |
| 901 | * When interrupts are being enabled, the interrupt registers |
| 902 | * should clear the register to assure a clean state. |
| 903 | */ |
| 904 | if (state == STATE_RADIO_IRQ_ON) { |
| 905 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); |
| 906 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); |
| 907 | } |
| 908 | |
| 909 | /* |
| 910 | * Only toggle the interrupts bits we are going to use. |
| 911 | * Non-checked interrupt bits are disabled by default. |
| 912 | */ |
| 913 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
| 914 | rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); |
| 915 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); |
| 916 | rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); |
| 917 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); |
| 918 | rt2x00_set_field32(®, CSR8_RXDONE, mask); |
| 919 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); |
| 920 | } |
| 921 | |
| 922 | static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev) |
| 923 | { |
| 924 | /* |
| 925 | * Initialize all registers. |
| 926 | */ |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 927 | if (unlikely(rt2400pci_init_queues(rt2x00dev) || |
| 928 | rt2400pci_init_registers(rt2x00dev) || |
| 929 | rt2400pci_init_bbp(rt2x00dev))) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 930 | return -EIO; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 931 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 932 | return 0; |
| 933 | } |
| 934 | |
| 935 | static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev) |
| 936 | { |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 937 | /* |
| 938 | * Disable power |
| 939 | */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 940 | rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 941 | } |
| 942 | |
| 943 | static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, |
| 944 | enum dev_state state) |
| 945 | { |
Gertjan van Wingerde | 9655a6e | 2010-05-13 21:16:03 +0200 | [diff] [blame] | 946 | u32 reg, reg2; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 947 | unsigned int i; |
| 948 | char put_to_sleep; |
| 949 | char bbp_state; |
| 950 | char rf_state; |
| 951 | |
| 952 | put_to_sleep = (state != STATE_AWAKE); |
| 953 | |
| 954 | rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®); |
| 955 | rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); |
| 956 | rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); |
| 957 | rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); |
| 958 | rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); |
| 959 | rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); |
| 960 | |
| 961 | /* |
| 962 | * Device is not guaranteed to be in the requested state yet. |
| 963 | * We must wait until the register indicates that the |
| 964 | * device has entered the correct state. |
| 965 | */ |
| 966 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
Gertjan van Wingerde | 9655a6e | 2010-05-13 21:16:03 +0200 | [diff] [blame] | 967 | rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®2); |
| 968 | bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE); |
| 969 | rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 970 | if (bbp_state == state && rf_state == state) |
| 971 | return 0; |
Gertjan van Wingerde | 9655a6e | 2010-05-13 21:16:03 +0200 | [diff] [blame] | 972 | rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 973 | msleep(10); |
| 974 | } |
| 975 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 976 | return -EBUSY; |
| 977 | } |
| 978 | |
| 979 | static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, |
| 980 | enum dev_state state) |
| 981 | { |
| 982 | int retval = 0; |
| 983 | |
| 984 | switch (state) { |
| 985 | case STATE_RADIO_ON: |
| 986 | retval = rt2400pci_enable_radio(rt2x00dev); |
| 987 | break; |
| 988 | case STATE_RADIO_OFF: |
| 989 | rt2400pci_disable_radio(rt2x00dev); |
| 990 | break; |
| 991 | case STATE_RADIO_RX_ON: |
Ivo van Doorn | 61667d8 | 2008-02-25 23:15:05 +0100 | [diff] [blame] | 992 | case STATE_RADIO_RX_ON_LINK: |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 993 | case STATE_RADIO_RX_OFF: |
Ivo van Doorn | 61667d8 | 2008-02-25 23:15:05 +0100 | [diff] [blame] | 994 | case STATE_RADIO_RX_OFF_LINK: |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 995 | rt2400pci_toggle_rx(rt2x00dev, state); |
| 996 | break; |
| 997 | case STATE_RADIO_IRQ_ON: |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 998 | case STATE_RADIO_IRQ_ON_ISR: |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 999 | case STATE_RADIO_IRQ_OFF: |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1000 | case STATE_RADIO_IRQ_OFF_ISR: |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1001 | rt2400pci_toggle_irq(rt2x00dev, state); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1002 | break; |
| 1003 | case STATE_DEEP_SLEEP: |
| 1004 | case STATE_SLEEP: |
| 1005 | case STATE_STANDBY: |
| 1006 | case STATE_AWAKE: |
| 1007 | retval = rt2400pci_set_state(rt2x00dev, state); |
| 1008 | break; |
| 1009 | default: |
| 1010 | retval = -ENOTSUPP; |
| 1011 | break; |
| 1012 | } |
| 1013 | |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1014 | if (unlikely(retval)) |
| 1015 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", |
| 1016 | state, retval); |
| 1017 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1018 | return retval; |
| 1019 | } |
| 1020 | |
| 1021 | /* |
| 1022 | * TX descriptor initialization |
| 1023 | */ |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1024 | static void rt2400pci_write_tx_desc(struct queue_entry *entry, |
Ivo van Doorn | 61486e0 | 2008-05-10 13:42:31 +0200 | [diff] [blame] | 1025 | struct txentry_desc *txdesc) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1026 | { |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1027 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
| 1028 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1029 | __le32 *txd = entry_priv->desc; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1030 | u32 word; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1031 | |
| 1032 | /* |
| 1033 | * Start writing the descriptor words. |
| 1034 | */ |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1035 | rt2x00_desc_read(txd, 1, &word); |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 1036 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1037 | rt2x00_desc_write(txd, 1, word); |
Gertjan van Wingerde | 4de36fe | 2008-05-10 13:44:14 +0200 | [diff] [blame] | 1038 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1039 | rt2x00_desc_read(txd, 2, &word); |
Gertjan van Wingerde | df624ca | 2010-05-03 22:43:05 +0200 | [diff] [blame] | 1040 | rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length); |
| 1041 | rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1042 | rt2x00_desc_write(txd, 2, word); |
| 1043 | |
| 1044 | rt2x00_desc_read(txd, 3, &word); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1045 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); |
Ivo van Doorn | 49da260 | 2007-11-27 21:47:56 +0100 | [diff] [blame] | 1046 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); |
| 1047 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1048 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); |
Ivo van Doorn | 49da260 | 2007-11-27 21:47:56 +0100 | [diff] [blame] | 1049 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6); |
| 1050 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1051 | rt2x00_desc_write(txd, 3, word); |
| 1052 | |
| 1053 | rt2x00_desc_read(txd, 4, &word); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1054 | rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low); |
Ivo van Doorn | 49da260 | 2007-11-27 21:47:56 +0100 | [diff] [blame] | 1055 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); |
| 1056 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1057 | rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high); |
Ivo van Doorn | 49da260 | 2007-11-27 21:47:56 +0100 | [diff] [blame] | 1058 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7); |
| 1059 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1060 | rt2x00_desc_write(txd, 4, word); |
| 1061 | |
Gertjan van Wingerde | e01f1ec | 2010-05-11 23:51:39 +0200 | [diff] [blame] | 1062 | /* |
| 1063 | * Writing TXD word 0 must the last to prevent a race condition with |
| 1064 | * the device, whereby the device may take hold of the TXD before we |
| 1065 | * finished updating it. |
| 1066 | */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1067 | rt2x00_desc_read(txd, 0, &word); |
| 1068 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); |
| 1069 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); |
| 1070 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1071 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1072 | rt2x00_set_field32(&word, TXD_W0_ACK, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1073 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1074 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1075 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1076 | rt2x00_set_field32(&word, TXD_W0_RTS, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1077 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); |
| 1078 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1079 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
Ivo van Doorn | aade510 | 2008-05-10 13:45:58 +0200 | [diff] [blame] | 1080 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1081 | rt2x00_desc_write(txd, 0, word); |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1082 | |
| 1083 | /* |
| 1084 | * Register descriptor details in skb frame descriptor. |
| 1085 | */ |
| 1086 | skbdesc->desc = txd; |
| 1087 | skbdesc->desc_len = TXD_DESC_SIZE; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1088 | } |
| 1089 | |
| 1090 | /* |
| 1091 | * TX data initialization |
| 1092 | */ |
Gertjan van Wingerde | f224f4e | 2010-05-08 23:40:25 +0200 | [diff] [blame] | 1093 | static void rt2400pci_write_beacon(struct queue_entry *entry, |
| 1094 | struct txentry_desc *txdesc) |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1095 | { |
| 1096 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1097 | u32 reg; |
| 1098 | |
| 1099 | /* |
| 1100 | * Disable beaconing while we are reloading the beacon data, |
| 1101 | * otherwise we might be sending out invalid data. |
| 1102 | */ |
| 1103 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1104 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); |
| 1105 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
| 1106 | |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1107 | rt2x00queue_map_txskb(rt2x00dev, entry->skb); |
| 1108 | |
Gertjan van Wingerde | 5c3b685 | 2010-06-03 10:51:41 +0200 | [diff] [blame] | 1109 | /* |
| 1110 | * Write the TX descriptor for the beacon. |
| 1111 | */ |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1112 | rt2400pci_write_tx_desc(entry, txdesc); |
Gertjan van Wingerde | 5c3b685 | 2010-06-03 10:51:41 +0200 | [diff] [blame] | 1113 | |
| 1114 | /* |
| 1115 | * Dump beacon to userspace through debugfs. |
| 1116 | */ |
| 1117 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); |
Gertjan van Wingerde | d61cb26 | 2010-05-08 23:40:24 +0200 | [diff] [blame] | 1118 | |
| 1119 | /* |
| 1120 | * Enable beaconing again. |
| 1121 | */ |
| 1122 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); |
| 1123 | rt2x00_set_field32(®, CSR14_TBCN, 1); |
| 1124 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); |
| 1125 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1126 | } |
| 1127 | |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1128 | static void rt2400pci_kick_tx_queue(struct data_queue *queue) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1129 | { |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1130 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1131 | u32 reg; |
| 1132 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1133 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1134 | rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue->qid == QID_AC_BE)); |
| 1135 | rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue->qid == QID_AC_BK)); |
| 1136 | rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue->qid == QID_ATIM)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1137 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); |
| 1138 | } |
| 1139 | |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1140 | static void rt2400pci_kill_tx_queue(struct data_queue *queue) |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1141 | { |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1142 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1143 | u32 reg; |
| 1144 | |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1145 | if (queue->qid == QID_BEACON) { |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1146 | rt2x00pci_register_write(rt2x00dev, CSR14, 0); |
| 1147 | } else { |
| 1148 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); |
| 1149 | rt2x00_set_field32(®, TXCSR0_ABORT, 1); |
| 1150 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); |
| 1151 | } |
| 1152 | } |
| 1153 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1154 | /* |
| 1155 | * RX control handlers |
| 1156 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1157 | static void rt2400pci_fill_rxdone(struct queue_entry *entry, |
| 1158 | struct rxdone_entry_desc *rxdesc) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1159 | { |
Ivo van Doorn | ae73e58 | 2008-07-04 16:14:59 +0200 | [diff] [blame] | 1160 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1161 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1162 | u32 word0; |
| 1163 | u32 word2; |
Ivo van Doorn | 8999389 | 2008-03-09 22:49:04 +0100 | [diff] [blame] | 1164 | u32 word3; |
Ivo van Doorn | ae73e58 | 2008-07-04 16:14:59 +0200 | [diff] [blame] | 1165 | u32 word4; |
| 1166 | u64 tsf; |
| 1167 | u32 rx_low; |
| 1168 | u32 rx_high; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1169 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1170 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
| 1171 | rt2x00_desc_read(entry_priv->desc, 2, &word2); |
| 1172 | rt2x00_desc_read(entry_priv->desc, 3, &word3); |
Ivo van Doorn | ae73e58 | 2008-07-04 16:14:59 +0200 | [diff] [blame] | 1173 | rt2x00_desc_read(entry_priv->desc, 4, &word4); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1174 | |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 1175 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1176 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 1177 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1178 | rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1179 | |
| 1180 | /* |
Ivo van Doorn | ae73e58 | 2008-07-04 16:14:59 +0200 | [diff] [blame] | 1181 | * We only get the lower 32bits from the timestamp, |
| 1182 | * to get the full 64bits we must complement it with |
| 1183 | * the timestamp from get_tsf(). |
| 1184 | * Note that when a wraparound of the lower 32bits |
| 1185 | * has occurred between the frame arrival and the get_tsf() |
| 1186 | * call, we must decrease the higher 32bits with 1 to get |
| 1187 | * to correct value. |
| 1188 | */ |
| 1189 | tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw); |
| 1190 | rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME); |
| 1191 | rx_high = upper_32_bits(tsf); |
| 1192 | |
| 1193 | if ((u32)tsf <= rx_low) |
| 1194 | rx_high--; |
| 1195 | |
| 1196 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1197 | * Obtain the status about this packet. |
Ivo van Doorn | 8ed0985 | 2008-03-10 00:30:44 +0100 | [diff] [blame] | 1198 | * The signal is the PLCP value, and needs to be stripped |
| 1199 | * of the preamble bit (0x08). |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1200 | */ |
Ivo van Doorn | ae73e58 | 2008-07-04 16:14:59 +0200 | [diff] [blame] | 1201 | rxdesc->timestamp = ((u64)rx_high << 32) | rx_low; |
Ivo van Doorn | 8ed0985 | 2008-03-10 00:30:44 +0100 | [diff] [blame] | 1202 | rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08; |
Ivo van Doorn | 8999389 | 2008-03-09 22:49:04 +0100 | [diff] [blame] | 1203 | rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) - |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1204 | entry->queue->rt2x00dev->rssi_offset; |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1205 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
Ivo van Doorn | 19d30e0 | 2008-03-15 21:38:07 +0100 | [diff] [blame] | 1206 | |
Ivo van Doorn | dec13b6 | 2008-05-10 13:46:08 +0200 | [diff] [blame] | 1207 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; |
Ivo van Doorn | 19d30e0 | 2008-03-15 21:38:07 +0100 | [diff] [blame] | 1208 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
| 1209 | rxdesc->dev_flags |= RXDONE_MY_BSS; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1210 | } |
| 1211 | |
| 1212 | /* |
| 1213 | * Interrupt functions. |
| 1214 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1215 | static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | e58c6ac | 2008-04-21 19:00:47 +0200 | [diff] [blame] | 1216 | const enum data_queue_qid queue_idx) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1217 | { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1218 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1219 | struct queue_entry_priv_pci *entry_priv; |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1220 | struct queue_entry *entry; |
| 1221 | struct txdone_entry_desc txdesc; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1222 | u32 word; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1223 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1224 | while (!rt2x00queue_empty(queue)) { |
| 1225 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1226 | entry_priv = entry->priv_data; |
| 1227 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1228 | |
| 1229 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
| 1230 | !rt2x00_get_field32(word, TXD_W0_VALID)) |
| 1231 | break; |
| 1232 | |
| 1233 | /* |
| 1234 | * Obtain the status about this packet. |
| 1235 | */ |
Ivo van Doorn | fb55f4d | 2008-05-10 13:42:06 +0200 | [diff] [blame] | 1236 | txdesc.flags = 0; |
| 1237 | switch (rt2x00_get_field32(word, TXD_W0_RESULT)) { |
| 1238 | case 0: /* Success */ |
| 1239 | case 1: /* Success with retry */ |
| 1240 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); |
| 1241 | break; |
| 1242 | case 2: /* Failure, excessive retries */ |
| 1243 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); |
| 1244 | /* Don't break, this is a failed frame! */ |
| 1245 | default: /* Failure */ |
| 1246 | __set_bit(TXDONE_FAILURE, &txdesc.flags); |
| 1247 | } |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1248 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1249 | |
Gertjan van Wingerde | e513a0b | 2010-06-29 21:41:40 +0200 | [diff] [blame] | 1250 | rt2x00lib_txdone(entry, &txdesc); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1251 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1252 | } |
| 1253 | |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1254 | static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1255 | { |
| 1256 | struct rt2x00_dev *rt2x00dev = dev_instance; |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1257 | u32 reg = rt2x00dev->irqvalue[0]; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1258 | |
| 1259 | /* |
| 1260 | * Handle interrupts, walk through all bits |
| 1261 | * and run the tasks, the bits are checked in order of |
| 1262 | * priority. |
| 1263 | */ |
| 1264 | |
| 1265 | /* |
| 1266 | * 1 - Beacon timer expired interrupt. |
| 1267 | */ |
| 1268 | if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) |
| 1269 | rt2x00lib_beacondone(rt2x00dev); |
| 1270 | |
| 1271 | /* |
| 1272 | * 2 - Rx ring done interrupt. |
| 1273 | */ |
| 1274 | if (rt2x00_get_field32(reg, CSR7_RXDONE)) |
| 1275 | rt2x00pci_rxdone(rt2x00dev); |
| 1276 | |
| 1277 | /* |
| 1278 | * 3 - Atim ring transmit done interrupt. |
| 1279 | */ |
| 1280 | if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) |
Ivo van Doorn | e58c6ac | 2008-04-21 19:00:47 +0200 | [diff] [blame] | 1281 | rt2400pci_txdone(rt2x00dev, QID_ATIM); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1282 | |
| 1283 | /* |
| 1284 | * 4 - Priority ring transmit done interrupt. |
| 1285 | */ |
| 1286 | if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) |
Ivo van Doorn | e58c6ac | 2008-04-21 19:00:47 +0200 | [diff] [blame] | 1287 | rt2400pci_txdone(rt2x00dev, QID_AC_BE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1288 | |
| 1289 | /* |
| 1290 | * 5 - Tx ring transmit done interrupt. |
| 1291 | */ |
| 1292 | if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) |
Ivo van Doorn | e58c6ac | 2008-04-21 19:00:47 +0200 | [diff] [blame] | 1293 | rt2400pci_txdone(rt2x00dev, QID_AC_BK); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1294 | |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1295 | /* Enable interrupts again. */ |
| 1296 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, |
| 1297 | STATE_RADIO_IRQ_ON_ISR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1298 | return IRQ_HANDLED; |
| 1299 | } |
| 1300 | |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1301 | static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) |
| 1302 | { |
| 1303 | struct rt2x00_dev *rt2x00dev = dev_instance; |
| 1304 | u32 reg; |
| 1305 | |
| 1306 | /* |
| 1307 | * Get the interrupt sources & saved to local variable. |
| 1308 | * Write register value back to clear pending interrupts. |
| 1309 | */ |
| 1310 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); |
| 1311 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); |
| 1312 | |
| 1313 | if (!reg) |
| 1314 | return IRQ_NONE; |
| 1315 | |
| 1316 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
| 1317 | return IRQ_HANDLED; |
| 1318 | |
| 1319 | /* Store irqvalues for use in the interrupt thread. */ |
| 1320 | rt2x00dev->irqvalue[0] = reg; |
| 1321 | |
| 1322 | /* Disable interrupts, will be enabled again in the interrupt thread. */ |
| 1323 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, |
| 1324 | STATE_RADIO_IRQ_OFF_ISR); |
| 1325 | |
| 1326 | return IRQ_WAKE_THREAD; |
| 1327 | } |
| 1328 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1329 | /* |
| 1330 | * Device probe functions. |
| 1331 | */ |
| 1332 | static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
| 1333 | { |
| 1334 | struct eeprom_93cx6 eeprom; |
| 1335 | u32 reg; |
| 1336 | u16 word; |
| 1337 | u8 *mac; |
| 1338 | |
| 1339 | rt2x00pci_register_read(rt2x00dev, CSR21, ®); |
| 1340 | |
| 1341 | eeprom.data = rt2x00dev; |
| 1342 | eeprom.register_read = rt2400pci_eepromregister_read; |
| 1343 | eeprom.register_write = rt2400pci_eepromregister_write; |
| 1344 | eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? |
| 1345 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; |
| 1346 | eeprom.reg_data_in = 0; |
| 1347 | eeprom.reg_data_out = 0; |
| 1348 | eeprom.reg_data_clock = 0; |
| 1349 | eeprom.reg_chip_select = 0; |
| 1350 | |
| 1351 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, |
| 1352 | EEPROM_SIZE / sizeof(u16)); |
| 1353 | |
| 1354 | /* |
| 1355 | * Start validation of the data that has been read. |
| 1356 | */ |
| 1357 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); |
| 1358 | if (!is_valid_ether_addr(mac)) { |
| 1359 | random_ether_addr(mac); |
Johannes Berg | e174961 | 2008-10-27 15:59:26 -0700 | [diff] [blame] | 1360 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1361 | } |
| 1362 | |
| 1363 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); |
| 1364 | if (word == 0xffff) { |
| 1365 | ERROR(rt2x00dev, "Invalid EEPROM data detected.\n"); |
| 1366 | return -EINVAL; |
| 1367 | } |
| 1368 | |
| 1369 | return 0; |
| 1370 | } |
| 1371 | |
| 1372 | static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev) |
| 1373 | { |
| 1374 | u32 reg; |
| 1375 | u16 value; |
| 1376 | u16 eeprom; |
| 1377 | |
| 1378 | /* |
| 1379 | * Read EEPROM word for configuration. |
| 1380 | */ |
| 1381 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); |
| 1382 | |
| 1383 | /* |
| 1384 | * Identify RF chipset. |
| 1385 | */ |
| 1386 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); |
| 1387 | rt2x00pci_register_read(rt2x00dev, CSR0, ®); |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1388 | rt2x00_set_chip(rt2x00dev, RT2460, value, |
| 1389 | rt2x00_get_field32(reg, CSR0_REVISION)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1390 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1391 | if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1392 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
| 1393 | return -ENODEV; |
| 1394 | } |
| 1395 | |
| 1396 | /* |
| 1397 | * Identify default antenna configuration. |
| 1398 | */ |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 1399 | rt2x00dev->default_ant.tx = |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1400 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 1401 | rt2x00dev->default_ant.rx = |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1402 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
| 1403 | |
| 1404 | /* |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 1405 | * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead. |
| 1406 | * I am not 100% sure about this, but the legacy drivers do not |
| 1407 | * indicate antenna swapping in software is required when |
| 1408 | * diversity is enabled. |
| 1409 | */ |
| 1410 | if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY) |
| 1411 | rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; |
| 1412 | if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY) |
| 1413 | rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; |
| 1414 | |
| 1415 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1416 | * Store led mode, for correct led behaviour. |
| 1417 | */ |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 1418 | #ifdef CONFIG_RT2X00_LIB_LEDS |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 1419 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); |
| 1420 | |
Ivo van Doorn | 475433b | 2008-06-03 20:30:01 +0200 | [diff] [blame] | 1421 | rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
Ivo van Doorn | 3d3e451 | 2009-01-17 20:44:08 +0100 | [diff] [blame] | 1422 | if (value == LED_MODE_TXRX_ACTIVITY || |
| 1423 | value == LED_MODE_DEFAULT || |
| 1424 | value == LED_MODE_ASUS) |
Ivo van Doorn | 475433b | 2008-06-03 20:30:01 +0200 | [diff] [blame] | 1425 | rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual, |
| 1426 | LED_TYPE_ACTIVITY); |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 1427 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1428 | |
| 1429 | /* |
| 1430 | * Detect if this device has an hardware controlled radio. |
| 1431 | */ |
| 1432 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) |
Ivo van Doorn | 066cb63 | 2007-09-25 20:55:39 +0200 | [diff] [blame] | 1433 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1434 | |
| 1435 | /* |
| 1436 | * Check if the BBP tuning should be enabled. |
| 1437 | */ |
Ivo van Doorn | 27df2a9 | 2010-07-11 12:24:22 +0200 | [diff] [blame] | 1438 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING)) |
| 1439 | __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1440 | |
| 1441 | return 0; |
| 1442 | } |
| 1443 | |
| 1444 | /* |
| 1445 | * RF value list for RF2420 & RF2421 |
| 1446 | * Supports: 2.4 GHz |
| 1447 | */ |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1448 | static const struct rf_channel rf_vals_b[] = { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1449 | { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 }, |
| 1450 | { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 }, |
| 1451 | { 3, 0x00022058, 0x000c2002, 0x00000101, 0 }, |
| 1452 | { 4, 0x00022058, 0x000c2016, 0x00000101, 0 }, |
| 1453 | { 5, 0x00022058, 0x000c202a, 0x00000101, 0 }, |
| 1454 | { 6, 0x00022058, 0x000c203e, 0x00000101, 0 }, |
| 1455 | { 7, 0x00022058, 0x000c2052, 0x00000101, 0 }, |
| 1456 | { 8, 0x00022058, 0x000c2066, 0x00000101, 0 }, |
| 1457 | { 9, 0x00022058, 0x000c207a, 0x00000101, 0 }, |
| 1458 | { 10, 0x00022058, 0x000c208e, 0x00000101, 0 }, |
| 1459 | { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 }, |
| 1460 | { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 }, |
| 1461 | { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 }, |
| 1462 | { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 }, |
| 1463 | }; |
| 1464 | |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1465 | static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1466 | { |
| 1467 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1468 | struct channel_info *info; |
| 1469 | char *tx_power; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1470 | unsigned int i; |
| 1471 | |
| 1472 | /* |
| 1473 | * Initialize all hw fields. |
| 1474 | */ |
Bruno Randolf | 566bfe5 | 2008-05-08 19:15:40 +0200 | [diff] [blame] | 1475 | rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
Johannes Berg | 4be8c38 | 2009-01-07 18:28:20 +0100 | [diff] [blame] | 1476 | IEEE80211_HW_SIGNAL_DBM | |
| 1477 | IEEE80211_HW_SUPPORTS_PS | |
| 1478 | IEEE80211_HW_PS_NULLFUNC_STACK; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1479 | |
Gertjan van Wingerde | 14a3bf8 | 2008-06-16 19:55:43 +0200 | [diff] [blame] | 1480 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1481 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
| 1482 | rt2x00_eeprom_addr(rt2x00dev, |
| 1483 | EEPROM_MAC_ADDR_0)); |
| 1484 | |
| 1485 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1486 | * Initialize hw_mode information. |
| 1487 | */ |
Ivo van Doorn | 31562e8 | 2008-02-17 17:35:05 +0100 | [diff] [blame] | 1488 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
| 1489 | spec->supported_rates = SUPPORT_RATE_CCK; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1490 | |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1491 | spec->num_channels = ARRAY_SIZE(rf_vals_b); |
| 1492 | spec->channels = rf_vals_b; |
| 1493 | |
| 1494 | /* |
| 1495 | * Create channel information array |
| 1496 | */ |
| 1497 | info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); |
| 1498 | if (!info) |
| 1499 | return -ENOMEM; |
| 1500 | |
| 1501 | spec->channels_info = info; |
| 1502 | |
| 1503 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); |
Ivo van Doorn | 8d1331b | 2010-08-23 19:56:07 +0200 | [diff] [blame] | 1504 | for (i = 0; i < 14; i++) { |
| 1505 | info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER); |
| 1506 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); |
| 1507 | } |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1508 | |
| 1509 | return 0; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1510 | } |
| 1511 | |
| 1512 | static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev) |
| 1513 | { |
| 1514 | int retval; |
| 1515 | |
| 1516 | /* |
| 1517 | * Allocate eeprom data. |
| 1518 | */ |
| 1519 | retval = rt2400pci_validate_eeprom(rt2x00dev); |
| 1520 | if (retval) |
| 1521 | return retval; |
| 1522 | |
| 1523 | retval = rt2400pci_init_eeprom(rt2x00dev); |
| 1524 | if (retval) |
| 1525 | return retval; |
| 1526 | |
| 1527 | /* |
| 1528 | * Initialize hw specifications. |
| 1529 | */ |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1530 | retval = rt2400pci_probe_hw_mode(rt2x00dev); |
| 1531 | if (retval) |
| 1532 | return retval; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1533 | |
| 1534 | /* |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 1535 | * This device requires the atim queue and DMA-mapped skbs. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1536 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1537 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 1538 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1539 | |
| 1540 | /* |
| 1541 | * Set the rssi offset. |
| 1542 | */ |
| 1543 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; |
| 1544 | |
| 1545 | return 0; |
| 1546 | } |
| 1547 | |
| 1548 | /* |
| 1549 | * IEEE80211 stack callback functions. |
| 1550 | */ |
Johannes Berg | e100bb6 | 2008-04-30 18:51:21 +0200 | [diff] [blame] | 1551 | static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1552 | const struct ieee80211_tx_queue_params *params) |
| 1553 | { |
| 1554 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 1555 | |
| 1556 | /* |
| 1557 | * We don't support variating cw_min and cw_max variables |
| 1558 | * per queue. So by default we only configure the TX queue, |
| 1559 | * and ignore all other configurations. |
| 1560 | */ |
Johannes Berg | e100bb6 | 2008-04-30 18:51:21 +0200 | [diff] [blame] | 1561 | if (queue != 0) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1562 | return -EINVAL; |
| 1563 | |
| 1564 | if (rt2x00mac_conf_tx(hw, queue, params)) |
| 1565 | return -EINVAL; |
| 1566 | |
| 1567 | /* |
| 1568 | * Write configuration to register. |
| 1569 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1570 | rt2400pci_config_cw(rt2x00dev, |
| 1571 | rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1572 | |
| 1573 | return 0; |
| 1574 | } |
| 1575 | |
| 1576 | static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw) |
| 1577 | { |
| 1578 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 1579 | u64 tsf; |
| 1580 | u32 reg; |
| 1581 | |
| 1582 | rt2x00pci_register_read(rt2x00dev, CSR17, ®); |
| 1583 | tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; |
| 1584 | rt2x00pci_register_read(rt2x00dev, CSR16, ®); |
| 1585 | tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); |
| 1586 | |
| 1587 | return tsf; |
| 1588 | } |
| 1589 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1590 | static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw) |
| 1591 | { |
| 1592 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 1593 | u32 reg; |
| 1594 | |
| 1595 | rt2x00pci_register_read(rt2x00dev, CSR15, ®); |
| 1596 | return rt2x00_get_field32(reg, CSR15_BEACON_SENT); |
| 1597 | } |
| 1598 | |
| 1599 | static const struct ieee80211_ops rt2400pci_mac80211_ops = { |
| 1600 | .tx = rt2x00mac_tx, |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 1601 | .start = rt2x00mac_start, |
| 1602 | .stop = rt2x00mac_stop, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1603 | .add_interface = rt2x00mac_add_interface, |
| 1604 | .remove_interface = rt2x00mac_remove_interface, |
| 1605 | .config = rt2x00mac_config, |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 1606 | .configure_filter = rt2x00mac_configure_filter, |
Ivo van Doorn | d8147f9 | 2010-07-11 12:24:47 +0200 | [diff] [blame] | 1607 | .sw_scan_start = rt2x00mac_sw_scan_start, |
| 1608 | .sw_scan_complete = rt2x00mac_sw_scan_complete, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1609 | .get_stats = rt2x00mac_get_stats, |
Johannes Berg | 471b3ef | 2007-12-28 14:32:58 +0100 | [diff] [blame] | 1610 | .bss_info_changed = rt2x00mac_bss_info_changed, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1611 | .conf_tx = rt2400pci_conf_tx, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1612 | .get_tsf = rt2400pci_get_tsf, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1613 | .tx_last_beacon = rt2400pci_tx_last_beacon, |
Ivo van Doorn | e47a5cd | 2009-07-01 15:17:35 +0200 | [diff] [blame] | 1614 | .rfkill_poll = rt2x00mac_rfkill_poll, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1615 | }; |
| 1616 | |
| 1617 | static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = { |
| 1618 | .irq_handler = rt2400pci_interrupt, |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1619 | .irq_handler_thread = rt2400pci_interrupt_thread, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1620 | .probe_hw = rt2400pci_probe_hw, |
| 1621 | .initialize = rt2x00pci_initialize, |
| 1622 | .uninitialize = rt2x00pci_uninitialize, |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 1623 | .get_entry_state = rt2400pci_get_entry_state, |
| 1624 | .clear_entry = rt2400pci_clear_entry, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1625 | .set_device_state = rt2400pci_set_device_state, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1626 | .rfkill_poll = rt2400pci_rfkill_poll, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1627 | .link_stats = rt2400pci_link_stats, |
| 1628 | .reset_tuner = rt2400pci_reset_tuner, |
| 1629 | .link_tuner = rt2400pci_link_tuner, |
| 1630 | .write_tx_desc = rt2400pci_write_tx_desc, |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1631 | .write_beacon = rt2400pci_write_beacon, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1632 | .kick_tx_queue = rt2400pci_kick_tx_queue, |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1633 | .kill_tx_queue = rt2400pci_kill_tx_queue, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1634 | .fill_rxdone = rt2400pci_fill_rxdone, |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 1635 | .config_filter = rt2400pci_config_filter, |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 1636 | .config_intf = rt2400pci_config_intf, |
Ivo van Doorn | 7281037 | 2008-03-09 22:46:18 +0100 | [diff] [blame] | 1637 | .config_erp = rt2400pci_config_erp, |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 1638 | .config_ant = rt2400pci_config_ant, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1639 | .config = rt2400pci_config, |
| 1640 | }; |
| 1641 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1642 | static const struct data_queue_desc rt2400pci_queue_rx = { |
| 1643 | .entry_num = RX_ENTRIES, |
| 1644 | .data_size = DATA_FRAME_SIZE, |
| 1645 | .desc_size = RXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1646 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1647 | }; |
| 1648 | |
| 1649 | static const struct data_queue_desc rt2400pci_queue_tx = { |
| 1650 | .entry_num = TX_ENTRIES, |
| 1651 | .data_size = DATA_FRAME_SIZE, |
| 1652 | .desc_size = TXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1653 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1654 | }; |
| 1655 | |
| 1656 | static const struct data_queue_desc rt2400pci_queue_bcn = { |
| 1657 | .entry_num = BEACON_ENTRIES, |
| 1658 | .data_size = MGMT_FRAME_SIZE, |
| 1659 | .desc_size = TXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1660 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1661 | }; |
| 1662 | |
| 1663 | static const struct data_queue_desc rt2400pci_queue_atim = { |
| 1664 | .entry_num = ATIM_ENTRIES, |
| 1665 | .data_size = DATA_FRAME_SIZE, |
| 1666 | .desc_size = TXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1667 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1668 | }; |
| 1669 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1670 | static const struct rt2x00_ops rt2400pci_ops = { |
Gertjan van Wingerde | 04d0362 | 2009-11-23 22:44:51 +0100 | [diff] [blame] | 1671 | .name = KBUILD_MODNAME, |
| 1672 | .max_sta_intf = 1, |
| 1673 | .max_ap_intf = 1, |
| 1674 | .eeprom_size = EEPROM_SIZE, |
| 1675 | .rf_size = RF_SIZE, |
| 1676 | .tx_queues = NUM_TX_QUEUES, |
Gertjan van Wingerde | e6218cc | 2009-11-23 22:44:52 +0100 | [diff] [blame] | 1677 | .extra_tx_headroom = 0, |
Gertjan van Wingerde | 04d0362 | 2009-11-23 22:44:51 +0100 | [diff] [blame] | 1678 | .rx = &rt2400pci_queue_rx, |
| 1679 | .tx = &rt2400pci_queue_tx, |
| 1680 | .bcn = &rt2400pci_queue_bcn, |
| 1681 | .atim = &rt2400pci_queue_atim, |
| 1682 | .lib = &rt2400pci_rt2x00_ops, |
| 1683 | .hw = &rt2400pci_mac80211_ops, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1684 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
Gertjan van Wingerde | 04d0362 | 2009-11-23 22:44:51 +0100 | [diff] [blame] | 1685 | .debugfs = &rt2400pci_rt2x00debug, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1686 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 1687 | }; |
| 1688 | |
| 1689 | /* |
| 1690 | * RT2400pci module information. |
| 1691 | */ |
Alexey Dobriyan | a3aa188 | 2010-01-07 11:58:11 +0000 | [diff] [blame] | 1692 | static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1693 | { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) }, |
| 1694 | { 0, } |
| 1695 | }; |
| 1696 | |
| 1697 | MODULE_AUTHOR(DRV_PROJECT); |
| 1698 | MODULE_VERSION(DRV_VERSION); |
| 1699 | MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver."); |
| 1700 | MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards"); |
| 1701 | MODULE_DEVICE_TABLE(pci, rt2400pci_device_table); |
| 1702 | MODULE_LICENSE("GPL"); |
| 1703 | |
| 1704 | static struct pci_driver rt2400pci_driver = { |
Ivo van Doorn | 2360157 | 2007-11-27 21:47:34 +0100 | [diff] [blame] | 1705 | .name = KBUILD_MODNAME, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1706 | .id_table = rt2400pci_device_table, |
| 1707 | .probe = rt2x00pci_probe, |
| 1708 | .remove = __devexit_p(rt2x00pci_remove), |
| 1709 | .suspend = rt2x00pci_suspend, |
| 1710 | .resume = rt2x00pci_resume, |
| 1711 | }; |
| 1712 | |
| 1713 | static int __init rt2400pci_init(void) |
| 1714 | { |
| 1715 | return pci_register_driver(&rt2400pci_driver); |
| 1716 | } |
| 1717 | |
| 1718 | static void __exit rt2400pci_exit(void) |
| 1719 | { |
| 1720 | pci_unregister_driver(&rt2400pci_driver); |
| 1721 | } |
| 1722 | |
| 1723 | module_init(rt2400pci_init); |
| 1724 | module_exit(rt2400pci_exit); |