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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_svw.c - ServerWorks / Apple K2 SATA
3 *
4 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
5 * Jeff Garzik <jgarzik@pobox.com>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
10 *
11 * Bits from Jeff Garzik, Copyright RedHat, Inc.
12 *
13 * This driver probably works with non-Apple versions of the
14 * Broadcom chipset...
15 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040017 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING. If not, write to
29 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 *
32 * libata documentation is available via 'make {ps|pdf}docs',
33 * as Documentation/DocBook/libata.*
34 *
35 * Hardware documentation available under NDA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070036 *
37 */
38
39#include <linux/config.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/pci.h>
43#include <linux/init.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/interrupt.h>
47#include "scsi.h"
48#include <scsi/scsi_host.h>
49#include <linux/libata.h>
50
51#ifdef CONFIG_PPC_OF
52#include <asm/prom.h>
53#include <asm/pci-bridge.h>
54#endif /* CONFIG_PPC_OF */
55
56#define DRV_NAME "sata_svw"
Narendra Sankar54258a82005-06-07 11:55:14 -070057#define DRV_VERSION "1.06"
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
59/* Taskfile registers offsets */
60#define K2_SATA_TF_CMD_OFFSET 0x00
61#define K2_SATA_TF_DATA_OFFSET 0x00
62#define K2_SATA_TF_ERROR_OFFSET 0x04
63#define K2_SATA_TF_NSECT_OFFSET 0x08
64#define K2_SATA_TF_LBAL_OFFSET 0x0c
65#define K2_SATA_TF_LBAM_OFFSET 0x10
66#define K2_SATA_TF_LBAH_OFFSET 0x14
67#define K2_SATA_TF_DEVICE_OFFSET 0x18
68#define K2_SATA_TF_CMDSTAT_OFFSET 0x1c
69#define K2_SATA_TF_CTL_OFFSET 0x20
70
71/* DMA base */
72#define K2_SATA_DMA_CMD_OFFSET 0x30
73
74/* SCRs base */
75#define K2_SATA_SCR_STATUS_OFFSET 0x40
76#define K2_SATA_SCR_ERROR_OFFSET 0x44
77#define K2_SATA_SCR_CONTROL_OFFSET 0x48
78
79/* Others */
80#define K2_SATA_SICR1_OFFSET 0x80
81#define K2_SATA_SICR2_OFFSET 0x84
82#define K2_SATA_SIM_OFFSET 0x88
83
84/* Port stride */
85#define K2_SATA_PORT_OFFSET 0x100
86
87
88static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
89{
90 if (sc_reg > SCR_CONTROL)
91 return 0xffffffffU;
92 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
93}
94
95
96static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
97 u32 val)
98{
99 if (sc_reg > SCR_CONTROL)
100 return;
101 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
102}
103
104
Jeff Garzik057ace52005-10-22 14:27:05 -0400105static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106{
107 struct ata_ioports *ioaddr = &ap->ioaddr;
108 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
109
110 if (tf->ctl != ap->last_ctl) {
111 writeb(tf->ctl, ioaddr->ctl_addr);
112 ap->last_ctl = tf->ctl;
113 ata_wait_idle(ap);
114 }
115 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
116 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
117 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
118 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
119 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
120 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
121 } else if (is_addr) {
122 writew(tf->feature, ioaddr->feature_addr);
123 writew(tf->nsect, ioaddr->nsect_addr);
124 writew(tf->lbal, ioaddr->lbal_addr);
125 writew(tf->lbam, ioaddr->lbam_addr);
126 writew(tf->lbah, ioaddr->lbah_addr);
127 }
128
129 if (tf->flags & ATA_TFLAG_DEVICE)
130 writeb(tf->device, ioaddr->device_addr);
131
132 ata_wait_idle(ap);
133}
134
135
136static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
137{
138 struct ata_ioports *ioaddr = &ap->ioaddr;
139 u16 nsect, lbal, lbam, lbah;
140
141 nsect = tf->nsect = readw(ioaddr->nsect_addr);
142 lbal = tf->lbal = readw(ioaddr->lbal_addr);
143 lbam = tf->lbam = readw(ioaddr->lbam_addr);
144 lbah = tf->lbah = readw(ioaddr->lbah_addr);
145 tf->device = readw(ioaddr->device_addr);
146
147 if (tf->flags & ATA_TFLAG_LBA48) {
148 tf->hob_feature = readw(ioaddr->error_addr) >> 8;
149 tf->hob_nsect = nsect >> 8;
150 tf->hob_lbal = lbal >> 8;
151 tf->hob_lbam = lbam >> 8;
152 tf->hob_lbah = lbah >> 8;
153 }
154}
155
156/**
157 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
158 * @qc: Info associated with this ATA transaction.
159 *
160 * LOCKING:
161 * spin_lock_irqsave(host_set lock)
162 */
163
164static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
165{
166 struct ata_port *ap = qc->ap;
167 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
168 u8 dmactl;
169 void *mmio = (void *) ap->ioaddr.bmdma_addr;
170 /* load PRD table addr. */
171 mb(); /* make sure PRD table writes are visible to controller */
172 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
173
174 /* specify data direction, triple-check start bit is clear */
175 dmactl = readb(mmio + ATA_DMA_CMD);
176 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
177 if (!rw)
178 dmactl |= ATA_DMA_WR;
179 writeb(dmactl, mmio + ATA_DMA_CMD);
180
181 /* issue r/w command if this is not a ATA DMA command*/
182 if (qc->tf.protocol != ATA_PROT_DMA)
183 ap->ops->exec_command(ap, &qc->tf);
184}
185
186/**
187 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
188 * @qc: Info associated with this ATA transaction.
189 *
190 * LOCKING:
191 * spin_lock_irqsave(host_set lock)
192 */
193
194static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
195{
196 struct ata_port *ap = qc->ap;
197 void *mmio = (void *) ap->ioaddr.bmdma_addr;
198 u8 dmactl;
199
200 /* start host DMA transaction */
201 dmactl = readb(mmio + ATA_DMA_CMD);
202 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
Jeff Garzik8a60a072005-07-31 13:13:24 -0400203 /* There is a race condition in certain SATA controllers that can
204 be seen when the r/w command is given to the controller before the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205 host DMA is started. On a Read command, the controller would initiate
206 the command to the drive even before it sees the DMA start. When there
Jeff Garzik8a60a072005-07-31 13:13:24 -0400207 are very fast drives connected to the controller, or when the data request
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208 hits in the drive cache, there is the possibility that the drive returns a part
209 or all of the requested data to the controller before the DMA start is issued.
210 In this case, the controller would become confused as to what to do with the data.
211 In the worst case when all the data is returned back to the controller, the
212 controller could hang. In other cases it could return partial data returning
213 in data corruption. This problem has been seen in PPC systems and can also appear
Jeff Garzik8a60a072005-07-31 13:13:24 -0400214 on an system with very fast disks, where the SATA controller is sitting behind a
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 number of bridges, and hence there is significant latency between the r/w command
216 and the start command. */
217 /* issue r/w command if the access is to ATA*/
218 if (qc->tf.protocol == ATA_PROT_DMA)
219 ap->ops->exec_command(ap, &qc->tf);
220}
221
Jeff Garzik8a60a072005-07-31 13:13:24 -0400222
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223static u8 k2_stat_check_status(struct ata_port *ap)
224{
225 return readl((void *) ap->ioaddr.status_addr);
226}
227
228#ifdef CONFIG_PPC_OF
229/*
230 * k2_sata_proc_info
231 * inout : decides on the direction of the dataflow and the meaning of the
232 * variables
233 * buffer: If inout==FALSE data is being written to it else read from it
234 * *start: If inout==FALSE start of the valid data in the buffer
235 * offset: If inout==FALSE offset from the beginning of the imaginary file
236 * from which we start writing into the buffer
237 * length: If inout==FALSE max number of bytes to be written into the buffer
238 * else number of bytes in the buffer
239 */
240static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
241 off_t offset, int count, int inout)
242{
243 struct ata_port *ap;
244 struct device_node *np;
245 int len, index;
246
247 /* Find the ata_port */
248 ap = (struct ata_port *) &shost->hostdata[0];
249 if (ap == NULL)
250 return 0;
251
252 /* Find the OF node for the PCI device proper */
253 np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
254 if (np == NULL)
255 return 0;
256
257 /* Match it to a port node */
258 index = (ap == ap->host_set->ports[0]) ? 0 : 1;
259 for (np = np->child; np != NULL; np = np->sibling) {
260 u32 *reg = (u32 *)get_property(np, "reg", NULL);
261 if (!reg)
262 continue;
263 if (index == *reg)
264 break;
265 }
266 if (np == NULL)
267 return 0;
268
269 len = sprintf(page, "devspec: %s\n", np->full_name);
270
271 return len;
272}
273#endif /* CONFIG_PPC_OF */
274
275
276static Scsi_Host_Template k2_sata_sht = {
277 .module = THIS_MODULE,
278 .name = DRV_NAME,
279 .ioctl = ata_scsi_ioctl,
280 .queuecommand = ata_scsi_queuecmd,
281 .eh_strategy_handler = ata_scsi_error,
282 .can_queue = ATA_DEF_QUEUE,
283 .this_id = ATA_SHT_THIS_ID,
284 .sg_tablesize = LIBATA_MAX_PRD,
285 .max_sectors = ATA_MAX_SECTORS,
286 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
287 .emulated = ATA_SHT_EMULATED,
288 .use_clustering = ATA_SHT_USE_CLUSTERING,
289 .proc_name = DRV_NAME,
290 .dma_boundary = ATA_DMA_BOUNDARY,
291 .slave_configure = ata_scsi_slave_config,
292#ifdef CONFIG_PPC_OF
293 .proc_info = k2_sata_proc_info,
294#endif
295 .bios_param = ata_std_bios_param,
296 .ordered_flush = 1,
297};
298
299
Jeff Garzik057ace52005-10-22 14:27:05 -0400300static const struct ata_port_operations k2_sata_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 .port_disable = ata_port_disable,
302 .tf_load = k2_sata_tf_load,
303 .tf_read = k2_sata_tf_read,
304 .check_status = k2_stat_check_status,
305 .exec_command = ata_exec_command,
306 .dev_select = ata_std_dev_select,
307 .phy_reset = sata_phy_reset,
308 .bmdma_setup = k2_bmdma_setup_mmio,
309 .bmdma_start = k2_bmdma_start_mmio,
310 .bmdma_stop = ata_bmdma_stop,
311 .bmdma_status = ata_bmdma_status,
312 .qc_prep = ata_qc_prep,
313 .qc_issue = ata_qc_issue_prot,
314 .eng_timeout = ata_eng_timeout,
315 .irq_handler = ata_interrupt,
316 .irq_clear = ata_bmdma_irq_clear,
317 .scr_read = k2_sata_scr_read,
318 .scr_write = k2_sata_scr_write,
319 .port_start = ata_port_start,
320 .port_stop = ata_port_stop,
Jeff Garzik374b1872005-08-30 05:42:52 -0400321 .host_stop = ata_pci_host_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322};
323
324static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
325{
326 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
327 port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
328 port->feature_addr =
329 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
330 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
331 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
332 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
333 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
334 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
335 port->command_addr =
336 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
337 port->altstatus_addr =
338 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
339 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
340 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
341}
342
343
344static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
345{
346 static int printed_version;
347 struct ata_probe_ent *probe_ent = NULL;
348 unsigned long base;
Jeff Garzikea6ba102005-08-30 05:18:18 -0400349 void __iomem *mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350 int pci_dev_busy = 0;
351 int rc;
Narendra Sankar60bf09a2005-05-25 16:51:00 -0700352 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353
354 if (!printed_version++)
355 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
356
357 /*
358 * If this driver happens to only be useful on Apple's K2, then
359 * we should check that here as it has a normal Serverworks ID
360 */
361 rc = pci_enable_device(pdev);
362 if (rc)
363 return rc;
364 /*
365 * Check if we have resources mapped at all (second function may
366 * have been disabled by firmware)
367 */
368 if (pci_resource_len(pdev, 5) == 0)
369 return -ENODEV;
370
371 /* Request PCI regions */
372 rc = pci_request_regions(pdev, DRV_NAME);
373 if (rc) {
374 pci_dev_busy = 1;
375 goto err_out;
376 }
377
378 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
379 if (rc)
380 goto err_out_regions;
381 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
382 if (rc)
383 goto err_out_regions;
384
385 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
386 if (probe_ent == NULL) {
387 rc = -ENOMEM;
388 goto err_out_regions;
389 }
390
391 memset(probe_ent, 0, sizeof(*probe_ent));
392 probe_ent->dev = pci_dev_to_dev(pdev);
393 INIT_LIST_HEAD(&probe_ent->node);
394
Jeff Garzik374b1872005-08-30 05:42:52 -0400395 mmio_base = pci_iomap(pdev, 5, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 if (mmio_base == NULL) {
397 rc = -ENOMEM;
398 goto err_out_free_ent;
399 }
400 base = (unsigned long) mmio_base;
401
402 /* Clear a magic bit in SCR1 according to Darwin, those help
403 * some funky seagate drives (though so far, those were already
Rolf Eike Beer104e5012005-03-27 08:50:38 -0500404 * set by the firmware on the machines I had access to)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405 */
406 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
407 mmio_base + K2_SATA_SICR1_OFFSET);
408
409 /* Clear SATA error & interrupts we don't use */
410 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
411 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
412
413 probe_ent->sht = &k2_sata_sht;
414 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
415 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
416 probe_ent->port_ops = &k2_sata_ops;
417 probe_ent->n_ports = 4;
418 probe_ent->irq = pdev->irq;
419 probe_ent->irq_flags = SA_SHIRQ;
420 probe_ent->mmio_base = mmio_base;
421
422 /* We don't care much about the PIO/UDMA masks, but the core won't like us
423 * if we don't fill these
424 */
425 probe_ent->pio_mask = 0x1f;
426 probe_ent->mwdma_mask = 0x7;
427 probe_ent->udma_mask = 0x7f;
428
Narendra Sankar60bf09a2005-05-25 16:51:00 -0700429 /* different controllers have different number of ports - currently 4 or 8 */
430 /* All ports are on the same function. Multi-function device is no
431 * longer available. This should not be seen in any system. */
432 for (i = 0; i < ent->driver_data; i++)
433 k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700434
435 pci_set_master(pdev);
436
437 /* FIXME: check ata_device_add return value */
438 ata_device_add(probe_ent);
439 kfree(probe_ent);
440
441 return 0;
442
443err_out_free_ent:
444 kfree(probe_ent);
445err_out_regions:
446 pci_release_regions(pdev);
447err_out:
448 if (!pci_dev_busy)
449 pci_disable_device(pdev);
450 return rc;
451}
452
Narendra Sankar60bf09a2005-05-25 16:51:00 -0700453/* 0x240 is device ID for Apple K2 device
454 * 0x241 is device ID for Serverworks Frodo4
455 * 0x242 is device ID for Serverworks Frodo8
456 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
457 * controller
458 * */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459static struct pci_device_id k2_sata_pci_tbl[] = {
Narendra Sankar60bf09a2005-05-25 16:51:00 -0700460 { 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
461 { 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
462 { 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
463 { 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 { }
465};
466
467
468static struct pci_driver k2_sata_pci_driver = {
469 .name = DRV_NAME,
470 .id_table = k2_sata_pci_tbl,
471 .probe = k2_sata_init_one,
472 .remove = ata_pci_remove_one,
473};
474
475
476static int __init k2_sata_init(void)
477{
478 return pci_module_init(&k2_sata_pci_driver);
479}
480
481
482static void __exit k2_sata_exit(void)
483{
484 pci_unregister_driver(&k2_sata_pci_driver);
485}
486
487
488MODULE_AUTHOR("Benjamin Herrenschmidt");
489MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
490MODULE_LICENSE("GPL");
491MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
492MODULE_VERSION(DRV_VERSION);
493
494module_init(k2_sata_init);
495module_exit(k2_sata_exit);