blob: e6568c19c939e1691a2a878e26292f1c877cae9b [file] [log] [blame]
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02001/*
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +02002 * GPIOs on MPC512x/8349/8572/8610 and compatible
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02003 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
17#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Peter Korsgaard345e5c82010-01-07 17:57:46 +010019#include <linux/irq.h>
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020020
21#define MPC8XXX_GPIO_PINS 32
22
23#define GPIO_DIR 0x00
24#define GPIO_ODR 0x04
25#define GPIO_DAT 0x08
26#define GPIO_IER 0x0c
27#define GPIO_IMR 0x10
28#define GPIO_ICR 0x14
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +020029#define GPIO_ICR2 0x18
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020030
31struct mpc8xxx_gpio_chip {
32 struct of_mm_gpio_chip mm_gc;
33 spinlock_t lock;
34
35 /*
36 * shadowed data register to be able to clear/set output pins in
37 * open drain mode safely
38 */
39 u32 data;
Grant Likelybae1d8f2012-02-14 14:06:50 -070040 struct irq_domain *irq;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +020041 void *of_dev_id_data;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020042};
43
44static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
45{
46 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
47}
48
49static inline struct mpc8xxx_gpio_chip *
50to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
51{
52 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
53}
54
55static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
56{
57 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
58
59 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
60}
61
Felix Radenskyc1a676d2009-08-12 08:57:39 +030062/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
63 * defined as output cannot be determined by reading GPDAT register,
64 * so we use shadow data register instead. The status of input pins
65 * is determined by reading GPDAT register.
66 */
67static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
68{
69 u32 val;
70 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
72
73 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
74
75 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
76}
77
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020078static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
79{
80 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
81
82 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
83}
84
85static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
86{
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
89 unsigned long flags;
90
91 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
92
93 if (val)
94 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
95 else
96 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
97
98 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
99
100 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
101}
102
103static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
104{
105 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
106 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
107 unsigned long flags;
108
109 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
110
111 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
112
113 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
114
115 return 0;
116}
117
118static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
119{
120 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
121 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
122 unsigned long flags;
123
124 mpc8xxx_gpio_set(gc, gpio, val);
125
126 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
127
128 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
129
130 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
131
132 return 0;
133}
134
Wolfram Sang28538df2011-12-13 10:12:48 +0100135static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
136{
137 /* GPIO 28..31 are input only on MPC5121 */
138 if (gpio >= 28)
139 return -EINVAL;
140
141 return mpc8xxx_gpio_dir_out(gc, gpio, val);
142}
143
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100144static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
145{
146 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
147 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
148
149 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
150 return irq_create_mapping(mpc8xxx_gc->irq, offset);
151 else
152 return -ENXIO;
153}
154
155static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
156{
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100157 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
Felix Radenskycfadd832011-10-11 10:24:21 +0200158 struct irq_chip *chip = irq_desc_get_chip(desc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100159 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
160 unsigned int mask;
161
162 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
163 if (mask)
164 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
165 32 - ffs(mask)));
Felix Radenskycfadd832011-10-11 10:24:21 +0200166 chip->irq_eoi(&desc->irq_data);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100167}
168
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000169static void mpc8xxx_irq_unmask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100170{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000171 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100172 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
173 unsigned long flags;
174
175 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
176
Grant Likely476eb492011-05-04 15:02:15 +1000177 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100178
179 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
180}
181
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000182static void mpc8xxx_irq_mask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100183{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000184 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100185 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
186 unsigned long flags;
187
188 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
189
Grant Likely476eb492011-05-04 15:02:15 +1000190 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100191
192 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
193}
194
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000195static void mpc8xxx_irq_ack(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100196{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000197 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100198 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
199
Grant Likely476eb492011-05-04 15:02:15 +1000200 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100201}
202
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000203static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100204{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000205 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100206 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
207 unsigned long flags;
208
209 switch (flow_type) {
210 case IRQ_TYPE_EDGE_FALLING:
211 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
212 setbits32(mm->regs + GPIO_ICR,
Grant Likely476eb492011-05-04 15:02:15 +1000213 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100214 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
215 break;
216
217 case IRQ_TYPE_EDGE_BOTH:
218 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
219 clrbits32(mm->regs + GPIO_ICR,
Grant Likely476eb492011-05-04 15:02:15 +1000220 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100221 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
222 break;
223
224 default:
225 return -EINVAL;
226 }
227
228 return 0;
229}
230
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000231static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200232{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000233 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200234 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
Grant Likely476eb492011-05-04 15:02:15 +1000235 unsigned long gpio = irqd_to_hwirq(d);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200236 void __iomem *reg;
237 unsigned int shift;
238 unsigned long flags;
239
240 if (gpio < 16) {
241 reg = mm->regs + GPIO_ICR;
242 shift = (15 - gpio) * 2;
243 } else {
244 reg = mm->regs + GPIO_ICR2;
245 shift = (15 - (gpio % 16)) * 2;
246 }
247
248 switch (flow_type) {
249 case IRQ_TYPE_EDGE_FALLING:
250 case IRQ_TYPE_LEVEL_LOW:
251 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
252 clrsetbits_be32(reg, 3 << shift, 2 << shift);
253 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
254 break;
255
256 case IRQ_TYPE_EDGE_RISING:
257 case IRQ_TYPE_LEVEL_HIGH:
258 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
259 clrsetbits_be32(reg, 3 << shift, 1 << shift);
260 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
261 break;
262
263 case IRQ_TYPE_EDGE_BOTH:
264 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
265 clrbits32(reg, 3 << shift);
266 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
267 break;
268
269 default:
270 return -EINVAL;
271 }
272
273 return 0;
274}
275
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100276static struct irq_chip mpc8xxx_irq_chip = {
277 .name = "mpc8xxx-gpio",
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000278 .irq_unmask = mpc8xxx_irq_unmask,
279 .irq_mask = mpc8xxx_irq_mask,
280 .irq_ack = mpc8xxx_irq_ack,
281 .irq_set_type = mpc8xxx_irq_set_type,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100282};
283
Grant Likelybae1d8f2012-02-14 14:06:50 -0700284static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100285 irq_hw_number_t hw)
286{
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200287 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
288
289 if (mpc8xxx_gc->of_dev_id_data)
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000290 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200291
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100292 irq_set_chip_data(virq, h->host_data);
293 irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
294 irq_set_irq_type(virq, IRQ_TYPE_NONE);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100295
296 return 0;
297}
298
Grant Likelybae1d8f2012-02-14 14:06:50 -0700299static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100300 .map = mpc8xxx_gpio_irq_map,
Grant Likelyff8c3ab2012-01-24 17:09:13 -0700301 .xlate = irq_domain_xlate_twocell,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100302};
303
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200304static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
305 { .compatible = "fsl,mpc8349-gpio", },
306 { .compatible = "fsl,mpc8572-gpio", },
307 { .compatible = "fsl,mpc8610-gpio", },
308 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
Kumar Gala15a51482011-10-22 16:20:42 -0500309 { .compatible = "fsl,pq3-gpio", },
Anatolij Gustschind1dcfbb2011-01-08 16:51:16 +0100310 { .compatible = "fsl,qoriq-gpio", },
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200311 {}
312};
313
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200314static void __init mpc8xxx_add_controller(struct device_node *np)
315{
316 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
317 struct of_mm_gpio_chip *mm_gc;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200318 struct gpio_chip *gc;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200319 const struct of_device_id *id;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100320 unsigned hwirq;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200321 int ret;
322
323 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
324 if (!mpc8xxx_gc) {
325 ret = -ENOMEM;
326 goto err;
327 }
328
329 spin_lock_init(&mpc8xxx_gc->lock);
330
331 mm_gc = &mpc8xxx_gc->mm_gc;
Anton Vorontsova19e3da2010-06-08 07:48:16 -0600332 gc = &mm_gc->gc;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200333
334 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200335 gc->ngpio = MPC8XXX_GPIO_PINS;
336 gc->direction_input = mpc8xxx_gpio_dir_in;
Wolfram Sang28538df2011-12-13 10:12:48 +0100337 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
338 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
339 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
340 mpc8572_gpio_get : mpc8xxx_gpio_get;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200341 gc->set = mpc8xxx_gpio_set;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100342 gc->to_irq = mpc8xxx_gpio_to_irq;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200343
344 ret = of_mm_gpiochip_add(np, mm_gc);
345 if (ret)
346 goto err;
347
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100348 hwirq = irq_of_parse_and_map(np, 0);
349 if (hwirq == NO_IRQ)
350 goto skip_irq;
351
Grant Likelya8db8cf2012-02-14 14:06:54 -0700352 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
353 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100354 if (!mpc8xxx_gc->irq)
355 goto skip_irq;
356
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200357 id = of_match_node(mpc8xxx_gpio_ids, np);
358 if (id)
359 mpc8xxx_gc->of_dev_id_data = id->data;
360
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100361 /* ack and mask all irqs */
362 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
363 out_be32(mm_gc->regs + GPIO_IMR, 0);
364
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100365 irq_set_handler_data(hwirq, mpc8xxx_gc);
366 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100367
368skip_irq:
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200369 return;
370
371err:
372 pr_err("%s: registration failed with status %d\n",
373 np->full_name, ret);
374 kfree(mpc8xxx_gc);
375
376 return;
377}
378
379static int __init mpc8xxx_add_gpiochips(void)
380{
381 struct device_node *np;
382
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200383 for_each_matching_node(np, mpc8xxx_gpio_ids)
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200384 mpc8xxx_add_controller(np);
385
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200386 return 0;
387}
388arch_initcall(mpc8xxx_add_gpiochips);