Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 1 | /* |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 2 | * GPIOs on MPC512x/8349/8572/8610 and compatible |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/spinlock.h> |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/of.h> |
| 16 | #include <linux/of_gpio.h> |
| 17 | #include <linux/gpio.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 18 | #include <linux/slab.h> |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 19 | #include <linux/irq.h> |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 20 | |
| 21 | #define MPC8XXX_GPIO_PINS 32 |
| 22 | |
| 23 | #define GPIO_DIR 0x00 |
| 24 | #define GPIO_ODR 0x04 |
| 25 | #define GPIO_DAT 0x08 |
| 26 | #define GPIO_IER 0x0c |
| 27 | #define GPIO_IMR 0x10 |
| 28 | #define GPIO_ICR 0x14 |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 29 | #define GPIO_ICR2 0x18 |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 30 | |
| 31 | struct mpc8xxx_gpio_chip { |
| 32 | struct of_mm_gpio_chip mm_gc; |
| 33 | spinlock_t lock; |
| 34 | |
| 35 | /* |
| 36 | * shadowed data register to be able to clear/set output pins in |
| 37 | * open drain mode safely |
| 38 | */ |
| 39 | u32 data; |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 40 | struct irq_domain *irq; |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 41 | void *of_dev_id_data; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 42 | }; |
| 43 | |
| 44 | static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) |
| 45 | { |
| 46 | return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); |
| 47 | } |
| 48 | |
| 49 | static inline struct mpc8xxx_gpio_chip * |
| 50 | to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm) |
| 51 | { |
| 52 | return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc); |
| 53 | } |
| 54 | |
| 55 | static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) |
| 56 | { |
| 57 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 58 | |
| 59 | mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); |
| 60 | } |
| 61 | |
Felix Radensky | c1a676d | 2009-08-12 08:57:39 +0300 | [diff] [blame] | 62 | /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs |
| 63 | * defined as output cannot be determined by reading GPDAT register, |
| 64 | * so we use shadow data register instead. The status of input pins |
| 65 | * is determined by reading GPDAT register. |
| 66 | */ |
| 67 | static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
| 68 | { |
| 69 | u32 val; |
| 70 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 71 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 72 | |
| 73 | val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR); |
| 74 | |
| 75 | return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio); |
| 76 | } |
| 77 | |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 78 | static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
| 79 | { |
| 80 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 81 | |
| 82 | return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); |
| 83 | } |
| 84 | |
| 85 | static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
| 86 | { |
| 87 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 88 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 89 | unsigned long flags; |
| 90 | |
| 91 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 92 | |
| 93 | if (val) |
| 94 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); |
| 95 | else |
| 96 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); |
| 97 | |
| 98 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); |
| 99 | |
| 100 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 101 | } |
| 102 | |
| 103 | static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
| 104 | { |
| 105 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 106 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 107 | unsigned long flags; |
| 108 | |
| 109 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 110 | |
| 111 | clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); |
| 112 | |
| 113 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 114 | |
| 115 | return 0; |
| 116 | } |
| 117 | |
| 118 | static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
| 119 | { |
| 120 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 121 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 122 | unsigned long flags; |
| 123 | |
| 124 | mpc8xxx_gpio_set(gc, gpio, val); |
| 125 | |
| 126 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 127 | |
| 128 | setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); |
| 129 | |
| 130 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 131 | |
| 132 | return 0; |
| 133 | } |
| 134 | |
Wolfram Sang | 28538df | 2011-12-13 10:12:48 +0100 | [diff] [blame] | 135 | static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
| 136 | { |
| 137 | /* GPIO 28..31 are input only on MPC5121 */ |
| 138 | if (gpio >= 28) |
| 139 | return -EINVAL; |
| 140 | |
| 141 | return mpc8xxx_gpio_dir_out(gc, gpio, val); |
| 142 | } |
| 143 | |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 144 | static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
| 145 | { |
| 146 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 147 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 148 | |
| 149 | if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) |
| 150 | return irq_create_mapping(mpc8xxx_gc->irq, offset); |
| 151 | else |
| 152 | return -ENXIO; |
| 153 | } |
| 154 | |
| 155 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) |
| 156 | { |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 157 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); |
Felix Radensky | cfadd83 | 2011-10-11 10:24:21 +0200 | [diff] [blame] | 158 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 159 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 160 | unsigned int mask; |
| 161 | |
| 162 | mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); |
| 163 | if (mask) |
| 164 | generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, |
| 165 | 32 - ffs(mask))); |
Felix Radensky | cfadd83 | 2011-10-11 10:24:21 +0200 | [diff] [blame] | 166 | chip->irq_eoi(&desc->irq_data); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 167 | } |
| 168 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 169 | static void mpc8xxx_irq_unmask(struct irq_data *d) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 170 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 171 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 172 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 173 | unsigned long flags; |
| 174 | |
| 175 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 176 | |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 177 | setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 178 | |
| 179 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 180 | } |
| 181 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 182 | static void mpc8xxx_irq_mask(struct irq_data *d) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 183 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 184 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 185 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 186 | unsigned long flags; |
| 187 | |
| 188 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 189 | |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 190 | clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 191 | |
| 192 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 193 | } |
| 194 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 195 | static void mpc8xxx_irq_ack(struct irq_data *d) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 196 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 197 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 198 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 199 | |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 200 | out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 201 | } |
| 202 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 203 | static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 204 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 205 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 206 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 207 | unsigned long flags; |
| 208 | |
| 209 | switch (flow_type) { |
| 210 | case IRQ_TYPE_EDGE_FALLING: |
| 211 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 212 | setbits32(mm->regs + GPIO_ICR, |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 213 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 214 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 215 | break; |
| 216 | |
| 217 | case IRQ_TYPE_EDGE_BOTH: |
| 218 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 219 | clrbits32(mm->regs + GPIO_ICR, |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 220 | mpc8xxx_gpio2mask(irqd_to_hwirq(d))); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 221 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 222 | break; |
| 223 | |
| 224 | default: |
| 225 | return -EINVAL; |
| 226 | } |
| 227 | |
| 228 | return 0; |
| 229 | } |
| 230 | |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 231 | static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 232 | { |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 233 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 234 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
Grant Likely | 476eb49 | 2011-05-04 15:02:15 +1000 | [diff] [blame] | 235 | unsigned long gpio = irqd_to_hwirq(d); |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 236 | void __iomem *reg; |
| 237 | unsigned int shift; |
| 238 | unsigned long flags; |
| 239 | |
| 240 | if (gpio < 16) { |
| 241 | reg = mm->regs + GPIO_ICR; |
| 242 | shift = (15 - gpio) * 2; |
| 243 | } else { |
| 244 | reg = mm->regs + GPIO_ICR2; |
| 245 | shift = (15 - (gpio % 16)) * 2; |
| 246 | } |
| 247 | |
| 248 | switch (flow_type) { |
| 249 | case IRQ_TYPE_EDGE_FALLING: |
| 250 | case IRQ_TYPE_LEVEL_LOW: |
| 251 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 252 | clrsetbits_be32(reg, 3 << shift, 2 << shift); |
| 253 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 254 | break; |
| 255 | |
| 256 | case IRQ_TYPE_EDGE_RISING: |
| 257 | case IRQ_TYPE_LEVEL_HIGH: |
| 258 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 259 | clrsetbits_be32(reg, 3 << shift, 1 << shift); |
| 260 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 261 | break; |
| 262 | |
| 263 | case IRQ_TYPE_EDGE_BOTH: |
| 264 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 265 | clrbits32(reg, 3 << shift); |
| 266 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 267 | break; |
| 268 | |
| 269 | default: |
| 270 | return -EINVAL; |
| 271 | } |
| 272 | |
| 273 | return 0; |
| 274 | } |
| 275 | |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 276 | static struct irq_chip mpc8xxx_irq_chip = { |
| 277 | .name = "mpc8xxx-gpio", |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 278 | .irq_unmask = mpc8xxx_irq_unmask, |
| 279 | .irq_mask = mpc8xxx_irq_mask, |
| 280 | .irq_ack = mpc8xxx_irq_ack, |
| 281 | .irq_set_type = mpc8xxx_irq_set_type, |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 282 | }; |
| 283 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 284 | static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int virq, |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 285 | irq_hw_number_t hw) |
| 286 | { |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 287 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; |
| 288 | |
| 289 | if (mpc8xxx_gc->of_dev_id_data) |
Lennert Buytenhek | 94347cb | 2011-03-08 22:26:58 +0000 | [diff] [blame] | 290 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 291 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 292 | irq_set_chip_data(virq, h->host_data); |
| 293 | irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); |
| 294 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 295 | |
| 296 | return 0; |
| 297 | } |
| 298 | |
Grant Likely | bae1d8f | 2012-02-14 14:06:50 -0700 | [diff] [blame] | 299 | static struct irq_domain_ops mpc8xxx_gpio_irq_ops = { |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 300 | .map = mpc8xxx_gpio_irq_map, |
Grant Likely | ff8c3ab | 2012-01-24 17:09:13 -0700 | [diff] [blame] | 301 | .xlate = irq_domain_xlate_twocell, |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 302 | }; |
| 303 | |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 304 | static struct of_device_id mpc8xxx_gpio_ids[] __initdata = { |
| 305 | { .compatible = "fsl,mpc8349-gpio", }, |
| 306 | { .compatible = "fsl,mpc8572-gpio", }, |
| 307 | { .compatible = "fsl,mpc8610-gpio", }, |
| 308 | { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, |
Kumar Gala | 15a5148 | 2011-10-22 16:20:42 -0500 | [diff] [blame] | 309 | { .compatible = "fsl,pq3-gpio", }, |
Anatolij Gustschin | d1dcfbb | 2011-01-08 16:51:16 +0100 | [diff] [blame] | 310 | { .compatible = "fsl,qoriq-gpio", }, |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 311 | {} |
| 312 | }; |
| 313 | |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 314 | static void __init mpc8xxx_add_controller(struct device_node *np) |
| 315 | { |
| 316 | struct mpc8xxx_gpio_chip *mpc8xxx_gc; |
| 317 | struct of_mm_gpio_chip *mm_gc; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 318 | struct gpio_chip *gc; |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 319 | const struct of_device_id *id; |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 320 | unsigned hwirq; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 321 | int ret; |
| 322 | |
| 323 | mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL); |
| 324 | if (!mpc8xxx_gc) { |
| 325 | ret = -ENOMEM; |
| 326 | goto err; |
| 327 | } |
| 328 | |
| 329 | spin_lock_init(&mpc8xxx_gc->lock); |
| 330 | |
| 331 | mm_gc = &mpc8xxx_gc->mm_gc; |
Anton Vorontsov | a19e3da | 2010-06-08 07:48:16 -0600 | [diff] [blame] | 332 | gc = &mm_gc->gc; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 333 | |
| 334 | mm_gc->save_regs = mpc8xxx_gpio_save_regs; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 335 | gc->ngpio = MPC8XXX_GPIO_PINS; |
| 336 | gc->direction_input = mpc8xxx_gpio_dir_in; |
Wolfram Sang | 28538df | 2011-12-13 10:12:48 +0100 | [diff] [blame] | 337 | gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ? |
| 338 | mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out; |
| 339 | gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ? |
| 340 | mpc8572_gpio_get : mpc8xxx_gpio_get; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 341 | gc->set = mpc8xxx_gpio_set; |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 342 | gc->to_irq = mpc8xxx_gpio_to_irq; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 343 | |
| 344 | ret = of_mm_gpiochip_add(np, mm_gc); |
| 345 | if (ret) |
| 346 | goto err; |
| 347 | |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 348 | hwirq = irq_of_parse_and_map(np, 0); |
| 349 | if (hwirq == NO_IRQ) |
| 350 | goto skip_irq; |
| 351 | |
Grant Likely | a8db8cf | 2012-02-14 14:06:54 -0700 | [diff] [blame] | 352 | mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, |
| 353 | &mpc8xxx_gpio_irq_ops, mpc8xxx_gc); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 354 | if (!mpc8xxx_gc->irq) |
| 355 | goto skip_irq; |
| 356 | |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 357 | id = of_match_node(mpc8xxx_gpio_ids, np); |
| 358 | if (id) |
| 359 | mpc8xxx_gc->of_dev_id_data = id->data; |
| 360 | |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 361 | /* ack and mask all irqs */ |
| 362 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); |
| 363 | out_be32(mm_gc->regs + GPIO_IMR, 0); |
| 364 | |
Thomas Gleixner | ec775d0 | 2011-03-25 16:45:20 +0100 | [diff] [blame] | 365 | irq_set_handler_data(hwirq, mpc8xxx_gc); |
| 366 | irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 367 | |
| 368 | skip_irq: |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 369 | return; |
| 370 | |
| 371 | err: |
| 372 | pr_err("%s: registration failed with status %d\n", |
| 373 | np->full_name, ret); |
| 374 | kfree(mpc8xxx_gc); |
| 375 | |
| 376 | return; |
| 377 | } |
| 378 | |
| 379 | static int __init mpc8xxx_add_gpiochips(void) |
| 380 | { |
| 381 | struct device_node *np; |
| 382 | |
Anatolij Gustschin | e39d5ef | 2010-08-09 07:58:48 +0200 | [diff] [blame] | 383 | for_each_matching_node(np, mpc8xxx_gpio_ids) |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 384 | mpc8xxx_add_controller(np); |
| 385 | |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 386 | return 0; |
| 387 | } |
| 388 | arch_initcall(mpc8xxx_add_gpiochips); |