blob: 186a68a794a9839fae619170054143143c3ea565 [file] [log] [blame]
Russell Kingd73e60b2008-10-31 13:08:02 +00001/*
2 * linux/arch/arm/mm/copypage-v4wb.c
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/init.h>
Russell King063b0a42008-10-31 15:08:35 +000011#include <linux/highmem.h>
Russell Kingd73e60b2008-10-31 13:08:02 +000012
13/*
Russell King063b0a42008-10-31 15:08:35 +000014 * ARMv4 optimised copy_user_highpage
Russell Kingd73e60b2008-10-31 13:08:02 +000015 *
16 * We flush the destination cache lines just before we write the data into the
17 * corresponding address. Since the Dcache is read-allocate, this removes the
18 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
19 * and merged as appropriate.
20 *
21 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
22 * instruction. If your processor does not supply this, you have to write your
Russell King063b0a42008-10-31 15:08:35 +000023 * own copy_user_highpage that does the right thing.
Russell Kingd73e60b2008-10-31 13:08:02 +000024 */
Russell King063b0a42008-10-31 15:08:35 +000025static void __attribute__((naked))
26v4wb_copy_user_page(void *kto, const void *kfrom)
Russell Kingd73e60b2008-10-31 13:08:02 +000027{
28 asm("\
29 stmfd sp!, {r4, lr} @ 2\n\
30 mov r2, %0 @ 1\n\
31 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
321: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
33 stmia r0!, {r3, r4, ip, lr} @ 4\n\
34 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
35 stmia r0!, {r3, r4, ip, lr} @ 4\n\
36 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
37 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
38 stmia r0!, {r3, r4, ip, lr} @ 4\n\
39 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
40 subs r2, r2, #1 @ 1\n\
41 stmia r0!, {r3, r4, ip, lr} @ 4\n\
42 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\
43 bne 1b @ 1\n\
44 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\
45 ldmfd sp!, {r4, pc} @ 3"
46 :
47 : "I" (PAGE_SIZE / 64));
48}
49
Russell King063b0a42008-10-31 15:08:35 +000050void v4wb_copy_user_highpage(struct page *to, struct page *from,
51 unsigned long vaddr)
52{
53 void *kto, *kfrom;
54
55 kto = kmap_atomic(to, KM_USER0);
56 kfrom = kmap_atomic(from, KM_USER1);
57 v4wb_copy_user_page(kto, kfrom);
58 kunmap_atomic(kfrom, KM_USER1);
59 kunmap_atomic(kto, KM_USER0);
60}
61
Russell Kingd73e60b2008-10-31 13:08:02 +000062/*
63 * ARMv4 optimised clear_user_page
64 *
65 * Same story as above.
66 */
67void __attribute__((naked))
68v4wb_clear_user_page(void *kaddr, unsigned long vaddr)
69{
70 asm("\
71 str lr, [sp, #-4]!\n\
72 mov r1, %0 @ 1\n\
73 mov r2, #0 @ 1\n\
74 mov r3, #0 @ 1\n\
75 mov ip, #0 @ 1\n\
76 mov lr, #0 @ 1\n\
771: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
78 stmia r0!, {r2, r3, ip, lr} @ 4\n\
79 stmia r0!, {r2, r3, ip, lr} @ 4\n\
80 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
81 stmia r0!, {r2, r3, ip, lr} @ 4\n\
82 stmia r0!, {r2, r3, ip, lr} @ 4\n\
83 subs r1, r1, #1 @ 1\n\
84 bne 1b @ 1\n\
85 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\
86 ldr pc, [sp], #4"
87 :
88 : "I" (PAGE_SIZE / 64));
89}
90
91struct cpu_user_fns v4wb_user_fns __initdata = {
92 .cpu_clear_user_page = v4wb_clear_user_page,
Russell King063b0a42008-10-31 15:08:35 +000093 .cpu_copy_user_highpage = v4wb_copy_user_highpage,
Russell Kingd73e60b2008-10-31 13:08:02 +000094};