Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 1 | #ifndef _SPARC64_TLBFLUSH_H |
| 2 | #define _SPARC64_TLBFLUSH_H |
| 3 | |
| 4 | #include <linux/mm.h> |
| 5 | #include <asm/mmu_context.h> |
| 6 | |
| 7 | /* TSB flush operations. */ |
Peter Zijlstra | 90f08e3 | 2011-05-24 17:11:50 -0700 | [diff] [blame] | 8 | |
| 9 | #define TLB_BATCH_NR 192 |
| 10 | |
| 11 | struct tlb_batch { |
| 12 | struct mm_struct *mm; |
| 13 | unsigned long tlb_nr; |
| 14 | unsigned long vaddrs[TLB_BATCH_NR]; |
| 15 | }; |
| 16 | |
Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 17 | extern void flush_tsb_kernel_range(unsigned long start, unsigned long end); |
Peter Zijlstra | 90f08e3 | 2011-05-24 17:11:50 -0700 | [diff] [blame] | 18 | extern void flush_tsb_user(struct tlb_batch *tb); |
Sam Ravnborg | f5e706a | 2008-07-17 21:55:51 -0700 | [diff] [blame] | 19 | |
| 20 | /* TLB flush operations. */ |
| 21 | |
| 22 | extern void flush_tlb_pending(void); |
| 23 | |
| 24 | #define flush_tlb_range(vma,start,end) \ |
| 25 | do { (void)(start); flush_tlb_pending(); } while (0) |
| 26 | #define flush_tlb_page(vma,addr) flush_tlb_pending() |
| 27 | #define flush_tlb_mm(mm) flush_tlb_pending() |
| 28 | |
| 29 | /* Local cpu only. */ |
| 30 | extern void __flush_tlb_all(void); |
| 31 | |
| 32 | extern void __flush_tlb_kernel_range(unsigned long start, unsigned long end); |
| 33 | |
| 34 | #ifndef CONFIG_SMP |
| 35 | |
| 36 | #define flush_tlb_kernel_range(start,end) \ |
| 37 | do { flush_tsb_kernel_range(start,end); \ |
| 38 | __flush_tlb_kernel_range(start,end); \ |
| 39 | } while (0) |
| 40 | |
| 41 | #else /* CONFIG_SMP */ |
| 42 | |
| 43 | extern void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end); |
| 44 | |
| 45 | #define flush_tlb_kernel_range(start, end) \ |
| 46 | do { flush_tsb_kernel_range(start,end); \ |
| 47 | smp_flush_tlb_kernel_range(start, end); \ |
| 48 | } while (0) |
| 49 | |
| 50 | #endif /* ! CONFIG_SMP */ |
| 51 | |
| 52 | #endif /* _SPARC64_TLBFLUSH_H */ |