| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1 | /* |
| Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 2 | * Copyright 2007-2008 Analog Devices Inc. |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 3 | * |
| Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 4 | * Licensed under the GPL-2 or later |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _CDEF_BF52X_H |
| Michael Hennerich | a81501a | 2008-04-24 07:32:41 +0800 | [diff] [blame] | 8 | #define _CDEF_BF52X_H |
| 9 | |
| Michael Hennerich | a81501a | 2008-04-24 07:32:41 +0800 | [diff] [blame] | 10 | #include <asm/blackfin.h> |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 11 | |
| 12 | #include "defBF52x_base.h" |
| 13 | |
| Michael Hennerich | a81501a | 2008-04-24 07:32:41 +0800 | [diff] [blame] | 14 | /* Include core specific register pointer definitions */ |
| Bryan Wu | 639f657 | 2008-08-27 10:51:02 +0800 | [diff] [blame] | 15 | #include <asm/cdef_LPBlackfin.h> |
| Michael Hennerich | a81501a | 2008-04-24 07:32:41 +0800 | [diff] [blame] | 16 | |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 17 | /* ==== begin from cdefBF534.h ==== */ |
| 18 | |
| 19 | /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ |
| 20 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 21 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
| 22 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) |
| 23 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 24 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
| 25 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) |
| 26 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| 27 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) |
| Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 28 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
| 29 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 30 | |
| 31 | |
| 32 | /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ |
| 33 | #define bfin_read_SWRST() bfin_read16(SWRST) |
| 34 | #define bfin_write_SWRST(val) bfin_write16(SWRST, val) |
| 35 | #define bfin_read_SYSCR() bfin_read16(SYSCR) |
| 36 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) |
| 37 | |
| 38 | #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) |
| 39 | #define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) |
| 40 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) |
| 41 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) |
| Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 42 | #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6)) |
| 43 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val) |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 44 | |
| 45 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
| 46 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) |
| 47 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) |
| 48 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) |
| 49 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) |
| 50 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) |
| 51 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) |
| 52 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) |
| 53 | |
| 54 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) |
| 55 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) |
| Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 56 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6)) |
| 57 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val) |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 58 | |
| 59 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) |
| 60 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) |
| Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 61 | #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6)) |
| 62 | #define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val) |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 63 | |
| 64 | /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ |
| 65 | |
| 66 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) |
| 67 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) |
| 68 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) |
| 69 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) |
| 70 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) |
| 71 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) |
| 72 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) |
| 73 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) |
| 74 | #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) |
| 75 | #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) |
| 76 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) |
| 77 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) |
| 78 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) |
| 79 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) |
| 80 | |
| 81 | /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ |
| 82 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) |
| 83 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) |
| 84 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) |
| 85 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) |
| 86 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) |
| 87 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) |
| 88 | |
| 89 | |
| 90 | /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ |
| 91 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) |
| 92 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) |
| 93 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) |
| 94 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) |
| 95 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) |
| 96 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) |
| 97 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) |
| 98 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) |
| 99 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) |
| 100 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) |
| 101 | #define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) |
| 102 | #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) |
| 103 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) |
| 104 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) |
| 105 | |
| 106 | |
| 107 | /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ |
| 108 | #define bfin_read_UART0_THR() bfin_read16(UART0_THR) |
| 109 | #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) |
| 110 | #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) |
| 111 | #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) |
| 112 | #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) |
| 113 | #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) |
| 114 | #define bfin_read_UART0_IER() bfin_read16(UART0_IER) |
| 115 | #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) |
| 116 | #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) |
| 117 | #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) |
| 118 | #define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) |
| 119 | #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) |
| 120 | #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) |
| 121 | #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) |
| 122 | #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) |
| 123 | #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) |
| 124 | #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) |
| 125 | #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) |
| 126 | #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) |
| 127 | #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) |
| 128 | #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) |
| 129 | #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) |
| 130 | #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) |
| 131 | #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) |
| 132 | |
| 133 | |
| 134 | /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ |
| 135 | #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) |
| 136 | #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) |
| 137 | #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) |
| 138 | #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) |
| 139 | #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) |
| 140 | #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) |
| 141 | #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) |
| 142 | #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) |
| 143 | #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) |
| 144 | #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) |
| 145 | #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) |
| 146 | #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) |
| 147 | #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) |
| 148 | #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) |
| 149 | |
| 150 | |
| 151 | /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ |
| 152 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) |
| 153 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) |
| 154 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) |
| 155 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) |
| 156 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) |
| 157 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) |
| 158 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) |
| 159 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) |
| 160 | |
| 161 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) |
| 162 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) |
| 163 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) |
| 164 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) |
| 165 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) |
| 166 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) |
| 167 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) |
| 168 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) |
| 169 | |
| 170 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) |
| 171 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) |
| 172 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) |
| 173 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) |
| 174 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) |
| 175 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) |
| 176 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) |
| 177 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) |
| 178 | |
| 179 | #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) |
| 180 | #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) |
| 181 | #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) |
| 182 | #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) |
| 183 | #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) |
| 184 | #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) |
| 185 | #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) |
| 186 | #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) |
| 187 | |
| 188 | #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) |
| 189 | #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) |
| 190 | #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) |
| 191 | #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) |
| 192 | #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) |
| 193 | #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) |
| 194 | #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) |
| 195 | #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) |
| 196 | |
| 197 | #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) |
| 198 | #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) |
| 199 | #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) |
| 200 | #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) |
| 201 | #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) |
| 202 | #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) |
| 203 | #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) |
| 204 | #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) |
| 205 | |
| 206 | #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) |
| 207 | #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) |
| 208 | #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) |
| 209 | #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) |
| 210 | #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) |
| 211 | #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) |
| 212 | #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) |
| 213 | #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) |
| 214 | |
| 215 | #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) |
| 216 | #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) |
| 217 | #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) |
| 218 | #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) |
| 219 | #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) |
| 220 | #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) |
| 221 | #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) |
| 222 | #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) |
| 223 | |
| 224 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) |
| 225 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) |
| 226 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) |
| 227 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) |
| 228 | #define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) |
| 229 | #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) |
| 230 | |
| 231 | |
| 232 | /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ |
| 233 | #define bfin_read_PORTFIO() bfin_read16(PORTFIO) |
| 234 | #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) |
| 235 | #define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) |
| 236 | #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) |
| 237 | #define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) |
| 238 | #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) |
| 239 | #define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) |
| 240 | #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) |
| 241 | #define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) |
| 242 | #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) |
| 243 | #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) |
| 244 | #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) |
| 245 | #define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) |
| 246 | #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) |
| 247 | #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) |
| 248 | #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) |
| 249 | #define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) |
| 250 | #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) |
| 251 | #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) |
| 252 | #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) |
| 253 | #define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) |
| 254 | #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) |
| 255 | #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) |
| 256 | #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) |
| 257 | #define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) |
| 258 | #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) |
| 259 | #define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) |
| 260 | #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) |
| 261 | #define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) |
| 262 | #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) |
| 263 | #define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) |
| 264 | #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) |
| 265 | #define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) |
| 266 | #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) |
| 267 | |
| 268 | |
| 269 | /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ |
| 270 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) |
| 271 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) |
| 272 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) |
| 273 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) |
| 274 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) |
| 275 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) |
| 276 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) |
| 277 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) |
| 278 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) |
| 279 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) |
| 280 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) |
| 281 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) |
| 282 | #define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32) |
| 283 | #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val) |
| 284 | #define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32) |
| 285 | #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val) |
| 286 | #define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16) |
| 287 | #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val) |
| 288 | #define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16) |
| 289 | #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val) |
| 290 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) |
| 291 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) |
| 292 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) |
| 293 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) |
| 294 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) |
| 295 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) |
| 296 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) |
| 297 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) |
| 298 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) |
| 299 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) |
| 300 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) |
| 301 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) |
| 302 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) |
| 303 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) |
| 304 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) |
| 305 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) |
| 306 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) |
| 307 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) |
| 308 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) |
| 309 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) |
| 310 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) |
| 311 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) |
| 312 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) |
| 313 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) |
| 314 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) |
| 315 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) |
| 316 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) |
| 317 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) |
| 318 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) |
| 319 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) |
| 320 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) |
| 321 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) |
| 322 | |
| 323 | |
| 324 | /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ |
| 325 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) |
| 326 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) |
| 327 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) |
| 328 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) |
| 329 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) |
| 330 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) |
| 331 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) |
| 332 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) |
| 333 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) |
| 334 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) |
| 335 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) |
| 336 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) |
| 337 | #define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32) |
| 338 | #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val) |
| 339 | #define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32) |
| 340 | #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val) |
| 341 | #define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16) |
| 342 | #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val) |
| 343 | #define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16) |
| 344 | #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val) |
| 345 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) |
| 346 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) |
| 347 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) |
| 348 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) |
| 349 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) |
| 350 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) |
| 351 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) |
| 352 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) |
| 353 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) |
| 354 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) |
| 355 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) |
| 356 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) |
| 357 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) |
| 358 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) |
| 359 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) |
| 360 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) |
| 361 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) |
| 362 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) |
| 363 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) |
| 364 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) |
| 365 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) |
| 366 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) |
| 367 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) |
| 368 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) |
| 369 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) |
| 370 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) |
| 371 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) |
| 372 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) |
| 373 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) |
| 374 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) |
| 375 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) |
| 376 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) |
| 377 | |
| 378 | |
| 379 | /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ |
| 380 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) |
| 381 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) |
| 382 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) |
| 383 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) |
| 384 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) |
| 385 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) |
| 386 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) |
| 387 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) |
| 388 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) |
| 389 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) |
| 390 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) |
| 391 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) |
| 392 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) |
| 393 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) |
| 394 | |
| 395 | |
| 396 | /* DMA Traffic Control Registers */ |
| 397 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) |
| 398 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) |
| 399 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) |
| 400 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) |
| 401 | |
| 402 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ |
| 403 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) |
| 404 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val) |
| 405 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) |
| 406 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val) |
| 407 | |
| 408 | /* DMA Controller */ |
| 409 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
| 410 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) |
| 411 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) |
| 412 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) |
| 413 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) |
| 414 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) |
| 415 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) |
| 416 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) |
| 417 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) |
| 418 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) |
| 419 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) |
| 420 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) |
| 421 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) |
| 422 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) |
| 423 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) |
| 424 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) |
| 425 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) |
| 426 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) |
| 427 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) |
| 428 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) |
| 429 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) |
| 430 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) |
| 431 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) |
| 432 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) |
| 433 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) |
| 434 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) |
| 435 | |
| 436 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) |
| 437 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) |
| 438 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) |
| 439 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) |
| 440 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) |
| 441 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) |
| 442 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) |
| 443 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) |
| 444 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) |
| 445 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) |
| 446 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) |
| 447 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) |
| 448 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) |
| 449 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) |
| 450 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) |
| 451 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) |
| 452 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) |
| 453 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) |
| 454 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) |
| 455 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) |
| 456 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) |
| 457 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) |
| 458 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) |
| 459 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) |
| 460 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) |
| 461 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) |
| 462 | |
| 463 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) |
| 464 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) |
| 465 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) |
| 466 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) |
| 467 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) |
| 468 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) |
| 469 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) |
| 470 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) |
| 471 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) |
| 472 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) |
| 473 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) |
| 474 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) |
| 475 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) |
| 476 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) |
| 477 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) |
| 478 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) |
| 479 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) |
| 480 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) |
| 481 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) |
| 482 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) |
| 483 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) |
| 484 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) |
| 485 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) |
| 486 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) |
| 487 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) |
| 488 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) |
| 489 | |
| 490 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) |
| 491 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) |
| 492 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) |
| 493 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) |
| 494 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) |
| 495 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) |
| 496 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) |
| 497 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) |
| 498 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) |
| 499 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) |
| 500 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) |
| 501 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) |
| 502 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) |
| 503 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) |
| 504 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) |
| 505 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) |
| 506 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) |
| 507 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) |
| 508 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) |
| 509 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) |
| 510 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) |
| 511 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) |
| 512 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) |
| 513 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) |
| 514 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) |
| 515 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) |
| 516 | |
| 517 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) |
| 518 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) |
| 519 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) |
| 520 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) |
| 521 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) |
| 522 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) |
| 523 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) |
| 524 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) |
| 525 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) |
| 526 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) |
| 527 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) |
| 528 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) |
| 529 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) |
| 530 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) |
| 531 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) |
| 532 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) |
| 533 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) |
| 534 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) |
| 535 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) |
| 536 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) |
| 537 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) |
| 538 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) |
| 539 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) |
| 540 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) |
| 541 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) |
| 542 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) |
| 543 | |
| 544 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) |
| 545 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) |
| 546 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) |
| 547 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) |
| 548 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) |
| 549 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) |
| 550 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) |
| 551 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) |
| 552 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) |
| 553 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) |
| 554 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) |
| 555 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) |
| 556 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) |
| 557 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) |
| 558 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) |
| 559 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) |
| 560 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) |
| 561 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) |
| 562 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) |
| 563 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) |
| 564 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) |
| 565 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) |
| 566 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) |
| 567 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) |
| 568 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) |
| 569 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) |
| 570 | |
| 571 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) |
| 572 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) |
| 573 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) |
| 574 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) |
| 575 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) |
| 576 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) |
| 577 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) |
| 578 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) |
| 579 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) |
| 580 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) |
| 581 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) |
| 582 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) |
| 583 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) |
| 584 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) |
| 585 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) |
| 586 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) |
| 587 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) |
| 588 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) |
| 589 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) |
| 590 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) |
| 591 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) |
| 592 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) |
| 593 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) |
| 594 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) |
| 595 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) |
| 596 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) |
| 597 | |
| 598 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) |
| 599 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) |
| 600 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) |
| 601 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) |
| 602 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) |
| 603 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) |
| 604 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) |
| 605 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) |
| 606 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) |
| 607 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) |
| 608 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) |
| 609 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) |
| 610 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) |
| 611 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) |
| 612 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) |
| 613 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) |
| 614 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) |
| 615 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) |
| 616 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) |
| 617 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) |
| 618 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) |
| 619 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) |
| 620 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) |
| 621 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) |
| 622 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) |
| 623 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) |
| 624 | |
| 625 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) |
| 626 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) |
| 627 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) |
| 628 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) |
| 629 | #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) |
| 630 | #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) |
| 631 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) |
| 632 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) |
| 633 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) |
| 634 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) |
| 635 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) |
| 636 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) |
| 637 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) |
| 638 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) |
| 639 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) |
| 640 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) |
| 641 | #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) |
| 642 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) |
| 643 | #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) |
| 644 | #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) |
| 645 | #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) |
| 646 | #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) |
| 647 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) |
| 648 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) |
| 649 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) |
| 650 | #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) |
| 651 | |
| 652 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) |
| 653 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) |
| 654 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) |
| 655 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) |
| 656 | #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) |
| 657 | #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) |
| 658 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) |
| 659 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) |
| 660 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) |
| 661 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) |
| 662 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) |
| 663 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) |
| 664 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) |
| 665 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) |
| 666 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) |
| 667 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) |
| 668 | #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) |
| 669 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) |
| 670 | #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) |
| 671 | #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) |
| 672 | #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) |
| 673 | #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) |
| 674 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) |
| 675 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) |
| 676 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) |
| 677 | #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) |
| 678 | |
| 679 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) |
| 680 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) |
| 681 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) |
| 682 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) |
| 683 | #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) |
| 684 | #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) |
| 685 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) |
| 686 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) |
| 687 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) |
| 688 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) |
| 689 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) |
| 690 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) |
| 691 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) |
| 692 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) |
| 693 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) |
| 694 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) |
| 695 | #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) |
| 696 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) |
| 697 | #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) |
| 698 | #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) |
| 699 | #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) |
| 700 | #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) |
| 701 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) |
| 702 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) |
| 703 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) |
| 704 | #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) |
| 705 | |
| 706 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) |
| 707 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) |
| 708 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) |
| 709 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) |
| 710 | #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) |
| 711 | #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) |
| 712 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) |
| 713 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) |
| 714 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) |
| 715 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) |
| 716 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) |
| 717 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) |
| 718 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) |
| 719 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) |
| 720 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) |
| 721 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) |
| 722 | #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) |
| 723 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) |
| 724 | #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) |
| 725 | #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) |
| 726 | #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) |
| 727 | #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) |
| 728 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) |
| 729 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) |
| 730 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) |
| 731 | #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) |
| 732 | |
| 733 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) |
| 734 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) |
| 735 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) |
| 736 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) |
| 737 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) |
| 738 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) |
| 739 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) |
| 740 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) |
| 741 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) |
| 742 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) |
| 743 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) |
| 744 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) |
| 745 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) |
| 746 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) |
| 747 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) |
| 748 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) |
| 749 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) |
| 750 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) |
| 751 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) |
| 752 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) |
| 753 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) |
| 754 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) |
| 755 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) |
| 756 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) |
| 757 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) |
| 758 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) |
| 759 | |
| 760 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) |
| 761 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) |
| 762 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) |
| 763 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) |
| 764 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) |
| 765 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) |
| 766 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) |
| 767 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) |
| 768 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) |
| 769 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) |
| 770 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) |
| 771 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) |
| 772 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) |
| 773 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) |
| 774 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) |
| 775 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) |
| 776 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) |
| 777 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) |
| 778 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) |
| 779 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) |
| 780 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) |
| 781 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) |
| 782 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) |
| 783 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) |
| 784 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) |
| 785 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) |
| 786 | |
| 787 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) |
| 788 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) |
| 789 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) |
| 790 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) |
| 791 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) |
| 792 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) |
| 793 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) |
| 794 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) |
| 795 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) |
| 796 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) |
| 797 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) |
| 798 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) |
| 799 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) |
| 800 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) |
| 801 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) |
| 802 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) |
| 803 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) |
| 804 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) |
| 805 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) |
| 806 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) |
| 807 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) |
| 808 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) |
| 809 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) |
| 810 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) |
| 811 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) |
| 812 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) |
| 813 | |
| 814 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) |
| 815 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) |
| 816 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) |
| 817 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) |
| 818 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) |
| 819 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) |
| 820 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) |
| 821 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) |
| 822 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) |
| 823 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) |
| 824 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) |
| 825 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) |
| 826 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) |
| 827 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) |
| 828 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) |
| 829 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) |
| 830 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) |
| 831 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) |
| 832 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) |
| 833 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) |
| 834 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) |
| 835 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) |
| 836 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) |
| 837 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) |
| 838 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) |
| 839 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) |
| 840 | |
| 841 | |
| 842 | /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ |
| 843 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) |
| 844 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) |
| 845 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) |
| 846 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) |
| 847 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) |
| 848 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) |
| 849 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) |
| 850 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) |
| 851 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) |
| 852 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) |
| 853 | |
| 854 | |
| 855 | /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 856 | |
| 857 | /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ |
| 858 | #define bfin_read_PORTGIO() bfin_read16(PORTGIO) |
| 859 | #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) |
| 860 | #define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) |
| 861 | #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) |
| 862 | #define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) |
| 863 | #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) |
| 864 | #define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) |
| 865 | #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) |
| 866 | #define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) |
| 867 | #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) |
| 868 | #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) |
| 869 | #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) |
| 870 | #define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) |
| 871 | #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) |
| 872 | #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) |
| 873 | #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) |
| 874 | #define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) |
| 875 | #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) |
| 876 | #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) |
| 877 | #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) |
| 878 | #define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) |
| 879 | #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) |
| 880 | #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) |
| 881 | #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) |
| 882 | #define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) |
| 883 | #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) |
| 884 | #define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) |
| 885 | #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) |
| 886 | #define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) |
| 887 | #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) |
| 888 | #define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) |
| 889 | #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) |
| 890 | #define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) |
| 891 | #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) |
| 892 | |
| 893 | |
| 894 | /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ |
| 895 | #define bfin_read_PORTHIO() bfin_read16(PORTHIO) |
| 896 | #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) |
| 897 | #define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) |
| 898 | #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) |
| 899 | #define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) |
| 900 | #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) |
| 901 | #define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) |
| 902 | #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) |
| 903 | #define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) |
| 904 | #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) |
| 905 | #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) |
| 906 | #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) |
| 907 | #define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) |
| 908 | #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) |
| 909 | #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) |
| 910 | #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) |
| 911 | #define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) |
| 912 | #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) |
| 913 | #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) |
| 914 | #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) |
| 915 | #define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) |
| 916 | #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) |
| 917 | #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) |
| 918 | #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) |
| 919 | #define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) |
| 920 | #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) |
| 921 | #define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) |
| 922 | #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) |
| 923 | #define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) |
| 924 | #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) |
| 925 | #define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) |
| 926 | #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) |
| 927 | #define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) |
| 928 | #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) |
| 929 | |
| 930 | |
| 931 | /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ |
| 932 | #define bfin_read_UART1_THR() bfin_read16(UART1_THR) |
| 933 | #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) |
| 934 | #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) |
| 935 | #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) |
| 936 | #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) |
| 937 | #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) |
| 938 | #define bfin_read_UART1_IER() bfin_read16(UART1_IER) |
| 939 | #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) |
| 940 | #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) |
| 941 | #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) |
| 942 | #define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) |
| 943 | #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) |
| 944 | #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) |
| 945 | #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) |
| 946 | #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) |
| 947 | #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) |
| 948 | #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) |
| 949 | #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) |
| 950 | #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) |
| 951 | #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) |
| 952 | #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) |
| 953 | #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) |
| 954 | #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) |
| 955 | #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) |
| 956 | |
| 957 | /* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */ |
| 958 | |
| 959 | /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ |
| 960 | #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) |
| 961 | #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) |
| 962 | #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) |
| 963 | #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) |
| 964 | #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) |
| 965 | #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) |
| 966 | #define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) |
| 967 | #define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) |
| 968 | |
| 969 | |
| 970 | /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */ |
| 971 | #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) |
| 972 | #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) |
| 973 | #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) |
| 974 | #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) |
| 975 | #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) |
| 976 | #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) |
| 977 | #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) |
| 978 | #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) |
| 979 | #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) |
| 980 | #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) |
| 981 | #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) |
| 982 | #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) |
| 983 | #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) |
| 984 | #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) |
| 985 | |
| 986 | #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) |
| 987 | #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) |
| 988 | #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) |
| 989 | #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) |
| 990 | #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) |
| 991 | #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) |
| 992 | #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) |
| 993 | #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) |
| 994 | #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) |
| 995 | #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) |
| 996 | #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) |
| 997 | #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) |
| 998 | #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) |
| 999 | #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) |
| 1000 | |
| 1001 | /* ==== end from cdefBF534.h ==== */ |
| 1002 | |
| 1003 | /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ |
| 1004 | |
| 1005 | #define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) |
| 1006 | #define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) |
| 1007 | #define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) |
| 1008 | #define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) |
| 1009 | #define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) |
| 1010 | #define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) |
| 1011 | |
| 1012 | #define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) |
| 1013 | #define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) |
| 1014 | #define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) |
| 1015 | #define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) |
| 1016 | #define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) |
| 1017 | #define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) |
| 1018 | #define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) |
| 1019 | #define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) |
| 1020 | #define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) |
| 1021 | #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) |
| 1022 | #define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) |
| 1023 | #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) |
| 1024 | #define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS) |
| 1025 | #define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val) |
| 1026 | #define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS) |
| 1027 | #define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val) |
| 1028 | #define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS) |
| 1029 | #define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val) |
| 1030 | #define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE) |
| 1031 | #define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val) |
| 1032 | #define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW) |
| 1033 | #define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val) |
| 1034 | #define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS) |
| 1035 | #define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val) |
| 1036 | |
| 1037 | /* HOST Port Registers */ |
| 1038 | |
| 1039 | #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) |
| 1040 | #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) |
| 1041 | #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) |
| 1042 | #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) |
| 1043 | #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) |
| 1044 | #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) |
| 1045 | |
| 1046 | /* Counter Registers */ |
| 1047 | |
| 1048 | #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) |
| 1049 | #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) |
| 1050 | #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) |
| 1051 | #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) |
| 1052 | #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) |
| 1053 | #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) |
| 1054 | #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) |
| 1055 | #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) |
| 1056 | #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) |
| 1057 | #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) |
| 1058 | #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) |
| 1059 | #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) |
| 1060 | #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) |
| 1061 | #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) |
| 1062 | #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) |
| 1063 | #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) |
| 1064 | |
| 1065 | /* OTP/FUSE Registers */ |
| 1066 | |
| 1067 | #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) |
| 1068 | #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) |
| 1069 | #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) |
| 1070 | #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) |
| 1071 | #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) |
| 1072 | #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) |
| 1073 | #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) |
| 1074 | #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) |
| 1075 | |
| 1076 | /* Security Registers */ |
| 1077 | |
| 1078 | #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) |
| 1079 | #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) |
| 1080 | #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) |
| 1081 | #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) |
| 1082 | #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) |
| 1083 | #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) |
| 1084 | |
| 1085 | /* OTP Read/Write Data Buffer Registers */ |
| 1086 | |
| 1087 | #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) |
| 1088 | #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) |
| 1089 | #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) |
| 1090 | #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) |
| 1091 | #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) |
| 1092 | #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) |
| 1093 | #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) |
| 1094 | #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) |
| 1095 | |
| 1096 | /* NFC Registers */ |
| 1097 | |
| 1098 | #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) |
| 1099 | #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) |
| 1100 | #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) |
| 1101 | #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) |
| 1102 | #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) |
| 1103 | #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) |
| 1104 | #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) |
| 1105 | #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) |
| 1106 | #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) |
| 1107 | #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) |
| 1108 | #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) |
| 1109 | #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) |
| 1110 | #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) |
| 1111 | #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) |
| 1112 | #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) |
| 1113 | #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) |
| 1114 | #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) |
| 1115 | #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) |
| 1116 | #define bfin_read_NFC_RST() bfin_read16(NFC_RST) |
| 1117 | #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) |
| 1118 | #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) |
| 1119 | #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) |
| 1120 | #define bfin_read_NFC_READ() bfin_read16(NFC_READ) |
| 1121 | #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) |
| 1122 | #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) |
| 1123 | #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) |
| 1124 | #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) |
| 1125 | #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) |
| 1126 | #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) |
| 1127 | #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) |
| 1128 | #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) |
| 1129 | #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) |
| 1130 | |
| Mike Frysinger | 53442e1 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1131 | /* These need to be last due to the cdef/linux inter-dependencies */ |
| Mike Frysinger | b607057 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1132 | #include <asm/irq.h> |
| Mike Frysinger | 53442e1 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1133 | |
| 1134 | /* Writing to PLL_CTL initiates a PLL relock sequence. */ |
| 1135 | static __inline__ void bfin_write_PLL_CTL(unsigned int val) |
| 1136 | { |
| 1137 | unsigned long flags, iwr0, iwr1; |
| 1138 | |
| 1139 | if (val == bfin_read_PLL_CTL()) |
| 1140 | return; |
| 1141 | |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1142 | local_irq_save_hw(flags); |
| Mike Frysinger | 53442e1 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1143 | /* Enable the PLL Wakeup bit in SIC IWR */ |
| 1144 | iwr0 = bfin_read32(SIC_IWR0); |
| 1145 | iwr1 = bfin_read32(SIC_IWR1); |
| 1146 | /* Only allow PPL Wakeup) */ |
| 1147 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); |
| 1148 | bfin_write32(SIC_IWR1, 0); |
| 1149 | |
| 1150 | bfin_write16(PLL_CTL, val); |
| 1151 | SSYNC(); |
| 1152 | asm("IDLE;"); |
| 1153 | |
| 1154 | bfin_write32(SIC_IWR0, iwr0); |
| 1155 | bfin_write32(SIC_IWR1, iwr1); |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1156 | local_irq_restore_hw(flags); |
| Mike Frysinger | 53442e1 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1157 | } |
| 1158 | |
| 1159 | /* Writing to VR_CTL initiates a PLL relock sequence. */ |
| 1160 | static __inline__ void bfin_write_VR_CTL(unsigned int val) |
| 1161 | { |
| 1162 | unsigned long flags, iwr0, iwr1; |
| 1163 | |
| 1164 | if (val == bfin_read_VR_CTL()) |
| 1165 | return; |
| 1166 | |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1167 | local_irq_save_hw(flags); |
| Mike Frysinger | 53442e1 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1168 | /* Enable the PLL Wakeup bit in SIC IWR */ |
| 1169 | iwr0 = bfin_read32(SIC_IWR0); |
| 1170 | iwr1 = bfin_read32(SIC_IWR1); |
| 1171 | /* Only allow PPL Wakeup) */ |
| 1172 | bfin_write32(SIC_IWR0, IWR_ENABLE(0)); |
| 1173 | bfin_write32(SIC_IWR1, 0); |
| 1174 | |
| 1175 | bfin_write16(VR_CTL, val); |
| 1176 | SSYNC(); |
| 1177 | asm("IDLE;"); |
| 1178 | |
| 1179 | bfin_write32(SIC_IWR0, iwr0); |
| 1180 | bfin_write32(SIC_IWR1, iwr1); |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1181 | local_irq_restore_hw(flags); |
| Mike Frysinger | 53442e1 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1182 | } |
| 1183 | |
| Bryan Wu | 19381f0 | 2007-05-21 18:09:31 +0800 | [diff] [blame] | 1184 | #endif /* _CDEF_BF52X_H */ |