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gerrit-public.fairphone.software / kernel / msm / 0bc2ecb6e5b7e61113e48336b818051b094006a9 / . / arch / arm / boot / dts / tegra20.dtsi
blob: 3da7afd45322ba288de7c36ac85923c53aed05a9 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
7 intc: interrupt-controller@50041000 {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]8 compatible = "arm,cortex-a9-gic";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]9 interrupt-controller;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]10 #interrupt-cells = <3>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]11 reg = < 0x50041000 0x1000 >,
12 < 0x50040100 0x0100 >;
13 };
14
15 i2c@7000c000 {
16 #address-cells = <1>;
17 #size-cells = <0>;
18 compatible = "nvidia,tegra20-i2c";
19 reg = <0x7000C000 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]20 interrupts = < 0 38 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]21 };
22
23 i2c@7000c400 {
24 #address-cells = <1>;
25 #size-cells = <0>;
26 compatible = "nvidia,tegra20-i2c";
27 reg = <0x7000C400 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]28 interrupts = < 0 84 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]29 };
30
31 i2c@7000c500 {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 compatible = "nvidia,tegra20-i2c";
35 reg = <0x7000C500 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]36 interrupts = < 0 92 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]37 };
38
39 i2c@7000d000 {
40 #address-cells = <1>;
41 #size-cells = <0>;
Stephen Warren0bc2ecb2011-12-17 23:29:31 -0700[diff] [blame^]42 compatible = "nvidia,tegra20-i2c-dvc";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]43 reg = <0x7000D000 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]44 interrupts = < 0 53 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]45 };
46
47 i2s@70002800 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]48 compatible = "nvidia,tegra20-i2s";
49 reg = <0x70002800 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]50 interrupts = < 0 13 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]51 dma-channel = < 2 >;
52 };
53
54 i2s@70002a00 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]55 compatible = "nvidia,tegra20-i2s";
56 reg = <0x70002a00 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]57 interrupts = < 0 3 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]58 dma-channel = < 1 >;
59 };
60
61 das@70000c00 {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]62 compatible = "nvidia,tegra20-das";
63 reg = <0x70000c00 0x80>;
64 };
65
66 gpio: gpio@6000d000 {
67 compatible = "nvidia,tegra20-gpio";
68 reg = < 0x6000d000 0x1000 >;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]69 interrupts = < 0 32 0x04
70 0 33 0x04
71 0 34 0x04
72 0 35 0x04
73 0 55 0x04
74 0 87 0x04
75 0 89 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]76 #gpio-cells = <2>;
77 gpio-controller;
78 };
79
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]80 pinmux: pinmux@70000000 {
81 compatible = "nvidia,tegra20-pinmux";
82 reg = < 0x70000014 0x10 /* Tri-state registers */
83 0x70000080 0x20 /* Mux registers */
84 0x700000a0 0x14 /* Pull-up/down registers */
85 0x70000868 0xa8 >; /* Pad control registers */
86 };
87
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]88 serial@70006000 {
89 compatible = "nvidia,tegra20-uart";
90 reg = <0x70006000 0x40>;
91 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]92 interrupts = < 0 36 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]93 };
94
95 serial@70006040 {
96 compatible = "nvidia,tegra20-uart";
97 reg = <0x70006040 0x40>;
98 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]99 interrupts = < 0 37 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]100 };
101
102 serial@70006200 {
103 compatible = "nvidia,tegra20-uart";
104 reg = <0x70006200 0x100>;
105 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]106 interrupts = < 0 46 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]107 };
108
109 serial@70006300 {
110 compatible = "nvidia,tegra20-uart";
111 reg = <0x70006300 0x100>;
112 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]113 interrupts = < 0 90 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]114 };
115
116 serial@70006400 {
117 compatible = "nvidia,tegra20-uart";
118 reg = <0x70006400 0x100>;
119 reg-shift = <2>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]120 interrupts = < 0 91 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]121 };
122
123 sdhci@c8000000 {
124 compatible = "nvidia,tegra20-sdhci";
125 reg = <0xc8000000 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]126 interrupts = < 0 14 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]127 };
128
129 sdhci@c8000200 {
130 compatible = "nvidia,tegra20-sdhci";
131 reg = <0xc8000200 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]132 interrupts = < 0 15 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]133 };
134
135 sdhci@c8000400 {
136 compatible = "nvidia,tegra20-sdhci";
137 reg = <0xc8000400 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]138 interrupts = < 0 19 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]139 };
140
141 sdhci@c8000600 {
142 compatible = "nvidia,tegra20-sdhci";
143 reg = <0xc8000600 0x200>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]144 interrupts = < 0 31 0x04 >;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]145 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]146
147 usb@c5000000 {
148 compatible = "nvidia,tegra20-ehci", "usb-ehci";
149 reg = <0xc5000000 0x4000>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]150 interrupts = < 0 20 0x04 >;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]151 phy_type = "utmi";
152 };
153
154 usb@c5004000 {
155 compatible = "nvidia,tegra20-ehci", "usb-ehci";
156 reg = <0xc5004000 0x4000>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]157 interrupts = < 0 21 0x04 >;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]158 phy_type = "ulpi";
159 };
160
161 usb@c5008000 {
162 compatible = "nvidia,tegra20-ehci", "usb-ehci";
163 reg = <0xc5008000 0x4000>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]164 interrupts = < 0 97 0x04 >;
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]165 phy_type = "utmi";
166 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]167};
168