blob: f535812e40573d69d8c057495563560ecb65f288 [file] [log] [blame]
Dave Airlie414ed532005-08-16 20:43:16 +10001/* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
2 *
3 * Copyright (C) The Weather Channel, Inc. 2002.
4 * Copyright (C) 2004 Nicolai Haehnle.
5 * All Rights Reserved.
6 *
7 * The Weather Channel (TM) funded Tungsten Graphics to develop the
8 * initial release of the Radeon 8500 driver under the XFree86 license.
9 * This notice must be preserved.
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the next
19 * paragraph) shall be included in all copies or substantial portions of the
20 * Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
26 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 *
30 * Authors:
31 * Nicolai Haehnle <prefect_@gmx.net>
32 */
33
34#include "drmP.h"
35#include "drm.h"
36#include "radeon_drm.h"
37#include "radeon_drv.h"
38#include "r300_reg.h"
39
Dave Airlie414ed532005-08-16 20:43:16 +100040#define R300_SIMULTANEOUS_CLIPRECTS 4
41
42/* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
43 */
44static const int r300_cliprect_cntl[4] = {
45 0xAAAA,
46 0xEEEE,
47 0xFEFE,
48 0xFFFE
49};
50
Dave Airlie414ed532005-08-16 20:43:16 +100051/**
52 * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
53 * buffer, starting with index n.
54 */
Dave Airlied985c102006-01-02 21:32:48 +110055static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
56 drm_radeon_kcmd_buffer_t *cmdbuf, int n)
Dave Airlie414ed532005-08-16 20:43:16 +100057{
Dave Airliec60ce622007-07-11 15:27:12 +100058 struct drm_clip_rect box;
Dave Airlie414ed532005-08-16 20:43:16 +100059 int nr;
60 int i;
61 RING_LOCALS;
62
63 nr = cmdbuf->nbox - n;
64 if (nr > R300_SIMULTANEOUS_CLIPRECTS)
65 nr = R300_SIMULTANEOUS_CLIPRECTS;
66
67 DRM_DEBUG("%i cliprects\n", nr);
68
69 if (nr) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +100070 BEGIN_RING(6 + nr * 2);
71 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
Dave Airlie414ed532005-08-16 20:43:16 +100072
Dave Airlieb5e89ed2005-09-25 14:28:13 +100073 for (i = 0; i < nr; ++i) {
74 if (DRM_COPY_FROM_USER_UNCHECKED
75 (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
Dave Airlie414ed532005-08-16 20:43:16 +100076 DRM_ERROR("copy cliprect faulted\n");
Eric Anholt20caafa2007-08-25 19:22:43 +100077 return -EFAULT;
Dave Airlie414ed532005-08-16 20:43:16 +100078 }
79
Dave Airlie3d5e2c12008-02-07 15:01:05 +100080 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
81 box.x1 = (box.x1) &
82 R300_CLIPRECT_MASK;
83 box.y1 = (box.y1) &
84 R300_CLIPRECT_MASK;
85 box.x2 = (box.x2) &
86 R300_CLIPRECT_MASK;
87 box.y2 = (box.y2) &
88 R300_CLIPRECT_MASK;
89 } else {
90 box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) &
91 R300_CLIPRECT_MASK;
92 box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) &
93 R300_CLIPRECT_MASK;
94 box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) &
95 R300_CLIPRECT_MASK;
96 box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) &
97 R300_CLIPRECT_MASK;
Dave Airlie414ed532005-08-16 20:43:16 +100098
Dave Airlie3d5e2c12008-02-07 15:01:05 +100099 }
Dave Airlie414ed532005-08-16 20:43:16 +1000100 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000101 (box.y1 << R300_CLIPRECT_Y_SHIFT));
Dave Airlie414ed532005-08-16 20:43:16 +1000102 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000103 (box.y2 << R300_CLIPRECT_Y_SHIFT));
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000104
Dave Airlie414ed532005-08-16 20:43:16 +1000105 }
106
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000107 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
Dave Airlie414ed532005-08-16 20:43:16 +1000108
109 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000110 * client might be able to trample over memory.
111 * The impact should be very limited, but I'd rather be safe than
112 * sorry.
113 */
114 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
115 OUT_RING(0);
116 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
Dave Airlie414ed532005-08-16 20:43:16 +1000117 ADVANCE_RING();
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000118 } else {
Dave Airlie414ed532005-08-16 20:43:16 +1000119 /* Why we allow zero cliprect rendering:
120 * There are some commands in a command buffer that must be submitted
121 * even when there are no cliprects, e.g. DMA buffer discard
122 * or state setting (though state setting could be avoided by
123 * simulating a loss of context).
124 *
125 * Now since the cmdbuf interface is so chaotic right now (and is
126 * bound to remain that way for a bit until things settle down),
127 * it is basically impossible to filter out the commands that are
128 * necessary and those that aren't.
129 *
130 * So I choose the safe way and don't do any filtering at all;
131 * instead, I simply set up the engine so that all rendering
132 * can't produce any fragments.
133 */
134 BEGIN_RING(2);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000135 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0);
Dave Airlie414ed532005-08-16 20:43:16 +1000136 ADVANCE_RING();
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000137 }
Dave Airlie414ed532005-08-16 20:43:16 +1000138
139 return 0;
140}
141
Dave Airlieb3a83632005-09-30 18:37:36 +1000142static u8 r300_reg_flags[0x10000 >> 2];
Dave Airlie414ed532005-08-16 20:43:16 +1000143
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000144void r300_init_reg_flags(struct drm_device *dev)
Dave Airlie414ed532005-08-16 20:43:16 +1000145{
146 int i;
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000147 drm_radeon_private_t *dev_priv = dev->dev_private;
148
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000149 memset(r300_reg_flags, 0, 0x10000 >> 2);
150#define ADD_RANGE_MARK(reg, count,mark) \
Dave Airlie414ed532005-08-16 20:43:16 +1000151 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
152 r300_reg_flags[i]|=(mark);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000153
154#define MARK_SAFE 1
155#define MARK_CHECK_OFFSET 2
156
157#define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
Dave Airlie414ed532005-08-16 20:43:16 +1000158
159 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
160 ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000161 ADD_RANGE(R300_VAP_CNTL, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000162 ADD_RANGE(R300_SE_VTE_CNTL, 2);
163 ADD_RANGE(0x2134, 2);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000164 ADD_RANGE(R300_VAP_CNTL_STATUS, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000165 ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
166 ADD_RANGE(0x21DC, 1);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000167 ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
168 ADD_RANGE(R300_VAP_CLIP_X_0, 4);
169 ADD_RANGE(R300_VAP_PVS_WAITIDLE, 1);
170 ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000171 ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
172 ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
173 ADD_RANGE(R300_GB_ENABLE, 1);
174 ADD_RANGE(R300_GB_MSPOS0, 5);
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100175 ADD_RANGE(R300_TX_CNTL, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000176 ADD_RANGE(R300_TX_ENABLE, 1);
177 ADD_RANGE(0x4200, 4);
178 ADD_RANGE(0x4214, 1);
179 ADD_RANGE(R300_RE_POINTSIZE, 1);
180 ADD_RANGE(0x4230, 3);
181 ADD_RANGE(R300_RE_LINE_CNT, 1);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000182 ADD_RANGE(R300_RE_UNK4238, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000183 ADD_RANGE(0x4260, 3);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000184 ADD_RANGE(R300_RE_SHADE, 4);
185 ADD_RANGE(R300_RE_POLYGON_MODE, 5);
186 ADD_RANGE(R300_RE_ZBIAS_CNTL, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000187 ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000188 ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000189 ADD_RANGE(R300_RE_CULL_CNTL, 1);
190 ADD_RANGE(0x42C0, 2);
191 ADD_RANGE(R300_RS_CNTL_0, 2);
192 ADD_RANGE(R300_RS_INTERP_0, 8);
193 ADD_RANGE(R300_RS_ROUTE_0, 8);
194 ADD_RANGE(0x43A4, 2);
195 ADD_RANGE(0x43E8, 1);
196 ADD_RANGE(R300_PFS_CNTL_0, 3);
197 ADD_RANGE(R300_PFS_NODE_0, 4);
198 ADD_RANGE(R300_PFS_TEXI_0, 64);
199 ADD_RANGE(0x46A4, 5);
200 ADD_RANGE(R300_PFS_INSTR0_0, 64);
201 ADD_RANGE(R300_PFS_INSTR1_0, 64);
202 ADD_RANGE(R300_PFS_INSTR2_0, 64);
203 ADD_RANGE(R300_PFS_INSTR3_0, 64);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000204 ADD_RANGE(R300_RE_FOG_STATE, 1);
205 ADD_RANGE(R300_FOG_COLOR_R, 3);
Dave Airlie414ed532005-08-16 20:43:16 +1000206 ADD_RANGE(R300_PP_ALPHA_TEST, 2);
207 ADD_RANGE(0x4BD8, 1);
208 ADD_RANGE(R300_PFS_PARAM_0_X, 64);
209 ADD_RANGE(0x4E00, 1);
210 ADD_RANGE(R300_RB3D_CBLEND, 2);
211 ADD_RANGE(R300_RB3D_COLORMASK, 1);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000212 ADD_RANGE(R300_RB3D_BLEND_COLOR, 3);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000213 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
Dave Airlie414ed532005-08-16 20:43:16 +1000214 ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
215 ADD_RANGE(0x4E50, 9);
216 ADD_RANGE(0x4E88, 1);
217 ADD_RANGE(0x4EA0, 2);
218 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000219 ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000220 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
221 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000222 ADD_RANGE(0x4F28, 1);
223 ADD_RANGE(0x4F30, 2);
224 ADD_RANGE(0x4F44, 1);
225 ADD_RANGE(0x4F54, 1);
226
227 ADD_RANGE(R300_TX_FILTER_0, 16);
Dave Airlie45f17102006-03-19 19:12:10 +1100228 ADD_RANGE(R300_TX_FILTER1_0, 16);
Dave Airlie414ed532005-08-16 20:43:16 +1000229 ADD_RANGE(R300_TX_SIZE_0, 16);
230 ADD_RANGE(R300_TX_FORMAT_0, 16);
Dave Airlied985c102006-01-02 21:32:48 +1100231 ADD_RANGE(R300_TX_PITCH_0, 16);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000232 /* Texture offset is dangerous and needs more checking */
Dave Airlie414ed532005-08-16 20:43:16 +1000233 ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
Dave Airlie45f17102006-03-19 19:12:10 +1100234 ADD_RANGE(R300_TX_CHROMA_KEY_0, 16);
Dave Airlie414ed532005-08-16 20:43:16 +1000235 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
236
237 /* Sporadic registers used as primitives are emitted */
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000238 ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000239 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
240 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
241 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
242
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000243 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
244 ADD_RANGE(0x4074, 16);
245 }
Dave Airlie414ed532005-08-16 20:43:16 +1000246}
247
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000248static __inline__ int r300_check_range(unsigned reg, int count)
Dave Airlie414ed532005-08-16 20:43:16 +1000249{
250 int i;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000251 if (reg & ~0xffff)
252 return -1;
253 for (i = (reg >> 2); i < (reg >> 2) + count; i++)
254 if (r300_reg_flags[i] != MARK_SAFE)
255 return 1;
Dave Airlie414ed532005-08-16 20:43:16 +1000256 return 0;
257}
258
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000259static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
260 dev_priv,
Dave Airlieb3a83632005-09-30 18:37:36 +1000261 drm_radeon_kcmd_buffer_t
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000262 * cmdbuf,
263 drm_r300_cmd_header_t
264 header)
Dave Airlie414ed532005-08-16 20:43:16 +1000265{
266 int reg;
267 int sz;
268 int i;
269 int values[64];
270 RING_LOCALS;
271
272 sz = header.packet0.count;
273 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000274
275 if ((sz > 64) || (sz < 0)) {
276 DRM_ERROR
277 ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
278 reg, sz);
Eric Anholt20caafa2007-08-25 19:22:43 +1000279 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000280 }
281 for (i = 0; i < sz; i++) {
Dave Airlieb3a83632005-09-30 18:37:36 +1000282 values[i] = ((int *)cmdbuf->buf)[i];
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000283 switch (r300_reg_flags[(reg >> 2) + i]) {
Dave Airlie414ed532005-08-16 20:43:16 +1000284 case MARK_SAFE:
285 break;
286 case MARK_CHECK_OFFSET:
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +1100287 if (!radeon_check_offset(dev_priv, (u32) values[i])) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000288 DRM_ERROR
289 ("Offset failed range check (reg=%04x sz=%d)\n",
290 reg, sz);
Eric Anholt20caafa2007-08-25 19:22:43 +1000291 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000292 }
Dave Airlie414ed532005-08-16 20:43:16 +1000293 break;
294 default:
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000295 DRM_ERROR("Register %04x failed check as flag=%02x\n",
296 reg + i * 4, r300_reg_flags[(reg >> 2) + i]);
Eric Anholt20caafa2007-08-25 19:22:43 +1000297 return -EINVAL;
Dave Airlie414ed532005-08-16 20:43:16 +1000298 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000299 }
300
301 BEGIN_RING(1 + sz);
302 OUT_RING(CP_PACKET0(reg, sz - 1));
303 OUT_RING_TABLE(values, sz);
Dave Airlie414ed532005-08-16 20:43:16 +1000304 ADVANCE_RING();
305
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000306 cmdbuf->buf += sz * 4;
307 cmdbuf->bufsz -= sz * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000308
309 return 0;
310}
311
312/**
313 * Emits a packet0 setting arbitrary registers.
314 * Called by r300_do_cp_cmdbuf.
315 *
316 * Note that checks are performed on contents and addresses of the registers
317 */
Dave Airlied985c102006-01-02 21:32:48 +1100318static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
319 drm_radeon_kcmd_buffer_t *cmdbuf,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000320 drm_r300_cmd_header_t header)
Dave Airlie414ed532005-08-16 20:43:16 +1000321{
322 int reg;
323 int sz;
324 RING_LOCALS;
325
326 sz = header.packet0.count;
327 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
328
329 if (!sz)
330 return 0;
331
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000332 if (sz * 4 > cmdbuf->bufsz)
Eric Anholt20caafa2007-08-25 19:22:43 +1000333 return -EINVAL;
Dave Airlie414ed532005-08-16 20:43:16 +1000334
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000335 if (reg + sz * 4 >= 0x10000) {
336 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg,
337 sz);
Eric Anholt20caafa2007-08-25 19:22:43 +1000338 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000339 }
340
341 if (r300_check_range(reg, sz)) {
Dave Airlie414ed532005-08-16 20:43:16 +1000342 /* go and check everything */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000343 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
344 header);
345 }
Dave Airlie414ed532005-08-16 20:43:16 +1000346 /* the rest of the data is safe to emit, whatever the values the user passed */
347
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000348 BEGIN_RING(1 + sz);
349 OUT_RING(CP_PACKET0(reg, sz - 1));
Dave Airlieb3a83632005-09-30 18:37:36 +1000350 OUT_RING_TABLE((int *)cmdbuf->buf, sz);
Dave Airlie414ed532005-08-16 20:43:16 +1000351 ADVANCE_RING();
352
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000353 cmdbuf->buf += sz * 4;
354 cmdbuf->bufsz -= sz * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000355
356 return 0;
357}
358
Dave Airlie414ed532005-08-16 20:43:16 +1000359/**
360 * Uploads user-supplied vertex program instructions or parameters onto
361 * the graphics card.
362 * Called by r300_do_cp_cmdbuf.
363 */
Dave Airlied985c102006-01-02 21:32:48 +1100364static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
365 drm_radeon_kcmd_buffer_t *cmdbuf,
Dave Airlie414ed532005-08-16 20:43:16 +1000366 drm_r300_cmd_header_t header)
367{
368 int sz;
369 int addr;
370 RING_LOCALS;
371
372 sz = header.vpu.count;
373 addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
374
375 if (!sz)
376 return 0;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000377 if (sz * 16 > cmdbuf->bufsz)
Eric Anholt20caafa2007-08-25 19:22:43 +1000378 return -EINVAL;
Dave Airlie414ed532005-08-16 20:43:16 +1000379
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000380 BEGIN_RING(5 + sz * 4);
Dave Airlie414ed532005-08-16 20:43:16 +1000381 /* Wait for VAP to come to senses.. */
382 /* there is no need to emit it multiple times, (only once before VAP is programmed,
383 but this optimization is for later */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000384 OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0);
385 OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
386 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
Dave Airlieb3a83632005-09-30 18:37:36 +1000387 OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
Dave Airlie414ed532005-08-16 20:43:16 +1000388
389 ADVANCE_RING();
390
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000391 cmdbuf->buf += sz * 16;
392 cmdbuf->bufsz -= sz * 16;
Dave Airlie414ed532005-08-16 20:43:16 +1000393
394 return 0;
395}
396
Dave Airlie414ed532005-08-16 20:43:16 +1000397/**
398 * Emit a clear packet from userspace.
399 * Called by r300_emit_packet3.
400 */
Dave Airlied985c102006-01-02 21:32:48 +1100401static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
402 drm_radeon_kcmd_buffer_t *cmdbuf)
Dave Airlie414ed532005-08-16 20:43:16 +1000403{
404 RING_LOCALS;
405
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000406 if (8 * 4 > cmdbuf->bufsz)
Eric Anholt20caafa2007-08-25 19:22:43 +1000407 return -EINVAL;
Dave Airlie414ed532005-08-16 20:43:16 +1000408
409 BEGIN_RING(10);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000410 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
411 OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
412 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
Dave Airlieb3a83632005-09-30 18:37:36 +1000413 OUT_RING_TABLE((int *)cmdbuf->buf, 8);
Dave Airlie414ed532005-08-16 20:43:16 +1000414 ADVANCE_RING();
415
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000416 cmdbuf->buf += 8 * 4;
417 cmdbuf->bufsz -= 8 * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000418
419 return 0;
420}
421
Dave Airlied985c102006-01-02 21:32:48 +1100422static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
423 drm_radeon_kcmd_buffer_t *cmdbuf,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000424 u32 header)
Dave Airlie414ed532005-08-16 20:43:16 +1000425{
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000426 int count, i, k;
427#define MAX_ARRAY_PACKET 64
Dave Airlie414ed532005-08-16 20:43:16 +1000428 u32 payload[MAX_ARRAY_PACKET];
429 u32 narrays;
430 RING_LOCALS;
431
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000432 count = (header >> 16) & 0x3fff;
433
434 if ((count + 1) > MAX_ARRAY_PACKET) {
435 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
436 count);
Eric Anholt20caafa2007-08-25 19:22:43 +1000437 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000438 }
439 memset(payload, 0, MAX_ARRAY_PACKET * 4);
440 memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4);
441
Dave Airlie414ed532005-08-16 20:43:16 +1000442 /* carefully check packet contents */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000443
444 narrays = payload[0];
445 k = 0;
446 i = 1;
447 while ((k < narrays) && (i < (count + 1))) {
448 i++; /* skip attribute field */
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +1100449 if (!radeon_check_offset(dev_priv, payload[i])) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000450 DRM_ERROR
451 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
452 k, i);
Eric Anholt20caafa2007-08-25 19:22:43 +1000453 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000454 }
Dave Airlie414ed532005-08-16 20:43:16 +1000455 k++;
456 i++;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000457 if (k == narrays)
458 break;
Dave Airlie414ed532005-08-16 20:43:16 +1000459 /* have one more to process, they come in pairs */
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +1100460 if (!radeon_check_offset(dev_priv, payload[i])) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000461 DRM_ERROR
462 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
463 k, i);
Eric Anholt20caafa2007-08-25 19:22:43 +1000464 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000465 }
Dave Airlie414ed532005-08-16 20:43:16 +1000466 k++;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000467 i++;
468 }
Dave Airlie414ed532005-08-16 20:43:16 +1000469 /* do the counts match what we expect ? */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000470 if ((k != narrays) || (i != (count + 1))) {
471 DRM_ERROR
472 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
473 k, i, narrays, count + 1);
Eric Anholt20caafa2007-08-25 19:22:43 +1000474 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000475 }
Dave Airlie414ed532005-08-16 20:43:16 +1000476
477 /* all clear, output packet */
478
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000479 BEGIN_RING(count + 2);
Dave Airlie414ed532005-08-16 20:43:16 +1000480 OUT_RING(header);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000481 OUT_RING_TABLE(payload, count + 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000482 ADVANCE_RING();
483
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000484 cmdbuf->buf += (count + 2) * 4;
485 cmdbuf->bufsz -= (count + 2) * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000486
487 return 0;
488}
Dave Airlied5ea7022006-03-19 19:37:55 +1100489
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100490static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
491 drm_radeon_kcmd_buffer_t *cmdbuf)
492{
493 u32 *cmd = (u32 *) cmdbuf->buf;
494 int count, ret;
495 RING_LOCALS;
496
497 count=(cmd[0]>>16) & 0x3fff;
498
499 if (cmd[0] & 0x8000) {
500 u32 offset;
501
Dave Airliebc5f4522007-11-05 12:50:58 +1000502 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100503 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
504 offset = cmd[2] << 10;
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +1100505 ret = !radeon_check_offset(dev_priv, offset);
Dave Airlie73d72cf2006-02-18 16:30:54 +1100506 if (ret) {
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100507 DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
Eric Anholt20caafa2007-08-25 19:22:43 +1000508 return -EINVAL;
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100509 }
510 }
511
512 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
513 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
514 offset = cmd[3] << 10;
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +1100515 ret = !radeon_check_offset(dev_priv, offset);
Dave Airlie73d72cf2006-02-18 16:30:54 +1100516 if (ret) {
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100517 DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
Eric Anholt20caafa2007-08-25 19:22:43 +1000518 return -EINVAL;
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100519 }
Dave Airliebc5f4522007-11-05 12:50:58 +1000520
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100521 }
522 }
523
524 BEGIN_RING(count+2);
525 OUT_RING(cmd[0]);
526 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
527 ADVANCE_RING();
528
529 cmdbuf->buf += (count+2)*4;
530 cmdbuf->bufsz -= (count+2)*4;
531
532 return 0;
533}
Dave Airlie414ed532005-08-16 20:43:16 +1000534
Roland Scheideggera1aa2892006-10-24 21:45:00 +1000535static __inline__ int r300_emit_indx_buffer(drm_radeon_private_t *dev_priv,
536 drm_radeon_kcmd_buffer_t *cmdbuf)
537{
538 u32 *cmd = (u32 *) cmdbuf->buf;
539 int count, ret;
540 RING_LOCALS;
541
542 count=(cmd[0]>>16) & 0x3fff;
543
544 if ((cmd[1] & 0x8000ffff) != 0x80000810) {
545 DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
Eric Anholt20caafa2007-08-25 19:22:43 +1000546 return -EINVAL;
Roland Scheideggera1aa2892006-10-24 21:45:00 +1000547 }
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +1100548 ret = !radeon_check_offset(dev_priv, cmd[2]);
Roland Scheideggera1aa2892006-10-24 21:45:00 +1000549 if (ret) {
550 DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
Eric Anholt20caafa2007-08-25 19:22:43 +1000551 return -EINVAL;
Roland Scheideggera1aa2892006-10-24 21:45:00 +1000552 }
553
554 BEGIN_RING(count+2);
555 OUT_RING(cmd[0]);
556 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
557 ADVANCE_RING();
558
559 cmdbuf->buf += (count+2)*4;
560 cmdbuf->bufsz -= (count+2)*4;
561
562 return 0;
563}
564
Dave Airlied985c102006-01-02 21:32:48 +1100565static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
566 drm_radeon_kcmd_buffer_t *cmdbuf)
Dave Airlie414ed532005-08-16 20:43:16 +1000567{
568 u32 header;
569 int count;
570 RING_LOCALS;
571
572 if (4 > cmdbuf->bufsz)
Eric Anholt20caafa2007-08-25 19:22:43 +1000573 return -EINVAL;
Dave Airlie414ed532005-08-16 20:43:16 +1000574
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000575 /* Fixme !! This simply emits a packet without much checking.
Dave Airlie414ed532005-08-16 20:43:16 +1000576 We need to be smarter. */
577
578 /* obtain first word - actual packet3 header */
Dave Airlieb3a83632005-09-30 18:37:36 +1000579 header = *(u32 *) cmdbuf->buf;
Dave Airlie414ed532005-08-16 20:43:16 +1000580
581 /* Is it packet 3 ? */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000582 if ((header >> 30) != 0x3) {
Dave Airlie414ed532005-08-16 20:43:16 +1000583 DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
Eric Anholt20caafa2007-08-25 19:22:43 +1000584 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000585 }
Dave Airlie414ed532005-08-16 20:43:16 +1000586
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000587 count = (header >> 16) & 0x3fff;
Dave Airlie414ed532005-08-16 20:43:16 +1000588
589 /* Check again now that we know how much data to expect */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000590 if ((count + 2) * 4 > cmdbuf->bufsz) {
591 DRM_ERROR
592 ("Expected packet3 of length %d but have only %d bytes left\n",
593 (count + 2) * 4, cmdbuf->bufsz);
Eric Anholt20caafa2007-08-25 19:22:43 +1000594 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000595 }
Dave Airlie414ed532005-08-16 20:43:16 +1000596
597 /* Is it a packet type we know about ? */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000598 switch (header & 0xff00) {
599 case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
Dave Airlie414ed532005-08-16 20:43:16 +1000600 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
601
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100602 case RADEON_CNTL_BITBLT_MULTI:
603 return r300_emit_bitblt_multi(dev_priv, cmdbuf);
604
Roland Scheideggera1aa2892006-10-24 21:45:00 +1000605 case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
606 return r300_emit_indx_buffer(dev_priv, cmdbuf);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000607 case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
608 case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
609 case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
Dave Airlie414ed532005-08-16 20:43:16 +1000610 case RADEON_WAIT_FOR_IDLE:
611 case RADEON_CP_NOP:
612 /* these packets are safe */
613 break;
614 default:
615 DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
Eric Anholt20caafa2007-08-25 19:22:43 +1000616 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000617 }
Dave Airlie414ed532005-08-16 20:43:16 +1000618
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000619 BEGIN_RING(count + 2);
Dave Airlie414ed532005-08-16 20:43:16 +1000620 OUT_RING(header);
Dave Airlieb3a83632005-09-30 18:37:36 +1000621 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000622 ADVANCE_RING();
623
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000624 cmdbuf->buf += (count + 2) * 4;
625 cmdbuf->bufsz -= (count + 2) * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000626
627 return 0;
628}
629
Dave Airlie414ed532005-08-16 20:43:16 +1000630/**
631 * Emit a rendering packet3 from userspace.
632 * Called by r300_do_cp_cmdbuf.
633 */
Dave Airlied985c102006-01-02 21:32:48 +1100634static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
635 drm_radeon_kcmd_buffer_t *cmdbuf,
Dave Airlie414ed532005-08-16 20:43:16 +1000636 drm_r300_cmd_header_t header)
637{
638 int n;
639 int ret;
Dave Airlieb3a83632005-09-30 18:37:36 +1000640 char *orig_buf = cmdbuf->buf;
Dave Airlie414ed532005-08-16 20:43:16 +1000641 int orig_bufsz = cmdbuf->bufsz;
642
643 /* This is a do-while-loop so that we run the interior at least once,
644 * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
645 */
646 n = 0;
647 do {
648 if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
649 ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
650 if (ret)
651 return ret;
652
653 cmdbuf->buf = orig_buf;
654 cmdbuf->bufsz = orig_bufsz;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000655 }
Dave Airlie414ed532005-08-16 20:43:16 +1000656
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000657 switch (header.packet3.packet) {
Dave Airlie414ed532005-08-16 20:43:16 +1000658 case R300_CMD_PACKET3_CLEAR:
659 DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
660 ret = r300_emit_clear(dev_priv, cmdbuf);
661 if (ret) {
662 DRM_ERROR("r300_emit_clear failed\n");
663 return ret;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000664 }
Dave Airlie414ed532005-08-16 20:43:16 +1000665 break;
666
667 case R300_CMD_PACKET3_RAW:
668 DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
669 ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
670 if (ret) {
671 DRM_ERROR("r300_emit_raw_packet3 failed\n");
672 return ret;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000673 }
Dave Airlie414ed532005-08-16 20:43:16 +1000674 break;
675
676 default:
677 DRM_ERROR("bad packet3 type %i at %p\n",
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000678 header.packet3.packet,
679 cmdbuf->buf - sizeof(header));
Eric Anholt20caafa2007-08-25 19:22:43 +1000680 return -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000681 }
Dave Airlie414ed532005-08-16 20:43:16 +1000682
683 n += R300_SIMULTANEOUS_CLIPRECTS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000684 } while (n < cmdbuf->nbox);
Dave Airlie414ed532005-08-16 20:43:16 +1000685
686 return 0;
687}
688
689/* Some of the R300 chips seem to be extremely touchy about the two registers
690 * that are configured in r300_pacify.
691 * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
692 * sends a command buffer that contains only state setting commands and a
693 * vertex program/parameter upload sequence, this will eventually lead to a
694 * lockup, unless the sequence is bracketed by calls to r300_pacify.
695 * So we should take great care to *always* call r300_pacify before
696 * *anything* 3D related, and again afterwards. This is what the
697 * call bracket in r300_do_cp_cmdbuf is for.
698 */
699
700/**
701 * Emit the sequence to pacify R300.
702 */
Dave Airlied985c102006-01-02 21:32:48 +1100703static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
Dave Airlie414ed532005-08-16 20:43:16 +1000704{
705 RING_LOCALS;
706
707 BEGIN_RING(6);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000708 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000709 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
710 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
711 OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000712 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
713 OUT_RING(0x0);
Dave Airlie414ed532005-08-16 20:43:16 +1000714 ADVANCE_RING();
715}
716
Dave Airlie414ed532005-08-16 20:43:16 +1000717/**
718 * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
719 * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
720 * be careful about how this function is called.
721 */
Dave Airlie056219e2007-07-11 16:17:42 +1000722static void r300_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
Dave Airlie414ed532005-08-16 20:43:16 +1000723{
724 drm_radeon_private_t *dev_priv = dev->dev_private;
725 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
726
727 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
728 buf->pending = 1;
729 buf->used = 0;
730}
731
Dave Airlie0c76be32008-03-30 07:51:49 +1000732static void r300_cmd_wait(drm_radeon_private_t * dev_priv,
733 drm_r300_cmd_header_t header)
734{
735 u32 wait_until;
736 RING_LOCALS;
737
738 if (!header.wait.flags)
739 return;
740
741 wait_until = 0;
742
743 switch(header.wait.flags) {
744 case R300_WAIT_2D:
745 wait_until = RADEON_WAIT_2D_IDLE;
746 break;
747 case R300_WAIT_3D:
748 wait_until = RADEON_WAIT_3D_IDLE;
749 break;
750 case R300_NEW_WAIT_2D_3D:
751 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_3D_IDLE;
752 break;
753 case R300_NEW_WAIT_2D_2D_CLEAN:
754 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
755 break;
756 case R300_NEW_WAIT_3D_3D_CLEAN:
757 wait_until = RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
758 break;
759 case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
760 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
761 wait_until |= RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
762 break;
763 default:
764 return;
765 }
766
767 BEGIN_RING(2);
768 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
769 OUT_RING(wait_until);
770 ADVANCE_RING();
771}
772
Dave Airlieee4621f2006-03-19 19:45:26 +1100773static int r300_scratch(drm_radeon_private_t *dev_priv,
774 drm_radeon_kcmd_buffer_t *cmdbuf,
775 drm_r300_cmd_header_t header)
776{
777 u32 *ref_age_base;
778 u32 i, buf_idx, h_pending;
779 RING_LOCALS;
Dave Airliebc5f4522007-11-05 12:50:58 +1000780
781 if (cmdbuf->bufsz <
Dave Airlieee4621f2006-03-19 19:45:26 +1100782 (sizeof(u64) + header.scratch.n_bufs * sizeof(buf_idx))) {
Eric Anholt20caafa2007-08-25 19:22:43 +1000783 return -EINVAL;
Dave Airlieee4621f2006-03-19 19:45:26 +1100784 }
Dave Airliebc5f4522007-11-05 12:50:58 +1000785
Dave Airlieee4621f2006-03-19 19:45:26 +1100786 if (header.scratch.reg >= 5) {
Eric Anholt20caafa2007-08-25 19:22:43 +1000787 return -EINVAL;
Dave Airlieee4621f2006-03-19 19:45:26 +1100788 }
Dave Airliebc5f4522007-11-05 12:50:58 +1000789
Dave Airlieee4621f2006-03-19 19:45:26 +1100790 dev_priv->scratch_ages[header.scratch.reg]++;
Dave Airliebc5f4522007-11-05 12:50:58 +1000791
Dave Airliecaa98c42006-04-23 18:14:00 +1000792 ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf);
Dave Airliebc5f4522007-11-05 12:50:58 +1000793
Dave Airlieee4621f2006-03-19 19:45:26 +1100794 cmdbuf->buf += sizeof(u64);
795 cmdbuf->bufsz -= sizeof(u64);
Dave Airliebc5f4522007-11-05 12:50:58 +1000796
Dave Airlieee4621f2006-03-19 19:45:26 +1100797 for (i=0; i < header.scratch.n_bufs; i++) {
798 buf_idx = *(u32 *)cmdbuf->buf;
799 buf_idx *= 2; /* 8 bytes per buf */
Dave Airliebc5f4522007-11-05 12:50:58 +1000800
Dave Airlieee4621f2006-03-19 19:45:26 +1100801 if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
Eric Anholt20caafa2007-08-25 19:22:43 +1000802 return -EINVAL;
Dave Airlieee4621f2006-03-19 19:45:26 +1100803 }
Dave Airliebc5f4522007-11-05 12:50:58 +1000804
Dave Airlieee4621f2006-03-19 19:45:26 +1100805 if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) {
Eric Anholt20caafa2007-08-25 19:22:43 +1000806 return -EINVAL;
Dave Airlieee4621f2006-03-19 19:45:26 +1100807 }
Dave Airliebc5f4522007-11-05 12:50:58 +1000808
Dave Airlieee4621f2006-03-19 19:45:26 +1100809 if (h_pending == 0) {
Eric Anholt20caafa2007-08-25 19:22:43 +1000810 return -EINVAL;
Dave Airlieee4621f2006-03-19 19:45:26 +1100811 }
Dave Airliebc5f4522007-11-05 12:50:58 +1000812
Dave Airlieee4621f2006-03-19 19:45:26 +1100813 h_pending--;
Dave Airliebc5f4522007-11-05 12:50:58 +1000814
Dave Airlieee4621f2006-03-19 19:45:26 +1100815 if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) {
Eric Anholt20caafa2007-08-25 19:22:43 +1000816 return -EINVAL;
Dave Airlieee4621f2006-03-19 19:45:26 +1100817 }
Dave Airliebc5f4522007-11-05 12:50:58 +1000818
Dave Airlieee4621f2006-03-19 19:45:26 +1100819 cmdbuf->buf += sizeof(buf_idx);
820 cmdbuf->bufsz -= sizeof(buf_idx);
821 }
Dave Airliebc5f4522007-11-05 12:50:58 +1000822
Dave Airlieee4621f2006-03-19 19:45:26 +1100823 BEGIN_RING(2);
Oliver McFaddenc6c656b2007-07-11 12:24:10 +1000824 OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) );
825 OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
Dave Airlieee4621f2006-03-19 19:45:26 +1100826 ADVANCE_RING();
Dave Airliebc5f4522007-11-05 12:50:58 +1000827
Dave Airlieee4621f2006-03-19 19:45:26 +1100828 return 0;
829}
830
Dave Airlie414ed532005-08-16 20:43:16 +1000831/**
832 * Parses and validates a user-supplied command buffer and emits appropriate
833 * commands on the DMA ring buffer.
834 * Called by the ioctl handler function radeon_cp_cmdbuf.
835 */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000836int r300_do_cp_cmdbuf(struct drm_device *dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000837 struct drm_file *file_priv,
Dave Airlied985c102006-01-02 21:32:48 +1100838 drm_radeon_kcmd_buffer_t *cmdbuf)
Dave Airlie414ed532005-08-16 20:43:16 +1000839{
840 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airliecdd55a22007-07-11 16:32:08 +1000841 struct drm_device_dma *dma = dev->dma;
Dave Airlie056219e2007-07-11 16:17:42 +1000842 struct drm_buf *buf = NULL;
Dave Airlie414ed532005-08-16 20:43:16 +1000843 int emit_dispatch_age = 0;
844 int ret = 0;
845
846 DRM_DEBUG("\n");
847
848 /* See the comment above r300_emit_begin3d for why this call must be here,
849 * and what the cleanup gotos are for. */
850 r300_pacify(dev_priv);
851
852 if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
853 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
854 if (ret)
855 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000856 }
Dave Airlie414ed532005-08-16 20:43:16 +1000857
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000858 while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
Dave Airlie414ed532005-08-16 20:43:16 +1000859 int idx;
860 drm_r300_cmd_header_t header;
861
862 header.u = *(unsigned int *)cmdbuf->buf;
863
864 cmdbuf->buf += sizeof(header);
865 cmdbuf->bufsz -= sizeof(header);
866
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000867 switch (header.header.cmd_type) {
868 case R300_CMD_PACKET0:
Dave Airlie414ed532005-08-16 20:43:16 +1000869 DRM_DEBUG("R300_CMD_PACKET0\n");
870 ret = r300_emit_packet0(dev_priv, cmdbuf, header);
871 if (ret) {
872 DRM_ERROR("r300_emit_packet0 failed\n");
873 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000874 }
Dave Airlie414ed532005-08-16 20:43:16 +1000875 break;
876
877 case R300_CMD_VPU:
878 DRM_DEBUG("R300_CMD_VPU\n");
879 ret = r300_emit_vpu(dev_priv, cmdbuf, header);
880 if (ret) {
881 DRM_ERROR("r300_emit_vpu failed\n");
882 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000883 }
Dave Airlie414ed532005-08-16 20:43:16 +1000884 break;
885
886 case R300_CMD_PACKET3:
887 DRM_DEBUG("R300_CMD_PACKET3\n");
888 ret = r300_emit_packet3(dev_priv, cmdbuf, header);
889 if (ret) {
890 DRM_ERROR("r300_emit_packet3 failed\n");
891 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000892 }
Dave Airlie414ed532005-08-16 20:43:16 +1000893 break;
894
895 case R300_CMD_END3D:
896 DRM_DEBUG("R300_CMD_END3D\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000897 /* TODO:
898 Ideally userspace driver should not need to issue this call,
899 i.e. the drm driver should issue it automatically and prevent
900 lockups.
Dave Airlie414ed532005-08-16 20:43:16 +1000901
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000902 In practice, we do not understand why this call is needed and what
903 it does (except for some vague guesses that it has to do with cache
904 coherence) and so the user space driver does it.
905
906 Once we are sure which uses prevent lockups the code could be moved
907 into the kernel and the userspace driver will not
908 need to use this command.
909
910 Note that issuing this command does not hurt anything
911 except, possibly, performance */
Dave Airlie414ed532005-08-16 20:43:16 +1000912 r300_pacify(dev_priv);
913 break;
914
915 case R300_CMD_CP_DELAY:
916 /* simple enough, we can do it here */
917 DRM_DEBUG("R300_CMD_CP_DELAY\n");
918 {
919 int i;
920 RING_LOCALS;
921
922 BEGIN_RING(header.delay.count);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000923 for (i = 0; i < header.delay.count; i++)
Dave Airlie414ed532005-08-16 20:43:16 +1000924 OUT_RING(RADEON_CP_PACKET2);
925 ADVANCE_RING();
926 }
927 break;
928
929 case R300_CMD_DMA_DISCARD:
930 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000931 idx = header.dma.buf_idx;
932 if (idx < 0 || idx >= dma->buf_count) {
933 DRM_ERROR("buffer index %d (of %d max)\n",
934 idx, dma->buf_count - 1);
Eric Anholt20caafa2007-08-25 19:22:43 +1000935 ret = -EINVAL;
Dave Airlie414ed532005-08-16 20:43:16 +1000936 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000937 }
938
939 buf = dma->buflist[idx];
Eric Anholt6c340ea2007-08-25 20:23:09 +1000940 if (buf->file_priv != file_priv || buf->pending) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000941 DRM_ERROR("bad buffer %p %p %d\n",
Eric Anholt6c340ea2007-08-25 20:23:09 +1000942 buf->file_priv, file_priv,
943 buf->pending);
Eric Anholt20caafa2007-08-25 19:22:43 +1000944 ret = -EINVAL;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000945 goto cleanup;
946 }
Dave Airlie414ed532005-08-16 20:43:16 +1000947
948 emit_dispatch_age = 1;
949 r300_discard_buffer(dev, buf);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000950 break;
Dave Airlie414ed532005-08-16 20:43:16 +1000951
952 case R300_CMD_WAIT:
Dave Airlie414ed532005-08-16 20:43:16 +1000953 DRM_DEBUG("R300_CMD_WAIT\n");
Dave Airlie0c76be32008-03-30 07:51:49 +1000954 r300_cmd_wait(dev_priv, header);
Dave Airlie414ed532005-08-16 20:43:16 +1000955 break;
956
Dave Airlieee4621f2006-03-19 19:45:26 +1100957 case R300_CMD_SCRATCH:
958 DRM_DEBUG("R300_CMD_SCRATCH\n");
959 ret = r300_scratch(dev_priv, cmdbuf, header);
960 if (ret) {
961 DRM_ERROR("r300_scratch failed\n");
962 goto cleanup;
963 }
964 break;
Dave Airliebc5f4522007-11-05 12:50:58 +1000965
Dave Airlie414ed532005-08-16 20:43:16 +1000966 default:
967 DRM_ERROR("bad cmd_type %i at %p\n",
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000968 header.header.cmd_type,
Dave Airlie414ed532005-08-16 20:43:16 +1000969 cmdbuf->buf - sizeof(header));
Eric Anholt20caafa2007-08-25 19:22:43 +1000970 ret = -EINVAL;
Dave Airlie414ed532005-08-16 20:43:16 +1000971 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000972 }
Dave Airlie414ed532005-08-16 20:43:16 +1000973 }
974
975 DRM_DEBUG("END\n");
976
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000977 cleanup:
Dave Airlie414ed532005-08-16 20:43:16 +1000978 r300_pacify(dev_priv);
979
980 /* We emit the vertex buffer age here, outside the pacifier "brackets"
981 * for two reasons:
982 * (1) This may coalesce multiple age emissions into a single one and
983 * (2) more importantly, some chips lock up hard when scratch registers
984 * are written inside the pacifier bracket.
985 */
986 if (emit_dispatch_age) {
987 RING_LOCALS;
988
989 /* Emit the vertex buffer age */
990 BEGIN_RING(2);
991 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);
992 ADVANCE_RING();
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000993 }
Dave Airlie414ed532005-08-16 20:43:16 +1000994
995 COMMIT_RING();
996
997 return ret;
998}