Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/ide/pci/sc1200.c Version 0.91 28-Jan-2003 |
| 3 | * |
| 4 | * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com> |
| 5 | * May be copied or modified under the terms of the GNU General Public License |
| 6 | * |
| 7 | * Development of this chipset driver was funded |
| 8 | * by the nice folks at National Semiconductor. |
| 9 | * |
| 10 | * Documentation: |
| 11 | * Available from National Semiconductor |
| 12 | */ |
| 13 | |
| 14 | #include <linux/config.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/types.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/timer.h> |
| 20 | #include <linux/mm.h> |
| 21 | #include <linux/ioport.h> |
| 22 | #include <linux/blkdev.h> |
| 23 | #include <linux/hdreg.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/pci.h> |
| 26 | #include <linux/init.h> |
| 27 | #include <linux/ide.h> |
| 28 | #include <linux/pm.h> |
| 29 | #include <asm/io.h> |
| 30 | #include <asm/irq.h> |
| 31 | |
| 32 | #define SC1200_REV_A 0x00 |
| 33 | #define SC1200_REV_B1 0x01 |
| 34 | #define SC1200_REV_B3 0x02 |
| 35 | #define SC1200_REV_C1 0x03 |
| 36 | #define SC1200_REV_D1 0x04 |
| 37 | |
| 38 | #define PCI_CLK_33 0x00 |
| 39 | #define PCI_CLK_48 0x01 |
| 40 | #define PCI_CLK_66 0x02 |
| 41 | #define PCI_CLK_33A 0x03 |
| 42 | |
| 43 | static unsigned short sc1200_get_pci_clock (void) |
| 44 | { |
| 45 | unsigned char chip_id, silicon_revision; |
| 46 | unsigned int pci_clock; |
| 47 | /* |
| 48 | * Check the silicon revision, as not all versions of the chip |
| 49 | * have the register with the fast PCI bus timings. |
| 50 | */ |
| 51 | chip_id = inb (0x903c); |
| 52 | silicon_revision = inb (0x903d); |
| 53 | |
| 54 | // Read the fast pci clock frequency |
| 55 | if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) { |
| 56 | pci_clock = PCI_CLK_33; |
| 57 | } else { |
| 58 | // check clock generator configuration (cfcc) |
| 59 | // the clock is in bits 8 and 9 of this word |
| 60 | |
| 61 | pci_clock = inw (0x901e); |
| 62 | pci_clock >>= 8; |
| 63 | pci_clock &= 0x03; |
| 64 | if (pci_clock == PCI_CLK_33A) |
| 65 | pci_clock = PCI_CLK_33; |
| 66 | } |
| 67 | return pci_clock; |
| 68 | } |
| 69 | |
| 70 | extern char *ide_xfer_verbose (byte xfer_rate); |
| 71 | |
| 72 | /* |
| 73 | * Set a new transfer mode at the drive |
| 74 | */ |
| 75 | static int sc1200_set_xfer_mode (ide_drive_t *drive, byte mode) |
| 76 | { |
| 77 | printk("%s: sc1200_set_xfer_mode(%s)\n", drive->name, ide_xfer_verbose(mode)); |
| 78 | return ide_config_drive_speed(drive, mode); |
| 79 | } |
| 80 | |
| 81 | /* |
| 82 | * Here are the standard PIO mode 0-4 timings for each "format". |
| 83 | * Format-0 uses fast data reg timings, with slower command reg timings. |
| 84 | * Format-1 uses fast timings for all registers, but won't work with all drives. |
| 85 | */ |
| 86 | static const unsigned int sc1200_pio_timings[4][5] = |
| 87 | {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz |
| 88 | {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz |
| 89 | {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz |
| 90 | {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz |
| 91 | |
| 92 | /* |
| 93 | * After chip reset, the PIO timings are set to 0x00009172, which is not valid. |
| 94 | */ |
| 95 | //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172) |
| 96 | |
| 97 | static int sc1200_autoselect_dma_mode (ide_drive_t *drive) |
| 98 | { |
| 99 | int udma_ok = 1, mode = 0; |
| 100 | ide_hwif_t *hwif = HWIF(drive); |
| 101 | int unit = drive->select.b.unit; |
| 102 | ide_drive_t *mate = &hwif->drives[unit^1]; |
| 103 | struct hd_driveid *id = drive->id; |
| 104 | |
| 105 | /* |
| 106 | * The SC1200 specifies that two drives sharing a cable cannot |
| 107 | * mix UDMA/MDMA. It has to be one or the other, for the pair, |
| 108 | * though different timings can still be chosen for each drive. |
| 109 | * We could set the appropriate timing bits on the fly, |
| 110 | * but that might be a bit confusing. So, for now we statically |
| 111 | * handle this requirement by looking at our mate drive to see |
| 112 | * what it is capable of, before choosing a mode for our own drive. |
| 113 | */ |
| 114 | if (mate->present) { |
| 115 | struct hd_driveid *mateid = mate->id; |
| 116 | if (mateid && (mateid->capability & 1) && !__ide_dma_bad_drive(mate)) { |
| 117 | if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7)) |
| 118 | udma_ok = 1; |
| 119 | else if ((mateid->field_valid & 2) && (mateid->dma_mword & 7)) |
| 120 | udma_ok = 0; |
| 121 | else |
| 122 | udma_ok = 1; |
| 123 | } |
| 124 | } |
| 125 | /* |
| 126 | * Now see what the current drive is capable of, |
| 127 | * selecting UDMA only if the mate said it was ok. |
| 128 | */ |
| 129 | if (id && (id->capability & 1) && hwif->autodma && !__ide_dma_bad_drive(drive)) { |
| 130 | if (udma_ok && (id->field_valid & 4) && (id->dma_ultra & 7)) { |
| 131 | if (id->dma_ultra & 4) |
| 132 | mode = XFER_UDMA_2; |
| 133 | else if (id->dma_ultra & 2) |
| 134 | mode = XFER_UDMA_1; |
| 135 | else if (id->dma_ultra & 1) |
| 136 | mode = XFER_UDMA_0; |
| 137 | } |
| 138 | if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) { |
| 139 | if (id->dma_mword & 4) |
| 140 | mode = XFER_MW_DMA_2; |
| 141 | else if (id->dma_mword & 2) |
| 142 | mode = XFER_MW_DMA_1; |
| 143 | else if (id->dma_mword & 1) |
| 144 | mode = XFER_MW_DMA_0; |
| 145 | } |
| 146 | } |
| 147 | return mode; |
| 148 | } |
| 149 | |
| 150 | /* |
| 151 | * sc1200_config_dma2() handles selection/setting of DMA/UDMA modes |
| 152 | * for both the chipset and drive. |
| 153 | */ |
| 154 | static int sc1200_config_dma2 (ide_drive_t *drive, int mode) |
| 155 | { |
| 156 | ide_hwif_t *hwif = HWIF(drive); |
| 157 | int unit = drive->select.b.unit; |
| 158 | unsigned int reg, timings; |
| 159 | unsigned short pci_clock; |
| 160 | unsigned int basereg = hwif->channel ? 0x50 : 0x40; |
| 161 | |
| 162 | /* |
| 163 | * Default to DMA-off in case we run into trouble here. |
| 164 | */ |
| 165 | hwif->ide_dma_off_quietly(drive); /* turn off DMA while we fiddle */ |
| 166 | outb(inb(hwif->dma_base+2)&~(unit?0x40:0x20), hwif->dma_base+2); /* clear DMA_capable bit */ |
| 167 | |
| 168 | /* |
| 169 | * Tell the drive to switch to the new mode; abort on failure. |
| 170 | */ |
| 171 | if (!mode || sc1200_set_xfer_mode(drive, mode)) { |
| 172 | printk("SC1200: set xfer mode failure\n"); |
| 173 | return 1; /* failure */ |
| 174 | } |
| 175 | |
| 176 | pci_clock = sc1200_get_pci_clock(); |
| 177 | |
| 178 | /* |
| 179 | * Now tune the chipset to match the drive: |
| 180 | * |
| 181 | * Note that each DMA mode has several timings associated with it. |
| 182 | * The correct timing depends on the fast PCI clock freq. |
| 183 | */ |
| 184 | timings = 0; |
| 185 | switch (mode) { |
| 186 | case XFER_UDMA_0: |
| 187 | switch (pci_clock) { |
| 188 | case PCI_CLK_33: timings = 0x00921250; break; |
| 189 | case PCI_CLK_48: timings = 0x00932470; break; |
| 190 | case PCI_CLK_66: timings = 0x009436a1; break; |
| 191 | } |
| 192 | break; |
| 193 | case XFER_UDMA_1: |
| 194 | switch (pci_clock) { |
| 195 | case PCI_CLK_33: timings = 0x00911140; break; |
| 196 | case PCI_CLK_48: timings = 0x00922260; break; |
| 197 | case PCI_CLK_66: timings = 0x00933481; break; |
| 198 | } |
| 199 | break; |
| 200 | case XFER_UDMA_2: |
| 201 | switch (pci_clock) { |
| 202 | case PCI_CLK_33: timings = 0x00911030; break; |
| 203 | case PCI_CLK_48: timings = 0x00922140; break; |
| 204 | case PCI_CLK_66: timings = 0x00923261; break; |
| 205 | } |
| 206 | break; |
| 207 | case XFER_MW_DMA_0: |
| 208 | switch (pci_clock) { |
| 209 | case PCI_CLK_33: timings = 0x00077771; break; |
| 210 | case PCI_CLK_48: timings = 0x000bbbb2; break; |
| 211 | case PCI_CLK_66: timings = 0x000ffff3; break; |
| 212 | } |
| 213 | break; |
| 214 | case XFER_MW_DMA_1: |
| 215 | switch (pci_clock) { |
| 216 | case PCI_CLK_33: timings = 0x00012121; break; |
| 217 | case PCI_CLK_48: timings = 0x00024241; break; |
| 218 | case PCI_CLK_66: timings = 0x00035352; break; |
| 219 | } |
| 220 | break; |
| 221 | case XFER_MW_DMA_2: |
| 222 | switch (pci_clock) { |
| 223 | case PCI_CLK_33: timings = 0x00002020; break; |
| 224 | case PCI_CLK_48: timings = 0x00013131; break; |
| 225 | case PCI_CLK_66: timings = 0x00015151; break; |
| 226 | } |
| 227 | break; |
| 228 | } |
| 229 | |
| 230 | if (timings == 0) { |
| 231 | printk("%s: sc1200_config_dma: huh? mode=%02x clk=%x \n", drive->name, mode, pci_clock); |
| 232 | return 1; /* failure */ |
| 233 | } |
| 234 | |
| 235 | if (unit == 0) { /* are we configuring drive0? */ |
| 236 | pci_read_config_dword(hwif->pci_dev, basereg+4, ®); |
| 237 | timings |= reg & 0x80000000; /* preserve PIO format bit */ |
| 238 | pci_write_config_dword(hwif->pci_dev, basereg+4, timings); |
| 239 | } else { |
| 240 | pci_write_config_dword(hwif->pci_dev, basereg+12, timings); |
| 241 | } |
| 242 | |
| 243 | outb(inb(hwif->dma_base+2)|(unit?0x40:0x20), hwif->dma_base+2); /* set DMA_capable bit */ |
| 244 | |
| 245 | /* |
| 246 | * Finally, turn DMA on in software, and exit. |
| 247 | */ |
| 248 | return hwif->ide_dma_on(drive); /* success */ |
| 249 | } |
| 250 | |
| 251 | /* |
| 252 | * sc1200_config_dma() handles selection/setting of DMA/UDMA modes |
| 253 | * for both the chipset and drive. |
| 254 | */ |
| 255 | static int sc1200_config_dma (ide_drive_t *drive) |
| 256 | { |
| 257 | return sc1200_config_dma2(drive, sc1200_autoselect_dma_mode(drive)); |
| 258 | } |
| 259 | |
| 260 | |
| 261 | /* Replacement for the standard ide_dma_end action in |
| 262 | * dma_proc. |
| 263 | * |
| 264 | * returns 1 on error, 0 otherwise |
| 265 | */ |
| 266 | static int sc1200_ide_dma_end (ide_drive_t *drive) |
| 267 | { |
| 268 | ide_hwif_t *hwif = HWIF(drive); |
| 269 | unsigned long dma_base = hwif->dma_base; |
| 270 | byte dma_stat; |
| 271 | |
| 272 | dma_stat = inb(dma_base+2); /* get DMA status */ |
| 273 | |
| 274 | if (!(dma_stat & 4)) |
| 275 | printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n", |
| 276 | dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2)); |
| 277 | |
| 278 | outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */ |
| 279 | outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */ |
| 280 | |
| 281 | drive->waiting_for_dma = 0; |
| 282 | ide_destroy_dmatable(drive); /* purge DMA mappings */ |
| 283 | |
| 284 | return (dma_stat & 7) != 4; /* verify good DMA status */ |
| 285 | } |
| 286 | |
| 287 | /* |
| 288 | * sc1200_tuneproc() handles selection/setting of PIO modes |
| 289 | * for both the chipset and drive. |
| 290 | * |
| 291 | * All existing BIOSs for this chipset guarantee that all drives |
| 292 | * will have valid default PIO timings set up before we get here. |
| 293 | */ |
| 294 | static void sc1200_tuneproc (ide_drive_t *drive, byte pio) /* mode=255 means "autotune" */ |
| 295 | { |
| 296 | ide_hwif_t *hwif = HWIF(drive); |
| 297 | unsigned int format; |
| 298 | static byte modes[5] = {XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4}; |
| 299 | int mode = -1; |
| 300 | |
| 301 | switch (pio) { |
| 302 | case 200: mode = XFER_UDMA_0; break; |
| 303 | case 201: mode = XFER_UDMA_1; break; |
| 304 | case 202: mode = XFER_UDMA_2; break; |
| 305 | case 100: mode = XFER_MW_DMA_0; break; |
| 306 | case 101: mode = XFER_MW_DMA_1; break; |
| 307 | case 102: mode = XFER_MW_DMA_2; break; |
| 308 | } |
| 309 | if (mode != -1) { |
| 310 | printk("SC1200: %s: changing (U)DMA mode\n", drive->name); |
| 311 | (void)sc1200_config_dma2(drive, mode); |
| 312 | return; |
| 313 | } |
| 314 | |
| 315 | pio = ide_get_best_pio_mode(drive, pio, 4, NULL); |
| 316 | printk("SC1200: %s: setting PIO mode%d\n", drive->name, pio); |
| 317 | if (!sc1200_set_xfer_mode(drive, modes[pio])) { |
| 318 | unsigned int basereg = hwif->channel ? 0x50 : 0x40; |
| 319 | pci_read_config_dword (hwif->pci_dev, basereg+4, &format); |
| 320 | format = (format >> 31) & 1; |
| 321 | if (format) |
| 322 | format += sc1200_get_pci_clock(); |
| 323 | pci_write_config_dword(hwif->pci_dev, basereg + (drive->select.b.unit << 3), sc1200_pio_timings[format][pio]); |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev) |
| 328 | { |
| 329 | int h; |
| 330 | |
| 331 | for (h = 0; h < MAX_HWIFS; h++) { |
| 332 | ide_hwif_t *hwif = &ide_hwifs[h]; |
| 333 | if (prev) { |
| 334 | if (hwif == prev) |
| 335 | prev = NULL; // found previous, now look for next match |
| 336 | } else { |
| 337 | if (hwif && hwif->pci_dev == dev) |
| 338 | return hwif; // found next match |
| 339 | } |
| 340 | } |
| 341 | return NULL; // not found |
| 342 | } |
| 343 | |
| 344 | typedef struct sc1200_saved_state_s { |
| 345 | __u32 regs[4]; |
| 346 | } sc1200_saved_state_t; |
| 347 | |
| 348 | |
Pavel Machek | 3bfffd9 | 2005-04-16 15:25:37 -0700 | [diff] [blame] | 349 | static int sc1200_suspend (struct pci_dev *dev, pm_message_t state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | { |
| 351 | ide_hwif_t *hwif = NULL; |
| 352 | |
| 353 | printk("SC1200: suspend(%u)\n", state); |
| 354 | |
| 355 | if (state == 0) { |
| 356 | // we only save state when going from full power to less |
| 357 | |
| 358 | // |
| 359 | // Loop over all interfaces that are part of this PCI device: |
| 360 | // |
| 361 | while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { |
| 362 | sc1200_saved_state_t *ss; |
| 363 | unsigned int basereg, r; |
| 364 | // |
| 365 | // allocate a permanent save area, if not already allocated |
| 366 | // |
| 367 | ss = (sc1200_saved_state_t *)hwif->config_data; |
| 368 | if (ss == NULL) { |
| 369 | ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL); |
| 370 | if (ss == NULL) |
| 371 | return -ENOMEM; |
| 372 | hwif->config_data = (unsigned long)ss; |
| 373 | } |
| 374 | ss = (sc1200_saved_state_t *)hwif->config_data; |
| 375 | // |
| 376 | // Save timing registers: this may be unnecessary if |
| 377 | // BIOS also does it |
| 378 | // |
| 379 | basereg = hwif->channel ? 0x50 : 0x40; |
| 380 | for (r = 0; r < 4; ++r) { |
| 381 | pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]); |
| 382 | } |
| 383 | } |
| 384 | } |
| 385 | |
| 386 | /* You don't need to iterate over disks -- sysfs should have done that for you already */ |
| 387 | |
| 388 | pci_disable_device(dev); |
| 389 | pci_set_power_state(dev,state); |
| 390 | dev->current_state = state; |
| 391 | return 0; |
| 392 | } |
| 393 | |
| 394 | static int sc1200_resume (struct pci_dev *dev) |
| 395 | { |
| 396 | ide_hwif_t *hwif = NULL; |
| 397 | |
| 398 | printk("SC1200: resume\n"); |
| 399 | pci_set_power_state(dev,0); // bring chip back from sleep state |
| 400 | dev->current_state = 0; |
| 401 | pci_enable_device(dev); |
| 402 | // |
| 403 | // loop over all interfaces that are part of this pci device: |
| 404 | // |
| 405 | while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) { |
| 406 | unsigned int basereg, r, d, format; |
| 407 | sc1200_saved_state_t *ss = (sc1200_saved_state_t *)hwif->config_data; |
| 408 | printk("%s: SC1200: resume\n", hwif->name); |
| 409 | |
| 410 | // |
| 411 | // Restore timing registers: this may be unnecessary if BIOS also does it |
| 412 | // |
| 413 | basereg = hwif->channel ? 0x50 : 0x40; |
| 414 | if (ss != NULL) { |
| 415 | for (r = 0; r < 4; ++r) { |
| 416 | pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]); |
| 417 | } |
| 418 | } |
| 419 | // |
| 420 | // Re-program drive PIO modes |
| 421 | // |
| 422 | pci_read_config_dword(hwif->pci_dev, basereg+4, &format); |
| 423 | format = (format >> 31) & 1; |
| 424 | if (format) |
| 425 | format += sc1200_get_pci_clock(); |
| 426 | for (d = 0; d < 2; ++d) { |
| 427 | ide_drive_t *drive = &(hwif->drives[d]); |
| 428 | if (drive->present) { |
| 429 | unsigned int pio, timings; |
| 430 | pci_read_config_dword(hwif->pci_dev, basereg+(drive->select.b.unit << 3), &timings); |
| 431 | for (pio = 0; pio <= 4; ++pio) { |
| 432 | if (sc1200_pio_timings[format][pio] == timings) |
| 433 | break; |
| 434 | } |
| 435 | if (pio > 4) |
| 436 | pio = 255; /* autotune */ |
| 437 | (void)sc1200_tuneproc(drive, pio); |
| 438 | } |
| 439 | } |
| 440 | // |
| 441 | // Re-program drive DMA modes |
| 442 | // |
| 443 | for (d = 0; d < MAX_DRIVES; ++d) { |
| 444 | ide_drive_t *drive = &(hwif->drives[d]); |
| 445 | if (drive->present && !__ide_dma_bad_drive(drive)) { |
| 446 | int was_using_dma = drive->using_dma; |
| 447 | hwif->ide_dma_off_quietly(drive); |
| 448 | sc1200_config_dma(drive); |
| 449 | if (!was_using_dma && drive->using_dma) { |
| 450 | hwif->ide_dma_off_quietly(drive); |
| 451 | } |
| 452 | } |
| 453 | } |
| 454 | } |
| 455 | return 0; |
| 456 | } |
| 457 | |
| 458 | /* |
| 459 | * This gets invoked by the IDE driver once for each channel, |
| 460 | * and performs channel-specific pre-initialization before drive probing. |
| 461 | */ |
| 462 | static void __init init_hwif_sc1200 (ide_hwif_t *hwif) |
| 463 | { |
| 464 | if (hwif->mate) |
| 465 | hwif->serialized = hwif->mate->serialized = 1; |
| 466 | hwif->autodma = 0; |
| 467 | if (hwif->dma_base) { |
| 468 | hwif->ide_dma_check = &sc1200_config_dma; |
| 469 | hwif->ide_dma_end = &sc1200_ide_dma_end; |
| 470 | if (!noautodma) |
| 471 | hwif->autodma = 1; |
| 472 | hwif->tuneproc = &sc1200_tuneproc; |
| 473 | } |
| 474 | hwif->atapi_dma = 1; |
| 475 | hwif->ultra_mask = 0x07; |
| 476 | hwif->mwdma_mask = 0x07; |
| 477 | |
| 478 | hwif->drives[0].autodma = hwif->autodma; |
| 479 | hwif->drives[1].autodma = hwif->autodma; |
| 480 | } |
| 481 | |
| 482 | static ide_pci_device_t sc1200_chipset __devinitdata = { |
| 483 | .name = "SC1200", |
| 484 | .init_hwif = init_hwif_sc1200, |
| 485 | .channels = 2, |
| 486 | .autodma = AUTODMA, |
| 487 | .bootable = ON_BOARD, |
| 488 | }; |
| 489 | |
| 490 | static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 491 | { |
| 492 | return ide_setup_pci_device(dev, &sc1200_chipset); |
| 493 | } |
| 494 | |
| 495 | static struct pci_device_id sc1200_pci_tbl[] = { |
| 496 | { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
| 497 | { 0, }, |
| 498 | }; |
| 499 | MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl); |
| 500 | |
| 501 | static struct pci_driver driver = { |
| 502 | .name = "SC1200_IDE", |
| 503 | .id_table = sc1200_pci_tbl, |
| 504 | .probe = sc1200_init_one, |
| 505 | .suspend = sc1200_suspend, |
| 506 | .resume = sc1200_resume, |
| 507 | }; |
| 508 | |
| 509 | static int sc1200_ide_init(void) |
| 510 | { |
| 511 | return ide_pci_register_driver(&driver); |
| 512 | } |
| 513 | |
| 514 | module_init(sc1200_ide_init); |
| 515 | |
| 516 | MODULE_AUTHOR("Mark Lord"); |
| 517 | MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE"); |
| 518 | MODULE_LICENSE("GPL"); |