Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /*====================================================================== |
| 2 | |
| 3 | Device driver for the PCMCIA control functionality of StrongARM |
| 4 | SA-1100 microprocessors. |
| 5 | |
| 6 | The contents of this file are subject to the Mozilla Public |
| 7 | License Version 1.1 (the "License"); you may not use this file |
| 8 | except in compliance with the License. You may obtain a copy of |
| 9 | the License at http://www.mozilla.org/MPL/ |
| 10 | |
| 11 | Software distributed under the License is distributed on an "AS |
| 12 | IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or |
| 13 | implied. See the License for the specific language governing |
| 14 | rights and limitations under the License. |
| 15 | |
| 16 | The initial developer of the original code is John G. Dorsey |
| 17 | <john+@cs.cmu.edu>. Portions created by John G. Dorsey are |
| 18 | Copyright (C) 1999 John G. Dorsey. All Rights Reserved. |
| 19 | |
| 20 | Alternatively, the contents of this file may be used under the |
| 21 | terms of the GNU Public License version 2 (the "GPL"), in which |
| 22 | case the provisions of the GPL are applicable instead of the |
| 23 | above. If you wish to allow the use of your version of this file |
| 24 | only under the terms of the GPL and not to allow others to use |
| 25 | your version of this file under the MPL, indicate your decision |
| 26 | by deleting the provisions above and replace them with the notice |
| 27 | and other provisions required by the GPL. If you do not delete |
| 28 | the provisions above, a recipient may use your version of this |
| 29 | file under either the MPL or the GPL. |
| 30 | |
| 31 | ======================================================================*/ |
| 32 | |
| 33 | #if !defined(_PCMCIA_SA1100_H) |
| 34 | # define _PCMCIA_SA1100_H |
| 35 | |
| 36 | /* SA-1100 PCMCIA Memory and I/O timing |
| 37 | * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 38 | * The SA-1110 Developer's Manual, section 10.2.5, says the following: |
| 39 | * |
| 40 | * "To calculate the recommended BS_xx value for each address space: |
| 41 | * divide the command width time (the greater of twIOWR and twIORD, |
| 42 | * or the greater of twWE and twOE) by processor cycle time; divide |
| 43 | * by 2; divide again by 3 (number of BCLK's per command assertion); |
| 44 | * round up to the next whole number; and subtract 1." |
| 45 | */ |
| 46 | |
| 47 | /* MECR: Expansion Memory Configuration Register |
| 48 | * (SA-1100 Developers Manual, p.10-13; SA-1110 Developers Manual, p.10-24) |
| 49 | * |
| 50 | * MECR layout is: |
| 51 | * |
| 52 | * FAST1 BSM1<4:0> BSA1<4:0> BSIO1<4:0> FAST0 BSM0<4:0> BSA0<4:0> BSIO0<4:0> |
| 53 | * |
| 54 | * (This layout is actually true only for the SA-1110; the FASTn bits are |
| 55 | * reserved on the SA-1100.) |
| 56 | */ |
| 57 | |
| 58 | #define MECR_SOCKET_0_SHIFT (0) |
| 59 | #define MECR_SOCKET_1_SHIFT (16) |
| 60 | |
| 61 | #define MECR_BS_MASK (0x1f) |
| 62 | #define MECR_FAST_MODE_MASK (0x01) |
| 63 | |
| 64 | #define MECR_BSIO_SHIFT (0) |
| 65 | #define MECR_BSA_SHIFT (5) |
| 66 | #define MECR_BSM_SHIFT (10) |
| 67 | #define MECR_FAST_SHIFT (15) |
| 68 | |
| 69 | #define MECR_SET(mecr, sock, shift, mask, bs) \ |
| 70 | ((mecr)=((mecr)&~(((mask)<<(shift))<<\ |
| 71 | ((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))|\ |
| 72 | (((bs)<<(shift))<<((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT))) |
| 73 | |
| 74 | #define MECR_GET(mecr, sock, shift, mask) \ |
| 75 | ((((mecr)>>(((sock)==0)?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT))>>\ |
| 76 | (shift))&(mask)) |
| 77 | |
| 78 | #define MECR_BSIO_SET(mecr, sock, bs) \ |
| 79 | MECR_SET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK, (bs)) |
| 80 | |
| 81 | #define MECR_BSIO_GET(mecr, sock) \ |
| 82 | MECR_GET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK) |
| 83 | |
| 84 | #define MECR_BSA_SET(mecr, sock, bs) \ |
| 85 | MECR_SET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK, (bs)) |
| 86 | |
| 87 | #define MECR_BSA_GET(mecr, sock) \ |
| 88 | MECR_GET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK) |
| 89 | |
| 90 | #define MECR_BSM_SET(mecr, sock, bs) \ |
| 91 | MECR_SET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK, (bs)) |
| 92 | |
| 93 | #define MECR_BSM_GET(mecr, sock) \ |
| 94 | MECR_GET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK) |
| 95 | |
| 96 | #define MECR_FAST_SET(mecr, sock, fast) \ |
| 97 | MECR_SET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK, (fast)) |
| 98 | |
| 99 | #define MECR_FAST_GET(mecr, sock) \ |
| 100 | MECR_GET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK) |
| 101 | |
| 102 | |
| 103 | /* This function implements the BS value calculation for setting the MECR |
| 104 | * using integer arithmetic: |
| 105 | */ |
| 106 | static inline unsigned int sa1100_pcmcia_mecr_bs(unsigned int pcmcia_cycle_ns, |
| 107 | unsigned int cpu_clock_khz){ |
| 108 | unsigned int t = ((pcmcia_cycle_ns * cpu_clock_khz) / 6) - 1000000; |
| 109 | return (t / 1000000) + (((t % 1000000) == 0) ? 0 : 1); |
| 110 | } |
| 111 | |
| 112 | /* This function returns the (approximate) command assertion period, in |
| 113 | * nanoseconds, for a given CPU clock frequency and MECR BS value: |
| 114 | */ |
| 115 | static inline unsigned int sa1100_pcmcia_cmd_time(unsigned int cpu_clock_khz, |
| 116 | unsigned int pcmcia_mecr_bs){ |
| 117 | return (((10000000 * 2) / cpu_clock_khz) * (3 * (pcmcia_mecr_bs + 1))) / 10; |
| 118 | } |
| 119 | |
| 120 | |
| 121 | extern int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr); |
| 122 | |
| 123 | #endif /* !defined(_PCMCIA_SA1100_H) */ |