blob: add2aa2732f0c56c4324088a1a18b08ec08c7b9a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ipmi_smic_sm.c
3 *
4 * The state-machine driver for an IPMI SMIC driver
5 *
6 * It started as a copy of Corey Minyard's driver for the KSC interface
7 * and the kernel patch "mmcdev-patch-245" by HP
8 *
9 * modified by: Hannes Schulz <schulz@schwaar.com>
10 * ipmi@schwaar.com
11 *
12 *
13 * Corey Minyard's driver for the KSC interface has the following
14 * copyright notice:
15 * Copyright 2002 MontaVista Software Inc.
16 *
17 * the kernel patch "mmcdev-patch-245" by HP has the following
18 * copyright notice:
19 * (c) Copyright 2001 Grant Grundler (c) Copyright
20 * 2001 Hewlett-Packard Company
21 *
22 *
23 * This program is free software; you can redistribute it and/or modify it
24 * under the terms of the GNU General Public License as published by the
25 * Free Software Foundation; either version 2 of the License, or (at your
26 * option) any later version.
27 *
28 *
29 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
34 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
35 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
37 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
38 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * You should have received a copy of the GNU General Public License along
41 * with this program; if not, write to the Free Software Foundation, Inc.,
42 * 675 Mass Ave, Cambridge, MA 02139, USA. */
43
44#include <linux/kernel.h> /* For printk. */
45#include <linux/string.h>
46#include <linux/ipmi_msgdefs.h> /* for completion codes */
47#include "ipmi_si_sm.h"
48
Linus Torvalds1da177e2005-04-16 15:20:36 -070049/* smic_debug is a bit-field
50 * SMIC_DEBUG_ENABLE - turned on for now
51 * SMIC_DEBUG_MSG - commands and their responses
52 * SMIC_DEBUG_STATES - state machine
53*/
54#define SMIC_DEBUG_STATES 4
55#define SMIC_DEBUG_MSG 2
56#define SMIC_DEBUG_ENABLE 1
57
58static int smic_debug = 1;
59
60enum smic_states {
61 SMIC_IDLE,
62 SMIC_START_OP,
63 SMIC_OP_OK,
64 SMIC_WRITE_START,
65 SMIC_WRITE_NEXT,
66 SMIC_WRITE_END,
67 SMIC_WRITE2READ,
68 SMIC_READ_START,
69 SMIC_READ_NEXT,
70 SMIC_READ_END,
71 SMIC_HOSED
72};
73
74#define MAX_SMIC_READ_SIZE 80
75#define MAX_SMIC_WRITE_SIZE 80
76#define SMIC_MAX_ERROR_RETRIES 3
77
78/* Timeouts in microseconds. */
79#define SMIC_RETRY_TIMEOUT 100000
80
81/* SMIC Flags Register Bits */
82#define SMIC_RX_DATA_READY 0x80
83#define SMIC_TX_DATA_READY 0x40
84#define SMIC_SMI 0x10
85#define SMIC_EVM_DATA_AVAIL 0x08
86#define SMIC_SMS_DATA_AVAIL 0x04
87#define SMIC_FLAG_BSY 0x01
88
89/* SMIC Error Codes */
90#define EC_NO_ERROR 0x00
91#define EC_ABORTED 0x01
92#define EC_ILLEGAL_CONTROL 0x02
93#define EC_NO_RESPONSE 0x03
94#define EC_ILLEGAL_COMMAND 0x04
95#define EC_BUFFER_FULL 0x05
96
97struct si_sm_data
98{
99 enum smic_states state;
100 struct si_sm_io *io;
101 unsigned char write_data[MAX_SMIC_WRITE_SIZE];
102 int write_pos;
103 int write_count;
104 int orig_write_count;
105 unsigned char read_data[MAX_SMIC_READ_SIZE];
106 int read_pos;
107 int truncated;
108 unsigned int error_retries;
109 long smic_timeout;
110};
111
112static unsigned int init_smic_data (struct si_sm_data *smic,
113 struct si_sm_io *io)
114{
115 smic->state = SMIC_IDLE;
116 smic->io = io;
117 smic->write_pos = 0;
118 smic->write_count = 0;
119 smic->orig_write_count = 0;
120 smic->read_pos = 0;
121 smic->error_retries = 0;
122 smic->truncated = 0;
123 smic->smic_timeout = SMIC_RETRY_TIMEOUT;
124
125 /* We use 3 bytes of I/O. */
126 return 3;
127}
128
129static int start_smic_transaction(struct si_sm_data *smic,
130 unsigned char *data, unsigned int size)
131{
132 unsigned int i;
133
134 if ((size < 2) || (size > MAX_SMIC_WRITE_SIZE)) {
135 return -1;
136 }
137 if ((smic->state != SMIC_IDLE) && (smic->state != SMIC_HOSED)) {
138 return -2;
139 }
140 if (smic_debug & SMIC_DEBUG_MSG) {
141 printk(KERN_INFO "start_smic_transaction -");
142 for (i = 0; i < size; i ++) {
143 printk (" %02x", (unsigned char) (data [i]));
144 }
145 printk ("\n");
146 }
147 smic->error_retries = 0;
148 memcpy(smic->write_data, data, size);
149 smic->write_count = size;
150 smic->orig_write_count = size;
151 smic->write_pos = 0;
152 smic->read_pos = 0;
153 smic->state = SMIC_START_OP;
154 smic->smic_timeout = SMIC_RETRY_TIMEOUT;
155 return 0;
156}
157
158static int smic_get_result(struct si_sm_data *smic,
159 unsigned char *data, unsigned int length)
160{
161 int i;
162
163 if (smic_debug & SMIC_DEBUG_MSG) {
164 printk (KERN_INFO "smic_get result -");
165 for (i = 0; i < smic->read_pos; i ++) {
166 printk (" %02x", (smic->read_data [i]));
167 }
168 printk ("\n");
169 }
170 if (length < smic->read_pos) {
171 smic->read_pos = length;
172 smic->truncated = 1;
173 }
174 memcpy(data, smic->read_data, smic->read_pos);
175
176 if ((length >= 3) && (smic->read_pos < 3)) {
177 data[2] = IPMI_ERR_UNSPECIFIED;
178 smic->read_pos = 3;
179 }
180 if (smic->truncated) {
181 data[2] = IPMI_ERR_MSG_TRUNCATED;
182 smic->truncated = 0;
183 }
184 return smic->read_pos;
185}
186
187static inline unsigned char read_smic_flags(struct si_sm_data *smic)
188{
189 return smic->io->inputb(smic->io, 2);
190}
191
192static inline unsigned char read_smic_status(struct si_sm_data *smic)
193{
194 return smic->io->inputb(smic->io, 1);
195}
196
197static inline unsigned char read_smic_data(struct si_sm_data *smic)
198{
199 return smic->io->inputb(smic->io, 0);
200}
201
202static inline void write_smic_flags(struct si_sm_data *smic,
203 unsigned char flags)
204{
205 smic->io->outputb(smic->io, 2, flags);
206}
207
208static inline void write_smic_control(struct si_sm_data *smic,
209 unsigned char control)
210{
211 smic->io->outputb(smic->io, 1, control);
212}
213
214static inline void write_si_sm_data (struct si_sm_data *smic,
215 unsigned char data)
216{
217 smic->io->outputb(smic->io, 0, data);
218}
219
220static inline void start_error_recovery(struct si_sm_data *smic, char *reason)
221{
222 (smic->error_retries)++;
223 if (smic->error_retries > SMIC_MAX_ERROR_RETRIES) {
224 if (smic_debug & SMIC_DEBUG_ENABLE) {
225 printk(KERN_WARNING
226 "ipmi_smic_drv: smic hosed: %s\n", reason);
227 }
228 smic->state = SMIC_HOSED;
229 } else {
230 smic->write_count = smic->orig_write_count;
231 smic->write_pos = 0;
232 smic->read_pos = 0;
233 smic->state = SMIC_START_OP;
234 smic->smic_timeout = SMIC_RETRY_TIMEOUT;
235 }
236}
237
238static inline void write_next_byte(struct si_sm_data *smic)
239{
240 write_si_sm_data(smic, smic->write_data[smic->write_pos]);
241 (smic->write_pos)++;
242 (smic->write_count)--;
243}
244
245static inline void read_next_byte (struct si_sm_data *smic)
246{
247 if (smic->read_pos >= MAX_SMIC_READ_SIZE) {
248 read_smic_data (smic);
249 smic->truncated = 1;
250 } else {
251 smic->read_data[smic->read_pos] = read_smic_data(smic);
252 (smic->read_pos)++;
253 }
254}
255
256/* SMIC Control/Status Code Components */
257#define SMIC_GET_STATUS 0x00 /* Control form's name */
258#define SMIC_READY 0x00 /* Status form's name */
259#define SMIC_WR_START 0x01 /* Unified Control/Status names... */
260#define SMIC_WR_NEXT 0x02
261#define SMIC_WR_END 0x03
262#define SMIC_RD_START 0x04
263#define SMIC_RD_NEXT 0x05
264#define SMIC_RD_END 0x06
265#define SMIC_CODE_MASK 0x0f
266
267#define SMIC_CONTROL 0x00
268#define SMIC_STATUS 0x80
269#define SMIC_CS_MASK 0x80
270
271#define SMIC_SMS 0x40
272#define SMIC_SMM 0x60
273#define SMIC_STREAM_MASK 0x60
274
275/* SMIC Control Codes */
276#define SMIC_CC_SMS_GET_STATUS (SMIC_CONTROL|SMIC_SMS|SMIC_GET_STATUS)
277#define SMIC_CC_SMS_WR_START (SMIC_CONTROL|SMIC_SMS|SMIC_WR_START)
278#define SMIC_CC_SMS_WR_NEXT (SMIC_CONTROL|SMIC_SMS|SMIC_WR_NEXT)
279#define SMIC_CC_SMS_WR_END (SMIC_CONTROL|SMIC_SMS|SMIC_WR_END)
280#define SMIC_CC_SMS_RD_START (SMIC_CONTROL|SMIC_SMS|SMIC_RD_START)
281#define SMIC_CC_SMS_RD_NEXT (SMIC_CONTROL|SMIC_SMS|SMIC_RD_NEXT)
282#define SMIC_CC_SMS_RD_END (SMIC_CONTROL|SMIC_SMS|SMIC_RD_END)
283
284#define SMIC_CC_SMM_GET_STATUS (SMIC_CONTROL|SMIC_SMM|SMIC_GET_STATUS)
285#define SMIC_CC_SMM_WR_START (SMIC_CONTROL|SMIC_SMM|SMIC_WR_START)
286#define SMIC_CC_SMM_WR_NEXT (SMIC_CONTROL|SMIC_SMM|SMIC_WR_NEXT)
287#define SMIC_CC_SMM_WR_END (SMIC_CONTROL|SMIC_SMM|SMIC_WR_END)
288#define SMIC_CC_SMM_RD_START (SMIC_CONTROL|SMIC_SMM|SMIC_RD_START)
289#define SMIC_CC_SMM_RD_NEXT (SMIC_CONTROL|SMIC_SMM|SMIC_RD_NEXT)
290#define SMIC_CC_SMM_RD_END (SMIC_CONTROL|SMIC_SMM|SMIC_RD_END)
291
292/* SMIC Status Codes */
293#define SMIC_SC_SMS_READY (SMIC_STATUS|SMIC_SMS|SMIC_READY)
294#define SMIC_SC_SMS_WR_START (SMIC_STATUS|SMIC_SMS|SMIC_WR_START)
295#define SMIC_SC_SMS_WR_NEXT (SMIC_STATUS|SMIC_SMS|SMIC_WR_NEXT)
296#define SMIC_SC_SMS_WR_END (SMIC_STATUS|SMIC_SMS|SMIC_WR_END)
297#define SMIC_SC_SMS_RD_START (SMIC_STATUS|SMIC_SMS|SMIC_RD_START)
298#define SMIC_SC_SMS_RD_NEXT (SMIC_STATUS|SMIC_SMS|SMIC_RD_NEXT)
299#define SMIC_SC_SMS_RD_END (SMIC_STATUS|SMIC_SMS|SMIC_RD_END)
300
301#define SMIC_SC_SMM_READY (SMIC_STATUS|SMIC_SMM|SMIC_READY)
302#define SMIC_SC_SMM_WR_START (SMIC_STATUS|SMIC_SMM|SMIC_WR_START)
303#define SMIC_SC_SMM_WR_NEXT (SMIC_STATUS|SMIC_SMM|SMIC_WR_NEXT)
304#define SMIC_SC_SMM_WR_END (SMIC_STATUS|SMIC_SMM|SMIC_WR_END)
305#define SMIC_SC_SMM_RD_START (SMIC_STATUS|SMIC_SMM|SMIC_RD_START)
306#define SMIC_SC_SMM_RD_NEXT (SMIC_STATUS|SMIC_SMM|SMIC_RD_NEXT)
307#define SMIC_SC_SMM_RD_END (SMIC_STATUS|SMIC_SMM|SMIC_RD_END)
308
309/* these are the control/status codes we actually use
310 SMIC_CC_SMS_GET_STATUS 0x40
311 SMIC_CC_SMS_WR_START 0x41
312 SMIC_CC_SMS_WR_NEXT 0x42
313 SMIC_CC_SMS_WR_END 0x43
314 SMIC_CC_SMS_RD_START 0x44
315 SMIC_CC_SMS_RD_NEXT 0x45
316 SMIC_CC_SMS_RD_END 0x46
317
318 SMIC_SC_SMS_READY 0xC0
319 SMIC_SC_SMS_WR_START 0xC1
320 SMIC_SC_SMS_WR_NEXT 0xC2
321 SMIC_SC_SMS_WR_END 0xC3
322 SMIC_SC_SMS_RD_START 0xC4
323 SMIC_SC_SMS_RD_NEXT 0xC5
324 SMIC_SC_SMS_RD_END 0xC6
325*/
326
327static enum si_sm_result smic_event (struct si_sm_data *smic, long time)
328{
329 unsigned char status;
330 unsigned char flags;
331 unsigned char data;
332
333 if (smic->state == SMIC_HOSED) {
334 init_smic_data(smic, smic->io);
335 return SI_SM_HOSED;
336 }
337 if (smic->state != SMIC_IDLE) {
338 if (smic_debug & SMIC_DEBUG_STATES) {
339 printk(KERN_INFO
340 "smic_event - smic->smic_timeout = %ld,"
341 " time = %ld\n",
342 smic->smic_timeout, time);
343 }
344/* FIXME: smic_event is sometimes called with time > SMIC_RETRY_TIMEOUT */
345 if (time < SMIC_RETRY_TIMEOUT) {
346 smic->smic_timeout -= time;
347 if (smic->smic_timeout < 0) {
348 start_error_recovery(smic, "smic timed out.");
349 return SI_SM_CALL_WITH_DELAY;
350 }
351 }
352 }
353 flags = read_smic_flags(smic);
354 if (flags & SMIC_FLAG_BSY)
355 return SI_SM_CALL_WITH_DELAY;
356
357 status = read_smic_status (smic);
358 if (smic_debug & SMIC_DEBUG_STATES)
359 printk(KERN_INFO
360 "smic_event - state = %d, flags = 0x%02x,"
361 " status = 0x%02x\n",
362 smic->state, flags, status);
363
364 switch (smic->state) {
365 case SMIC_IDLE:
366 /* in IDLE we check for available messages */
367 if (flags & (SMIC_SMI |
368 SMIC_EVM_DATA_AVAIL | SMIC_SMS_DATA_AVAIL))
369 {
370 return SI_SM_ATTN;
371 }
372 return SI_SM_IDLE;
373
374 case SMIC_START_OP:
375 /* sanity check whether smic is really idle */
376 write_smic_control(smic, SMIC_CC_SMS_GET_STATUS);
377 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
378 smic->state = SMIC_OP_OK;
379 break;
380
381 case SMIC_OP_OK:
382 if (status != SMIC_SC_SMS_READY) {
383 /* this should not happen */
384 start_error_recovery(smic,
385 "state = SMIC_OP_OK,"
386 " status != SMIC_SC_SMS_READY");
387 return SI_SM_CALL_WITH_DELAY;
388 }
389 /* OK so far; smic is idle let us start ... */
390 write_smic_control(smic, SMIC_CC_SMS_WR_START);
391 write_next_byte(smic);
392 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
393 smic->state = SMIC_WRITE_START;
394 break;
395
396 case SMIC_WRITE_START:
397 if (status != SMIC_SC_SMS_WR_START) {
398 start_error_recovery(smic,
399 "state = SMIC_WRITE_START, "
400 "status != SMIC_SC_SMS_WR_START");
401 return SI_SM_CALL_WITH_DELAY;
402 }
403 /* we must not issue WR_(NEXT|END) unless
404 TX_DATA_READY is set */
405 if (flags & SMIC_TX_DATA_READY) {
406 if (smic->write_count == 1) {
407 /* last byte */
408 write_smic_control(smic, SMIC_CC_SMS_WR_END);
409 smic->state = SMIC_WRITE_END;
410 } else {
411 write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
412 smic->state = SMIC_WRITE_NEXT;
413 }
414 write_next_byte(smic);
415 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
416 }
417 else {
418 return SI_SM_CALL_WITH_DELAY;
419 }
420 break;
421
422 case SMIC_WRITE_NEXT:
423 if (status != SMIC_SC_SMS_WR_NEXT) {
424 start_error_recovery(smic,
425 "state = SMIC_WRITE_NEXT, "
426 "status != SMIC_SC_SMS_WR_NEXT");
427 return SI_SM_CALL_WITH_DELAY;
428 }
429 /* this is the same code as in SMIC_WRITE_START */
430 if (flags & SMIC_TX_DATA_READY) {
431 if (smic->write_count == 1) {
432 write_smic_control(smic, SMIC_CC_SMS_WR_END);
433 smic->state = SMIC_WRITE_END;
434 }
435 else {
436 write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
437 smic->state = SMIC_WRITE_NEXT;
438 }
439 write_next_byte(smic);
440 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
441 }
442 else {
443 return SI_SM_CALL_WITH_DELAY;
444 }
445 break;
446
447 case SMIC_WRITE_END:
448 if (status != SMIC_SC_SMS_WR_END) {
449 start_error_recovery (smic,
450 "state = SMIC_WRITE_END, "
451 "status != SMIC_SC_SMS_WR_END");
452 return SI_SM_CALL_WITH_DELAY;
453 }
454 /* data register holds an error code */
455 data = read_smic_data(smic);
456 if (data != 0) {
457 if (smic_debug & SMIC_DEBUG_ENABLE) {
458 printk(KERN_INFO
459 "SMIC_WRITE_END: data = %02x\n", data);
460 }
461 start_error_recovery(smic,
462 "state = SMIC_WRITE_END, "
463 "data != SUCCESS");
464 return SI_SM_CALL_WITH_DELAY;
465 } else {
466 smic->state = SMIC_WRITE2READ;
467 }
468 break;
469
470 case SMIC_WRITE2READ:
471 /* we must wait for RX_DATA_READY to be set before we
472 can continue */
473 if (flags & SMIC_RX_DATA_READY) {
474 write_smic_control(smic, SMIC_CC_SMS_RD_START);
475 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
476 smic->state = SMIC_READ_START;
477 } else {
478 return SI_SM_CALL_WITH_DELAY;
479 }
480 break;
481
482 case SMIC_READ_START:
483 if (status != SMIC_SC_SMS_RD_START) {
484 start_error_recovery(smic,
485 "state = SMIC_READ_START, "
486 "status != SMIC_SC_SMS_RD_START");
487 return SI_SM_CALL_WITH_DELAY;
488 }
489 if (flags & SMIC_RX_DATA_READY) {
490 read_next_byte(smic);
491 write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
492 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
493 smic->state = SMIC_READ_NEXT;
494 } else {
495 return SI_SM_CALL_WITH_DELAY;
496 }
497 break;
498
499 case SMIC_READ_NEXT:
500 switch (status) {
501 /* smic tells us that this is the last byte to be read
502 --> clean up */
503 case SMIC_SC_SMS_RD_END:
504 read_next_byte(smic);
505 write_smic_control(smic, SMIC_CC_SMS_RD_END);
506 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
507 smic->state = SMIC_READ_END;
508 break;
509 case SMIC_SC_SMS_RD_NEXT:
510 if (flags & SMIC_RX_DATA_READY) {
511 read_next_byte(smic);
512 write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
513 write_smic_flags(smic, flags | SMIC_FLAG_BSY);
514 smic->state = SMIC_READ_NEXT;
515 } else {
516 return SI_SM_CALL_WITH_DELAY;
517 }
518 break;
519 default:
520 start_error_recovery(
521 smic,
522 "state = SMIC_READ_NEXT, "
523 "status != SMIC_SC_SMS_RD_(NEXT|END)");
524 return SI_SM_CALL_WITH_DELAY;
525 }
526 break;
527
528 case SMIC_READ_END:
529 if (status != SMIC_SC_SMS_READY) {
530 start_error_recovery(smic,
531 "state = SMIC_READ_END, "
532 "status != SMIC_SC_SMS_READY");
533 return SI_SM_CALL_WITH_DELAY;
534 }
535 data = read_smic_data(smic);
536 /* data register holds an error code */
537 if (data != 0) {
538 if (smic_debug & SMIC_DEBUG_ENABLE) {
539 printk(KERN_INFO
540 "SMIC_READ_END: data = %02x\n", data);
541 }
542 start_error_recovery(smic,
543 "state = SMIC_READ_END, "
544 "data != SUCCESS");
545 return SI_SM_CALL_WITH_DELAY;
546 } else {
547 smic->state = SMIC_IDLE;
548 return SI_SM_TRANSACTION_COMPLETE;
549 }
550
551 case SMIC_HOSED:
552 init_smic_data(smic, smic->io);
553 return SI_SM_HOSED;
554
555 default:
556 if (smic_debug & SMIC_DEBUG_ENABLE) {
557 printk(KERN_WARNING "smic->state = %d\n", smic->state);
558 start_error_recovery(smic, "state = UNKNOWN");
559 return SI_SM_CALL_WITH_DELAY;
560 }
561 }
562 smic->smic_timeout = SMIC_RETRY_TIMEOUT;
563 return SI_SM_CALL_WITHOUT_DELAY;
564}
565
566static int smic_detect(struct si_sm_data *smic)
567{
568 /* It's impossible for the SMIC fnags register to be all 1's,
569 (assuming a properly functioning, self-initialized BMC)
570 but that's what you get from reading a bogus address, so we
571 test that first. */
572 if (read_smic_flags(smic) == 0xff)
573 return 1;
574
575 return 0;
576}
577
578static void smic_cleanup(struct si_sm_data *kcs)
579{
580}
581
582static int smic_size(void)
583{
584 return sizeof(struct si_sm_data);
585}
586
587struct si_sm_handlers smic_smi_handlers =
588{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589 .init_data = init_smic_data,
590 .start_transaction = start_smic_transaction,
591 .get_result = smic_get_result,
592 .event = smic_event,
593 .detect = smic_detect,
594 .cleanup = smic_cleanup,
595 .size = smic_size,
596};