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gerrit-public.fairphone.software / kernel / msm / 0e4d5502b8e830f1b1c14563fb96007a0e1b01c1 / . / arch / arm / plat-samsung / include / plat / s3c64xx-spi.h
blob: fa95e9a009729f41ddd1c39174e4f6908f515226 [file] [log] [blame]
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]1/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S3C64XX_PLAT_SPI_H
12#define __S3C64XX_PLAT_SPI_H
13
Mark Brown5b0b34e2011-12-29 18:01:08 +0900[diff] [blame]14struct platform_device;
15
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]16/**
17 * struct s3c64xx_spi_csinfo - ChipSelect description
18 * @fb_delay: Slave specific feedback delay.
19 * Refer to FB_CLK_SEL register definition in SPI chapter.
20 * @line: Custom 'identity' of the CS line.
21 * @set_level: CS line control.
22 *
23 * This is per SPI-Slave Chipselect information.
24 * Allocate and initialize one in machine init code and make the
25 * spi_board_info.controller_data point to it.
26 */
27struct s3c64xx_spi_csinfo {
28 u8 fb_delay;
29 unsigned line;
30 void (*set_level)(unsigned line_id, int lvl);
31};
32
33/**
34 * struct s3c64xx_spi_info - SPI Controller defining structure
35 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
Jassi Brarb42a81c2010-09-29 17:31:33 +0900[diff] [blame]36 * @clk_from_cmu: If the SPI clock/prescalar control block is present
37 * by the platform's clock-management-unit and not in SPI controller.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]38 * @num_cs: Number of CS this controller emulates.
39 * @cfg_gpio: Configure pins for this SPI controller.
40 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
41 * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
42 * @high_speed: If the controller supports HIGH_SPEED_EN bit
Padmavathi Venna89180342011-07-05 17:13:56 +0900[diff] [blame]43 * @tx_st_done: Depends on tx fifo_lvl field
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]44 */
45struct s3c64xx_spi_info {
46 int src_clk_nr;
Jassi Brarb42a81c2010-09-29 17:31:33 +0900[diff] [blame]47 bool clk_from_cmu;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]48
49 int num_cs;
50
51 int (*cfg_gpio)(struct platform_device *pdev);
52
53 /* Following two fields are for future compatibility */
54 int fifo_lvl_mask;
55 int rx_lvl_offset;
56 int high_speed;
Padmavathi Venna89180342011-07-05 17:13:56 +0900[diff] [blame]57 int tx_st_done;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]58};
59
60/**
Padmavathi Venna875a5932011-12-23 10:14:31 +0900[diff] [blame]61 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]62 * initialization code.
Padmavathi Venna875a5932011-12-23 10:14:31 +0900[diff] [blame]63 * @pd: SPI platform data to set.
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]64 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
65 * @num_cs: Number of elements in the 'cs' array.
66 *
67 * Call this from machine init code for each SPI Controller that
68 * has some chips attached to it.
69 */
Padmavathi Venna875a5932011-12-23 10:14:31 +0900[diff] [blame]70extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
71 int src_clk_nr, int num_cs);
72extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
73 int src_clk_nr, int num_cs);
74extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
75 int src_clk_nr, int num_cs);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +0900[diff] [blame]76
77/* defined by architecture to configure gpio */
78extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
79extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
Padmavathi Venna323d7712011-12-23 10:14:45 +0900[diff] [blame]80extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
Padmavathi Venna4566c7f2011-12-23 10:14:36 +0900[diff] [blame]81
82extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
83extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
Padmavathi Venna323d7712011-12-23 10:14:45 +0900[diff] [blame]84extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
Jassi Brar398cccc2010-01-18 17:45:52 +0900[diff] [blame]85#endif /* __S3C64XX_PLAT_SPI_H */