Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap24xx/clock.h |
| 3 | * |
| 4 | * Copyright (C) 2005 Texas Instruments Inc. |
| 5 | * Richard Woodruff <r-woodruff2@ti.com> |
| 6 | * Created for OMAP2. |
| 7 | * |
| 8 | * Copyright (C) 2004 Nokia corporation |
| 9 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
| 10 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. |
| 15 | */ |
| 16 | |
| 17 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 18 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 19 | |
| 20 | static void omap2_sys_clk_recalc(struct clk * clk); |
| 21 | static void omap2_clksel_recalc(struct clk * clk); |
| 22 | static void omap2_followparent_recalc(struct clk * clk); |
| 23 | static void omap2_propagate_rate(struct clk * clk); |
| 24 | static void omap2_mpu_recalc(struct clk * clk); |
| 25 | static int omap2_select_table_rate(struct clk * clk, unsigned long rate); |
| 26 | static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate); |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 27 | static void omap2_clk_disable(struct clk *clk); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 28 | static void omap2_sys_clk_recalc(struct clk * clk); |
| 29 | static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val); |
| 30 | static u32 omap2_clksel_get_divisor(struct clk *clk); |
| 31 | |
| 32 | |
| 33 | #define RATE_IN_242X (1 << 0) |
| 34 | #define RATE_IN_243X (1 << 1) |
| 35 | |
| 36 | /* Memory timings */ |
| 37 | #define M_DDR 1 |
| 38 | #define M_LOCK_CTRL (1 << 2) |
| 39 | #define M_UNLOCK 0 |
| 40 | #define M_LOCK 1 |
| 41 | |
| 42 | struct memory_timings { |
| 43 | u32 m_type; /* ddr = 1, sdr = 0 */ |
| 44 | u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ |
| 45 | u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ |
| 46 | u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ |
| 47 | u32 base_cs; /* base chip select to use for calculations */ |
| 48 | }; |
| 49 | |
| 50 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. |
| 51 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP |
| 52 | * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM |
| 53 | */ |
| 54 | struct prcm_config { |
| 55 | unsigned long xtal_speed; /* crystal rate */ |
| 56 | unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */ |
| 57 | unsigned long mpu_speed; /* speed of MPU */ |
| 58 | unsigned long cm_clksel_mpu; /* mpu divider */ |
| 59 | unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */ |
| 60 | unsigned long cm_clksel_gfx; /* gfx dividers */ |
| 61 | unsigned long cm_clksel1_core; /* major subsystem dividers */ |
| 62 | unsigned long cm_clksel1_pll; /* m,n */ |
| 63 | unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */ |
| 64 | unsigned long cm_clksel_mdm; /* modem dividers 2430 only */ |
| 65 | unsigned long base_sdrc_rfr; /* base refresh timing for a set */ |
| 66 | unsigned char flags; |
| 67 | }; |
| 68 | |
| 69 | /* Mask for clksel which support parent settign in set_rate */ |
| 70 | #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \ |
| 71 | CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1) |
| 72 | |
| 73 | /* Mask for clksel regs which support rate operations */ |
| 74 | #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \ |
| 75 | CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \ |
| 76 | CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \ |
| 77 | CM_SYSCLKOUT_SEL1) |
| 78 | |
| 79 | /* |
| 80 | * The OMAP2 processor can be run at several discrete 'PRCM configurations'. |
| 81 | * These configurations are characterized by voltage and speed for clocks. |
| 82 | * The device is only validated for certain combinations. One way to express |
| 83 | * these combinations is via the 'ratio's' which the clocks operate with |
| 84 | * respect to each other. These ratio sets are for a given voltage/DPLL |
| 85 | * setting. All configurations can be described by a DPLL setting and a ratio |
| 86 | * There are 3 ratio sets for the 2430 and X ratio sets for 2420. |
| 87 | * |
| 88 | * 2430 differs from 2420 in that there are no more phase synchronizers used. |
| 89 | * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs |
| 90 | * 2430 (iva2.1, NOdsp, mdm) |
| 91 | */ |
| 92 | |
| 93 | /* Core fields for cm_clksel, not ratio governed */ |
| 94 | #define RX_CLKSEL_DSS1 (0x10 << 8) |
| 95 | #define RX_CLKSEL_DSS2 (0x0 << 13) |
| 96 | #define RX_CLKSEL_SSI (0x5 << 20) |
| 97 | |
| 98 | /*------------------------------------------------------------------------- |
| 99 | * Voltage/DPLL ratios |
| 100 | *-------------------------------------------------------------------------*/ |
| 101 | |
| 102 | /* 2430 Ratio's, 2430-Ratio Config 1 */ |
| 103 | #define R1_CLKSEL_L3 (4 << 0) |
| 104 | #define R1_CLKSEL_L4 (2 << 5) |
| 105 | #define R1_CLKSEL_USB (4 << 25) |
| 106 | #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \ |
| 107 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
| 108 | R1_CLKSEL_L4 | R1_CLKSEL_L3 |
| 109 | #define R1_CLKSEL_MPU (2 << 0) |
| 110 | #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU |
| 111 | #define R1_CLKSEL_DSP (2 << 0) |
| 112 | #define R1_CLKSEL_DSP_IF (2 << 5) |
| 113 | #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF |
| 114 | #define R1_CLKSEL_GFX (2 << 0) |
| 115 | #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX |
| 116 | #define R1_CLKSEL_MDM (4 << 0) |
| 117 | #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM |
| 118 | |
| 119 | /* 2430-Ratio Config 2 */ |
| 120 | #define R2_CLKSEL_L3 (6 << 0) |
| 121 | #define R2_CLKSEL_L4 (2 << 5) |
| 122 | #define R2_CLKSEL_USB (2 << 25) |
| 123 | #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \ |
| 124 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
| 125 | R2_CLKSEL_L4 | R2_CLKSEL_L3 |
| 126 | #define R2_CLKSEL_MPU (2 << 0) |
| 127 | #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU |
| 128 | #define R2_CLKSEL_DSP (2 << 0) |
| 129 | #define R2_CLKSEL_DSP_IF (3 << 5) |
| 130 | #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF |
| 131 | #define R2_CLKSEL_GFX (2 << 0) |
| 132 | #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX |
| 133 | #define R2_CLKSEL_MDM (6 << 0) |
| 134 | #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM |
| 135 | |
| 136 | /* 2430-Ratio Bootm (BYPASS) */ |
| 137 | #define RB_CLKSEL_L3 (1 << 0) |
| 138 | #define RB_CLKSEL_L4 (1 << 5) |
| 139 | #define RB_CLKSEL_USB (1 << 25) |
| 140 | #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \ |
| 141 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
| 142 | RB_CLKSEL_L4 | RB_CLKSEL_L3 |
| 143 | #define RB_CLKSEL_MPU (1 << 0) |
| 144 | #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU |
| 145 | #define RB_CLKSEL_DSP (1 << 0) |
| 146 | #define RB_CLKSEL_DSP_IF (1 << 5) |
| 147 | #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF |
| 148 | #define RB_CLKSEL_GFX (1 << 0) |
| 149 | #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX |
| 150 | #define RB_CLKSEL_MDM (1 << 0) |
| 151 | #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM |
| 152 | |
| 153 | /* 2420 Ratio Equivalents */ |
| 154 | #define RXX_CLKSEL_VLYNQ (0x12 << 15) |
| 155 | #define RXX_CLKSEL_SSI (0x8 << 20) |
| 156 | |
| 157 | /* 2420-PRCM III 532MHz core */ |
| 158 | #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */ |
| 159 | #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */ |
| 160 | #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */ |
| 161 | #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \ |
| 162 | RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \ |
| 163 | RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \ |
| 164 | RIII_CLKSEL_L3 |
| 165 | #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */ |
| 166 | #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU |
| 167 | #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */ |
| 168 | #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */ |
| 169 | #define RIII_SYNC_DSP (1 << 7) /* Enable sync */ |
| 170 | #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */ |
| 171 | #define RIII_SYNC_IVA (1 << 13) /* Enable sync */ |
| 172 | #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \ |
| 173 | RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \ |
| 174 | RIII_CLKSEL_DSP |
| 175 | #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */ |
| 176 | #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX |
| 177 | |
| 178 | /* 2420-PRCM II 600MHz core */ |
| 179 | #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */ |
| 180 | #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */ |
| 181 | #define RII_CLKSEL_USB (2 << 25) /* 50MHz */ |
| 182 | #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \ |
| 183 | RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \ |
| 184 | RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \ |
| 185 | RII_CLKSEL_L4 | RII_CLKSEL_L3 |
| 186 | #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */ |
| 187 | #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU |
| 188 | #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */ |
| 189 | #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */ |
| 190 | #define RII_SYNC_DSP (0 << 7) /* Bypass sync */ |
| 191 | #define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */ |
| 192 | #define RII_SYNC_IVA (0 << 13) /* Bypass sync */ |
| 193 | #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \ |
| 194 | RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \ |
| 195 | RII_CLKSEL_DSP |
| 196 | #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */ |
| 197 | #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX |
| 198 | |
| 199 | /* 2420-PRCM VII (boot) */ |
| 200 | #define RVII_CLKSEL_L3 (1 << 0) |
| 201 | #define RVII_CLKSEL_L4 (1 << 5) |
| 202 | #define RVII_CLKSEL_DSS1 (1 << 8) |
| 203 | #define RVII_CLKSEL_DSS2 (0 << 13) |
| 204 | #define RVII_CLKSEL_VLYNQ (1 << 15) |
| 205 | #define RVII_CLKSEL_SSI (1 << 20) |
| 206 | #define RVII_CLKSEL_USB (1 << 25) |
| 207 | |
| 208 | #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \ |
| 209 | RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \ |
| 210 | RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3 |
| 211 | |
| 212 | #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */ |
| 213 | #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU |
| 214 | |
| 215 | #define RVII_CLKSEL_DSP (1 << 0) |
| 216 | #define RVII_CLKSEL_DSP_IF (1 << 5) |
| 217 | #define RVII_SYNC_DSP (0 << 7) |
| 218 | #define RVII_CLKSEL_IVA (1 << 8) |
| 219 | #define RVII_SYNC_IVA (0 << 13) |
| 220 | #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \ |
| 221 | RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP |
| 222 | |
| 223 | #define RVII_CLKSEL_GFX (1 << 0) |
| 224 | #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX |
| 225 | |
| 226 | /*------------------------------------------------------------------------- |
| 227 | * 2430 Target modes: Along with each configuration the CPU has several |
| 228 | * modes which goes along with them. Modes mainly are the addition of |
| 229 | * describe DPLL combinations to go along with a ratio. |
| 230 | *-------------------------------------------------------------------------*/ |
| 231 | |
| 232 | /* Hardware governed */ |
| 233 | #define MX_48M_SRC (0 << 3) |
| 234 | #define MX_54M_SRC (0 << 5) |
| 235 | #define MX_APLLS_CLIKIN_12 (3 << 23) |
| 236 | #define MX_APLLS_CLIKIN_13 (2 << 23) |
| 237 | #define MX_APLLS_CLIKIN_19_2 (0 << 23) |
| 238 | |
| 239 | /* |
| 240 | * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed |
| 241 | * #2 (ratio1) baseport-target |
| 242 | * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz |
| 243 | */ |
| 244 | #define M5A_DPLL_MULT_12 (133 << 12) |
| 245 | #define M5A_DPLL_DIV_12 (5 << 8) |
| 246 | #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 247 | M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \ |
| 248 | MX_APLLS_CLIKIN_12 |
| 249 | #define M5A_DPLL_MULT_13 (266 << 12) |
| 250 | #define M5A_DPLL_DIV_13 (12 << 8) |
| 251 | #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 252 | M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \ |
| 253 | MX_APLLS_CLIKIN_13 |
| 254 | #define M5A_DPLL_MULT_19 (180 << 12) |
| 255 | #define M5A_DPLL_DIV_19 (12 << 8) |
| 256 | #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 257 | M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \ |
| 258 | MX_APLLS_CLIKIN_19_2 |
| 259 | /* #5b (ratio1) target DPLL = 200*2 = 400MHz */ |
| 260 | #define M5B_DPLL_MULT_12 (50 << 12) |
| 261 | #define M5B_DPLL_DIV_12 (2 << 8) |
| 262 | #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 263 | M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \ |
| 264 | MX_APLLS_CLIKIN_12 |
| 265 | #define M5B_DPLL_MULT_13 (200 << 12) |
| 266 | #define M5B_DPLL_DIV_13 (12 << 8) |
| 267 | |
| 268 | #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 269 | M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \ |
| 270 | MX_APLLS_CLIKIN_13 |
| 271 | #define M5B_DPLL_MULT_19 (125 << 12) |
| 272 | #define M5B_DPLL_DIV_19 (31 << 8) |
| 273 | #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 274 | M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \ |
| 275 | MX_APLLS_CLIKIN_19_2 |
| 276 | /* |
| 277 | * #4 (ratio2) |
| 278 | * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz |
| 279 | */ |
| 280 | #define M3_DPLL_MULT_12 (55 << 12) |
| 281 | #define M3_DPLL_DIV_12 (1 << 8) |
| 282 | #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 283 | M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \ |
| 284 | MX_APLLS_CLIKIN_12 |
| 285 | #define M3_DPLL_MULT_13 (330 << 12) |
| 286 | #define M3_DPLL_DIV_13 (12 << 8) |
| 287 | #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 288 | M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \ |
| 289 | MX_APLLS_CLIKIN_13 |
| 290 | #define M3_DPLL_MULT_19 (275 << 12) |
| 291 | #define M3_DPLL_DIV_19 (15 << 8) |
| 292 | #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 293 | M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \ |
| 294 | MX_APLLS_CLIKIN_19_2 |
| 295 | /* boot (boot) */ |
| 296 | #define MB_DPLL_MULT (1 << 12) |
| 297 | #define MB_DPLL_DIV (0 << 8) |
| 298 | #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ |
| 299 | MB_DPLL_MULT | MX_APLLS_CLIKIN_12 |
| 300 | |
| 301 | #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ |
| 302 | MB_DPLL_MULT | MX_APLLS_CLIKIN_13 |
| 303 | |
| 304 | #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\ |
| 305 | MB_DPLL_MULT | MX_APLLS_CLIKIN_19 |
| 306 | |
| 307 | /* |
| 308 | * 2430 - chassis (sedna) |
| 309 | * 165 (ratio1) same as above #2 |
| 310 | * 150 (ratio1) |
| 311 | * 133 (ratio2) same as above #4 |
| 312 | * 110 (ratio2) same as above #3 |
| 313 | * 104 (ratio2) |
| 314 | * boot (boot) |
| 315 | */ |
| 316 | |
| 317 | /* |
| 318 | * 2420 Equivalent - mode registers |
| 319 | * PRCM II , target DPLL = 2*300MHz = 600MHz |
| 320 | */ |
| 321 | #define MII_DPLL_MULT_12 (50 << 12) |
| 322 | #define MII_DPLL_DIV_12 (1 << 8) |
| 323 | #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 324 | MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \ |
| 325 | MX_APLLS_CLIKIN_12 |
| 326 | #define MII_DPLL_MULT_13 (300 << 12) |
| 327 | #define MII_DPLL_DIV_13 (12 << 8) |
| 328 | #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 329 | MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \ |
| 330 | MX_APLLS_CLIKIN_13 |
| 331 | |
| 332 | /* PRCM III target DPLL = 2*266 = 532MHz*/ |
| 333 | #define MIII_DPLL_MULT_12 (133 << 12) |
| 334 | #define MIII_DPLL_DIV_12 (5 << 8) |
| 335 | #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 336 | MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \ |
| 337 | MX_APLLS_CLIKIN_12 |
| 338 | #define MIII_DPLL_MULT_13 (266 << 12) |
| 339 | #define MIII_DPLL_DIV_13 (12 << 8) |
| 340 | #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \ |
| 341 | MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \ |
| 342 | MX_APLLS_CLIKIN_13 |
| 343 | |
| 344 | /* PRCM VII (boot bypass) */ |
| 345 | #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL |
| 346 | #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL |
| 347 | |
| 348 | /* High and low operation value */ |
| 349 | #define MX_CLKSEL2_PLL_2x_VAL (2 << 0) |
| 350 | #define MX_CLKSEL2_PLL_1x_VAL (1 << 0) |
| 351 | |
| 352 | /* |
| 353 | * These represent optimal values for common parts, it won't work for all. |
| 354 | * As long as you scale down, most parameters are still work, they just |
| 355 | * become sub-optimal. The RFR value goes in the oppisite direction. If you |
| 356 | * don't adjust it down as your clock period increases the refresh interval |
| 357 | * will not be met. Setting all parameters for complete worst case may work, |
| 358 | * but may cut memory performance by 2x. Due to errata the DLLs need to be |
| 359 | * unlocked and their value needs run time calibration. A dynamic call is |
| 360 | * need for that as no single right value exists acorss production samples. |
| 361 | * |
| 362 | * Only the FULL speed values are given. Current code is such that rate |
| 363 | * changes must be made at DPLLoutx2. The actual value adjustment for low |
| 364 | * frequency operation will be handled by omap_set_performance() |
| 365 | * |
| 366 | * By having the boot loader boot up in the fastest L4 speed available likely |
| 367 | * will result in something which you can switch between. |
| 368 | */ |
| 369 | #define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) |
| 370 | #define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) |
| 371 | #define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ |
| 372 | #define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ |
| 373 | |
| 374 | /* MPU speed defines */ |
| 375 | #define S12M 12000000 |
| 376 | #define S13M 13000000 |
| 377 | #define S19M 19200000 |
| 378 | #define S26M 26000000 |
| 379 | #define S100M 100000000 |
| 380 | #define S133M 133000000 |
| 381 | #define S150M 150000000 |
| 382 | #define S165M 165000000 |
| 383 | #define S200M 200000000 |
| 384 | #define S266M 266000000 |
| 385 | #define S300M 300000000 |
| 386 | #define S330M 330000000 |
| 387 | #define S400M 400000000 |
| 388 | #define S532M 532000000 |
| 389 | #define S600M 600000000 |
| 390 | #define S660M 660000000 |
| 391 | |
| 392 | /*------------------------------------------------------------------------- |
| 393 | * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. |
| 394 | * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, |
| 395 | * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, |
| 396 | * CM_CLKSEL2_PLL, CM_CLKSEL_MDM |
| 397 | * |
| 398 | * Filling in table based on H4 boards and 2430-SDPs variants available. |
| 399 | * There are quite a few more rates combinations which could be defined. |
| 400 | * |
| 401 | * When multiple values are defiend the start up will try and choose the |
| 402 | * fastest one. If a 'fast' value is defined, then automatically, the /2 |
| 403 | * one should be included as it can be used. Generally having more that |
| 404 | * one fast set does not make sense, as static timings need to be changed |
| 405 | * to change the set. The exception is the bypass setting which is |
| 406 | * availble for low power bypass. |
| 407 | * |
| 408 | * Note: This table needs to be sorted, fastest to slowest. |
| 409 | *-------------------------------------------------------------------------*/ |
| 410 | static struct prcm_config rate_table[] = { |
| 411 | /* PRCM II - FAST */ |
| 412 | {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ |
| 413 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
| 414 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, |
| 415 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, |
| 416 | RATE_IN_242X}, |
| 417 | |
| 418 | {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ |
| 419 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
| 420 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, |
| 421 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, |
| 422 | RATE_IN_242X}, |
| 423 | |
| 424 | /* PRCM III - FAST */ |
| 425 | {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ |
| 426 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
| 427 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, |
| 428 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, |
| 429 | RATE_IN_242X}, |
| 430 | |
| 431 | {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ |
| 432 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
| 433 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, |
| 434 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, |
| 435 | RATE_IN_242X}, |
| 436 | |
| 437 | /* PRCM II - SLOW */ |
| 438 | {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ |
| 439 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
| 440 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, |
| 441 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, |
| 442 | RATE_IN_242X}, |
| 443 | |
| 444 | {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ |
| 445 | RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, |
| 446 | RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, |
| 447 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz, |
| 448 | RATE_IN_242X}, |
| 449 | |
| 450 | /* PRCM III - SLOW */ |
| 451 | {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ |
| 452 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
| 453 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, |
| 454 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, |
| 455 | RATE_IN_242X}, |
| 456 | |
| 457 | {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ |
| 458 | RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, |
| 459 | RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, |
| 460 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz, |
| 461 | RATE_IN_242X}, |
| 462 | |
| 463 | /* PRCM-VII (boot-bypass) */ |
| 464 | {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ |
| 465 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, |
| 466 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, |
| 467 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS, |
| 468 | RATE_IN_242X}, |
| 469 | |
| 470 | /* PRCM-VII (boot-bypass) */ |
| 471 | {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ |
| 472 | RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, |
| 473 | RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, |
| 474 | MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS, |
| 475 | RATE_IN_242X}, |
| 476 | |
| 477 | /* PRCM #3 - ratio2 (ES2) - FAST */ |
| 478 | {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ |
| 479 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, |
| 480 | R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL, |
| 481 | MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, |
| 482 | V24XX_SDRC_RFR_CTRL_110MHz, |
| 483 | RATE_IN_243X}, |
| 484 | |
| 485 | /* PRCM #5a - ratio1 - FAST */ |
| 486 | {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ |
| 487 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 488 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, |
| 489 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, |
| 490 | V24XX_SDRC_RFR_CTRL_133MHz, |
| 491 | RATE_IN_243X}, |
| 492 | |
| 493 | /* PRCM #5b - ratio1 - FAST */ |
| 494 | {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ |
| 495 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 496 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, |
| 497 | MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, |
| 498 | V24XX_SDRC_RFR_CTRL_100MHz, |
| 499 | RATE_IN_243X}, |
| 500 | |
| 501 | /* PRCM #3 - ratio2 (ES2) - SLOW */ |
| 502 | {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ |
| 503 | R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, |
| 504 | R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL, |
| 505 | MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, |
| 506 | V24XX_SDRC_RFR_CTRL_110MHz, |
| 507 | RATE_IN_243X}, |
| 508 | |
| 509 | /* PRCM #5a - ratio1 - SLOW */ |
| 510 | {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ |
| 511 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 512 | R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, |
| 513 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, |
| 514 | V24XX_SDRC_RFR_CTRL_133MHz, |
| 515 | RATE_IN_243X}, |
| 516 | |
| 517 | /* PRCM #5b - ratio1 - SLOW*/ |
| 518 | {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ |
| 519 | R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, |
| 520 | R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, |
| 521 | MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, |
| 522 | V24XX_SDRC_RFR_CTRL_100MHz, |
| 523 | RATE_IN_243X}, |
| 524 | |
| 525 | /* PRCM-boot/bypass */ |
| 526 | {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ |
| 527 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, |
| 528 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, |
| 529 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, |
| 530 | V24XX_SDRC_RFR_CTRL_BYPASS, |
| 531 | RATE_IN_243X}, |
| 532 | |
| 533 | /* PRCM-boot/bypass */ |
| 534 | {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ |
| 535 | RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, |
| 536 | RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, |
| 537 | MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, |
| 538 | V24XX_SDRC_RFR_CTRL_BYPASS, |
| 539 | RATE_IN_243X}, |
| 540 | |
| 541 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
| 542 | }; |
| 543 | |
| 544 | /*------------------------------------------------------------------------- |
| 545 | * 24xx clock tree. |
| 546 | * |
| 547 | * NOTE:In many cases here we are assigning a 'default' parent. In many |
| 548 | * cases the parent is selectable. The get/set parent calls will also |
| 549 | * switch sources. |
| 550 | * |
| 551 | * Many some clocks say always_enabled, but they can be auto idled for |
| 552 | * power savings. They will always be available upon clock request. |
| 553 | * |
| 554 | * Several sources are given initial rates which may be wrong, this will |
| 555 | * be fixed up in the init func. |
| 556 | * |
| 557 | * Things are broadly separated below by clock domains. It is |
| 558 | * noteworthy that most periferals have dependencies on multiple clock |
| 559 | * domains. Many get their interface clocks from the L4 domain, but get |
| 560 | * functional clocks from fixed sources or other core domain derived |
| 561 | * clocks. |
| 562 | *-------------------------------------------------------------------------*/ |
| 563 | |
| 564 | /* Base external input clocks */ |
| 565 | static struct clk func_32k_ck = { |
| 566 | .name = "func_32k_ck", |
| 567 | .rate = 32000, |
| 568 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 569 | RATE_FIXED | ALWAYS_ENABLED, |
| 570 | }; |
| 571 | |
| 572 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
| 573 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ |
| 574 | .name = "osc_ck", |
| 575 | .rate = 26000000, /* fixed up in clock init */ |
| 576 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 577 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, |
| 578 | }; |
| 579 | |
| 580 | /* With out modem likely 12MHz, with modem likely 13MHz */ |
| 581 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
| 582 | .name = "sys_ck", /* ~ ref_clk also */ |
| 583 | .parent = &osc_ck, |
| 584 | .rate = 13000000, |
| 585 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 586 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, |
| 587 | .rate_offset = 6, /* sysclkdiv 1 or 2, already handled or no boot */ |
| 588 | .recalc = &omap2_sys_clk_recalc, |
| 589 | }; |
| 590 | |
| 591 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
| 592 | .name = "alt_ck", |
| 593 | .rate = 54000000, |
| 594 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 595 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, |
| 596 | .recalc = &omap2_propagate_rate, |
| 597 | }; |
| 598 | |
| 599 | /* |
| 600 | * Analog domain root source clocks |
| 601 | */ |
| 602 | |
| 603 | /* dpll_ck, is broken out in to special cases through clksel */ |
| 604 | static struct clk dpll_ck = { |
| 605 | .name = "dpll_ck", |
| 606 | .parent = &sys_ck, /* Can be func_32k also */ |
| 607 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 608 | RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1, |
| 609 | .recalc = &omap2_clksel_recalc, |
| 610 | }; |
| 611 | |
| 612 | static struct clk apll96_ck = { |
| 613 | .name = "apll96_ck", |
| 614 | .parent = &sys_ck, |
| 615 | .rate = 96000000, |
| 616 | .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X | |
| 617 | RATE_FIXED | RATE_PROPAGATES, |
| 618 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, |
| 619 | .enable_bit = 0x2, |
| 620 | .recalc = &omap2_propagate_rate, |
| 621 | }; |
| 622 | |
| 623 | static struct clk apll54_ck = { |
| 624 | .name = "apll54_ck", |
| 625 | .parent = &sys_ck, |
| 626 | .rate = 54000000, |
| 627 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 628 | RATE_FIXED | RATE_PROPAGATES, |
| 629 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, |
| 630 | .enable_bit = 0x6, |
| 631 | .recalc = &omap2_propagate_rate, |
| 632 | }; |
| 633 | |
| 634 | /* |
| 635 | * PRCM digital base sources |
| 636 | */ |
| 637 | static struct clk func_54m_ck = { |
| 638 | .name = "func_54m_ck", |
| 639 | .parent = &apll54_ck, /* can also be alt_clk */ |
| 640 | .rate = 54000000, |
| 641 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 642 | RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES, |
| 643 | .src_offset = 5, |
| 644 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, |
| 645 | .enable_bit = 0xff, |
| 646 | .recalc = &omap2_propagate_rate, |
| 647 | }; |
| 648 | |
| 649 | static struct clk core_ck = { |
| 650 | .name = "core_ck", |
| 651 | .parent = &dpll_ck, /* can also be 32k */ |
| 652 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 653 | ALWAYS_ENABLED | RATE_PROPAGATES, |
| 654 | .recalc = &omap2_propagate_rate, |
| 655 | }; |
| 656 | |
| 657 | static struct clk sleep_ck = { /* sys_clk or 32k */ |
| 658 | .name = "sleep_ck", |
| 659 | .parent = &func_32k_ck, |
| 660 | .rate = 32000, |
| 661 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 662 | .recalc = &omap2_propagate_rate, |
| 663 | }; |
| 664 | |
| 665 | static struct clk func_96m_ck = { |
| 666 | .name = "func_96m_ck", |
| 667 | .parent = &apll96_ck, |
| 668 | .rate = 96000000, |
| 669 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 670 | RATE_FIXED | RATE_PROPAGATES, |
| 671 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, |
| 672 | .enable_bit = 0xff, |
| 673 | .recalc = &omap2_propagate_rate, |
| 674 | }; |
| 675 | |
| 676 | static struct clk func_48m_ck = { |
| 677 | .name = "func_48m_ck", |
| 678 | .parent = &apll96_ck, /* 96M or Alt */ |
| 679 | .rate = 48000000, |
| 680 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 681 | RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES, |
| 682 | .src_offset = 3, |
| 683 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, |
| 684 | .enable_bit = 0xff, |
| 685 | .recalc = &omap2_propagate_rate, |
| 686 | }; |
| 687 | |
| 688 | static struct clk func_12m_ck = { |
| 689 | .name = "func_12m_ck", |
| 690 | .parent = &func_48m_ck, |
| 691 | .rate = 12000000, |
| 692 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 693 | RATE_FIXED | RATE_PROPAGATES, |
| 694 | .recalc = &omap2_propagate_rate, |
| 695 | .enable_reg = (void __iomem *)&CM_CLKEN_PLL, |
| 696 | .enable_bit = 0xff, |
| 697 | }; |
| 698 | |
| 699 | /* Secure timer, only available in secure mode */ |
| 700 | static struct clk wdt1_osc_ck = { |
| 701 | .name = "ck_wdt1_osc", |
| 702 | .parent = &osc_ck, |
| 703 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 704 | .recalc = &omap2_followparent_recalc, |
| 705 | }; |
| 706 | |
| 707 | static struct clk sys_clkout = { |
| 708 | .name = "sys_clkout", |
| 709 | .parent = &func_54m_ck, |
| 710 | .rate = 54000000, |
| 711 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 712 | CM_SYSCLKOUT_SEL1 | RATE_CKCTL, |
| 713 | .src_offset = 0, |
| 714 | .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL, |
| 715 | .enable_bit = 7, |
| 716 | .rate_offset = 3, |
| 717 | .recalc = &omap2_clksel_recalc, |
| 718 | }; |
| 719 | |
| 720 | /* In 2430, new in 2420 ES2 */ |
| 721 | static struct clk sys_clkout2 = { |
| 722 | .name = "sys_clkout2", |
| 723 | .parent = &func_54m_ck, |
| 724 | .rate = 54000000, |
| 725 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 726 | CM_SYSCLKOUT_SEL1 | RATE_CKCTL, |
| 727 | .src_offset = 8, |
| 728 | .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL, |
| 729 | .enable_bit = 15, |
| 730 | .rate_offset = 11, |
| 731 | .recalc = &omap2_clksel_recalc, |
| 732 | }; |
| 733 | |
| 734 | /* |
| 735 | * MPU clock domain |
| 736 | * Clocks: |
| 737 | * MPU_FCLK, MPU_ICLK |
| 738 | * INT_M_FCLK, INT_M_I_CLK |
| 739 | * |
| 740 | * - Individual clocks are hardware managed. |
| 741 | * - Base divider comes from: CM_CLKSEL_MPU |
| 742 | * |
| 743 | */ |
| 744 | static struct clk mpu_ck = { /* Control cpu */ |
| 745 | .name = "mpu_ck", |
| 746 | .parent = &core_ck, |
| 747 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL | |
| 748 | ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP | |
| 749 | CONFIG_PARTICIPANT | RATE_PROPAGATES, |
| 750 | .rate_offset = 0, /* bits 0-4 */ |
| 751 | .recalc = &omap2_clksel_recalc, |
| 752 | }; |
| 753 | |
| 754 | /* |
| 755 | * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain |
| 756 | * Clocks: |
| 757 | * 2430: IVA2.1_FCLK, IVA2.1_ICLK |
| 758 | * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP |
| 759 | */ |
| 760 | static struct clk iva2_1_fck = { |
| 761 | .name = "iva2_1_fck", |
| 762 | .parent = &core_ck, |
| 763 | .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 | |
| 764 | DELAYED_APP | RATE_PROPAGATES | |
| 765 | CONFIG_PARTICIPANT, |
| 766 | .rate_offset = 0, |
| 767 | .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, |
| 768 | .enable_bit = 0, |
| 769 | .recalc = &omap2_clksel_recalc, |
| 770 | }; |
| 771 | |
| 772 | static struct clk iva2_1_ick = { |
| 773 | .name = "iva2_1_ick", |
| 774 | .parent = &iva2_1_fck, |
| 775 | .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 | |
| 776 | DELAYED_APP | CONFIG_PARTICIPANT, |
| 777 | .rate_offset = 5, |
| 778 | .recalc = &omap2_clksel_recalc, |
| 779 | }; |
| 780 | |
| 781 | /* |
| 782 | * Won't be too specific here. The core clock comes into this block |
| 783 | * it is divided then tee'ed. One branch goes directly to xyz enable |
| 784 | * controls. The other branch gets further divided by 2 then possibly |
| 785 | * routed into a synchronizer and out of clocks abc. |
| 786 | */ |
| 787 | static struct clk dsp_fck = { |
| 788 | .name = "dsp_fck", |
| 789 | .parent = &core_ck, |
| 790 | .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 | |
| 791 | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, |
| 792 | .rate_offset = 0, |
| 793 | .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, |
| 794 | .enable_bit = 0, |
| 795 | .recalc = &omap2_clksel_recalc, |
| 796 | }; |
| 797 | |
| 798 | static struct clk dsp_ick = { |
| 799 | .name = "dsp_ick", /* apparently ipi and isp */ |
| 800 | .parent = &dsp_fck, |
| 801 | .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 | |
| 802 | DELAYED_APP | CONFIG_PARTICIPANT, |
| 803 | .rate_offset = 5, |
| 804 | .enable_reg = (void __iomem *)&CM_ICLKEN_DSP, |
| 805 | .enable_bit = 1, /* for ipi */ |
| 806 | .recalc = &omap2_clksel_recalc, |
| 807 | }; |
| 808 | |
| 809 | static struct clk iva1_ifck = { |
| 810 | .name = "iva1_ifck", |
| 811 | .parent = &core_ck, |
| 812 | .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL | |
| 813 | CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, |
| 814 | .rate_offset= 8, |
| 815 | .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, |
| 816 | .enable_bit = 10, |
| 817 | .recalc = &omap2_clksel_recalc, |
| 818 | }; |
| 819 | |
| 820 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ |
| 821 | static struct clk iva1_mpu_int_ifck = { |
| 822 | .name = "iva1_mpu_int_ifck", |
| 823 | .parent = &iva1_ifck, |
| 824 | .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1, |
| 825 | .enable_reg = (void __iomem *)&CM_FCLKEN_DSP, |
| 826 | .enable_bit = 8, |
| 827 | .recalc = &omap2_clksel_recalc, |
| 828 | }; |
| 829 | |
| 830 | /* |
| 831 | * L3 clock domain |
| 832 | * L3 clocks are used for both interface and functional clocks to |
| 833 | * multiple entities. Some of these clocks are completely managed |
| 834 | * by hardware, and some others allow software control. Hardware |
| 835 | * managed ones general are based on directly CLK_REQ signals and |
| 836 | * various auto idle settings. The functional spec sets many of these |
| 837 | * as 'tie-high' for their enables. |
| 838 | * |
| 839 | * I-CLOCKS: |
| 840 | * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA |
| 841 | * CAM, HS-USB. |
| 842 | * F-CLOCK |
| 843 | * SSI. |
| 844 | * |
| 845 | * GPMC memories and SDRC have timing and clock sensitive registers which |
| 846 | * may very well need notification when the clock changes. Currently for low |
| 847 | * operating points, these are taken care of in sleep.S. |
| 848 | */ |
| 849 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
| 850 | .name = "core_l3_ck", |
| 851 | .parent = &core_ck, |
| 852 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 853 | RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 | |
| 854 | DELAYED_APP | CONFIG_PARTICIPANT | |
| 855 | RATE_PROPAGATES, |
| 856 | .rate_offset = 0, |
| 857 | .recalc = &omap2_clksel_recalc, |
| 858 | }; |
| 859 | |
| 860 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
| 861 | .name = "usb_l4_ick", |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 862 | .parent = &core_l3_ck, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 863 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 864 | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP | |
| 865 | CONFIG_PARTICIPANT, |
| 866 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 867 | .enable_bit = 0, |
| 868 | .rate_offset = 25, |
| 869 | .recalc = &omap2_clksel_recalc, |
| 870 | }; |
| 871 | |
| 872 | /* |
| 873 | * SSI is in L3 management domain, its direct parent is core not l3, |
| 874 | * many core power domain entities are grouped into the L3 clock |
| 875 | * domain. |
| 876 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK |
| 877 | * |
| 878 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. |
| 879 | */ |
| 880 | static struct clk ssi_ssr_sst_fck = { |
| 881 | .name = "ssi_fck", |
| 882 | .parent = &core_ck, |
| 883 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 884 | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP, |
| 885 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */ |
| 886 | .enable_bit = 1, |
| 887 | .rate_offset = 20, |
| 888 | .recalc = &omap2_clksel_recalc, |
| 889 | }; |
| 890 | |
| 891 | /* |
| 892 | * GFX clock domain |
| 893 | * Clocks: |
| 894 | * GFX_FCLK, GFX_ICLK |
| 895 | * GFX_CG1(2d), GFX_CG2(3d) |
| 896 | * |
| 897 | * GFX_FCLK runs from L3, and is divided by (1,2,3,4) |
| 898 | * The 2d and 3d clocks run at a hardware determined |
| 899 | * divided value of fclk. |
| 900 | * |
| 901 | */ |
| 902 | static struct clk gfx_3d_fck = { |
| 903 | .name = "gfx_3d_fck", |
| 904 | .parent = &core_l3_ck, |
| 905 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 906 | RATE_CKCTL | CM_GFX_SEL1, |
| 907 | .enable_reg = (void __iomem *)&CM_FCLKEN_GFX, |
| 908 | .enable_bit = 2, |
| 909 | .rate_offset= 0, |
| 910 | .recalc = &omap2_clksel_recalc, |
| 911 | }; |
| 912 | |
| 913 | static struct clk gfx_2d_fck = { |
| 914 | .name = "gfx_2d_fck", |
| 915 | .parent = &core_l3_ck, |
| 916 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 917 | RATE_CKCTL | CM_GFX_SEL1, |
| 918 | .enable_reg = (void __iomem *)&CM_FCLKEN_GFX, |
| 919 | .enable_bit = 1, |
| 920 | .rate_offset= 0, |
| 921 | .recalc = &omap2_clksel_recalc, |
| 922 | }; |
| 923 | |
| 924 | static struct clk gfx_ick = { |
| 925 | .name = "gfx_ick", /* From l3 */ |
| 926 | .parent = &core_l3_ck, |
| 927 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 928 | RATE_CKCTL, |
| 929 | .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */ |
| 930 | .enable_bit = 0, |
| 931 | .recalc = &omap2_followparent_recalc, |
| 932 | }; |
| 933 | |
| 934 | /* |
| 935 | * Modem clock domain (2430) |
| 936 | * CLOCKS: |
| 937 | * MDM_OSC_CLK |
| 938 | * MDM_ICLK |
| 939 | */ |
| 940 | static struct clk mdm_ick = { /* used both as a ick and fck */ |
| 941 | .name = "mdm_ick", |
| 942 | .parent = &core_ck, |
| 943 | .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 | |
| 944 | DELAYED_APP | CONFIG_PARTICIPANT, |
| 945 | .rate_offset = 0, |
| 946 | .enable_reg = (void __iomem *)&CM_ICLKEN_MDM, |
| 947 | .enable_bit = 0, |
| 948 | .recalc = &omap2_clksel_recalc, |
| 949 | }; |
| 950 | |
| 951 | static struct clk mdm_osc_ck = { |
| 952 | .name = "mdm_osc_ck", |
| 953 | .rate = 26000000, |
| 954 | .parent = &osc_ck, |
| 955 | .flags = CLOCK_IN_OMAP243X | RATE_FIXED, |
| 956 | .enable_reg = (void __iomem *)&CM_FCLKEN_MDM, |
| 957 | .enable_bit = 1, |
| 958 | .recalc = &omap2_followparent_recalc, |
| 959 | }; |
| 960 | |
| 961 | /* |
| 962 | * L4 clock management domain |
| 963 | * |
| 964 | * This domain contains lots of interface clocks from the L4 interface, some |
| 965 | * functional clocks. Fixed APLL functional source clocks are managed in |
| 966 | * this domain. |
| 967 | */ |
| 968 | static struct clk l4_ck = { /* used both as an ick and fck */ |
| 969 | .name = "l4_ck", |
| 970 | .parent = &core_l3_ck, |
| 971 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 972 | RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 | |
| 973 | DELAYED_APP | RATE_PROPAGATES, |
| 974 | .rate_offset = 5, |
| 975 | .recalc = &omap2_clksel_recalc, |
| 976 | }; |
| 977 | |
| 978 | static struct clk ssi_l4_ick = { |
| 979 | .name = "ssi_l4_ick", |
| 980 | .parent = &l4_ck, |
| 981 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL, |
| 982 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */ |
| 983 | .enable_bit = 1, |
| 984 | .recalc = &omap2_followparent_recalc, |
| 985 | }; |
| 986 | |
| 987 | /* |
| 988 | * DSS clock domain |
| 989 | * CLOCKs: |
| 990 | * DSS_L4_ICLK, DSS_L3_ICLK, |
| 991 | * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK |
| 992 | * |
| 993 | * DSS is both initiator and target. |
| 994 | */ |
| 995 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
| 996 | .name = "dss_ick", |
| 997 | .parent = &l4_ck, /* really both l3 and l4 */ |
| 998 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL, |
| 999 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1000 | .enable_bit = 0, |
| 1001 | .recalc = &omap2_followparent_recalc, |
| 1002 | }; |
| 1003 | |
| 1004 | static struct clk dss1_fck = { |
| 1005 | .name = "dss1_fck", |
| 1006 | .parent = &core_ck, /* Core or sys */ |
| 1007 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1008 | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP, |
| 1009 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1010 | .enable_bit = 0, |
| 1011 | .rate_offset = 8, |
| 1012 | .src_offset = 8, |
| 1013 | .recalc = &omap2_clksel_recalc, |
| 1014 | }; |
| 1015 | |
| 1016 | static struct clk dss2_fck = { /* Alt clk used in power management */ |
| 1017 | .name = "dss2_fck", |
| 1018 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
| 1019 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1020 | RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED, |
| 1021 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1022 | .enable_bit = 1, |
| 1023 | .src_offset = 13, |
| 1024 | .recalc = &omap2_followparent_recalc, |
| 1025 | }; |
| 1026 | |
| 1027 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ |
| 1028 | .name = "dss_54m_fck", /* 54m tv clk */ |
| 1029 | .parent = &func_54m_ck, |
| 1030 | .rate = 54000000, |
| 1031 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1032 | RATE_FIXED | RATE_PROPAGATES, |
| 1033 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1034 | .enable_bit = 2, |
| 1035 | .recalc = &omap2_propagate_rate, |
| 1036 | }; |
| 1037 | |
| 1038 | /* |
| 1039 | * CORE power domain ICLK & FCLK defines. |
| 1040 | * Many of the these can have more than one possible parent. Entries |
| 1041 | * here will likely have an L4 interface parent, and may have multiple |
| 1042 | * functional clock parents. |
| 1043 | */ |
| 1044 | static struct clk gpt1_ick = { |
| 1045 | .name = "gpt1_ick", |
| 1046 | .parent = &l4_ck, |
| 1047 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 1048 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1049 | .enable_bit = 0, |
| 1050 | .recalc = &omap2_followparent_recalc, |
| 1051 | }; |
| 1052 | |
| 1053 | static struct clk gpt1_fck = { |
| 1054 | .name = "gpt1_fck", |
| 1055 | .parent = &func_32k_ck, |
| 1056 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1057 | CM_WKUP_SEL1, |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 1058 | .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1059 | .enable_bit = 0, |
| 1060 | .src_offset = 0, |
| 1061 | .recalc = &omap2_followparent_recalc, |
| 1062 | }; |
| 1063 | |
| 1064 | static struct clk gpt2_ick = { |
| 1065 | .name = "gpt2_ick", |
| 1066 | .parent = &l4_ck, |
| 1067 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 1068 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1069 | .enable_bit = 0, |
| 1070 | .recalc = &omap2_followparent_recalc, |
| 1071 | }; |
| 1072 | |
| 1073 | static struct clk gpt2_fck = { |
| 1074 | .name = "gpt2_fck", |
| 1075 | .parent = &func_32k_ck, |
| 1076 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1077 | CM_CORE_SEL2, |
| 1078 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1079 | .enable_bit = 4, |
| 1080 | .src_offset = 2, |
| 1081 | .recalc = &omap2_followparent_recalc, |
| 1082 | }; |
| 1083 | |
| 1084 | static struct clk gpt3_ick = { |
| 1085 | .name = "gpt3_ick", |
| 1086 | .parent = &l4_ck, |
| 1087 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1088 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */ |
| 1089 | .enable_bit = 5, |
| 1090 | .recalc = &omap2_followparent_recalc, |
| 1091 | }; |
| 1092 | |
| 1093 | static struct clk gpt3_fck = { |
| 1094 | .name = "gpt3_fck", |
| 1095 | .parent = &func_32k_ck, |
| 1096 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1097 | CM_CORE_SEL2, |
| 1098 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1099 | .enable_bit = 5, |
| 1100 | .src_offset = 4, |
| 1101 | .recalc = &omap2_followparent_recalc, |
| 1102 | }; |
| 1103 | |
| 1104 | static struct clk gpt4_ick = { |
| 1105 | .name = "gpt4_ick", |
| 1106 | .parent = &l4_ck, |
| 1107 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1108 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */ |
| 1109 | .enable_bit = 6, |
| 1110 | .recalc = &omap2_followparent_recalc, |
| 1111 | }; |
| 1112 | |
| 1113 | static struct clk gpt4_fck = { |
| 1114 | .name = "gpt4_fck", |
| 1115 | .parent = &func_32k_ck, |
| 1116 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1117 | CM_CORE_SEL2, |
| 1118 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1119 | .enable_bit = 6, |
| 1120 | .src_offset = 6, |
| 1121 | .recalc = &omap2_followparent_recalc, |
| 1122 | }; |
| 1123 | |
| 1124 | static struct clk gpt5_ick = { |
| 1125 | .name = "gpt5_ick", |
| 1126 | .parent = &l4_ck, |
| 1127 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1128 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */ |
| 1129 | .enable_bit = 7, |
| 1130 | .recalc = &omap2_followparent_recalc, |
| 1131 | }; |
| 1132 | |
| 1133 | static struct clk gpt5_fck = { |
| 1134 | .name = "gpt5_fck", |
| 1135 | .parent = &func_32k_ck, |
| 1136 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1137 | CM_CORE_SEL2, |
| 1138 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1139 | .enable_bit = 7, |
| 1140 | .src_offset = 8, |
| 1141 | .recalc = &omap2_followparent_recalc, |
| 1142 | }; |
| 1143 | |
| 1144 | static struct clk gpt6_ick = { |
| 1145 | .name = "gpt6_ick", |
| 1146 | .parent = &l4_ck, |
| 1147 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1148 | .enable_bit = 8, |
| 1149 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */ |
| 1150 | .recalc = &omap2_followparent_recalc, |
| 1151 | }; |
| 1152 | |
| 1153 | static struct clk gpt6_fck = { |
| 1154 | .name = "gpt6_fck", |
| 1155 | .parent = &func_32k_ck, |
| 1156 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1157 | CM_CORE_SEL2, |
| 1158 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1159 | .enable_bit = 8, |
| 1160 | .src_offset = 10, |
| 1161 | .recalc = &omap2_followparent_recalc, |
| 1162 | }; |
| 1163 | |
| 1164 | static struct clk gpt7_ick = { |
| 1165 | .name = "gpt7_ick", |
| 1166 | .parent = &l4_ck, |
| 1167 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1168 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */ |
| 1169 | .enable_bit = 9, |
| 1170 | .recalc = &omap2_followparent_recalc, |
| 1171 | }; |
| 1172 | |
| 1173 | static struct clk gpt7_fck = { |
| 1174 | .name = "gpt7_fck", |
| 1175 | .parent = &func_32k_ck, |
| 1176 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1177 | CM_CORE_SEL2, |
| 1178 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1179 | .enable_bit = 9, |
| 1180 | .src_offset = 12, |
| 1181 | .recalc = &omap2_followparent_recalc, |
| 1182 | }; |
| 1183 | |
| 1184 | static struct clk gpt8_ick = { |
| 1185 | .name = "gpt8_ick", |
| 1186 | .parent = &l4_ck, |
| 1187 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1188 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */ |
| 1189 | .enable_bit = 10, |
| 1190 | .recalc = &omap2_followparent_recalc, |
| 1191 | }; |
| 1192 | |
| 1193 | static struct clk gpt8_fck = { |
| 1194 | .name = "gpt8_fck", |
| 1195 | .parent = &func_32k_ck, |
| 1196 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1197 | CM_CORE_SEL2, |
| 1198 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1199 | .enable_bit = 10, |
| 1200 | .src_offset = 14, |
| 1201 | .recalc = &omap2_followparent_recalc, |
| 1202 | }; |
| 1203 | |
| 1204 | static struct clk gpt9_ick = { |
| 1205 | .name = "gpt9_ick", |
| 1206 | .parent = &l4_ck, |
| 1207 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1208 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1209 | .enable_bit = 11, |
| 1210 | .recalc = &omap2_followparent_recalc, |
| 1211 | }; |
| 1212 | |
| 1213 | static struct clk gpt9_fck = { |
| 1214 | .name = "gpt9_fck", |
| 1215 | .parent = &func_32k_ck, |
| 1216 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1217 | CM_CORE_SEL2, |
| 1218 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1219 | .enable_bit = 11, |
| 1220 | .src_offset = 16, |
| 1221 | .recalc = &omap2_followparent_recalc, |
| 1222 | }; |
| 1223 | |
| 1224 | static struct clk gpt10_ick = { |
| 1225 | .name = "gpt10_ick", |
| 1226 | .parent = &l4_ck, |
| 1227 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1228 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1229 | .enable_bit = 12, |
| 1230 | .recalc = &omap2_followparent_recalc, |
| 1231 | }; |
| 1232 | |
| 1233 | static struct clk gpt10_fck = { |
| 1234 | .name = "gpt10_fck", |
| 1235 | .parent = &func_32k_ck, |
| 1236 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1237 | CM_CORE_SEL2, |
| 1238 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1239 | .enable_bit = 12, |
| 1240 | .src_offset = 18, |
| 1241 | .recalc = &omap2_followparent_recalc, |
| 1242 | }; |
| 1243 | |
| 1244 | static struct clk gpt11_ick = { |
| 1245 | .name = "gpt11_ick", |
| 1246 | .parent = &l4_ck, |
| 1247 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1248 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1249 | .enable_bit = 13, |
| 1250 | .recalc = &omap2_followparent_recalc, |
| 1251 | }; |
| 1252 | |
| 1253 | static struct clk gpt11_fck = { |
| 1254 | .name = "gpt11_fck", |
| 1255 | .parent = &func_32k_ck, |
| 1256 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1257 | CM_CORE_SEL2, |
| 1258 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1259 | .enable_bit = 13, |
| 1260 | .src_offset = 20, |
| 1261 | .recalc = &omap2_followparent_recalc, |
| 1262 | }; |
| 1263 | |
| 1264 | static struct clk gpt12_ick = { |
| 1265 | .name = "gpt12_ick", |
| 1266 | .parent = &l4_ck, |
| 1267 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1268 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */ |
| 1269 | .enable_bit = 14, |
| 1270 | .recalc = &omap2_followparent_recalc, |
| 1271 | }; |
| 1272 | |
| 1273 | static struct clk gpt12_fck = { |
| 1274 | .name = "gpt12_fck", |
| 1275 | .parent = &func_32k_ck, |
| 1276 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1277 | CM_CORE_SEL2, |
| 1278 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1279 | .enable_bit = 14, |
| 1280 | .src_offset = 22, |
| 1281 | .recalc = &omap2_followparent_recalc, |
| 1282 | }; |
| 1283 | |
| 1284 | static struct clk mcbsp1_ick = { |
| 1285 | .name = "mcbsp1_ick", |
| 1286 | .parent = &l4_ck, |
| 1287 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1288 | .enable_bit = 15, |
| 1289 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */ |
| 1290 | .recalc = &omap2_followparent_recalc, |
| 1291 | }; |
| 1292 | |
| 1293 | static struct clk mcbsp1_fck = { |
| 1294 | .name = "mcbsp1_fck", |
| 1295 | .parent = &func_96m_ck, |
| 1296 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1297 | .enable_bit = 15, |
| 1298 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1299 | .recalc = &omap2_followparent_recalc, |
| 1300 | }; |
| 1301 | |
| 1302 | static struct clk mcbsp2_ick = { |
| 1303 | .name = "mcbsp2_ick", |
| 1304 | .parent = &l4_ck, |
| 1305 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1306 | .enable_bit = 16, |
| 1307 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1308 | .recalc = &omap2_followparent_recalc, |
| 1309 | }; |
| 1310 | |
| 1311 | static struct clk mcbsp2_fck = { |
| 1312 | .name = "mcbsp2_fck", |
| 1313 | .parent = &func_96m_ck, |
| 1314 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1315 | .enable_bit = 16, |
| 1316 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1317 | .recalc = &omap2_followparent_recalc, |
| 1318 | }; |
| 1319 | |
| 1320 | static struct clk mcbsp3_ick = { |
| 1321 | .name = "mcbsp3_ick", |
| 1322 | .parent = &l4_ck, |
| 1323 | .flags = CLOCK_IN_OMAP243X, |
| 1324 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1325 | .enable_bit = 3, |
| 1326 | .recalc = &omap2_followparent_recalc, |
| 1327 | }; |
| 1328 | |
| 1329 | static struct clk mcbsp3_fck = { |
| 1330 | .name = "mcbsp3_fck", |
| 1331 | .parent = &func_96m_ck, |
| 1332 | .flags = CLOCK_IN_OMAP243X, |
| 1333 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1334 | .enable_bit = 3, |
| 1335 | .recalc = &omap2_followparent_recalc, |
| 1336 | }; |
| 1337 | |
| 1338 | static struct clk mcbsp4_ick = { |
| 1339 | .name = "mcbsp4_ick", |
| 1340 | .parent = &l4_ck, |
| 1341 | .flags = CLOCK_IN_OMAP243X, |
| 1342 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1343 | .enable_bit = 4, |
| 1344 | .recalc = &omap2_followparent_recalc, |
| 1345 | }; |
| 1346 | |
| 1347 | static struct clk mcbsp4_fck = { |
| 1348 | .name = "mcbsp4_fck", |
| 1349 | .parent = &func_96m_ck, |
| 1350 | .flags = CLOCK_IN_OMAP243X, |
| 1351 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1352 | .enable_bit = 4, |
| 1353 | .recalc = &omap2_followparent_recalc, |
| 1354 | }; |
| 1355 | |
| 1356 | static struct clk mcbsp5_ick = { |
| 1357 | .name = "mcbsp5_ick", |
| 1358 | .parent = &l4_ck, |
| 1359 | .flags = CLOCK_IN_OMAP243X, |
| 1360 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1361 | .enable_bit = 5, |
| 1362 | .recalc = &omap2_followparent_recalc, |
| 1363 | }; |
| 1364 | |
| 1365 | static struct clk mcbsp5_fck = { |
| 1366 | .name = "mcbsp5_fck", |
| 1367 | .parent = &func_96m_ck, |
| 1368 | .flags = CLOCK_IN_OMAP243X, |
| 1369 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1370 | .enable_bit = 5, |
| 1371 | .recalc = &omap2_followparent_recalc, |
| 1372 | }; |
| 1373 | |
| 1374 | static struct clk mcspi1_ick = { |
| 1375 | .name = "mcspi1_ick", |
| 1376 | .parent = &l4_ck, |
| 1377 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1378 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1379 | .enable_bit = 17, |
| 1380 | .recalc = &omap2_followparent_recalc, |
| 1381 | }; |
| 1382 | |
| 1383 | static struct clk mcspi1_fck = { |
| 1384 | .name = "mcspi1_fck", |
| 1385 | .parent = &func_48m_ck, |
| 1386 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1387 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1388 | .enable_bit = 17, |
| 1389 | .recalc = &omap2_followparent_recalc, |
| 1390 | }; |
| 1391 | |
| 1392 | static struct clk mcspi2_ick = { |
| 1393 | .name = "mcspi2_ick", |
| 1394 | .parent = &l4_ck, |
| 1395 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1396 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1397 | .enable_bit = 18, |
| 1398 | .recalc = &omap2_followparent_recalc, |
| 1399 | }; |
| 1400 | |
| 1401 | static struct clk mcspi2_fck = { |
| 1402 | .name = "mcspi2_fck", |
| 1403 | .parent = &func_48m_ck, |
| 1404 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1405 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1406 | .enable_bit = 18, |
| 1407 | .recalc = &omap2_followparent_recalc, |
| 1408 | }; |
| 1409 | |
| 1410 | static struct clk mcspi3_ick = { |
| 1411 | .name = "mcspi3_ick", |
| 1412 | .parent = &l4_ck, |
| 1413 | .flags = CLOCK_IN_OMAP243X, |
| 1414 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1415 | .enable_bit = 9, |
| 1416 | .recalc = &omap2_followparent_recalc, |
| 1417 | }; |
| 1418 | |
| 1419 | static struct clk mcspi3_fck = { |
| 1420 | .name = "mcspi3_fck", |
| 1421 | .parent = &func_48m_ck, |
| 1422 | .flags = CLOCK_IN_OMAP243X, |
| 1423 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1424 | .enable_bit = 9, |
| 1425 | .recalc = &omap2_followparent_recalc, |
| 1426 | }; |
| 1427 | |
| 1428 | static struct clk uart1_ick = { |
| 1429 | .name = "uart1_ick", |
| 1430 | .parent = &l4_ck, |
| 1431 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1432 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1433 | .enable_bit = 21, |
| 1434 | .recalc = &omap2_followparent_recalc, |
| 1435 | }; |
| 1436 | |
| 1437 | static struct clk uart1_fck = { |
| 1438 | .name = "uart1_fck", |
| 1439 | .parent = &func_48m_ck, |
| 1440 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1441 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1442 | .enable_bit = 21, |
| 1443 | .recalc = &omap2_followparent_recalc, |
| 1444 | }; |
| 1445 | |
| 1446 | static struct clk uart2_ick = { |
| 1447 | .name = "uart2_ick", |
| 1448 | .parent = &l4_ck, |
| 1449 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1450 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1451 | .enable_bit = 22, |
| 1452 | .recalc = &omap2_followparent_recalc, |
| 1453 | }; |
| 1454 | |
| 1455 | static struct clk uart2_fck = { |
| 1456 | .name = "uart2_fck", |
| 1457 | .parent = &func_48m_ck, |
| 1458 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1459 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1460 | .enable_bit = 22, |
| 1461 | .recalc = &omap2_followparent_recalc, |
| 1462 | }; |
| 1463 | |
| 1464 | static struct clk uart3_ick = { |
| 1465 | .name = "uart3_ick", |
| 1466 | .parent = &l4_ck, |
| 1467 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1468 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1469 | .enable_bit = 2, |
| 1470 | .recalc = &omap2_followparent_recalc, |
| 1471 | }; |
| 1472 | |
| 1473 | static struct clk uart3_fck = { |
| 1474 | .name = "uart3_fck", |
| 1475 | .parent = &func_48m_ck, |
| 1476 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1477 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1478 | .enable_bit = 2, |
| 1479 | .recalc = &omap2_followparent_recalc, |
| 1480 | }; |
| 1481 | |
| 1482 | static struct clk gpios_ick = { |
| 1483 | .name = "gpios_ick", |
| 1484 | .parent = &l4_ck, |
| 1485 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1486 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, |
| 1487 | .enable_bit = 2, |
| 1488 | .recalc = &omap2_followparent_recalc, |
| 1489 | }; |
| 1490 | |
| 1491 | static struct clk gpios_fck = { |
| 1492 | .name = "gpios_fck", |
| 1493 | .parent = &func_32k_ck, |
| 1494 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1495 | .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, |
| 1496 | .enable_bit = 2, |
| 1497 | .recalc = &omap2_followparent_recalc, |
| 1498 | }; |
| 1499 | |
| 1500 | static struct clk mpu_wdt_ick = { |
| 1501 | .name = "mpu_wdt_ick", |
| 1502 | .parent = &l4_ck, |
| 1503 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1504 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, |
| 1505 | .enable_bit = 3, |
| 1506 | .recalc = &omap2_followparent_recalc, |
| 1507 | }; |
| 1508 | |
| 1509 | static struct clk mpu_wdt_fck = { |
| 1510 | .name = "mpu_wdt_fck", |
| 1511 | .parent = &func_32k_ck, |
| 1512 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1513 | .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, |
| 1514 | .enable_bit = 3, |
| 1515 | .recalc = &omap2_followparent_recalc, |
| 1516 | }; |
| 1517 | |
| 1518 | static struct clk sync_32k_ick = { |
| 1519 | .name = "sync_32k_ick", |
| 1520 | .parent = &l4_ck, |
| 1521 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1522 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, |
| 1523 | .enable_bit = 1, |
| 1524 | .recalc = &omap2_followparent_recalc, |
| 1525 | }; |
| 1526 | static struct clk wdt1_ick = { |
| 1527 | .name = "wdt1_ick", |
| 1528 | .parent = &l4_ck, |
| 1529 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1530 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, |
| 1531 | .enable_bit = 4, |
| 1532 | .recalc = &omap2_followparent_recalc, |
| 1533 | }; |
| 1534 | static struct clk omapctrl_ick = { |
| 1535 | .name = "omapctrl_ick", |
| 1536 | .parent = &l4_ck, |
| 1537 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1538 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, |
| 1539 | .enable_bit = 5, |
| 1540 | .recalc = &omap2_followparent_recalc, |
| 1541 | }; |
| 1542 | static struct clk icr_ick = { |
| 1543 | .name = "icr_ick", |
| 1544 | .parent = &l4_ck, |
| 1545 | .flags = CLOCK_IN_OMAP243X, |
| 1546 | .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, |
| 1547 | .enable_bit = 6, |
| 1548 | .recalc = &omap2_followparent_recalc, |
| 1549 | }; |
| 1550 | |
| 1551 | static struct clk cam_ick = { |
| 1552 | .name = "cam_ick", |
| 1553 | .parent = &l4_ck, |
| 1554 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1555 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1556 | .enable_bit = 31, |
| 1557 | .recalc = &omap2_followparent_recalc, |
| 1558 | }; |
| 1559 | |
| 1560 | static struct clk cam_fck = { |
| 1561 | .name = "cam_fck", |
| 1562 | .parent = &func_96m_ck, |
| 1563 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1564 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1565 | .enable_bit = 31, |
| 1566 | .recalc = &omap2_followparent_recalc, |
| 1567 | }; |
| 1568 | |
| 1569 | static struct clk mailboxes_ick = { |
| 1570 | .name = "mailboxes_ick", |
| 1571 | .parent = &l4_ck, |
| 1572 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1573 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1574 | .enable_bit = 30, |
| 1575 | .recalc = &omap2_followparent_recalc, |
| 1576 | }; |
| 1577 | |
| 1578 | static struct clk wdt4_ick = { |
| 1579 | .name = "wdt4_ick", |
| 1580 | .parent = &l4_ck, |
| 1581 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1582 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1583 | .enable_bit = 29, |
| 1584 | .recalc = &omap2_followparent_recalc, |
| 1585 | }; |
| 1586 | |
| 1587 | static struct clk wdt4_fck = { |
| 1588 | .name = "wdt4_fck", |
| 1589 | .parent = &func_32k_ck, |
| 1590 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1591 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1592 | .enable_bit = 29, |
| 1593 | .recalc = &omap2_followparent_recalc, |
| 1594 | }; |
| 1595 | |
| 1596 | static struct clk wdt3_ick = { |
| 1597 | .name = "wdt3_ick", |
| 1598 | .parent = &l4_ck, |
| 1599 | .flags = CLOCK_IN_OMAP242X, |
| 1600 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1601 | .enable_bit = 28, |
| 1602 | .recalc = &omap2_followparent_recalc, |
| 1603 | }; |
| 1604 | |
| 1605 | static struct clk wdt3_fck = { |
| 1606 | .name = "wdt3_fck", |
| 1607 | .parent = &func_32k_ck, |
| 1608 | .flags = CLOCK_IN_OMAP242X, |
| 1609 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1610 | .enable_bit = 28, |
| 1611 | .recalc = &omap2_followparent_recalc, |
| 1612 | }; |
| 1613 | |
| 1614 | static struct clk mspro_ick = { |
| 1615 | .name = "mspro_ick", |
| 1616 | .parent = &l4_ck, |
| 1617 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1618 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1619 | .enable_bit = 27, |
| 1620 | .recalc = &omap2_followparent_recalc, |
| 1621 | }; |
| 1622 | |
| 1623 | static struct clk mspro_fck = { |
| 1624 | .name = "mspro_fck", |
| 1625 | .parent = &func_96m_ck, |
| 1626 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1627 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1628 | .enable_bit = 27, |
| 1629 | .recalc = &omap2_followparent_recalc, |
| 1630 | }; |
| 1631 | |
| 1632 | static struct clk mmc_ick = { |
| 1633 | .name = "mmc_ick", |
| 1634 | .parent = &l4_ck, |
| 1635 | .flags = CLOCK_IN_OMAP242X, |
| 1636 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1637 | .enable_bit = 26, |
| 1638 | .recalc = &omap2_followparent_recalc, |
| 1639 | }; |
| 1640 | |
| 1641 | static struct clk mmc_fck = { |
| 1642 | .name = "mmc_fck", |
| 1643 | .parent = &func_96m_ck, |
| 1644 | .flags = CLOCK_IN_OMAP242X, |
| 1645 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1646 | .enable_bit = 26, |
| 1647 | .recalc = &omap2_followparent_recalc, |
| 1648 | }; |
| 1649 | |
| 1650 | static struct clk fac_ick = { |
| 1651 | .name = "fac_ick", |
| 1652 | .parent = &l4_ck, |
| 1653 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1654 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1655 | .enable_bit = 25, |
| 1656 | .recalc = &omap2_followparent_recalc, |
| 1657 | }; |
| 1658 | |
| 1659 | static struct clk fac_fck = { |
| 1660 | .name = "fac_fck", |
| 1661 | .parent = &func_12m_ck, |
| 1662 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1663 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1664 | .enable_bit = 25, |
| 1665 | .recalc = &omap2_followparent_recalc, |
| 1666 | }; |
| 1667 | |
| 1668 | static struct clk eac_ick = { |
| 1669 | .name = "eac_ick", |
| 1670 | .parent = &l4_ck, |
| 1671 | .flags = CLOCK_IN_OMAP242X, |
| 1672 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1673 | .enable_bit = 24, |
| 1674 | .recalc = &omap2_followparent_recalc, |
| 1675 | }; |
| 1676 | |
| 1677 | static struct clk eac_fck = { |
| 1678 | .name = "eac_fck", |
| 1679 | .parent = &func_96m_ck, |
| 1680 | .flags = CLOCK_IN_OMAP242X, |
| 1681 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1682 | .enable_bit = 24, |
| 1683 | .recalc = &omap2_followparent_recalc, |
| 1684 | }; |
| 1685 | |
| 1686 | static struct clk hdq_ick = { |
| 1687 | .name = "hdq_ick", |
| 1688 | .parent = &l4_ck, |
| 1689 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1690 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1691 | .enable_bit = 23, |
| 1692 | .recalc = &omap2_followparent_recalc, |
| 1693 | }; |
| 1694 | |
| 1695 | static struct clk hdq_fck = { |
| 1696 | .name = "hdq_fck", |
| 1697 | .parent = &func_12m_ck, |
| 1698 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1699 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1700 | .enable_bit = 23, |
| 1701 | .recalc = &omap2_followparent_recalc, |
| 1702 | }; |
| 1703 | |
| 1704 | static struct clk i2c2_ick = { |
| 1705 | .name = "i2c2_ick", |
| 1706 | .parent = &l4_ck, |
| 1707 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1708 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1709 | .enable_bit = 20, |
| 1710 | .recalc = &omap2_followparent_recalc, |
| 1711 | }; |
| 1712 | |
| 1713 | static struct clk i2c2_fck = { |
| 1714 | .name = "i2c2_fck", |
| 1715 | .parent = &func_12m_ck, |
| 1716 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1717 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1718 | .enable_bit = 20, |
| 1719 | .recalc = &omap2_followparent_recalc, |
| 1720 | }; |
| 1721 | |
| 1722 | static struct clk i2chs2_fck = { |
| 1723 | .name = "i2chs2_fck", |
| 1724 | .parent = &func_96m_ck, |
| 1725 | .flags = CLOCK_IN_OMAP243X, |
| 1726 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1727 | .enable_bit = 20, |
| 1728 | .recalc = &omap2_followparent_recalc, |
| 1729 | }; |
| 1730 | |
| 1731 | static struct clk i2c1_ick = { |
| 1732 | .name = "i2c1_ick", |
| 1733 | .parent = &l4_ck, |
| 1734 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1735 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1736 | .enable_bit = 19, |
| 1737 | .recalc = &omap2_followparent_recalc, |
| 1738 | }; |
| 1739 | |
| 1740 | static struct clk i2c1_fck = { |
| 1741 | .name = "i2c1_fck", |
| 1742 | .parent = &func_12m_ck, |
| 1743 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
| 1744 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1745 | .enable_bit = 19, |
| 1746 | .recalc = &omap2_followparent_recalc, |
| 1747 | }; |
| 1748 | |
| 1749 | static struct clk i2chs1_fck = { |
| 1750 | .name = "i2chs1_fck", |
| 1751 | .parent = &func_96m_ck, |
| 1752 | .flags = CLOCK_IN_OMAP243X, |
| 1753 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1754 | .enable_bit = 19, |
| 1755 | .recalc = &omap2_followparent_recalc, |
| 1756 | }; |
| 1757 | |
| 1758 | static struct clk vlynq_ick = { |
| 1759 | .name = "vlynq_ick", |
| 1760 | .parent = &core_l3_ck, |
| 1761 | .flags = CLOCK_IN_OMAP242X, |
| 1762 | .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, |
| 1763 | .enable_bit = 3, |
| 1764 | .recalc = &omap2_followparent_recalc, |
| 1765 | }; |
| 1766 | |
| 1767 | static struct clk vlynq_fck = { |
| 1768 | .name = "vlynq_fck", |
| 1769 | .parent = &func_96m_ck, |
| 1770 | .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP, |
| 1771 | .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, |
| 1772 | .enable_bit = 3, |
| 1773 | .src_offset = 15, |
| 1774 | .recalc = &omap2_followparent_recalc, |
| 1775 | }; |
| 1776 | |
| 1777 | static struct clk sdrc_ick = { |
| 1778 | .name = "sdrc_ick", |
| 1779 | .parent = &l4_ck, |
| 1780 | .flags = CLOCK_IN_OMAP243X, |
| 1781 | .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE, |
| 1782 | .enable_bit = 2, |
| 1783 | .recalc = &omap2_followparent_recalc, |
| 1784 | }; |
| 1785 | |
| 1786 | static struct clk des_ick = { |
| 1787 | .name = "des_ick", |
| 1788 | .parent = &l4_ck, |
| 1789 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
| 1790 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, |
| 1791 | .enable_bit = 0, |
| 1792 | .recalc = &omap2_followparent_recalc, |
| 1793 | }; |
| 1794 | |
| 1795 | static struct clk sha_ick = { |
| 1796 | .name = "sha_ick", |
| 1797 | .parent = &l4_ck, |
| 1798 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
| 1799 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, |
| 1800 | .enable_bit = 1, |
| 1801 | .recalc = &omap2_followparent_recalc, |
| 1802 | }; |
| 1803 | |
| 1804 | static struct clk rng_ick = { |
| 1805 | .name = "rng_ick", |
| 1806 | .parent = &l4_ck, |
| 1807 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
| 1808 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, |
| 1809 | .enable_bit = 2, |
| 1810 | .recalc = &omap2_followparent_recalc, |
| 1811 | }; |
| 1812 | |
| 1813 | static struct clk aes_ick = { |
| 1814 | .name = "aes_ick", |
| 1815 | .parent = &l4_ck, |
| 1816 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
| 1817 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, |
| 1818 | .enable_bit = 3, |
| 1819 | .recalc = &omap2_followparent_recalc, |
| 1820 | }; |
| 1821 | |
| 1822 | static struct clk pka_ick = { |
| 1823 | .name = "pka_ick", |
| 1824 | .parent = &l4_ck, |
| 1825 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
| 1826 | .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE, |
| 1827 | .enable_bit = 4, |
| 1828 | .recalc = &omap2_followparent_recalc, |
| 1829 | }; |
| 1830 | |
| 1831 | static struct clk usb_fck = { |
| 1832 | .name = "usb_fck", |
| 1833 | .parent = &func_48m_ck, |
| 1834 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
| 1835 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1836 | .enable_bit = 0, |
| 1837 | .recalc = &omap2_followparent_recalc, |
| 1838 | }; |
| 1839 | |
| 1840 | static struct clk usbhs_ick = { |
| 1841 | .name = "usbhs_ick", |
Tony Lindgren | fde0fd4 | 2006-01-17 15:31:18 -0800 | [diff] [blame] | 1842 | .parent = &core_l3_ck, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1843 | .flags = CLOCK_IN_OMAP243X, |
| 1844 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1845 | .enable_bit = 6, |
| 1846 | .recalc = &omap2_followparent_recalc, |
| 1847 | }; |
| 1848 | |
| 1849 | static struct clk mmchs1_ick = { |
| 1850 | .name = "mmchs1_ick", |
| 1851 | .parent = &l4_ck, |
| 1852 | .flags = CLOCK_IN_OMAP243X, |
| 1853 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1854 | .enable_bit = 7, |
| 1855 | .recalc = &omap2_followparent_recalc, |
| 1856 | }; |
| 1857 | |
| 1858 | static struct clk mmchs1_fck = { |
| 1859 | .name = "mmchs1_fck", |
| 1860 | .parent = &func_96m_ck, |
| 1861 | .flags = CLOCK_IN_OMAP243X, |
| 1862 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1863 | .enable_bit = 7, |
| 1864 | .recalc = &omap2_followparent_recalc, |
| 1865 | }; |
| 1866 | |
| 1867 | static struct clk mmchs2_ick = { |
| 1868 | .name = "mmchs2_ick", |
| 1869 | .parent = &l4_ck, |
| 1870 | .flags = CLOCK_IN_OMAP243X, |
| 1871 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1872 | .enable_bit = 8, |
| 1873 | .recalc = &omap2_followparent_recalc, |
| 1874 | }; |
| 1875 | |
| 1876 | static struct clk mmchs2_fck = { |
| 1877 | .name = "mmchs2_fck", |
| 1878 | .parent = &func_96m_ck, |
| 1879 | .flags = CLOCK_IN_OMAP243X, |
| 1880 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1881 | .enable_bit = 8, |
| 1882 | .recalc = &omap2_followparent_recalc, |
| 1883 | }; |
| 1884 | |
| 1885 | static struct clk gpio5_ick = { |
| 1886 | .name = "gpio5_ick", |
| 1887 | .parent = &l4_ck, |
| 1888 | .flags = CLOCK_IN_OMAP243X, |
| 1889 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1890 | .enable_bit = 10, |
| 1891 | .recalc = &omap2_followparent_recalc, |
| 1892 | }; |
| 1893 | |
| 1894 | static struct clk gpio5_fck = { |
| 1895 | .name = "gpio5_fck", |
| 1896 | .parent = &func_32k_ck, |
| 1897 | .flags = CLOCK_IN_OMAP243X, |
| 1898 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1899 | .enable_bit = 10, |
| 1900 | .recalc = &omap2_followparent_recalc, |
| 1901 | }; |
| 1902 | |
| 1903 | static struct clk mdm_intc_ick = { |
| 1904 | .name = "mdm_intc_ick", |
| 1905 | .parent = &l4_ck, |
| 1906 | .flags = CLOCK_IN_OMAP243X, |
| 1907 | .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, |
| 1908 | .enable_bit = 11, |
| 1909 | .recalc = &omap2_followparent_recalc, |
| 1910 | }; |
| 1911 | |
| 1912 | static struct clk mmchsdb1_fck = { |
| 1913 | .name = "mmchsdb1_fck", |
| 1914 | .parent = &func_32k_ck, |
| 1915 | .flags = CLOCK_IN_OMAP243X, |
| 1916 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1917 | .enable_bit = 16, |
| 1918 | .recalc = &omap2_followparent_recalc, |
| 1919 | }; |
| 1920 | |
| 1921 | static struct clk mmchsdb2_fck = { |
| 1922 | .name = "mmchsdb2_fck", |
| 1923 | .parent = &func_32k_ck, |
| 1924 | .flags = CLOCK_IN_OMAP243X, |
| 1925 | .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, |
| 1926 | .enable_bit = 17, |
| 1927 | .recalc = &omap2_followparent_recalc, |
| 1928 | }; |
| 1929 | |
| 1930 | /* |
| 1931 | * This clock is a composite clock which does entire set changes then |
| 1932 | * forces a rebalance. It keys on the MPU speed, but it really could |
| 1933 | * be any key speed part of a set in the rate table. |
| 1934 | * |
| 1935 | * to really change a set, you need memory table sets which get changed |
| 1936 | * in sram, pre-notifiers & post notifiers, changing the top set, without |
| 1937 | * having low level display recalc's won't work... this is why dpm notifiers |
| 1938 | * work, isr's off, walk a list of clocks already _off_ and not messing with |
| 1939 | * the bus. |
| 1940 | * |
| 1941 | * This clock should have no parent. It embodies the entire upper level |
| 1942 | * active set. A parent will mess up some of the init also. |
| 1943 | */ |
| 1944 | static struct clk virt_prcm_set = { |
| 1945 | .name = "virt_prcm_set", |
| 1946 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
| 1947 | VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, |
| 1948 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
| 1949 | .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */ |
| 1950 | .set_rate = &omap2_select_table_rate, |
| 1951 | .round_rate = &omap2_round_to_table_rate, |
| 1952 | }; |
| 1953 | |
| 1954 | static struct clk *onchip_clks[] = { |
| 1955 | /* external root sources */ |
| 1956 | &func_32k_ck, |
| 1957 | &osc_ck, |
| 1958 | &sys_ck, |
| 1959 | &alt_ck, |
| 1960 | /* internal analog sources */ |
| 1961 | &dpll_ck, |
| 1962 | &apll96_ck, |
| 1963 | &apll54_ck, |
| 1964 | /* internal prcm root sources */ |
| 1965 | &func_54m_ck, |
| 1966 | &core_ck, |
| 1967 | &sleep_ck, |
| 1968 | &func_96m_ck, |
| 1969 | &func_48m_ck, |
| 1970 | &func_12m_ck, |
| 1971 | &wdt1_osc_ck, |
| 1972 | &sys_clkout, |
| 1973 | &sys_clkout2, |
| 1974 | /* mpu domain clocks */ |
| 1975 | &mpu_ck, |
| 1976 | /* dsp domain clocks */ |
| 1977 | &iva2_1_fck, /* 2430 */ |
| 1978 | &iva2_1_ick, |
| 1979 | &dsp_ick, /* 2420 */ |
| 1980 | &dsp_fck, |
| 1981 | &iva1_ifck, |
| 1982 | &iva1_mpu_int_ifck, |
| 1983 | /* GFX domain clocks */ |
| 1984 | &gfx_3d_fck, |
| 1985 | &gfx_2d_fck, |
| 1986 | &gfx_ick, |
| 1987 | /* Modem domain clocks */ |
| 1988 | &mdm_ick, |
| 1989 | &mdm_osc_ck, |
| 1990 | /* DSS domain clocks */ |
| 1991 | &dss_ick, |
| 1992 | &dss1_fck, |
| 1993 | &dss2_fck, |
| 1994 | &dss_54m_fck, |
| 1995 | /* L3 domain clocks */ |
| 1996 | &core_l3_ck, |
| 1997 | &ssi_ssr_sst_fck, |
| 1998 | &usb_l4_ick, |
| 1999 | /* L4 domain clocks */ |
| 2000 | &l4_ck, /* used as both core_l4 and wu_l4 */ |
| 2001 | &ssi_l4_ick, |
| 2002 | /* virtual meta-group clock */ |
| 2003 | &virt_prcm_set, |
| 2004 | /* general l4 interface ck, multi-parent functional clk */ |
| 2005 | &gpt1_ick, |
| 2006 | &gpt1_fck, |
| 2007 | &gpt2_ick, |
| 2008 | &gpt2_fck, |
| 2009 | &gpt3_ick, |
| 2010 | &gpt3_fck, |
| 2011 | &gpt4_ick, |
| 2012 | &gpt4_fck, |
| 2013 | &gpt5_ick, |
| 2014 | &gpt5_fck, |
| 2015 | &gpt6_ick, |
| 2016 | &gpt6_fck, |
| 2017 | &gpt7_ick, |
| 2018 | &gpt7_fck, |
| 2019 | &gpt8_ick, |
| 2020 | &gpt8_fck, |
| 2021 | &gpt9_ick, |
| 2022 | &gpt9_fck, |
| 2023 | &gpt10_ick, |
| 2024 | &gpt10_fck, |
| 2025 | &gpt11_ick, |
| 2026 | &gpt11_fck, |
| 2027 | &gpt12_ick, |
| 2028 | &gpt12_fck, |
| 2029 | &mcbsp1_ick, |
| 2030 | &mcbsp1_fck, |
| 2031 | &mcbsp2_ick, |
| 2032 | &mcbsp2_fck, |
| 2033 | &mcbsp3_ick, |
| 2034 | &mcbsp3_fck, |
| 2035 | &mcbsp4_ick, |
| 2036 | &mcbsp4_fck, |
| 2037 | &mcbsp5_ick, |
| 2038 | &mcbsp5_fck, |
| 2039 | &mcspi1_ick, |
| 2040 | &mcspi1_fck, |
| 2041 | &mcspi2_ick, |
| 2042 | &mcspi2_fck, |
| 2043 | &mcspi3_ick, |
| 2044 | &mcspi3_fck, |
| 2045 | &uart1_ick, |
| 2046 | &uart1_fck, |
| 2047 | &uart2_ick, |
| 2048 | &uart2_fck, |
| 2049 | &uart3_ick, |
| 2050 | &uart3_fck, |
| 2051 | &gpios_ick, |
| 2052 | &gpios_fck, |
| 2053 | &mpu_wdt_ick, |
| 2054 | &mpu_wdt_fck, |
| 2055 | &sync_32k_ick, |
| 2056 | &wdt1_ick, |
| 2057 | &omapctrl_ick, |
| 2058 | &icr_ick, |
| 2059 | &cam_fck, |
| 2060 | &cam_ick, |
| 2061 | &mailboxes_ick, |
| 2062 | &wdt4_ick, |
| 2063 | &wdt4_fck, |
| 2064 | &wdt3_ick, |
| 2065 | &wdt3_fck, |
| 2066 | &mspro_ick, |
| 2067 | &mspro_fck, |
| 2068 | &mmc_ick, |
| 2069 | &mmc_fck, |
| 2070 | &fac_ick, |
| 2071 | &fac_fck, |
| 2072 | &eac_ick, |
| 2073 | &eac_fck, |
| 2074 | &hdq_ick, |
| 2075 | &hdq_fck, |
| 2076 | &i2c1_ick, |
| 2077 | &i2c1_fck, |
| 2078 | &i2chs1_fck, |
| 2079 | &i2c2_ick, |
| 2080 | &i2c2_fck, |
| 2081 | &i2chs2_fck, |
| 2082 | &vlynq_ick, |
| 2083 | &vlynq_fck, |
| 2084 | &sdrc_ick, |
| 2085 | &des_ick, |
| 2086 | &sha_ick, |
| 2087 | &rng_ick, |
| 2088 | &aes_ick, |
| 2089 | &pka_ick, |
| 2090 | &usb_fck, |
| 2091 | &usbhs_ick, |
| 2092 | &mmchs1_ick, |
| 2093 | &mmchs1_fck, |
| 2094 | &mmchs2_ick, |
| 2095 | &mmchs2_fck, |
| 2096 | &gpio5_ick, |
| 2097 | &gpio5_fck, |
| 2098 | &mdm_intc_ick, |
| 2099 | &mmchsdb1_fck, |
| 2100 | &mmchsdb2_fck, |
| 2101 | }; |
| 2102 | |
| 2103 | #endif |