blob: 250f4d4b94368c6158917d701dabf12026f9eb0d [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
Bryan Wu1394f032007-05-06 14:50:22 -07003 *
Robin Getz96f10502009-09-24 14:11:24 +00004 * Copyright 2005-2009 Analog Devices Inc.
5 * 2005 BuyWays BV
6 * Bas Vermeulen <bas@buyways.nl>
Bryan Wu1394f032007-05-06 14:50:22 -07007 *
Robin Getz96f10502009-09-24 14:11:24 +00008 * Licensed under the GPL-2.
Bryan Wu1394f032007-05-06 14:50:22 -07009 */
10
11#include <linux/linkage.h>
12
13.align 2
14
15ENTRY(_outsl)
16 P0 = R0; /* P0 = port */
17 P1 = R1; /* P1 = address */
18 P2 = R2; /* P2 = count */
19
20 LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
21.Llong_loop_s: R0 = [P1++];
22.Llong_loop_e: [P0] = R0;
23 RTS;
Mike Frysinger51be24c2007-06-11 15:31:30 +080024ENDPROC(_outsl)
Bryan Wu1394f032007-05-06 14:50:22 -070025
26ENTRY(_outsw)
27 P0 = R0; /* P0 = port */
28 P1 = R1; /* P1 = address */
29 P2 = R2; /* P2 = count */
30
31 LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
32.Lword_loop_s: R0 = W[P1++];
33.Lword_loop_e: W[P0] = R0;
34 RTS;
Mike Frysinger51be24c2007-06-11 15:31:30 +080035ENDPROC(_outsw)
Bryan Wu1394f032007-05-06 14:50:22 -070036
37ENTRY(_outsb)
38 P0 = R0; /* P0 = port */
39 P1 = R1; /* P1 = address */
40 P2 = R2; /* P2 = count */
41
42 LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
43.Lbyte_loop_s: R0 = B[P1++];
44.Lbyte_loop_e: B[P0] = R0;
45 RTS;
Mike Frysinger51be24c2007-06-11 15:31:30 +080046ENDPROC(_outsb)
Michael Hennerich59069672008-05-17 16:38:52 +080047
48ENTRY(_outsw_8)
49 P0 = R0; /* P0 = port */
50 P1 = R1; /* P1 = address */
51 P2 = R2; /* P2 = count */
52
53 LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
54.Lword8_loop_s: R1 = B[P1++];
55 R0 = B[P1++];
56 R0 = R0 << 8;
57 R0 = R0 + R1;
58.Lword8_loop_e: W[P0] = R0;
59 RTS;
Bryan Wuca56d9a2008-05-20 16:45:29 +080060ENDPROC(_outsw_8)