Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. |
| 3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. |
| 4 | |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public |
| 7 | * License as published by the Free Software Foundation; |
| 8 | * either version 2, or (at your option) any later version. |
| 9 | |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even |
| 12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR |
| 13 | * A PARTICULAR PURPOSE.See the GNU General Public License |
| 14 | * for more details. |
| 15 | |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., |
| 19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 20 | */ |
Jonathan Corbet | ec66841 | 2010-05-05 14:44:55 -0600 | [diff] [blame] | 21 | |
| 22 | #include <linux/via-core.h> |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 23 | #include "global.h" |
| 24 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 25 | static struct pll_limit cle266_pll_limits[] = { |
| 26 | {19, 19, 4, 0}, |
| 27 | {26, 102, 5, 0}, |
| 28 | {53, 112, 6, 0}, |
| 29 | {41, 100, 7, 0}, |
| 30 | {83, 108, 8, 0}, |
| 31 | {87, 118, 9, 0}, |
| 32 | {95, 115, 12, 0}, |
| 33 | {108, 108, 13, 0}, |
| 34 | {83, 83, 17, 0}, |
| 35 | {67, 98, 20, 0}, |
| 36 | {121, 121, 24, 0}, |
| 37 | {99, 99, 29, 0}, |
| 38 | {33, 33, 3, 1}, |
| 39 | {15, 23, 4, 1}, |
| 40 | {37, 121, 5, 1}, |
| 41 | {82, 82, 6, 1}, |
| 42 | {31, 84, 7, 1}, |
| 43 | {83, 83, 8, 1}, |
| 44 | {76, 127, 9, 1}, |
| 45 | {33, 121, 4, 2}, |
| 46 | {91, 118, 5, 2}, |
| 47 | {83, 109, 6, 2}, |
| 48 | {90, 90, 7, 2}, |
| 49 | {93, 93, 2, 3}, |
| 50 | {53, 53, 3, 3}, |
| 51 | {73, 117, 4, 3}, |
| 52 | {101, 127, 5, 3}, |
| 53 | {99, 99, 7, 3} |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 54 | }; |
| 55 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 56 | static struct pll_limit k800_pll_limits[] = { |
| 57 | {22, 22, 2, 0}, |
| 58 | {28, 28, 3, 0}, |
| 59 | {81, 112, 3, 1}, |
| 60 | {86, 166, 4, 1}, |
| 61 | {109, 153, 5, 1}, |
| 62 | {66, 116, 3, 2}, |
| 63 | {93, 137, 4, 2}, |
| 64 | {117, 208, 5, 2}, |
| 65 | {30, 30, 2, 3}, |
| 66 | {69, 125, 3, 3}, |
| 67 | {89, 161, 4, 3}, |
| 68 | {121, 208, 5, 3}, |
| 69 | {66, 66, 2, 4}, |
| 70 | {85, 85, 3, 4}, |
| 71 | {141, 161, 4, 4}, |
| 72 | {177, 177, 5, 4} |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 73 | }; |
| 74 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 75 | static struct pll_limit cx700_pll_limits[] = { |
| 76 | {98, 98, 3, 1}, |
| 77 | {86, 86, 4, 1}, |
| 78 | {109, 208, 5, 1}, |
| 79 | {68, 68, 2, 2}, |
| 80 | {95, 116, 3, 2}, |
| 81 | {93, 166, 4, 2}, |
| 82 | {110, 206, 5, 2}, |
| 83 | {174, 174, 7, 2}, |
| 84 | {82, 109, 3, 3}, |
| 85 | {117, 161, 4, 3}, |
| 86 | {112, 208, 5, 3}, |
| 87 | {141, 202, 5, 4} |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 88 | }; |
| 89 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 90 | static struct pll_limit vx855_pll_limits[] = { |
| 91 | {86, 86, 4, 1}, |
| 92 | {108, 208, 5, 1}, |
| 93 | {110, 208, 5, 2}, |
| 94 | {83, 112, 3, 3}, |
| 95 | {103, 161, 4, 3}, |
| 96 | {112, 209, 5, 3}, |
| 97 | {142, 161, 4, 4}, |
| 98 | {141, 176, 5, 4} |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 99 | }; |
| 100 | |
Florian Tobias Schandinat | bf5ea02 | 2011-01-05 10:36:05 +0000 | [diff] [blame] | 101 | /* according to VIA Technologies these values are based on experiment */ |
| 102 | static struct io_reg scaling_parameters[] = { |
| 103 | {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */ |
| 104 | {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */ |
| 105 | {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */ |
| 106 | {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */ |
| 107 | {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */ |
| 108 | {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */ |
| 109 | {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */ |
| 110 | {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */ |
| 111 | {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */ |
| 112 | {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */ |
| 113 | {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */ |
| 114 | {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */ |
| 115 | {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */ |
| 116 | {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */ |
| 117 | }; |
| 118 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 119 | static struct fifo_depth_select display_fifo_depth_reg = { |
| 120 | /* IGA1 FIFO Depth_Select */ |
| 121 | {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } }, |
| 122 | /* IGA2 FIFO Depth_Select */ |
| 123 | {IGA2_FIFO_DEPTH_SELECT_REG_NUM, |
| 124 | {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } } |
| 125 | }; |
| 126 | |
| 127 | static struct fifo_threshold_select fifo_threshold_select_reg = { |
| 128 | /* IGA1 FIFO Threshold Select */ |
| 129 | {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } }, |
| 130 | /* IGA2 FIFO Threshold Select */ |
| 131 | {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } } |
| 132 | }; |
| 133 | |
| 134 | static struct fifo_high_threshold_select fifo_high_threshold_select_reg = { |
| 135 | /* IGA1 FIFO High Threshold Select */ |
| 136 | {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } }, |
| 137 | /* IGA2 FIFO High Threshold Select */ |
| 138 | {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } } |
| 139 | }; |
| 140 | |
| 141 | static struct display_queue_expire_num display_queue_expire_num_reg = { |
| 142 | /* IGA1 Display Queue Expire Num */ |
| 143 | {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } }, |
| 144 | /* IGA2 Display Queue Expire Num */ |
| 145 | {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } } |
| 146 | }; |
| 147 | |
| 148 | /* Definition Fetch Count Registers*/ |
| 149 | static struct fetch_count fetch_count_reg = { |
| 150 | /* IGA1 Fetch Count Register */ |
| 151 | {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } }, |
| 152 | /* IGA2 Fetch Count Register */ |
| 153 | {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } } |
| 154 | }; |
| 155 | |
| 156 | static struct iga1_crtc_timing iga1_crtc_reg = { |
| 157 | /* IGA1 Horizontal Total */ |
| 158 | {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } }, |
| 159 | /* IGA1 Horizontal Addressable Video */ |
| 160 | {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } }, |
| 161 | /* IGA1 Horizontal Blank Start */ |
| 162 | {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } }, |
| 163 | /* IGA1 Horizontal Blank End */ |
| 164 | {IGA1_HOR_BLANK_END_REG_NUM, |
| 165 | {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } }, |
| 166 | /* IGA1 Horizontal Sync Start */ |
| 167 | {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } }, |
| 168 | /* IGA1 Horizontal Sync End */ |
| 169 | {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } }, |
| 170 | /* IGA1 Vertical Total */ |
| 171 | {IGA1_VER_TOTAL_REG_NUM, |
| 172 | {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } }, |
| 173 | /* IGA1 Vertical Addressable Video */ |
| 174 | {IGA1_VER_ADDR_REG_NUM, |
| 175 | {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } }, |
| 176 | /* IGA1 Vertical Blank Start */ |
| 177 | {IGA1_VER_BLANK_START_REG_NUM, |
| 178 | {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } }, |
| 179 | /* IGA1 Vertical Blank End */ |
| 180 | {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } }, |
| 181 | /* IGA1 Vertical Sync Start */ |
| 182 | {IGA1_VER_SYNC_START_REG_NUM, |
| 183 | {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } }, |
| 184 | /* IGA1 Vertical Sync End */ |
| 185 | {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } } |
| 186 | }; |
| 187 | |
| 188 | static struct iga2_crtc_timing iga2_crtc_reg = { |
| 189 | /* IGA2 Horizontal Total */ |
| 190 | {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } }, |
| 191 | /* IGA2 Horizontal Addressable Video */ |
| 192 | {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } }, |
| 193 | /* IGA2 Horizontal Blank Start */ |
| 194 | {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } }, |
| 195 | /* IGA2 Horizontal Blank End */ |
| 196 | {IGA2_HOR_BLANK_END_REG_NUM, |
| 197 | {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } }, |
| 198 | /* IGA2 Horizontal Sync Start */ |
| 199 | {IGA2_HOR_SYNC_START_REG_NUM, |
| 200 | {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } }, |
| 201 | /* IGA2 Horizontal Sync End */ |
| 202 | {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } }, |
| 203 | /* IGA2 Vertical Total */ |
| 204 | {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } }, |
| 205 | /* IGA2 Vertical Addressable Video */ |
| 206 | {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } }, |
| 207 | /* IGA2 Vertical Blank Start */ |
| 208 | {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } }, |
| 209 | /* IGA2 Vertical Blank End */ |
| 210 | {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } }, |
| 211 | /* IGA2 Vertical Sync Start */ |
| 212 | {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } }, |
| 213 | /* IGA2 Vertical Sync End */ |
| 214 | {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } } |
| 215 | }; |
| 216 | |
| 217 | static struct rgbLUT palLUT_table[] = { |
| 218 | /* {R,G,B} */ |
| 219 | /* Index 0x00~0x03 */ |
| 220 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00, |
| 221 | 0x2A, |
| 222 | 0x2A}, |
| 223 | /* Index 0x04~0x07 */ |
| 224 | {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A, |
| 225 | 0x2A, |
| 226 | 0x2A}, |
| 227 | /* Index 0x08~0x0B */ |
| 228 | {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15, |
| 229 | 0x3F, |
| 230 | 0x3F}, |
| 231 | /* Index 0x0C~0x0F */ |
| 232 | {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F, |
| 233 | 0x3F, |
| 234 | 0x3F}, |
| 235 | /* Index 0x10~0x13 */ |
| 236 | {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B, |
| 237 | 0x0B, |
| 238 | 0x0B}, |
| 239 | /* Index 0x14~0x17 */ |
| 240 | {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18, |
| 241 | 0x18, |
| 242 | 0x18}, |
| 243 | /* Index 0x18~0x1B */ |
| 244 | {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28, |
| 245 | 0x28, |
| 246 | 0x28}, |
| 247 | /* Index 0x1C~0x1F */ |
| 248 | {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F, |
| 249 | 0x3F, |
| 250 | 0x3F}, |
| 251 | /* Index 0x20~0x23 */ |
| 252 | {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F, |
| 253 | 0x00, |
| 254 | 0x3F}, |
| 255 | /* Index 0x24~0x27 */ |
| 256 | {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F, |
| 257 | 0x00, |
| 258 | 0x10}, |
| 259 | /* Index 0x28~0x2B */ |
| 260 | {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F, |
| 261 | 0x2F, |
| 262 | 0x00}, |
| 263 | /* Index 0x2C~0x2F */ |
| 264 | {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10, |
| 265 | 0x3F, |
| 266 | 0x00}, |
| 267 | /* Index 0x30~0x33 */ |
| 268 | {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00, |
| 269 | 0x3F, |
| 270 | 0x2F}, |
| 271 | /* Index 0x34~0x37 */ |
| 272 | {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00, |
| 273 | 0x10, |
| 274 | 0x3F}, |
| 275 | /* Index 0x38~0x3B */ |
| 276 | {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37, |
| 277 | 0x1F, |
| 278 | 0x3F}, |
| 279 | /* Index 0x3C~0x3F */ |
| 280 | {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F, |
| 281 | 0x1F, |
| 282 | 0x27}, |
| 283 | /* Index 0x40~0x43 */ |
| 284 | {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F, |
| 285 | 0x3F, |
| 286 | 0x1F}, |
| 287 | /* Index 0x44~0x47 */ |
| 288 | {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27, |
| 289 | 0x3F, |
| 290 | 0x1F}, |
| 291 | /* Index 0x48~0x4B */ |
| 292 | {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F, |
| 293 | 0x3F, |
| 294 | 0x37}, |
| 295 | /* Index 0x4C~0x4F */ |
| 296 | {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F, |
| 297 | 0x27, |
| 298 | 0x3F}, |
| 299 | /* Index 0x50~0x53 */ |
| 300 | {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A, |
| 301 | 0x2D, |
| 302 | 0x3F}, |
| 303 | /* Index 0x54~0x57 */ |
| 304 | {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F, |
| 305 | 0x2D, |
| 306 | 0x31}, |
| 307 | /* Index 0x58~0x5B */ |
| 308 | {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F, |
| 309 | 0x3A, |
| 310 | 0x2D}, |
| 311 | /* Index 0x5C~0x5F */ |
| 312 | {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31, |
| 313 | 0x3F, |
| 314 | 0x2D}, |
| 315 | /* Index 0x60~0x63 */ |
| 316 | {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D, |
| 317 | 0x3F, |
| 318 | 0x3A}, |
| 319 | /* Index 0x64~0x67 */ |
| 320 | {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D, |
| 321 | 0x31, |
| 322 | 0x3F}, |
| 323 | /* Index 0x68~0x6B */ |
| 324 | {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15, |
| 325 | 0x00, |
| 326 | 0x1C}, |
| 327 | /* Index 0x6C~0x6F */ |
| 328 | {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C, |
| 329 | 0x00, |
| 330 | 0x07}, |
| 331 | /* Index 0x70~0x73 */ |
| 332 | {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C, |
| 333 | 0x15, |
| 334 | 0x00}, |
| 335 | /* Index 0x74~0x77 */ |
| 336 | {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07, |
| 337 | 0x1C, |
| 338 | 0x00}, |
| 339 | /* Index 0x78~0x7B */ |
| 340 | {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00, |
| 341 | 0x1C, |
| 342 | 0x15}, |
| 343 | /* Index 0x7C~0x7F */ |
| 344 | {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00, |
| 345 | 0x07, |
| 346 | 0x1C}, |
| 347 | /* Index 0x80~0x83 */ |
| 348 | {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18, |
| 349 | 0x0E, |
| 350 | 0x1C}, |
| 351 | /* Index 0x84~0x87 */ |
| 352 | {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C, |
| 353 | 0x0E, |
| 354 | 0x11}, |
| 355 | /* Index 0x88~0x8B */ |
| 356 | {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C, |
| 357 | 0x18, |
| 358 | 0x0E}, |
| 359 | /* Index 0x8C~0x8F */ |
| 360 | {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11, |
| 361 | 0x1C, |
| 362 | 0x0E}, |
| 363 | /* Index 0x90~0x93 */ |
| 364 | {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E, |
| 365 | 0x1C, |
| 366 | 0x18}, |
| 367 | /* Index 0x94~0x97 */ |
| 368 | {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E, |
| 369 | 0x11, |
| 370 | 0x1C}, |
| 371 | /* Index 0x98~0x9B */ |
| 372 | {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A, |
| 373 | 0x14, |
| 374 | 0x1C}, |
| 375 | /* Index 0x9C~0x9F */ |
| 376 | {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C, |
| 377 | 0x14, |
| 378 | 0x16}, |
| 379 | /* Index 0xA0~0xA3 */ |
| 380 | {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C, |
| 381 | 0x1A, |
| 382 | 0x14}, |
| 383 | /* Index 0xA4~0xA7 */ |
| 384 | {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16, |
| 385 | 0x1C, |
| 386 | 0x14}, |
| 387 | /* Index 0xA8~0xAB */ |
| 388 | {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14, |
| 389 | 0x1C, |
| 390 | 0x1A}, |
| 391 | /* Index 0xAC~0xAF */ |
| 392 | {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14, |
| 393 | 0x16, |
| 394 | 0x1C}, |
| 395 | /* Index 0xB0~0xB3 */ |
| 396 | {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C, |
| 397 | 0x00, |
| 398 | 0x10}, |
| 399 | /* Index 0xB4~0xB7 */ |
| 400 | {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10, |
| 401 | 0x00, |
| 402 | 0x04}, |
| 403 | /* Index 0xB8~0xBB */ |
| 404 | {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10, |
| 405 | 0x0C, |
| 406 | 0x00}, |
| 407 | /* Index 0xBC~0xBF */ |
| 408 | {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04, |
| 409 | 0x10, |
| 410 | 0x00}, |
| 411 | /* Index 0xC0~0xC3 */ |
| 412 | {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00, |
| 413 | 0x10, |
| 414 | 0x0C}, |
| 415 | /* Index 0xC4~0xC7 */ |
| 416 | {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00, |
| 417 | 0x04, |
| 418 | 0x10}, |
| 419 | /* Index 0xC8~0xCB */ |
| 420 | {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E, |
| 421 | 0x08, |
| 422 | 0x10}, |
| 423 | /* Index 0xCC~0xCF */ |
| 424 | {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10, |
| 425 | 0x08, |
| 426 | 0x0A}, |
| 427 | /* Index 0xD0~0xD3 */ |
| 428 | {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10, |
| 429 | 0x0E, |
| 430 | 0x08}, |
| 431 | /* Index 0xD4~0xD7 */ |
| 432 | {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A, |
| 433 | 0x10, |
| 434 | 0x08}, |
| 435 | /* Index 0xD8~0xDB */ |
| 436 | {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08, |
| 437 | 0x10, |
| 438 | 0x0E}, |
| 439 | /* Index 0xDC~0xDF */ |
| 440 | {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08, |
| 441 | 0x0A, |
| 442 | 0x10}, |
| 443 | /* Index 0xE0~0xE3 */ |
| 444 | {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F, |
| 445 | 0x0B, |
| 446 | 0x10}, |
| 447 | /* Index 0xE4~0xE7 */ |
| 448 | {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10, |
| 449 | 0x0B, |
| 450 | 0x0C}, |
| 451 | /* Index 0xE8~0xEB */ |
| 452 | {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10, |
| 453 | 0x0F, |
| 454 | 0x0B}, |
| 455 | /* Index 0xEC~0xEF */ |
| 456 | {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C, |
| 457 | 0x10, |
| 458 | 0x0B}, |
| 459 | /* Index 0xF0~0xF3 */ |
| 460 | {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B, |
| 461 | 0x10, |
| 462 | 0x0F}, |
| 463 | /* Index 0xF4~0xF7 */ |
| 464 | {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B, |
| 465 | 0x0C, |
| 466 | 0x10}, |
| 467 | /* Index 0xF8~0xFB */ |
| 468 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, |
| 469 | 0x00, |
| 470 | 0x00}, |
| 471 | /* Index 0xFC~0xFF */ |
| 472 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, |
| 473 | 0x00, |
| 474 | 0x00} |
| 475 | }; |
| 476 | |
Florian Tobias Schandinat | 2a91839 | 2010-09-05 01:33:28 +0000 | [diff] [blame] | 477 | static struct via_device_mapping device_mapping[] = { |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 478 | {VIA_LDVP0, "LDVP0"}, |
| 479 | {VIA_LDVP1, "LDVP1"}, |
| 480 | {VIA_DVP0, "DVP0"}, |
Florian Tobias Schandinat | 2a91839 | 2010-09-05 01:33:28 +0000 | [diff] [blame] | 481 | {VIA_CRT, "CRT"}, |
| 482 | {VIA_DVP1, "DVP1"}, |
| 483 | {VIA_LVDS1, "LVDS1"}, |
| 484 | {VIA_LVDS2, "LVDS2"} |
| 485 | }; |
| 486 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 487 | static void load_fix_bit_crtc_reg(void); |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 488 | static void __devinit init_gfx_chip_info(int chip_type); |
| 489 | static void __devinit init_tmds_chip_info(void); |
| 490 | static void __devinit init_lvds_chip_info(void); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 491 | static void device_screen_off(void); |
| 492 | static void device_screen_on(void); |
| 493 | static void set_display_channel(void); |
| 494 | static void device_off(void); |
| 495 | static void device_on(void); |
| 496 | static void enable_second_display_channel(void); |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 497 | static void disable_second_display_channel(void); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 498 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 499 | void viafb_lock_crt(void) |
| 500 | { |
| 501 | viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); |
| 502 | } |
| 503 | |
| 504 | void viafb_unlock_crt(void) |
| 505 | { |
| 506 | viafb_write_reg_mask(CR11, VIACR, 0, BIT7); |
| 507 | viafb_write_reg_mask(CR47, VIACR, 0, BIT0); |
| 508 | } |
| 509 | |
Stephen Hemminger | 23e5abd | 2011-03-03 10:00:08 -0800 | [diff] [blame] | 510 | static void write_dac_reg(u8 index, u8 r, u8 g, u8 b) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 511 | { |
| 512 | outb(index, LUT_INDEX_WRITE); |
| 513 | outb(r, LUT_DATA); |
| 514 | outb(g, LUT_DATA); |
| 515 | outb(b, LUT_DATA); |
| 516 | } |
| 517 | |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 518 | static u32 get_dvi_devices(int output_interface) |
| 519 | { |
| 520 | switch (output_interface) { |
| 521 | case INTERFACE_DVP0: |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 522 | return VIA_DVP0 | VIA_LDVP0; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 523 | |
| 524 | case INTERFACE_DVP1: |
| 525 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 526 | return VIA_LDVP1; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 527 | else |
| 528 | return VIA_DVP1; |
| 529 | |
| 530 | case INTERFACE_DFP_HIGH: |
| 531 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
| 532 | return 0; |
| 533 | else |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 534 | return VIA_LVDS2 | VIA_DVP0; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 535 | |
| 536 | case INTERFACE_DFP_LOW: |
| 537 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
| 538 | return 0; |
| 539 | else |
| 540 | return VIA_DVP1 | VIA_LVDS1; |
| 541 | |
| 542 | case INTERFACE_TMDS: |
| 543 | return VIA_LVDS1; |
| 544 | } |
| 545 | |
| 546 | return 0; |
| 547 | } |
| 548 | |
| 549 | static u32 get_lcd_devices(int output_interface) |
| 550 | { |
| 551 | switch (output_interface) { |
| 552 | case INTERFACE_DVP0: |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 553 | return VIA_DVP0; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 554 | |
| 555 | case INTERFACE_DVP1: |
| 556 | return VIA_DVP1; |
| 557 | |
| 558 | case INTERFACE_DFP_HIGH: |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 559 | return VIA_LVDS2 | VIA_DVP0; |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 560 | |
| 561 | case INTERFACE_DFP_LOW: |
| 562 | return VIA_LVDS1 | VIA_DVP1; |
| 563 | |
| 564 | case INTERFACE_DFP: |
| 565 | return VIA_LVDS1 | VIA_LVDS2; |
| 566 | |
| 567 | case INTERFACE_LVDS0: |
| 568 | case INTERFACE_LVDS0LVDS1: |
| 569 | return VIA_LVDS1; |
| 570 | |
| 571 | case INTERFACE_LVDS1: |
| 572 | return VIA_LVDS2; |
| 573 | } |
| 574 | |
| 575 | return 0; |
| 576 | } |
| 577 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 578 | /*Set IGA path for each device*/ |
| 579 | void viafb_set_iga_path(void) |
| 580 | { |
| 581 | |
| 582 | if (viafb_SAMM_ON == 1) { |
| 583 | if (viafb_CRT_ON) { |
| 584 | if (viafb_primary_dev == CRT_Device) |
| 585 | viaparinfo->crt_setting_info->iga_path = IGA1; |
| 586 | else |
| 587 | viaparinfo->crt_setting_info->iga_path = IGA2; |
| 588 | } |
| 589 | |
| 590 | if (viafb_DVI_ON) { |
| 591 | if (viafb_primary_dev == DVI_Device) |
| 592 | viaparinfo->tmds_setting_info->iga_path = IGA1; |
| 593 | else |
| 594 | viaparinfo->tmds_setting_info->iga_path = IGA2; |
| 595 | } |
| 596 | |
| 597 | if (viafb_LCD_ON) { |
| 598 | if (viafb_primary_dev == LCD_Device) { |
| 599 | if (viafb_dual_fb && |
| 600 | (viaparinfo->chip_info->gfx_chip_name == |
| 601 | UNICHROME_CLE266)) { |
| 602 | viaparinfo-> |
| 603 | lvds_setting_info->iga_path = IGA2; |
| 604 | viaparinfo-> |
| 605 | crt_setting_info->iga_path = IGA1; |
| 606 | viaparinfo-> |
| 607 | tmds_setting_info->iga_path = IGA1; |
| 608 | } else |
| 609 | viaparinfo-> |
| 610 | lvds_setting_info->iga_path = IGA1; |
| 611 | } else { |
| 612 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 613 | } |
| 614 | } |
| 615 | if (viafb_LCD2_ON) { |
| 616 | if (LCD2_Device == viafb_primary_dev) |
| 617 | viaparinfo->lvds_setting_info2->iga_path = IGA1; |
| 618 | else |
| 619 | viaparinfo->lvds_setting_info2->iga_path = IGA2; |
| 620 | } |
| 621 | } else { |
| 622 | viafb_SAMM_ON = 0; |
| 623 | |
| 624 | if (viafb_CRT_ON && viafb_LCD_ON) { |
| 625 | viaparinfo->crt_setting_info->iga_path = IGA1; |
| 626 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 627 | } else if (viafb_CRT_ON && viafb_DVI_ON) { |
| 628 | viaparinfo->crt_setting_info->iga_path = IGA1; |
| 629 | viaparinfo->tmds_setting_info->iga_path = IGA2; |
| 630 | } else if (viafb_LCD_ON && viafb_DVI_ON) { |
| 631 | viaparinfo->tmds_setting_info->iga_path = IGA1; |
| 632 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 633 | } else if (viafb_LCD_ON && viafb_LCD2_ON) { |
| 634 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 635 | viaparinfo->lvds_setting_info2->iga_path = IGA2; |
| 636 | } else if (viafb_CRT_ON) { |
| 637 | viaparinfo->crt_setting_info->iga_path = IGA1; |
| 638 | } else if (viafb_LCD_ON) { |
| 639 | viaparinfo->lvds_setting_info->iga_path = IGA2; |
| 640 | } else if (viafb_DVI_ON) { |
| 641 | viaparinfo->tmds_setting_info->iga_path = IGA1; |
| 642 | } |
| 643 | } |
Florian Tobias Schandinat | 18d9dc0 | 2010-08-10 02:44:44 +0000 | [diff] [blame] | 644 | |
| 645 | viaparinfo->shared->iga1_devices = 0; |
| 646 | viaparinfo->shared->iga2_devices = 0; |
| 647 | if (viafb_CRT_ON) { |
| 648 | if (viaparinfo->crt_setting_info->iga_path == IGA1) |
| 649 | viaparinfo->shared->iga1_devices |= VIA_CRT; |
| 650 | else |
| 651 | viaparinfo->shared->iga2_devices |= VIA_CRT; |
| 652 | } |
| 653 | |
| 654 | if (viafb_DVI_ON) { |
| 655 | if (viaparinfo->tmds_setting_info->iga_path == IGA1) |
| 656 | viaparinfo->shared->iga1_devices |= get_dvi_devices( |
| 657 | viaparinfo->chip_info-> |
| 658 | tmds_chip_info.output_interface); |
| 659 | else |
| 660 | viaparinfo->shared->iga2_devices |= get_dvi_devices( |
| 661 | viaparinfo->chip_info-> |
| 662 | tmds_chip_info.output_interface); |
| 663 | } |
| 664 | |
| 665 | if (viafb_LCD_ON) { |
| 666 | if (viaparinfo->lvds_setting_info->iga_path == IGA1) |
| 667 | viaparinfo->shared->iga1_devices |= get_lcd_devices( |
| 668 | viaparinfo->chip_info-> |
| 669 | lvds_chip_info.output_interface); |
| 670 | else |
| 671 | viaparinfo->shared->iga2_devices |= get_lcd_devices( |
| 672 | viaparinfo->chip_info-> |
| 673 | lvds_chip_info.output_interface); |
| 674 | } |
| 675 | |
| 676 | if (viafb_LCD2_ON) { |
| 677 | if (viaparinfo->lvds_setting_info2->iga_path == IGA1) |
| 678 | viaparinfo->shared->iga1_devices |= get_lcd_devices( |
| 679 | viaparinfo->chip_info-> |
| 680 | lvds_chip_info2.output_interface); |
| 681 | else |
| 682 | viaparinfo->shared->iga2_devices |= get_lcd_devices( |
| 683 | viaparinfo->chip_info-> |
| 684 | lvds_chip_info2.output_interface); |
| 685 | } |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 686 | } |
| 687 | |
Florian Tobias Schandinat | 415559f | 2010-03-10 15:21:40 -0800 | [diff] [blame] | 688 | static void set_color_register(u8 index, u8 red, u8 green, u8 blue) |
| 689 | { |
| 690 | outb(0xFF, 0x3C6); /* bit mask of palette */ |
| 691 | outb(index, 0x3C8); |
| 692 | outb(red, 0x3C9); |
| 693 | outb(green, 0x3C9); |
| 694 | outb(blue, 0x3C9); |
| 695 | } |
| 696 | |
| 697 | void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue) |
| 698 | { |
| 699 | viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01); |
| 700 | set_color_register(index, red, green, blue); |
| 701 | } |
| 702 | |
| 703 | void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue) |
| 704 | { |
| 705 | viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01); |
| 706 | set_color_register(index, red, green, blue); |
| 707 | } |
| 708 | |
Florian Tobias Schandinat | a54be17 | 2010-07-28 23:06:04 +0000 | [diff] [blame] | 709 | static void set_source_common(u8 index, u8 offset, u8 iga) |
| 710 | { |
| 711 | u8 value, mask = 1 << offset; |
| 712 | |
| 713 | switch (iga) { |
| 714 | case IGA1: |
| 715 | value = 0x00; |
| 716 | break; |
| 717 | case IGA2: |
| 718 | value = mask; |
| 719 | break; |
| 720 | default: |
| 721 | printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga); |
| 722 | return; |
| 723 | } |
| 724 | |
| 725 | via_write_reg_mask(VIACR, index, value, mask); |
| 726 | } |
| 727 | |
| 728 | static void set_crt_source(u8 iga) |
| 729 | { |
| 730 | u8 value; |
| 731 | |
| 732 | switch (iga) { |
| 733 | case IGA1: |
| 734 | value = 0x00; |
| 735 | break; |
| 736 | case IGA2: |
| 737 | value = 0x40; |
| 738 | break; |
| 739 | default: |
| 740 | printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga); |
| 741 | return; |
| 742 | } |
| 743 | |
| 744 | via_write_reg_mask(VIASR, 0x16, value, 0x40); |
| 745 | } |
| 746 | |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 747 | static inline void set_ldvp0_source(u8 iga) |
Florian Tobias Schandinat | a54be17 | 2010-07-28 23:06:04 +0000 | [diff] [blame] | 748 | { |
| 749 | set_source_common(0x6C, 7, iga); |
| 750 | } |
| 751 | |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 752 | static inline void set_ldvp1_source(u8 iga) |
Florian Tobias Schandinat | a54be17 | 2010-07-28 23:06:04 +0000 | [diff] [blame] | 753 | { |
| 754 | set_source_common(0x93, 7, iga); |
| 755 | } |
| 756 | |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 757 | static inline void set_dvp0_source(u8 iga) |
Florian Tobias Schandinat | a54be17 | 2010-07-28 23:06:04 +0000 | [diff] [blame] | 758 | { |
| 759 | set_source_common(0x96, 4, iga); |
| 760 | } |
| 761 | |
| 762 | static inline void set_dvp1_source(u8 iga) |
| 763 | { |
| 764 | set_source_common(0x9B, 4, iga); |
| 765 | } |
| 766 | |
| 767 | static inline void set_lvds1_source(u8 iga) |
| 768 | { |
| 769 | set_source_common(0x99, 4, iga); |
| 770 | } |
| 771 | |
| 772 | static inline void set_lvds2_source(u8 iga) |
| 773 | { |
| 774 | set_source_common(0x97, 4, iga); |
| 775 | } |
| 776 | |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 777 | void via_set_source(u32 devices, u8 iga) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 778 | { |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 779 | if (devices & VIA_LDVP0) |
| 780 | set_ldvp0_source(iga); |
| 781 | if (devices & VIA_LDVP1) |
| 782 | set_ldvp1_source(iga); |
| 783 | if (devices & VIA_DVP0) |
| 784 | set_dvp0_source(iga); |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 785 | if (devices & VIA_CRT) |
| 786 | set_crt_source(iga); |
| 787 | if (devices & VIA_DVP1) |
| 788 | set_dvp1_source(iga); |
| 789 | if (devices & VIA_LVDS1) |
| 790 | set_lvds1_source(iga); |
| 791 | if (devices & VIA_LVDS2) |
| 792 | set_lvds2_source(iga); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 793 | } |
| 794 | |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 795 | static void set_crt_state(u8 state) |
| 796 | { |
| 797 | u8 value; |
| 798 | |
| 799 | switch (state) { |
| 800 | case VIA_STATE_ON: |
| 801 | value = 0x00; |
| 802 | break; |
| 803 | case VIA_STATE_STANDBY: |
| 804 | value = 0x10; |
| 805 | break; |
| 806 | case VIA_STATE_SUSPEND: |
| 807 | value = 0x20; |
| 808 | break; |
| 809 | case VIA_STATE_OFF: |
| 810 | value = 0x30; |
| 811 | break; |
| 812 | default: |
| 813 | return; |
| 814 | } |
| 815 | |
| 816 | via_write_reg_mask(VIACR, 0x36, value, 0x30); |
| 817 | } |
| 818 | |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 819 | static void set_dvp0_state(u8 state) |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 820 | { |
| 821 | u8 value; |
| 822 | |
| 823 | switch (state) { |
| 824 | case VIA_STATE_ON: |
| 825 | value = 0xC0; |
| 826 | break; |
| 827 | case VIA_STATE_OFF: |
| 828 | value = 0x00; |
| 829 | break; |
| 830 | default: |
| 831 | return; |
| 832 | } |
| 833 | |
| 834 | via_write_reg_mask(VIASR, 0x1E, value, 0xC0); |
| 835 | } |
| 836 | |
| 837 | static void set_dvp1_state(u8 state) |
| 838 | { |
| 839 | u8 value; |
| 840 | |
| 841 | switch (state) { |
| 842 | case VIA_STATE_ON: |
| 843 | value = 0x30; |
| 844 | break; |
| 845 | case VIA_STATE_OFF: |
| 846 | value = 0x00; |
| 847 | break; |
| 848 | default: |
| 849 | return; |
| 850 | } |
| 851 | |
| 852 | via_write_reg_mask(VIASR, 0x1E, value, 0x30); |
| 853 | } |
| 854 | |
| 855 | static void set_lvds1_state(u8 state) |
| 856 | { |
| 857 | u8 value; |
| 858 | |
| 859 | switch (state) { |
| 860 | case VIA_STATE_ON: |
| 861 | value = 0x03; |
| 862 | break; |
| 863 | case VIA_STATE_OFF: |
| 864 | value = 0x00; |
| 865 | break; |
| 866 | default: |
| 867 | return; |
| 868 | } |
| 869 | |
| 870 | via_write_reg_mask(VIASR, 0x2A, value, 0x03); |
| 871 | } |
| 872 | |
| 873 | static void set_lvds2_state(u8 state) |
| 874 | { |
| 875 | u8 value; |
| 876 | |
| 877 | switch (state) { |
| 878 | case VIA_STATE_ON: |
| 879 | value = 0x0C; |
| 880 | break; |
| 881 | case VIA_STATE_OFF: |
| 882 | value = 0x00; |
| 883 | break; |
| 884 | default: |
| 885 | return; |
| 886 | } |
| 887 | |
| 888 | via_write_reg_mask(VIASR, 0x2A, value, 0x0C); |
| 889 | } |
| 890 | |
| 891 | void via_set_state(u32 devices, u8 state) |
| 892 | { |
| 893 | /* |
| 894 | TODO: Can we enable/disable these devices? How? |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 895 | if (devices & VIA_LDVP0) |
| 896 | if (devices & VIA_LDVP1) |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 897 | */ |
Florian Tobias Schandinat | a2aa9f9 | 2010-09-19 04:40:15 +0000 | [diff] [blame] | 898 | if (devices & VIA_DVP0) |
| 899 | set_dvp0_state(state); |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 900 | if (devices & VIA_CRT) |
| 901 | set_crt_state(state); |
| 902 | if (devices & VIA_DVP1) |
| 903 | set_dvp1_state(state); |
| 904 | if (devices & VIA_LVDS1) |
| 905 | set_lvds1_state(state); |
| 906 | if (devices & VIA_LVDS2) |
| 907 | set_lvds2_state(state); |
| 908 | } |
| 909 | |
Florian Tobias Schandinat | 7f0e153 | 2010-09-18 23:47:28 +0000 | [diff] [blame] | 910 | void via_set_sync_polarity(u32 devices, u8 polarity) |
| 911 | { |
| 912 | if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) { |
| 913 | printk(KERN_WARNING "viafb: Unsupported polarity: %d\n", |
| 914 | polarity); |
| 915 | return; |
| 916 | } |
| 917 | |
| 918 | if (devices & VIA_CRT) |
| 919 | via_write_misc_reg_mask(polarity << 6, 0xC0); |
| 920 | if (devices & VIA_DVP1) |
| 921 | via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60); |
| 922 | if (devices & VIA_LVDS1) |
| 923 | via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60); |
| 924 | if (devices & VIA_LVDS2) |
| 925 | via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60); |
| 926 | } |
| 927 | |
Florian Tobias Schandinat | 2a91839 | 2010-09-05 01:33:28 +0000 | [diff] [blame] | 928 | u32 via_parse_odev(char *input, char **end) |
| 929 | { |
| 930 | char *ptr = input; |
| 931 | u32 odev = 0; |
| 932 | bool next = true; |
| 933 | int i, len; |
| 934 | |
| 935 | while (next) { |
| 936 | next = false; |
| 937 | for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { |
| 938 | len = strlen(device_mapping[i].name); |
| 939 | if (!strncmp(ptr, device_mapping[i].name, len)) { |
| 940 | odev |= device_mapping[i].device; |
| 941 | ptr += len; |
| 942 | if (*ptr == ',') { |
| 943 | ptr++; |
| 944 | next = true; |
| 945 | } |
| 946 | } |
| 947 | } |
| 948 | } |
| 949 | |
| 950 | *end = ptr; |
| 951 | return odev; |
| 952 | } |
| 953 | |
| 954 | void via_odev_to_seq(struct seq_file *m, u32 odev) |
| 955 | { |
| 956 | int i, count = 0; |
| 957 | |
| 958 | for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { |
| 959 | if (odev & device_mapping[i].device) { |
| 960 | if (count > 0) |
| 961 | seq_putc(m, ','); |
| 962 | |
| 963 | seq_puts(m, device_mapping[i].name); |
| 964 | count++; |
| 965 | } |
| 966 | } |
| 967 | |
| 968 | seq_putc(m, '\n'); |
| 969 | } |
| 970 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 971 | static void load_fix_bit_crtc_reg(void) |
| 972 | { |
| 973 | /* always set to 1 */ |
| 974 | viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); |
| 975 | /* line compare should set all bits = 1 (extend modes) */ |
| 976 | viafb_write_reg(CR18, VIACR, 0xff); |
| 977 | /* line compare should set all bits = 1 (extend modes) */ |
| 978 | viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4); |
| 979 | /* line compare should set all bits = 1 (extend modes) */ |
| 980 | viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6); |
| 981 | /* line compare should set all bits = 1 (extend modes) */ |
| 982 | viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); |
| 983 | /* line compare should set all bits = 1 (extend modes) */ |
| 984 | viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); |
| 985 | /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */ |
| 986 | /* extend mode always set to e3h */ |
| 987 | viafb_write_reg(CR17, VIACR, 0xe3); |
| 988 | /* extend mode always set to 0h */ |
| 989 | viafb_write_reg(CR08, VIACR, 0x00); |
| 990 | /* extend mode always set to 0h */ |
| 991 | viafb_write_reg(CR14, VIACR, 0x00); |
| 992 | |
| 993 | /* If K8M800, enable Prefetch Mode. */ |
| 994 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) |
| 995 | || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890)) |
| 996 | viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3); |
| 997 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) |
| 998 | && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX)) |
| 999 | viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); |
| 1000 | |
| 1001 | } |
| 1002 | |
| 1003 | void viafb_load_reg(int timing_value, int viafb_load_reg_num, |
| 1004 | struct io_register *reg, |
| 1005 | int io_type) |
| 1006 | { |
| 1007 | int reg_mask; |
| 1008 | int bit_num = 0; |
| 1009 | int data; |
| 1010 | int i, j; |
| 1011 | int shift_next_reg; |
| 1012 | int start_index, end_index, cr_index; |
| 1013 | u16 get_bit; |
| 1014 | |
| 1015 | for (i = 0; i < viafb_load_reg_num; i++) { |
| 1016 | reg_mask = 0; |
| 1017 | data = 0; |
| 1018 | start_index = reg[i].start_bit; |
| 1019 | end_index = reg[i].end_bit; |
| 1020 | cr_index = reg[i].io_addr; |
| 1021 | |
| 1022 | shift_next_reg = bit_num; |
| 1023 | for (j = start_index; j <= end_index; j++) { |
| 1024 | /*if (bit_num==8) timing_value = timing_value >>8; */ |
| 1025 | reg_mask = reg_mask | (BIT0 << j); |
| 1026 | get_bit = (timing_value & (BIT0 << bit_num)); |
| 1027 | data = |
| 1028 | data | ((get_bit >> shift_next_reg) << start_index); |
| 1029 | bit_num++; |
| 1030 | } |
| 1031 | if (io_type == VIACR) |
| 1032 | viafb_write_reg_mask(cr_index, VIACR, data, reg_mask); |
| 1033 | else |
| 1034 | viafb_write_reg_mask(cr_index, VIASR, data, reg_mask); |
| 1035 | } |
| 1036 | |
| 1037 | } |
| 1038 | |
| 1039 | /* Write Registers */ |
| 1040 | void viafb_write_regx(struct io_reg RegTable[], int ItemNum) |
| 1041 | { |
| 1042 | int i; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1043 | |
| 1044 | /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */ |
| 1045 | |
Florian Tobias Schandinat | 384c304 | 2010-04-17 19:44:54 +0000 | [diff] [blame] | 1046 | for (i = 0; i < ItemNum; i++) |
| 1047 | via_write_reg_mask(RegTable[i].port, RegTable[i].index, |
| 1048 | RegTable[i].value, RegTable[i].mask); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1049 | } |
| 1050 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1051 | void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga) |
| 1052 | { |
| 1053 | int reg_value; |
| 1054 | int viafb_load_reg_num; |
| 1055 | struct io_register *reg = NULL; |
| 1056 | |
| 1057 | switch (set_iga) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1058 | case IGA1: |
| 1059 | reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte); |
| 1060 | viafb_load_reg_num = fetch_count_reg. |
| 1061 | iga1_fetch_count_reg.reg_num; |
| 1062 | reg = fetch_count_reg.iga1_fetch_count_reg.reg; |
| 1063 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
Florian Tobias Schandinat | 4bbac05 | 2010-03-10 15:21:36 -0800 | [diff] [blame] | 1064 | break; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1065 | case IGA2: |
| 1066 | reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte); |
| 1067 | viafb_load_reg_num = fetch_count_reg. |
| 1068 | iga2_fetch_count_reg.reg_num; |
| 1069 | reg = fetch_count_reg.iga2_fetch_count_reg.reg; |
| 1070 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); |
| 1071 | break; |
| 1072 | } |
| 1073 | |
| 1074 | } |
| 1075 | |
| 1076 | void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active) |
| 1077 | { |
| 1078 | int reg_value; |
| 1079 | int viafb_load_reg_num; |
| 1080 | struct io_register *reg = NULL; |
| 1081 | int iga1_fifo_max_depth = 0, iga1_fifo_threshold = |
| 1082 | 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0; |
| 1083 | int iga2_fifo_max_depth = 0, iga2_fifo_threshold = |
| 1084 | 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0; |
| 1085 | |
| 1086 | if (set_iga == IGA1) { |
| 1087 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { |
| 1088 | iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH; |
| 1089 | iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD; |
| 1090 | iga1_fifo_high_threshold = |
| 1091 | K800_IGA1_FIFO_HIGH_THRESHOLD; |
| 1092 | /* If resolution > 1280x1024, expire length = 64, else |
| 1093 | expire length = 128 */ |
| 1094 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1095 | iga1_display_queue_expire_num = 16; |
| 1096 | else |
| 1097 | iga1_display_queue_expire_num = |
| 1098 | K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1099 | |
| 1100 | } |
| 1101 | |
| 1102 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) { |
| 1103 | iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH; |
| 1104 | iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD; |
| 1105 | iga1_fifo_high_threshold = |
| 1106 | P880_IGA1_FIFO_HIGH_THRESHOLD; |
| 1107 | iga1_display_queue_expire_num = |
| 1108 | P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1109 | |
| 1110 | /* If resolution > 1280x1024, expire length = 64, else |
| 1111 | expire length = 128 */ |
| 1112 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1113 | iga1_display_queue_expire_num = 16; |
| 1114 | else |
| 1115 | iga1_display_queue_expire_num = |
| 1116 | P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1117 | } |
| 1118 | |
| 1119 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) { |
| 1120 | iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH; |
| 1121 | iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD; |
| 1122 | iga1_fifo_high_threshold = |
| 1123 | CN700_IGA1_FIFO_HIGH_THRESHOLD; |
| 1124 | |
| 1125 | /* If resolution > 1280x1024, expire length = 64, |
| 1126 | else expire length = 128 */ |
| 1127 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1128 | iga1_display_queue_expire_num = 16; |
| 1129 | else |
| 1130 | iga1_display_queue_expire_num = |
| 1131 | CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1132 | } |
| 1133 | |
| 1134 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { |
| 1135 | iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH; |
| 1136 | iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD; |
| 1137 | iga1_fifo_high_threshold = |
| 1138 | CX700_IGA1_FIFO_HIGH_THRESHOLD; |
| 1139 | iga1_display_queue_expire_num = |
| 1140 | CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1141 | } |
| 1142 | |
| 1143 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) { |
| 1144 | iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH; |
| 1145 | iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD; |
| 1146 | iga1_fifo_high_threshold = |
| 1147 | K8M890_IGA1_FIFO_HIGH_THRESHOLD; |
| 1148 | iga1_display_queue_expire_num = |
| 1149 | K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1150 | } |
| 1151 | |
| 1152 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) { |
| 1153 | iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH; |
| 1154 | iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD; |
| 1155 | iga1_fifo_high_threshold = |
| 1156 | P4M890_IGA1_FIFO_HIGH_THRESHOLD; |
| 1157 | iga1_display_queue_expire_num = |
| 1158 | P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1159 | } |
| 1160 | |
| 1161 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) { |
| 1162 | iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH; |
| 1163 | iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD; |
| 1164 | iga1_fifo_high_threshold = |
| 1165 | P4M900_IGA1_FIFO_HIGH_THRESHOLD; |
| 1166 | iga1_display_queue_expire_num = |
| 1167 | P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1168 | } |
| 1169 | |
| 1170 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) { |
| 1171 | iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH; |
| 1172 | iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD; |
| 1173 | iga1_fifo_high_threshold = |
| 1174 | VX800_IGA1_FIFO_HIGH_THRESHOLD; |
| 1175 | iga1_display_queue_expire_num = |
| 1176 | VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1177 | } |
| 1178 | |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 1179 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) { |
| 1180 | iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH; |
| 1181 | iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD; |
| 1182 | iga1_fifo_high_threshold = |
| 1183 | VX855_IGA1_FIFO_HIGH_THRESHOLD; |
| 1184 | iga1_display_queue_expire_num = |
| 1185 | VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1186 | } |
| 1187 | |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 1188 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) { |
| 1189 | iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH; |
| 1190 | iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD; |
| 1191 | iga1_fifo_high_threshold = |
| 1192 | VX900_IGA1_FIFO_HIGH_THRESHOLD; |
| 1193 | iga1_display_queue_expire_num = |
| 1194 | VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1195 | } |
| 1196 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1197 | /* Set Display FIFO Depath Select */ |
| 1198 | reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); |
| 1199 | viafb_load_reg_num = |
| 1200 | display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num; |
| 1201 | reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg; |
| 1202 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
| 1203 | |
| 1204 | /* Set Display FIFO Threshold Select */ |
| 1205 | reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold); |
| 1206 | viafb_load_reg_num = |
| 1207 | fifo_threshold_select_reg. |
| 1208 | iga1_fifo_threshold_select_reg.reg_num; |
| 1209 | reg = |
| 1210 | fifo_threshold_select_reg. |
| 1211 | iga1_fifo_threshold_select_reg.reg; |
| 1212 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
| 1213 | |
| 1214 | /* Set FIFO High Threshold Select */ |
| 1215 | reg_value = |
| 1216 | IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold); |
| 1217 | viafb_load_reg_num = |
| 1218 | fifo_high_threshold_select_reg. |
| 1219 | iga1_fifo_high_threshold_select_reg.reg_num; |
| 1220 | reg = |
| 1221 | fifo_high_threshold_select_reg. |
| 1222 | iga1_fifo_high_threshold_select_reg.reg; |
| 1223 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
| 1224 | |
| 1225 | /* Set Display Queue Expire Num */ |
| 1226 | reg_value = |
| 1227 | IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA |
| 1228 | (iga1_display_queue_expire_num); |
| 1229 | viafb_load_reg_num = |
| 1230 | display_queue_expire_num_reg. |
| 1231 | iga1_display_queue_expire_num_reg.reg_num; |
| 1232 | reg = |
| 1233 | display_queue_expire_num_reg. |
| 1234 | iga1_display_queue_expire_num_reg.reg; |
| 1235 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); |
| 1236 | |
| 1237 | } else { |
| 1238 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { |
| 1239 | iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH; |
| 1240 | iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD; |
| 1241 | iga2_fifo_high_threshold = |
| 1242 | K800_IGA2_FIFO_HIGH_THRESHOLD; |
| 1243 | |
| 1244 | /* If resolution > 1280x1024, expire length = 64, |
| 1245 | else expire length = 128 */ |
| 1246 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1247 | iga2_display_queue_expire_num = 16; |
| 1248 | else |
| 1249 | iga2_display_queue_expire_num = |
| 1250 | K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1251 | } |
| 1252 | |
| 1253 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) { |
| 1254 | iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH; |
| 1255 | iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD; |
| 1256 | iga2_fifo_high_threshold = |
| 1257 | P880_IGA2_FIFO_HIGH_THRESHOLD; |
| 1258 | |
| 1259 | /* If resolution > 1280x1024, expire length = 64, |
| 1260 | else expire length = 128 */ |
| 1261 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1262 | iga2_display_queue_expire_num = 16; |
| 1263 | else |
| 1264 | iga2_display_queue_expire_num = |
| 1265 | P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1266 | } |
| 1267 | |
| 1268 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) { |
| 1269 | iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH; |
| 1270 | iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD; |
| 1271 | iga2_fifo_high_threshold = |
| 1272 | CN700_IGA2_FIFO_HIGH_THRESHOLD; |
| 1273 | |
| 1274 | /* If resolution > 1280x1024, expire length = 64, |
| 1275 | else expire length = 128 */ |
| 1276 | if ((hor_active > 1280) && (ver_active > 1024)) |
| 1277 | iga2_display_queue_expire_num = 16; |
| 1278 | else |
| 1279 | iga2_display_queue_expire_num = |
| 1280 | CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1281 | } |
| 1282 | |
| 1283 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { |
| 1284 | iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH; |
| 1285 | iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD; |
| 1286 | iga2_fifo_high_threshold = |
| 1287 | CX700_IGA2_FIFO_HIGH_THRESHOLD; |
| 1288 | iga2_display_queue_expire_num = |
| 1289 | CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1290 | } |
| 1291 | |
| 1292 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) { |
| 1293 | iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH; |
| 1294 | iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD; |
| 1295 | iga2_fifo_high_threshold = |
| 1296 | K8M890_IGA2_FIFO_HIGH_THRESHOLD; |
| 1297 | iga2_display_queue_expire_num = |
| 1298 | K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1299 | } |
| 1300 | |
| 1301 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) { |
| 1302 | iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH; |
| 1303 | iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD; |
| 1304 | iga2_fifo_high_threshold = |
| 1305 | P4M890_IGA2_FIFO_HIGH_THRESHOLD; |
| 1306 | iga2_display_queue_expire_num = |
| 1307 | P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1308 | } |
| 1309 | |
| 1310 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) { |
| 1311 | iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH; |
| 1312 | iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD; |
| 1313 | iga2_fifo_high_threshold = |
| 1314 | P4M900_IGA2_FIFO_HIGH_THRESHOLD; |
| 1315 | iga2_display_queue_expire_num = |
| 1316 | P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1317 | } |
| 1318 | |
| 1319 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) { |
| 1320 | iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH; |
| 1321 | iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD; |
| 1322 | iga2_fifo_high_threshold = |
| 1323 | VX800_IGA2_FIFO_HIGH_THRESHOLD; |
| 1324 | iga2_display_queue_expire_num = |
| 1325 | VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1326 | } |
| 1327 | |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 1328 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) { |
| 1329 | iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH; |
| 1330 | iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD; |
| 1331 | iga2_fifo_high_threshold = |
| 1332 | VX855_IGA2_FIFO_HIGH_THRESHOLD; |
| 1333 | iga2_display_queue_expire_num = |
| 1334 | VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1335 | } |
| 1336 | |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 1337 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) { |
| 1338 | iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH; |
| 1339 | iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD; |
| 1340 | iga2_fifo_high_threshold = |
| 1341 | VX900_IGA2_FIFO_HIGH_THRESHOLD; |
| 1342 | iga2_display_queue_expire_num = |
| 1343 | VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; |
| 1344 | } |
| 1345 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1346 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { |
| 1347 | /* Set Display FIFO Depath Select */ |
| 1348 | reg_value = |
| 1349 | IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth) |
| 1350 | - 1; |
| 1351 | /* Patch LCD in IGA2 case */ |
| 1352 | viafb_load_reg_num = |
| 1353 | display_fifo_depth_reg. |
| 1354 | iga2_fifo_depth_select_reg.reg_num; |
| 1355 | reg = |
| 1356 | display_fifo_depth_reg. |
| 1357 | iga2_fifo_depth_select_reg.reg; |
| 1358 | viafb_load_reg(reg_value, |
| 1359 | viafb_load_reg_num, reg, VIACR); |
| 1360 | } else { |
| 1361 | |
| 1362 | /* Set Display FIFO Depath Select */ |
| 1363 | reg_value = |
| 1364 | IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth); |
| 1365 | viafb_load_reg_num = |
| 1366 | display_fifo_depth_reg. |
| 1367 | iga2_fifo_depth_select_reg.reg_num; |
| 1368 | reg = |
| 1369 | display_fifo_depth_reg. |
| 1370 | iga2_fifo_depth_select_reg.reg; |
| 1371 | viafb_load_reg(reg_value, |
| 1372 | viafb_load_reg_num, reg, VIACR); |
| 1373 | } |
| 1374 | |
| 1375 | /* Set Display FIFO Threshold Select */ |
| 1376 | reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold); |
| 1377 | viafb_load_reg_num = |
| 1378 | fifo_threshold_select_reg. |
| 1379 | iga2_fifo_threshold_select_reg.reg_num; |
| 1380 | reg = |
| 1381 | fifo_threshold_select_reg. |
| 1382 | iga2_fifo_threshold_select_reg.reg; |
| 1383 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); |
| 1384 | |
| 1385 | /* Set FIFO High Threshold Select */ |
| 1386 | reg_value = |
| 1387 | IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold); |
| 1388 | viafb_load_reg_num = |
| 1389 | fifo_high_threshold_select_reg. |
| 1390 | iga2_fifo_high_threshold_select_reg.reg_num; |
| 1391 | reg = |
| 1392 | fifo_high_threshold_select_reg. |
| 1393 | iga2_fifo_high_threshold_select_reg.reg; |
| 1394 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); |
| 1395 | |
| 1396 | /* Set Display Queue Expire Num */ |
| 1397 | reg_value = |
| 1398 | IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA |
| 1399 | (iga2_display_queue_expire_num); |
| 1400 | viafb_load_reg_num = |
| 1401 | display_queue_expire_num_reg. |
| 1402 | iga2_display_queue_expire_num_reg.reg_num; |
| 1403 | reg = |
| 1404 | display_queue_expire_num_reg. |
| 1405 | iga2_display_queue_expire_num_reg.reg; |
| 1406 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); |
| 1407 | |
| 1408 | } |
| 1409 | |
| 1410 | } |
| 1411 | |
Florian Tobias Schandinat | 1f84435 | 2010-07-11 00:57:34 +0000 | [diff] [blame] | 1412 | static u32 cle266_encode_pll(struct pll_config pll) |
| 1413 | { |
| 1414 | return (pll.multiplier << 8) |
| 1415 | | (pll.rshift << 6) |
| 1416 | | pll.divisor; |
| 1417 | } |
| 1418 | |
| 1419 | static u32 k800_encode_pll(struct pll_config pll) |
| 1420 | { |
| 1421 | return ((pll.divisor - 2) << 16) |
| 1422 | | (pll.rshift << 10) |
| 1423 | | (pll.multiplier - 2); |
| 1424 | } |
| 1425 | |
| 1426 | static u32 vx855_encode_pll(struct pll_config pll) |
| 1427 | { |
| 1428 | return (pll.divisor << 16) |
| 1429 | | (pll.rshift << 10) |
| 1430 | | pll.multiplier; |
| 1431 | } |
| 1432 | |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1433 | static inline void cle266_set_primary_pll_encoded(u32 data) |
| 1434 | { |
| 1435 | via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ |
| 1436 | via_write_reg(VIASR, 0x46, data & 0xFF); |
| 1437 | via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF); |
| 1438 | via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ |
| 1439 | } |
| 1440 | |
| 1441 | static inline void k800_set_primary_pll_encoded(u32 data) |
| 1442 | { |
| 1443 | via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */ |
| 1444 | via_write_reg(VIASR, 0x44, data & 0xFF); |
| 1445 | via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF); |
| 1446 | via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF); |
| 1447 | via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */ |
| 1448 | } |
| 1449 | |
| 1450 | static inline void cle266_set_secondary_pll_encoded(u32 data) |
| 1451 | { |
| 1452 | via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ |
| 1453 | via_write_reg(VIASR, 0x44, data & 0xFF); |
| 1454 | via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF); |
| 1455 | via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */ |
| 1456 | } |
| 1457 | |
| 1458 | static inline void k800_set_secondary_pll_encoded(u32 data) |
| 1459 | { |
| 1460 | via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */ |
| 1461 | via_write_reg(VIASR, 0x4A, data & 0xFF); |
| 1462 | via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF); |
| 1463 | via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF); |
| 1464 | via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */ |
| 1465 | } |
| 1466 | |
| 1467 | static void cle266_set_primary_pll(struct pll_config config) |
| 1468 | { |
| 1469 | cle266_set_primary_pll_encoded(cle266_encode_pll(config)); |
| 1470 | } |
| 1471 | |
| 1472 | static void k800_set_primary_pll(struct pll_config config) |
| 1473 | { |
| 1474 | k800_set_primary_pll_encoded(k800_encode_pll(config)); |
| 1475 | } |
| 1476 | |
| 1477 | static void vx855_set_primary_pll(struct pll_config config) |
| 1478 | { |
| 1479 | k800_set_primary_pll_encoded(vx855_encode_pll(config)); |
| 1480 | } |
| 1481 | |
| 1482 | static void cle266_set_secondary_pll(struct pll_config config) |
| 1483 | { |
| 1484 | cle266_set_secondary_pll_encoded(cle266_encode_pll(config)); |
| 1485 | } |
| 1486 | |
| 1487 | static void k800_set_secondary_pll(struct pll_config config) |
| 1488 | { |
| 1489 | k800_set_secondary_pll_encoded(k800_encode_pll(config)); |
| 1490 | } |
| 1491 | |
| 1492 | static void vx855_set_secondary_pll(struct pll_config config) |
| 1493 | { |
| 1494 | k800_set_secondary_pll_encoded(vx855_encode_pll(config)); |
| 1495 | } |
| 1496 | |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 1497 | static inline u32 get_pll_internal_frequency(u32 ref_freq, |
| 1498 | struct pll_config pll) |
| 1499 | { |
| 1500 | return ref_freq / pll.divisor * pll.multiplier; |
| 1501 | } |
| 1502 | |
| 1503 | static inline u32 get_pll_output_frequency(u32 ref_freq, struct pll_config pll) |
| 1504 | { |
| 1505 | return get_pll_internal_frequency(ref_freq, pll)>>pll.rshift; |
| 1506 | } |
| 1507 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 1508 | static struct pll_config get_pll_config(struct pll_limit *limits, int size, |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 1509 | int clk) |
| 1510 | { |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 1511 | struct pll_config cur, up, down, best = {0, 1, 0}; |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 1512 | const u32 f0 = 14318180; /* X1 frequency */ |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 1513 | int i, f; |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 1514 | |
Florian Tobias Schandinat | eb0536c | 2011-03-21 13:28:26 +0000 | [diff] [blame] | 1515 | for (i = 0; i < size; i++) { |
| 1516 | cur.rshift = limits[i].rshift; |
| 1517 | cur.divisor = limits[i].divisor; |
| 1518 | cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift); |
| 1519 | f = abs(get_pll_output_frequency(f0, cur) - clk); |
| 1520 | up = down = cur; |
| 1521 | up.multiplier++; |
| 1522 | down.multiplier--; |
| 1523 | if (abs(get_pll_output_frequency(f0, up) - clk) < f) |
| 1524 | cur = up; |
| 1525 | else if (abs(get_pll_output_frequency(f0, down) - clk) < f) |
| 1526 | cur = down; |
| 1527 | |
| 1528 | if (cur.multiplier < limits[i].multiplier_min) |
| 1529 | cur.multiplier = limits[i].multiplier_min; |
| 1530 | else if (cur.multiplier > limits[i].multiplier_max) |
| 1531 | cur.multiplier = limits[i].multiplier_max; |
| 1532 | |
| 1533 | f = abs(get_pll_output_frequency(f0, cur) - clk); |
| 1534 | if (f < abs(get_pll_output_frequency(f0, best) - clk)) |
| 1535 | best = cur; |
Florian Tobias Schandinat | e4fcaef | 2011-03-12 01:36:38 +0000 | [diff] [blame] | 1536 | } |
| 1537 | |
| 1538 | return best; |
| 1539 | } |
| 1540 | |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1541 | static struct pll_config get_best_pll_config(int clk) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1542 | { |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1543 | struct pll_config config; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1544 | |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1545 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 1546 | case UNICHROME_CLE266: |
| 1547 | case UNICHROME_K400: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1548 | config = get_pll_config(cle266_pll_limits, |
| 1549 | ARRAY_SIZE(cle266_pll_limits), clk); |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1550 | break; |
| 1551 | case UNICHROME_K800: |
| 1552 | case UNICHROME_PM800: |
| 1553 | case UNICHROME_CN700: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1554 | config = get_pll_config(k800_pll_limits, |
| 1555 | ARRAY_SIZE(k800_pll_limits), clk); |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1556 | break; |
| 1557 | case UNICHROME_CX700: |
| 1558 | case UNICHROME_CN750: |
| 1559 | case UNICHROME_K8M890: |
| 1560 | case UNICHROME_P4M890: |
| 1561 | case UNICHROME_P4M900: |
| 1562 | case UNICHROME_VX800: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1563 | config = get_pll_config(cx700_pll_limits, |
| 1564 | ARRAY_SIZE(cx700_pll_limits), clk); |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1565 | break; |
| 1566 | case UNICHROME_VX855: |
| 1567 | case UNICHROME_VX900: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1568 | config = get_pll_config(vx855_pll_limits, |
| 1569 | ARRAY_SIZE(vx855_pll_limits), clk); |
Florian Tobias Schandinat | 97597a3 | 2011-03-10 22:39:22 +0000 | [diff] [blame] | 1570 | break; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1571 | } |
| 1572 | |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1573 | return config; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1574 | } |
| 1575 | |
| 1576 | /* Set VCLK*/ |
Florian Tobias Schandinat | 1f84435 | 2010-07-11 00:57:34 +0000 | [diff] [blame] | 1577 | void viafb_set_vclock(u32 clk, int set_iga) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1578 | { |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1579 | struct pll_config config = get_best_pll_config(clk); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1580 | |
Florian Tobias Schandinat | 4bbac05 | 2010-03-10 15:21:36 -0800 | [diff] [blame] | 1581 | if (set_iga == IGA1) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1582 | /* Change D,N FOR VCLK */ |
| 1583 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 1584 | case UNICHROME_CLE266: |
| 1585 | case UNICHROME_K400: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1586 | cle266_set_primary_pll(config); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1587 | break; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1588 | case UNICHROME_K800: |
| 1589 | case UNICHROME_PM800: |
| 1590 | case UNICHROME_CN700: |
| 1591 | case UNICHROME_CX700: |
Florian Tobias Schandinat | 1f84435 | 2010-07-11 00:57:34 +0000 | [diff] [blame] | 1592 | case UNICHROME_CN750: |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1593 | case UNICHROME_K8M890: |
| 1594 | case UNICHROME_P4M890: |
| 1595 | case UNICHROME_P4M900: |
| 1596 | case UNICHROME_VX800: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1597 | k800_set_primary_pll(config); |
| 1598 | break; |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 1599 | case UNICHROME_VX855: |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 1600 | case UNICHROME_VX900: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1601 | vx855_set_primary_pll(config); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1602 | break; |
| 1603 | } |
| 1604 | } |
| 1605 | |
Florian Tobias Schandinat | 4bbac05 | 2010-03-10 15:21:36 -0800 | [diff] [blame] | 1606 | if (set_iga == IGA2) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1607 | /* Change D,N FOR LCK */ |
| 1608 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 1609 | case UNICHROME_CLE266: |
| 1610 | case UNICHROME_K400: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1611 | cle266_set_secondary_pll(config); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1612 | break; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1613 | case UNICHROME_K800: |
| 1614 | case UNICHROME_PM800: |
| 1615 | case UNICHROME_CN700: |
| 1616 | case UNICHROME_CX700: |
Florian Tobias Schandinat | 1f84435 | 2010-07-11 00:57:34 +0000 | [diff] [blame] | 1617 | case UNICHROME_CN750: |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1618 | case UNICHROME_K8M890: |
| 1619 | case UNICHROME_P4M890: |
| 1620 | case UNICHROME_P4M900: |
| 1621 | case UNICHROME_VX800: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1622 | k800_set_secondary_pll(config); |
| 1623 | break; |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 1624 | case UNICHROME_VX855: |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 1625 | case UNICHROME_VX900: |
Florian Tobias Schandinat | 0f77d4a | 2011-03-23 17:14:26 +0000 | [diff] [blame^] | 1626 | vx855_set_secondary_pll(config); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1627 | break; |
| 1628 | } |
| 1629 | } |
| 1630 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1631 | /* Fire! */ |
Florian Tobias Schandinat | 162fc8c | 2010-04-17 19:44:55 +0000 | [diff] [blame] | 1632 | via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */ |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1633 | } |
| 1634 | |
| 1635 | void viafb_load_crtc_timing(struct display_timing device_timing, |
| 1636 | int set_iga) |
| 1637 | { |
| 1638 | int i; |
| 1639 | int viafb_load_reg_num = 0; |
| 1640 | int reg_value = 0; |
| 1641 | struct io_register *reg = NULL; |
| 1642 | |
| 1643 | viafb_unlock_crt(); |
| 1644 | |
| 1645 | for (i = 0; i < 12; i++) { |
| 1646 | if (set_iga == IGA1) { |
| 1647 | switch (i) { |
| 1648 | case H_TOTAL_INDEX: |
| 1649 | reg_value = |
| 1650 | IGA1_HOR_TOTAL_FORMULA(device_timing. |
| 1651 | hor_total); |
| 1652 | viafb_load_reg_num = |
| 1653 | iga1_crtc_reg.hor_total.reg_num; |
| 1654 | reg = iga1_crtc_reg.hor_total.reg; |
| 1655 | break; |
| 1656 | case H_ADDR_INDEX: |
| 1657 | reg_value = |
| 1658 | IGA1_HOR_ADDR_FORMULA(device_timing. |
| 1659 | hor_addr); |
| 1660 | viafb_load_reg_num = |
| 1661 | iga1_crtc_reg.hor_addr.reg_num; |
| 1662 | reg = iga1_crtc_reg.hor_addr.reg; |
| 1663 | break; |
| 1664 | case H_BLANK_START_INDEX: |
| 1665 | reg_value = |
| 1666 | IGA1_HOR_BLANK_START_FORMULA |
| 1667 | (device_timing.hor_blank_start); |
| 1668 | viafb_load_reg_num = |
| 1669 | iga1_crtc_reg.hor_blank_start.reg_num; |
| 1670 | reg = iga1_crtc_reg.hor_blank_start.reg; |
| 1671 | break; |
| 1672 | case H_BLANK_END_INDEX: |
| 1673 | reg_value = |
| 1674 | IGA1_HOR_BLANK_END_FORMULA |
| 1675 | (device_timing.hor_blank_start, |
| 1676 | device_timing.hor_blank_end); |
| 1677 | viafb_load_reg_num = |
| 1678 | iga1_crtc_reg.hor_blank_end.reg_num; |
| 1679 | reg = iga1_crtc_reg.hor_blank_end.reg; |
| 1680 | break; |
| 1681 | case H_SYNC_START_INDEX: |
| 1682 | reg_value = |
| 1683 | IGA1_HOR_SYNC_START_FORMULA |
| 1684 | (device_timing.hor_sync_start); |
| 1685 | viafb_load_reg_num = |
| 1686 | iga1_crtc_reg.hor_sync_start.reg_num; |
| 1687 | reg = iga1_crtc_reg.hor_sync_start.reg; |
| 1688 | break; |
| 1689 | case H_SYNC_END_INDEX: |
| 1690 | reg_value = |
| 1691 | IGA1_HOR_SYNC_END_FORMULA |
| 1692 | (device_timing.hor_sync_start, |
| 1693 | device_timing.hor_sync_end); |
| 1694 | viafb_load_reg_num = |
| 1695 | iga1_crtc_reg.hor_sync_end.reg_num; |
| 1696 | reg = iga1_crtc_reg.hor_sync_end.reg; |
| 1697 | break; |
| 1698 | case V_TOTAL_INDEX: |
| 1699 | reg_value = |
| 1700 | IGA1_VER_TOTAL_FORMULA(device_timing. |
| 1701 | ver_total); |
| 1702 | viafb_load_reg_num = |
| 1703 | iga1_crtc_reg.ver_total.reg_num; |
| 1704 | reg = iga1_crtc_reg.ver_total.reg; |
| 1705 | break; |
| 1706 | case V_ADDR_INDEX: |
| 1707 | reg_value = |
| 1708 | IGA1_VER_ADDR_FORMULA(device_timing. |
| 1709 | ver_addr); |
| 1710 | viafb_load_reg_num = |
| 1711 | iga1_crtc_reg.ver_addr.reg_num; |
| 1712 | reg = iga1_crtc_reg.ver_addr.reg; |
| 1713 | break; |
| 1714 | case V_BLANK_START_INDEX: |
| 1715 | reg_value = |
| 1716 | IGA1_VER_BLANK_START_FORMULA |
| 1717 | (device_timing.ver_blank_start); |
| 1718 | viafb_load_reg_num = |
| 1719 | iga1_crtc_reg.ver_blank_start.reg_num; |
| 1720 | reg = iga1_crtc_reg.ver_blank_start.reg; |
| 1721 | break; |
| 1722 | case V_BLANK_END_INDEX: |
| 1723 | reg_value = |
| 1724 | IGA1_VER_BLANK_END_FORMULA |
| 1725 | (device_timing.ver_blank_start, |
| 1726 | device_timing.ver_blank_end); |
| 1727 | viafb_load_reg_num = |
| 1728 | iga1_crtc_reg.ver_blank_end.reg_num; |
| 1729 | reg = iga1_crtc_reg.ver_blank_end.reg; |
| 1730 | break; |
| 1731 | case V_SYNC_START_INDEX: |
| 1732 | reg_value = |
| 1733 | IGA1_VER_SYNC_START_FORMULA |
| 1734 | (device_timing.ver_sync_start); |
| 1735 | viafb_load_reg_num = |
| 1736 | iga1_crtc_reg.ver_sync_start.reg_num; |
| 1737 | reg = iga1_crtc_reg.ver_sync_start.reg; |
| 1738 | break; |
| 1739 | case V_SYNC_END_INDEX: |
| 1740 | reg_value = |
| 1741 | IGA1_VER_SYNC_END_FORMULA |
| 1742 | (device_timing.ver_sync_start, |
| 1743 | device_timing.ver_sync_end); |
| 1744 | viafb_load_reg_num = |
| 1745 | iga1_crtc_reg.ver_sync_end.reg_num; |
| 1746 | reg = iga1_crtc_reg.ver_sync_end.reg; |
| 1747 | break; |
| 1748 | |
| 1749 | } |
| 1750 | } |
| 1751 | |
| 1752 | if (set_iga == IGA2) { |
| 1753 | switch (i) { |
| 1754 | case H_TOTAL_INDEX: |
| 1755 | reg_value = |
| 1756 | IGA2_HOR_TOTAL_FORMULA(device_timing. |
| 1757 | hor_total); |
| 1758 | viafb_load_reg_num = |
| 1759 | iga2_crtc_reg.hor_total.reg_num; |
| 1760 | reg = iga2_crtc_reg.hor_total.reg; |
| 1761 | break; |
| 1762 | case H_ADDR_INDEX: |
| 1763 | reg_value = |
| 1764 | IGA2_HOR_ADDR_FORMULA(device_timing. |
| 1765 | hor_addr); |
| 1766 | viafb_load_reg_num = |
| 1767 | iga2_crtc_reg.hor_addr.reg_num; |
| 1768 | reg = iga2_crtc_reg.hor_addr.reg; |
| 1769 | break; |
| 1770 | case H_BLANK_START_INDEX: |
| 1771 | reg_value = |
| 1772 | IGA2_HOR_BLANK_START_FORMULA |
| 1773 | (device_timing.hor_blank_start); |
| 1774 | viafb_load_reg_num = |
| 1775 | iga2_crtc_reg.hor_blank_start.reg_num; |
| 1776 | reg = iga2_crtc_reg.hor_blank_start.reg; |
| 1777 | break; |
| 1778 | case H_BLANK_END_INDEX: |
| 1779 | reg_value = |
| 1780 | IGA2_HOR_BLANK_END_FORMULA |
| 1781 | (device_timing.hor_blank_start, |
| 1782 | device_timing.hor_blank_end); |
| 1783 | viafb_load_reg_num = |
| 1784 | iga2_crtc_reg.hor_blank_end.reg_num; |
| 1785 | reg = iga2_crtc_reg.hor_blank_end.reg; |
| 1786 | break; |
| 1787 | case H_SYNC_START_INDEX: |
| 1788 | reg_value = |
| 1789 | IGA2_HOR_SYNC_START_FORMULA |
| 1790 | (device_timing.hor_sync_start); |
| 1791 | if (UNICHROME_CN700 <= |
| 1792 | viaparinfo->chip_info->gfx_chip_name) |
| 1793 | viafb_load_reg_num = |
| 1794 | iga2_crtc_reg.hor_sync_start. |
| 1795 | reg_num; |
| 1796 | else |
| 1797 | viafb_load_reg_num = 3; |
| 1798 | reg = iga2_crtc_reg.hor_sync_start.reg; |
| 1799 | break; |
| 1800 | case H_SYNC_END_INDEX: |
| 1801 | reg_value = |
| 1802 | IGA2_HOR_SYNC_END_FORMULA |
| 1803 | (device_timing.hor_sync_start, |
| 1804 | device_timing.hor_sync_end); |
| 1805 | viafb_load_reg_num = |
| 1806 | iga2_crtc_reg.hor_sync_end.reg_num; |
| 1807 | reg = iga2_crtc_reg.hor_sync_end.reg; |
| 1808 | break; |
| 1809 | case V_TOTAL_INDEX: |
| 1810 | reg_value = |
| 1811 | IGA2_VER_TOTAL_FORMULA(device_timing. |
| 1812 | ver_total); |
| 1813 | viafb_load_reg_num = |
| 1814 | iga2_crtc_reg.ver_total.reg_num; |
| 1815 | reg = iga2_crtc_reg.ver_total.reg; |
| 1816 | break; |
| 1817 | case V_ADDR_INDEX: |
| 1818 | reg_value = |
| 1819 | IGA2_VER_ADDR_FORMULA(device_timing. |
| 1820 | ver_addr); |
| 1821 | viafb_load_reg_num = |
| 1822 | iga2_crtc_reg.ver_addr.reg_num; |
| 1823 | reg = iga2_crtc_reg.ver_addr.reg; |
| 1824 | break; |
| 1825 | case V_BLANK_START_INDEX: |
| 1826 | reg_value = |
| 1827 | IGA2_VER_BLANK_START_FORMULA |
| 1828 | (device_timing.ver_blank_start); |
| 1829 | viafb_load_reg_num = |
| 1830 | iga2_crtc_reg.ver_blank_start.reg_num; |
| 1831 | reg = iga2_crtc_reg.ver_blank_start.reg; |
| 1832 | break; |
| 1833 | case V_BLANK_END_INDEX: |
| 1834 | reg_value = |
| 1835 | IGA2_VER_BLANK_END_FORMULA |
| 1836 | (device_timing.ver_blank_start, |
| 1837 | device_timing.ver_blank_end); |
| 1838 | viafb_load_reg_num = |
| 1839 | iga2_crtc_reg.ver_blank_end.reg_num; |
| 1840 | reg = iga2_crtc_reg.ver_blank_end.reg; |
| 1841 | break; |
| 1842 | case V_SYNC_START_INDEX: |
| 1843 | reg_value = |
| 1844 | IGA2_VER_SYNC_START_FORMULA |
| 1845 | (device_timing.ver_sync_start); |
| 1846 | viafb_load_reg_num = |
| 1847 | iga2_crtc_reg.ver_sync_start.reg_num; |
| 1848 | reg = iga2_crtc_reg.ver_sync_start.reg; |
| 1849 | break; |
| 1850 | case V_SYNC_END_INDEX: |
| 1851 | reg_value = |
| 1852 | IGA2_VER_SYNC_END_FORMULA |
| 1853 | (device_timing.ver_sync_start, |
| 1854 | device_timing.ver_sync_end); |
| 1855 | viafb_load_reg_num = |
| 1856 | iga2_crtc_reg.ver_sync_end.reg_num; |
| 1857 | reg = iga2_crtc_reg.ver_sync_end.reg; |
| 1858 | break; |
| 1859 | |
| 1860 | } |
| 1861 | } |
| 1862 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); |
| 1863 | } |
| 1864 | |
| 1865 | viafb_lock_crt(); |
| 1866 | } |
| 1867 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1868 | void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 1869 | struct VideoModeTable *video_mode, int bpp_byte, int set_iga) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1870 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1871 | struct display_timing crt_reg; |
| 1872 | int i; |
| 1873 | int index = 0; |
| 1874 | int h_addr, v_addr; |
Florian Tobias Schandinat | 1606f87 | 2011-03-23 13:49:32 +0000 | [diff] [blame] | 1875 | u32 clock, refresh = viafb_refresh; |
Florian Tobias Schandinat | 726abbc | 2011-03-16 16:31:32 +0000 | [diff] [blame] | 1876 | |
| 1877 | if (viafb_SAMM_ON && set_iga == IGA2) |
| 1878 | refresh = viafb_refresh1; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1879 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1880 | for (i = 0; i < video_mode->mode_array; i++) { |
| 1881 | index = i; |
| 1882 | |
Florian Tobias Schandinat | 726abbc | 2011-03-16 16:31:32 +0000 | [diff] [blame] | 1883 | if (crt_table[i].refresh_rate == refresh) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1884 | break; |
| 1885 | } |
| 1886 | |
| 1887 | crt_reg = crt_table[index].crtc; |
| 1888 | |
| 1889 | /* Mode 640x480 has border, but LCD/DFP didn't have border. */ |
| 1890 | /* So we would delete border. */ |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 1891 | if ((viafb_LCD_ON | viafb_DVI_ON) |
| 1892 | && video_mode->crtc[0].crtc.hor_addr == 640 |
| 1893 | && video_mode->crtc[0].crtc.ver_addr == 480 |
Florian Tobias Schandinat | 726abbc | 2011-03-16 16:31:32 +0000 | [diff] [blame] | 1894 | && refresh == 60) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1895 | /* The border is 8 pixels. */ |
| 1896 | crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8; |
| 1897 | |
| 1898 | /* Blanking time should add left and right borders. */ |
| 1899 | crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16; |
| 1900 | } |
| 1901 | |
| 1902 | h_addr = crt_reg.hor_addr; |
| 1903 | v_addr = crt_reg.ver_addr; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1904 | if (set_iga == IGA1) { |
| 1905 | viafb_unlock_crt(); |
| 1906 | viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */ |
| 1907 | viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6); |
| 1908 | viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); |
| 1909 | } |
| 1910 | |
| 1911 | switch (set_iga) { |
| 1912 | case IGA1: |
| 1913 | viafb_load_crtc_timing(crt_reg, IGA1); |
| 1914 | break; |
| 1915 | case IGA2: |
| 1916 | viafb_load_crtc_timing(crt_reg, IGA2); |
| 1917 | break; |
| 1918 | } |
| 1919 | |
| 1920 | load_fix_bit_crtc_reg(); |
| 1921 | viafb_lock_crt(); |
| 1922 | viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1923 | viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga); |
| 1924 | |
| 1925 | /* load FIFO */ |
| 1926 | if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) |
| 1927 | && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) |
| 1928 | viafb_load_FIFO_reg(set_iga, h_addr, v_addr); |
| 1929 | |
Florian Tobias Schandinat | fd3cc69 | 2011-03-11 00:04:01 +0000 | [diff] [blame] | 1930 | clock = crt_reg.hor_total * crt_reg.ver_total |
| 1931 | * crt_table[index].refresh_rate; |
Florian Tobias Schandinat | 1606f87 | 2011-03-23 13:49:32 +0000 | [diff] [blame] | 1932 | viafb_set_vclock(clock, set_iga); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1933 | |
| 1934 | } |
| 1935 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 1936 | void __devinit viafb_init_chip_info(int chip_type) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1937 | { |
Jonathan Corbet | 24b4d82 | 2010-04-22 13:48:09 -0600 | [diff] [blame] | 1938 | init_gfx_chip_info(chip_type); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1939 | init_tmds_chip_info(); |
| 1940 | init_lvds_chip_info(); |
| 1941 | |
| 1942 | viaparinfo->crt_setting_info->iga_path = IGA1; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1943 | |
| 1944 | /*Set IGA path for each device */ |
| 1945 | viafb_set_iga_path(); |
| 1946 | |
| 1947 | viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1948 | viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode; |
| 1949 | viaparinfo->lvds_setting_info2->display_method = |
| 1950 | viaparinfo->lvds_setting_info->display_method; |
| 1951 | viaparinfo->lvds_setting_info2->lcd_mode = |
| 1952 | viaparinfo->lvds_setting_info->lcd_mode; |
| 1953 | } |
| 1954 | |
Florian Tobias Schandinat | 726abbc | 2011-03-16 16:31:32 +0000 | [diff] [blame] | 1955 | void viafb_update_device_setting(int hres, int vres, int bpp, int flag) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1956 | { |
| 1957 | if (flag == 0) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1958 | viaparinfo->tmds_setting_info->h_active = hres; |
| 1959 | viaparinfo->tmds_setting_info->v_active = vres; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1960 | |
| 1961 | viaparinfo->lvds_setting_info->h_active = hres; |
| 1962 | viaparinfo->lvds_setting_info->v_active = vres; |
| 1963 | viaparinfo->lvds_setting_info->bpp = bpp; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1964 | viaparinfo->lvds_setting_info2->h_active = hres; |
| 1965 | viaparinfo->lvds_setting_info2->v_active = vres; |
| 1966 | viaparinfo->lvds_setting_info2->bpp = bpp; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1967 | } else { |
| 1968 | |
| 1969 | if (viaparinfo->tmds_setting_info->iga_path == IGA2) { |
| 1970 | viaparinfo->tmds_setting_info->h_active = hres; |
| 1971 | viaparinfo->tmds_setting_info->v_active = vres; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1972 | } |
| 1973 | |
| 1974 | if (viaparinfo->lvds_setting_info->iga_path == IGA2) { |
| 1975 | viaparinfo->lvds_setting_info->h_active = hres; |
| 1976 | viaparinfo->lvds_setting_info->v_active = vres; |
| 1977 | viaparinfo->lvds_setting_info->bpp = bpp; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1978 | } |
| 1979 | if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) { |
| 1980 | viaparinfo->lvds_setting_info2->h_active = hres; |
| 1981 | viaparinfo->lvds_setting_info2->v_active = vres; |
| 1982 | viaparinfo->lvds_setting_info2->bpp = bpp; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1983 | } |
| 1984 | } |
| 1985 | } |
| 1986 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 1987 | static void __devinit init_gfx_chip_info(int chip_type) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1988 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1989 | u8 tmp; |
| 1990 | |
Jonathan Corbet | 24b4d82 | 2010-04-22 13:48:09 -0600 | [diff] [blame] | 1991 | viaparinfo->chip_info->gfx_chip_name = chip_type; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 1992 | |
| 1993 | /* Check revision of CLE266 Chip */ |
| 1994 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { |
| 1995 | /* CR4F only define in CLE266.CX chip */ |
| 1996 | tmp = viafb_read_reg(VIACR, CR4F); |
| 1997 | viafb_write_reg(CR4F, VIACR, 0x55); |
| 1998 | if (viafb_read_reg(VIACR, CR4F) != 0x55) |
| 1999 | viaparinfo->chip_info->gfx_chip_revision = |
| 2000 | CLE266_REVISION_AX; |
| 2001 | else |
| 2002 | viaparinfo->chip_info->gfx_chip_revision = |
| 2003 | CLE266_REVISION_CX; |
| 2004 | /* restore orignal CR4F value */ |
| 2005 | viafb_write_reg(CR4F, VIACR, tmp); |
| 2006 | } |
| 2007 | |
| 2008 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { |
| 2009 | tmp = viafb_read_reg(VIASR, SR43); |
| 2010 | DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp); |
| 2011 | if (tmp & 0x02) { |
| 2012 | viaparinfo->chip_info->gfx_chip_revision = |
| 2013 | CX700_REVISION_700M2; |
| 2014 | } else if (tmp & 0x40) { |
| 2015 | viaparinfo->chip_info->gfx_chip_revision = |
| 2016 | CX700_REVISION_700M; |
| 2017 | } else { |
| 2018 | viaparinfo->chip_info->gfx_chip_revision = |
| 2019 | CX700_REVISION_700; |
| 2020 | } |
| 2021 | } |
Harald Welte | 107ea34 | 2009-05-20 01:36:03 +0800 | [diff] [blame] | 2022 | |
| 2023 | /* Determine which 2D engine we have */ |
| 2024 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 2025 | case UNICHROME_VX800: |
| 2026 | case UNICHROME_VX855: |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 2027 | case UNICHROME_VX900: |
Harald Welte | 107ea34 | 2009-05-20 01:36:03 +0800 | [diff] [blame] | 2028 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1; |
| 2029 | break; |
| 2030 | case UNICHROME_K8M890: |
| 2031 | case UNICHROME_P4M900: |
| 2032 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5; |
| 2033 | break; |
| 2034 | default: |
| 2035 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2; |
| 2036 | break; |
| 2037 | } |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2038 | } |
| 2039 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 2040 | static void __devinit init_tmds_chip_info(void) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2041 | { |
| 2042 | viafb_tmds_trasmitter_identify(); |
| 2043 | |
| 2044 | if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info. |
| 2045 | output_interface) { |
| 2046 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 2047 | case UNICHROME_CX700: |
| 2048 | { |
| 2049 | /* we should check support by hardware layout.*/ |
| 2050 | if ((viafb_display_hardware_layout == |
| 2051 | HW_LAYOUT_DVI_ONLY) |
| 2052 | || (viafb_display_hardware_layout == |
| 2053 | HW_LAYOUT_LCD_DVI)) { |
| 2054 | viaparinfo->chip_info->tmds_chip_info. |
| 2055 | output_interface = INTERFACE_TMDS; |
| 2056 | } else { |
| 2057 | viaparinfo->chip_info->tmds_chip_info. |
| 2058 | output_interface = |
| 2059 | INTERFACE_NONE; |
| 2060 | } |
| 2061 | break; |
| 2062 | } |
| 2063 | case UNICHROME_K8M890: |
| 2064 | case UNICHROME_P4M900: |
| 2065 | case UNICHROME_P4M890: |
| 2066 | /* TMDS on PCIE, we set DFPLOW as default. */ |
| 2067 | viaparinfo->chip_info->tmds_chip_info.output_interface = |
| 2068 | INTERFACE_DFP_LOW; |
| 2069 | break; |
| 2070 | default: |
| 2071 | { |
| 2072 | /* set DVP1 default for DVI */ |
| 2073 | viaparinfo->chip_info->tmds_chip_info |
| 2074 | .output_interface = INTERFACE_DVP1; |
| 2075 | } |
| 2076 | } |
| 2077 | } |
| 2078 | |
| 2079 | DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n", |
| 2080 | viaparinfo->chip_info->tmds_chip_info.tmds_chip_name); |
Florian Tobias Schandinat | c5f06f5 | 2010-03-10 15:21:30 -0800 | [diff] [blame] | 2081 | viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info, |
| 2082 | &viaparinfo->shared->tmds_setting_info); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2083 | } |
| 2084 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 2085 | static void __devinit init_lvds_chip_info(void) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2086 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2087 | viafb_lvds_trasmitter_identify(); |
| 2088 | viafb_init_lcd_size(); |
| 2089 | viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info, |
| 2090 | viaparinfo->lvds_setting_info); |
| 2091 | if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) { |
| 2092 | viafb_init_lvds_output_interface(&viaparinfo->chip_info-> |
| 2093 | lvds_chip_info2, viaparinfo->lvds_setting_info2); |
| 2094 | } |
| 2095 | /*If CX700,two singel LCD, we need to reassign |
| 2096 | LCD interface to different LVDS port */ |
| 2097 | if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name) |
| 2098 | && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) { |
| 2099 | if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info. |
| 2100 | lvds_chip_name) && (INTEGRATED_LVDS == |
| 2101 | viaparinfo->chip_info-> |
| 2102 | lvds_chip_info2.lvds_chip_name)) { |
| 2103 | viaparinfo->chip_info->lvds_chip_info.output_interface = |
| 2104 | INTERFACE_LVDS0; |
| 2105 | viaparinfo->chip_info->lvds_chip_info2. |
| 2106 | output_interface = |
| 2107 | INTERFACE_LVDS1; |
| 2108 | } |
| 2109 | } |
| 2110 | |
| 2111 | DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n", |
| 2112 | viaparinfo->chip_info->lvds_chip_info.lvds_chip_name); |
| 2113 | DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n", |
| 2114 | viaparinfo->chip_info->lvds_chip_info.output_interface); |
| 2115 | DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n", |
| 2116 | viaparinfo->chip_info->lvds_chip_info.output_interface); |
| 2117 | } |
| 2118 | |
Florian Tobias Schandinat | f4ab2f7a | 2010-08-09 01:34:27 +0000 | [diff] [blame] | 2119 | void __devinit viafb_init_dac(int set_iga) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2120 | { |
| 2121 | int i; |
| 2122 | u8 tmp; |
| 2123 | |
| 2124 | if (set_iga == IGA1) { |
| 2125 | /* access Primary Display's LUT */ |
| 2126 | viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); |
| 2127 | /* turn off LCK */ |
| 2128 | viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); |
| 2129 | for (i = 0; i < 256; i++) { |
| 2130 | write_dac_reg(i, palLUT_table[i].red, |
| 2131 | palLUT_table[i].green, |
| 2132 | palLUT_table[i].blue); |
| 2133 | } |
| 2134 | /* turn on LCK */ |
| 2135 | viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); |
| 2136 | } else { |
| 2137 | tmp = viafb_read_reg(VIACR, CR6A); |
| 2138 | /* access Secondary Display's LUT */ |
| 2139 | viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); |
| 2140 | viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); |
| 2141 | for (i = 0; i < 256; i++) { |
| 2142 | write_dac_reg(i, palLUT_table[i].red, |
| 2143 | palLUT_table[i].green, |
| 2144 | palLUT_table[i].blue); |
| 2145 | } |
| 2146 | /* set IGA1 DAC for default */ |
| 2147 | viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); |
| 2148 | viafb_write_reg(CR6A, VIACR, tmp); |
| 2149 | } |
| 2150 | } |
| 2151 | |
| 2152 | static void device_screen_off(void) |
| 2153 | { |
| 2154 | /* turn off CRT screen (IGA1) */ |
| 2155 | viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); |
| 2156 | } |
| 2157 | |
| 2158 | static void device_screen_on(void) |
| 2159 | { |
| 2160 | /* turn on CRT screen (IGA1) */ |
| 2161 | viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); |
| 2162 | } |
| 2163 | |
| 2164 | static void set_display_channel(void) |
| 2165 | { |
| 2166 | /*If viafb_LCD2_ON, on cx700, internal lvds's information |
| 2167 | is keeped on lvds_setting_info2 */ |
| 2168 | if (viafb_LCD2_ON && |
| 2169 | viaparinfo->lvds_setting_info2->device_lcd_dualedge) { |
| 2170 | /* For dual channel LCD: */ |
| 2171 | /* Set to Dual LVDS channel. */ |
| 2172 | viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); |
| 2173 | } else if (viafb_LCD_ON && viafb_DVI_ON) { |
| 2174 | /* For LCD+DFP: */ |
| 2175 | /* Set to LVDS1 + TMDS channel. */ |
| 2176 | viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); |
| 2177 | } else if (viafb_DVI_ON) { |
| 2178 | /* Set to single TMDS channel. */ |
| 2179 | viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); |
| 2180 | } else if (viafb_LCD_ON) { |
| 2181 | if (viaparinfo->lvds_setting_info->device_lcd_dualedge) { |
| 2182 | /* For dual channel LCD: */ |
| 2183 | /* Set to Dual LVDS channel. */ |
| 2184 | viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); |
| 2185 | } else { |
| 2186 | /* Set to LVDS0 + LVDS1 channel. */ |
| 2187 | viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); |
| 2188 | } |
| 2189 | } |
| 2190 | } |
| 2191 | |
Florian Tobias Schandinat | 2e1abbd | 2010-09-19 01:20:19 +0000 | [diff] [blame] | 2192 | static u8 get_sync(struct fb_info *info) |
| 2193 | { |
| 2194 | u8 polarity = 0; |
| 2195 | |
| 2196 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) |
| 2197 | polarity |= VIA_HSYNC_NEGATIVE; |
| 2198 | if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) |
| 2199 | polarity |= VIA_VSYNC_NEGATIVE; |
| 2200 | return polarity; |
| 2201 | } |
| 2202 | |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2203 | int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, |
| 2204 | struct VideoModeTable *vmode_tbl1, int video_bpp1) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2205 | { |
| 2206 | int i, j; |
| 2207 | int port; |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 2208 | u32 devices = viaparinfo->shared->iga1_devices |
| 2209 | | viaparinfo->shared->iga2_devices; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2210 | u8 value, index, mask; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2211 | struct crt_mode_table *crt_timing; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2212 | struct crt_mode_table *crt_timing1 = NULL; |
| 2213 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2214 | device_screen_off(); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2215 | crt_timing = vmode_tbl->crtc; |
| 2216 | |
| 2217 | if (viafb_SAMM_ON == 1) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2218 | crt_timing1 = vmode_tbl1->crtc; |
| 2219 | } |
| 2220 | |
| 2221 | inb(VIAStatus); |
| 2222 | outb(0x00, VIAAR); |
| 2223 | |
| 2224 | /* Write Common Setting for Video Mode */ |
| 2225 | switch (viaparinfo->chip_info->gfx_chip_name) { |
| 2226 | case UNICHROME_CLE266: |
| 2227 | viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs); |
| 2228 | break; |
| 2229 | |
| 2230 | case UNICHROME_K400: |
| 2231 | viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs); |
| 2232 | break; |
| 2233 | |
| 2234 | case UNICHROME_K800: |
| 2235 | case UNICHROME_PM800: |
| 2236 | viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs); |
| 2237 | break; |
| 2238 | |
| 2239 | case UNICHROME_CN700: |
| 2240 | case UNICHROME_K8M890: |
| 2241 | case UNICHROME_P4M890: |
| 2242 | case UNICHROME_P4M900: |
| 2243 | viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs); |
| 2244 | break; |
| 2245 | |
| 2246 | case UNICHROME_CX700: |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2247 | case UNICHROME_VX800: |
Florian Tobias Schandinat | 0e3ca33 | 2009-09-22 16:47:10 -0700 | [diff] [blame] | 2248 | viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2249 | break; |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 2250 | |
| 2251 | case UNICHROME_VX855: |
Florian Tobias Schandinat | 51f4332 | 2010-10-24 04:02:14 +0000 | [diff] [blame] | 2252 | case UNICHROME_VX900: |
Harald Welte | 0306ab1 | 2009-09-22 16:47:35 -0700 | [diff] [blame] | 2253 | viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs); |
| 2254 | break; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2255 | } |
| 2256 | |
Florian Tobias Schandinat | bf5ea02 | 2011-01-05 10:36:05 +0000 | [diff] [blame] | 2257 | viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters)); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2258 | device_off(); |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 2259 | via_set_state(devices, VIA_STATE_OFF); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2260 | |
| 2261 | /* Fill VPIT Parameters */ |
| 2262 | /* Write Misc Register */ |
Florian Tobias Schandinat | 162fc8c | 2010-04-17 19:44:55 +0000 | [diff] [blame] | 2263 | outb(VPIT.Misc, VIA_MISC_REG_WRITE); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2264 | |
| 2265 | /* Write Sequencer */ |
Florian Tobias Schandinat | 384c304 | 2010-04-17 19:44:54 +0000 | [diff] [blame] | 2266 | for (i = 1; i <= StdSR; i++) |
| 2267 | via_write_reg(VIASR, i, VPIT.SR[i - 1]); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2268 | |
Florian Tobias Schandinat | 415559f | 2010-03-10 15:21:40 -0800 | [diff] [blame] | 2269 | viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2270 | |
| 2271 | /* Write CRTC */ |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2272 | viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2273 | |
| 2274 | /* Write Graphic Controller */ |
Florian Tobias Schandinat | 384c304 | 2010-04-17 19:44:54 +0000 | [diff] [blame] | 2275 | for (i = 0; i < StdGR; i++) |
| 2276 | via_write_reg(VIAGR, i, VPIT.GR[i]); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2277 | |
| 2278 | /* Write Attribute Controller */ |
| 2279 | for (i = 0; i < StdAR; i++) { |
| 2280 | inb(VIAStatus); |
| 2281 | outb(i, VIAAR); |
| 2282 | outb(VPIT.AR[i], VIAAR); |
| 2283 | } |
| 2284 | |
| 2285 | inb(VIAStatus); |
| 2286 | outb(0x20, VIAAR); |
| 2287 | |
| 2288 | /* Update Patch Register */ |
| 2289 | |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2290 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266 |
| 2291 | || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400) |
| 2292 | && vmode_tbl->crtc[0].crtc.hor_addr == 1024 |
| 2293 | && vmode_tbl->crtc[0].crtc.ver_addr == 768) { |
| 2294 | for (j = 0; j < res_patch_table[0].table_length; j++) { |
| 2295 | index = res_patch_table[0].io_reg_table[j].index; |
| 2296 | port = res_patch_table[0].io_reg_table[j].port; |
| 2297 | value = res_patch_table[0].io_reg_table[j].value; |
| 2298 | mask = res_patch_table[0].io_reg_table[j].mask; |
| 2299 | viafb_write_reg_mask(index, port, value, mask); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2300 | } |
| 2301 | } |
| 2302 | |
Florian Tobias Schandinat | 2749413 | 2010-04-17 19:44:52 +0000 | [diff] [blame] | 2303 | via_set_primary_pitch(viafbinfo->fix.line_length); |
| 2304 | via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length |
Florian Tobias Schandinat | 2d6e885 | 2009-09-22 16:47:29 -0700 | [diff] [blame] | 2305 | : viafbinfo->fix.line_length); |
Florian Tobias Schandinat | 2749413 | 2010-04-17 19:44:52 +0000 | [diff] [blame] | 2306 | via_set_primary_color_depth(viaparinfo->depth); |
| 2307 | via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth |
Florian Tobias Schandinat | daacccd | 2010-03-10 15:21:35 -0800 | [diff] [blame] | 2308 | : viaparinfo->depth); |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 2309 | via_set_source(viaparinfo->shared->iga1_devices, IGA1); |
| 2310 | via_set_source(viaparinfo->shared->iga2_devices, IGA2); |
| 2311 | if (viaparinfo->shared->iga2_devices) |
| 2312 | enable_second_display_channel(); |
| 2313 | else |
| 2314 | disable_second_display_channel(); |
| 2315 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2316 | /* Update Refresh Rate Setting */ |
| 2317 | |
| 2318 | /* Clear On Screen */ |
| 2319 | |
| 2320 | /* CRT set mode */ |
| 2321 | if (viafb_CRT_ON) { |
| 2322 | if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path == |
| 2323 | IGA2)) { |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2324 | viafb_fill_crtc_timing(crt_timing1, vmode_tbl1, |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2325 | video_bpp1 / 8, |
| 2326 | viaparinfo->crt_setting_info->iga_path); |
| 2327 | } else { |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2328 | viafb_fill_crtc_timing(crt_timing, vmode_tbl, |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2329 | video_bpp / 8, |
| 2330 | viaparinfo->crt_setting_info->iga_path); |
| 2331 | } |
| 2332 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2333 | /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode |
| 2334 | to 8 alignment (1368),there is several pixels (2 pixels) |
| 2335 | on right side of screen. */ |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2336 | if (vmode_tbl->crtc[0].crtc.hor_addr % 8) { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2337 | viafb_unlock_crt(); |
| 2338 | viafb_write_reg(CR02, VIACR, |
| 2339 | viafb_read_reg(VIACR, CR02) - 1); |
| 2340 | viafb_lock_crt(); |
| 2341 | } |
| 2342 | } |
| 2343 | |
| 2344 | if (viafb_DVI_ON) { |
| 2345 | if (viafb_SAMM_ON && |
| 2346 | (viaparinfo->tmds_setting_info->iga_path == IGA2)) { |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2347 | viafb_dvi_set_mode(viafb_get_mode |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2348 | (viaparinfo->tmds_setting_info->h_active, |
| 2349 | viaparinfo->tmds_setting_info-> |
Florian Tobias Schandinat | 5215944 | 2009-08-06 15:07:34 -0700 | [diff] [blame] | 2350 | v_active), |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2351 | video_bpp1, viaparinfo-> |
| 2352 | tmds_setting_info->iga_path); |
| 2353 | } else { |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2354 | viafb_dvi_set_mode(viafb_get_mode |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2355 | (viaparinfo->tmds_setting_info->h_active, |
| 2356 | viaparinfo-> |
Florian Tobias Schandinat | 5215944 | 2009-08-06 15:07:34 -0700 | [diff] [blame] | 2357 | tmds_setting_info->v_active), |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2358 | video_bpp, viaparinfo-> |
| 2359 | tmds_setting_info->iga_path); |
| 2360 | } |
| 2361 | } |
| 2362 | |
| 2363 | if (viafb_LCD_ON) { |
| 2364 | if (viafb_SAMM_ON && |
| 2365 | (viaparinfo->lvds_setting_info->iga_path == IGA2)) { |
| 2366 | viaparinfo->lvds_setting_info->bpp = video_bpp1; |
| 2367 | viafb_lcd_set_mode(crt_timing1, viaparinfo-> |
| 2368 | lvds_setting_info, |
| 2369 | &viaparinfo->chip_info->lvds_chip_info); |
| 2370 | } else { |
| 2371 | /* IGA1 doesn't have LCD scaling, so set it center. */ |
| 2372 | if (viaparinfo->lvds_setting_info->iga_path == IGA1) { |
| 2373 | viaparinfo->lvds_setting_info->display_method = |
| 2374 | LCD_CENTERING; |
| 2375 | } |
| 2376 | viaparinfo->lvds_setting_info->bpp = video_bpp; |
| 2377 | viafb_lcd_set_mode(crt_timing, viaparinfo-> |
| 2378 | lvds_setting_info, |
| 2379 | &viaparinfo->chip_info->lvds_chip_info); |
| 2380 | } |
| 2381 | } |
| 2382 | if (viafb_LCD2_ON) { |
| 2383 | if (viafb_SAMM_ON && |
| 2384 | (viaparinfo->lvds_setting_info2->iga_path == IGA2)) { |
| 2385 | viaparinfo->lvds_setting_info2->bpp = video_bpp1; |
| 2386 | viafb_lcd_set_mode(crt_timing1, viaparinfo-> |
| 2387 | lvds_setting_info2, |
| 2388 | &viaparinfo->chip_info->lvds_chip_info2); |
| 2389 | } else { |
| 2390 | /* IGA1 doesn't have LCD scaling, so set it center. */ |
| 2391 | if (viaparinfo->lvds_setting_info2->iga_path == IGA1) { |
| 2392 | viaparinfo->lvds_setting_info2->display_method = |
| 2393 | LCD_CENTERING; |
| 2394 | } |
| 2395 | viaparinfo->lvds_setting_info2->bpp = video_bpp; |
| 2396 | viafb_lcd_set_mode(crt_timing, viaparinfo-> |
| 2397 | lvds_setting_info2, |
| 2398 | &viaparinfo->chip_info->lvds_chip_info2); |
| 2399 | } |
| 2400 | } |
| 2401 | |
| 2402 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) |
| 2403 | && (viafb_LCD_ON || viafb_DVI_ON)) |
| 2404 | set_display_channel(); |
| 2405 | |
| 2406 | /* If set mode normally, save resolution information for hot-plug . */ |
| 2407 | if (!viafb_hotplug) { |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2408 | viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr; |
| 2409 | viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2410 | viafb_hotplug_bpp = video_bpp; |
| 2411 | viafb_hotplug_refresh = viafb_refresh; |
| 2412 | |
| 2413 | if (viafb_DVI_ON) |
| 2414 | viafb_DeviceStatus = DVI_Device; |
| 2415 | else |
| 2416 | viafb_DeviceStatus = CRT_Device; |
| 2417 | } |
| 2418 | device_on(); |
Florian Tobias Schandinat | 2e1abbd | 2010-09-19 01:20:19 +0000 | [diff] [blame] | 2419 | if (!viafb_dual_fb) |
| 2420 | via_set_sync_polarity(devices, get_sync(viafbinfo)); |
| 2421 | else { |
| 2422 | via_set_sync_polarity(viaparinfo->shared->iga1_devices, |
| 2423 | get_sync(viafbinfo)); |
| 2424 | via_set_sync_polarity(viaparinfo->shared->iga2_devices, |
| 2425 | get_sync(viafbinfo1)); |
| 2426 | } |
| 2427 | |
Florian Tobias Schandinat | 6f9422d | 2010-09-07 14:28:26 +0000 | [diff] [blame] | 2428 | via_set_state(devices, VIA_STATE_ON); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2429 | device_screen_on(); |
| 2430 | return 1; |
| 2431 | } |
| 2432 | |
| 2433 | int viafb_get_pixclock(int hres, int vres, int vmode_refresh) |
| 2434 | { |
| 2435 | int i; |
Florian Tobias Schandinat | f5b1c4b | 2011-03-09 22:13:32 +0000 | [diff] [blame] | 2436 | struct crt_mode_table *best; |
| 2437 | struct VideoModeTable *vmode = viafb_get_mode(hres, vres); |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2438 | |
Florian Tobias Schandinat | f5b1c4b | 2011-03-09 22:13:32 +0000 | [diff] [blame] | 2439 | if (!vmode) |
| 2440 | return RES_640X480_60HZ_PIXCLOCK; |
| 2441 | |
| 2442 | best = &vmode->crtc[0]; |
| 2443 | for (i = 1; i < vmode->mode_array; i++) { |
| 2444 | if (abs(vmode->crtc[i].refresh_rate - vmode_refresh) |
| 2445 | < abs(best->refresh_rate - vmode_refresh)) |
| 2446 | best = &vmode->crtc[i]; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2447 | } |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2448 | |
Florian Tobias Schandinat | f5b1c4b | 2011-03-09 22:13:32 +0000 | [diff] [blame] | 2449 | return 1000000000 / (best->crtc.hor_total * best->crtc.ver_total) |
| 2450 | * 1000 / best->refresh_rate; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2451 | } |
| 2452 | |
| 2453 | int viafb_get_refresh(int hres, int vres, u32 long_refresh) |
| 2454 | { |
Florian Tobias Schandinat | f5b1c4b | 2011-03-09 22:13:32 +0000 | [diff] [blame] | 2455 | int i; |
| 2456 | struct crt_mode_table *best; |
| 2457 | struct VideoModeTable *vmode = viafb_get_mode(hres, vres); |
| 2458 | |
| 2459 | if (!vmode) |
| 2460 | return 60; |
| 2461 | |
| 2462 | best = &vmode->crtc[0]; |
| 2463 | for (i = 1; i < vmode->mode_array; i++) { |
| 2464 | if (abs(vmode->crtc[i].refresh_rate - long_refresh) |
| 2465 | < abs(best->refresh_rate - long_refresh)) |
| 2466 | best = &vmode->crtc[i]; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2467 | } |
Florian Tobias Schandinat | f5b1c4b | 2011-03-09 22:13:32 +0000 | [diff] [blame] | 2468 | |
| 2469 | if (abs(best->refresh_rate - long_refresh) > 3) |
| 2470 | return 60; |
| 2471 | |
| 2472 | return best->refresh_rate; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2473 | } |
| 2474 | |
| 2475 | static void device_off(void) |
| 2476 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2477 | viafb_dvi_disable(); |
| 2478 | viafb_lcd_disable(); |
| 2479 | } |
| 2480 | |
| 2481 | static void device_on(void) |
| 2482 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2483 | if (viafb_DVI_ON == 1) |
| 2484 | viafb_dvi_enable(); |
| 2485 | if (viafb_LCD_ON == 1) |
| 2486 | viafb_lcd_enable(); |
| 2487 | } |
| 2488 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2489 | static void enable_second_display_channel(void) |
| 2490 | { |
| 2491 | /* to enable second display channel. */ |
| 2492 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); |
| 2493 | viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7); |
| 2494 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); |
| 2495 | } |
| 2496 | |
Florian Tobias Schandinat | bc68488 | 2010-08-11 00:37:58 +0000 | [diff] [blame] | 2497 | static void disable_second_display_channel(void) |
| 2498 | { |
| 2499 | /* to disable second display channel. */ |
| 2500 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); |
| 2501 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); |
| 2502 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); |
| 2503 | } |
| 2504 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2505 | void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ |
| 2506 | *p_gfx_dpa_setting) |
| 2507 | { |
| 2508 | switch (output_interface) { |
| 2509 | case INTERFACE_DVP0: |
| 2510 | { |
| 2511 | /* DVP0 Clock Polarity and Adjust: */ |
| 2512 | viafb_write_reg_mask(CR96, VIACR, |
| 2513 | p_gfx_dpa_setting->DVP0, 0x0F); |
| 2514 | |
| 2515 | /* DVP0 Clock and Data Pads Driving: */ |
| 2516 | viafb_write_reg_mask(SR1E, VIASR, |
| 2517 | p_gfx_dpa_setting->DVP0ClockDri_S, BIT2); |
| 2518 | viafb_write_reg_mask(SR2A, VIASR, |
| 2519 | p_gfx_dpa_setting->DVP0ClockDri_S1, |
| 2520 | BIT4); |
| 2521 | viafb_write_reg_mask(SR1B, VIASR, |
| 2522 | p_gfx_dpa_setting->DVP0DataDri_S, BIT1); |
| 2523 | viafb_write_reg_mask(SR2A, VIASR, |
| 2524 | p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); |
| 2525 | break; |
| 2526 | } |
| 2527 | |
| 2528 | case INTERFACE_DVP1: |
| 2529 | { |
| 2530 | /* DVP1 Clock Polarity and Adjust: */ |
| 2531 | viafb_write_reg_mask(CR9B, VIACR, |
| 2532 | p_gfx_dpa_setting->DVP1, 0x0F); |
| 2533 | |
| 2534 | /* DVP1 Clock and Data Pads Driving: */ |
| 2535 | viafb_write_reg_mask(SR65, VIASR, |
| 2536 | p_gfx_dpa_setting->DVP1Driving, 0x0F); |
| 2537 | break; |
| 2538 | } |
| 2539 | |
| 2540 | case INTERFACE_DFP_HIGH: |
| 2541 | { |
| 2542 | viafb_write_reg_mask(CR97, VIACR, |
| 2543 | p_gfx_dpa_setting->DFPHigh, 0x0F); |
| 2544 | break; |
| 2545 | } |
| 2546 | |
| 2547 | case INTERFACE_DFP_LOW: |
| 2548 | { |
| 2549 | viafb_write_reg_mask(CR99, VIACR, |
| 2550 | p_gfx_dpa_setting->DFPLow, 0x0F); |
| 2551 | break; |
| 2552 | } |
| 2553 | |
| 2554 | case INTERFACE_DFP: |
| 2555 | { |
| 2556 | viafb_write_reg_mask(CR97, VIACR, |
| 2557 | p_gfx_dpa_setting->DFPHigh, 0x0F); |
| 2558 | viafb_write_reg_mask(CR99, VIACR, |
| 2559 | p_gfx_dpa_setting->DFPLow, 0x0F); |
| 2560 | break; |
| 2561 | } |
| 2562 | } |
| 2563 | } |
| 2564 | |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2565 | /*According var's xres, yres fill var's other timing information*/ |
| 2566 | void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, |
Florian Tobias Schandinat | dd73d68 | 2010-03-10 15:21:28 -0800 | [diff] [blame] | 2567 | struct VideoModeTable *vmode_tbl) |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2568 | { |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2569 | struct crt_mode_table *crt_timing = NULL; |
| 2570 | struct display_timing crt_reg; |
| 2571 | int i = 0, index = 0; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2572 | crt_timing = vmode_tbl->crtc; |
| 2573 | for (i = 0; i < vmode_tbl->mode_array; i++) { |
| 2574 | index = i; |
| 2575 | if (crt_timing[i].refresh_rate == refresh) |
| 2576 | break; |
| 2577 | } |
| 2578 | |
| 2579 | crt_reg = crt_timing[index].crtc; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2580 | var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh); |
| 2581 | var->left_margin = |
| 2582 | crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end); |
| 2583 | var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr; |
| 2584 | var->hsync_len = crt_reg.hor_sync_end; |
| 2585 | var->upper_margin = |
| 2586 | crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end); |
| 2587 | var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr; |
| 2588 | var->vsync_len = crt_reg.ver_sync_end; |
Florian Tobias Schandinat | 2e1abbd | 2010-09-19 01:20:19 +0000 | [diff] [blame] | 2589 | var->sync = 0; |
| 2590 | if (crt_timing[index].h_sync_polarity == POSITIVE) |
| 2591 | var->sync |= FB_SYNC_HOR_HIGH_ACT; |
| 2592 | if (crt_timing[index].v_sync_polarity == POSITIVE) |
| 2593 | var->sync |= FB_SYNC_VERT_HIGH_ACT; |
Joseph Chan | d61e0bf | 2008-10-15 22:03:23 -0700 | [diff] [blame] | 2594 | } |