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Michael Wucc0b88c2007-08-31 01:15:25 -04001#ifndef ADM8211_H
2#define ADM8211_H
3
4/* ADM8211 Registers */
5
6/* CR32 (SIG) signature */
7#define ADM8211_SIG1 0x82011317 /* ADM8211A */
8#define ADM8211_SIG2 0x82111317 /* ADM8211B/ADM8211C */
9
10#define ADM8211_CSR_READ(r) ioread32(&priv->map->r)
11#define ADM8211_CSR_WRITE(r, val) iowrite32((val), &priv->map->r)
12
13/* CSR (Host Control and Status Registers) */
14struct adm8211_csr {
15 __le32 PAR; /* 0x00 CSR0 */
16 __le32 FRCTL; /* 0x04 CSR0A */
17 __le32 TDR; /* 0x08 CSR1 */
18 __le32 WTDP; /* 0x0C CSR1A */
19 __le32 RDR; /* 0x10 CSR2 */
20 __le32 WRDP; /* 0x14 CSR2A */
21 __le32 RDB; /* 0x18 CSR3 */
22 __le32 TDBH; /* 0x1C CSR3A */
23 __le32 TDBD; /* 0x20 CSR4 */
24 __le32 TDBP; /* 0x24 CSR4A */
25 __le32 STSR; /* 0x28 CSR5 */
26 __le32 TDBB; /* 0x2C CSR5A */
27 __le32 NAR; /* 0x30 CSR6 */
28 __le32 CSR6A; /* reserved */
29 __le32 IER; /* 0x38 CSR7 */
30 __le32 TKIPSCEP; /* 0x3C CSR7A */
31 __le32 LPC; /* 0x40 CSR8 */
32 __le32 CSR_TEST1; /* 0x44 CSR8A */
33 __le32 SPR; /* 0x48 CSR9 */
34 __le32 CSR_TEST0; /* 0x4C CSR9A */
35 __le32 WCSR; /* 0x50 CSR10 */
36 __le32 WPDR; /* 0x54 CSR10A */
37 __le32 GPTMR; /* 0x58 CSR11 */
38 __le32 GPIO; /* 0x5C CSR11A */
39 __le32 BBPCTL; /* 0x60 CSR12 */
40 __le32 SYNCTL; /* 0x64 CSR12A */
41 __le32 PLCPHD; /* 0x68 CSR13 */
42 __le32 MMIWA; /* 0x6C CSR13A */
43 __le32 MMIRD0; /* 0x70 CSR14 */
44 __le32 MMIRD1; /* 0x74 CSR14A */
45 __le32 TXBR; /* 0x78 CSR15 */
46 __le32 SYNDATA; /* 0x7C CSR15A */
47 __le32 ALCS; /* 0x80 CSR16 */
48 __le32 TOFS2; /* 0x84 CSR17 */
49 __le32 CMDR; /* 0x88 CSR18 */
50 __le32 PCIC; /* 0x8C CSR19 */
51 __le32 PMCSR; /* 0x90 CSR20 */
52 __le32 PAR0; /* 0x94 CSR21 */
53 __le32 PAR1; /* 0x98 CSR22 */
54 __le32 MAR0; /* 0x9C CSR23 */
55 __le32 MAR1; /* 0xA0 CSR24 */
56 __le32 ATIMDA0; /* 0xA4 CSR25 */
57 __le32 ABDA1; /* 0xA8 CSR26 */
58 __le32 BSSID0; /* 0xAC CSR27 */
59 __le32 TXLMT; /* 0xB0 CSR28 */
60 __le32 MIBCNT; /* 0xB4 CSR29 */
61 __le32 BCNT; /* 0xB8 CSR30 */
62 __le32 TSFTH; /* 0xBC CSR31 */
63 __le32 TSC; /* 0xC0 CSR32 */
64 __le32 SYNRF; /* 0xC4 CSR33 */
65 __le32 BPLI; /* 0xC8 CSR34 */
66 __le32 CAP0; /* 0xCC CSR35 */
67 __le32 CAP1; /* 0xD0 CSR36 */
68 __le32 RMD; /* 0xD4 CSR37 */
69 __le32 CFPP; /* 0xD8 CSR38 */
70 __le32 TOFS0; /* 0xDC CSR39 */
71 __le32 TOFS1; /* 0xE0 CSR40 */
72 __le32 IFST; /* 0xE4 CSR41 */
73 __le32 RSPT; /* 0xE8 CSR42 */
74 __le32 TSFTL; /* 0xEC CSR43 */
75 __le32 WEPCTL; /* 0xF0 CSR44 */
76 __le32 WESK; /* 0xF4 CSR45 */
77 __le32 WEPCNT; /* 0xF8 CSR46 */
78 __le32 MACTEST; /* 0xFC CSR47 */
79 __le32 FER; /* 0x100 */
80 __le32 FEMR; /* 0x104 */
81 __le32 FPSR; /* 0x108 */
82 __le32 FFER; /* 0x10C */
Eric Dumazetba2d3582010-06-02 18:10:09 +000083} __packed;
Michael Wucc0b88c2007-08-31 01:15:25 -040084
85/* CSR0 - PAR (PCI Address Register) */
86#define ADM8211_PAR_MWIE (1 << 24)
87#define ADM8211_PAR_MRLE (1 << 23)
88#define ADM8211_PAR_MRME (1 << 21)
89#define ADM8211_PAR_RAP ((1 << 18) | (1 << 17))
90#define ADM8211_PAR_CAL ((1 << 15) | (1 << 14))
91#define ADM8211_PAR_PBL 0x00003f00
92#define ADM8211_PAR_BLE (1 << 7)
93#define ADM8211_PAR_DSL 0x0000007c
94#define ADM8211_PAR_BAR (1 << 1)
95#define ADM8211_PAR_SWR (1 << 0)
96
97/* CSR1 - FRCTL (Frame Control Register) */
98#define ADM8211_FRCTL_PWRMGT (1 << 31)
99#define ADM8211_FRCTL_MAXPSP (1 << 27)
100#define ADM8211_FRCTL_DRVPRSP (1 << 26)
101#define ADM8211_FRCTL_DRVBCON (1 << 25)
102#define ADM8211_FRCTL_AID 0x0000ffff
103#define ADM8211_FRCTL_AID_ON 0x0000c000
104
105/* CSR5 - STSR (Status Register) */
106#define ADM8211_STSR_PCF (1 << 31)
107#define ADM8211_STSR_BCNTC (1 << 30)
108#define ADM8211_STSR_GPINT (1 << 29)
109#define ADM8211_STSR_LinkOff (1 << 28)
110#define ADM8211_STSR_ATIMTC (1 << 27)
111#define ADM8211_STSR_TSFTF (1 << 26)
112#define ADM8211_STSR_TSCZ (1 << 25)
113#define ADM8211_STSR_LinkOn (1 << 24)
114#define ADM8211_STSR_SQL (1 << 23)
115#define ADM8211_STSR_WEPTD (1 << 22)
116#define ADM8211_STSR_ATIME (1 << 21)
117#define ADM8211_STSR_TBTT (1 << 20)
118#define ADM8211_STSR_NISS (1 << 16)
119#define ADM8211_STSR_AISS (1 << 15)
120#define ADM8211_STSR_TEIS (1 << 14)
121#define ADM8211_STSR_FBE (1 << 13)
122#define ADM8211_STSR_REIS (1 << 12)
123#define ADM8211_STSR_GPTT (1 << 11)
124#define ADM8211_STSR_RPS (1 << 8)
125#define ADM8211_STSR_RDU (1 << 7)
126#define ADM8211_STSR_RCI (1 << 6)
127#define ADM8211_STSR_TUF (1 << 5)
128#define ADM8211_STSR_TRT (1 << 4)
129#define ADM8211_STSR_TLT (1 << 3)
130#define ADM8211_STSR_TDU (1 << 2)
131#define ADM8211_STSR_TPS (1 << 1)
132#define ADM8211_STSR_TCI (1 << 0)
133
134/* CSR6 - NAR (Network Access Register) */
135#define ADM8211_NAR_TXCF (1 << 31)
136#define ADM8211_NAR_HF (1 << 30)
137#define ADM8211_NAR_UTR (1 << 29)
138#define ADM8211_NAR_SQ (1 << 28)
139#define ADM8211_NAR_CFP (1 << 27)
140#define ADM8211_NAR_SF (1 << 21)
141#define ADM8211_NAR_TR ((1 << 15) | (1 << 14))
142#define ADM8211_NAR_ST (1 << 13)
143#define ADM8211_NAR_OM ((1 << 11) | (1 << 10))
144#define ADM8211_NAR_MM (1 << 7)
145#define ADM8211_NAR_PR (1 << 6)
146#define ADM8211_NAR_EA (1 << 5)
147#define ADM8211_NAR_PB (1 << 3)
148#define ADM8211_NAR_STPDMA (1 << 2)
149#define ADM8211_NAR_SR (1 << 1)
150#define ADM8211_NAR_CTX (1 << 0)
151
152#define ADM8211_IDLE() \
153do { \
154 if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST)) { \
155 ADM8211_CSR_WRITE(NAR, priv->nar & \
156 ~(ADM8211_NAR_SR | ADM8211_NAR_ST));\
157 ADM8211_CSR_READ(NAR); \
158 msleep(20); \
159 } \
160} while (0)
161
162#define ADM8211_IDLE_RX() \
163do { \
164 if (priv->nar & ADM8211_NAR_SR) { \
165 ADM8211_CSR_WRITE(NAR, priv->nar & ~ADM8211_NAR_SR); \
166 ADM8211_CSR_READ(NAR); \
167 mdelay(20); \
168 } \
169} while (0)
170
171#define ADM8211_RESTORE() \
172do { \
173 if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST)) \
174 ADM8211_CSR_WRITE(NAR, priv->nar); \
175} while (0)
176
177/* CSR7 - IER (Interrupt Enable Register) */
178#define ADM8211_IER_PCFIE (1 << 31)
179#define ADM8211_IER_BCNTCIE (1 << 30)
180#define ADM8211_IER_GPIE (1 << 29)
181#define ADM8211_IER_LinkOffIE (1 << 28)
182#define ADM8211_IER_ATIMTCIE (1 << 27)
183#define ADM8211_IER_TSFTFIE (1 << 26)
184#define ADM8211_IER_TSCZE (1 << 25)
185#define ADM8211_IER_LinkOnIE (1 << 24)
186#define ADM8211_IER_SQLIE (1 << 23)
187#define ADM8211_IER_WEPIE (1 << 22)
188#define ADM8211_IER_ATIMEIE (1 << 21)
189#define ADM8211_IER_TBTTIE (1 << 20)
190#define ADM8211_IER_NIE (1 << 16)
191#define ADM8211_IER_AIE (1 << 15)
192#define ADM8211_IER_TEIE (1 << 14)
193#define ADM8211_IER_FBEIE (1 << 13)
194#define ADM8211_IER_REIE (1 << 12)
195#define ADM8211_IER_GPTIE (1 << 11)
196#define ADM8211_IER_RSIE (1 << 8)
197#define ADM8211_IER_RUIE (1 << 7)
198#define ADM8211_IER_RCIE (1 << 6)
199#define ADM8211_IER_TUIE (1 << 5)
200#define ADM8211_IER_TRTIE (1 << 4)
201#define ADM8211_IER_TLTTIE (1 << 3)
202#define ADM8211_IER_TDUIE (1 << 2)
203#define ADM8211_IER_TPSIE (1 << 1)
204#define ADM8211_IER_TCIE (1 << 0)
205
206/* CSR9 - SPR (Serial Port Register) */
207#define ADM8211_SPR_SRS (1 << 11)
208#define ADM8211_SPR_SDO (1 << 3)
209#define ADM8211_SPR_SDI (1 << 2)
210#define ADM8211_SPR_SCLK (1 << 1)
211#define ADM8211_SPR_SCS (1 << 0)
212
213/* CSR9A - CSR_TEST0 */
214#define ADM8211_CSR_TEST0_EPNE (1 << 18)
215#define ADM8211_CSR_TEST0_EPSNM (1 << 17)
216#define ADM8211_CSR_TEST0_EPTYP (1 << 16)
217#define ADM8211_CSR_TEST0_EPRLD (1 << 15)
218
219/* CSR10 - WCSR (Wake-up Control/Status Register) */
220#define ADM8211_WCSR_CRCT (1 << 30)
221#define ADM8211_WCSR_TSFTWE (1 << 20)
222#define ADM8211_WCSR_TIMWE (1 << 19)
223#define ADM8211_WCSR_ATIMWE (1 << 18)
224#define ADM8211_WCSR_KEYWE (1 << 17)
225#define ADM8211_WCSR_MPRE (1 << 9)
226#define ADM8211_WCSR_LSOE (1 << 8)
227#define ADM8211_WCSR_KEYUP (1 << 6)
228#define ADM8211_WCSR_TSFTW (1 << 5)
229#define ADM8211_WCSR_TIMW (1 << 4)
230#define ADM8211_WCSR_ATIMW (1 << 3)
231#define ADM8211_WCSR_MPR (1 << 1)
232#define ADM8211_WCSR_LSO (1 << 0)
233
234/* CSR11A - GPIO */
235#define ADM8211_CSR_GPIO_EN5 (1 << 17)
236#define ADM8211_CSR_GPIO_EN4 (1 << 16)
237#define ADM8211_CSR_GPIO_EN3 (1 << 15)
238#define ADM8211_CSR_GPIO_EN2 (1 << 14)
239#define ADM8211_CSR_GPIO_EN1 (1 << 13)
240#define ADM8211_CSR_GPIO_EN0 (1 << 12)
241#define ADM8211_CSR_GPIO_O5 (1 << 11)
242#define ADM8211_CSR_GPIO_O4 (1 << 10)
243#define ADM8211_CSR_GPIO_O3 (1 << 9)
244#define ADM8211_CSR_GPIO_O2 (1 << 8)
245#define ADM8211_CSR_GPIO_O1 (1 << 7)
246#define ADM8211_CSR_GPIO_O0 (1 << 6)
247#define ADM8211_CSR_GPIO_IN 0x0000003f
248
249/* CSR12 - BBPCTL (BBP Control port) */
250#define ADM8211_BBPCTL_MMISEL (1 << 31)
251#define ADM8211_BBPCTL_SPICADD (0x7F << 24)
252#define ADM8211_BBPCTL_RF3000 (0x20 << 24)
253#define ADM8211_BBPCTL_TXCE (1 << 23)
254#define ADM8211_BBPCTL_RXCE (1 << 22)
255#define ADM8211_BBPCTL_CCAP (1 << 21)
256#define ADM8211_BBPCTL_TYPE 0x001c0000
257#define ADM8211_BBPCTL_WR (1 << 17)
258#define ADM8211_BBPCTL_RD (1 << 16)
259#define ADM8211_BBPCTL_ADDR 0x0000ff00
260#define ADM8211_BBPCTL_DATA 0x000000ff
261
262/* CSR12A - SYNCTL (Synthesizer Control port) */
263#define ADM8211_SYNCTL_WR (1 << 31)
264#define ADM8211_SYNCTL_RD (1 << 30)
265#define ADM8211_SYNCTL_CS0 (1 << 29)
266#define ADM8211_SYNCTL_CS1 (1 << 28)
267#define ADM8211_SYNCTL_CAL (1 << 27)
268#define ADM8211_SYNCTL_SELCAL (1 << 26)
Roel Kluin9e7ba242009-10-06 14:33:14 +0200269#define ADM8211_SYNCTL_RFtype ((1 << 24) | (1 << 23) | (1 << 22))
Michael Wucc0b88c2007-08-31 01:15:25 -0400270#define ADM8211_SYNCTL_RFMD (1 << 22)
271#define ADM8211_SYNCTL_GENERAL (0x7 << 22)
272/* SYNCTL 21:0 Data (Si4126: 18-bit data, 4-bit address) */
273
274/* CSR18 - CMDR (Command Register) */
275#define ADM8211_CMDR_PM (1 << 19)
276#define ADM8211_CMDR_APM (1 << 18)
277#define ADM8211_CMDR_RTE (1 << 4)
278#define ADM8211_CMDR_DRT ((1 << 3) | (1 << 2))
279#define ADM8211_CMDR_DRT_8DW (0x0 << 2)
280#define ADM8211_CMDR_DRT_16DW (0x1 << 2)
281#define ADM8211_CMDR_DRT_SF (0x2 << 2)
282
283/* CSR33 - SYNRF (SYNRF direct control) */
284#define ADM8211_SYNRF_SELSYN (1 << 31)
285#define ADM8211_SYNRF_SELRF (1 << 30)
286#define ADM8211_SYNRF_LERF (1 << 29)
287#define ADM8211_SYNRF_LEIF (1 << 28)
288#define ADM8211_SYNRF_SYNCLK (1 << 27)
289#define ADM8211_SYNRF_SYNDATA (1 << 26)
290#define ADM8211_SYNRF_PE1 (1 << 25)
291#define ADM8211_SYNRF_PE2 (1 << 24)
292#define ADM8211_SYNRF_PA_PE (1 << 23)
293#define ADM8211_SYNRF_TR_SW (1 << 22)
294#define ADM8211_SYNRF_TR_SWN (1 << 21)
295#define ADM8211_SYNRF_RADIO (1 << 20)
296#define ADM8211_SYNRF_CAL_EN (1 << 19)
297#define ADM8211_SYNRF_PHYRST (1 << 18)
298
299#define ADM8211_SYNRF_IF_SELECT_0 (1 << 31)
300#define ADM8211_SYNRF_IF_SELECT_1 ((1 << 31) | (1 << 28))
301#define ADM8211_SYNRF_WRITE_SYNDATA_0 (1 << 31)
302#define ADM8211_SYNRF_WRITE_SYNDATA_1 ((1 << 31) | (1 << 26))
303#define ADM8211_SYNRF_WRITE_CLOCK_0 (1 << 31)
304#define ADM8211_SYNRF_WRITE_CLOCK_1 ((1 << 31) | (1 << 27))
305
306/* CSR44 - WEPCTL (WEP Control) */
307#define ADM8211_WEPCTL_WEPENABLE (1 << 31)
308#define ADM8211_WEPCTL_WPAENABLE (1 << 30)
309#define ADM8211_WEPCTL_CURRENT_TABLE (1 << 29)
310#define ADM8211_WEPCTL_TABLE_WR (1 << 28)
311#define ADM8211_WEPCTL_TABLE_RD (1 << 27)
312#define ADM8211_WEPCTL_WEPRXBYP (1 << 25)
313#define ADM8211_WEPCTL_SEL_WEPTABLE (1 << 23)
314#define ADM8211_WEPCTL_ADDR (0x000001ff)
315
316/* CSR45 - WESK (Data Entry for Share/Individual Key) */
317#define ADM8211_WESK_DATA (0x0000ffff)
318
319/* FER (Function Event Register) */
320#define ADM8211_FER_INTR_EV_ENT (1 << 15)
321
322
323/* Si4126 RF Synthesizer - Control Registers */
324#define SI4126_MAIN_CONF 0
325#define SI4126_PHASE_DET_GAIN 1
326#define SI4126_POWERDOWN 2
327#define SI4126_RF1_N_DIV 3 /* only Si4136 */
328#define SI4126_RF2_N_DIV 4
329#define SI4126_IF_N_DIV 5
330#define SI4126_RF1_R_DIV 6 /* only Si4136 */
331#define SI4126_RF2_R_DIV 7
332#define SI4126_IF_R_DIV 8
333
334/* Main Configuration */
335#define SI4126_MAIN_XINDIV2 (1 << 6)
336#define SI4126_MAIN_IFDIV ((1 << 11) | (1 << 10))
337/* Powerdown */
338#define SI4126_POWERDOWN_PDIB (1 << 1)
339#define SI4126_POWERDOWN_PDRB (1 << 0)
340
341
342/* RF3000 BBP - Control Port Registers */
343/* 0x00 - reserved */
344#define RF3000_MODEM_CTRL__RX_STATUS 0x01
345#define RF3000_CCA_CTRL 0x02
346#define RF3000_DIVERSITY__RSSI 0x03
347#define RF3000_RX_SIGNAL_FIELD 0x04
348#define RF3000_RX_LEN_MSB 0x05
349#define RF3000_RX_LEN_LSB 0x06
350#define RF3000_RX_SERVICE_FIELD 0x07
351#define RF3000_TX_VAR_GAIN__TX_LEN_EXT 0x11
352#define RF3000_TX_LEN_MSB 0x12
353#define RF3000_TX_LEN_LSB 0x13
354#define RF3000_LOW_GAIN_CALIB 0x14
355#define RF3000_HIGH_GAIN_CALIB 0x15
356
357/* ADM8211 revisions */
358#define ADM8211_REV_AB 0x11
359#define ADM8211_REV_AF 0x15
360#define ADM8211_REV_BA 0x20
361#define ADM8211_REV_CA 0x30
362
363struct adm8211_desc {
364 __le32 status;
365 __le32 length;
366 __le32 buffer1;
367 __le32 buffer2;
368};
369
370#define RDES0_STATUS_OWN (1 << 31)
371#define RDES0_STATUS_ES (1 << 30)
372#define RDES0_STATUS_SQL (1 << 29)
373#define RDES0_STATUS_DE (1 << 28)
374#define RDES0_STATUS_FS (1 << 27)
375#define RDES0_STATUS_LS (1 << 26)
376#define RDES0_STATUS_PCF (1 << 25)
377#define RDES0_STATUS_SFDE (1 << 24)
378#define RDES0_STATUS_SIGE (1 << 23)
379#define RDES0_STATUS_CRC16E (1 << 22)
380#define RDES0_STATUS_RXTOE (1 << 21)
381#define RDES0_STATUS_CRC32E (1 << 20)
382#define RDES0_STATUS_ICVE (1 << 19)
383#define RDES0_STATUS_DA1 (1 << 17)
384#define RDES0_STATUS_DA0 (1 << 16)
385#define RDES0_STATUS_RXDR ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12))
386#define RDES0_STATUS_FL (0x00000fff)
387
388#define RDES1_CONTROL_RER (1 << 25)
389#define RDES1_CONTROL_RCH (1 << 24)
390#define RDES1_CONTROL_RBS2 (0x00fff000)
391#define RDES1_CONTROL_RBS1 (0x00000fff)
392
393#define RDES1_STATUS_RSSI (0x0000007f)
394
395
396#define TDES0_CONTROL_OWN (1 << 31)
397#define TDES0_CONTROL_DONE (1 << 30)
398#define TDES0_CONTROL_TXDR (0x0ff00000)
399
400#define TDES0_STATUS_OWN (1 << 31)
401#define TDES0_STATUS_DONE (1 << 30)
402#define TDES0_STATUS_ES (1 << 29)
403#define TDES0_STATUS_TLT (1 << 28)
404#define TDES0_STATUS_TRT (1 << 27)
405#define TDES0_STATUS_TUF (1 << 26)
406#define TDES0_STATUS_TRO (1 << 25)
407#define TDES0_STATUS_SOFBR (1 << 24)
408#define TDES0_STATUS_ACR (0x00000fff)
409
410#define TDES1_CONTROL_IC (1 << 31)
411#define TDES1_CONTROL_LS (1 << 30)
412#define TDES1_CONTROL_FS (1 << 29)
413#define TDES1_CONTROL_TER (1 << 25)
414#define TDES1_CONTROL_TCH (1 << 24)
415#define TDES1_CONTROL_RBS2 (0x00fff000)
416#define TDES1_CONTROL_RBS1 (0x00000fff)
417
418/* SRAM offsets */
Michael Wuf6ac0ad2007-09-24 18:10:25 -0400419#define ADM8211_SRAM(x) (priv->pdev->revision < ADM8211_REV_BA ? \
Michael Wucc0b88c2007-08-31 01:15:25 -0400420 ADM8211_SRAM_A_ ## x : ADM8211_SRAM_B_ ## x)
421
422#define ADM8211_SRAM_INDIV_KEY 0x0000
423#define ADM8211_SRAM_A_SHARE_KEY 0x0160
424#define ADM8211_SRAM_B_SHARE_KEY 0x00c0
425
426#define ADM8211_SRAM_A_SSID 0x0180
427#define ADM8211_SRAM_B_SSID 0x00d4
428#define ADM8211_SRAM_SSID ADM8211_SRAM(SSID)
429
430#define ADM8211_SRAM_A_SUPP_RATE 0x0191
431#define ADM8211_SRAM_B_SUPP_RATE 0x00dd
432#define ADM8211_SRAM_SUPP_RATE ADM8211_SRAM(SUPP_RATE)
433
434#define ADM8211_SRAM_A_SIZE 0x0200
435#define ADM8211_SRAM_B_SIZE 0x01c0
436#define ADM8211_SRAM_SIZE ADM8211_SRAM(SIZE)
437
438struct adm8211_rx_ring_info {
439 struct sk_buff *skb;
440 dma_addr_t mapping;
441};
442
443struct adm8211_tx_ring_info {
444 struct sk_buff *skb;
445 dma_addr_t mapping;
Michael Wucc0b88c2007-08-31 01:15:25 -0400446 size_t hdrlen;
447};
448
449#define PLCP_SIGNAL_1M 0x0a
450#define PLCP_SIGNAL_2M 0x14
451#define PLCP_SIGNAL_5M5 0x37
452#define PLCP_SIGNAL_11M 0x6e
453
454struct adm8211_tx_hdr {
455 u8 da[6];
456 u8 signal; /* PLCP signal / TX rate in 100 Kbps */
457 u8 service;
458 __le16 frame_body_size;
459 __le16 frame_control;
460 __le16 plcp_frag_tail_len;
461 __le16 plcp_frag_head_len;
462 __le16 dur_frag_tail;
463 __le16 dur_frag_head;
464 u8 addr4[6];
465
466#define ADM8211_TXHDRCTL_SHORT_PREAMBLE (1 << 0)
467#define ADM8211_TXHDRCTL_MORE_FRAG (1 << 1)
468#define ADM8211_TXHDRCTL_MORE_DATA (1 << 2)
469#define ADM8211_TXHDRCTL_FRAG_NO (1 << 3) /* ? */
470#define ADM8211_TXHDRCTL_ENABLE_RTS (1 << 4)
471#define ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE (1 << 5)
472#define ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER (1 << 15) /* ? */
473 __le16 header_control;
474 __le16 frag;
475 u8 reserved_0;
476 u8 retry_limit;
477
478 u32 wep2key0;
479 u32 wep2key1;
480 u32 wep2key2;
481 u32 wep2key3;
482
483 u8 keyid;
484 u8 entry_control; // huh??
485 u16 reserved_1;
486 u32 reserved_2;
Eric Dumazetba2d3582010-06-02 18:10:09 +0000487} __packed;
Michael Wucc0b88c2007-08-31 01:15:25 -0400488
489
490#define RX_COPY_BREAK 128
491#define RX_PKT_SIZE 2500
492
493struct adm8211_eeprom {
494 __le16 signature; /* 0x00 */
495 u8 major_version; /* 0x02 */
496 u8 minor_version; /* 0x03 */
497 u8 reserved_1[4]; /* 0x04 */
498 u8 hwaddr[6]; /* 0x08 */
499 u8 reserved_2[8]; /* 0x1E */
500 __le16 cr49; /* 0x16 */
501 u8 cr03; /* 0x18 */
502 u8 cr28; /* 0x19 */
503 u8 cr29; /* 0x1A */
504 u8 country_code; /* 0x1B */
505
506/* specific bbp types */
507#define ADM8211_BBP_RFMD3000 0x00
508#define ADM8211_BBP_RFMD3002 0x01
509#define ADM8211_BBP_ADM8011 0x04
510 u8 specific_bbptype; /* 0x1C */
511 u8 specific_rftype; /* 0x1D */
512 u8 reserved_3[2]; /* 0x1E */
513 __le16 device_id; /* 0x20 */
514 __le16 vendor_id; /* 0x22 */
515 __le16 subsystem_id; /* 0x24 */
516 __le16 subsystem_vendor_id; /* 0x26 */
517 u8 maxlat; /* 0x28 */
518 u8 mingnt; /* 0x29 */
519 __le16 cis_pointer_low; /* 0x2A */
520 __le16 cis_pointer_high; /* 0x2C */
521 __le16 csr18; /* 0x2E */
522 u8 reserved_4[16]; /* 0x30 */
523 u8 d1_pwrdara; /* 0x40 */
524 u8 d0_pwrdara; /* 0x41 */
525 u8 d3_pwrdara; /* 0x42 */
526 u8 d2_pwrdara; /* 0x43 */
527 u8 antenna_power[14]; /* 0x44 */
528 __le16 cis_wordcnt; /* 0x52 */
529 u8 tx_power[14]; /* 0x54 */
530 u8 lpf_cutoff[14]; /* 0x62 */
531 u8 lnags_threshold[14]; /* 0x70 */
532 __le16 checksum; /* 0x7E */
533 u8 cis_data[0]; /* 0x80, 384 bytes */
Eric Dumazetba2d3582010-06-02 18:10:09 +0000534} __packed;
Michael Wucc0b88c2007-08-31 01:15:25 -0400535
Michael Wucc0b88c2007-08-31 01:15:25 -0400536struct adm8211_priv {
537 struct pci_dev *pdev;
538 spinlock_t lock;
539 struct adm8211_csr __iomem *map;
540 struct adm8211_desc *rx_ring;
541 struct adm8211_desc *tx_ring;
542 dma_addr_t rx_ring_dma;
543 dma_addr_t tx_ring_dma;
544 struct adm8211_rx_ring_info *rx_buffers;
545 struct adm8211_tx_ring_info *tx_buffers;
546 unsigned int rx_ring_size, tx_ring_size;
547 unsigned int cur_tx, dirty_tx, cur_rx;
548
549 struct ieee80211_low_level_stats stats;
Johannes Berg8318d782008-01-24 19:38:38 +0100550 struct ieee80211_supported_band band;
551 struct ieee80211_channel channels[14];
Michael Wucc0b88c2007-08-31 01:15:25 -0400552 int mode;
553
554 int channel;
555 u8 bssid[ETH_ALEN];
Michael Wucc0b88c2007-08-31 01:15:25 -0400556
557 u8 soft_rx_crc;
558 u8 retry_limit;
559
560 u8 ant_power;
561 u8 tx_power;
562 u8 lpf_cutoff;
563 u8 lnags_threshold;
564 struct adm8211_eeprom *eeprom;
565 size_t eeprom_len;
566
Michael Wucc0b88c2007-08-31 01:15:25 -0400567 u32 nar;
568
569#define ADM8211_TYPE_INTERSIL 0x00
570#define ADM8211_TYPE_RFMD 0x01
571#define ADM8211_TYPE_MARVEL 0x02
572#define ADM8211_TYPE_AIROHA 0x03
573#define ADM8211_TYPE_ADMTEK 0x05
574 unsigned int rf_type:3;
575 unsigned int bbp_type:3;
576
577 u8 specific_bbptype;
578 enum {
579 ADM8211_RFMD2948 = 0x0,
580 ADM8211_RFMD2958 = 0x1,
581 ADM8211_RFMD2958_RF3000_CONTROL_POWER = 0x2,
582 ADM8211_MAX2820 = 0x8,
583 ADM8211_AL2210L = 0xC, /* Airoha */
584 } transceiver_type;
585};
586
Johannes Berg8318d782008-01-24 19:38:38 +0100587struct ieee80211_chan_range {
588 u8 min;
589 u8 max;
590};
591
Michael Wucc0b88c2007-08-31 01:15:25 -0400592static const struct ieee80211_chan_range cranges[] = {
593 {1, 11}, /* FCC */
594 {1, 11}, /* IC */
595 {1, 13}, /* ETSI */
596 {10, 11}, /* SPAIN */
597 {10, 13}, /* FRANCE */
598 {14, 14}, /* MMK */
599 {1, 14}, /* MMK2 */
600};
601
602#endif /* ADM8211_H */