Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ahci.c - AHCI SATA support |
| 3 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 8 | * Copyright 2004-2005 Red Hat, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; see the file COPYING. If not, write to |
| 23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | * |
| 25 | * |
| 26 | * libata documentation is available via 'make {ps|pdf}docs', |
| 27 | * as Documentation/DocBook/libata.* |
| 28 | * |
| 29 | * AHCI hardware documentation: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/blkdev.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/interrupt.h> |
domen@coderock.org | 87507cf | 2005-04-08 09:53:06 +0200 | [diff] [blame] | 42 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 43 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 45 | #include <scsi/scsi_cmnd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #include <linux/libata.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | |
| 48 | #define DRV_NAME "ahci" |
Jeff Garzik | cb48cab | 2007-02-26 06:04:24 -0500 | [diff] [blame] | 49 | #define DRV_VERSION "2.1" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
| 51 | |
| 52 | enum { |
| 53 | AHCI_PCI_BAR = 5, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 54 | AHCI_MAX_PORTS = 32, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
| 56 | AHCI_DMA_BOUNDARY = 0xffffffff, |
| 57 | AHCI_USE_CLUSTERING = 0, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 58 | AHCI_MAX_CMDS = 32, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 59 | AHCI_CMD_SZ = 32, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 60 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | AHCI_RX_FIS_SZ = 256, |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 62 | AHCI_CMD_TBL_CDB = 0x40, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 63 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
| 64 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
| 65 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
| 66 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | AHCI_RX_FIS_SZ, |
| 68 | AHCI_IRQ_ON_SG = (1 << 31), |
| 69 | AHCI_CMD_ATAPI = (1 << 5), |
| 70 | AHCI_CMD_WRITE = (1 << 6), |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 71 | AHCI_CMD_PREFETCH = (1 << 7), |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 72 | AHCI_CMD_RESET = (1 << 8), |
| 73 | AHCI_CMD_CLR_BUSY = (1 << 10), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
| 75 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 76 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | |
| 79 | board_ahci = 0, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 80 | board_ahci_pi = 1, |
| 81 | board_ahci_vt8251 = 2, |
| 82 | board_ahci_ign_iferr = 3, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 83 | board_ahci_sb600 = 4, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | |
| 85 | /* global controller registers */ |
| 86 | HOST_CAP = 0x00, /* host capabilities */ |
| 87 | HOST_CTL = 0x04, /* global host control */ |
| 88 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
| 89 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
| 90 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
| 91 | |
| 92 | /* HOST_CTL bits */ |
| 93 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
| 94 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
| 95 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
| 96 | |
| 97 | /* HOST_CAP bits */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 98 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 99 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 100 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
Tejun Heo | 979db80 | 2006-05-15 21:03:52 +0900 | [diff] [blame] | 101 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 102 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
| 104 | /* registers for each SATA port */ |
| 105 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
| 106 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
| 107 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
| 108 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
| 109 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
| 110 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
| 111 | PORT_CMD = 0x18, /* port command */ |
| 112 | PORT_TFDATA = 0x20, /* taskfile data */ |
| 113 | PORT_SIG = 0x24, /* device TF signature */ |
| 114 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
| 115 | PORT_SCR = 0x28, /* SATA phy register block */ |
| 116 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
| 117 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
| 118 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
| 119 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
| 120 | |
| 121 | /* PORT_IRQ_{STAT,MASK} bits */ |
| 122 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
| 123 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
| 124 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
| 125 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
| 126 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
| 127 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
| 128 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
| 129 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
| 130 | |
| 131 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
| 132 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
| 133 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
| 134 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
| 135 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
| 136 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
| 137 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
| 138 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
| 139 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
| 140 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 141 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
| 142 | PORT_IRQ_IF_ERR | |
| 143 | PORT_IRQ_CONNECT | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 144 | PORT_IRQ_PHYRDY | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 145 | PORT_IRQ_UNK_FIS, |
| 146 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
| 147 | PORT_IRQ_TF_ERR | |
| 148 | PORT_IRQ_HBUS_DATA_ERR, |
| 149 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
| 150 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
| 151 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | |
| 153 | /* PORT_CMD bits */ |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 154 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
| 156 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
| 157 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 158 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
| 160 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
| 161 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
| 162 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 163 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
| 165 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
| 166 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 167 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 168 | /* ap->flags bits */ |
Tejun Heo | 4aeb0e3 | 2006-11-01 17:58:33 +0900 | [diff] [blame] | 169 | AHCI_FLAG_NO_NCQ = (1 << 24), |
| 170 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 171 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 172 | AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */ |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 173 | |
| 174 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 175 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
| 176 | ATA_FLAG_SKIP_D2H_BSY, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | }; |
| 178 | |
| 179 | struct ahci_cmd_hdr { |
| 180 | u32 opts; |
| 181 | u32 status; |
| 182 | u32 tbl_addr; |
| 183 | u32 tbl_addr_hi; |
| 184 | u32 reserved[4]; |
| 185 | }; |
| 186 | |
| 187 | struct ahci_sg { |
| 188 | u32 addr; |
| 189 | u32 addr_hi; |
| 190 | u32 reserved; |
| 191 | u32 flags_size; |
| 192 | }; |
| 193 | |
| 194 | struct ahci_host_priv { |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 195 | u32 cap; /* cap to use */ |
| 196 | u32 port_map; /* port map to use */ |
| 197 | u32 saved_cap; /* saved initial cap */ |
| 198 | u32 saved_port_map; /* saved initial port_map */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | struct ahci_port_priv { |
| 202 | struct ahci_cmd_hdr *cmd_slot; |
| 203 | dma_addr_t cmd_slot_dma; |
| 204 | void *cmd_tbl; |
| 205 | dma_addr_t cmd_tbl_dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | void *rx_fis; |
| 207 | dma_addr_t rx_fis_dma; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 208 | /* for NCQ spurious interrupt analysis */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 209 | unsigned int ncq_saw_d2h:1; |
| 210 | unsigned int ncq_saw_dmas:1; |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 211 | unsigned int ncq_saw_sdb:1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | }; |
| 213 | |
| 214 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); |
| 215 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); |
| 216 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 217 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | static void ahci_irq_clear(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | static int ahci_port_start(struct ata_port *ap); |
| 220 | static void ahci_port_stop(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
| 222 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
| 223 | static u8 ahci_check_status(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 224 | static void ahci_freeze(struct ata_port *ap); |
| 225 | static void ahci_thaw(struct ata_port *ap); |
| 226 | static void ahci_error_handler(struct ata_port *ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 227 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 228 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 229 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 230 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
| 231 | static int ahci_port_resume(struct ata_port *ap); |
| 232 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
| 233 | static int ahci_pci_device_resume(struct pci_dev *pdev); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 234 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 236 | static struct scsi_host_template ahci_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | .module = THIS_MODULE, |
| 238 | .name = DRV_NAME, |
| 239 | .ioctl = ata_scsi_ioctl, |
| 240 | .queuecommand = ata_scsi_queuecmd, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 241 | .change_queue_depth = ata_scsi_change_queue_depth, |
| 242 | .can_queue = AHCI_MAX_CMDS - 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | .this_id = ATA_SHT_THIS_ID, |
| 244 | .sg_tablesize = AHCI_MAX_SG, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 246 | .emulated = ATA_SHT_EMULATED, |
| 247 | .use_clustering = AHCI_USE_CLUSTERING, |
| 248 | .proc_name = DRV_NAME, |
| 249 | .dma_boundary = AHCI_DMA_BOUNDARY, |
| 250 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 251 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | .bios_param = ata_std_bios_param, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 253 | }; |
| 254 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 255 | static const struct ata_port_operations ahci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | .port_disable = ata_port_disable, |
| 257 | |
| 258 | .check_status = ahci_check_status, |
| 259 | .check_altstatus = ahci_check_status, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | .dev_select = ata_noop_dev_select, |
| 261 | |
| 262 | .tf_read = ahci_tf_read, |
| 263 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | .qc_prep = ahci_qc_prep, |
| 265 | .qc_issue = ahci_qc_issue, |
| 266 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 267 | .irq_clear = ahci_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 268 | .irq_on = ata_dummy_irq_on, |
| 269 | .irq_ack = ata_dummy_irq_ack, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 270 | |
| 271 | .scr_read = ahci_scr_read, |
| 272 | .scr_write = ahci_scr_write, |
| 273 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 274 | .freeze = ahci_freeze, |
| 275 | .thaw = ahci_thaw, |
| 276 | |
| 277 | .error_handler = ahci_error_handler, |
| 278 | .post_internal_cmd = ahci_post_internal_cmd, |
| 279 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 280 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 281 | .port_suspend = ahci_port_suspend, |
| 282 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 283 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 284 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 285 | .port_start = ahci_port_start, |
| 286 | .port_stop = ahci_port_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | }; |
| 288 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 289 | static const struct ata_port_operations ahci_vt8251_ops = { |
| 290 | .port_disable = ata_port_disable, |
| 291 | |
| 292 | .check_status = ahci_check_status, |
| 293 | .check_altstatus = ahci_check_status, |
| 294 | .dev_select = ata_noop_dev_select, |
| 295 | |
| 296 | .tf_read = ahci_tf_read, |
| 297 | |
| 298 | .qc_prep = ahci_qc_prep, |
| 299 | .qc_issue = ahci_qc_issue, |
| 300 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 301 | .irq_clear = ahci_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 302 | .irq_on = ata_dummy_irq_on, |
| 303 | .irq_ack = ata_dummy_irq_ack, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 304 | |
| 305 | .scr_read = ahci_scr_read, |
| 306 | .scr_write = ahci_scr_write, |
| 307 | |
| 308 | .freeze = ahci_freeze, |
| 309 | .thaw = ahci_thaw, |
| 310 | |
| 311 | .error_handler = ahci_vt8251_error_handler, |
| 312 | .post_internal_cmd = ahci_post_internal_cmd, |
| 313 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 314 | #ifdef CONFIG_PM |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 315 | .port_suspend = ahci_port_suspend, |
| 316 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 317 | #endif |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 318 | |
| 319 | .port_start = ahci_port_start, |
| 320 | .port_stop = ahci_port_stop, |
| 321 | }; |
| 322 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 323 | static const struct ata_port_info ahci_port_info[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 324 | /* board_ahci */ |
| 325 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 326 | .flags = AHCI_FLAG_COMMON, |
Brett Russ | 7da7931 | 2005-09-01 21:53:34 -0400 | [diff] [blame] | 327 | .pio_mask = 0x1f, /* pio0-4 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 329 | .port_ops = &ahci_ops, |
| 330 | }, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 331 | /* board_ahci_pi */ |
| 332 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 333 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 334 | .pio_mask = 0x1f, /* pio0-4 */ |
| 335 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 336 | .port_ops = &ahci_ops, |
| 337 | }, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 338 | /* board_ahci_vt8251 */ |
| 339 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 340 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME | |
| 341 | AHCI_FLAG_NO_NCQ, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 342 | .pio_mask = 0x1f, /* pio0-4 */ |
| 343 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 344 | .port_ops = &ahci_vt8251_ops, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 345 | }, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 346 | /* board_ahci_ign_iferr */ |
| 347 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 348 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 349 | .pio_mask = 0x1f, /* pio0-4 */ |
| 350 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 351 | .port_ops = &ahci_ops, |
| 352 | }, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 353 | /* board_ahci_sb600 */ |
| 354 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 355 | .flags = AHCI_FLAG_COMMON | |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 356 | AHCI_FLAG_IGN_SERR_INTERNAL, |
| 357 | .pio_mask = 0x1f, /* pio0-4 */ |
| 358 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 359 | .port_ops = &ahci_ops, |
| 360 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | }; |
| 362 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 363 | static const struct pci_device_id ahci_pci_tbl[] = { |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 364 | /* Intel */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 365 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
| 366 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ |
| 367 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ |
| 368 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ |
| 369 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ |
Tejun Heo | 82490c0 | 2007-01-23 15:13:39 +0900 | [diff] [blame] | 370 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 371 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
| 372 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ |
| 373 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ |
| 374 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 375 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */ |
| 376 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */ |
| 377 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */ |
| 378 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */ |
| 379 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */ |
| 380 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */ |
| 381 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */ |
| 382 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */ |
| 383 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */ |
| 384 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */ |
| 385 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */ |
| 386 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */ |
| 387 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */ |
Jason Gaston | 8af12cd | 2007-03-02 17:39:46 -0800 | [diff] [blame] | 388 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */ |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 389 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */ |
| 390 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */ |
| 391 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 392 | |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 393 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
| 394 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 395 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 396 | |
| 397 | /* ATI */ |
Conke Hu | c65ec1c | 2007-04-11 18:23:14 +0800 | [diff] [blame] | 398 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 399 | |
| 400 | /* VIA */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 401 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
Tejun Heo | bf33554 | 2007-04-11 17:27:14 +0900 | [diff] [blame] | 402 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 403 | |
| 404 | /* NVIDIA */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 405 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
| 406 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ |
| 407 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ |
| 408 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ |
Peer Chen | 6fbf5ba | 2006-12-20 14:18:00 -0500 | [diff] [blame] | 409 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
| 410 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ |
| 411 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ |
| 412 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ |
| 413 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ |
| 414 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ |
| 415 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ |
| 416 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ |
Peer Chen | 895663c | 2006-11-02 17:59:46 -0500 | [diff] [blame] | 417 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
| 418 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ |
| 419 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ |
| 420 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ |
| 421 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ |
| 422 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ |
| 423 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ |
| 424 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 425 | |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 426 | /* SiS */ |
Jeff Garzik | 54bb3a9 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 427 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
| 428 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ |
| 429 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 430 | |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 431 | /* Generic, PCI class code for AHCI */ |
| 432 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 433 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 434 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | { } /* terminate list */ |
| 436 | }; |
| 437 | |
| 438 | |
| 439 | static struct pci_driver ahci_pci_driver = { |
| 440 | .name = DRV_NAME, |
| 441 | .id_table = ahci_pci_tbl, |
| 442 | .probe = ahci_init_one, |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 443 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 444 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 445 | .suspend = ahci_pci_device_suspend, |
| 446 | .resume = ahci_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 447 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | }; |
| 449 | |
| 450 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 451 | static inline int ahci_nr_ports(u32 cap) |
| 452 | { |
| 453 | return (cap & 0x1f) + 1; |
| 454 | } |
| 455 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 456 | static inline void __iomem *ahci_port_base(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 458 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
| 459 | |
| 460 | return mmio + 0x100 + (ap->port_no * 0x80); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | } |
| 462 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 463 | /** |
| 464 | * ahci_save_initial_config - Save and fixup initial config values |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 465 | * @pdev: target PCI device |
| 466 | * @pi: associated ATA port info |
| 467 | * @hpriv: host private area to store config values |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 468 | * |
| 469 | * Some registers containing configuration info might be setup by |
| 470 | * BIOS and might be cleared on reset. This function saves the |
| 471 | * initial values of those registers into @hpriv such that they |
| 472 | * can be restored after controller reset. |
| 473 | * |
| 474 | * If inconsistent, config values are fixed up by this function. |
| 475 | * |
| 476 | * LOCKING: |
| 477 | * None. |
| 478 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 479 | static void ahci_save_initial_config(struct pci_dev *pdev, |
| 480 | const struct ata_port_info *pi, |
| 481 | struct ahci_host_priv *hpriv) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 482 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 483 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 484 | u32 cap, port_map; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 485 | int i; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 486 | |
| 487 | /* Values prefixed with saved_ are written back to host after |
| 488 | * reset. Values without are used for driver operation. |
| 489 | */ |
| 490 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); |
| 491 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); |
| 492 | |
| 493 | /* fixup zero port_map */ |
| 494 | if (!port_map) { |
| 495 | port_map = (1 << ahci_nr_ports(hpriv->cap)) - 1; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 496 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 497 | "PORTS_IMPL is zero, forcing 0x%x\n", port_map); |
| 498 | |
| 499 | /* write the fixed up value to the PI register */ |
| 500 | hpriv->saved_port_map = port_map; |
| 501 | } |
| 502 | |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 503 | /* cross check port_map and cap.n_ports */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 504 | if (pi->flags & AHCI_FLAG_HONOR_PI) { |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 505 | u32 tmp_port_map = port_map; |
| 506 | int n_ports = ahci_nr_ports(cap); |
| 507 | |
| 508 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { |
| 509 | if (tmp_port_map & (1 << i)) { |
| 510 | n_ports--; |
| 511 | tmp_port_map &= ~(1 << i); |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | /* Whine if inconsistent. No need to update cap. |
| 516 | * port_map is used to determine number of ports. |
| 517 | */ |
| 518 | if (n_ports || tmp_port_map) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 519 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 520 | "nr_ports (%u) and implemented port map " |
| 521 | "(0x%x) don't match\n", |
| 522 | ahci_nr_ports(cap), port_map); |
| 523 | } else { |
| 524 | /* fabricate port_map from cap.nr_ports */ |
| 525 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
| 526 | } |
| 527 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 528 | /* record values to use during operation */ |
| 529 | hpriv->cap = cap; |
| 530 | hpriv->port_map = port_map; |
| 531 | } |
| 532 | |
| 533 | /** |
| 534 | * ahci_restore_initial_config - Restore initial config |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 535 | * @host: target ATA host |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 536 | * |
| 537 | * Restore initial config stored by ahci_save_initial_config(). |
| 538 | * |
| 539 | * LOCKING: |
| 540 | * None. |
| 541 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 542 | static void ahci_restore_initial_config(struct ata_host *host) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 543 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 544 | struct ahci_host_priv *hpriv = host->private_data; |
| 545 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 546 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 547 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
| 548 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); |
| 549 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
| 550 | } |
| 551 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 552 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
| 553 | { |
| 554 | unsigned int sc_reg; |
| 555 | |
| 556 | switch (sc_reg_in) { |
| 557 | case SCR_STATUS: sc_reg = 0; break; |
| 558 | case SCR_CONTROL: sc_reg = 1; break; |
| 559 | case SCR_ERROR: sc_reg = 2; break; |
| 560 | case SCR_ACTIVE: sc_reg = 3; break; |
| 561 | default: |
| 562 | return 0xffffffffU; |
| 563 | } |
| 564 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 565 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 566 | } |
| 567 | |
| 568 | |
| 569 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, |
| 570 | u32 val) |
| 571 | { |
| 572 | unsigned int sc_reg; |
| 573 | |
| 574 | switch (sc_reg_in) { |
| 575 | case SCR_STATUS: sc_reg = 0; break; |
| 576 | case SCR_CONTROL: sc_reg = 1; break; |
| 577 | case SCR_ERROR: sc_reg = 2; break; |
| 578 | case SCR_ACTIVE: sc_reg = 3; break; |
| 579 | default: |
| 580 | return; |
| 581 | } |
| 582 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 583 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 584 | } |
| 585 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 586 | static void ahci_start_engine(struct ata_port *ap) |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 587 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 588 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 589 | u32 tmp; |
| 590 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 591 | /* start DMA */ |
Tejun Heo | 9f59205 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 592 | tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 593 | tmp |= PORT_CMD_START; |
| 594 | writel(tmp, port_mmio + PORT_CMD); |
| 595 | readl(port_mmio + PORT_CMD); /* flush */ |
| 596 | } |
| 597 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 598 | static int ahci_stop_engine(struct ata_port *ap) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 599 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 600 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 601 | u32 tmp; |
| 602 | |
| 603 | tmp = readl(port_mmio + PORT_CMD); |
| 604 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 605 | /* check if the HBA is idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 606 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
| 607 | return 0; |
| 608 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 609 | /* setting HBA to idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 610 | tmp &= ~PORT_CMD_START; |
| 611 | writel(tmp, port_mmio + PORT_CMD); |
| 612 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 613 | /* wait for engine to stop. This could be as long as 500 msec */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 614 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 615 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 616 | if (tmp & PORT_CMD_LIST_ON) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 617 | return -EIO; |
| 618 | |
| 619 | return 0; |
| 620 | } |
| 621 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 622 | static void ahci_start_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 623 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 624 | void __iomem *port_mmio = ahci_port_base(ap); |
| 625 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 626 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 627 | u32 tmp; |
| 628 | |
| 629 | /* set FIS registers */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 630 | if (hpriv->cap & HOST_CAP_64) |
| 631 | writel((pp->cmd_slot_dma >> 16) >> 16, |
| 632 | port_mmio + PORT_LST_ADDR_HI); |
| 633 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 634 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 635 | if (hpriv->cap & HOST_CAP_64) |
| 636 | writel((pp->rx_fis_dma >> 16) >> 16, |
| 637 | port_mmio + PORT_FIS_ADDR_HI); |
| 638 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 639 | |
| 640 | /* enable FIS reception */ |
| 641 | tmp = readl(port_mmio + PORT_CMD); |
| 642 | tmp |= PORT_CMD_FIS_RX; |
| 643 | writel(tmp, port_mmio + PORT_CMD); |
| 644 | |
| 645 | /* flush */ |
| 646 | readl(port_mmio + PORT_CMD); |
| 647 | } |
| 648 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 649 | static int ahci_stop_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 650 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 651 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 652 | u32 tmp; |
| 653 | |
| 654 | /* disable FIS reception */ |
| 655 | tmp = readl(port_mmio + PORT_CMD); |
| 656 | tmp &= ~PORT_CMD_FIS_RX; |
| 657 | writel(tmp, port_mmio + PORT_CMD); |
| 658 | |
| 659 | /* wait for completion, spec says 500ms, give it 1000 */ |
| 660 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, |
| 661 | PORT_CMD_FIS_ON, 10, 1000); |
| 662 | if (tmp & PORT_CMD_FIS_ON) |
| 663 | return -EBUSY; |
| 664 | |
| 665 | return 0; |
| 666 | } |
| 667 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 668 | static void ahci_power_up(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 669 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 670 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 671 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 672 | u32 cmd; |
| 673 | |
| 674 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
| 675 | |
| 676 | /* spin up device */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 677 | if (hpriv->cap & HOST_CAP_SSS) { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 678 | cmd |= PORT_CMD_SPIN_UP; |
| 679 | writel(cmd, port_mmio + PORT_CMD); |
| 680 | } |
| 681 | |
| 682 | /* wake up link */ |
| 683 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); |
| 684 | } |
| 685 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 686 | #ifdef CONFIG_PM |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 687 | static void ahci_power_down(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 688 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 689 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 690 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 691 | u32 cmd, scontrol; |
| 692 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 693 | if (!(hpriv->cap & HOST_CAP_SSS)) |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 694 | return; |
| 695 | |
| 696 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
| 697 | scontrol = readl(port_mmio + PORT_SCR_CTL); |
| 698 | scontrol &= ~0xf; |
| 699 | writel(scontrol, port_mmio + PORT_SCR_CTL); |
| 700 | |
| 701 | /* then set PxCMD.SUD to 0 */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 702 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 703 | cmd &= ~PORT_CMD_SPIN_UP; |
| 704 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 705 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 706 | #endif |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 707 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 708 | static void ahci_init_port(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 709 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 710 | /* enable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 711 | ahci_start_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 712 | |
| 713 | /* enable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 714 | ahci_start_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 715 | } |
| 716 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 717 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 718 | { |
| 719 | int rc; |
| 720 | |
| 721 | /* disable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 722 | rc = ahci_stop_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 723 | if (rc) { |
| 724 | *emsg = "failed to stop engine"; |
| 725 | return rc; |
| 726 | } |
| 727 | |
| 728 | /* disable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 729 | rc = ahci_stop_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 730 | if (rc) { |
| 731 | *emsg = "failed stop FIS RX"; |
| 732 | return rc; |
| 733 | } |
| 734 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 735 | return 0; |
| 736 | } |
| 737 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 738 | static int ahci_reset_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 739 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 740 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 741 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 742 | u32 tmp; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 743 | |
| 744 | /* global controller reset */ |
| 745 | tmp = readl(mmio + HOST_CTL); |
| 746 | if ((tmp & HOST_RESET) == 0) { |
| 747 | writel(tmp | HOST_RESET, mmio + HOST_CTL); |
| 748 | readl(mmio + HOST_CTL); /* flush */ |
| 749 | } |
| 750 | |
| 751 | /* reset must complete within 1 second, or |
| 752 | * the hardware should be considered fried. |
| 753 | */ |
| 754 | ssleep(1); |
| 755 | |
| 756 | tmp = readl(mmio + HOST_CTL); |
| 757 | if (tmp & HOST_RESET) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 758 | dev_printk(KERN_ERR, host->dev, |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 759 | "controller reset failed (0x%x)\n", tmp); |
| 760 | return -EIO; |
| 761 | } |
| 762 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 763 | /* turn on AHCI mode */ |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 764 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
| 765 | (void) readl(mmio + HOST_CTL); /* flush */ |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 766 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 767 | /* some registers might be cleared on reset. restore initial values */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 768 | ahci_restore_initial_config(host); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 769 | |
| 770 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
| 771 | u16 tmp16; |
| 772 | |
| 773 | /* configure PCS */ |
| 774 | pci_read_config_word(pdev, 0x92, &tmp16); |
| 775 | tmp16 |= 0xf; |
| 776 | pci_write_config_word(pdev, 0x92, tmp16); |
| 777 | } |
| 778 | |
| 779 | return 0; |
| 780 | } |
| 781 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 782 | static void ahci_init_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 783 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 784 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 785 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 786 | int i, rc; |
| 787 | u32 tmp; |
| 788 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 789 | for (i = 0; i < host->n_ports; i++) { |
| 790 | struct ata_port *ap = host->ports[i]; |
| 791 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 792 | const char *emsg = NULL; |
| 793 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 794 | if (ata_port_is_dummy(ap)) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 795 | continue; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 796 | |
| 797 | /* make sure port is not active */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 798 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 799 | if (rc) |
| 800 | dev_printk(KERN_WARNING, &pdev->dev, |
| 801 | "%s (%d)\n", emsg, rc); |
| 802 | |
| 803 | /* clear SError */ |
| 804 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 805 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); |
| 806 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 807 | |
Tejun Heo | f4b5cc8 | 2006-08-07 11:39:04 +0900 | [diff] [blame] | 808 | /* clear port IRQ */ |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 809 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 810 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 811 | if (tmp) |
| 812 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 813 | |
| 814 | writel(1 << i, mmio + HOST_IRQ_STAT); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 815 | } |
| 816 | |
| 817 | tmp = readl(mmio + HOST_CTL); |
| 818 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 819 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 820 | tmp = readl(mmio + HOST_CTL); |
| 821 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 822 | } |
| 823 | |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 824 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 825 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 826 | void __iomem *port_mmio = ahci_port_base(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 827 | struct ata_taskfile tf; |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 828 | u32 tmp; |
| 829 | |
| 830 | tmp = readl(port_mmio + PORT_SIG); |
| 831 | tf.lbah = (tmp >> 24) & 0xff; |
| 832 | tf.lbam = (tmp >> 16) & 0xff; |
| 833 | tf.lbal = (tmp >> 8) & 0xff; |
| 834 | tf.nsect = (tmp) & 0xff; |
| 835 | |
| 836 | return ata_dev_classify(&tf); |
| 837 | } |
| 838 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 839 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 840 | u32 opts) |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 841 | { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 842 | dma_addr_t cmd_tbl_dma; |
| 843 | |
| 844 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; |
| 845 | |
| 846 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); |
| 847 | pp->cmd_slot[tag].status = 0; |
| 848 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); |
| 849 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 850 | } |
| 851 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 852 | static int ahci_clo(struct ata_port *ap) |
| 853 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 854 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 855 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 856 | u32 tmp; |
| 857 | |
| 858 | if (!(hpriv->cap & HOST_CAP_CLO)) |
| 859 | return -EOPNOTSUPP; |
| 860 | |
| 861 | tmp = readl(port_mmio + PORT_CMD); |
| 862 | tmp |= PORT_CMD_CLO; |
| 863 | writel(tmp, port_mmio + PORT_CMD); |
| 864 | |
| 865 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 866 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); |
| 867 | if (tmp & PORT_CMD_CLO) |
| 868 | return -EIO; |
| 869 | |
| 870 | return 0; |
| 871 | } |
| 872 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 873 | static int ahci_softreset(struct ata_port *ap, unsigned int *class, |
| 874 | unsigned long deadline) |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 875 | { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 876 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 877 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 878 | const u32 cmd_fis_len = 5; /* five dwords */ |
| 879 | const char *reason = NULL; |
| 880 | struct ata_taskfile tf; |
Tejun Heo | 75fe180 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 881 | u32 tmp; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 882 | u8 *fis; |
| 883 | int rc; |
| 884 | |
| 885 | DPRINTK("ENTER\n"); |
| 886 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 887 | if (ata_port_offline(ap)) { |
Tejun Heo | c2a6585 | 2006-04-03 01:58:06 +0900 | [diff] [blame] | 888 | DPRINTK("PHY reports no device\n"); |
| 889 | *class = ATA_DEV_NONE; |
| 890 | return 0; |
| 891 | } |
| 892 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 893 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 894 | rc = ahci_stop_engine(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 895 | if (rc) { |
| 896 | reason = "failed to stop engine"; |
| 897 | goto fail_restart; |
| 898 | } |
| 899 | |
| 900 | /* check BUSY/DRQ, perform Command List Override if necessary */ |
Tejun Heo | 1244a19 | 2006-11-01 17:19:18 +0900 | [diff] [blame] | 901 | if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) { |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 902 | rc = ahci_clo(ap); |
| 903 | |
| 904 | if (rc == -EOPNOTSUPP) { |
| 905 | reason = "port busy but CLO unavailable"; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 906 | goto fail_restart; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 907 | } else if (rc) { |
| 908 | reason = "port busy but CLO failed"; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 909 | goto fail_restart; |
| 910 | } |
| 911 | } |
| 912 | |
| 913 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 914 | ahci_start_engine(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 915 | |
Tejun Heo | 3373efd | 2006-05-15 20:57:53 +0900 | [diff] [blame] | 916 | ata_tf_init(ap->device, &tf); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 917 | fis = pp->cmd_tbl; |
| 918 | |
| 919 | /* issue the first D2H Register FIS */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 920 | ahci_fill_cmd_slot(pp, 0, |
| 921 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 922 | |
| 923 | tf.ctl |= ATA_SRST; |
| 924 | ata_tf_to_fis(&tf, fis, 0); |
| 925 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ |
| 926 | |
| 927 | writel(1, port_mmio + PORT_CMD_ISSUE); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 928 | |
Tejun Heo | 75fe180 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 929 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
| 930 | if (tmp & 0x1) { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 931 | rc = -EIO; |
| 932 | reason = "1st FIS failed"; |
| 933 | goto fail; |
| 934 | } |
| 935 | |
| 936 | /* spec says at least 5us, but be generous and sleep for 1ms */ |
| 937 | msleep(1); |
| 938 | |
| 939 | /* issue the second D2H Register FIS */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 940 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 941 | |
| 942 | tf.ctl &= ~ATA_SRST; |
| 943 | ata_tf_to_fis(&tf, fis, 0); |
| 944 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ |
| 945 | |
| 946 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 947 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 948 | |
| 949 | /* spec mandates ">= 2ms" before checking status. |
| 950 | * We wait 150ms, because that was the magic delay used for |
| 951 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time |
| 952 | * between when the ATA command register is written, and then |
| 953 | * status is checked. Because waiting for "a while" before |
| 954 | * checking status is fine, post SRST, we perform this magic |
| 955 | * delay here as well. |
| 956 | */ |
| 957 | msleep(150); |
| 958 | |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 959 | rc = ata_wait_ready(ap, deadline); |
| 960 | /* link occupied, -ENODEV too is an error */ |
| 961 | if (rc) { |
| 962 | reason = "device not ready"; |
| 963 | goto fail; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 964 | } |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 965 | *class = ahci_dev_classify(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 966 | |
| 967 | DPRINTK("EXIT, class=%u\n", *class); |
| 968 | return 0; |
| 969 | |
| 970 | fail_restart: |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 971 | ahci_start_engine(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 972 | fail: |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 973 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 974 | return rc; |
| 975 | } |
| 976 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 977 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class, |
| 978 | unsigned long deadline) |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 979 | { |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 980 | struct ahci_port_priv *pp = ap->private_data; |
| 981 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 982 | struct ata_taskfile tf; |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 983 | int rc; |
| 984 | |
| 985 | DPRINTK("ENTER\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 987 | ahci_stop_engine(ap); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 988 | |
| 989 | /* clear D2H reception area to properly wait for D2H FIS */ |
| 990 | ata_tf_init(ap->device, &tf); |
Tejun Heo | dfd7a3d | 2007-01-26 15:37:20 +0900 | [diff] [blame] | 991 | tf.command = 0x80; |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 992 | ata_tf_to_fis(&tf, d2h_fis, 0); |
| 993 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 994 | rc = sata_std_hardreset(ap, class, deadline); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 995 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 996 | ahci_start_engine(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 997 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 998 | if (rc == 0 && ata_port_online(ap)) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 999 | *class = ahci_dev_classify(ap); |
| 1000 | if (*class == ATA_DEV_UNKNOWN) |
| 1001 | *class = ATA_DEV_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1002 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1003 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1004 | return rc; |
| 1005 | } |
| 1006 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1007 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class, |
| 1008 | unsigned long deadline) |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1009 | { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1010 | int rc; |
| 1011 | |
| 1012 | DPRINTK("ENTER\n"); |
| 1013 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1014 | ahci_stop_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1015 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1016 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context), |
| 1017 | deadline); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1018 | |
| 1019 | /* vt8251 needs SError cleared for the port to operate */ |
| 1020 | ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); |
| 1021 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1022 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1023 | |
| 1024 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1025 | |
| 1026 | /* vt8251 doesn't clear BSY on signature FIS reception, |
| 1027 | * request follow-up softreset. |
| 1028 | */ |
| 1029 | return rc ?: -EAGAIN; |
| 1030 | } |
| 1031 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1032 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
| 1033 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1034 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1035 | u32 new_tmp, tmp; |
| 1036 | |
| 1037 | ata_std_postreset(ap, class); |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1038 | |
| 1039 | /* Make sure port's ATAPI bit is set appropriately */ |
| 1040 | new_tmp = tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1041 | if (*class == ATA_DEV_ATAPI) |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1042 | new_tmp |= PORT_CMD_ATAPI; |
| 1043 | else |
| 1044 | new_tmp &= ~PORT_CMD_ATAPI; |
| 1045 | if (new_tmp != tmp) { |
| 1046 | writel(new_tmp, port_mmio + PORT_CMD); |
| 1047 | readl(port_mmio + PORT_CMD); /* flush */ |
| 1048 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1049 | } |
| 1050 | |
| 1051 | static u8 ahci_check_status(struct ata_port *ap) |
| 1052 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1053 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1054 | |
| 1055 | return readl(mmio + PORT_TFDATA) & 0xFF; |
| 1056 | } |
| 1057 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1058 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| 1059 | { |
| 1060 | struct ahci_port_priv *pp = ap->private_data; |
| 1061 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1062 | |
| 1063 | ata_tf_from_fis(d2h_fis, tf); |
| 1064 | } |
| 1065 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1066 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1067 | { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1068 | struct scatterlist *sg; |
| 1069 | struct ahci_sg *ahci_sg; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1070 | unsigned int n_sg = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1071 | |
| 1072 | VPRINTK("ENTER\n"); |
| 1073 | |
| 1074 | /* |
| 1075 | * Next, the S/G list. |
| 1076 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1077 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1078 | ata_for_each_sg(sg, qc) { |
| 1079 | dma_addr_t addr = sg_dma_address(sg); |
| 1080 | u32 sg_len = sg_dma_len(sg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1081 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1082 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 1083 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 1084 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1085 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1086 | ahci_sg++; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1087 | n_sg++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1088 | } |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1089 | |
| 1090 | return n_sg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1091 | } |
| 1092 | |
| 1093 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
| 1094 | { |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1095 | struct ata_port *ap = qc->ap; |
| 1096 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1097 | int is_atapi = is_atapi_taskfile(&qc->tf); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1098 | void *cmd_tbl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1099 | u32 opts; |
| 1100 | const u32 cmd_fis_len = 5; /* five dwords */ |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1101 | unsigned int n_elem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1102 | |
| 1103 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1104 | * Fill in command table information. First, the header, |
| 1105 | * a SATA Register - Host to Device command FIS. |
| 1106 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1107 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
| 1108 | |
| 1109 | ata_tf_to_fis(&qc->tf, cmd_tbl, 0); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1110 | if (is_atapi) { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1111 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
| 1112 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1113 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1114 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1115 | n_elem = 0; |
| 1116 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1117 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1118 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1119 | /* |
| 1120 | * Fill in command slot information. |
| 1121 | */ |
| 1122 | opts = cmd_fis_len | n_elem << 16; |
| 1123 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
| 1124 | opts |= AHCI_CMD_WRITE; |
| 1125 | if (is_atapi) |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 1126 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1127 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1128 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1129 | } |
| 1130 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1131 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1132 | { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1133 | struct ahci_port_priv *pp = ap->private_data; |
| 1134 | struct ata_eh_info *ehi = &ap->eh_info; |
| 1135 | unsigned int err_mask = 0, action = 0; |
| 1136 | struct ata_queued_cmd *qc; |
| 1137 | u32 serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1138 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1139 | ata_ehi_clear_desc(ehi); |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 1140 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1141 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
| 1142 | serror = ahci_scr_read(ap, SCR_ERROR); |
| 1143 | ahci_scr_write(ap, SCR_ERROR, serror); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1144 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1145 | /* analyze @irq_stat */ |
| 1146 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1147 | |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 1148 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
| 1149 | if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR) |
| 1150 | irq_stat &= ~PORT_IRQ_IF_ERR; |
| 1151 | |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 1152 | if (irq_stat & PORT_IRQ_TF_ERR) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1153 | err_mask |= AC_ERR_DEV; |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 1154 | if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL) |
| 1155 | serror &= ~SERR_INTERNAL; |
| 1156 | } |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1157 | |
| 1158 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { |
| 1159 | err_mask |= AC_ERR_HOST_BUS; |
| 1160 | action |= ATA_EH_SOFTRESET; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1161 | } |
| 1162 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1163 | if (irq_stat & PORT_IRQ_IF_ERR) { |
| 1164 | err_mask |= AC_ERR_ATA_BUS; |
| 1165 | action |= ATA_EH_SOFTRESET; |
| 1166 | ata_ehi_push_desc(ehi, ", interface fatal error"); |
| 1167 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1168 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1169 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1170 | ata_ehi_hotplugged(ehi); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1171 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
| 1172 | "connection status changed" : "PHY RDY changed"); |
| 1173 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1174 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1175 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
| 1176 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1177 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1178 | err_mask |= AC_ERR_HSM; |
| 1179 | action |= ATA_EH_SOFTRESET; |
| 1180 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", |
| 1181 | unk[0], unk[1], unk[2], unk[3]); |
| 1182 | } |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 1183 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1184 | /* okay, let's hand over to EH */ |
| 1185 | ehi->serror |= serror; |
| 1186 | ehi->action |= action; |
| 1187 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1188 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1189 | if (qc) |
| 1190 | qc->err_mask |= err_mask; |
| 1191 | else |
| 1192 | ehi->err_mask |= err_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1193 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1194 | if (irq_stat & PORT_IRQ_FREEZE) |
| 1195 | ata_port_freeze(ap); |
| 1196 | else |
| 1197 | ata_port_abort(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1198 | } |
| 1199 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1200 | static void ahci_host_intr(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1201 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1202 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1203 | struct ata_eh_info *ehi = &ap->eh_info; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1204 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1205 | u32 status, qc_active; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1206 | int rc, known_irq = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1207 | |
| 1208 | status = readl(port_mmio + PORT_IRQ_STAT); |
| 1209 | writel(status, port_mmio + PORT_IRQ_STAT); |
| 1210 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1211 | if (unlikely(status & PORT_IRQ_ERROR)) { |
| 1212 | ahci_error_intr(ap, status); |
| 1213 | return; |
| 1214 | } |
| 1215 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1216 | if (ap->sactive) |
| 1217 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
| 1218 | else |
| 1219 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); |
| 1220 | |
| 1221 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); |
| 1222 | if (rc > 0) |
| 1223 | return; |
| 1224 | if (rc < 0) { |
| 1225 | ehi->err_mask |= AC_ERR_HSM; |
| 1226 | ehi->action |= ATA_EH_SOFTRESET; |
| 1227 | ata_port_freeze(ap); |
| 1228 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1229 | } |
| 1230 | |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 1231 | /* hmmm... a spurious interupt */ |
| 1232 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1233 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
| 1234 | * implementation for non-NCQ commands. |
| 1235 | */ |
| 1236 | if (!ap->sactive) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1237 | return; |
| 1238 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1239 | if (status & PORT_IRQ_D2H_REG_FIS) { |
| 1240 | if (!pp->ncq_saw_d2h) |
| 1241 | ata_port_printk(ap, KERN_INFO, |
| 1242 | "D2H reg with I during NCQ, " |
| 1243 | "this message won't be printed again\n"); |
| 1244 | pp->ncq_saw_d2h = 1; |
| 1245 | known_irq = 1; |
| 1246 | } |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 1247 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1248 | if (status & PORT_IRQ_DMAS_FIS) { |
| 1249 | if (!pp->ncq_saw_dmas) |
| 1250 | ata_port_printk(ap, KERN_INFO, |
| 1251 | "DMAS FIS during NCQ, " |
| 1252 | "this message won't be printed again\n"); |
| 1253 | pp->ncq_saw_dmas = 1; |
| 1254 | known_irq = 1; |
| 1255 | } |
| 1256 | |
Tejun Heo | a2bbd0c | 2007-02-21 16:34:25 +0900 | [diff] [blame] | 1257 | if (status & PORT_IRQ_SDB_FIS) { |
Al Viro | 04d4f7a | 2007-02-09 16:39:30 +0000 | [diff] [blame] | 1258 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1259 | |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 1260 | if (le32_to_cpu(f[1])) { |
| 1261 | /* SDB FIS containing spurious completions |
| 1262 | * might be dangerous, whine and fail commands |
| 1263 | * with HSM violation. EH will turn off NCQ |
| 1264 | * after several such failures. |
| 1265 | */ |
| 1266 | ata_ehi_push_desc(ehi, |
| 1267 | "spurious completions during NCQ " |
| 1268 | "issue=0x%x SAct=0x%x FIS=%08x:%08x", |
| 1269 | readl(port_mmio + PORT_CMD_ISSUE), |
| 1270 | readl(port_mmio + PORT_SCR_ACT), |
| 1271 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); |
| 1272 | ehi->err_mask |= AC_ERR_HSM; |
| 1273 | ehi->action |= ATA_EH_SOFTRESET; |
| 1274 | ata_port_freeze(ap); |
| 1275 | } else { |
| 1276 | if (!pp->ncq_saw_sdb) |
| 1277 | ata_port_printk(ap, KERN_INFO, |
| 1278 | "spurious SDB FIS %08x:%08x during NCQ, " |
| 1279 | "this message won't be printed again\n", |
| 1280 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); |
| 1281 | pp->ncq_saw_sdb = 1; |
| 1282 | } |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1283 | known_irq = 1; |
| 1284 | } |
| 1285 | |
| 1286 | if (!known_irq) |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1287 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1288 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1289 | status, ap->active_tag, ap->sactive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1290 | } |
| 1291 | |
| 1292 | static void ahci_irq_clear(struct ata_port *ap) |
| 1293 | { |
| 1294 | /* TODO */ |
| 1295 | } |
| 1296 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1297 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1298 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1299 | struct ata_host *host = dev_instance; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1300 | struct ahci_host_priv *hpriv; |
| 1301 | unsigned int i, handled = 0; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1302 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1303 | u32 irq_stat, irq_ack = 0; |
| 1304 | |
| 1305 | VPRINTK("ENTER\n"); |
| 1306 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1307 | hpriv = host->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1308 | mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1309 | |
| 1310 | /* sigh. 0xffffffff is a valid return from h/w */ |
| 1311 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
| 1312 | irq_stat &= hpriv->port_map; |
| 1313 | if (!irq_stat) |
| 1314 | return IRQ_NONE; |
| 1315 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1316 | spin_lock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1317 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1318 | for (i = 0; i < host->n_ports; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1319 | struct ata_port *ap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1320 | |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1321 | if (!(irq_stat & (1 << i))) |
| 1322 | continue; |
| 1323 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1324 | ap = host->ports[i]; |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1325 | if (ap) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1326 | ahci_host_intr(ap); |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1327 | VPRINTK("port %u\n", i); |
| 1328 | } else { |
| 1329 | VPRINTK("port %u (no irq)\n", i); |
Tejun Heo | 6971ed1 | 2006-03-11 12:47:54 +0900 | [diff] [blame] | 1330 | if (ata_ratelimit()) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1331 | dev_printk(KERN_WARNING, host->dev, |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1332 | "interrupt on disabled port %u\n", i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1333 | } |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1334 | |
| 1335 | irq_ack |= (1 << i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1336 | } |
| 1337 | |
| 1338 | if (irq_ack) { |
| 1339 | writel(irq_ack, mmio + HOST_IRQ_STAT); |
| 1340 | handled = 1; |
| 1341 | } |
| 1342 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1343 | spin_unlock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1344 | |
| 1345 | VPRINTK("EXIT\n"); |
| 1346 | |
| 1347 | return IRQ_RETVAL(handled); |
| 1348 | } |
| 1349 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 1350 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1351 | { |
| 1352 | struct ata_port *ap = qc->ap; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1353 | void __iomem *port_mmio = ahci_port_base(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1354 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1355 | if (qc->tf.protocol == ATA_PROT_NCQ) |
| 1356 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
| 1357 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1358 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1359 | |
| 1360 | return 0; |
| 1361 | } |
| 1362 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1363 | static void ahci_freeze(struct ata_port *ap) |
| 1364 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1365 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1366 | |
| 1367 | /* turn IRQ off */ |
| 1368 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 1369 | } |
| 1370 | |
| 1371 | static void ahci_thaw(struct ata_port *ap) |
| 1372 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1373 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1374 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1375 | u32 tmp; |
| 1376 | |
| 1377 | /* clear IRQ */ |
| 1378 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1379 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
Tejun Heo | a718728 | 2007-01-27 11:04:26 +0900 | [diff] [blame] | 1380 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1381 | |
| 1382 | /* turn IRQ back on */ |
| 1383 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); |
| 1384 | } |
| 1385 | |
| 1386 | static void ahci_error_handler(struct ata_port *ap) |
| 1387 | { |
Tejun Heo | b51e9e5 | 2006-06-29 01:29:30 +0900 | [diff] [blame] | 1388 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1389 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1390 | ahci_stop_engine(ap); |
| 1391 | ahci_start_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1392 | } |
| 1393 | |
| 1394 | /* perform recovery */ |
Tejun Heo | 4aeb0e3 | 2006-11-01 17:58:33 +0900 | [diff] [blame] | 1395 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset, |
Tejun Heo | f5914a4 | 2006-05-31 18:27:48 +0900 | [diff] [blame] | 1396 | ahci_postreset); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1397 | } |
| 1398 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1399 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
| 1400 | { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1401 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
| 1402 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1403 | ahci_stop_engine(ap); |
| 1404 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1405 | } |
| 1406 | |
| 1407 | /* perform recovery */ |
| 1408 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, |
| 1409 | ahci_postreset); |
| 1410 | } |
| 1411 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1412 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
| 1413 | { |
| 1414 | struct ata_port *ap = qc->ap; |
| 1415 | |
Tejun Heo | a51d644 | 2007-03-20 15:24:11 +0900 | [diff] [blame] | 1416 | if (qc->flags & ATA_QCFLAG_FAILED) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1417 | /* make DMA engine forget about the failed command */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1418 | ahci_stop_engine(ap); |
| 1419 | ahci_start_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1420 | } |
| 1421 | } |
| 1422 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1423 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1424 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
| 1425 | { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1426 | const char *emsg = NULL; |
| 1427 | int rc; |
| 1428 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1429 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1430 | if (rc == 0) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1431 | ahci_power_down(ap); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1432 | else { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1433 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1434 | ahci_init_port(ap); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1435 | } |
| 1436 | |
| 1437 | return rc; |
| 1438 | } |
| 1439 | |
| 1440 | static int ahci_port_resume(struct ata_port *ap) |
| 1441 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1442 | ahci_power_up(ap); |
| 1443 | ahci_init_port(ap); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1444 | |
| 1445 | return 0; |
| 1446 | } |
| 1447 | |
| 1448 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
| 1449 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1450 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1451 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1452 | u32 ctl; |
| 1453 | |
| 1454 | if (mesg.event == PM_EVENT_SUSPEND) { |
| 1455 | /* AHCI spec rev1.1 section 8.3.3: |
| 1456 | * Software must disable interrupts prior to requesting a |
| 1457 | * transition of the HBA to D3 state. |
| 1458 | */ |
| 1459 | ctl = readl(mmio + HOST_CTL); |
| 1460 | ctl &= ~HOST_IRQ_EN; |
| 1461 | writel(ctl, mmio + HOST_CTL); |
| 1462 | readl(mmio + HOST_CTL); /* flush */ |
| 1463 | } |
| 1464 | |
| 1465 | return ata_pci_device_suspend(pdev, mesg); |
| 1466 | } |
| 1467 | |
| 1468 | static int ahci_pci_device_resume(struct pci_dev *pdev) |
| 1469 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1470 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1471 | int rc; |
| 1472 | |
Tejun Heo | 553c4aa | 2006-12-26 19:39:50 +0900 | [diff] [blame] | 1473 | rc = ata_pci_device_do_resume(pdev); |
| 1474 | if (rc) |
| 1475 | return rc; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1476 | |
| 1477 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1478 | rc = ahci_reset_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1479 | if (rc) |
| 1480 | return rc; |
| 1481 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1482 | ahci_init_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1483 | } |
| 1484 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1485 | ata_host_resume(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1486 | |
| 1487 | return 0; |
| 1488 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1489 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1490 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1491 | static int ahci_port_start(struct ata_port *ap) |
| 1492 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1493 | struct device *dev = ap->host->dev; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1494 | struct ahci_port_priv *pp; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1495 | void *mem; |
| 1496 | dma_addr_t mem_dma; |
| 1497 | int rc; |
| 1498 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1499 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1500 | if (!pp) |
| 1501 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1502 | |
| 1503 | rc = ata_pad_alloc(ap, dev); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1504 | if (rc) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1505 | return rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1506 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1507 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
| 1508 | GFP_KERNEL); |
| 1509 | if (!mem) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1510 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1511 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 1512 | |
| 1513 | /* |
| 1514 | * First item in chunk of DMA memory: 32-slot command table, |
| 1515 | * 32 bytes each in size |
| 1516 | */ |
| 1517 | pp->cmd_slot = mem; |
| 1518 | pp->cmd_slot_dma = mem_dma; |
| 1519 | |
| 1520 | mem += AHCI_CMD_SLOT_SZ; |
| 1521 | mem_dma += AHCI_CMD_SLOT_SZ; |
| 1522 | |
| 1523 | /* |
| 1524 | * Second item: Received-FIS area |
| 1525 | */ |
| 1526 | pp->rx_fis = mem; |
| 1527 | pp->rx_fis_dma = mem_dma; |
| 1528 | |
| 1529 | mem += AHCI_RX_FIS_SZ; |
| 1530 | mem_dma += AHCI_RX_FIS_SZ; |
| 1531 | |
| 1532 | /* |
| 1533 | * Third item: data area for storing a single command |
| 1534 | * and its scatter-gather table |
| 1535 | */ |
| 1536 | pp->cmd_tbl = mem; |
| 1537 | pp->cmd_tbl_dma = mem_dma; |
| 1538 | |
| 1539 | ap->private_data = pp; |
| 1540 | |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1541 | /* power up port */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1542 | ahci_power_up(ap); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1543 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1544 | /* initialize port */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1545 | ahci_init_port(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1546 | |
| 1547 | return 0; |
| 1548 | } |
| 1549 | |
| 1550 | static void ahci_port_stop(struct ata_port *ap) |
| 1551 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1552 | const char *emsg = NULL; |
| 1553 | int rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1554 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1555 | /* de-initialize port */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1556 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1557 | if (rc) |
| 1558 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1559 | } |
| 1560 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1561 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1562 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1563 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1564 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1565 | if (using_dac && |
| 1566 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 1567 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 1568 | if (rc) { |
| 1569 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1570 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1571 | dev_printk(KERN_ERR, &pdev->dev, |
| 1572 | "64-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1573 | return rc; |
| 1574 | } |
| 1575 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1576 | } else { |
| 1577 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 1578 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1579 | dev_printk(KERN_ERR, &pdev->dev, |
| 1580 | "32-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1581 | return rc; |
| 1582 | } |
| 1583 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1584 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1585 | dev_printk(KERN_ERR, &pdev->dev, |
| 1586 | "32-bit consistent DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1587 | return rc; |
| 1588 | } |
| 1589 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1590 | return 0; |
| 1591 | } |
| 1592 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1593 | static void ahci_print_info(struct ata_host *host) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1594 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1595 | struct ahci_host_priv *hpriv = host->private_data; |
| 1596 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 1597 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1598 | u32 vers, cap, impl, speed; |
| 1599 | const char *speed_s; |
| 1600 | u16 cc; |
| 1601 | const char *scc_s; |
| 1602 | |
| 1603 | vers = readl(mmio + HOST_VERSION); |
| 1604 | cap = hpriv->cap; |
| 1605 | impl = hpriv->port_map; |
| 1606 | |
| 1607 | speed = (cap >> 20) & 0xf; |
| 1608 | if (speed == 1) |
| 1609 | speed_s = "1.5"; |
| 1610 | else if (speed == 2) |
| 1611 | speed_s = "3"; |
| 1612 | else |
| 1613 | speed_s = "?"; |
| 1614 | |
| 1615 | pci_read_config_word(pdev, 0x0a, &cc); |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1616 | if (cc == PCI_CLASS_STORAGE_IDE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1617 | scc_s = "IDE"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1618 | else if (cc == PCI_CLASS_STORAGE_SATA) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1619 | scc_s = "SATA"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1620 | else if (cc == PCI_CLASS_STORAGE_RAID) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1621 | scc_s = "RAID"; |
| 1622 | else |
| 1623 | scc_s = "unknown"; |
| 1624 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1625 | dev_printk(KERN_INFO, &pdev->dev, |
| 1626 | "AHCI %02x%02x.%02x%02x " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1627 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
| 1628 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1629 | |
| 1630 | (vers >> 24) & 0xff, |
| 1631 | (vers >> 16) & 0xff, |
| 1632 | (vers >> 8) & 0xff, |
| 1633 | vers & 0xff, |
| 1634 | |
| 1635 | ((cap >> 8) & 0x1f) + 1, |
| 1636 | (cap & 0x1f) + 1, |
| 1637 | speed_s, |
| 1638 | impl, |
| 1639 | scc_s); |
| 1640 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1641 | dev_printk(KERN_INFO, &pdev->dev, |
| 1642 | "flags: " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1643 | "%s%s%s%s%s%s" |
| 1644 | "%s%s%s%s%s%s%s\n" |
| 1645 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1646 | |
| 1647 | cap & (1 << 31) ? "64bit " : "", |
| 1648 | cap & (1 << 30) ? "ncq " : "", |
| 1649 | cap & (1 << 28) ? "ilck " : "", |
| 1650 | cap & (1 << 27) ? "stag " : "", |
| 1651 | cap & (1 << 26) ? "pm " : "", |
| 1652 | cap & (1 << 25) ? "led " : "", |
| 1653 | |
| 1654 | cap & (1 << 24) ? "clo " : "", |
| 1655 | cap & (1 << 19) ? "nz " : "", |
| 1656 | cap & (1 << 18) ? "only " : "", |
| 1657 | cap & (1 << 17) ? "pmp " : "", |
| 1658 | cap & (1 << 15) ? "pio " : "", |
| 1659 | cap & (1 << 14) ? "slum " : "", |
| 1660 | cap & (1 << 13) ? "part " : "" |
| 1661 | ); |
| 1662 | } |
| 1663 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1664 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1665 | { |
| 1666 | static int printed_version; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1667 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
| 1668 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1669 | struct device *dev = &pdev->dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1670 | struct ahci_host_priv *hpriv; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1671 | struct ata_host *host; |
| 1672 | int i, rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1673 | |
| 1674 | VPRINTK("ENTER\n"); |
| 1675 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1676 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
| 1677 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1678 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1679 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1680 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1681 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1682 | rc = pcim_enable_device(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1683 | if (rc) |
| 1684 | return rc; |
| 1685 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1686 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
| 1687 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1688 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1689 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1690 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1691 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1692 | if (pci_enable_msi(pdev)) |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1693 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1694 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1695 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
| 1696 | if (!hpriv) |
| 1697 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1698 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1699 | /* save initial config */ |
| 1700 | ahci_save_initial_config(pdev, &pi, hpriv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1701 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1702 | /* prepare host */ |
| 1703 | if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ)) |
| 1704 | pi.flags |= ATA_FLAG_NCQ; |
| 1705 | |
| 1706 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); |
| 1707 | if (!host) |
| 1708 | return -ENOMEM; |
| 1709 | host->iomap = pcim_iomap_table(pdev); |
| 1710 | host->private_data = hpriv; |
| 1711 | |
| 1712 | for (i = 0; i < host->n_ports; i++) { |
| 1713 | if (hpriv->port_map & (1 << i)) { |
| 1714 | struct ata_port *ap = host->ports[i]; |
| 1715 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1716 | |
| 1717 | ap->ioaddr.cmd_addr = port_mmio; |
| 1718 | ap->ioaddr.scr_addr = port_mmio + PORT_SCR; |
| 1719 | } else |
| 1720 | host->ports[i]->ops = &ata_dummy_port_ops; |
| 1721 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1722 | |
| 1723 | /* initialize adapter */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1724 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1725 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1726 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1727 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1728 | rc = ahci_reset_controller(host); |
| 1729 | if (rc) |
| 1730 | return rc; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1731 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1732 | ahci_init_controller(host); |
| 1733 | ahci_print_info(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1734 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1735 | pci_set_master(pdev); |
| 1736 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, |
| 1737 | &ahci_sht); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1738 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1739 | |
| 1740 | static int __init ahci_init(void) |
| 1741 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 1742 | return pci_register_driver(&ahci_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1743 | } |
| 1744 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1745 | static void __exit ahci_exit(void) |
| 1746 | { |
| 1747 | pci_unregister_driver(&ahci_pci_driver); |
| 1748 | } |
| 1749 | |
| 1750 | |
| 1751 | MODULE_AUTHOR("Jeff Garzik"); |
| 1752 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); |
| 1753 | MODULE_LICENSE("GPL"); |
| 1754 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); |
Jeff Garzik | 6885433 | 2005-08-23 02:53:51 -0400 | [diff] [blame] | 1755 | MODULE_VERSION(DRV_VERSION); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1756 | |
| 1757 | module_init(ahci_init); |
| 1758 | module_exit(ahci_exit); |